| ... | ... | @@ -2730,15 +2730,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 2730 | 2730 | // movabs does not support indirect register addressing |
| 2731 | 2731 | // so we need an extra register and an extra mov. |
| 2732 | 2732 | const tmp_reg = try self.copyToTmpRegister(value_ty, value); |
| 2733 | | _ = try self.addInst(.{ |
| 2734 | | .tag = .mov, |
| 2735 | | .ops = Mir.Inst.Ops.encode(.{ |
| 2736 | | .reg1 = reg.to64(), |
| 2737 | | .reg2 = tmp_reg.to64(), |
| 2738 | | .flags = 0b10, |
| 2739 | | }), |
| 2740 | | .data = .{ .imm = 0 }, |
| 2741 | | }); |
| 2733 | return self.store(ptr, .{ .register = tmp_reg }, ptr_ty, value_ty); |
| 2742 | 2734 | }, |
| 2743 | 2735 | else => { |
| 2744 | 2736 | return self.fail("TODO implement set pointee with immediate of ABI size {d}", .{abi_size}); |
| ... | ... | @@ -2835,6 +2827,8 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 2835 | 2827 | .data = .{ .imm = 0 }, |
| 2836 | 2828 | }); |
| 2837 | 2829 | |
| 2830 | const new_ptr = MCValue{ .register = addr_reg.to64() }; |
| 2831 | |
| 2838 | 2832 | switch (value) { |
| 2839 | 2833 | .immediate => |imm| { |
| 2840 | 2834 | if (abi_size > 8) { |
| ... | ... | @@ -2873,16 +2867,8 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 2873 | 2867 | .data = .{ .payload = payload }, |
| 2874 | 2868 | }); |
| 2875 | 2869 | }, |
| 2876 | | .register => |reg| { |
| 2877 | | _ = try self.addInst(.{ |
| 2878 | | .tag = .mov, |
| 2879 | | .ops = Mir.Inst.Ops.encode(.{ |
| 2880 | | .reg1 = addr_reg.to64(), |
| 2881 | | .reg2 = reg, |
| 2882 | | .flags = 0b10, |
| 2883 | | }), |
| 2884 | | .data = .{ .imm = 0 }, |
| 2885 | | }); |
| 2870 | .register => { |
| 2871 | return self.store(new_ptr, value, ptr_ty, value_ty); |
| 2886 | 2872 | }, |
| 2887 | 2873 | .got_load, |
| 2888 | 2874 | .direct_load, |
| ... | ... | @@ -2904,37 +2890,18 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type |
| 2904 | 2890 | }), |
| 2905 | 2891 | .data = .{ .imm = 0 }, |
| 2906 | 2892 | }); |
| 2907 | | _ = try self.addInst(.{ |
| 2908 | | .tag = .mov, |
| 2909 | | .ops = Mir.Inst.Ops.encode(.{ |
| 2910 | | .reg1 = addr_reg.to64(), |
| 2911 | | .reg2 = tmp_reg, |
| 2912 | | .flags = 0b10, |
| 2913 | | }), |
| 2914 | | .data = .{ .imm = 0 }, |
| 2915 | | }); |
| 2916 | | return; |
| 2893 | return self.store(new_ptr, .{ .register = tmp_reg }, ptr_ty, value_ty); |
| 2917 | 2894 | } |
| 2918 | 2895 | |
| 2919 | | try self.genInlineMemcpy(.{ .register = addr_reg.to64() }, value, .{ .immediate = abi_size }, .{}); |
| 2896 | try self.genInlineMemcpy(new_ptr, value, .{ .immediate = abi_size }, .{}); |
| 2920 | 2897 | }, |
| 2921 | 2898 | .stack_offset => { |
| 2922 | 2899 | if (abi_size <= 8) { |
| 2923 | | // TODO this should really be a recursive call |
| 2924 | 2900 | const tmp_reg = try self.copyToTmpRegister(value_ty, value); |
| 2925 | | _ = try self.addInst(.{ |
| 2926 | | .tag = .mov, |
| 2927 | | .ops = Mir.Inst.Ops.encode(.{ |
| 2928 | | .reg1 = addr_reg.to64(), |
| 2929 | | .reg2 = tmp_reg, |
| 2930 | | .flags = 0b10, |
| 2931 | | }), |
| 2932 | | .data = .{ .imm = 0 }, |
| 2933 | | }); |
| 2934 | | return; |
| 2901 | return self.store(new_ptr, .{ .register = tmp_reg }, ptr_ty, value_ty); |
| 2935 | 2902 | } |
| 2936 | 2903 | |
| 2937 | | try self.genInlineMemcpy(.{ .register = addr_reg.to64() }, value, .{ .immediate = abi_size }, .{}); |
| 2904 | try self.genInlineMemcpy(new_ptr, value, .{ .immediate = abi_size }, .{}); |
| 2938 | 2905 | }, |
| 2939 | 2906 | else => return self.fail("TODO implement storing {} to MCValue.memory", .{value}), |
| 2940 | 2907 | } |
Jakub Konka <kubkon@jakubkonka.com> 2022-06-07 18:30:59+02:00