diff --git a/lib/std/zig/system/x86.zig b/lib/std/zig/system/x86.zig index dd3abde589992dbddbafda4ee8c3a2676dd14e7c..e4fa035747ce7195a1401722d1a9aa366dfd9698 100644 --- a/lib/std/zig/system/x86.zig +++ b/lib/std/zig/system/x86.zig @@ -72,14 +72,12 @@ pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, os: Target.Os, query: T } // Now we detect the model. - switch (vendor) { - 0x756e6547 => { - detectIntelProcessor(&cpu, family, model, brand_id); - }, - 0x68747541 => { - if (detectAMDProcessor(cpu, family, model)) |m| cpu.model = m; - }, - else => {}, + if (switch (vendor) { + 0x756e6547 => detectIntelProcessor(&cpu, family, model, brand_id), + 0x68747541 => detectAmdProcessor(&cpu, family, model), + else => null, + }) |m| { + cpu.model = m; } } @@ -93,239 +91,85 @@ pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, os: Target.Os, query: T return cpu; } -fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32) void { - if (brand_id != 0) { - return; - } - switch (family) { - 3 => { - cpu.model = &Target.x86.cpu.i386; - return; - }, - 4 => { - cpu.model = &Target.x86.cpu.i486; - return; - }, - 5 => { - if (cpu.has(.x86, .mmx)) { - cpu.model = &Target.x86.cpu.pentium_mmx; - return; - } - cpu.model = &Target.x86.cpu.pentium; - return; - }, - 6 => { - switch (model) { - 0x01 => { - cpu.model = &Target.x86.cpu.pentiumpro; - return; - }, - 0x03, 0x05, 0x06 => { - cpu.model = &Target.x86.cpu.pentium2; - return; - }, - 0x07, 0x08, 0x0a, 0x0b => { - cpu.model = &Target.x86.cpu.pentium3; - return; - }, - 0x09, 0x0d, 0x15 => { - cpu.model = &Target.x86.cpu.pentium_m; - return; - }, - 0x0e => { - cpu.model = &Target.x86.cpu.yonah; - return; - }, - 0x0f, 0x16 => { - cpu.model = &Target.x86.cpu.core2; - return; - }, - 0x17, 0x1d => { - cpu.model = &Target.x86.cpu.penryn; - return; - }, - 0x1a, 0x1e, 0x1f, 0x2e => { - cpu.model = &Target.x86.cpu.nehalem; - return; - }, - 0x25, 0x2c, 0x2f => { - cpu.model = &Target.x86.cpu.westmere; - return; - }, - 0x2a, 0x2d => { - cpu.model = &Target.x86.cpu.sandybridge; - return; - }, - 0x3a, 0x3e => { - cpu.model = &Target.x86.cpu.ivybridge; - return; - }, - 0x3c, 0x3f, 0x45, 0x46 => { - cpu.model = &Target.x86.cpu.haswell; - return; - }, - 0x3d, 0x47, 0x4f, 0x56 => { - cpu.model = &Target.x86.cpu.broadwell; - return; - }, - 0x4e, 0x5e, 0x8e, 0x9e, 0xa5, 0xa6 => { - cpu.model = &Target.x86.cpu.skylake; - return; - }, - 0xa7 => { - cpu.model = &Target.x86.cpu.rocketlake; - return; - }, - 0x55 => { - if (cpu.has(.x86, .avx512bf16)) { - cpu.model = &Target.x86.cpu.cooperlake; - return; - } else if (cpu.has(.x86, .avx512vnni)) { - cpu.model = &Target.x86.cpu.cascadelake; - return; - } else { - cpu.model = &Target.x86.cpu.skylake_avx512; - return; - } - }, - 0x66 => { - cpu.model = &Target.x86.cpu.cannonlake; - return; - }, - 0x7d, 0x7e => { - cpu.model = &Target.x86.cpu.icelake_client; - return; - }, - 0x6a, 0x6c => { - cpu.model = &Target.x86.cpu.icelake_server; - return; - }, - 0x8c, 0x8d => { - cpu.model = &Target.x86.cpu.tigerlake; - return; - }, - 0x97, 0x9a => { - cpu.model = &Target.x86.cpu.alderlake; - return; - }, - 0xbe => { - cpu.model = &Target.x86.cpu.gracemont; - return; - }, - 0xb7, 0xba, 0xbf => { - cpu.model = &Target.x86.cpu.raptorlake; - return; - }, - 0xaa, 0xac => { - cpu.model = &Target.x86.cpu.meteorlake; - return; - }, - 0xc5, 0xb5 => { - cpu.model = &Target.x86.cpu.arrowlake; - return; - }, - 0xc6 => { - cpu.model = &Target.x86.cpu.arrowlake_s; - return; - }, - 0xbd => { - cpu.model = &Target.x86.cpu.lunarlake; - return; - }, - 0xcc, 0xd5 => { - cpu.model = &Target.x86.cpu.pantherlake; - return; - }, - 0xad => { - cpu.model = &Target.x86.cpu.graniterapids; - return; - }, - 0xae => { - cpu.model = &Target.x86.cpu.graniterapids_d; - return; - }, - 0xcf => { - cpu.model = &Target.x86.cpu.emeraldrapids; - return; - }, - 0x8f => { - cpu.model = &Target.x86.cpu.sapphirerapids; - return; - }, - 0x1c, 0x26, 0x27, 0x35, 0x36 => { - cpu.model = &Target.x86.cpu.bonnell; - return; - }, - 0x37, 0x4a, 0x4d, 0x5a, 0x5d, 0x4c => { - cpu.model = &Target.x86.cpu.silvermont; - return; - }, - 0x5c, 0x5f => { - cpu.model = &Target.x86.cpu.goldmont; - return; - }, - 0x7a => { - cpu.model = &Target.x86.cpu.goldmont_plus; - return; - }, - 0x86, 0x8a, 0x96, 0x9c => { - cpu.model = &Target.x86.cpu.tremont; - return; - }, - 0xaf => { - cpu.model = &Target.x86.cpu.sierraforest; - return; - }, - 0xb6 => { - cpu.model = &Target.x86.cpu.grandridge; - return; - }, - 0xdd => { - cpu.model = &Target.x86.cpu.clearwaterforest; - return; - }, - 0x57 => { - cpu.model = &Target.x86.cpu.knl; - return; - }, - 0x85 => { - cpu.model = &Target.x86.cpu.knm; - return; - }, - else => return, // Unknown CPU Model - } - }, - 15 => { - if (cpu.has(.x86, .@"64bit")) { - cpu.model = &Target.x86.cpu.nocona; - return; - } - if (cpu.has(.x86, .sse3)) { - cpu.model = &Target.x86.cpu.prescott; - return; - } - cpu.model = &Target.x86.cpu.pentium4; - return; +fn detectIntelProcessor(cpu: *const Target.Cpu, family: u32, model: u32, brand_id: u32) ?*const Target.Cpu.Model { + if (brand_id != 0) return null; + + return switch (family) { + 3 => &Target.x86.cpu.i386, + 4 => &Target.x86.cpu.i486, + 5 => if (cpu.has(.x86, .mmx)) + &Target.x86.cpu.pentium_mmx + else + &Target.x86.cpu.pentium, + 6 => switch (model) { + 0x01 => &Target.x86.cpu.pentiumpro, + 0x03, 0x05, 0x06 => &Target.x86.cpu.pentium2, + 0x07, 0x08, 0x0a, 0x0b => &Target.x86.cpu.pentium3, + 0x09, 0x0d, 0x15 => &Target.x86.cpu.pentium_m, + 0x0e => &Target.x86.cpu.yonah, + 0x0f, 0x16 => &Target.x86.cpu.core2, + 0x17, 0x1d => &Target.x86.cpu.penryn, + 0x1a, 0x1e, 0x1f, 0x2e => &Target.x86.cpu.nehalem, + 0x25, 0x2c, 0x2f => &Target.x86.cpu.westmere, + 0x2a, 0x2d => &Target.x86.cpu.sandybridge, + 0x3a, 0x3e => &Target.x86.cpu.ivybridge, + 0x3c, 0x3f, 0x45, 0x46 => &Target.x86.cpu.haswell, + 0x3d, 0x47, 0x4f, 0x56 => &Target.x86.cpu.broadwell, + 0x4e, 0x5e, 0x8e, 0x9e, 0xa5, 0xa6 => &Target.x86.cpu.skylake, + 0xa7 => &Target.x86.cpu.rocketlake, + 0x55 => if (cpu.has(.x86, .avx512bf16)) + &Target.x86.cpu.cooperlake + else if (cpu.has(.x86, .avx512vnni)) + &Target.x86.cpu.cascadelake + else + &Target.x86.cpu.skylake_avx512, + 0x66 => &Target.x86.cpu.cannonlake, + 0x7d, 0x7e => &Target.x86.cpu.icelake_client, + 0x6a, 0x6c => &Target.x86.cpu.icelake_server, + 0x8c, 0x8d => &Target.x86.cpu.tigerlake, + 0x97, 0x9a => &Target.x86.cpu.alderlake, + 0xbe => &Target.x86.cpu.gracemont, + 0xb7, 0xba, 0xbf => &Target.x86.cpu.raptorlake, + 0xaa, 0xac => &Target.x86.cpu.meteorlake, + 0xc5, 0xb5 => &Target.x86.cpu.arrowlake, + 0xc6 => &Target.x86.cpu.arrowlake_s, + 0xbd => &Target.x86.cpu.lunarlake, + 0xcc, 0xd5 => &Target.x86.cpu.pantherlake, + 0xad => &Target.x86.cpu.graniterapids, + 0xae => &Target.x86.cpu.graniterapids_d, + 0xcf => &Target.x86.cpu.emeraldrapids, + 0x8f => &Target.x86.cpu.sapphirerapids, + 0x1c, 0x26, 0x27, 0x35, 0x36 => &Target.x86.cpu.bonnell, + 0x37, 0x4a, 0x4d, 0x5a, 0x5d, 0x4c => &Target.x86.cpu.silvermont, + 0x5c, 0x5f => &Target.x86.cpu.goldmont, + 0x7a => &Target.x86.cpu.goldmont_plus, + 0x86, 0x8a, 0x96, 0x9c => &Target.x86.cpu.tremont, + 0xaf => &Target.x86.cpu.sierraforest, + 0xb6 => &Target.x86.cpu.grandridge, + 0xdd => &Target.x86.cpu.clearwaterforest, + 0x57 => &Target.x86.cpu.knl, + 0x85 => &Target.x86.cpu.knm, + else => null, }, + 15 => if (cpu.has(.x86, .@"64bit")) + &Target.x86.cpu.nocona + else if (cpu.has(.x86, .sse3)) + &Target.x86.cpu.prescott + else + &Target.x86.cpu.pentium4, 18 => switch (model) { - 0x01, 0x03 => { - cpu.model = &Target.x86.cpu.novalake; - return; - }, - else => return, // Unknown CPU Model + 0x01, 0x03 => &Target.x86.cpu.novalake, + else => null, }, 19 => switch (model) { - 0x01 => { - cpu.model = &Target.x86.cpu.diamondrapids; - return; - }, - else => return, // Unknown CPU Model + 0x01 => &Target.x86.cpu.diamondrapids, + else => null, }, - else => return, // Unknown CPU Model - } + else => null, + }; } -fn detectAMDProcessor(cpu: Target.Cpu, family: u32, model: u32) ?*const Target.Cpu.Model { +fn detectAmdProcessor(cpu: *const Target.Cpu, family: u32, model: u32) ?*const Target.Cpu.Model { return switch (family) { 4 => &Target.x86.cpu.i486, 5 => switch (model) {