authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-11-25 14:28:38+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-11-28 17:07:33+01:00
log1eac3c57eca2e736275d0d5066f0ff431ae1f9e8
tree7e60071de30b6048a172bb5e22cb45146dd41fde
parentd9a51648e6b1f1765089e0a50570d86b95b819e9

windows: add processor feature enumeration

2 files changed, 105 insertions(+), 0 deletions(-)

lib/std/os/windows.zig+104
......@@ -3714,3 +3714,107 @@ pub const CTRL_LOGOFF_EVENT: DWORD = 5;
37143714pub const CTRL_SHUTDOWN_EVENT: DWORD = 6;
37153715
37163716pub const HANDLER_ROUTINE = std.meta.FnPtr(fn (dwCtrlType: DWORD) callconv(WINAPI) BOOL);
3717
3718/// The 64-bit load/store atomic instructions are available.
3719pub const PF_ARM_64BIT_LOADSTORE_ATOMIC = 25;
3720
3721/// The divide instruction_available.
3722pub const PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE = 24;
3723
3724/// The external cache is available.
3725pub const PF_ARM_EXTERNAL_CACHE_AVAILABLE = 26;
3726
3727/// The floating-point multiply-accumulate instruction is available.
3728pub const PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE = 27;
3729
3730/// The VFP/Neon: 32 x 64bit register bank is present.
3731/// This flag has the same meaning as PF_ARM_VFP_EXTENDED_REGISTERS.
3732pub const PF_ARM_VFP_32_REGISTERS_AVAILABLE = 18;
3733
3734/// The 3D-Now instruction is available.
3735pub const PF_3DNOW_INSTRUCTIONS_AVAILABLE = 7;
3736
3737/// The processor channels are enabled.
3738pub const PF_CHANNELS_ENABLED = 16;
3739
3740/// The atomic compare and exchange operation (cmpxchg) is available.
3741pub const PF_COMPARE_EXCHANGE_DOUBLE = 2;
3742
3743/// The atomic compare and exchange 128-bit operation (cmpxchg16b) is available.
3744pub const PF_COMPARE_EXCHANGE128 = 14;
3745
3746/// The atomic compare 64 and exchange 128-bit operation (cmp8xchg16) is available.
3747pub const PF_COMPARE64_EXCHANGE128 = 15;
3748
3749/// _fastfail() is available.
3750pub const PF_FASTFAIL_AVAILABLE = 23;
3751
3752/// Floating-point operations are emulated using software emulator.
3753/// This function returns a nonzero value if floating-point operations are emulated; otherwise, it returns zero.
3754pub const PF_FLOATING_POINT_EMULATED = 1;
3755
3756/// On a Pentium, a floating-point precision error can occur in rare circumstances.
3757pub const PF_FLOATING_POINT_PRECISION_ERRATA = 0;
3758
3759/// The MMX instruction set is available.
3760pub const PF_MMX_INSTRUCTIONS_AVAILABLE = 3;
3761
3762/// Data execution prevention is enabled.
3763pub const PF_NX_ENABLED = 12;
3764
3765/// The processor is PAE-enabled.
3766pub const PF_PAE_ENABLED = 9;
3767
3768/// The RDTSC instruction is available.
3769pub const PF_RDTSC_INSTRUCTION_AVAILABLE = 8;
3770
3771/// RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions are available.
3772pub const PF_RDWRFSGBASE_AVAILABLE = 22;
3773
3774/// Second Level Address Translation is supported by the hardware.
3775pub const PF_SECOND_LEVEL_ADDRESS_TRANSLATION = 20;
3776
3777/// The SSE3 instruction set is available.
3778pub const PF_SSE3_INSTRUCTIONS_AVAILABLE = 13;
3779
3780/// The SSSE3 instruction set is available.
3781pub const PF_SSSE3_INSTRUCTIONS_AVAILABLE = 36;
3782
3783/// The SSE4_1 instruction set is available.
3784pub const PF_SSE4_1_INSTRUCTIONS_AVAILABLE = 37;
3785
3786/// The SSE4_2 instruction set is available.
3787pub const PF_SSE4_2_INSTRUCTIONS_AVAILABLE = 38;
3788
3789/// The AVX instruction set is available.
3790pub const PF_AVX_INSTRUCTIONS_AVAILABLE = 39;
3791
3792/// The AVX2 instruction set is available.
3793pub const PF_AVX2_INSTRUCTIONS_AVAILABLE = 40;
3794
3795/// The AVX512F instruction set is available.
3796pub const PF_AVX512F_INSTRUCTIONS_AVAILABLE = 41;
3797
3798/// Virtualization is enabled in the firmware and made available by the operating system.
3799pub const PF_VIRT_FIRMWARE_ENABLED = 21;
3800
3801/// The SSE instruction set is available.
3802pub const PF_XMMI_INSTRUCTIONS_AVAILABLE = 6;
3803
3804/// The SSE2 instruction set is available.
3805pub const PF_XMMI64_INSTRUCTIONS_AVAILABLE = 10;
3806
3807/// The processor implements the XSAVI and XRSTOR instructions.
3808pub const PF_XSAVE_ENABLED = 17;
3809
3810/// This ARM processor implements the ARM v8 instructions set.
3811pub const PF_ARM_V8_INSTRUCTIONS_AVAILABLE = 29;
3812
3813/// This ARM processor implements the ARM v8 extra cryptographic instructions (i.e., AES, SHA1 and SHA2).
3814pub const PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE = 30;
3815
3816/// This ARM processor implements the ARM v8 extra CRC32 instructions.
3817pub const PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE = 31;
3818
3819/// This ARM processor implements the ARM v8.1 atomic instructions (e.g., CAS, SWP).
3820pub const PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE = 34;
lib/std/os/windows/kernel32.zig+1
......@@ -231,6 +231,7 @@ pub extern "kernel32" fn GetQueuedCompletionStatusEx(
231231
232232pub extern "kernel32" fn GetSystemInfo(lpSystemInfo: *SYSTEM_INFO) callconv(WINAPI) void;
233233pub extern "kernel32" fn GetSystemTimeAsFileTime(*FILETIME) callconv(WINAPI) void;
234pub extern "kernel32" fn IsProcessorFeaturePresent(ProcessorFeature: DWORD) BOOL;
234235
235236pub extern "kernel32" fn HeapCreate(flOptions: DWORD, dwInitialSize: SIZE_T, dwMaximumSize: SIZE_T) callconv(WINAPI) ?HANDLE;
236237pub extern "kernel32" fn HeapDestroy(hHeap: HANDLE) callconv(WINAPI) BOOL;