Commit 21908e100e42c5630e1e4253167496fb76238670 | zig

author	Layne Gustafson <lgustaf1@binghamton.edu> 2019-12-17 09:45:00-05:00
committer	Andrew Kelley <andrew@ziglang.org> 2020-01-19 20:53:18-05:00
log	21908e100e42c5630e1e4253167496fb76238670
tree	3a020f997a601b4ce0f46c8bb1ee9604df3158f0
parent	8ac138a318d5581fa7fb80cc540d14e0a482f59e
signature	Commit is signed but in an unrecognized format.

Fix CPU and feature defs

34 files changed, 4682 insertions(+), 4674 deletions(-)

lib/std/target/cpu.zig+7-5

...	...	@@ -1,7 +1,7 @@
1	1	const std = @import("std");
2	2
3	3	const feature = @import("feature.zig");
4		const Arch = @import("arch.zig").Arch;
	4	const Arch = std.Target.Arch;
5	5
6	6	pub const AArch64Cpu = @import("cpu/AArch64Cpu.zig").AArch64Cpu;
7	7	pub const AmdGpuCpu = @import("cpu/AmdGpuCpu.zig").AmdGpuCpu;
...	...	@@ -19,7 +19,7 @@ pub const SystemZCpu = @import("cpu/SystemZCpu.zig").SystemZCpu;
19	19	pub const WebAssemblyCpu = @import("cpu/WebAssemblyCpu.zig").WebAssemblyCpu;
20	20	pub const X86Cpu = @import("cpu/X86Cpu.zig").X86Cpu;
21	21
22		const EmptyCpu = @import("feature/empty.zig").EmptyCpu;
	22	pub const EmptyCpu = @import("cpu/empty.zig").EmptyCpu;
23	23
24	24	pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
25	25	return switch (arch) {
...	...	@@ -44,19 +44,21 @@ pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
44	44	}
45	45
46	46	pub fn ArchCpuInfo(comptime arch: @TagType(Arch)) type {
47		return CpuInfo(feature.ArchFeature(arch));
	47	return CpuInfo(ArchCpu(arch), feature.ArchFeature(arch));
48	48	}
49	49
50		pub fn CpuInfo(comptime FeatureType: type) type {
	50	pub fn CpuInfo(comptime CpuType: type, comptime FeatureType: type) type {
51	51	return struct {
	52	value: CpuType,
52	53	name: []const u8,
53	54
54	55	features: []const FeatureType,
55	56
56	57	const Self = @This();
57	58
58		fn create(name: []const u8, features: []const FeatureType) Self {
	59	pub fn create(value: CpuType, name: []const u8, features: []const FeatureType) Self {
59	60	return Self {
	61	.value = value,
60	62	.name = name,
61	63	.features = features,
62	64	};

lib/std/target/cpu/AArch64Cpu.zig+257-257

...	...	@@ -33,298 +33,298 @@ pub const AArch64Cpu = enum {
33	33	Thunderxt88,
34	34	Tsv110,
35	35
36		pub fn getInfo(self: @This()) CpuInfo {
	36	const FeatureType = feature.AArch64Feature;
	37
	38	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
37	39	return cpu_infos[@enumToInt(self)];
38	40	}
39	41
40		pub const FeatureType = feature.AArch64Feature;
41
42		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
43		CpuInfo(@This()).create(.AppleLatest, "apple-latest", &[_]FeatureType {
44		.ZczFp,
	42	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	43	CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
	44	.ArithBccFusion,
45	45	.ArithCbzFusion,
46		.FuseAes,
	46	.ZczFp,
47	47	.AlternateSextloadCvtF32Pattern,
48		.ZczFpWorkaround,
49		.FpArmv8,
50		.Perfmon,
51	48	.DisableLatencySchedHeuristic,
52		.Zcm,
	49	.Perfmon,
53	50	.ZczGp,
54		.ArithBccFusion,
	51	.ZczFpWorkaround,
	52	.Zcm,
	53	.FpArmv8,
55	54	.FuseCryptoEor,
	55	.FuseAes,
56	56	.Cyclone,
57		},
58		CpuInfo(@This()).create(.CortexA35, "cortex-a35", &[_]FeatureType {
	57	}),
	58	CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
59	59	.Perfmon,
60	60	.FpArmv8,
61	61	.Crc,
62	62	.A35,
63		},
64		CpuInfo(@This()).create(.CortexA53, "cortex-a53", &[_]FeatureType {
65		.UseAa,
66		.FuseAes,
67		.FpArmv8,
	63	}),
	64	CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
68	65	.Perfmon,
69		.Crc,
70		.BalanceFpOps,
71	66	.UsePostraScheduler,
	67	.Crc,
72	68	.CustomCheapAsMove,
	69	.BalanceFpOps,
	70	.UseAa,
	71	.FpArmv8,
	72	.FuseAes,
73	73	.A53,
74		},
75		CpuInfo(@This()).create(.CortexA55, "cortex-a55", &[_]FeatureType {
76		.Rcpc,
77		.Ccpp,
78		.Pan,
	74	}),
	75	CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
	76	.Lse,
	77	.Vh,
79	78	.Rdm,
80		.FuseAes,
81	79	.Perfmon,
82		.FpArmv8,
83		.Lse,
84		.Crc,
	80	.Pan,
85	81	.Dotprod,
	82	.Crc,
86	83	.Lor,
87	84	.Uaops,
88		.Vh,
89	85	.Ras,
90		.A55,
91		},
92		CpuInfo(@This()).create(.CortexA57, "cortex-a57", &[_]FeatureType {
93		.FuseLiterals,
94		.FuseAes,
	86	.Rcpc,
	87	.Ccpp,
95	88	.FpArmv8,
	89	.FuseAes,
	90	.A55,
	91	}),
	92	CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
96	93	.Perfmon,
97		.Crc,
98		.BalanceFpOps,
99	94	.UsePostraScheduler,
100		.CustomCheapAsMove,
	95	.Crc,
101	96	.PredictableSelectExpensive,
102		.A57,
103		},
104		CpuInfo(@This()).create(.CortexA65, "cortex-a65", &[_]FeatureType {
105		.Rcpc,
106		.Ccpp,
107		.Pan,
108		.Rdm,
	97	.CustomCheapAsMove,
	98	.BalanceFpOps,
	99	.FuseLiterals,
109	100	.FpArmv8,
	101	.FuseAes,
	102	.A57,
	103	}),
	104	CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
110	105	.Lse,
111		.Crc,
	106	.Vh,
	107	.Rdm,
	108	.Pan,
112	109	.Dotprod,
113		.Lor,
	110	.Crc,
114	111	.Ssbs,
	112	.Lor,
115	113	.Uaops,
116		.Vh,
117	114	.Ras,
118		.A65,
119		},
120		CpuInfo(@This()).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
121	115	.Rcpc,
122	116	.Ccpp,
123		.Pan,
124		.Rdm,
125	117	.FpArmv8,
	118	.A65,
	119	}),
	120	CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
126	121	.Lse,
127		.Crc,
	122	.Vh,
	123	.Rdm,
	124	.Pan,
128	125	.Dotprod,
129		.Lor,
	126	.Crc,
130	127	.Ssbs,
	128	.Lor,
131	129	.Uaops,
132		.Vh,
133	130	.Ras,
	131	.Rcpc,
	132	.Ccpp,
	133	.FpArmv8,
134	134	.A65,
135		},
136		CpuInfo(@This()).create(.CortexA72, "cortex-a72", &[_]FeatureType {
	135	}),
	136	CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
137	137	.Perfmon,
138		.FuseAes,
139	138	.FpArmv8,
140	139	.Crc,
	140	.FuseAes,
141	141	.A72,
142		},
143		CpuInfo(@This()).create(.CortexA73, "cortex-a73", &[_]FeatureType {
	142	}),
	143	CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
144	144	.Perfmon,
145		.FuseAes,
146	145	.FpArmv8,
147	146	.Crc,
	147	.FuseAes,
148	148	.A73,
149		},
150		CpuInfo(@This()).create(.CortexA75, "cortex-a75", &[_]FeatureType {
151		.Rcpc,
152		.Ccpp,
153		.Pan,
	149	}),
	150	CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
	151	.Lse,
	152	.Vh,
154	153	.Rdm,
155		.FuseAes,
156	154	.Perfmon,
157		.FpArmv8,
158		.Lse,
159		.Crc,
	155	.Pan,
160	156	.Dotprod,
	157	.Crc,
161	158	.Lor,
162	159	.Uaops,
163		.Vh,
164	160	.Ras,
165		.A75,
166		},
167		CpuInfo(@This()).create(.CortexA76, "cortex-a76", &[_]FeatureType {
168	161	.Rcpc,
169	162	.Ccpp,
170		.Pan,
171		.Rdm,
172	163	.FpArmv8,
	164	.FuseAes,
	165	.A75,
	166	}),
	167	CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
173	168	.Lse,
174		.Crc,
	169	.Vh,
	170	.Rdm,
	171	.Pan,
175	172	.Dotprod,
176		.Lor,
	173	.Crc,
177	174	.Ssbs,
	175	.Lor,
178	176	.Uaops,
179		.Vh,
180	177	.Ras,
181		.A76,
182		},
183		CpuInfo(@This()).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
184	178	.Rcpc,
185	179	.Ccpp,
186		.Pan,
187		.Rdm,
188	180	.FpArmv8,
	181	.A76,
	182	}),
	183	CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
189	184	.Lse,
190		.Crc,
	185	.Vh,
	186	.Rdm,
	187	.Pan,
191	188	.Dotprod,
192		.Lor,
	189	.Crc,
193	190	.Ssbs,
	191	.Lor,
194	192	.Uaops,
195		.Vh,
196	193	.Ras,
	194	.Rcpc,
	195	.Ccpp,
	196	.FpArmv8,
197	197	.A76,
198		},
199		CpuInfo(@This()).create(.Cyclone, "cyclone", &[_]FeatureType {
200		.ZczFp,
	198	}),
	199	CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
	200	.ArithBccFusion,
201	201	.ArithCbzFusion,
202		.FuseAes,
	202	.ZczFp,
203	203	.AlternateSextloadCvtF32Pattern,
204		.ZczFpWorkaround,
205		.FpArmv8,
206		.Perfmon,
207	204	.DisableLatencySchedHeuristic,
208		.Zcm,
	205	.Perfmon,
209	206	.ZczGp,
210		.ArithBccFusion,
	207	.ZczFpWorkaround,
	208	.Zcm,
	209	.FpArmv8,
211	210	.FuseCryptoEor,
	211	.FuseAes,
212	212	.Cyclone,
213		},
214		CpuInfo(@This()).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
	213	}),
	214	CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
215	215	.ZczFp,
216		.FuseAes,
217		.SlowPaired128,
218		.Force32bitJumpTables,
219		.UseReciprocalSquareRoot,
220		.FpArmv8,
221	216	.Perfmon,
222		.SlowMisaligned128store,
223		.Crc,
224	217	.UsePostraScheduler,
	218	.Crc,
	219	.UseReciprocalSquareRoot,
225	220	.CustomCheapAsMove,
226		.Exynosm1,
227		},
228		CpuInfo(@This()).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
229		.ZczFp,
230		.FuseAes,
231		.SlowPaired128,
232	221	.Force32bitJumpTables,
	222	.SlowMisaligned128store,
233	223	.FpArmv8,
	224	.SlowPaired128,
	225	.FuseAes,
	226	.Exynosm1,
	227	}),
	228	CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
	229	.ZczFp,
234	230	.Perfmon,
235		.SlowMisaligned128store,
236		.Crc,
237	231	.UsePostraScheduler,
	232	.Crc,
238	233	.CustomCheapAsMove,
239		.Exynosm2,
240		},
241		CpuInfo(@This()).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
242		.ZczFp,
243		.FuseLiterals,
244		.FuseAes,
245	234	.Force32bitJumpTables,
	235	.SlowMisaligned128store,
246	236	.FpArmv8,
	237	.SlowPaired128,
	238	.FuseAes,
	239	.Exynosm2,
	240	}),
	241	CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
	242	.FuseCsel,
	243	.ZczFp,
247	244	.Perfmon,
248		.Crc,
249		.LslFast,
250		.FuseAddress,
251	245	.UsePostraScheduler,
252		.CustomCheapAsMove,
	246	.Crc,
253	247	.PredictableSelectExpensive,
254		.FuseCsel,
	248	.CustomCheapAsMove,
	249	.Force32bitJumpTables,
	250	.FuseLiterals,
	251	.FuseAddress,
	252	.LslFast,
	253	.FpArmv8,
	254	.FuseAes,
255	255	.Exynosm3,
256		},
257		CpuInfo(@This()).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
	256	}),
	257	CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
	258	.ArithBccFusion,
	259	.Vh,
	260	.ArithCbzFusion,
258	261	.ZczFp,
259		.Lse,
260		.FuseArithLogic,
261		.Lor,
	262	.Rdm,
262	263	.UsePostraScheduler,
263		.Uaops,
264		.CustomCheapAsMove,
265		.ArithBccFusion,
	264	.Ras,
	265	.Force32bitJumpTables,
266	266	.Ccpp,
267		.Perfmon,
	267	.FuseCsel,
268	268	.Pan,
269		.Rdm,
	269	.Uaops,
270	270	.FuseLiterals,
271		.Force32bitJumpTables,
272	271	.LslFast,
	272	.Lse,
	273	.Perfmon,
	274	.Dotprod,
	275	.Lor,
	276	.FuseArithLogic,
	277	.Crc,
	278	.CustomCheapAsMove,
273	279	.FuseAddress,
274	280	.ZczGp,
275		.Ras,
276		.FuseCsel,
277		.ArithCbzFusion,
278		.FuseAes,
279	281	.FpArmv8,
280		.Crc,
281		.Dotprod,
282		.Vh,
	282	.FuseAes,
283	283	.Exynosm4,
284		},
285		CpuInfo(@This()).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
	284	}),
	285	CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
	286	.ArithBccFusion,
	287	.Vh,
	288	.ArithCbzFusion,
286	289	.ZczFp,
287		.Lse,
288		.FuseArithLogic,
289		.Lor,
	290	.Rdm,
290	291	.UsePostraScheduler,
291		.Uaops,
292		.CustomCheapAsMove,
293		.ArithBccFusion,
	292	.Ras,
	293	.Force32bitJumpTables,
294	294	.Ccpp,
295		.Perfmon,
	295	.FuseCsel,
296	296	.Pan,
297		.Rdm,
	297	.Uaops,
298	298	.FuseLiterals,
299		.Force32bitJumpTables,
300	299	.LslFast,
	300	.Lse,
	301	.Perfmon,
	302	.Dotprod,
	303	.Lor,
	304	.FuseArithLogic,
	305	.Crc,
	306	.CustomCheapAsMove,
301	307	.FuseAddress,
302	308	.ZczGp,
303		.Ras,
304		.FuseCsel,
305		.ArithCbzFusion,
306		.FuseAes,
307	309	.FpArmv8,
308		.Crc,
309		.Dotprod,
310		.Vh,
	310	.FuseAes,
311	311	.Exynosm4,
312		},
313		CpuInfo(@This()).create(.Falkor, "falkor", &[_]FeatureType {
	312	}),
	313	CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
314	314	.ZczFp,
315	315	.Rdm,
316		.SlowStrqroStore,
317	316	.Perfmon,
318		.FpArmv8,
319		.Crc,
320		.LslFast,
321	317	.UsePostraScheduler,
322		.ZczGp,
323		.CustomCheapAsMove,
	318	.Crc,
324	319	.PredictableSelectExpensive,
	320	.CustomCheapAsMove,
	321	.ZczGp,
	322	.FpArmv8,
	323	.SlowStrqroStore,
	324	.LslFast,
325	325	.Falkor,
326		},
327		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
	326	}),
	327	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
328	328	.Trbe,
329	329	.Ete,
330	330	.FpArmv8,
...	...	@@ -332,149 +332,149 @@ pub const AArch64Cpu = enum {
332	332	.Neon,
333	333	.Perfmon,
334	334	.UsePostraScheduler,
335		},
336		CpuInfo(@This()).create(.Kryo, "kryo", &[_]FeatureType {
	335	}),
	336	CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
337	337	.ZczFp,
338	338	.Perfmon,
339		.FpArmv8,
340		.Crc,
341		.LslFast,
342	339	.UsePostraScheduler,
343		.ZczGp,
344		.CustomCheapAsMove,
	340	.Crc,
345	341	.PredictableSelectExpensive,
346		.Kryo,
347		},
348		CpuInfo(@This()).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
349		.Rcpc,
350		.Ccpp,
351		.Pan,
352		.Rdm,
	342	.CustomCheapAsMove,
	343	.ZczGp,
353	344	.FpArmv8,
	345	.LslFast,
	346	.Kryo,
	347	}),
	348	CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
354	349	.Lse,
355		.Crc,
	350	.Vh,
	351	.Rdm,
	352	.Pan,
356	353	.Dotprod,
357		.Lor,
	354	.Crc,
358	355	.Ssbs,
	356	.Lor,
359	357	.Uaops,
360		.Vh,
361	358	.Ras,
362		.Neoversee1,
363		},
364		CpuInfo(@This()).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
365	359	.Rcpc,
366		.Spe,
367	360	.Ccpp,
368		.Pan,
369		.Rdm,
370	361	.FpArmv8,
	362	.Neoversee1,
	363	}),
	364	CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
371	365	.Lse,
372		.Crc,
	366	.Spe,
	367	.Vh,
	368	.Rdm,
	369	.Pan,
373	370	.Dotprod,
374		.Lor,
	371	.Crc,
375	372	.Ssbs,
	373	.Lor,
376	374	.Uaops,
377		.Vh,
378	375	.Ras,
	376	.Rcpc,
	377	.Ccpp,
	378	.FpArmv8,
379	379	.Neoversen1,
380		},
381		CpuInfo(@This()).create(.Saphira, "saphira", &[_]FeatureType {
	380	}),
	381	CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
	382	.Spe,
	383	.Vh,
382	384	.ZczFp,
383		.Nv,
	385	.Rdm,
	386	.UsePostraScheduler,
	387	.Dit,
384	388	.Am,
385		.Lse,
	389	.Ras,
	390	.Rcpc,
386	391	.Sel2,
387		.Lor,
388		.Tracev84,
389		.Uaops,
390		.UsePostraScheduler,
391		.CustomCheapAsMove,
392	392	.Ccpp,
	393	.Pa,
	394	.Pan,
	395	.Uaops,
	396	.Tracev84,
	397	.Mpam,
	398	.LslFast,
	399	.Lse,
	400	.Nv,
393	401	.Perfmon,
	402	.Dotprod,
394	403	.TlbRmi,
	404	.Lor,
	405	.Ccidx,
395	406	.PredictableSelectExpensive,
	407	.Crc,
	408	.CustomCheapAsMove,
396	409	.Fmi,
397		.Rcpc,
398		.Pan,
399		.Rdm,
400		.LslFast,
401		.Pa,
402	410	.ZczGp,
403		.Dit,
404		.Ras,
405		.Spe,
406		.Mpam,
407	411	.FpArmv8,
408		.Ccidx,
409		.Dotprod,
410		.Crc,
411		.Vh,
412	412	.Saphira,
413		},
414		CpuInfo(@This()).create(.Thunderx, "thunderx", &[_]FeatureType {
	413	}),
	414	CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
415	415	.Perfmon,
416		.FpArmv8,
417		.Crc,
418	416	.UsePostraScheduler,
	417	.Crc,
	418	.FpArmv8,
419	419	.PredictableSelectExpensive,
420	420	.Thunderx,
421		},
422		CpuInfo(@This()).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
423		.Pan,
424		.Rdm,
425		.Vh,
426		.AggressiveFma,
427		.FpArmv8,
	421	}),
	422	CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
428	423	.Lse,
	424	.ArithBccFusion,
	425	.Vh,
	426	.Rdm,
	427	.UsePostraScheduler,
429	428	.Crc,
430	429	.Lor,
431		.UsePostraScheduler,
432		.ArithBccFusion,
	430	.Pan,
	431	.AggressiveFma,
	432	.FpArmv8,
433	433	.PredictableSelectExpensive,
434	434	.Thunderx2t99,
435		},
436		CpuInfo(@This()).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
	435	}),
	436	CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
437	437	.Perfmon,
438		.FpArmv8,
439		.Crc,
440	438	.UsePostraScheduler,
	439	.Crc,
	440	.FpArmv8,
441	441	.PredictableSelectExpensive,
442	442	.Thunderxt81,
443		},
444		CpuInfo(@This()).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
	443	}),
	444	CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
445	445	.Perfmon,
446		.FpArmv8,
447		.Crc,
448	446	.UsePostraScheduler,
	447	.Crc,
	448	.FpArmv8,
449	449	.PredictableSelectExpensive,
450	450	.Thunderxt83,
451		},
452		CpuInfo(@This()).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
	451	}),
	452	CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
453	453	.Perfmon,
454		.FpArmv8,
455		.Crc,
456	454	.UsePostraScheduler,
	455	.Crc,
	456	.FpArmv8,
457	457	.PredictableSelectExpensive,
458	458	.Thunderxt88,
459		},
460		CpuInfo(@This()).create(.Tsv110, "tsv110", &[_]FeatureType {
461		.Uaops,
	459	}),
	460	CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
	461	.Lse,
462	462	.Spe,
463		.Ccpp,
464		.Pan,
465		.Rdm,
466		.FuseAes,
467	463	.Vh,
	464	.Rdm,
468	465	.Perfmon,
469		.FpArmv8,
470		.Lse,
471		.Crc,
	466	.UsePostraScheduler,
	467	.Pan,
472	468	.Dotprod,
	469	.Crc,
473	470	.Lor,
474		.UsePostraScheduler,
	471	.Uaops,
475	472	.CustomCheapAsMove,
476	473	.Ras,
	474	.Ccpp,
	475	.FpArmv8,
	476	.FuseAes,
477	477	.Tsv110,
478		},
	478	}),
479	479	};
480	480	};

lib/std/target/cpu/AmdGpuCpu.zig+521-521

...	...	@@ -42,135 +42,135 @@ pub const AmdGpuCpu = enum {
42	42	Tonga,
43	43	Verde,
44	44
45		pub fn getInfo(self: @This()) CpuInfo {
	45	const FeatureType = feature.AmdGpuFeature;
	46
	47	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
46	48	return cpu_infos[@enumToInt(self)];
47	49	}
48	50
49		pub const FeatureType = feature.AmdGpuFeature;
50
51		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
52		CpuInfo(@This()).create(.Bonaire, "bonaire", &[_]FeatureType {
	51	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	52	CpuInfo(@This(), FeatureType).create(.Bonaire, "bonaire", &[_]FeatureType {
53	53	.CodeObjectV3,
54	54	.NoXnackSupport,
55	55	.Ldsbankcount32,
56		.Wavefrontsize64,
57		.MimgR128,
	56	.Movrel,
	57	.Gfx7Gfx8Gfx9Insts,
58	58	.Fp64,
	59	.TrigReducedRange,
59	60	.CiInsts,
60	61	.FlatAddressSpace,
61		.TrigReducedRange,
62		.NoSramEccSupport,
63		.Movrel,
64	62	.Localmemorysize65536,
65		.Gfx7Gfx8Gfx9Insts,
	63	.Wavefrontsize64,
	64	.NoSramEccSupport,
	65	.MimgR128,
66	66	.SeaIslands,
67		},
68		CpuInfo(@This()).create(.Carrizo, "carrizo", &[_]FeatureType {
	67	}),
	68	CpuInfo(@This(), FeatureType).create(.Carrizo, "carrizo", &[_]FeatureType {
69	69	.CodeObjectV3,
70	70	.FastFmaf,
71	71	.Ldsbankcount32,
72	72	.UnpackedD16Vmem,
73		.Wavefrontsize64,
74		.Fp64,
	73	.IntClampInsts,
	74	.SdwaMav,
	75	.Movrel,
	76	.SMemrealtime,
75	77	.Gcn3Encoding,
76	78	.TrigReducedRange,
77		.Sdwa,
78		.VgprIndexMode,
79		.Dpp,
	79	.CiInsts,
80	80	.FlatAddressSpace,
81		.Gfx8Insts,
82		.Gfx7Gfx8Gfx9Insts,
83		.MimgR128,
	81	.Sdwa,
	82	.Wavefrontsize64,
84	83	.NoSramEccSupport,
85		.IntClampInsts,
86	84	.ScalarStores,
87		.Movrel,
88		.SdwaMav,
89		.CiInsts,
	85	.Gfx7Gfx8Gfx9Insts,
	86	.Dpp,
	87	.Localmemorysize65536,
90	88	.BitInsts16,
91		.SMemrealtime,
	89	.VgprIndexMode,
	90	.Gfx8Insts,
92	91	.Inv2piInlineImm,
93		.Localmemorysize65536,
	92	.MimgR128,
94	93	.SdwaOutModsVopc,
	94	.Fp64,
95	95	.VolcanicIslands,
96	96	.Xnack,
97	97	.HalfRate64Ops,
98		},
99		CpuInfo(@This()).create(.Fiji, "fiji", &[_]FeatureType {
	98	}),
	99	CpuInfo(@This(), FeatureType).create(.Fiji, "fiji", &[_]FeatureType {
100	100	.CodeObjectV3,
101	101	.NoXnackSupport,
102	102	.Ldsbankcount32,
103	103	.UnpackedD16Vmem,
104		.Wavefrontsize64,
105		.Fp64,
	104	.IntClampInsts,
	105	.SdwaMav,
	106	.Movrel,
	107	.SMemrealtime,
106	108	.Gcn3Encoding,
107	109	.TrigReducedRange,
108		.Sdwa,
109		.VgprIndexMode,
110		.Dpp,
	110	.CiInsts,
111	111	.FlatAddressSpace,
112		.Gfx8Insts,
113		.Gfx7Gfx8Gfx9Insts,
114		.MimgR128,
	112	.Sdwa,
	113	.Wavefrontsize64,
115	114	.NoSramEccSupport,
116		.IntClampInsts,
117	115	.ScalarStores,
118		.Movrel,
119		.SdwaMav,
120		.CiInsts,
	116	.Gfx7Gfx8Gfx9Insts,
	117	.Dpp,
	118	.Localmemorysize65536,
121	119	.BitInsts16,
122		.SMemrealtime,
	120	.VgprIndexMode,
	121	.Gfx8Insts,
123	122	.Inv2piInlineImm,
124		.Localmemorysize65536,
	123	.MimgR128,
125	124	.SdwaOutModsVopc,
	125	.Fp64,
126	126	.VolcanicIslands,
127		},
128		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
	127	}),
	128	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
129	129	.Wavefrontsize64,
130		},
131		CpuInfo(@This()).create(.GenericHsa, "generic-hsa", &[_]FeatureType {
	130	}),
	131	CpuInfo(@This(), FeatureType).create(.GenericHsa, "generic-hsa", &[_]FeatureType {
132	132	.FlatAddressSpace,
133	133	.Wavefrontsize64,
134		},
135		CpuInfo(@This()).create(.Gfx1010, "gfx1010", &[_]FeatureType {
	134	}),
	135	CpuInfo(@This(), FeatureType).create(.Gfx1010, "gfx1010", &[_]FeatureType {
136	136	.CodeObjectV3,
137	137	.DlInsts,
138	138	.NoXnackSupport,
139	139	.FlatSegmentOffsetBug,
140		.Gfx9Insts,
141		.NoSdstCmpx,
142		.Fp64,
143		.FastFmaf,
144		.Sdwa,
145		.SdwaScalar,
146		.Dpp,
147		.RegisterBanking,
	140	.Vscnt,
	141	.ApertureRegs,
148	142	.Gfx10Insts,
149		.AddNoCarryInsts,
	143	.IntClampInsts,
	144	.PkFmacF16Inst,
150	145	.SdwaOmod,
151		.SdwaSdst,
	146	.SdwaScalar,
	147	.AddNoCarryInsts,
	148	.Movrel,
	149	.SMemrealtime,
	150	.NoSdstCmpx,
	151	.CiInsts,
152	152	.FlatAddressSpace,
	153	.Sdwa,
	154	.NoSramEccSupport,
	155	.SdwaSdst,
	156	.FlatInstOffsets,
	157	.RegisterBanking,
	158	.Dpp,
	159	.Localmemorysize65536,
	160	.Vop3p,
	161	.BitInsts16,
	162	.Dpp8,
153	163	.Gfx8Insts,
	164	.Inv2piInlineImm,
	165	.Gfx9Insts,
154	166	.FmaMixInsts,
155		.PkFmacF16Inst,
156		.Vop3Literal,
157	167	.MimgR128,
158		.NoSramEccSupport,
159		.IntClampInsts,
160		.Movrel,
161		.Dpp8,
162		.ApertureRegs,
163		.NoDataDepHazard,
164		.CiInsts,
	168	.Vop3Literal,
165	169	.FlatGlobalInsts,
166		.BitInsts16,
167	170	.FlatScratchInsts,
168		.SMemrealtime,
169		.Vop3p,
170		.FlatInstOffsets,
171		.Inv2piInlineImm,
172		.Localmemorysize65536,
173		.Vscnt,
	171	.Fp64,
	172	.FastFmaf,
	173	.NoDataDepHazard,
174	174	.Gfx10,
175	175	.InstFwdPrefetchBug,
176	176	.Ldsbankcount32,
...	...	@@ -187,8 +187,8 @@ pub const AmdGpuCpu = enum {
187	187	.VcmpxExecWarHazard,
188	188	.VcmpxPermlaneHazard,
189	189	.Wavefrontsize32,
190		},
191		CpuInfo(@This()).create(.Gfx1011, "gfx1011", &[_]FeatureType {
	190	}),
	191	CpuInfo(@This(), FeatureType).create(.Gfx1011, "gfx1011", &[_]FeatureType {
192	192	.CodeObjectV3,
193	193	.DlInsts,
194	194	.NoXnackSupport,
...	...	@@ -197,40 +197,40 @@ pub const AmdGpuCpu = enum {
197	197	.Dot5Insts,
198	198	.Dot6Insts,
199	199	.FlatSegmentOffsetBug,
200		.Gfx9Insts,
201		.NoSdstCmpx,
202		.Fp64,
203		.FastFmaf,
204		.Sdwa,
205		.SdwaScalar,
206		.Dpp,
207		.RegisterBanking,
	200	.Vscnt,
	201	.ApertureRegs,
208	202	.Gfx10Insts,
209		.AddNoCarryInsts,
	203	.IntClampInsts,
	204	.PkFmacF16Inst,
210	205	.SdwaOmod,
211		.SdwaSdst,
	206	.SdwaScalar,
	207	.AddNoCarryInsts,
	208	.Movrel,
	209	.SMemrealtime,
	210	.NoSdstCmpx,
	211	.CiInsts,
212	212	.FlatAddressSpace,
	213	.Sdwa,
	214	.NoSramEccSupport,
	215	.SdwaSdst,
	216	.FlatInstOffsets,
	217	.RegisterBanking,
	218	.Dpp,
	219	.Localmemorysize65536,
	220	.Vop3p,
	221	.BitInsts16,
	222	.Dpp8,
213	223	.Gfx8Insts,
	224	.Inv2piInlineImm,
	225	.Gfx9Insts,
214	226	.FmaMixInsts,
215		.PkFmacF16Inst,
216		.Vop3Literal,
217	227	.MimgR128,
218		.NoSramEccSupport,
219		.IntClampInsts,
220		.Movrel,
221		.Dpp8,
222		.ApertureRegs,
223		.NoDataDepHazard,
224		.CiInsts,
	228	.Vop3Literal,
225	229	.FlatGlobalInsts,
226		.BitInsts16,
227	230	.FlatScratchInsts,
228		.SMemrealtime,
229		.Vop3p,
230		.FlatInstOffsets,
231		.Inv2piInlineImm,
232		.Localmemorysize65536,
233		.Vscnt,
	231	.Fp64,
	232	.FastFmaf,
	233	.NoDataDepHazard,
234	234	.Gfx10,
235	235	.InstFwdPrefetchBug,
236	236	.Ldsbankcount32,
...	...	@@ -246,8 +246,8 @@ pub const AmdGpuCpu = enum {
246	246	.VcmpxExecWarHazard,
247	247	.VcmpxPermlaneHazard,
248	248	.Wavefrontsize32,
249		},
250		CpuInfo(@This()).create(.Gfx1012, "gfx1012", &[_]FeatureType {
	249	}),
	250	CpuInfo(@This(), FeatureType).create(.Gfx1012, "gfx1012", &[_]FeatureType {
251	251	.CodeObjectV3,
252	252	.DlInsts,
253	253	.NoXnackSupport,
...	...	@@ -256,40 +256,40 @@ pub const AmdGpuCpu = enum {
256	256	.Dot5Insts,
257	257	.Dot6Insts,
258	258	.FlatSegmentOffsetBug,
259		.Gfx9Insts,
260		.NoSdstCmpx,
261		.Fp64,
262		.FastFmaf,
263		.Sdwa,
264		.SdwaScalar,
265		.Dpp,
266		.RegisterBanking,
	259	.Vscnt,
	260	.ApertureRegs,
267	261	.Gfx10Insts,
268		.AddNoCarryInsts,
	262	.IntClampInsts,
	263	.PkFmacF16Inst,
269	264	.SdwaOmod,
270		.SdwaSdst,
	265	.SdwaScalar,
	266	.AddNoCarryInsts,
	267	.Movrel,
	268	.SMemrealtime,
	269	.NoSdstCmpx,
	270	.CiInsts,
271	271	.FlatAddressSpace,
	272	.Sdwa,
	273	.NoSramEccSupport,
	274	.SdwaSdst,
	275	.FlatInstOffsets,
	276	.RegisterBanking,
	277	.Dpp,
	278	.Localmemorysize65536,
	279	.Vop3p,
	280	.BitInsts16,
	281	.Dpp8,
272	282	.Gfx8Insts,
	283	.Inv2piInlineImm,
	284	.Gfx9Insts,
273	285	.FmaMixInsts,
274		.PkFmacF16Inst,
275		.Vop3Literal,
276	286	.MimgR128,
277		.NoSramEccSupport,
278		.IntClampInsts,
279		.Movrel,
280		.Dpp8,
281		.ApertureRegs,
282		.NoDataDepHazard,
283		.CiInsts,
	287	.Vop3Literal,
284	288	.FlatGlobalInsts,
285		.BitInsts16,
286	289	.FlatScratchInsts,
287		.SMemrealtime,
288		.Vop3p,
289		.FlatInstOffsets,
290		.Inv2piInlineImm,
291		.Localmemorysize65536,
292		.Vscnt,
	290	.Fp64,
	291	.FastFmaf,
	292	.NoDataDepHazard,
293	293	.Gfx10,
294	294	.InstFwdPrefetchBug,
295	295	.Ldsbankcount32,
...	...	@@ -306,392 +306,392 @@ pub const AmdGpuCpu = enum {
306	306	.VcmpxExecWarHazard,
307	307	.VcmpxPermlaneHazard,
308	308	.Wavefrontsize32,
309		},
310		CpuInfo(@This()).create(.Gfx600, "gfx600", &[_]FeatureType {
	309	}),
	310	CpuInfo(@This(), FeatureType).create(.Gfx600, "gfx600", &[_]FeatureType {
311	311	.CodeObjectV3,
312	312	.NoXnackSupport,
313	313	.FastFmaf,
314	314	.Ldsbankcount32,
315		.Wavefrontsize64,
	315	.Movrel,
316	316	.MimgR128,
317	317	.Fp64,
318	318	.TrigReducedRange,
	319	.Wavefrontsize64,
319	320	.NoSramEccSupport,
320		.Movrel,
321	321	.Localmemorysize32768,
322	322	.SouthernIslands,
323	323	.HalfRate64Ops,
324		},
325		CpuInfo(@This()).create(.Gfx601, "gfx601", &[_]FeatureType {
	324	}),
	325	CpuInfo(@This(), FeatureType).create(.Gfx601, "gfx601", &[_]FeatureType {
326	326	.CodeObjectV3,
327	327	.NoXnackSupport,
328	328	.Ldsbankcount32,
329		.Wavefrontsize64,
	329	.Movrel,
330	330	.MimgR128,
331	331	.Fp64,
332	332	.TrigReducedRange,
	333	.Wavefrontsize64,
333	334	.NoSramEccSupport,
334		.Movrel,
335	335	.Localmemorysize32768,
336	336	.SouthernIslands,
337		},
338		CpuInfo(@This()).create(.Gfx700, "gfx700", &[_]FeatureType {
	337	}),
	338	CpuInfo(@This(), FeatureType).create(.Gfx700, "gfx700", &[_]FeatureType {
339	339	.CodeObjectV3,
340	340	.NoXnackSupport,
341	341	.Ldsbankcount32,
342		.Wavefrontsize64,
343		.MimgR128,
	342	.Movrel,
	343	.Gfx7Gfx8Gfx9Insts,
344	344	.Fp64,
	345	.TrigReducedRange,
345	346	.CiInsts,
346	347	.FlatAddressSpace,
347		.TrigReducedRange,
348		.NoSramEccSupport,
349		.Movrel,
350	348	.Localmemorysize65536,
351		.Gfx7Gfx8Gfx9Insts,
	349	.Wavefrontsize64,
	350	.NoSramEccSupport,
	351	.MimgR128,
352	352	.SeaIslands,
353		},
354		CpuInfo(@This()).create(.Gfx701, "gfx701", &[_]FeatureType {
	353	}),
	354	CpuInfo(@This(), FeatureType).create(.Gfx701, "gfx701", &[_]FeatureType {
355	355	.CodeObjectV3,
356	356	.NoXnackSupport,
357	357	.FastFmaf,
358	358	.Ldsbankcount32,
359		.Wavefrontsize64,
360		.MimgR128,
	359	.Movrel,
	360	.Gfx7Gfx8Gfx9Insts,
361	361	.Fp64,
	362	.TrigReducedRange,
362	363	.CiInsts,
363	364	.FlatAddressSpace,
364		.TrigReducedRange,
365		.NoSramEccSupport,
366		.Movrel,
367	365	.Localmemorysize65536,
368		.Gfx7Gfx8Gfx9Insts,
369		.SeaIslands,
	366	.Wavefrontsize64,
	367	.NoSramEccSupport,
	368	.MimgR128,
	369	.SeaIslands,
370	370	.HalfRate64Ops,
371		},
372		CpuInfo(@This()).create(.Gfx702, "gfx702", &[_]FeatureType {
	371	}),
	372	CpuInfo(@This(), FeatureType).create(.Gfx702, "gfx702", &[_]FeatureType {
373	373	.CodeObjectV3,
374	374	.NoXnackSupport,
375	375	.FastFmaf,
376	376	.Ldsbankcount16,
377		.Wavefrontsize64,
378		.MimgR128,
	377	.Movrel,
	378	.Gfx7Gfx8Gfx9Insts,
379	379	.Fp64,
	380	.TrigReducedRange,
380	381	.CiInsts,
381	382	.FlatAddressSpace,
382		.TrigReducedRange,
383		.NoSramEccSupport,
384		.Movrel,
385	383	.Localmemorysize65536,
386		.Gfx7Gfx8Gfx9Insts,
	384	.Wavefrontsize64,
	385	.NoSramEccSupport,
	386	.MimgR128,
387	387	.SeaIslands,
388		},
389		CpuInfo(@This()).create(.Gfx703, "gfx703", &[_]FeatureType {
	388	}),
	389	CpuInfo(@This(), FeatureType).create(.Gfx703, "gfx703", &[_]FeatureType {
390	390	.CodeObjectV3,
391	391	.NoXnackSupport,
392	392	.Ldsbankcount16,
393		.Wavefrontsize64,
394		.MimgR128,
	393	.Movrel,
	394	.Gfx7Gfx8Gfx9Insts,
395	395	.Fp64,
	396	.TrigReducedRange,
396	397	.CiInsts,
397	398	.FlatAddressSpace,
398		.TrigReducedRange,
399		.NoSramEccSupport,
400		.Movrel,
401	399	.Localmemorysize65536,
402		.Gfx7Gfx8Gfx9Insts,
	400	.Wavefrontsize64,
	401	.NoSramEccSupport,
	402	.MimgR128,
403	403	.SeaIslands,
404		},
405		CpuInfo(@This()).create(.Gfx704, "gfx704", &[_]FeatureType {
	404	}),
	405	CpuInfo(@This(), FeatureType).create(.Gfx704, "gfx704", &[_]FeatureType {
406	406	.CodeObjectV3,
407	407	.NoXnackSupport,
408	408	.Ldsbankcount32,
409		.Wavefrontsize64,
410		.MimgR128,
	409	.Movrel,
	410	.Gfx7Gfx8Gfx9Insts,
411	411	.Fp64,
	412	.TrigReducedRange,
412	413	.CiInsts,
413	414	.FlatAddressSpace,
414		.TrigReducedRange,
415		.NoSramEccSupport,
416		.Movrel,
417	415	.Localmemorysize65536,
418		.Gfx7Gfx8Gfx9Insts,
	416	.Wavefrontsize64,
	417	.NoSramEccSupport,
	418	.MimgR128,
419	419	.SeaIslands,
420		},
421		CpuInfo(@This()).create(.Gfx801, "gfx801", &[_]FeatureType {
	420	}),
	421	CpuInfo(@This(), FeatureType).create(.Gfx801, "gfx801", &[_]FeatureType {
422	422	.CodeObjectV3,
423	423	.FastFmaf,
424	424	.Ldsbankcount32,
425	425	.UnpackedD16Vmem,
426		.Wavefrontsize64,
427		.Fp64,
	426	.IntClampInsts,
	427	.SdwaMav,
	428	.Movrel,
	429	.SMemrealtime,
428	430	.Gcn3Encoding,
429	431	.TrigReducedRange,
430		.Sdwa,
431		.VgprIndexMode,
432		.Dpp,
	432	.CiInsts,
433	433	.FlatAddressSpace,
434		.Gfx8Insts,
435		.Gfx7Gfx8Gfx9Insts,
436		.MimgR128,
	434	.Sdwa,
	435	.Wavefrontsize64,
437	436	.NoSramEccSupport,
438		.IntClampInsts,
439	437	.ScalarStores,
440		.Movrel,
441		.SdwaMav,
442		.CiInsts,
	438	.Gfx7Gfx8Gfx9Insts,
	439	.Dpp,
	440	.Localmemorysize65536,
443	441	.BitInsts16,
444		.SMemrealtime,
	442	.VgprIndexMode,
	443	.Gfx8Insts,
445	444	.Inv2piInlineImm,
446		.Localmemorysize65536,
	445	.MimgR128,
447	446	.SdwaOutModsVopc,
	447	.Fp64,
448	448	.VolcanicIslands,
449	449	.Xnack,
450	450	.HalfRate64Ops,
451		},
452		CpuInfo(@This()).create(.Gfx802, "gfx802", &[_]FeatureType {
	451	}),
	452	CpuInfo(@This(), FeatureType).create(.Gfx802, "gfx802", &[_]FeatureType {
453	453	.CodeObjectV3,
454	454	.NoXnackSupport,
455	455	.Ldsbankcount32,
456	456	.SgprInitBug,
457	457	.UnpackedD16Vmem,
458		.Wavefrontsize64,
459		.Fp64,
	458	.IntClampInsts,
	459	.SdwaMav,
	460	.Movrel,
	461	.SMemrealtime,
460	462	.Gcn3Encoding,
461	463	.TrigReducedRange,
462		.Sdwa,
463		.VgprIndexMode,
464		.Dpp,
	464	.CiInsts,
465	465	.FlatAddressSpace,
466		.Gfx8Insts,
467		.Gfx7Gfx8Gfx9Insts,
468		.MimgR128,
	466	.Sdwa,
	467	.Wavefrontsize64,
469	468	.NoSramEccSupport,
470		.IntClampInsts,
471	469	.ScalarStores,
472		.Movrel,
473		.SdwaMav,
474		.CiInsts,
	470	.Gfx7Gfx8Gfx9Insts,
	471	.Dpp,
	472	.Localmemorysize65536,
475	473	.BitInsts16,
476		.SMemrealtime,
	474	.VgprIndexMode,
	475	.Gfx8Insts,
477	476	.Inv2piInlineImm,
478		.Localmemorysize65536,
	477	.MimgR128,
479	478	.SdwaOutModsVopc,
	479	.Fp64,
480	480	.VolcanicIslands,
481		},
482		CpuInfo(@This()).create(.Gfx803, "gfx803", &[_]FeatureType {
	481	}),
	482	CpuInfo(@This(), FeatureType).create(.Gfx803, "gfx803", &[_]FeatureType {
483	483	.CodeObjectV3,
484	484	.NoXnackSupport,
485	485	.Ldsbankcount32,
486	486	.UnpackedD16Vmem,
487		.Wavefrontsize64,
488		.Fp64,
	487	.IntClampInsts,
	488	.SdwaMav,
	489	.Movrel,
	490	.SMemrealtime,
489	491	.Gcn3Encoding,
490	492	.TrigReducedRange,
491		.Sdwa,
492		.VgprIndexMode,
493		.Dpp,
	493	.CiInsts,
494	494	.FlatAddressSpace,
495		.Gfx8Insts,
496		.Gfx7Gfx8Gfx9Insts,
497		.MimgR128,
	495	.Sdwa,
	496	.Wavefrontsize64,
498	497	.NoSramEccSupport,
499		.IntClampInsts,
500	498	.ScalarStores,
501		.Movrel,
502		.SdwaMav,
503		.CiInsts,
	499	.Gfx7Gfx8Gfx9Insts,
	500	.Dpp,
	501	.Localmemorysize65536,
504	502	.BitInsts16,
505		.SMemrealtime,
	503	.VgprIndexMode,
	504	.Gfx8Insts,
506	505	.Inv2piInlineImm,
507		.Localmemorysize65536,
	506	.MimgR128,
508	507	.SdwaOutModsVopc,
	508	.Fp64,
509	509	.VolcanicIslands,
510		},
511		CpuInfo(@This()).create(.Gfx810, "gfx810", &[_]FeatureType {
	510	}),
	511	CpuInfo(@This(), FeatureType).create(.Gfx810, "gfx810", &[_]FeatureType {
512	512	.CodeObjectV3,
513	513	.Ldsbankcount16,
514		.Wavefrontsize64,
515		.Fp64,
	514	.IntClampInsts,
	515	.SdwaMav,
	516	.Movrel,
	517	.SMemrealtime,
516	518	.Gcn3Encoding,
517	519	.TrigReducedRange,
518		.Sdwa,
519		.VgprIndexMode,
520		.Dpp,
	520	.CiInsts,
521	521	.FlatAddressSpace,
522		.Gfx8Insts,
523		.Gfx7Gfx8Gfx9Insts,
524		.MimgR128,
	522	.Sdwa,
	523	.Wavefrontsize64,
525	524	.NoSramEccSupport,
526		.IntClampInsts,
527	525	.ScalarStores,
528		.Movrel,
529		.SdwaMav,
530		.CiInsts,
	526	.Gfx7Gfx8Gfx9Insts,
	527	.Dpp,
	528	.Localmemorysize65536,
531	529	.BitInsts16,
532		.SMemrealtime,
	530	.VgprIndexMode,
	531	.Gfx8Insts,
533	532	.Inv2piInlineImm,
534		.Localmemorysize65536,
	533	.MimgR128,
535	534	.SdwaOutModsVopc,
	535	.Fp64,
536	536	.VolcanicIslands,
537	537	.Xnack,
538		},
539		CpuInfo(@This()).create(.Gfx900, "gfx900", &[_]FeatureType {
	538	}),
	539	CpuInfo(@This(), FeatureType).create(.Gfx900, "gfx900", &[_]FeatureType {
540	540	.CodeObjectV3,
541	541	.NoSramEccSupport,
542	542	.NoXnackSupport,
543		.Gfx9Insts,
544		.Wavefrontsize64,
545		.Fp64,
546		.Gcn3Encoding,
547		.FastFmaf,
548		.Sdwa,
	543	.ApertureRegs,
	544	.IntClampInsts,
	545	.SdwaOmod,
549	546	.SdwaScalar,
550		.VgprIndexMode,
551		.Dpp,
552	547	.AddNoCarryInsts,
553		.SdwaOmod,
554		.SdwaSdst,
555	548	.ScalarAtomics,
	549	.SMemrealtime,
	550	.Gcn3Encoding,
	551	.CiInsts,
556	552	.FlatAddressSpace,
557		.ScalarFlatScratchInsts,
558		.Gfx8Insts,
	553	.Sdwa,
	554	.Wavefrontsize64,
	555	.SdwaSdst,
	556	.FlatInstOffsets,
	557	.ScalarStores,
559	558	.Gfx7Gfx8Gfx9Insts,
560	559	.R128A16,
561		.IntClampInsts,
562		.ScalarStores,
563		.ApertureRegs,
564		.CiInsts,
565		.FlatGlobalInsts,
566		.BitInsts16,
567		.FlatScratchInsts,
568		.SMemrealtime,
	560	.Dpp,
	561	.Localmemorysize65536,
569	562	.Vop3p,
570		.FlatInstOffsets,
	563	.BitInsts16,
	564	.VgprIndexMode,
	565	.Gfx8Insts,
571	566	.Inv2piInlineImm,
572		.Localmemorysize65536,
	567	.Gfx9Insts,
	568	.ScalarFlatScratchInsts,
	569	.FlatGlobalInsts,
	570	.FlatScratchInsts,
	571	.Fp64,
	572	.FastFmaf,
573	573	.Gfx9,
574	574	.Ldsbankcount32,
575	575	.MadMixInsts,
576		},
577		CpuInfo(@This()).create(.Gfx902, "gfx902", &[_]FeatureType {
	576	}),
	577	CpuInfo(@This(), FeatureType).create(.Gfx902, "gfx902", &[_]FeatureType {
578	578	.CodeObjectV3,
579	579	.NoSramEccSupport,
580		.Gfx9Insts,
581		.Wavefrontsize64,
582		.Fp64,
583		.Gcn3Encoding,
584		.FastFmaf,
585		.Sdwa,
	580	.ApertureRegs,
	581	.IntClampInsts,
	582	.SdwaOmod,
586	583	.SdwaScalar,
587		.VgprIndexMode,
588		.Dpp,
589	584	.AddNoCarryInsts,
590		.SdwaOmod,
591		.SdwaSdst,
592	585	.ScalarAtomics,
	586	.SMemrealtime,
	587	.Gcn3Encoding,
	588	.CiInsts,
593	589	.FlatAddressSpace,
594		.ScalarFlatScratchInsts,
595		.Gfx8Insts,
	590	.Sdwa,
	591	.Wavefrontsize64,
	592	.SdwaSdst,
	593	.FlatInstOffsets,
	594	.ScalarStores,
596	595	.Gfx7Gfx8Gfx9Insts,
597	596	.R128A16,
598		.IntClampInsts,
599		.ScalarStores,
600		.ApertureRegs,
601		.CiInsts,
602		.FlatGlobalInsts,
603		.BitInsts16,
604		.FlatScratchInsts,
605		.SMemrealtime,
	597	.Dpp,
	598	.Localmemorysize65536,
606	599	.Vop3p,
607		.FlatInstOffsets,
	600	.BitInsts16,
	601	.VgprIndexMode,
	602	.Gfx8Insts,
608	603	.Inv2piInlineImm,
609		.Localmemorysize65536,
	604	.Gfx9Insts,
	605	.ScalarFlatScratchInsts,
	606	.FlatGlobalInsts,
	607	.FlatScratchInsts,
	608	.Fp64,
	609	.FastFmaf,
610	610	.Gfx9,
611	611	.Ldsbankcount32,
612	612	.MadMixInsts,
613	613	.Xnack,
614		},
615		CpuInfo(@This()).create(.Gfx904, "gfx904", &[_]FeatureType {
	614	}),
	615	CpuInfo(@This(), FeatureType).create(.Gfx904, "gfx904", &[_]FeatureType {
616	616	.CodeObjectV3,
617	617	.NoSramEccSupport,
618	618	.NoXnackSupport,
619	619	.FmaMixInsts,
620		.Gfx9Insts,
621		.Wavefrontsize64,
622		.Fp64,
623		.Gcn3Encoding,
624		.FastFmaf,
625		.Sdwa,
	620	.ApertureRegs,
	621	.IntClampInsts,
	622	.SdwaOmod,
626	623	.SdwaScalar,
627		.VgprIndexMode,
628		.Dpp,
629	624	.AddNoCarryInsts,
630		.SdwaOmod,
631		.SdwaSdst,
632	625	.ScalarAtomics,
	626	.SMemrealtime,
	627	.Gcn3Encoding,
	628	.CiInsts,
633	629	.FlatAddressSpace,
634		.ScalarFlatScratchInsts,
635		.Gfx8Insts,
	630	.Sdwa,
	631	.Wavefrontsize64,
	632	.SdwaSdst,
	633	.FlatInstOffsets,
	634	.ScalarStores,
636	635	.Gfx7Gfx8Gfx9Insts,
637	636	.R128A16,
638		.IntClampInsts,
639		.ScalarStores,
640		.ApertureRegs,
641		.CiInsts,
642		.FlatGlobalInsts,
643		.BitInsts16,
644		.FlatScratchInsts,
645		.SMemrealtime,
	637	.Dpp,
	638	.Localmemorysize65536,
646	639	.Vop3p,
647		.FlatInstOffsets,
	640	.BitInsts16,
	641	.VgprIndexMode,
	642	.Gfx8Insts,
648	643	.Inv2piInlineImm,
649		.Localmemorysize65536,
	644	.Gfx9Insts,
	645	.ScalarFlatScratchInsts,
	646	.FlatGlobalInsts,
	647	.FlatScratchInsts,
	648	.Fp64,
	649	.FastFmaf,
650	650	.Gfx9,
651	651	.Ldsbankcount32,
652		},
653		CpuInfo(@This()).create(.Gfx906, "gfx906", &[_]FeatureType {
	652	}),
	653	CpuInfo(@This(), FeatureType).create(.Gfx906, "gfx906", &[_]FeatureType {
654	654	.CodeObjectV3,
655	655	.DlInsts,
656	656	.NoXnackSupport,
657	657	.Dot1Insts,
658	658	.Dot2Insts,
659	659	.FmaMixInsts,
660		.Gfx9Insts,
661		.Wavefrontsize64,
662		.Fp64,
663		.Gcn3Encoding,
664		.FastFmaf,
665		.Sdwa,
	660	.ApertureRegs,
	661	.IntClampInsts,
	662	.SdwaOmod,
666	663	.SdwaScalar,
667		.VgprIndexMode,
668		.Dpp,
669	664	.AddNoCarryInsts,
670		.SdwaOmod,
671		.SdwaSdst,
672	665	.ScalarAtomics,
	666	.SMemrealtime,
	667	.Gcn3Encoding,
	668	.CiInsts,
673	669	.FlatAddressSpace,
674		.ScalarFlatScratchInsts,
675		.Gfx8Insts,
	670	.Sdwa,
	671	.Wavefrontsize64,
	672	.SdwaSdst,
	673	.FlatInstOffsets,
	674	.ScalarStores,
676	675	.Gfx7Gfx8Gfx9Insts,
677	676	.R128A16,
678		.IntClampInsts,
679		.ScalarStores,
680		.ApertureRegs,
681		.CiInsts,
682		.FlatGlobalInsts,
683		.BitInsts16,
684		.FlatScratchInsts,
685		.SMemrealtime,
	677	.Dpp,
	678	.Localmemorysize65536,
686	679	.Vop3p,
687		.FlatInstOffsets,
	680	.BitInsts16,
	681	.VgprIndexMode,
	682	.Gfx8Insts,
688	683	.Inv2piInlineImm,
689		.Localmemorysize65536,
	684	.Gfx9Insts,
	685	.ScalarFlatScratchInsts,
	686	.FlatGlobalInsts,
	687	.FlatScratchInsts,
	688	.Fp64,
	689	.FastFmaf,
690	690	.Gfx9,
691	691	.Ldsbankcount32,
692	692	.HalfRate64Ops,
693		},
694		CpuInfo(@This()).create(.Gfx908, "gfx908", &[_]FeatureType {
	693	}),
	694	CpuInfo(@This(), FeatureType).create(.Gfx908, "gfx908", &[_]FeatureType {
695	695	.AtomicFaddInsts,
696	696	.CodeObjectV3,
697	697	.DlInsts,
...	...	@@ -702,36 +702,36 @@ pub const AmdGpuCpu = enum {
702	702	.Dot5Insts,
703	703	.Dot6Insts,
704	704	.FmaMixInsts,
705		.Gfx9Insts,
706		.Wavefrontsize64,
707		.Fp64,
708		.Gcn3Encoding,
709		.FastFmaf,
710		.Sdwa,
	705	.ApertureRegs,
	706	.IntClampInsts,
	707	.SdwaOmod,
711	708	.SdwaScalar,
712		.VgprIndexMode,
713		.Dpp,
714	709	.AddNoCarryInsts,
715		.SdwaOmod,
716		.SdwaSdst,
717	710	.ScalarAtomics,
	711	.SMemrealtime,
	712	.Gcn3Encoding,
	713	.CiInsts,
718	714	.FlatAddressSpace,
719		.ScalarFlatScratchInsts,
720		.Gfx8Insts,
	715	.Sdwa,
	716	.Wavefrontsize64,
	717	.SdwaSdst,
	718	.FlatInstOffsets,
	719	.ScalarStores,
721	720	.Gfx7Gfx8Gfx9Insts,
722	721	.R128A16,
723		.IntClampInsts,
724		.ScalarStores,
725		.ApertureRegs,
726		.CiInsts,
727		.FlatGlobalInsts,
728		.BitInsts16,
729		.FlatScratchInsts,
730		.SMemrealtime,
	722	.Dpp,
	723	.Localmemorysize65536,
731	724	.Vop3p,
732		.FlatInstOffsets,
	725	.BitInsts16,
	726	.VgprIndexMode,
	727	.Gfx8Insts,
733	728	.Inv2piInlineImm,
734		.Localmemorysize65536,
	729	.Gfx9Insts,
	730	.ScalarFlatScratchInsts,
	731	.FlatGlobalInsts,
	732	.FlatScratchInsts,
	733	.Fp64,
	734	.FastFmaf,
735	735	.Gfx9,
736	736	.Ldsbankcount32,
737	737	.MaiInsts,
...	...	@@ -739,322 +739,322 @@ pub const AmdGpuCpu = enum {
739	739	.PkFmacF16Inst,
740	740	.SramEcc,
741	741	.HalfRate64Ops,
742		},
743		CpuInfo(@This()).create(.Gfx909, "gfx909", &[_]FeatureType {
	742	}),
	743	CpuInfo(@This(), FeatureType).create(.Gfx909, "gfx909", &[_]FeatureType {
744	744	.CodeObjectV3,
745		.Gfx9Insts,
746		.Wavefrontsize64,
747		.Fp64,
748		.Gcn3Encoding,
749		.FastFmaf,
750		.Sdwa,
	745	.ApertureRegs,
	746	.IntClampInsts,
	747	.SdwaOmod,
751	748	.SdwaScalar,
752		.VgprIndexMode,
753		.Dpp,
754	749	.AddNoCarryInsts,
755		.SdwaOmod,
756		.SdwaSdst,
757	750	.ScalarAtomics,
	751	.SMemrealtime,
	752	.Gcn3Encoding,
	753	.CiInsts,
758	754	.FlatAddressSpace,
759		.ScalarFlatScratchInsts,
760		.Gfx8Insts,
	755	.Sdwa,
	756	.Wavefrontsize64,
	757	.SdwaSdst,
	758	.FlatInstOffsets,
	759	.ScalarStores,
761	760	.Gfx7Gfx8Gfx9Insts,
762	761	.R128A16,
763		.IntClampInsts,
764		.ScalarStores,
765		.ApertureRegs,
766		.CiInsts,
767		.FlatGlobalInsts,
768		.BitInsts16,
769		.FlatScratchInsts,
770		.SMemrealtime,
	762	.Dpp,
	763	.Localmemorysize65536,
771	764	.Vop3p,
772		.FlatInstOffsets,
	765	.BitInsts16,
	766	.VgprIndexMode,
	767	.Gfx8Insts,
773	768	.Inv2piInlineImm,
774		.Localmemorysize65536,
	769	.Gfx9Insts,
	770	.ScalarFlatScratchInsts,
	771	.FlatGlobalInsts,
	772	.FlatScratchInsts,
	773	.Fp64,
	774	.FastFmaf,
775	775	.Gfx9,
776	776	.Ldsbankcount32,
777	777	.MadMixInsts,
778	778	.Xnack,
779		},
780		CpuInfo(@This()).create(.Hainan, "hainan", &[_]FeatureType {
	779	}),
	780	CpuInfo(@This(), FeatureType).create(.Hainan, "hainan", &[_]FeatureType {
781	781	.CodeObjectV3,
782	782	.NoXnackSupport,
783	783	.Ldsbankcount32,
784		.Wavefrontsize64,
	784	.Movrel,
785	785	.MimgR128,
786	786	.Fp64,
787	787	.TrigReducedRange,
	788	.Wavefrontsize64,
788	789	.NoSramEccSupport,
789		.Movrel,
790	790	.Localmemorysize32768,
791	791	.SouthernIslands,
792		},
793		CpuInfo(@This()).create(.Hawaii, "hawaii", &[_]FeatureType {
	792	}),
	793	CpuInfo(@This(), FeatureType).create(.Hawaii, "hawaii", &[_]FeatureType {
794	794	.CodeObjectV3,
795	795	.NoXnackSupport,
796	796	.FastFmaf,
797	797	.Ldsbankcount32,
798		.Wavefrontsize64,
799		.MimgR128,
	798	.Movrel,
	799	.Gfx7Gfx8Gfx9Insts,
800	800	.Fp64,
	801	.TrigReducedRange,
801	802	.CiInsts,
802	803	.FlatAddressSpace,
803		.TrigReducedRange,
804		.NoSramEccSupport,
805		.Movrel,
806	804	.Localmemorysize65536,
807		.Gfx7Gfx8Gfx9Insts,
	805	.Wavefrontsize64,
	806	.NoSramEccSupport,
	807	.MimgR128,
808	808	.SeaIslands,
809	809	.HalfRate64Ops,
810		},
811		CpuInfo(@This()).create(.Iceland, "iceland", &[_]FeatureType {
	810	}),
	811	CpuInfo(@This(), FeatureType).create(.Iceland, "iceland", &[_]FeatureType {
812	812	.CodeObjectV3,
813	813	.NoXnackSupport,
814	814	.Ldsbankcount32,
815	815	.SgprInitBug,
816	816	.UnpackedD16Vmem,
817		.Wavefrontsize64,
818		.Fp64,
	817	.IntClampInsts,
	818	.SdwaMav,
	819	.Movrel,
	820	.SMemrealtime,
819	821	.Gcn3Encoding,
820	822	.TrigReducedRange,
821		.Sdwa,
822		.VgprIndexMode,
823		.Dpp,
	823	.CiInsts,
824	824	.FlatAddressSpace,
825		.Gfx8Insts,
826		.Gfx7Gfx8Gfx9Insts,
827		.MimgR128,
	825	.Sdwa,
	826	.Wavefrontsize64,
828	827	.NoSramEccSupport,
829		.IntClampInsts,
830	828	.ScalarStores,
831		.Movrel,
832		.SdwaMav,
833		.CiInsts,
	829	.Gfx7Gfx8Gfx9Insts,
	830	.Dpp,
	831	.Localmemorysize65536,
834	832	.BitInsts16,
835		.SMemrealtime,
	833	.VgprIndexMode,
	834	.Gfx8Insts,
836	835	.Inv2piInlineImm,
837		.Localmemorysize65536,
	836	.MimgR128,
838	837	.SdwaOutModsVopc,
	838	.Fp64,
839	839	.VolcanicIslands,
840		},
841		CpuInfo(@This()).create(.Kabini, "kabini", &[_]FeatureType {
	840	}),
	841	CpuInfo(@This(), FeatureType).create(.Kabini, "kabini", &[_]FeatureType {
842	842	.CodeObjectV3,
843	843	.NoXnackSupport,
844	844	.Ldsbankcount16,
845		.Wavefrontsize64,
846		.MimgR128,
	845	.Movrel,
	846	.Gfx7Gfx8Gfx9Insts,
847	847	.Fp64,
	848	.TrigReducedRange,
848	849	.CiInsts,
849	850	.FlatAddressSpace,
850		.TrigReducedRange,
851		.NoSramEccSupport,
852		.Movrel,
853	851	.Localmemorysize65536,
854		.Gfx7Gfx8Gfx9Insts,
	852	.Wavefrontsize64,
	853	.NoSramEccSupport,
	854	.MimgR128,
855	855	.SeaIslands,
856		},
857		CpuInfo(@This()).create(.Kaveri, "kaveri", &[_]FeatureType {
	856	}),
	857	CpuInfo(@This(), FeatureType).create(.Kaveri, "kaveri", &[_]FeatureType {
858	858	.CodeObjectV3,
859	859	.NoXnackSupport,
860	860	.Ldsbankcount32,
861		.Wavefrontsize64,
862		.MimgR128,
	861	.Movrel,
	862	.Gfx7Gfx8Gfx9Insts,
863	863	.Fp64,
	864	.TrigReducedRange,
864	865	.CiInsts,
865	866	.FlatAddressSpace,
866		.TrigReducedRange,
867		.NoSramEccSupport,
868		.Movrel,
869	867	.Localmemorysize65536,
870		.Gfx7Gfx8Gfx9Insts,
	868	.Wavefrontsize64,
	869	.NoSramEccSupport,
	870	.MimgR128,
871	871	.SeaIslands,
872		},
873		CpuInfo(@This()).create(.Mullins, "mullins", &[_]FeatureType {
	872	}),
	873	CpuInfo(@This(), FeatureType).create(.Mullins, "mullins", &[_]FeatureType {
874	874	.CodeObjectV3,
875	875	.NoXnackSupport,
876	876	.Ldsbankcount16,
877		.Wavefrontsize64,
878		.MimgR128,
	877	.Movrel,
	878	.Gfx7Gfx8Gfx9Insts,
879	879	.Fp64,
	880	.TrigReducedRange,
880	881	.CiInsts,
881	882	.FlatAddressSpace,
882		.TrigReducedRange,
883		.NoSramEccSupport,
884		.Movrel,
885	883	.Localmemorysize65536,
886		.Gfx7Gfx8Gfx9Insts,
	884	.Wavefrontsize64,
	885	.NoSramEccSupport,
	886	.MimgR128,
887	887	.SeaIslands,
888		},
889		CpuInfo(@This()).create(.Oland, "oland", &[_]FeatureType {
	888	}),
	889	CpuInfo(@This(), FeatureType).create(.Oland, "oland", &[_]FeatureType {
890	890	.CodeObjectV3,
891	891	.NoXnackSupport,
892	892	.Ldsbankcount32,
893		.Wavefrontsize64,
	893	.Movrel,
894	894	.MimgR128,
895	895	.Fp64,
896	896	.TrigReducedRange,
	897	.Wavefrontsize64,
897	898	.NoSramEccSupport,
898		.Movrel,
899	899	.Localmemorysize32768,
900	900	.SouthernIslands,
901		},
902		CpuInfo(@This()).create(.Pitcairn, "pitcairn", &[_]FeatureType {
	901	}),
	902	CpuInfo(@This(), FeatureType).create(.Pitcairn, "pitcairn", &[_]FeatureType {
903	903	.CodeObjectV3,
904	904	.NoXnackSupport,
905	905	.Ldsbankcount32,
906		.Wavefrontsize64,
	906	.Movrel,
907	907	.MimgR128,
908	908	.Fp64,
909	909	.TrigReducedRange,
	910	.Wavefrontsize64,
910	911	.NoSramEccSupport,
911		.Movrel,
912	912	.Localmemorysize32768,
913	913	.SouthernIslands,
914		},
915		CpuInfo(@This()).create(.Polaris10, "polaris10", &[_]FeatureType {
	914	}),
	915	CpuInfo(@This(), FeatureType).create(.Polaris10, "polaris10", &[_]FeatureType {
916	916	.CodeObjectV3,
917	917	.NoXnackSupport,
918	918	.Ldsbankcount32,
919	919	.UnpackedD16Vmem,
920		.Wavefrontsize64,
921		.Fp64,
	920	.IntClampInsts,
	921	.SdwaMav,
	922	.Movrel,
	923	.SMemrealtime,
922	924	.Gcn3Encoding,
923	925	.TrigReducedRange,
924		.Sdwa,
925		.VgprIndexMode,
926		.Dpp,
	926	.CiInsts,
927	927	.FlatAddressSpace,
928		.Gfx8Insts,
929		.Gfx7Gfx8Gfx9Insts,
930		.MimgR128,
	928	.Sdwa,
	929	.Wavefrontsize64,
931	930	.NoSramEccSupport,
932		.IntClampInsts,
933	931	.ScalarStores,
934		.Movrel,
935		.SdwaMav,
936		.CiInsts,
	932	.Gfx7Gfx8Gfx9Insts,
	933	.Dpp,
	934	.Localmemorysize65536,
937	935	.BitInsts16,
938		.SMemrealtime,
	936	.VgprIndexMode,
	937	.Gfx8Insts,
939	938	.Inv2piInlineImm,
940		.Localmemorysize65536,
	939	.MimgR128,
941	940	.SdwaOutModsVopc,
	941	.Fp64,
942	942	.VolcanicIslands,
943		},
944		CpuInfo(@This()).create(.Polaris11, "polaris11", &[_]FeatureType {
	943	}),
	944	CpuInfo(@This(), FeatureType).create(.Polaris11, "polaris11", &[_]FeatureType {
945	945	.CodeObjectV3,
946	946	.NoXnackSupport,
947	947	.Ldsbankcount32,
948	948	.UnpackedD16Vmem,
949		.Wavefrontsize64,
950		.Fp64,
	949	.IntClampInsts,
	950	.SdwaMav,
	951	.Movrel,
	952	.SMemrealtime,
951	953	.Gcn3Encoding,
952	954	.TrigReducedRange,
953		.Sdwa,
954		.VgprIndexMode,
955		.Dpp,
	955	.CiInsts,
956	956	.FlatAddressSpace,
957		.Gfx8Insts,
958		.Gfx7Gfx8Gfx9Insts,
959		.MimgR128,
	957	.Sdwa,
	958	.Wavefrontsize64,
960	959	.NoSramEccSupport,
961		.IntClampInsts,
962	960	.ScalarStores,
963		.Movrel,
964		.SdwaMav,
965		.CiInsts,
	961	.Gfx7Gfx8Gfx9Insts,
	962	.Dpp,
	963	.Localmemorysize65536,
966	964	.BitInsts16,
967		.SMemrealtime,
	965	.VgprIndexMode,
	966	.Gfx8Insts,
968	967	.Inv2piInlineImm,
969		.Localmemorysize65536,
	968	.MimgR128,
970	969	.SdwaOutModsVopc,
	970	.Fp64,
971	971	.VolcanicIslands,
972		},
973		CpuInfo(@This()).create(.Stoney, "stoney", &[_]FeatureType {
	972	}),
	973	CpuInfo(@This(), FeatureType).create(.Stoney, "stoney", &[_]FeatureType {
974	974	.CodeObjectV3,
975	975	.Ldsbankcount16,
976		.Wavefrontsize64,
977		.Fp64,
	976	.IntClampInsts,
	977	.SdwaMav,
	978	.Movrel,
	979	.SMemrealtime,
978	980	.Gcn3Encoding,
979	981	.TrigReducedRange,
980		.Sdwa,
981		.VgprIndexMode,
982		.Dpp,
	982	.CiInsts,
983	983	.FlatAddressSpace,
984		.Gfx8Insts,
985		.Gfx7Gfx8Gfx9Insts,
986		.MimgR128,
	984	.Sdwa,
	985	.Wavefrontsize64,
987	986	.NoSramEccSupport,
988		.IntClampInsts,
989	987	.ScalarStores,
990		.Movrel,
991		.SdwaMav,
992		.CiInsts,
	988	.Gfx7Gfx8Gfx9Insts,
	989	.Dpp,
	990	.Localmemorysize65536,
993	991	.BitInsts16,
994		.SMemrealtime,
	992	.VgprIndexMode,
	993	.Gfx8Insts,
995	994	.Inv2piInlineImm,
996		.Localmemorysize65536,
	995	.MimgR128,
997	996	.SdwaOutModsVopc,
	997	.Fp64,
998	998	.VolcanicIslands,
999	999	.Xnack,
1000		},
1001		CpuInfo(@This()).create(.Tahiti, "tahiti", &[_]FeatureType {
	1000	}),
	1001	CpuInfo(@This(), FeatureType).create(.Tahiti, "tahiti", &[_]FeatureType {
1002	1002	.CodeObjectV3,
1003	1003	.NoXnackSupport,
1004	1004	.FastFmaf,
1005	1005	.Ldsbankcount32,
1006		.Wavefrontsize64,
	1006	.Movrel,
1007	1007	.MimgR128,
1008	1008	.Fp64,
1009	1009	.TrigReducedRange,
	1010	.Wavefrontsize64,
1010	1011	.NoSramEccSupport,
1011		.Movrel,
1012	1012	.Localmemorysize32768,
1013	1013	.SouthernIslands,
1014	1014	.HalfRate64Ops,
1015		},
1016		CpuInfo(@This()).create(.Tonga, "tonga", &[_]FeatureType {
	1015	}),
	1016	CpuInfo(@This(), FeatureType).create(.Tonga, "tonga", &[_]FeatureType {
1017	1017	.CodeObjectV3,
1018	1018	.NoXnackSupport,
1019	1019	.Ldsbankcount32,
1020	1020	.SgprInitBug,
1021	1021	.UnpackedD16Vmem,
1022		.Wavefrontsize64,
1023		.Fp64,
	1022	.IntClampInsts,
	1023	.SdwaMav,
	1024	.Movrel,
	1025	.SMemrealtime,
1024	1026	.Gcn3Encoding,
1025	1027	.TrigReducedRange,
1026		.Sdwa,
1027		.VgprIndexMode,
1028		.Dpp,
	1028	.CiInsts,
1029	1029	.FlatAddressSpace,
1030		.Gfx8Insts,
1031		.Gfx7Gfx8Gfx9Insts,
1032		.MimgR128,
	1030	.Sdwa,
	1031	.Wavefrontsize64,
1033	1032	.NoSramEccSupport,
1034		.IntClampInsts,
1035	1033	.ScalarStores,
1036		.Movrel,
1037		.SdwaMav,
1038		.CiInsts,
	1034	.Gfx7Gfx8Gfx9Insts,
	1035	.Dpp,
	1036	.Localmemorysize65536,
1039	1037	.BitInsts16,
1040		.SMemrealtime,
	1038	.VgprIndexMode,
	1039	.Gfx8Insts,
1041	1040	.Inv2piInlineImm,
1042		.Localmemorysize65536,
	1041	.MimgR128,
1043	1042	.SdwaOutModsVopc,
	1043	.Fp64,
1044	1044	.VolcanicIslands,
1045		},
1046		CpuInfo(@This()).create(.Verde, "verde", &[_]FeatureType {
	1045	}),
	1046	CpuInfo(@This(), FeatureType).create(.Verde, "verde", &[_]FeatureType {
1047	1047	.CodeObjectV3,
1048	1048	.NoXnackSupport,
1049	1049	.Ldsbankcount32,
1050		.Wavefrontsize64,
	1050	.Movrel,
1051	1051	.MimgR128,
1052	1052	.Fp64,
1053	1053	.TrigReducedRange,
	1054	.Wavefrontsize64,
1054	1055	.NoSramEccSupport,
1055		.Movrel,
1056	1056	.Localmemorysize32768,
1057	1057	.SouthernIslands,
1058		},
	1058	}),
1059	1059	};
1060	1060	};

lib/std/target/cpu/ArmCpu.zig+509-509

...	...	@@ -86,154 +86,154 @@ pub const ArmCpu = enum {
86	86	Swift,
87	87	Xscale,
88	88
89		pub fn getInfo(self: @This()) CpuInfo {
	89	const FeatureType = feature.ArmFeature;
	90
	91	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
90	92	return cpu_infos[@enumToInt(self)];
91	93	}
92	94
93		pub const FeatureType = feature.ArmFeature;
94
95		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
96		CpuInfo(@This()).create(.Arm1020e, "arm1020e", &[_]FeatureType {
	95	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	96	CpuInfo(@This(), FeatureType).create(.Arm1020e, "arm1020e", &[_]FeatureType {
97	97	.V4t,
98	98	.Armv5te,
99		},
100		CpuInfo(@This()).create(.Arm1020t, "arm1020t", &[_]FeatureType {
	99	}),
	100	CpuInfo(@This(), FeatureType).create(.Arm1020t, "arm1020t", &[_]FeatureType {
101	101	.V4t,
102	102	.Armv5t,
103		},
104		CpuInfo(@This()).create(.Arm1022e, "arm1022e", &[_]FeatureType {
	103	}),
	104	CpuInfo(@This(), FeatureType).create(.Arm1022e, "arm1022e", &[_]FeatureType {
105	105	.V4t,
106	106	.Armv5te,
107		},
108		CpuInfo(@This()).create(.Arm10e, "arm10e", &[_]FeatureType {
	107	}),
	108	CpuInfo(@This(), FeatureType).create(.Arm10e, "arm10e", &[_]FeatureType {
109	109	.V4t,
110	110	.Armv5te,
111		},
112		CpuInfo(@This()).create(.Arm10tdmi, "arm10tdmi", &[_]FeatureType {
	111	}),
	112	CpuInfo(@This(), FeatureType).create(.Arm10tdmi, "arm10tdmi", &[_]FeatureType {
113	113	.V4t,
114	114	.Armv5t,
115		},
116		CpuInfo(@This()).create(.Arm1136jS, "arm1136j-s", &[_]FeatureType {
	115	}),
	116	CpuInfo(@This(), FeatureType).create(.Arm1136jS, "arm1136j-s", &[_]FeatureType {
117	117	.V4t,
118	118	.Dsp,
119	119	.Armv6,
120		},
121		CpuInfo(@This()).create(.Arm1136jfS, "arm1136jf-s", &[_]FeatureType {
	120	}),
	121	CpuInfo(@This(), FeatureType).create(.Arm1136jfS, "arm1136jf-s", &[_]FeatureType {
122	122	.V4t,
123	123	.Dsp,
124	124	.Armv6,
125	125	.Slowfpvmlx,
126	126	.Fpregs,
127	127	.Vfp2,
128		},
129		CpuInfo(@This()).create(.Arm1156t2S, "arm1156t2-s", &[_]FeatureType {
130		.Thumb2,
	128	}),
	129	CpuInfo(@This(), FeatureType).create(.Arm1156t2S, "arm1156t2-s", &[_]FeatureType {
131	130	.V4t,
	131	.Thumb2,
132	132	.Dsp,
133	133	.Armv6t2,
134		},
135		CpuInfo(@This()).create(.Arm1156t2fS, "arm1156t2f-s", &[_]FeatureType {
136		.Thumb2,
	134	}),
	135	CpuInfo(@This(), FeatureType).create(.Arm1156t2fS, "arm1156t2f-s", &[_]FeatureType {
137	136	.V4t,
	137	.Thumb2,
138	138	.Dsp,
139	139	.Armv6t2,
140	140	.Slowfpvmlx,
141	141	.Fpregs,
142	142	.Vfp2,
143		},
144		CpuInfo(@This()).create(.Arm1176jS, "arm1176j-s", &[_]FeatureType {
	143	}),
	144	CpuInfo(@This(), FeatureType).create(.Arm1176jS, "arm1176j-s", &[_]FeatureType {
145	145	.V4t,
146	146	.Trustzone,
147	147	.Armv6kz,
148		},
149		CpuInfo(@This()).create(.Arm1176jzS, "arm1176jz-s", &[_]FeatureType {
	148	}),
	149	CpuInfo(@This(), FeatureType).create(.Arm1176jzS, "arm1176jz-s", &[_]FeatureType {
150	150	.V4t,
151	151	.Trustzone,
152	152	.Armv6kz,
153		},
154		CpuInfo(@This()).create(.Arm1176jzfS, "arm1176jzf-s", &[_]FeatureType {
	153	}),
	154	CpuInfo(@This(), FeatureType).create(.Arm1176jzfS, "arm1176jzf-s", &[_]FeatureType {
155	155	.V4t,
156	156	.Trustzone,
157	157	.Armv6kz,
158	158	.Slowfpvmlx,
159	159	.Fpregs,
160	160	.Vfp2,
161		},
162		CpuInfo(@This()).create(.Arm710t, "arm710t", &[_]FeatureType {
	161	}),
	162	CpuInfo(@This(), FeatureType).create(.Arm710t, "arm710t", &[_]FeatureType {
163	163	.V4t,
164	164	.Armv4t,
165		},
166		CpuInfo(@This()).create(.Arm720t, "arm720t", &[_]FeatureType {
	165	}),
	166	CpuInfo(@This(), FeatureType).create(.Arm720t, "arm720t", &[_]FeatureType {
167	167	.V4t,
168	168	.Armv4t,
169		},
170		CpuInfo(@This()).create(.Arm7tdmi, "arm7tdmi", &[_]FeatureType {
	169	}),
	170	CpuInfo(@This(), FeatureType).create(.Arm7tdmi, "arm7tdmi", &[_]FeatureType {
171	171	.V4t,
172	172	.Armv4t,
173		},
174		CpuInfo(@This()).create(.Arm7tdmiS, "arm7tdmi-s", &[_]FeatureType {
	173	}),
	174	CpuInfo(@This(), FeatureType).create(.Arm7tdmiS, "arm7tdmi-s", &[_]FeatureType {
175	175	.V4t,
176	176	.Armv4t,
177		},
178		CpuInfo(@This()).create(.Arm8, "arm8", &[_]FeatureType {
	177	}),
	178	CpuInfo(@This(), FeatureType).create(.Arm8, "arm8", &[_]FeatureType {
179	179	.Armv4,
180		},
181		CpuInfo(@This()).create(.Arm810, "arm810", &[_]FeatureType {
	180	}),
	181	CpuInfo(@This(), FeatureType).create(.Arm810, "arm810", &[_]FeatureType {
182	182	.Armv4,
183		},
184		CpuInfo(@This()).create(.Arm9, "arm9", &[_]FeatureType {
	183	}),
	184	CpuInfo(@This(), FeatureType).create(.Arm9, "arm9", &[_]FeatureType {
185	185	.V4t,
186	186	.Armv4t,
187		},
188		CpuInfo(@This()).create(.Arm920, "arm920", &[_]FeatureType {
	187	}),
	188	CpuInfo(@This(), FeatureType).create(.Arm920, "arm920", &[_]FeatureType {
189	189	.V4t,
190	190	.Armv4t,
191		},
192		CpuInfo(@This()).create(.Arm920t, "arm920t", &[_]FeatureType {
	191	}),
	192	CpuInfo(@This(), FeatureType).create(.Arm920t, "arm920t", &[_]FeatureType {
193	193	.V4t,
194	194	.Armv4t,
195		},
196		CpuInfo(@This()).create(.Arm922t, "arm922t", &[_]FeatureType {
	195	}),
	196	CpuInfo(@This(), FeatureType).create(.Arm922t, "arm922t", &[_]FeatureType {
197	197	.V4t,
198	198	.Armv4t,
199		},
200		CpuInfo(@This()).create(.Arm926ejS, "arm926ej-s", &[_]FeatureType {
	199	}),
	200	CpuInfo(@This(), FeatureType).create(.Arm926ejS, "arm926ej-s", &[_]FeatureType {
201	201	.V4t,
202	202	.Armv5te,
203		},
204		CpuInfo(@This()).create(.Arm940t, "arm940t", &[_]FeatureType {
	203	}),
	204	CpuInfo(@This(), FeatureType).create(.Arm940t, "arm940t", &[_]FeatureType {
205	205	.V4t,
206	206	.Armv4t,
207		},
208		CpuInfo(@This()).create(.Arm946eS, "arm946e-s", &[_]FeatureType {
	207	}),
	208	CpuInfo(@This(), FeatureType).create(.Arm946eS, "arm946e-s", &[_]FeatureType {
209	209	.V4t,
210	210	.Armv5te,
211		},
212		CpuInfo(@This()).create(.Arm966eS, "arm966e-s", &[_]FeatureType {
	211	}),
	212	CpuInfo(@This(), FeatureType).create(.Arm966eS, "arm966e-s", &[_]FeatureType {
213	213	.V4t,
214	214	.Armv5te,
215		},
216		CpuInfo(@This()).create(.Arm968eS, "arm968e-s", &[_]FeatureType {
	215	}),
	216	CpuInfo(@This(), FeatureType).create(.Arm968eS, "arm968e-s", &[_]FeatureType {
217	217	.V4t,
218	218	.Armv5te,
219		},
220		CpuInfo(@This()).create(.Arm9e, "arm9e", &[_]FeatureType {
	219	}),
	220	CpuInfo(@This(), FeatureType).create(.Arm9e, "arm9e", &[_]FeatureType {
221	221	.V4t,
222	222	.Armv5te,
223		},
224		CpuInfo(@This()).create(.Arm9tdmi, "arm9tdmi", &[_]FeatureType {
	223	}),
	224	CpuInfo(@This(), FeatureType).create(.Arm9tdmi, "arm9tdmi", &[_]FeatureType {
225	225	.V4t,
226	226	.Armv4t,
227		},
228		CpuInfo(@This()).create(.CortexA12, "cortex-a12", &[_]FeatureType {
229		.Thumb2,
	227	}),
	228	CpuInfo(@This(), FeatureType).create(.CortexA12, "cortex-a12", &[_]FeatureType {
230	229	.Perfmon,
231		.Db,
232		.Dsp,
233		.V7clrex,
234	230	.V4t,
235		.Fpregs,
236	231	.D32,
	232	.Fpregs,
	233	.V7clrex,
	234	.Dsp,
	235	.Thumb2,
	236	.Db,
237	237	.Aclass,
238	238	.Armv7A,
239	239	.AvoidPartialCpsr,
...	...	@@ -247,16 +247,16 @@ pub const ArmCpu = enum {
247	247	.Hwdiv,
248	248	.Virtualization,
249	249	.A12,
250		},
251		CpuInfo(@This()).create(.CortexA15, "cortex-a15", &[_]FeatureType {
252		.Thumb2,
	250	}),
	251	CpuInfo(@This(), FeatureType).create(.CortexA15, "cortex-a15", &[_]FeatureType {
253	252	.Perfmon,
254		.Db,
255		.Dsp,
256		.V7clrex,
257	253	.V4t,
258		.Fpregs,
259	254	.D32,
	255	.Fpregs,
	256	.V7clrex,
	257	.Dsp,
	258	.Thumb2,
	259	.Db,
260	260	.Aclass,
261	261	.Armv7A,
262	262	.AvoidPartialCpsr,
...	...	@@ -273,16 +273,16 @@ pub const ArmCpu = enum {
273	273	.Hwdiv,
274	274	.Virtualization,
275	275	.A15,
276		},
277		CpuInfo(@This()).create(.CortexA17, "cortex-a17", &[_]FeatureType {
278		.Thumb2,
	276	}),
	277	CpuInfo(@This(), FeatureType).create(.CortexA17, "cortex-a17", &[_]FeatureType {
279	278	.Perfmon,
280		.Db,
281		.Dsp,
282		.V7clrex,
283	279	.V4t,
284		.Fpregs,
285	280	.D32,
	281	.Fpregs,
	282	.V7clrex,
	283	.Dsp,
	284	.Thumb2,
	285	.Db,
286	286	.Aclass,
287	287	.Armv7A,
288	288	.AvoidPartialCpsr,
...	...	@@ -296,57 +296,57 @@ pub const ArmCpu = enum {
296	296	.Hwdiv,
297	297	.Virtualization,
298	298	.A17,
299		},
300		CpuInfo(@This()).create(.CortexA32, "cortex-a32", &[_]FeatureType {
301		.Thumb2,
302		.Mp,
	299	}),
	300	CpuInfo(@This(), FeatureType).create(.CortexA32, "cortex-a32", &[_]FeatureType {
	301	.HwdivArm,
303	302	.Perfmon,
304		.Db,
	303	.D32,
	304	.Fpregs,
305	305	.Crc,
	306	.Mp,
306	307	.Fp16,
307	308	.Dsp,
308		.V7clrex,
309	309	.V4t,
310		.Fpregs,
311		.D32,
312		.Hwdiv,
313		.HwdivArm,
	310	.V7clrex,
	311	.Db,
314	312	.Aclass,
315		.Trustzone,
	313	.Thumb2,
316	314	.AcquireRelease,
	315	.Hwdiv,
	316	.Trustzone,
317	317	.Armv8A,
318	318	.Crypto,
319		},
320		CpuInfo(@This()).create(.CortexA35, "cortex-a35", &[_]FeatureType {
321		.Thumb2,
322		.Mp,
	319	}),
	320	CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
	321	.HwdivArm,
323	322	.Perfmon,
324		.Db,
	323	.D32,
	324	.Fpregs,
325	325	.Crc,
	326	.Mp,
326	327	.Fp16,
327	328	.Dsp,
328		.V7clrex,
329	329	.V4t,
330		.Fpregs,
331		.D32,
332		.Hwdiv,
333		.HwdivArm,
	330	.V7clrex,
	331	.Db,
334	332	.Aclass,
335		.Trustzone,
	333	.Thumb2,
336	334	.AcquireRelease,
	335	.Hwdiv,
	336	.Trustzone,
337	337	.Armv8A,
338	338	.Crypto,
339	339	.A35,
340		},
341		CpuInfo(@This()).create(.CortexA5, "cortex-a5", &[_]FeatureType {
342		.Thumb2,
	340	}),
	341	CpuInfo(@This(), FeatureType).create(.CortexA5, "cortex-a5", &[_]FeatureType {
343	342	.Perfmon,
344		.Db,
345		.Dsp,
346		.V7clrex,
347	343	.V4t,
348		.Fpregs,
349	344	.D32,
	345	.Fpregs,
	346	.V7clrex,
	347	.Dsp,
	348	.Thumb2,
	349	.Db,
350	350	.Aclass,
351	351	.Armv7A,
352	352	.RetAddrStack,
...	...	@@ -358,84 +358,84 @@ pub const ArmCpu = enum {
358	358	.Vfp4,
359	359	.VmlxForwarding,
360	360	.A5,
361		},
362		CpuInfo(@This()).create(.CortexA53, "cortex-a53", &[_]FeatureType {
363		.Thumb2,
364		.Mp,
	361	}),
	362	CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
	363	.HwdivArm,
365	364	.Perfmon,
366		.Db,
	365	.D32,
	366	.Fpregs,
367	367	.Crc,
	368	.Mp,
368	369	.Fp16,
369	370	.Dsp,
370		.V7clrex,
371	371	.V4t,
372		.Fpregs,
373		.D32,
374		.Hwdiv,
375		.HwdivArm,
	372	.V7clrex,
	373	.Db,
376	374	.Aclass,
377		.Trustzone,
	375	.Thumb2,
378	376	.AcquireRelease,
	377	.Hwdiv,
	378	.Trustzone,
379	379	.Armv8A,
380	380	.Crypto,
381	381	.Fpao,
382	382	.A53,
383		},
384		CpuInfo(@This()).create(.CortexA55, "cortex-a55", &[_]FeatureType {
385		.Thumb2,
386		.Mp,
	383	}),
	384	CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
	385	.HwdivArm,
387	386	.Perfmon,
388		.Db,
	387	.D32,
	388	.Fpregs,
389	389	.Crc,
	390	.Mp,
390	391	.Fp16,
391		.Ras,
392	392	.Dsp,
393		.V7clrex,
394	393	.V4t,
395		.Fpregs,
396		.D32,
397		.Hwdiv,
398		.HwdivArm,
	394	.V7clrex,
	395	.Db,
399	396	.Aclass,
400		.Trustzone,
	397	.Thumb2,
	398	.Ras,
401	399	.AcquireRelease,
	400	.Hwdiv,
	401	.Trustzone,
402	402	.Armv82A,
403	403	.Dotprod,
404	404	.A55,
405		},
406		CpuInfo(@This()).create(.CortexA57, "cortex-a57", &[_]FeatureType {
407		.Thumb2,
408		.Mp,
	405	}),
	406	CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
	407	.HwdivArm,
409	408	.Perfmon,
410		.Db,
	409	.D32,
	410	.Fpregs,
411	411	.Crc,
	412	.Mp,
412	413	.Fp16,
413	414	.Dsp,
414		.V7clrex,
415	415	.V4t,
416		.Fpregs,
417		.D32,
418		.Hwdiv,
419		.HwdivArm,
	416	.V7clrex,
	417	.Db,
420	418	.Aclass,
421		.Trustzone,
	419	.Thumb2,
422	420	.AcquireRelease,
	421	.Hwdiv,
	422	.Trustzone,
423	423	.Armv8A,
424	424	.AvoidPartialCpsr,
425	425	.CheapPredicableCpsr,
426	426	.Crypto,
427	427	.Fpao,
428	428	.A57,
429		},
430		CpuInfo(@This()).create(.CortexA7, "cortex-a7", &[_]FeatureType {
431		.Thumb2,
	429	}),
	430	CpuInfo(@This(), FeatureType).create(.CortexA7, "cortex-a7", &[_]FeatureType {
432	431	.Perfmon,
433		.Db,
434		.Dsp,
435		.V7clrex,
436	432	.V4t,
437		.Fpregs,
438	433	.D32,
	434	.Fpregs,
	435	.V7clrex,
	436	.Dsp,
	437	.Thumb2,
	438	.Db,
439	439	.Aclass,
440	440	.Armv7A,
441	441	.RetAddrStack,
...	...	@@ -451,128 +451,128 @@ pub const ArmCpu = enum {
451	451	.Hwdiv,
452	452	.Virtualization,
453	453	.A7,
454		},
455		CpuInfo(@This()).create(.CortexA72, "cortex-a72", &[_]FeatureType {
456		.Thumb2,
457		.Mp,
	454	}),
	455	CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
	456	.HwdivArm,
458	457	.Perfmon,
459		.Db,
	458	.D32,
	459	.Fpregs,
460	460	.Crc,
	461	.Mp,
461	462	.Fp16,
462	463	.Dsp,
463		.V7clrex,
464	464	.V4t,
465		.Fpregs,
466		.D32,
467		.Hwdiv,
468		.HwdivArm,
	465	.V7clrex,
	466	.Db,
469	467	.Aclass,
470		.Trustzone,
	468	.Thumb2,
471	469	.AcquireRelease,
	470	.Hwdiv,
	471	.Trustzone,
472	472	.Armv8A,
473	473	.Crypto,
474	474	.A72,
475		},
476		CpuInfo(@This()).create(.CortexA73, "cortex-a73", &[_]FeatureType {
477		.Thumb2,
478		.Mp,
	475	}),
	476	CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
	477	.HwdivArm,
479	478	.Perfmon,
480		.Db,
	479	.D32,
	480	.Fpregs,
481	481	.Crc,
	482	.Mp,
482	483	.Fp16,
483	484	.Dsp,
484		.V7clrex,
485	485	.V4t,
486		.Fpregs,
487		.D32,
488		.Hwdiv,
489		.HwdivArm,
	486	.V7clrex,
	487	.Db,
490	488	.Aclass,
491		.Trustzone,
	489	.Thumb2,
492	490	.AcquireRelease,
	491	.Hwdiv,
	492	.Trustzone,
493	493	.Armv8A,
494	494	.Crypto,
495	495	.A73,
496		},
497		CpuInfo(@This()).create(.CortexA75, "cortex-a75", &[_]FeatureType {
498		.Thumb2,
499		.Mp,
	496	}),
	497	CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
	498	.HwdivArm,
500	499	.Perfmon,
501		.Db,
	500	.D32,
	501	.Fpregs,
502	502	.Crc,
	503	.Mp,
503	504	.Fp16,
504		.Ras,
505	505	.Dsp,
506		.V7clrex,
507	506	.V4t,
508		.Fpregs,
509		.D32,
510		.Hwdiv,
511		.HwdivArm,
	507	.V7clrex,
	508	.Db,
512	509	.Aclass,
513		.Trustzone,
	510	.Thumb2,
	511	.Ras,
514	512	.AcquireRelease,
	513	.Hwdiv,
	514	.Trustzone,
515	515	.Armv82A,
516	516	.Dotprod,
517	517	.A75,
518		},
519		CpuInfo(@This()).create(.CortexA76, "cortex-a76", &[_]FeatureType {
520		.Thumb2,
521		.Mp,
	518	}),
	519	CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
	520	.HwdivArm,
522	521	.Perfmon,
523		.Db,
	522	.D32,
	523	.Fpregs,
524	524	.Crc,
	525	.Mp,
525	526	.Fp16,
526		.Ras,
527	527	.Dsp,
528		.V7clrex,
529	528	.V4t,
530		.Fpregs,
531		.D32,
532		.Hwdiv,
533		.HwdivArm,
	529	.V7clrex,
	530	.Db,
534	531	.Aclass,
535		.Trustzone,
	532	.Thumb2,
	533	.Ras,
536	534	.AcquireRelease,
	535	.Hwdiv,
	536	.Trustzone,
537	537	.Armv82A,
538	538	.Crypto,
539	539	.Dotprod,
540	540	.Fullfp16,
541	541	.A76,
542		},
543		CpuInfo(@This()).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
544		.Thumb2,
545		.Mp,
	542	}),
	543	CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
	544	.HwdivArm,
546	545	.Perfmon,
547		.Db,
	546	.D32,
	547	.Fpregs,
548	548	.Crc,
	549	.Mp,
549	550	.Fp16,
550		.Ras,
551	551	.Dsp,
552		.V7clrex,
553	552	.V4t,
554		.Fpregs,
555		.D32,
556		.Hwdiv,
557		.HwdivArm,
	553	.V7clrex,
	554	.Db,
558	555	.Aclass,
559		.Trustzone,
	556	.Thumb2,
	557	.Ras,
560	558	.AcquireRelease,
	559	.Hwdiv,
	560	.Trustzone,
561	561	.Armv82A,
562	562	.Crypto,
563	563	.Dotprod,
564	564	.Fullfp16,
565	565	.A76,
566		},
567		CpuInfo(@This()).create(.CortexA8, "cortex-a8", &[_]FeatureType {
568		.Thumb2,
	566	}),
	567	CpuInfo(@This(), FeatureType).create(.CortexA8, "cortex-a8", &[_]FeatureType {
569	568	.Perfmon,
570		.Db,
571		.Dsp,
572		.V7clrex,
573	569	.V4t,
574		.Fpregs,
575	570	.D32,
	571	.Fpregs,
	572	.V7clrex,
	573	.Dsp,
	574	.Thumb2,
	575	.Db,
576	576	.Aclass,
577	577	.Armv7A,
578	578	.RetAddrStack,
...	...	@@ -583,16 +583,16 @@ pub const ArmCpu = enum {
583	583	.Trustzone,
584	584	.VmlxForwarding,
585	585	.A8,
586		},
587		CpuInfo(@This()).create(.CortexA9, "cortex-a9", &[_]FeatureType {
588		.Thumb2,
	586	}),
	587	CpuInfo(@This(), FeatureType).create(.CortexA9, "cortex-a9", &[_]FeatureType {
589	588	.Perfmon,
590		.Db,
591		.Dsp,
592		.V7clrex,
593	589	.V4t,
594		.Fpregs,
595	590	.D32,
	591	.Fpregs,
	592	.V7clrex,
	593	.Dsp,
	594	.Thumb2,
	595	.Db,
596	596	.Aclass,
597	597	.Armv7A,
598	598	.AvoidPartialCpsr,
...	...	@@ -608,171 +608,171 @@ pub const ArmCpu = enum {
608	608	.Trustzone,
609	609	.VmlxForwarding,
610	610	.A9,
611		},
612		CpuInfo(@This()).create(.CortexM0, "cortex-m0", &[_]FeatureType {
613		.Mclass,
614		.StrictAlign,
	611	}),
	612	CpuInfo(@This(), FeatureType).create(.CortexM0, "cortex-m0", &[_]FeatureType {
	613	.V4t,
615	614	.ThumbMode,
616	615	.Db,
617		.V4t,
	616	.StrictAlign,
	617	.Mclass,
618	618	.Noarm,
619	619	.Armv6M,
620		},
621		CpuInfo(@This()).create(.CortexM0plus, "cortex-m0plus", &[_]FeatureType {
622		.Mclass,
623		.StrictAlign,
	620	}),
	621	CpuInfo(@This(), FeatureType).create(.CortexM0plus, "cortex-m0plus", &[_]FeatureType {
	622	.V4t,
624	623	.ThumbMode,
625	624	.Db,
626		.V4t,
	625	.StrictAlign,
	626	.Mclass,
627	627	.Noarm,
628	628	.Armv6M,
629		},
630		CpuInfo(@This()).create(.CortexM1, "cortex-m1", &[_]FeatureType {
631		.Mclass,
632		.StrictAlign,
	629	}),
	630	CpuInfo(@This(), FeatureType).create(.CortexM1, "cortex-m1", &[_]FeatureType {
	631	.V4t,
633	632	.ThumbMode,
634	633	.Db,
635		.V4t,
	634	.StrictAlign,
	635	.Mclass,
636	636	.Noarm,
637	637	.Armv6M,
638		},
639		CpuInfo(@This()).create(.CortexM23, "cortex-m23", &[_]FeatureType {
640		.Mclass,
641		.StrictAlign,
	638	}),
	639	CpuInfo(@This(), FeatureType).create(.CortexM23, "cortex-m23", &[_]FeatureType {
	640	.V4t,
642	641	.ThumbMode,
643		.Db,
644	642	.Msecext8,
645	643	.V7clrex,
646		.V4t,
647		.Hwdiv,
	644	.Db,
	645	.StrictAlign,
	646	.Mclass,
648	647	.Noarm,
649	648	.AcquireRelease,
	649	.Hwdiv,
650	650	.Armv8Mbase,
651	651	.NoMovt,
652		},
653		CpuInfo(@This()).create(.CortexM3, "cortex-m3", &[_]FeatureType {
654		.Thumb2,
655		.Mclass,
	652	}),
	653	CpuInfo(@This(), FeatureType).create(.CortexM3, "cortex-m3", &[_]FeatureType {
656	654	.Perfmon,
	655	.V4t,
657	656	.ThumbMode,
658		.Db,
659	657	.V7clrex,
660		.V4t,
661		.Hwdiv,
	658	.Thumb2,
	659	.Db,
	660	.Mclass,
662	661	.Noarm,
	662	.Hwdiv,
663	663	.Armv7M,
664	664	.NoBranchPredictor,
665	665	.LoopAlign,
666	666	.UseAa,
667	667	.UseMisched,
668	668	.M3,
669		},
670		CpuInfo(@This()).create(.CortexM33, "cortex-m33", &[_]FeatureType {
671		.Thumb2,
672		.Mclass,
	669	}),
	670	CpuInfo(@This(), FeatureType).create(.CortexM33, "cortex-m33", &[_]FeatureType {
673	671	.Perfmon,
	672	.V4t,
674	673	.ThumbMode,
675		.Db,
676	674	.Msecext8,
677	675	.V7clrex,
678		.V4t,
679		.Hwdiv,
	676	.Thumb2,
	677	.Db,
	678	.Mclass,
680	679	.Noarm,
681	680	.AcquireRelease,
	681	.Hwdiv,
682	682	.Armv8Mmain,
683	683	.Dsp,
684		.Fp16,
685	684	.Fpregs,
	685	.Fp16,
686	686	.FpArmv8d16sp,
687	687	.NoBranchPredictor,
688	688	.Slowfpvmlx,
689	689	.LoopAlign,
690	690	.UseAa,
691	691	.UseMisched,
692		},
693		CpuInfo(@This()).create(.CortexM35p, "cortex-m35p", &[_]FeatureType {
694		.Thumb2,
695		.Mclass,
	692	}),
	693	CpuInfo(@This(), FeatureType).create(.CortexM35p, "cortex-m35p", &[_]FeatureType {
696	694	.Perfmon,
	695	.V4t,
697	696	.ThumbMode,
698		.Db,
699	697	.Msecext8,
700	698	.V7clrex,
701		.V4t,
702		.Hwdiv,
	699	.Thumb2,
	700	.Db,
	701	.Mclass,
703	702	.Noarm,
704	703	.AcquireRelease,
	704	.Hwdiv,
705	705	.Armv8Mmain,
706	706	.Dsp,
707		.Fp16,
708	707	.Fpregs,
	708	.Fp16,
709	709	.FpArmv8d16sp,
710	710	.NoBranchPredictor,
711	711	.Slowfpvmlx,
712	712	.LoopAlign,
713	713	.UseAa,
714	714	.UseMisched,
715		},
716		CpuInfo(@This()).create(.CortexM4, "cortex-m4", &[_]FeatureType {
717		.Thumb2,
718		.Mclass,
	715	}),
	716	CpuInfo(@This(), FeatureType).create(.CortexM4, "cortex-m4", &[_]FeatureType {
719	717	.Perfmon,
	718	.V4t,
720	719	.ThumbMode,
721		.Db,
722		.Dsp,
723	720	.V7clrex,
724		.V4t,
725		.Hwdiv,
	721	.Dsp,
	722	.Thumb2,
	723	.Db,
	724	.Mclass,
726	725	.Noarm,
	726	.Hwdiv,
727	727	.Armv7eM,
728	728	.NoBranchPredictor,
729	729	.Slowfpvmlx,
730	730	.LoopAlign,
731	731	.UseAa,
732	732	.UseMisched,
733		.Fp16,
734	733	.Fpregs,
	734	.Fp16,
735	735	.Vfp4d16sp,
736		},
737		CpuInfo(@This()).create(.CortexM7, "cortex-m7", &[_]FeatureType {
738		.Thumb2,
739		.Mclass,
	736	}),
	737	CpuInfo(@This(), FeatureType).create(.CortexM7, "cortex-m7", &[_]FeatureType {
740	738	.Perfmon,
	739	.V4t,
741	740	.ThumbMode,
742		.Db,
743		.Dsp,
744	741	.V7clrex,
745		.V4t,
746		.Hwdiv,
	742	.Dsp,
	743	.Thumb2,
	744	.Db,
	745	.Mclass,
747	746	.Noarm,
	747	.Hwdiv,
748	748	.Armv7eM,
749		.Fp16,
750	749	.Fpregs,
	750	.Fp16,
751	751	.FpArmv8d16,
752		},
753		CpuInfo(@This()).create(.CortexR4, "cortex-r4", &[_]FeatureType {
754		.Thumb2,
	752	}),
	753	CpuInfo(@This(), FeatureType).create(.CortexR4, "cortex-r4", &[_]FeatureType {
755	754	.Perfmon,
756		.Db,
757		.Dsp,
758		.Rclass,
759		.V7clrex,
760	755	.V4t,
	756	.V7clrex,
	757	.Dsp,
	758	.Thumb2,
	759	.Db,
761	760	.Hwdiv,
	761	.Rclass,
762	762	.Armv7R,
763	763	.AvoidPartialCpsr,
764	764	.RetAddrStack,
765	765	.R4,
766		},
767		CpuInfo(@This()).create(.CortexR4f, "cortex-r4f", &[_]FeatureType {
768		.Thumb2,
	766	}),
	767	CpuInfo(@This(), FeatureType).create(.CortexR4f, "cortex-r4f", &[_]FeatureType {
769	768	.Perfmon,
770		.Db,
771		.Dsp,
772		.Rclass,
773		.V7clrex,
774	769	.V4t,
	770	.V7clrex,
	771	.Dsp,
	772	.Thumb2,
	773	.Db,
775	774	.Hwdiv,
	775	.Rclass,
776	776	.Armv7R,
777	777	.AvoidPartialCpsr,
778	778	.RetAddrStack,
...	...	@@ -781,16 +781,16 @@ pub const ArmCpu = enum {
781	781	.Fpregs,
782	782	.Vfp3d16,
783	783	.R4,
784		},
785		CpuInfo(@This()).create(.CortexR5, "cortex-r5", &[_]FeatureType {
786		.Thumb2,
	784	}),
	785	CpuInfo(@This(), FeatureType).create(.CortexR5, "cortex-r5", &[_]FeatureType {
787	786	.Perfmon,
788		.Db,
789		.Dsp,
790		.Rclass,
791		.V7clrex,
792	787	.V4t,
	788	.V7clrex,
	789	.Dsp,
	790	.Thumb2,
	791	.Db,
793	792	.Hwdiv,
	793	.Rclass,
794	794	.Armv7R,
795	795	.AvoidPartialCpsr,
796	796	.HwdivArm,
...	...	@@ -800,39 +800,39 @@ pub const ArmCpu = enum {
800	800	.Fpregs,
801	801	.Vfp3d16,
802	802	.R5,
803		},
804		CpuInfo(@This()).create(.CortexR52, "cortex-r52", &[_]FeatureType {
805		.Thumb2,
806		.Mp,
	803	}),
	804	CpuInfo(@This(), FeatureType).create(.CortexR52, "cortex-r52", &[_]FeatureType {
	805	.HwdivArm,
807	806	.Perfmon,
808		.Db,
	807	.D32,
809	808	.Crc,
810		.Fp16,
	809	.Fpregs,
	810	.Mp,
811	811	.Dfb,
812	812	.Dsp,
813		.Rclass,
814		.V7clrex,
	813	.Fp16,
815	814	.V4t,
816		.Fpregs,
817		.D32,
818		.Hwdiv,
819		.HwdivArm,
	815	.Db,
	816	.V7clrex,
	817	.Thumb2,
820	818	.AcquireRelease,
	819	.Hwdiv,
	820	.Rclass,
821	821	.Armv8R,
822	822	.Fpao,
823	823	.UseAa,
824	824	.UseMisched,
825	825	.R52,
826		},
827		CpuInfo(@This()).create(.CortexR7, "cortex-r7", &[_]FeatureType {
828		.Thumb2,
	826	}),
	827	CpuInfo(@This(), FeatureType).create(.CortexR7, "cortex-r7", &[_]FeatureType {
829	828	.Perfmon,
830		.Db,
831		.Dsp,
832		.Rclass,
833		.V7clrex,
834	829	.V4t,
	830	.V7clrex,
	831	.Dsp,
	832	.Thumb2,
	833	.Db,
835	834	.Hwdiv,
	835	.Rclass,
836	836	.Armv7R,
837	837	.AvoidPartialCpsr,
838	838	.Fp16,
...	...	@@ -844,16 +844,16 @@ pub const ArmCpu = enum {
844	844	.Fpregs,
845	845	.Vfp3d16,
846	846	.R7,
847		},
848		CpuInfo(@This()).create(.CortexR8, "cortex-r8", &[_]FeatureType {
849		.Thumb2,
	847	}),
	848	CpuInfo(@This(), FeatureType).create(.CortexR8, "cortex-r8", &[_]FeatureType {
850	849	.Perfmon,
851		.Db,
852		.Dsp,
853		.Rclass,
854		.V7clrex,
855	850	.V4t,
	851	.V7clrex,
	852	.Dsp,
	853	.Thumb2,
	854	.Db,
856	855	.Hwdiv,
	856	.Rclass,
857	857	.Armv7R,
858	858	.AvoidPartialCpsr,
859	859	.Fp16,
...	...	@@ -864,24 +864,24 @@ pub const ArmCpu = enum {
864	864	.SlowFpBrcc,
865	865	.Fpregs,
866	866	.Vfp3d16,
867		},
868		CpuInfo(@This()).create(.Cyclone, "cyclone", &[_]FeatureType {
869		.Thumb2,
870		.Mp,
	867	}),
	868	CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
	869	.HwdivArm,
871	870	.Perfmon,
872		.Db,
	871	.D32,
	872	.Fpregs,
873	873	.Crc,
	874	.Mp,
874	875	.Fp16,
875	876	.Dsp,
876		.V7clrex,
877	877	.V4t,
878		.Fpregs,
879		.D32,
880		.Hwdiv,
881		.HwdivArm,
	878	.V7clrex,
	879	.Db,
882	880	.Aclass,
883		.Trustzone,
	881	.Thumb2,
884	882	.AcquireRelease,
	883	.Hwdiv,
	884	.Trustzone,
885	885	.Armv8A,
886	886	.AvoidMovsShop,
887	887	.AvoidPartialCpsr,
...	...	@@ -894,197 +894,197 @@ pub const ArmCpu = enum {
894	894	.Vfp4,
895	895	.Zcz,
896	896	.Swift,
897		},
898		CpuInfo(@This()).create(.Ep9312, "ep9312", &[_]FeatureType {
	897	}),
	898	CpuInfo(@This(), FeatureType).create(.Ep9312, "ep9312", &[_]FeatureType {
899	899	.V4t,
900	900	.Armv4t,
901		},
902		CpuInfo(@This()).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
903		.Thumb2,
904		.Mp,
	901	}),
	902	CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
	903	.HwdivArm,
905	904	.Perfmon,
906		.Db,
	905	.D32,
	906	.Fpregs,
907	907	.Crc,
	908	.Mp,
908	909	.Fp16,
909	910	.Dsp,
910		.V7clrex,
911	911	.V4t,
912		.Fpregs,
913		.D32,
914		.Hwdiv,
915		.HwdivArm,
	912	.V7clrex,
	913	.Db,
916	914	.Aclass,
917		.Trustzone,
	915	.Thumb2,
918	916	.AcquireRelease,
	917	.Hwdiv,
	918	.Trustzone,
919	919	.Armv8A,
920		.Zcz,
921		.SlowVdup32,
	920	.RetAddrStack,
922	921	.SlowVgetlni32,
923		.DontWidenVmovs,
924		.FuseAes,
925	922	.WideStrideVfp,
	923	.SlowVdup32,
	924	.SlowFpBrcc,
926	925	.ProfUnpr,
	926	.DontWidenVmovs,
	927	.Zcz,
	928	.FuseAes,
927	929	.Slowfpvmlx,
928		.SlowFpBrcc,
	930	.UseAa,
929	931	.FuseLiterals,
930	932	.ExpandFpMlx,
931		.RetAddrStack,
932		.UseAa,
933	933	.Exynos,
934		},
935		CpuInfo(@This()).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
936		.Thumb2,
937		.Mp,
	934	}),
	935	CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
	936	.HwdivArm,
938	937	.Perfmon,
939		.Db,
	938	.D32,
	939	.Fpregs,
940	940	.Crc,
	941	.Mp,
941	942	.Fp16,
942	943	.Dsp,
943		.V7clrex,
944	944	.V4t,
945		.Fpregs,
946		.D32,
947		.Hwdiv,
948		.HwdivArm,
	945	.V7clrex,
	946	.Db,
949	947	.Aclass,
950		.Trustzone,
	948	.Thumb2,
951	949	.AcquireRelease,
	950	.Hwdiv,
	951	.Trustzone,
952	952	.Armv8A,
953		.Zcz,
954		.SlowVdup32,
	953	.RetAddrStack,
955	954	.SlowVgetlni32,
956		.DontWidenVmovs,
957		.FuseAes,
958	955	.WideStrideVfp,
	956	.SlowVdup32,
	957	.SlowFpBrcc,
959	958	.ProfUnpr,
	959	.DontWidenVmovs,
	960	.Zcz,
	961	.FuseAes,
960	962	.Slowfpvmlx,
961		.SlowFpBrcc,
	963	.UseAa,
962	964	.FuseLiterals,
963	965	.ExpandFpMlx,
964		.RetAddrStack,
965		.UseAa,
966	966	.Exynos,
967		},
968		CpuInfo(@This()).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
969		.Thumb2,
970		.Mp,
	967	}),
	968	CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
	969	.HwdivArm,
971	970	.Perfmon,
972		.Db,
	971	.D32,
	972	.Fpregs,
973	973	.Crc,
	974	.Mp,
974	975	.Fp16,
975	976	.Dsp,
976		.V7clrex,
977	977	.V4t,
978		.Fpregs,
979		.D32,
980		.Hwdiv,
981		.HwdivArm,
	978	.V7clrex,
	979	.Db,
982	980	.Aclass,
983		.Trustzone,
	981	.Thumb2,
984	982	.AcquireRelease,
	983	.Hwdiv,
	984	.Trustzone,
985	985	.Armv8A,
986		.Zcz,
987		.SlowVdup32,
	986	.RetAddrStack,
988	987	.SlowVgetlni32,
989		.DontWidenVmovs,
990		.FuseAes,
991	988	.WideStrideVfp,
	989	.SlowVdup32,
	990	.SlowFpBrcc,
992	991	.ProfUnpr,
	992	.DontWidenVmovs,
	993	.Zcz,
	994	.FuseAes,
993	995	.Slowfpvmlx,
994		.SlowFpBrcc,
	996	.UseAa,
995	997	.FuseLiterals,
996	998	.ExpandFpMlx,
997		.RetAddrStack,
998		.UseAa,
999	999	.Exynos,
1000		},
1001		CpuInfo(@This()).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
1002		.Thumb2,
1003		.Mp,
	1000	}),
	1001	CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
	1002	.HwdivArm,
1004	1003	.Perfmon,
1005		.Db,
	1004	.D32,
	1005	.Fpregs,
1006	1006	.Crc,
	1007	.Mp,
1007	1008	.Fp16,
1008		.Ras,
1009	1009	.Dsp,
1010		.V7clrex,
1011	1010	.V4t,
1012		.Fpregs,
1013		.D32,
1014		.Hwdiv,
1015		.HwdivArm,
	1011	.V7clrex,
	1012	.Db,
1016	1013	.Aclass,
1017		.Trustzone,
	1014	.Thumb2,
	1015	.Ras,
1018	1016	.AcquireRelease,
	1017	.Hwdiv,
	1018	.Trustzone,
1019	1019	.Armv82A,
1020	1020	.Dotprod,
1021	1021	.Fullfp16,
1022		.Zcz,
1023		.SlowVdup32,
	1022	.RetAddrStack,
1024	1023	.SlowVgetlni32,
1025		.DontWidenVmovs,
1026		.FuseAes,
1027	1024	.WideStrideVfp,
	1025	.SlowVdup32,
	1026	.SlowFpBrcc,
1028	1027	.ProfUnpr,
	1028	.DontWidenVmovs,
	1029	.Zcz,
	1030	.FuseAes,
1029	1031	.Slowfpvmlx,
1030		.SlowFpBrcc,
	1032	.UseAa,
1031	1033	.FuseLiterals,
1032	1034	.ExpandFpMlx,
1033		.RetAddrStack,
1034		.UseAa,
1035	1035	.Exynos,
1036		},
1037		CpuInfo(@This()).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
1038		.Thumb2,
1039		.Mp,
	1036	}),
	1037	CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
	1038	.HwdivArm,
1040	1039	.Perfmon,
1041		.Db,
	1040	.D32,
	1041	.Fpregs,
1042	1042	.Crc,
	1043	.Mp,
1043	1044	.Fp16,
1044		.Ras,
1045	1045	.Dsp,
1046		.V7clrex,
1047	1046	.V4t,
1048		.Fpregs,
1049		.D32,
1050		.Hwdiv,
1051		.HwdivArm,
	1047	.V7clrex,
	1048	.Db,
1052	1049	.Aclass,
1053		.Trustzone,
	1050	.Thumb2,
	1051	.Ras,
1054	1052	.AcquireRelease,
	1053	.Hwdiv,
	1054	.Trustzone,
1055	1055	.Armv82A,
1056	1056	.Dotprod,
1057	1057	.Fullfp16,
1058		.Zcz,
1059		.SlowVdup32,
	1058	.RetAddrStack,
1060	1059	.SlowVgetlni32,
1061		.DontWidenVmovs,
1062		.FuseAes,
1063	1060	.WideStrideVfp,
	1061	.SlowVdup32,
	1062	.SlowFpBrcc,
1064	1063	.ProfUnpr,
	1064	.DontWidenVmovs,
	1065	.Zcz,
	1066	.FuseAes,
1065	1067	.Slowfpvmlx,
1066		.SlowFpBrcc,
	1068	.UseAa,
1067	1069	.FuseLiterals,
1068	1070	.ExpandFpMlx,
1069		.RetAddrStack,
1070		.UseAa,
1071	1071	.Exynos,
1072		},
1073		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
1074		},
1075		CpuInfo(@This()).create(.Iwmmxt, "iwmmxt", &[_]FeatureType {
	1072	}),
	1073	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
	1074	}),
	1075	CpuInfo(@This(), FeatureType).create(.Iwmmxt, "iwmmxt", &[_]FeatureType {
1076	1076	.V4t,
1077	1077	.Armv5te,
1078		},
1079		CpuInfo(@This()).create(.Krait, "krait", &[_]FeatureType {
1080		.Thumb2,
	1078	}),
	1079	CpuInfo(@This(), FeatureType).create(.Krait, "krait", &[_]FeatureType {
1081	1080	.Perfmon,
1082		.Db,
1083		.Dsp,
1084		.V7clrex,
1085	1081	.V4t,
1086		.Fpregs,
1087	1082	.D32,
	1083	.Fpregs,
	1084	.V7clrex,
	1085	.Dsp,
	1086	.Thumb2,
	1087	.Db,
1088	1088	.Aclass,
1089	1089	.Armv7A,
1090	1090	.AvoidPartialCpsr,
...	...	@@ -1097,107 +1097,107 @@ pub const ArmCpu = enum {
1097	1097	.Vfp4,
1098	1098	.VmlxForwarding,
1099	1099	.Krait,
1100		},
1101		CpuInfo(@This()).create(.Kryo, "kryo", &[_]FeatureType {
1102		.Thumb2,
1103		.Mp,
	1100	}),
	1101	CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
	1102	.HwdivArm,
1104	1103	.Perfmon,
1105		.Db,
	1104	.D32,
	1105	.Fpregs,
1106	1106	.Crc,
	1107	.Mp,
1107	1108	.Fp16,
1108	1109	.Dsp,
1109		.V7clrex,
1110	1110	.V4t,
1111		.Fpregs,
1112		.D32,
1113		.Hwdiv,
1114		.HwdivArm,
	1111	.V7clrex,
	1112	.Db,
1115	1113	.Aclass,
1116		.Trustzone,
	1114	.Thumb2,
1117	1115	.AcquireRelease,
	1116	.Hwdiv,
	1117	.Trustzone,
1118	1118	.Armv8A,
1119	1119	.Crypto,
1120	1120	.Kryo,
1121		},
1122		CpuInfo(@This()).create(.Mpcore, "mpcore", &[_]FeatureType {
	1121	}),
	1122	CpuInfo(@This(), FeatureType).create(.Mpcore, "mpcore", &[_]FeatureType {
1123	1123	.V4t,
1124	1124	.Armv6k,
1125	1125	.Slowfpvmlx,
1126	1126	.Fpregs,
1127	1127	.Vfp2,
1128		},
1129		CpuInfo(@This()).create(.Mpcorenovfp, "mpcorenovfp", &[_]FeatureType {
	1128	}),
	1129	CpuInfo(@This(), FeatureType).create(.Mpcorenovfp, "mpcorenovfp", &[_]FeatureType {
1130	1130	.V4t,
1131	1131	.Armv6k,
1132		},
1133		CpuInfo(@This()).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
1134		.Thumb2,
1135		.Mp,
	1132	}),
	1133	CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
	1134	.HwdivArm,
1136	1135	.Perfmon,
1137		.Db,
	1136	.D32,
	1137	.Fpregs,
1138	1138	.Crc,
	1139	.Mp,
1139	1140	.Fp16,
1140		.Ras,
1141	1141	.Dsp,
1142		.V7clrex,
1143	1142	.V4t,
1144		.Fpregs,
1145		.D32,
1146		.Hwdiv,
1147		.HwdivArm,
	1143	.V7clrex,
	1144	.Db,
1148	1145	.Aclass,
1149		.Trustzone,
	1146	.Thumb2,
	1147	.Ras,
1150	1148	.AcquireRelease,
	1149	.Hwdiv,
	1150	.Trustzone,
1151	1151	.Armv82A,
1152	1152	.Crypto,
1153	1153	.Dotprod,
1154		},
1155		CpuInfo(@This()).create(.Sc000, "sc000", &[_]FeatureType {
1156		.Mclass,
1157		.StrictAlign,
	1154	}),
	1155	CpuInfo(@This(), FeatureType).create(.Sc000, "sc000", &[_]FeatureType {
	1156	.V4t,
1158	1157	.ThumbMode,
1159	1158	.Db,
1160		.V4t,
	1159	.StrictAlign,
	1160	.Mclass,
1161	1161	.Noarm,
1162	1162	.Armv6M,
1163		},
1164		CpuInfo(@This()).create(.Sc300, "sc300", &[_]FeatureType {
1165		.Thumb2,
1166		.Mclass,
	1163	}),
	1164	CpuInfo(@This(), FeatureType).create(.Sc300, "sc300", &[_]FeatureType {
1167	1165	.Perfmon,
	1166	.V4t,
1168	1167	.ThumbMode,
1169		.Db,
1170	1168	.V7clrex,
1171		.V4t,
1172		.Hwdiv,
	1169	.Thumb2,
	1170	.Db,
	1171	.Mclass,
1173	1172	.Noarm,
	1173	.Hwdiv,
1174	1174	.Armv7M,
1175	1175	.NoBranchPredictor,
1176	1176	.UseAa,
1177	1177	.UseMisched,
1178	1178	.M3,
1179		},
1180		CpuInfo(@This()).create(.Strongarm, "strongarm", &[_]FeatureType {
	1179	}),
	1180	CpuInfo(@This(), FeatureType).create(.Strongarm, "strongarm", &[_]FeatureType {
1181	1181	.Armv4,
1182		},
1183		CpuInfo(@This()).create(.Strongarm110, "strongarm110", &[_]FeatureType {
	1182	}),
	1183	CpuInfo(@This(), FeatureType).create(.Strongarm110, "strongarm110", &[_]FeatureType {
1184	1184	.Armv4,
1185		},
1186		CpuInfo(@This()).create(.Strongarm1100, "strongarm1100", &[_]FeatureType {
	1185	}),
	1186	CpuInfo(@This(), FeatureType).create(.Strongarm1100, "strongarm1100", &[_]FeatureType {
1187	1187	.Armv4,
1188		},
1189		CpuInfo(@This()).create(.Strongarm1110, "strongarm1110", &[_]FeatureType {
	1188	}),
	1189	CpuInfo(@This(), FeatureType).create(.Strongarm1110, "strongarm1110", &[_]FeatureType {
1190	1190	.Armv4,
1191		},
1192		CpuInfo(@This()).create(.Swift, "swift", &[_]FeatureType {
1193		.Thumb2,
	1191	}),
	1192	CpuInfo(@This(), FeatureType).create(.Swift, "swift", &[_]FeatureType {
1194	1193	.Perfmon,
1195		.Db,
1196		.Dsp,
1197		.V7clrex,
1198	1194	.V4t,
1199		.Fpregs,
1200	1195	.D32,
	1196	.Fpregs,
	1197	.V7clrex,
	1198	.Dsp,
	1199	.Thumb2,
	1200	.Db,
1201	1201	.Aclass,
1202	1202	.Armv7A,
1203	1203	.AvoidMovsShop,
...	...	@@ -1221,10 +1221,10 @@ pub const ArmCpu = enum {
1221	1221	.Fp16,
1222	1222	.Vfp4,
1223	1223	.Swift,
1224		},
1225		CpuInfo(@This()).create(.Xscale, "xscale", &[_]FeatureType {
	1224	}),
	1225	CpuInfo(@This(), FeatureType).create(.Xscale, "xscale", &[_]FeatureType {
1226	1226	.V4t,
1227	1227	.Armv5te,
1228		},
	1228	}),
1229	1229	};
1230	1230	};

lib/std/target/cpu/AvrCpu.zig+2159-2159

...	...	@@ -260,3604 +260,3604 @@ pub const AvrCpu = enum {
260	260	Avrxmega7,
261	261	M3000,
262	262
263		pub fn getInfo(self: @This()) CpuInfo {
	263	const FeatureType = feature.AvrFeature;
	264
	265	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
264	266	return cpu_infos[@enumToInt(self)];
265	267	}
266	268
267		pub const FeatureType = feature.AvrFeature;
268
269		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
270		CpuInfo(@This()).create(.At43usb320, "at43usb320", &[_]FeatureType {
271		.Ijmpcall,
272		.Sram,
	269	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	270	CpuInfo(@This(), FeatureType).create(.At43usb320, "at43usb320", &[_]FeatureType {
	271	.Lpm,
273	272	.Elpm,
274	273	.Avr0,
	274	.Sram,
275	275	.Jmpcall,
276	276	.Addsubiw,
277		.Lpm,
278		.Avr31,
279		},
280		CpuInfo(@This()).create(.At43usb355, "at43usb355", &[_]FeatureType {
281	277	.Ijmpcall,
282		.Sram,
	278	.Avr31,
	279	}),
	280	CpuInfo(@This(), FeatureType).create(.At43usb355, "at43usb355", &[_]FeatureType {
	281	.Lpm,
283	282	.Avr0,
	283	.Sram,
284	284	.Jmpcall,
285	285	.Addsubiw,
286		.Lpm,
287		.Avr3,
288		},
289		CpuInfo(@This()).create(.At76c711, "at76c711", &[_]FeatureType {
290	286	.Ijmpcall,
291		.Sram,
	287	.Avr3,
	288	}),
	289	CpuInfo(@This(), FeatureType).create(.At76c711, "at76c711", &[_]FeatureType {
	290	.Lpm,
292	291	.Avr0,
	292	.Sram,
293	293	.Jmpcall,
294	294	.Addsubiw,
295		.Lpm,
296		.Avr3,
297		},
298		CpuInfo(@This()).create(.At86rf401, "at86rf401", &[_]FeatureType {
299	295	.Ijmpcall,
300		.Sram,
	296	.Avr3,
	297	}),
	298	CpuInfo(@This(), FeatureType).create(.At86rf401, "at86rf401", &[_]FeatureType {
	299	.Lpm,
301	300	.Avr0,
	301	.Sram,
302	302	.Addsubiw,
303		.Lpm,
	303	.Ijmpcall,
304	304	.Avr2,
305	305	.Lpmx,
306	306	.Movw,
307		},
308		CpuInfo(@This()).create(.At90c8534, "at90c8534", &[_]FeatureType {
309		.Ijmpcall,
310		.Sram,
	307	}),
	308	CpuInfo(@This(), FeatureType).create(.At90c8534, "at90c8534", &[_]FeatureType {
	309	.Lpm,
311	310	.Avr0,
	311	.Sram,
312	312	.Addsubiw,
313		.Lpm,
314		.Avr2,
315		},
316		CpuInfo(@This()).create(.At90can128, "at90can128", &[_]FeatureType {
317	313	.Ijmpcall,
318		.Elpmx,
	314	.Avr2,
	315	}),
	316	CpuInfo(@This(), FeatureType).create(.At90can128, "at90can128", &[_]FeatureType {
	317	.Lpm,
	318	.Elpm,
319	319	.Movw,
320		.Mul,
321		.Sram,
322		.Break,
	320	.Elpmx,
323	321	.Spm,
324		.Elpm,
325		.Lpmx,
326	322	.Avr0,
	323	.Sram,
327	324	.Jmpcall,
328	325	.Addsubiw,
329		.Lpm,
330		.Avr51,
331		},
332		CpuInfo(@This()).create(.At90can32, "at90can32", &[_]FeatureType {
333		.Ijmpcall,
334		.Movw,
335	326	.Mul,
336		.Sram,
	327	.Lpmx,
	328	.Ijmpcall,
337	329	.Break,
	330	.Avr51,
	331	}),
	332	CpuInfo(@This(), FeatureType).create(.At90can32, "at90can32", &[_]FeatureType {
	333	.Lpm,
	334	.Movw,
338	335	.Spm,
339		.Lpmx,
340	336	.Avr0,
	337	.Sram,
341	338	.Jmpcall,
342	339	.Addsubiw,
343		.Lpm,
344		.Avr5,
345		},
346		CpuInfo(@This()).create(.At90can64, "at90can64", &[_]FeatureType {
347		.Ijmpcall,
348		.Movw,
349	340	.Mul,
350		.Sram,
	341	.Lpmx,
	342	.Ijmpcall,
351	343	.Break,
	344	.Avr5,
	345	}),
	346	CpuInfo(@This(), FeatureType).create(.At90can64, "at90can64", &[_]FeatureType {
	347	.Lpm,
	348	.Movw,
352	349	.Spm,
353		.Lpmx,
354	350	.Avr0,
	351	.Sram,
355	352	.Jmpcall,
356	353	.Addsubiw,
357		.Lpm,
358		.Avr5,
359		},
360		CpuInfo(@This()).create(.At90pwm1, "at90pwm1", &[_]FeatureType {
361		.Ijmpcall,
362		.Movw,
363	354	.Mul,
364		.Sram,
	355	.Lpmx,
	356	.Ijmpcall,
365	357	.Break,
	358	.Avr5,
	359	}),
	360	CpuInfo(@This(), FeatureType).create(.At90pwm1, "at90pwm1", &[_]FeatureType {
	361	.Lpm,
	362	.Movw,
366	363	.Spm,
367		.Lpmx,
368	364	.Avr0,
	365	.Sram,
369	366	.Addsubiw,
370		.Lpm,
371		.Avr4,
372		},
373		CpuInfo(@This()).create(.At90pwm161, "at90pwm161", &[_]FeatureType {
374		.Ijmpcall,
375		.Movw,
376	367	.Mul,
377		.Sram,
	368	.Lpmx,
	369	.Ijmpcall,
378	370	.Break,
	371	.Avr4,
	372	}),
	373	CpuInfo(@This(), FeatureType).create(.At90pwm161, "at90pwm161", &[_]FeatureType {
	374	.Lpm,
	375	.Movw,
379	376	.Spm,
380		.Lpmx,
381	377	.Avr0,
	378	.Sram,
382	379	.Jmpcall,
383	380	.Addsubiw,
384		.Lpm,
385		.Avr5,
386		},
387		CpuInfo(@This()).create(.At90pwm2, "at90pwm2", &[_]FeatureType {
388		.Ijmpcall,
389		.Movw,
390	381	.Mul,
391		.Sram,
	382	.Lpmx,
	383	.Ijmpcall,
392	384	.Break,
	385	.Avr5,
	386	}),
	387	CpuInfo(@This(), FeatureType).create(.At90pwm2, "at90pwm2", &[_]FeatureType {
	388	.Lpm,
	389	.Movw,
393	390	.Spm,
394		.Lpmx,
395	391	.Avr0,
	392	.Sram,
396	393	.Addsubiw,
397		.Lpm,
398		.Avr4,
399		},
400		CpuInfo(@This()).create(.At90pwm216, "at90pwm216", &[_]FeatureType {
401		.Ijmpcall,
402		.Movw,
403	394	.Mul,
404		.Sram,
	395	.Lpmx,
	396	.Ijmpcall,
405	397	.Break,
	398	.Avr4,
	399	}),
	400	CpuInfo(@This(), FeatureType).create(.At90pwm216, "at90pwm216", &[_]FeatureType {
	401	.Lpm,
	402	.Movw,
406	403	.Spm,
407		.Lpmx,
408	404	.Avr0,
	405	.Sram,
409	406	.Jmpcall,
410	407	.Addsubiw,
411		.Lpm,
412		.Avr5,
413		},
414		CpuInfo(@This()).create(.At90pwm2b, "at90pwm2b", &[_]FeatureType {
415		.Ijmpcall,
416		.Movw,
417	408	.Mul,
418		.Sram,
	409	.Lpmx,
	410	.Ijmpcall,
419	411	.Break,
	412	.Avr5,
	413	}),
	414	CpuInfo(@This(), FeatureType).create(.At90pwm2b, "at90pwm2b", &[_]FeatureType {
	415	.Lpm,
	416	.Movw,
420	417	.Spm,
421		.Lpmx,
422	418	.Avr0,
	419	.Sram,
423	420	.Addsubiw,
424		.Lpm,
425		.Avr4,
426		},
427		CpuInfo(@This()).create(.At90pwm3, "at90pwm3", &[_]FeatureType {
428		.Ijmpcall,
429		.Movw,
430	421	.Mul,
431		.Sram,
	422	.Lpmx,
	423	.Ijmpcall,
432	424	.Break,
	425	.Avr4,
	426	}),
	427	CpuInfo(@This(), FeatureType).create(.At90pwm3, "at90pwm3", &[_]FeatureType {
	428	.Lpm,
	429	.Movw,
433	430	.Spm,
434		.Lpmx,
435	431	.Avr0,
	432	.Sram,
436	433	.Addsubiw,
437		.Lpm,
438		.Avr4,
439		},
440		CpuInfo(@This()).create(.At90pwm316, "at90pwm316", &[_]FeatureType {
441		.Ijmpcall,
442		.Movw,
443	434	.Mul,
444		.Sram,
	435	.Lpmx,
	436	.Ijmpcall,
445	437	.Break,
	438	.Avr4,
	439	}),
	440	CpuInfo(@This(), FeatureType).create(.At90pwm316, "at90pwm316", &[_]FeatureType {
	441	.Lpm,
	442	.Movw,
446	443	.Spm,
447		.Lpmx,
448	444	.Avr0,
	445	.Sram,
449	446	.Jmpcall,
450	447	.Addsubiw,
451		.Lpm,
452		.Avr5,
453		},
454		CpuInfo(@This()).create(.At90pwm3b, "at90pwm3b", &[_]FeatureType {
455		.Ijmpcall,
456		.Movw,
457	448	.Mul,
458		.Sram,
	449	.Lpmx,
	450	.Ijmpcall,
459	451	.Break,
	452	.Avr5,
	453	}),
	454	CpuInfo(@This(), FeatureType).create(.At90pwm3b, "at90pwm3b", &[_]FeatureType {
	455	.Lpm,
	456	.Movw,
460	457	.Spm,
461		.Lpmx,
462	458	.Avr0,
	459	.Sram,
463	460	.Addsubiw,
464		.Lpm,
465		.Avr4,
466		},
467		CpuInfo(@This()).create(.At90pwm81, "at90pwm81", &[_]FeatureType {
468		.Ijmpcall,
469		.Movw,
470	461	.Mul,
471		.Sram,
	462	.Lpmx,
	463	.Ijmpcall,
472	464	.Break,
	465	.Avr4,
	466	}),
	467	CpuInfo(@This(), FeatureType).create(.At90pwm81, "at90pwm81", &[_]FeatureType {
	468	.Lpm,
	469	.Movw,
473	470	.Spm,
474		.Lpmx,
475	471	.Avr0,
	472	.Sram,
476	473	.Addsubiw,
477		.Lpm,
	474	.Mul,
	475	.Lpmx,
	476	.Ijmpcall,
	477	.Break,
478	478	.Avr4,
479		},
480		CpuInfo(@This()).create(.At90s1200, "at90s1200", &[_]FeatureType {
	479	}),
	480	CpuInfo(@This(), FeatureType).create(.At90s1200, "at90s1200", &[_]FeatureType {
481	481	.Avr0,
482		},
483		CpuInfo(@This()).create(.At90s2313, "at90s2313", &[_]FeatureType {
484		.Ijmpcall,
485		.Sram,
	482	}),
	483	CpuInfo(@This(), FeatureType).create(.At90s2313, "at90s2313", &[_]FeatureType {
	484	.Lpm,
486	485	.Avr0,
	486	.Sram,
487	487	.Addsubiw,
488		.Lpm,
489		.Avr2,
490		},
491		CpuInfo(@This()).create(.At90s2323, "at90s2323", &[_]FeatureType {
492	488	.Ijmpcall,
493		.Sram,
	489	.Avr2,
	490	}),
	491	CpuInfo(@This(), FeatureType).create(.At90s2323, "at90s2323", &[_]FeatureType {
	492	.Lpm,
494	493	.Avr0,
	494	.Sram,
495	495	.Addsubiw,
496		.Lpm,
497		.Avr2,
498		},
499		CpuInfo(@This()).create(.At90s2333, "at90s2333", &[_]FeatureType {
500	496	.Ijmpcall,
501		.Sram,
	497	.Avr2,
	498	}),
	499	CpuInfo(@This(), FeatureType).create(.At90s2333, "at90s2333", &[_]FeatureType {
	500	.Lpm,
502	501	.Avr0,
	502	.Sram,
503	503	.Addsubiw,
504		.Lpm,
505		.Avr2,
506		},
507		CpuInfo(@This()).create(.At90s2343, "at90s2343", &[_]FeatureType {
508	504	.Ijmpcall,
509		.Sram,
	505	.Avr2,
	506	}),
	507	CpuInfo(@This(), FeatureType).create(.At90s2343, "at90s2343", &[_]FeatureType {
	508	.Lpm,
510	509	.Avr0,
	510	.Sram,
511	511	.Addsubiw,
512		.Lpm,
513		.Avr2,
514		},
515		CpuInfo(@This()).create(.At90s4414, "at90s4414", &[_]FeatureType {
516	512	.Ijmpcall,
517		.Sram,
	513	.Avr2,
	514	}),
	515	CpuInfo(@This(), FeatureType).create(.At90s4414, "at90s4414", &[_]FeatureType {
	516	.Lpm,
518	517	.Avr0,
	518	.Sram,
519	519	.Addsubiw,
520		.Lpm,
521		.Avr2,
522		},
523		CpuInfo(@This()).create(.At90s4433, "at90s4433", &[_]FeatureType {
524	520	.Ijmpcall,
525		.Sram,
	521	.Avr2,
	522	}),
	523	CpuInfo(@This(), FeatureType).create(.At90s4433, "at90s4433", &[_]FeatureType {
	524	.Lpm,
526	525	.Avr0,
	526	.Sram,
527	527	.Addsubiw,
528		.Lpm,
529		.Avr2,
530		},
531		CpuInfo(@This()).create(.At90s4434, "at90s4434", &[_]FeatureType {
532	528	.Ijmpcall,
533		.Sram,
	529	.Avr2,
	530	}),
	531	CpuInfo(@This(), FeatureType).create(.At90s4434, "at90s4434", &[_]FeatureType {
	532	.Lpm,
534	533	.Avr0,
	534	.Sram,
535	535	.Addsubiw,
536		.Lpm,
537		.Avr2,
538		},
539		CpuInfo(@This()).create(.At90s8515, "at90s8515", &[_]FeatureType {
540	536	.Ijmpcall,
541		.Sram,
	537	.Avr2,
	538	}),
	539	CpuInfo(@This(), FeatureType).create(.At90s8515, "at90s8515", &[_]FeatureType {
	540	.Lpm,
542	541	.Avr0,
	542	.Sram,
543	543	.Addsubiw,
544		.Lpm,
545		.Avr2,
546		},
547		CpuInfo(@This()).create(.At90s8535, "at90s8535", &[_]FeatureType {
548	544	.Ijmpcall,
549		.Sram,
	545	.Avr2,
	546	}),
	547	CpuInfo(@This(), FeatureType).create(.At90s8535, "at90s8535", &[_]FeatureType {
	548	.Lpm,
550	549	.Avr0,
	550	.Sram,
551	551	.Addsubiw,
552		.Lpm,
553		.Avr2,
554		},
555		CpuInfo(@This()).create(.At90scr100, "at90scr100", &[_]FeatureType {
556	552	.Ijmpcall,
	553	.Avr2,
	554	}),
	555	CpuInfo(@This(), FeatureType).create(.At90scr100, "at90scr100", &[_]FeatureType {
	556	.Lpm,
557	557	.Movw,
558		.Mul,
559		.Sram,
560		.Break,
561	558	.Spm,
562		.Lpmx,
563	559	.Avr0,
	560	.Sram,
564	561	.Jmpcall,
565	562	.Addsubiw,
566		.Lpm,
567		.Avr5,
568		},
569		CpuInfo(@This()).create(.At90usb1286, "at90usb1286", &[_]FeatureType {
570		.Ijmpcall,
571		.Elpmx,
572		.Movw,
573	563	.Mul,
574		.Sram,
	564	.Lpmx,
	565	.Ijmpcall,
575	566	.Break,
576		.Spm,
	567	.Avr5,
	568	}),
	569	CpuInfo(@This(), FeatureType).create(.At90usb1286, "at90usb1286", &[_]FeatureType {
	570	.Lpm,
577	571	.Elpm,
578		.Lpmx,
	572	.Movw,
	573	.Elpmx,
	574	.Spm,
579	575	.Avr0,
	576	.Sram,
580	577	.Jmpcall,
581	578	.Addsubiw,
582		.Lpm,
583		.Avr51,
584		},
585		CpuInfo(@This()).create(.At90usb1287, "at90usb1287", &[_]FeatureType {
586		.Ijmpcall,
587		.Elpmx,
588		.Movw,
589	579	.Mul,
590		.Sram,
	580	.Lpmx,
	581	.Ijmpcall,
591	582	.Break,
592		.Spm,
	583	.Avr51,
	584	}),
	585	CpuInfo(@This(), FeatureType).create(.At90usb1287, "at90usb1287", &[_]FeatureType {
	586	.Lpm,
593	587	.Elpm,
594		.Lpmx,
	588	.Movw,
	589	.Elpmx,
	590	.Spm,
595	591	.Avr0,
	592	.Sram,
596	593	.Jmpcall,
597	594	.Addsubiw,
598		.Lpm,
599		.Avr51,
600		},
601		CpuInfo(@This()).create(.At90usb162, "at90usb162", &[_]FeatureType {
	595	.Mul,
	596	.Lpmx,
602	597	.Ijmpcall,
603		.Movw,
604		.Sram,
605	598	.Break,
	599	.Avr51,
	600	}),
	601	CpuInfo(@This(), FeatureType).create(.At90usb162, "at90usb162", &[_]FeatureType {
	602	.Lpm,
	603	.Movw,
606	604	.Spm,
607		.Lpmx,
608	605	.Avr0,
	606	.Sram,
609	607	.Jmpcall,
610	608	.Addsubiw,
611		.Lpm,
612		.Avr35,
613		},
614		CpuInfo(@This()).create(.At90usb646, "at90usb646", &[_]FeatureType {
	609	.Lpmx,
615	610	.Ijmpcall,
616		.Movw,
617		.Mul,
618		.Sram,
619	611	.Break,
	612	.Avr35,
	613	}),
	614	CpuInfo(@This(), FeatureType).create(.At90usb646, "at90usb646", &[_]FeatureType {
	615	.Lpm,
	616	.Movw,
620	617	.Spm,
621		.Lpmx,
622	618	.Avr0,
	619	.Sram,
623	620	.Jmpcall,
624	621	.Addsubiw,
625		.Lpm,
626		.Avr5,
627		},
628		CpuInfo(@This()).create(.At90usb647, "at90usb647", &[_]FeatureType {
629		.Ijmpcall,
630		.Movw,
631	622	.Mul,
632		.Sram,
	623	.Lpmx,
	624	.Ijmpcall,
633	625	.Break,
	626	.Avr5,
	627	}),
	628	CpuInfo(@This(), FeatureType).create(.At90usb647, "at90usb647", &[_]FeatureType {
	629	.Lpm,
	630	.Movw,
634	631	.Spm,
635		.Lpmx,
636	632	.Avr0,
	633	.Sram,
637	634	.Jmpcall,
638	635	.Addsubiw,
639		.Lpm,
640		.Avr5,
641		},
642		CpuInfo(@This()).create(.At90usb82, "at90usb82", &[_]FeatureType {
	636	.Mul,
	637	.Lpmx,
643	638	.Ijmpcall,
644		.Movw,
645		.Sram,
646	639	.Break,
	640	.Avr5,
	641	}),
	642	CpuInfo(@This(), FeatureType).create(.At90usb82, "at90usb82", &[_]FeatureType {
	643	.Lpm,
	644	.Movw,
647	645	.Spm,
648		.Lpmx,
649	646	.Avr0,
	647	.Sram,
650	648	.Jmpcall,
651	649	.Addsubiw,
652		.Lpm,
653		.Avr35,
654		},
655		CpuInfo(@This()).create(.At94k, "at94k", &[_]FeatureType {
	650	.Lpmx,
656	651	.Ijmpcall,
657		.Sram,
	652	.Break,
	653	.Avr35,
	654	}),
	655	CpuInfo(@This(), FeatureType).create(.At94k, "at94k", &[_]FeatureType {
	656	.Lpm,
658	657	.Avr0,
	658	.Sram,
659	659	.Jmpcall,
660	660	.Addsubiw,
661		.Lpm,
	661	.Ijmpcall,
662	662	.Avr3,
663	663	.Lpmx,
664	664	.Movw,
665	665	.Mul,
666		},
667		CpuInfo(@This()).create(.Ata5272, "ata5272", &[_]FeatureType {
668		.Ijmpcall,
	666	}),
	667	CpuInfo(@This(), FeatureType).create(.Ata5272, "ata5272", &[_]FeatureType {
	668	.Lpm,
669	669	.Movw,
670		.Sram,
671		.Break,
672	670	.Spm,
673		.Lpmx,
674	671	.Avr0,
	672	.Sram,
675	673	.Addsubiw,
676		.Lpm,
677		.Avr25,
678		},
679		CpuInfo(@This()).create(.Ata5505, "ata5505", &[_]FeatureType {
	674	.Lpmx,
680	675	.Ijmpcall,
681		.Movw,
682		.Sram,
683	676	.Break,
	677	.Avr25,
	678	}),
	679	CpuInfo(@This(), FeatureType).create(.Ata5505, "ata5505", &[_]FeatureType {
	680	.Lpm,
	681	.Movw,
684	682	.Spm,
685		.Lpmx,
686	683	.Avr0,
	684	.Sram,
687	685	.Jmpcall,
688	686	.Addsubiw,
689		.Lpm,
690		.Avr35,
691		},
692		CpuInfo(@This()).create(.Ata5790, "ata5790", &[_]FeatureType {
	687	.Lpmx,
693	688	.Ijmpcall,
694		.Movw,
695		.Mul,
696		.Sram,
697	689	.Break,
	690	.Avr35,
	691	}),
	692	CpuInfo(@This(), FeatureType).create(.Ata5790, "ata5790", &[_]FeatureType {
	693	.Lpm,
	694	.Movw,
698	695	.Spm,
699		.Lpmx,
700	696	.Avr0,
	697	.Sram,
701	698	.Jmpcall,
702	699	.Addsubiw,
703		.Lpm,
704		.Avr5,
705		},
706		CpuInfo(@This()).create(.Ata5795, "ata5795", &[_]FeatureType {
707		.Ijmpcall,
708		.Movw,
709	700	.Mul,
710		.Sram,
	701	.Lpmx,
	702	.Ijmpcall,
711	703	.Break,
	704	.Avr5,
	705	}),
	706	CpuInfo(@This(), FeatureType).create(.Ata5795, "ata5795", &[_]FeatureType {
	707	.Lpm,
	708	.Movw,
712	709	.Spm,
713		.Lpmx,
714	710	.Avr0,
	711	.Sram,
715	712	.Jmpcall,
716	713	.Addsubiw,
717		.Lpm,
718		.Avr5,
719		},
720		CpuInfo(@This()).create(.Ata6285, "ata6285", &[_]FeatureType {
721		.Ijmpcall,
722		.Movw,
723	714	.Mul,
724		.Sram,
	715	.Lpmx,
	716	.Ijmpcall,
725	717	.Break,
	718	.Avr5,
	719	}),
	720	CpuInfo(@This(), FeatureType).create(.Ata6285, "ata6285", &[_]FeatureType {
	721	.Lpm,
	722	.Movw,
726	723	.Spm,
727		.Lpmx,
728	724	.Avr0,
	725	.Sram,
729	726	.Addsubiw,
730		.Lpm,
731		.Avr4,
732		},
733		CpuInfo(@This()).create(.Ata6286, "ata6286", &[_]FeatureType {
734		.Ijmpcall,
735		.Movw,
736	727	.Mul,
737		.Sram,
	728	.Lpmx,
	729	.Ijmpcall,
738	730	.Break,
	731	.Avr4,
	732	}),
	733	CpuInfo(@This(), FeatureType).create(.Ata6286, "ata6286", &[_]FeatureType {
	734	.Lpm,
	735	.Movw,
739	736	.Spm,
740		.Lpmx,
741	737	.Avr0,
	738	.Sram,
742	739	.Addsubiw,
743		.Lpm,
744		.Avr4,
745		},
746		CpuInfo(@This()).create(.Ata6289, "ata6289", &[_]FeatureType {
747		.Ijmpcall,
748		.Movw,
749	740	.Mul,
750		.Sram,
	741	.Lpmx,
	742	.Ijmpcall,
751	743	.Break,
	744	.Avr4,
	745	}),
	746	CpuInfo(@This(), FeatureType).create(.Ata6289, "ata6289", &[_]FeatureType {
	747	.Lpm,
	748	.Movw,
752	749	.Spm,
753		.Lpmx,
754	750	.Avr0,
	751	.Sram,
755	752	.Addsubiw,
756		.Lpm,
757		.Avr4,
758		},
759		CpuInfo(@This()).create(.Atmega103, "atmega103", &[_]FeatureType {
	753	.Mul,
	754	.Lpmx,
760	755	.Ijmpcall,
761		.Sram,
	756	.Break,
	757	.Avr4,
	758	}),
	759	CpuInfo(@This(), FeatureType).create(.Atmega103, "atmega103", &[_]FeatureType {
	760	.Lpm,
762	761	.Elpm,
763	762	.Avr0,
	763	.Sram,
764	764	.Jmpcall,
765	765	.Addsubiw,
766		.Lpm,
767		.Avr31,
768		},
769		CpuInfo(@This()).create(.Atmega128, "atmega128", &[_]FeatureType {
770	766	.Ijmpcall,
771		.Elpmx,
	767	.Avr31,
	768	}),
	769	CpuInfo(@This(), FeatureType).create(.Atmega128, "atmega128", &[_]FeatureType {
	770	.Lpm,
	771	.Elpm,
772	772	.Movw,
773		.Mul,
774		.Sram,
775		.Break,
	773	.Elpmx,
776	774	.Spm,
777		.Elpm,
778		.Lpmx,
779	775	.Avr0,
	776	.Sram,
780	777	.Jmpcall,
781	778	.Addsubiw,
782		.Lpm,
783		.Avr51,
784		},
785		CpuInfo(@This()).create(.Atmega1280, "atmega1280", &[_]FeatureType {
786		.Ijmpcall,
787		.Elpmx,
788		.Movw,
789	779	.Mul,
790		.Sram,
	780	.Lpmx,
	781	.Ijmpcall,
791	782	.Break,
792		.Spm,
	783	.Avr51,
	784	}),
	785	CpuInfo(@This(), FeatureType).create(.Atmega1280, "atmega1280", &[_]FeatureType {
	786	.Lpm,
793	787	.Elpm,
794		.Lpmx,
	788	.Movw,
	789	.Elpmx,
	790	.Spm,
795	791	.Avr0,
	792	.Sram,
796	793	.Jmpcall,
797	794	.Addsubiw,
798		.Lpm,
799		.Avr51,
800		},
801		CpuInfo(@This()).create(.Atmega1281, "atmega1281", &[_]FeatureType {
802		.Ijmpcall,
803		.Elpmx,
804		.Movw,
805	795	.Mul,
806		.Sram,
	796	.Lpmx,
	797	.Ijmpcall,
807	798	.Break,
808		.Spm,
	799	.Avr51,
	800	}),
	801	CpuInfo(@This(), FeatureType).create(.Atmega1281, "atmega1281", &[_]FeatureType {
	802	.Lpm,
809	803	.Elpm,
810		.Lpmx,
	804	.Movw,
	805	.Elpmx,
	806	.Spm,
811	807	.Avr0,
	808	.Sram,
812	809	.Jmpcall,
813	810	.Addsubiw,
814		.Lpm,
815		.Avr51,
816		},
817		CpuInfo(@This()).create(.Atmega1284, "atmega1284", &[_]FeatureType {
818		.Ijmpcall,
819		.Elpmx,
820		.Movw,
821	811	.Mul,
822		.Sram,
	812	.Lpmx,
	813	.Ijmpcall,
823	814	.Break,
824		.Spm,
	815	.Avr51,
	816	}),
	817	CpuInfo(@This(), FeatureType).create(.Atmega1284, "atmega1284", &[_]FeatureType {
	818	.Lpm,
825	819	.Elpm,
826		.Lpmx,
	820	.Movw,
	821	.Elpmx,
	822	.Spm,
827	823	.Avr0,
	824	.Sram,
828	825	.Jmpcall,
829	826	.Addsubiw,
830		.Lpm,
831		.Avr51,
832		},
833		CpuInfo(@This()).create(.Atmega1284p, "atmega1284p", &[_]FeatureType {
834		.Ijmpcall,
835		.Elpmx,
836		.Movw,
837	827	.Mul,
838		.Sram,
	828	.Lpmx,
	829	.Ijmpcall,
839	830	.Break,
840		.Spm,
	831	.Avr51,
	832	}),
	833	CpuInfo(@This(), FeatureType).create(.Atmega1284p, "atmega1284p", &[_]FeatureType {
	834	.Lpm,
841	835	.Elpm,
842		.Lpmx,
	836	.Movw,
	837	.Elpmx,
	838	.Spm,
843	839	.Avr0,
	840	.Sram,
844	841	.Jmpcall,
845	842	.Addsubiw,
846		.Lpm,
847		.Avr51,
848		},
849		CpuInfo(@This()).create(.Atmega1284rfr2, "atmega1284rfr2", &[_]FeatureType {
850		.Ijmpcall,
851		.Elpmx,
852		.Movw,
853	843	.Mul,
854		.Sram,
	844	.Lpmx,
	845	.Ijmpcall,
855	846	.Break,
856		.Spm,
	847	.Avr51,
	848	}),
	849	CpuInfo(@This(), FeatureType).create(.Atmega1284rfr2, "atmega1284rfr2", &[_]FeatureType {
	850	.Lpm,
857	851	.Elpm,
858		.Lpmx,
	852	.Movw,
	853	.Elpmx,
	854	.Spm,
859	855	.Avr0,
	856	.Sram,
860	857	.Jmpcall,
861	858	.Addsubiw,
862		.Lpm,
863		.Avr51,
864		},
865		CpuInfo(@This()).create(.Atmega128a, "atmega128a", &[_]FeatureType {
866		.Ijmpcall,
867		.Elpmx,
868		.Movw,
869	859	.Mul,
870		.Sram,
871		.Break,
872		.Spm,
873		.Elpm,
874	860	.Lpmx,
	861	.Ijmpcall,
	862	.Break,
	863	.Avr51,
	864	}),
	865	CpuInfo(@This(), FeatureType).create(.Atmega128a, "atmega128a", &[_]FeatureType {
	866	.Lpm,
	867	.Elpm,
	868	.Movw,
	869	.Elpmx,
	870	.Spm,
875	871	.Avr0,
	872	.Sram,
876	873	.Jmpcall,
877	874	.Addsubiw,
878		.Lpm,
879		.Avr51,
880		},
881		CpuInfo(@This()).create(.Atmega128rfa1, "atmega128rfa1", &[_]FeatureType {
882		.Ijmpcall,
883		.Elpmx,
884		.Movw,
885	875	.Mul,
886		.Sram,
	876	.Lpmx,
	877	.Ijmpcall,
887	878	.Break,
888		.Spm,
	879	.Avr51,
	880	}),
	881	CpuInfo(@This(), FeatureType).create(.Atmega128rfa1, "atmega128rfa1", &[_]FeatureType {
	882	.Lpm,
889	883	.Elpm,
890		.Lpmx,
	884	.Movw,
	885	.Elpmx,
	886	.Spm,
891	887	.Avr0,
	888	.Sram,
892	889	.Jmpcall,
893	890	.Addsubiw,
894		.Lpm,
895		.Avr51,
896		},
897		CpuInfo(@This()).create(.Atmega128rfr2, "atmega128rfr2", &[_]FeatureType {
898		.Ijmpcall,
899		.Elpmx,
900		.Movw,
901	891	.Mul,
902		.Sram,
	892	.Lpmx,
	893	.Ijmpcall,
903	894	.Break,
904		.Spm,
	895	.Avr51,
	896	}),
	897	CpuInfo(@This(), FeatureType).create(.Atmega128rfr2, "atmega128rfr2", &[_]FeatureType {
	898	.Lpm,
905	899	.Elpm,
906		.Lpmx,
	900	.Movw,
	901	.Elpmx,
	902	.Spm,
907	903	.Avr0,
	904	.Sram,
908	905	.Jmpcall,
909	906	.Addsubiw,
910		.Lpm,
911		.Avr51,
912		},
913		CpuInfo(@This()).create(.Atmega16, "atmega16", &[_]FeatureType {
914		.Ijmpcall,
915		.Movw,
916	907	.Mul,
917		.Sram,
	908	.Lpmx,
	909	.Ijmpcall,
918	910	.Break,
	911	.Avr51,
	912	}),
	913	CpuInfo(@This(), FeatureType).create(.Atmega16, "atmega16", &[_]FeatureType {
	914	.Lpm,
	915	.Movw,
919	916	.Spm,
920		.Lpmx,
921	917	.Avr0,
	918	.Sram,
922	919	.Jmpcall,
923	920	.Addsubiw,
924		.Lpm,
925		.Avr5,
926		},
927		CpuInfo(@This()).create(.Atmega161, "atmega161", &[_]FeatureType {
	921	.Mul,
	922	.Lpmx,
928	923	.Ijmpcall,
929		.Sram,
	924	.Break,
	925	.Avr5,
	926	}),
	927	CpuInfo(@This(), FeatureType).create(.Atmega161, "atmega161", &[_]FeatureType {
	928	.Lpm,
930	929	.Avr0,
	930	.Sram,
931	931	.Jmpcall,
932	932	.Addsubiw,
933		.Lpm,
	933	.Ijmpcall,
934	934	.Avr3,
935	935	.Lpmx,
936	936	.Movw,
937	937	.Mul,
938	938	.Spm,
939		},
940		CpuInfo(@This()).create(.Atmega162, "atmega162", &[_]FeatureType {
941		.Ijmpcall,
	939	}),
	940	CpuInfo(@This(), FeatureType).create(.Atmega162, "atmega162", &[_]FeatureType {
	941	.Lpm,
942	942	.Movw,
943		.Mul,
944		.Sram,
945		.Break,
946	943	.Spm,
947		.Lpmx,
948	944	.Avr0,
	945	.Sram,
949	946	.Jmpcall,
950	947	.Addsubiw,
951		.Lpm,
952		.Avr5,
953		},
954		CpuInfo(@This()).create(.Atmega163, "atmega163", &[_]FeatureType {
	948	.Mul,
	949	.Lpmx,
955	950	.Ijmpcall,
956		.Sram,
	951	.Break,
	952	.Avr5,
	953	}),
	954	CpuInfo(@This(), FeatureType).create(.Atmega163, "atmega163", &[_]FeatureType {
	955	.Lpm,
957	956	.Avr0,
	957	.Sram,
958	958	.Jmpcall,
959	959	.Addsubiw,
960		.Lpm,
	960	.Ijmpcall,
961	961	.Avr3,
962	962	.Lpmx,
963	963	.Movw,
964	964	.Mul,
965	965	.Spm,
966		},
967		CpuInfo(@This()).create(.Atmega164a, "atmega164a", &[_]FeatureType {
968		.Ijmpcall,
	966	}),
	967	CpuInfo(@This(), FeatureType).create(.Atmega164a, "atmega164a", &[_]FeatureType {
	968	.Lpm,
969	969	.Movw,
970		.Mul,
971		.Sram,
972		.Break,
973	970	.Spm,
974		.Lpmx,
975	971	.Avr0,
	972	.Sram,
976	973	.Jmpcall,
977	974	.Addsubiw,
978		.Lpm,
979		.Avr5,
980		},
981		CpuInfo(@This()).create(.Atmega164p, "atmega164p", &[_]FeatureType {
982		.Ijmpcall,
983		.Movw,
984	975	.Mul,
985		.Sram,
986		.Break,
987		.Spm,
988	976	.Lpmx,
989		.Avr0,
990		.Jmpcall,
991		.Addsubiw,
992		.Lpm,
993		.Avr5,
994		},
995		CpuInfo(@This()).create(.Atmega164pa, "atmega164pa", &[_]FeatureType {
996	977	.Ijmpcall,
997		.Movw,
998		.Mul,
999		.Sram,
1000	978	.Break,
	979	.Avr5,
	980	}),
	981	CpuInfo(@This(), FeatureType).create(.Atmega164p, "atmega164p", &[_]FeatureType {
	982	.Lpm,
	983	.Movw,
1001	984	.Spm,
1002		.Lpmx,
1003	985	.Avr0,
	986	.Sram,
1004	987	.Jmpcall,
1005	988	.Addsubiw,
1006		.Lpm,
1007		.Avr5,
1008		},
1009		CpuInfo(@This()).create(.Atmega165, "atmega165", &[_]FeatureType {
1010		.Ijmpcall,
1011		.Movw,
1012	989	.Mul,
1013		.Sram,
	990	.Lpmx,
	991	.Ijmpcall,
1014	992	.Break,
	993	.Avr5,
	994	}),
	995	CpuInfo(@This(), FeatureType).create(.Atmega164pa, "atmega164pa", &[_]FeatureType {
	996	.Lpm,
	997	.Movw,
1015	998	.Spm,
1016		.Lpmx,
1017	999	.Avr0,
	1000	.Sram,
1018	1001	.Jmpcall,
1019	1002	.Addsubiw,
1020		.Lpm,
1021		.Avr5,
1022		},
1023		CpuInfo(@This()).create(.Atmega165a, "atmega165a", &[_]FeatureType {
1024		.Ijmpcall,
1025		.Movw,
1026	1003	.Mul,
1027		.Sram,
	1004	.Lpmx,
	1005	.Ijmpcall,
1028	1006	.Break,
	1007	.Avr5,
	1008	}),
	1009	CpuInfo(@This(), FeatureType).create(.Atmega165, "atmega165", &[_]FeatureType {
	1010	.Lpm,
	1011	.Movw,
1029	1012	.Spm,
1030		.Lpmx,
1031	1013	.Avr0,
	1014	.Sram,
1032	1015	.Jmpcall,
1033	1016	.Addsubiw,
1034		.Lpm,
1035		.Avr5,
1036		},
1037		CpuInfo(@This()).create(.Atmega165p, "atmega165p", &[_]FeatureType {
1038		.Ijmpcall,
1039		.Movw,
1040	1017	.Mul,
1041		.Sram,
	1018	.Lpmx,
	1019	.Ijmpcall,
1042	1020	.Break,
	1021	.Avr5,
	1022	}),
	1023	CpuInfo(@This(), FeatureType).create(.Atmega165a, "atmega165a", &[_]FeatureType {
	1024	.Lpm,
	1025	.Movw,
1043	1026	.Spm,
1044		.Lpmx,
1045	1027	.Avr0,
	1028	.Sram,
1046	1029	.Jmpcall,
1047	1030	.Addsubiw,
1048		.Lpm,
1049		.Avr5,
1050		},
1051		CpuInfo(@This()).create(.Atmega165pa, "atmega165pa", &[_]FeatureType {
1052		.Ijmpcall,
1053		.Movw,
1054	1031	.Mul,
1055		.Sram,
	1032	.Lpmx,
	1033	.Ijmpcall,
1056	1034	.Break,
	1035	.Avr5,
	1036	}),
	1037	CpuInfo(@This(), FeatureType).create(.Atmega165p, "atmega165p", &[_]FeatureType {
	1038	.Lpm,
	1039	.Movw,
1057	1040	.Spm,
1058		.Lpmx,
1059	1041	.Avr0,
	1042	.Sram,
1060	1043	.Jmpcall,
1061	1044	.Addsubiw,
1062		.Lpm,
1063		.Avr5,
1064		},
1065		CpuInfo(@This()).create(.Atmega168, "atmega168", &[_]FeatureType {
1066		.Ijmpcall,
1067		.Movw,
1068	1045	.Mul,
1069		.Sram,
	1046	.Lpmx,
	1047	.Ijmpcall,
1070	1048	.Break,
	1049	.Avr5,
	1050	}),
	1051	CpuInfo(@This(), FeatureType).create(.Atmega165pa, "atmega165pa", &[_]FeatureType {
	1052	.Lpm,
	1053	.Movw,
1071	1054	.Spm,
1072		.Lpmx,
1073	1055	.Avr0,
	1056	.Sram,
1074	1057	.Jmpcall,
1075	1058	.Addsubiw,
1076		.Lpm,
1077		.Avr5,
1078		},
1079		CpuInfo(@This()).create(.Atmega168a, "atmega168a", &[_]FeatureType {
1080		.Ijmpcall,
1081		.Movw,
1082	1059	.Mul,
1083		.Sram,
	1060	.Lpmx,
	1061	.Ijmpcall,
1084	1062	.Break,
	1063	.Avr5,
	1064	}),
	1065	CpuInfo(@This(), FeatureType).create(.Atmega168, "atmega168", &[_]FeatureType {
	1066	.Lpm,
	1067	.Movw,
1085	1068	.Spm,
1086		.Lpmx,
1087	1069	.Avr0,
	1070	.Sram,
1088	1071	.Jmpcall,
1089	1072	.Addsubiw,
1090		.Lpm,
1091		.Avr5,
1092		},
1093		CpuInfo(@This()).create(.Atmega168p, "atmega168p", &[_]FeatureType {
1094		.Ijmpcall,
1095		.Movw,
1096	1073	.Mul,
1097		.Sram,
	1074	.Lpmx,
	1075	.Ijmpcall,
1098	1076	.Break,
	1077	.Avr5,
	1078	}),
	1079	CpuInfo(@This(), FeatureType).create(.Atmega168a, "atmega168a", &[_]FeatureType {
	1080	.Lpm,
	1081	.Movw,
1099	1082	.Spm,
1100		.Lpmx,
1101	1083	.Avr0,
	1084	.Sram,
1102	1085	.Jmpcall,
1103	1086	.Addsubiw,
1104		.Lpm,
1105		.Avr5,
1106		},
1107		CpuInfo(@This()).create(.Atmega168pa, "atmega168pa", &[_]FeatureType {
1108		.Ijmpcall,
1109		.Movw,
1110	1087	.Mul,
1111		.Sram,
	1088	.Lpmx,
	1089	.Ijmpcall,
1112	1090	.Break,
	1091	.Avr5,
	1092	}),
	1093	CpuInfo(@This(), FeatureType).create(.Atmega168p, "atmega168p", &[_]FeatureType {
	1094	.Lpm,
	1095	.Movw,
1113	1096	.Spm,
1114		.Lpmx,
1115	1097	.Avr0,
	1098	.Sram,
1116	1099	.Jmpcall,
1117	1100	.Addsubiw,
1118		.Lpm,
1119		.Avr5,
1120		},
1121		CpuInfo(@This()).create(.Atmega169, "atmega169", &[_]FeatureType {
1122		.Ijmpcall,
1123		.Movw,
1124	1101	.Mul,
1125		.Sram,
	1102	.Lpmx,
	1103	.Ijmpcall,
1126	1104	.Break,
	1105	.Avr5,
	1106	}),
	1107	CpuInfo(@This(), FeatureType).create(.Atmega168pa, "atmega168pa", &[_]FeatureType {
	1108	.Lpm,
	1109	.Movw,
1127	1110	.Spm,
1128		.Lpmx,
1129	1111	.Avr0,
	1112	.Sram,
1130	1113	.Jmpcall,
1131	1114	.Addsubiw,
1132		.Lpm,
1133		.Avr5,
1134		},
1135		CpuInfo(@This()).create(.Atmega169a, "atmega169a", &[_]FeatureType {
1136		.Ijmpcall,
1137		.Movw,
1138	1115	.Mul,
1139		.Sram,
	1116	.Lpmx,
	1117	.Ijmpcall,
1140	1118	.Break,
	1119	.Avr5,
	1120	}),
	1121	CpuInfo(@This(), FeatureType).create(.Atmega169, "atmega169", &[_]FeatureType {
	1122	.Lpm,
	1123	.Movw,
1141	1124	.Spm,
1142		.Lpmx,
1143	1125	.Avr0,
	1126	.Sram,
1144	1127	.Jmpcall,
1145	1128	.Addsubiw,
1146		.Lpm,
1147		.Avr5,
1148		},
1149		CpuInfo(@This()).create(.Atmega169p, "atmega169p", &[_]FeatureType {
1150		.Ijmpcall,
1151		.Movw,
1152	1129	.Mul,
1153		.Sram,
	1130	.Lpmx,
	1131	.Ijmpcall,
1154	1132	.Break,
	1133	.Avr5,
	1134	}),
	1135	CpuInfo(@This(), FeatureType).create(.Atmega169a, "atmega169a", &[_]FeatureType {
	1136	.Lpm,
	1137	.Movw,
1155	1138	.Spm,
1156		.Lpmx,
1157	1139	.Avr0,
	1140	.Sram,
1158	1141	.Jmpcall,
1159	1142	.Addsubiw,
1160		.Lpm,
1161		.Avr5,
1162		},
1163		CpuInfo(@This()).create(.Atmega169pa, "atmega169pa", &[_]FeatureType {
1164		.Ijmpcall,
1165		.Movw,
1166	1143	.Mul,
1167		.Sram,
	1144	.Lpmx,
	1145	.Ijmpcall,
1168	1146	.Break,
	1147	.Avr5,
	1148	}),
	1149	CpuInfo(@This(), FeatureType).create(.Atmega169p, "atmega169p", &[_]FeatureType {
	1150	.Lpm,
	1151	.Movw,
1169	1152	.Spm,
1170		.Lpmx,
1171	1153	.Avr0,
	1154	.Sram,
1172	1155	.Jmpcall,
1173	1156	.Addsubiw,
1174		.Lpm,
1175		.Avr5,
1176		},
1177		CpuInfo(@This()).create(.Atmega16a, "atmega16a", &[_]FeatureType {
1178		.Ijmpcall,
1179		.Movw,
1180	1157	.Mul,
1181		.Sram,
	1158	.Lpmx,
	1159	.Ijmpcall,
1182	1160	.Break,
	1161	.Avr5,
	1162	}),
	1163	CpuInfo(@This(), FeatureType).create(.Atmega169pa, "atmega169pa", &[_]FeatureType {
	1164	.Lpm,
	1165	.Movw,
1183	1166	.Spm,
1184		.Lpmx,
1185	1167	.Avr0,
	1168	.Sram,
1186	1169	.Jmpcall,
1187	1170	.Addsubiw,
1188		.Lpm,
1189		.Avr5,
1190		},
1191		CpuInfo(@This()).create(.Atmega16hva, "atmega16hva", &[_]FeatureType {
1192		.Ijmpcall,
1193		.Movw,
1194	1171	.Mul,
1195		.Sram,
	1172	.Lpmx,
	1173	.Ijmpcall,
1196	1174	.Break,
	1175	.Avr5,
	1176	}),
	1177	CpuInfo(@This(), FeatureType).create(.Atmega16a, "atmega16a", &[_]FeatureType {
	1178	.Lpm,
	1179	.Movw,
1197	1180	.Spm,
1198		.Lpmx,
1199	1181	.Avr0,
	1182	.Sram,
1200	1183	.Jmpcall,
1201	1184	.Addsubiw,
1202		.Lpm,
1203		.Avr5,
1204		},
1205		CpuInfo(@This()).create(.Atmega16hva2, "atmega16hva2", &[_]FeatureType {
1206		.Ijmpcall,
1207		.Movw,
1208	1185	.Mul,
1209		.Sram,
	1186	.Lpmx,
	1187	.Ijmpcall,
1210	1188	.Break,
	1189	.Avr5,
	1190	}),
	1191	CpuInfo(@This(), FeatureType).create(.Atmega16hva, "atmega16hva", &[_]FeatureType {
	1192	.Lpm,
	1193	.Movw,
1211	1194	.Spm,
1212		.Lpmx,
1213	1195	.Avr0,
	1196	.Sram,
1214	1197	.Jmpcall,
1215	1198	.Addsubiw,
1216		.Lpm,
1217		.Avr5,
1218		},
1219		CpuInfo(@This()).create(.Atmega16hvb, "atmega16hvb", &[_]FeatureType {
1220		.Ijmpcall,
1221		.Movw,
1222	1199	.Mul,
1223		.Sram,
	1200	.Lpmx,
	1201	.Ijmpcall,
1224	1202	.Break,
	1203	.Avr5,
	1204	}),
	1205	CpuInfo(@This(), FeatureType).create(.Atmega16hva2, "atmega16hva2", &[_]FeatureType {
	1206	.Lpm,
	1207	.Movw,
1225	1208	.Spm,
1226		.Lpmx,
1227	1209	.Avr0,
	1210	.Sram,
1228	1211	.Jmpcall,
1229	1212	.Addsubiw,
1230		.Lpm,
1231		.Avr5,
1232		},
1233		CpuInfo(@This()).create(.Atmega16hvbrevb, "atmega16hvbrevb", &[_]FeatureType {
1234		.Ijmpcall,
1235		.Movw,
1236	1213	.Mul,
1237		.Sram,
	1214	.Lpmx,
	1215	.Ijmpcall,
1238	1216	.Break,
	1217	.Avr5,
	1218	}),
	1219	CpuInfo(@This(), FeatureType).create(.Atmega16hvb, "atmega16hvb", &[_]FeatureType {
	1220	.Lpm,
	1221	.Movw,
1239	1222	.Spm,
1240		.Lpmx,
1241	1223	.Avr0,
	1224	.Sram,
1242	1225	.Jmpcall,
1243	1226	.Addsubiw,
1244		.Lpm,
1245		.Avr5,
1246		},
1247		CpuInfo(@This()).create(.Atmega16m1, "atmega16m1", &[_]FeatureType {
1248		.Ijmpcall,
1249		.Movw,
1250	1227	.Mul,
1251		.Sram,
	1228	.Lpmx,
	1229	.Ijmpcall,
1252	1230	.Break,
	1231	.Avr5,
	1232	}),
	1233	CpuInfo(@This(), FeatureType).create(.Atmega16hvbrevb, "atmega16hvbrevb", &[_]FeatureType {
	1234	.Lpm,
	1235	.Movw,
1253	1236	.Spm,
1254		.Lpmx,
1255	1237	.Avr0,
	1238	.Sram,
1256	1239	.Jmpcall,
1257	1240	.Addsubiw,
1258		.Lpm,
1259		.Avr5,
1260		},
1261		CpuInfo(@This()).create(.Atmega16u2, "atmega16u2", &[_]FeatureType {
	1241	.Mul,
	1242	.Lpmx,
1262	1243	.Ijmpcall,
1263		.Movw,
1264		.Sram,
1265	1244	.Break,
	1245	.Avr5,
	1246	}),
	1247	CpuInfo(@This(), FeatureType).create(.Atmega16m1, "atmega16m1", &[_]FeatureType {
	1248	.Lpm,
	1249	.Movw,
1266	1250	.Spm,
1267		.Lpmx,
1268	1251	.Avr0,
	1252	.Sram,
1269	1253	.Jmpcall,
1270	1254	.Addsubiw,
1271		.Lpm,
1272		.Avr35,
1273		},
1274		CpuInfo(@This()).create(.Atmega16u4, "atmega16u4", &[_]FeatureType {
1275		.Ijmpcall,
1276		.Movw,
1277	1255	.Mul,
1278		.Sram,
	1256	.Lpmx,
	1257	.Ijmpcall,
1279	1258	.Break,
	1259	.Avr5,
	1260	}),
	1261	CpuInfo(@This(), FeatureType).create(.Atmega16u2, "atmega16u2", &[_]FeatureType {
	1262	.Lpm,
	1263	.Movw,
1280	1264	.Spm,
1281		.Lpmx,
1282	1265	.Avr0,
	1266	.Sram,
1283	1267	.Jmpcall,
1284	1268	.Addsubiw,
1285		.Lpm,
1286		.Avr5,
1287		},
1288		CpuInfo(@This()).create(.Atmega2560, "atmega2560", &[_]FeatureType {
	1269	.Lpmx,
1289	1270	.Ijmpcall,
1290		.Elpmx,
1291		.Movw,
1292		.Mul,
1293		.Sram,
1294	1271	.Break,
	1272	.Avr35,
	1273	}),
	1274	CpuInfo(@This(), FeatureType).create(.Atmega16u4, "atmega16u4", &[_]FeatureType {
	1275	.Lpm,
	1276	.Movw,
1295	1277	.Spm,
1296		.Elpm,
1297		.Lpmx,
1298	1278	.Avr0,
	1279	.Sram,
1299	1280	.Jmpcall,
1300	1281	.Addsubiw,
1301		.Lpm,
1302		.Avr6,
1303		},
1304		CpuInfo(@This()).create(.Atmega2561, "atmega2561", &[_]FeatureType {
1305		.Ijmpcall,
1306		.Elpmx,
1307		.Movw,
1308	1282	.Mul,
1309		.Sram,
	1283	.Lpmx,
	1284	.Ijmpcall,
1310	1285	.Break,
1311		.Spm,
	1286	.Avr5,
	1287	}),
	1288	CpuInfo(@This(), FeatureType).create(.Atmega2560, "atmega2560", &[_]FeatureType {
	1289	.Lpm,
1312	1290	.Elpm,
1313		.Lpmx,
	1291	.Movw,
	1292	.Elpmx,
	1293	.Spm,
1314	1294	.Avr0,
	1295	.Sram,
1315	1296	.Jmpcall,
1316	1297	.Addsubiw,
1317		.Lpm,
1318		.Avr6,
1319		},
1320		CpuInfo(@This()).create(.Atmega2564rfr2, "atmega2564rfr2", &[_]FeatureType {
1321		.Ijmpcall,
1322		.Elpmx,
1323		.Movw,
1324	1298	.Mul,
1325		.Sram,
	1299	.Lpmx,
	1300	.Ijmpcall,
1326	1301	.Break,
1327		.Spm,
	1302	.Avr6,
	1303	}),
	1304	CpuInfo(@This(), FeatureType).create(.Atmega2561, "atmega2561", &[_]FeatureType {
	1305	.Lpm,
1328	1306	.Elpm,
1329		.Lpmx,
	1307	.Movw,
	1308	.Elpmx,
	1309	.Spm,
1330	1310	.Avr0,
	1311	.Sram,
1331	1312	.Jmpcall,
1332	1313	.Addsubiw,
1333		.Lpm,
1334		.Avr6,
1335		},
1336		CpuInfo(@This()).create(.Atmega256rfr2, "atmega256rfr2", &[_]FeatureType {
1337		.Ijmpcall,
1338		.Elpmx,
1339		.Movw,
1340	1314	.Mul,
1341		.Sram,
	1315	.Lpmx,
	1316	.Ijmpcall,
1342	1317	.Break,
1343		.Spm,
	1318	.Avr6,
	1319	}),
	1320	CpuInfo(@This(), FeatureType).create(.Atmega2564rfr2, "atmega2564rfr2", &[_]FeatureType {
	1321	.Lpm,
1344	1322	.Elpm,
1345		.Lpmx,
	1323	.Movw,
	1324	.Elpmx,
	1325	.Spm,
1346	1326	.Avr0,
	1327	.Sram,
1347	1328	.Jmpcall,
1348	1329	.Addsubiw,
1349		.Lpm,
1350		.Avr6,
1351		},
1352		CpuInfo(@This()).create(.Atmega32, "atmega32", &[_]FeatureType {
1353		.Ijmpcall,
1354		.Movw,
1355	1330	.Mul,
1356		.Sram,
	1331	.Lpmx,
	1332	.Ijmpcall,
1357	1333	.Break,
	1334	.Avr6,
	1335	}),
	1336	CpuInfo(@This(), FeatureType).create(.Atmega256rfr2, "atmega256rfr2", &[_]FeatureType {
	1337	.Lpm,
	1338	.Elpm,
	1339	.Movw,
	1340	.Elpmx,
1358	1341	.Spm,
1359		.Lpmx,
1360	1342	.Avr0,
	1343	.Sram,
1361	1344	.Jmpcall,
1362	1345	.Addsubiw,
1363		.Lpm,
1364		.Avr5,
1365		},
1366		CpuInfo(@This()).create(.Atmega323, "atmega323", &[_]FeatureType {
1367		.Ijmpcall,
1368		.Movw,
1369	1346	.Mul,
1370		.Sram,
	1347	.Lpmx,
	1348	.Ijmpcall,
1371	1349	.Break,
	1350	.Avr6,
	1351	}),
	1352	CpuInfo(@This(), FeatureType).create(.Atmega32, "atmega32", &[_]FeatureType {
	1353	.Lpm,
	1354	.Movw,
1372	1355	.Spm,
1373		.Lpmx,
1374	1356	.Avr0,
	1357	.Sram,
1375	1358	.Jmpcall,
1376	1359	.Addsubiw,
1377		.Lpm,
1378		.Avr5,
1379		},
1380		CpuInfo(@This()).create(.Atmega324a, "atmega324a", &[_]FeatureType {
1381		.Ijmpcall,
1382		.Movw,
1383	1360	.Mul,
1384		.Sram,
	1361	.Lpmx,
	1362	.Ijmpcall,
1385	1363	.Break,
	1364	.Avr5,
	1365	}),
	1366	CpuInfo(@This(), FeatureType).create(.Atmega323, "atmega323", &[_]FeatureType {
	1367	.Lpm,
	1368	.Movw,
1386	1369	.Spm,
1387		.Lpmx,
1388	1370	.Avr0,
	1371	.Sram,
1389	1372	.Jmpcall,
1390	1373	.Addsubiw,
1391		.Lpm,
1392		.Avr5,
1393		},
1394		CpuInfo(@This()).create(.Atmega324p, "atmega324p", &[_]FeatureType {
1395		.Ijmpcall,
1396		.Movw,
1397	1374	.Mul,
1398		.Sram,
	1375	.Lpmx,
	1376	.Ijmpcall,
1399	1377	.Break,
	1378	.Avr5,
	1379	}),
	1380	CpuInfo(@This(), FeatureType).create(.Atmega324a, "atmega324a", &[_]FeatureType {
	1381	.Lpm,
	1382	.Movw,
1400	1383	.Spm,
1401		.Lpmx,
1402	1384	.Avr0,
	1385	.Sram,
1403	1386	.Jmpcall,
1404	1387	.Addsubiw,
1405		.Lpm,
1406		.Avr5,
1407		},
1408		CpuInfo(@This()).create(.Atmega324pa, "atmega324pa", &[_]FeatureType {
1409		.Ijmpcall,
1410		.Movw,
1411	1388	.Mul,
1412		.Sram,
	1389	.Lpmx,
	1390	.Ijmpcall,
1413	1391	.Break,
	1392	.Avr5,
	1393	}),
	1394	CpuInfo(@This(), FeatureType).create(.Atmega324p, "atmega324p", &[_]FeatureType {
	1395	.Lpm,
	1396	.Movw,
1414	1397	.Spm,
1415		.Lpmx,
1416	1398	.Avr0,
	1399	.Sram,
1417	1400	.Jmpcall,
1418	1401	.Addsubiw,
1419		.Lpm,
1420		.Avr5,
1421		},
1422		CpuInfo(@This()).create(.Atmega325, "atmega325", &[_]FeatureType {
1423		.Ijmpcall,
1424		.Movw,
1425	1402	.Mul,
1426		.Sram,
	1403	.Lpmx,
	1404	.Ijmpcall,
1427	1405	.Break,
	1406	.Avr5,
	1407	}),
	1408	CpuInfo(@This(), FeatureType).create(.Atmega324pa, "atmega324pa", &[_]FeatureType {
	1409	.Lpm,
	1410	.Movw,
1428	1411	.Spm,
1429		.Lpmx,
1430	1412	.Avr0,
	1413	.Sram,
1431	1414	.Jmpcall,
1432	1415	.Addsubiw,
1433		.Lpm,
1434		.Avr5,
1435		},
1436		CpuInfo(@This()).create(.Atmega3250, "atmega3250", &[_]FeatureType {
1437		.Ijmpcall,
1438		.Movw,
1439	1416	.Mul,
1440		.Sram,
	1417	.Lpmx,
	1418	.Ijmpcall,
1441	1419	.Break,
	1420	.Avr5,
	1421	}),
	1422	CpuInfo(@This(), FeatureType).create(.Atmega325, "atmega325", &[_]FeatureType {
	1423	.Lpm,
	1424	.Movw,
1442	1425	.Spm,
1443		.Lpmx,
1444	1426	.Avr0,
	1427	.Sram,
1445	1428	.Jmpcall,
1446	1429	.Addsubiw,
1447		.Lpm,
1448		.Avr5,
1449		},
1450		CpuInfo(@This()).create(.Atmega3250a, "atmega3250a", &[_]FeatureType {
1451		.Ijmpcall,
1452		.Movw,
1453	1430	.Mul,
1454		.Sram,
	1431	.Lpmx,
	1432	.Ijmpcall,
1455	1433	.Break,
	1434	.Avr5,
	1435	}),
	1436	CpuInfo(@This(), FeatureType).create(.Atmega3250, "atmega3250", &[_]FeatureType {
	1437	.Lpm,
	1438	.Movw,
1456	1439	.Spm,
1457		.Lpmx,
1458	1440	.Avr0,
	1441	.Sram,
1459	1442	.Jmpcall,
1460	1443	.Addsubiw,
1461		.Lpm,
1462		.Avr5,
1463		},
1464		CpuInfo(@This()).create(.Atmega3250p, "atmega3250p", &[_]FeatureType {
1465		.Ijmpcall,
1466		.Movw,
1467	1444	.Mul,
1468		.Sram,
1469		.Break,
1470		.Spm,
1471	1445	.Lpmx,
1472		.Avr0,
1473		.Jmpcall,
1474		.Addsubiw,
1475		.Lpm,
1476		.Avr5,
1477		},
1478		CpuInfo(@This()).create(.Atmega3250pa, "atmega3250pa", &[_]FeatureType {
1479	1446	.Ijmpcall,
1480		.Movw,
1481		.Mul,
1482		.Sram,
1483	1447	.Break,
	1448	.Avr5,
	1449	}),
	1450	CpuInfo(@This(), FeatureType).create(.Atmega3250a, "atmega3250a", &[_]FeatureType {
	1451	.Lpm,
	1452	.Movw,
1484	1453	.Spm,
1485		.Lpmx,
1486	1454	.Avr0,
	1455	.Sram,
1487	1456	.Jmpcall,
1488	1457	.Addsubiw,
1489		.Lpm,
1490		.Avr5,
1491		},
1492		CpuInfo(@This()).create(.Atmega325a, "atmega325a", &[_]FeatureType {
1493		.Ijmpcall,
1494		.Movw,
1495	1458	.Mul,
1496		.Sram,
	1459	.Lpmx,
	1460	.Ijmpcall,
1497	1461	.Break,
	1462	.Avr5,
	1463	}),
	1464	CpuInfo(@This(), FeatureType).create(.Atmega3250p, "atmega3250p", &[_]FeatureType {
	1465	.Lpm,
	1466	.Movw,
1498	1467	.Spm,
1499		.Lpmx,
1500	1468	.Avr0,
	1469	.Sram,
1501	1470	.Jmpcall,
1502	1471	.Addsubiw,
1503		.Lpm,
1504		.Avr5,
1505		},
1506		CpuInfo(@This()).create(.Atmega325p, "atmega325p", &[_]FeatureType {
1507		.Ijmpcall,
1508		.Movw,
1509	1472	.Mul,
1510		.Sram,
	1473	.Lpmx,
	1474	.Ijmpcall,
1511	1475	.Break,
	1476	.Avr5,
	1477	}),
	1478	CpuInfo(@This(), FeatureType).create(.Atmega3250pa, "atmega3250pa", &[_]FeatureType {
	1479	.Lpm,
	1480	.Movw,
1512	1481	.Spm,
1513		.Lpmx,
1514	1482	.Avr0,
	1483	.Sram,
1515	1484	.Jmpcall,
1516	1485	.Addsubiw,
1517		.Lpm,
1518		.Avr5,
1519		},
1520		CpuInfo(@This()).create(.Atmega325pa, "atmega325pa", &[_]FeatureType {
1521		.Ijmpcall,
1522		.Movw,
1523	1486	.Mul,
1524		.Sram,
	1487	.Lpmx,
	1488	.Ijmpcall,
1525	1489	.Break,
	1490	.Avr5,
	1491	}),
	1492	CpuInfo(@This(), FeatureType).create(.Atmega325a, "atmega325a", &[_]FeatureType {
	1493	.Lpm,
	1494	.Movw,
1526	1495	.Spm,
1527		.Lpmx,
1528	1496	.Avr0,
	1497	.Sram,
1529	1498	.Jmpcall,
1530	1499	.Addsubiw,
1531		.Lpm,
1532		.Avr5,
1533		},
1534		CpuInfo(@This()).create(.Atmega328, "atmega328", &[_]FeatureType {
1535		.Ijmpcall,
1536		.Movw,
1537	1500	.Mul,
1538		.Sram,
	1501	.Lpmx,
	1502	.Ijmpcall,
1539	1503	.Break,
	1504	.Avr5,
	1505	}),
	1506	CpuInfo(@This(), FeatureType).create(.Atmega325p, "atmega325p", &[_]FeatureType {
	1507	.Lpm,
	1508	.Movw,
1540	1509	.Spm,
1541		.Lpmx,
1542	1510	.Avr0,
	1511	.Sram,
1543	1512	.Jmpcall,
1544	1513	.Addsubiw,
1545		.Lpm,
1546		.Avr5,
1547		},
1548		CpuInfo(@This()).create(.Atmega328p, "atmega328p", &[_]FeatureType {
1549		.Ijmpcall,
1550		.Movw,
1551	1514	.Mul,
1552		.Sram,
	1515	.Lpmx,
	1516	.Ijmpcall,
1553	1517	.Break,
	1518	.Avr5,
	1519	}),
	1520	CpuInfo(@This(), FeatureType).create(.Atmega325pa, "atmega325pa", &[_]FeatureType {
	1521	.Lpm,
	1522	.Movw,
1554	1523	.Spm,
1555		.Lpmx,
1556	1524	.Avr0,
	1525	.Sram,
1557	1526	.Jmpcall,
1558	1527	.Addsubiw,
1559		.Lpm,
1560		.Avr5,
1561		},
1562		CpuInfo(@This()).create(.Atmega329, "atmega329", &[_]FeatureType {
1563		.Ijmpcall,
1564		.Movw,
1565	1528	.Mul,
1566		.Sram,
	1529	.Lpmx,
	1530	.Ijmpcall,
1567	1531	.Break,
	1532	.Avr5,
	1533	}),
	1534	CpuInfo(@This(), FeatureType).create(.Atmega328, "atmega328", &[_]FeatureType {
	1535	.Lpm,
	1536	.Movw,
1568	1537	.Spm,
1569		.Lpmx,
1570	1538	.Avr0,
	1539	.Sram,
1571	1540	.Jmpcall,
1572	1541	.Addsubiw,
1573		.Lpm,
1574		.Avr5,
1575		},
1576		CpuInfo(@This()).create(.Atmega3290, "atmega3290", &[_]FeatureType {
1577		.Ijmpcall,
1578		.Movw,
1579	1542	.Mul,
1580		.Sram,
	1543	.Lpmx,
	1544	.Ijmpcall,
1581	1545	.Break,
	1546	.Avr5,
	1547	}),
	1548	CpuInfo(@This(), FeatureType).create(.Atmega328p, "atmega328p", &[_]FeatureType {
	1549	.Lpm,
	1550	.Movw,
1582	1551	.Spm,
1583		.Lpmx,
1584	1552	.Avr0,
	1553	.Sram,
1585	1554	.Jmpcall,
1586	1555	.Addsubiw,
1587		.Lpm,
1588		.Avr5,
1589		},
1590		CpuInfo(@This()).create(.Atmega3290a, "atmega3290a", &[_]FeatureType {
1591		.Ijmpcall,
1592		.Movw,
1593	1556	.Mul,
1594		.Sram,
	1557	.Lpmx,
	1558	.Ijmpcall,
1595	1559	.Break,
	1560	.Avr5,
	1561	}),
	1562	CpuInfo(@This(), FeatureType).create(.Atmega329, "atmega329", &[_]FeatureType {
	1563	.Lpm,
	1564	.Movw,
1596	1565	.Spm,
1597		.Lpmx,
1598	1566	.Avr0,
	1567	.Sram,
1599	1568	.Jmpcall,
1600	1569	.Addsubiw,
1601		.Lpm,
1602		.Avr5,
1603		},
1604		CpuInfo(@This()).create(.Atmega3290p, "atmega3290p", &[_]FeatureType {
1605		.Ijmpcall,
1606		.Movw,
1607	1570	.Mul,
1608		.Sram,
	1571	.Lpmx,
	1572	.Ijmpcall,
1609	1573	.Break,
	1574	.Avr5,
	1575	}),
	1576	CpuInfo(@This(), FeatureType).create(.Atmega3290, "atmega3290", &[_]FeatureType {
	1577	.Lpm,
	1578	.Movw,
1610	1579	.Spm,
1611		.Lpmx,
1612	1580	.Avr0,
	1581	.Sram,
1613	1582	.Jmpcall,
1614	1583	.Addsubiw,
1615		.Lpm,
1616		.Avr5,
1617		},
1618		CpuInfo(@This()).create(.Atmega3290pa, "atmega3290pa", &[_]FeatureType {
1619		.Ijmpcall,
1620		.Movw,
1621	1584	.Mul,
1622		.Sram,
	1585	.Lpmx,
	1586	.Ijmpcall,
1623	1587	.Break,
	1588	.Avr5,
	1589	}),
	1590	CpuInfo(@This(), FeatureType).create(.Atmega3290a, "atmega3290a", &[_]FeatureType {
	1591	.Lpm,
	1592	.Movw,
1624	1593	.Spm,
1625		.Lpmx,
1626	1594	.Avr0,
	1595	.Sram,
1627	1596	.Jmpcall,
1628	1597	.Addsubiw,
1629		.Lpm,
1630		.Avr5,
1631		},
1632		CpuInfo(@This()).create(.Atmega329a, "atmega329a", &[_]FeatureType {
1633		.Ijmpcall,
1634		.Movw,
1635	1598	.Mul,
1636		.Sram,
	1599	.Lpmx,
	1600	.Ijmpcall,
1637	1601	.Break,
	1602	.Avr5,
	1603	}),
	1604	CpuInfo(@This(), FeatureType).create(.Atmega3290p, "atmega3290p", &[_]FeatureType {
	1605	.Lpm,
	1606	.Movw,
1638	1607	.Spm,
1639		.Lpmx,
1640	1608	.Avr0,
	1609	.Sram,
1641	1610	.Jmpcall,
1642	1611	.Addsubiw,
1643		.Lpm,
1644		.Avr5,
1645		},
1646		CpuInfo(@This()).create(.Atmega329p, "atmega329p", &[_]FeatureType {
1647		.Ijmpcall,
1648		.Movw,
1649	1612	.Mul,
1650		.Sram,
	1613	.Lpmx,
	1614	.Ijmpcall,
1651	1615	.Break,
	1616	.Avr5,
	1617	}),
	1618	CpuInfo(@This(), FeatureType).create(.Atmega3290pa, "atmega3290pa", &[_]FeatureType {
	1619	.Lpm,
	1620	.Movw,
1652	1621	.Spm,
1653		.Lpmx,
1654	1622	.Avr0,
	1623	.Sram,
1655	1624	.Jmpcall,
1656	1625	.Addsubiw,
1657		.Lpm,
1658		.Avr5,
1659		},
1660		CpuInfo(@This()).create(.Atmega329pa, "atmega329pa", &[_]FeatureType {
1661		.Ijmpcall,
1662		.Movw,
1663	1626	.Mul,
1664		.Sram,
	1627	.Lpmx,
	1628	.Ijmpcall,
1665	1629	.Break,
	1630	.Avr5,
	1631	}),
	1632	CpuInfo(@This(), FeatureType).create(.Atmega329a, "atmega329a", &[_]FeatureType {
	1633	.Lpm,
	1634	.Movw,
1666	1635	.Spm,
1667		.Lpmx,
1668	1636	.Avr0,
	1637	.Sram,
1669	1638	.Jmpcall,
1670	1639	.Addsubiw,
1671		.Lpm,
1672		.Avr5,
1673		},
1674		CpuInfo(@This()).create(.Atmega32a, "atmega32a", &[_]FeatureType {
1675		.Ijmpcall,
1676		.Movw,
1677	1640	.Mul,
1678		.Sram,
	1641	.Lpmx,
	1642	.Ijmpcall,
1679	1643	.Break,
	1644	.Avr5,
	1645	}),
	1646	CpuInfo(@This(), FeatureType).create(.Atmega329p, "atmega329p", &[_]FeatureType {
	1647	.Lpm,
	1648	.Movw,
1680	1649	.Spm,
1681		.Lpmx,
1682	1650	.Avr0,
	1651	.Sram,
1683	1652	.Jmpcall,
1684	1653	.Addsubiw,
1685		.Lpm,
1686		.Avr5,
1687		},
1688		CpuInfo(@This()).create(.Atmega32c1, "atmega32c1", &[_]FeatureType {
1689		.Ijmpcall,
1690		.Movw,
1691	1654	.Mul,
1692		.Sram,
	1655	.Lpmx,
	1656	.Ijmpcall,
1693	1657	.Break,
	1658	.Avr5,
	1659	}),
	1660	CpuInfo(@This(), FeatureType).create(.Atmega329pa, "atmega329pa", &[_]FeatureType {
	1661	.Lpm,
	1662	.Movw,
1694	1663	.Spm,
1695		.Lpmx,
1696	1664	.Avr0,
	1665	.Sram,
1697	1666	.Jmpcall,
1698	1667	.Addsubiw,
1699		.Lpm,
1700		.Avr5,
1701		},
1702		CpuInfo(@This()).create(.Atmega32hvb, "atmega32hvb", &[_]FeatureType {
1703		.Ijmpcall,
1704		.Movw,
1705	1668	.Mul,
1706		.Sram,
	1669	.Lpmx,
	1670	.Ijmpcall,
1707	1671	.Break,
	1672	.Avr5,
	1673	}),
	1674	CpuInfo(@This(), FeatureType).create(.Atmega32a, "atmega32a", &[_]FeatureType {
	1675	.Lpm,
	1676	.Movw,
1708	1677	.Spm,
1709		.Lpmx,
1710	1678	.Avr0,
	1679	.Sram,
1711	1680	.Jmpcall,
1712	1681	.Addsubiw,
1713		.Lpm,
1714		.Avr5,
1715		},
1716		CpuInfo(@This()).create(.Atmega32hvbrevb, "atmega32hvbrevb", &[_]FeatureType {
1717		.Ijmpcall,
1718		.Movw,
1719	1682	.Mul,
1720		.Sram,
	1683	.Lpmx,
	1684	.Ijmpcall,
1721	1685	.Break,
	1686	.Avr5,
	1687	}),
	1688	CpuInfo(@This(), FeatureType).create(.Atmega32c1, "atmega32c1", &[_]FeatureType {
	1689	.Lpm,
	1690	.Movw,
1722	1691	.Spm,
1723		.Lpmx,
1724	1692	.Avr0,
	1693	.Sram,
1725	1694	.Jmpcall,
1726	1695	.Addsubiw,
1727		.Lpm,
1728		.Avr5,
1729		},
1730		CpuInfo(@This()).create(.Atmega32m1, "atmega32m1", &[_]FeatureType {
1731		.Ijmpcall,
1732		.Movw,
1733	1696	.Mul,
1734		.Sram,
	1697	.Lpmx,
	1698	.Ijmpcall,
1735	1699	.Break,
	1700	.Avr5,
	1701	}),
	1702	CpuInfo(@This(), FeatureType).create(.Atmega32hvb, "atmega32hvb", &[_]FeatureType {
	1703	.Lpm,
	1704	.Movw,
1736	1705	.Spm,
1737		.Lpmx,
1738	1706	.Avr0,
	1707	.Sram,
1739	1708	.Jmpcall,
1740	1709	.Addsubiw,
1741		.Lpm,
1742		.Avr5,
1743		},
1744		CpuInfo(@This()).create(.Atmega32u2, "atmega32u2", &[_]FeatureType {
	1710	.Mul,
	1711	.Lpmx,
1745	1712	.Ijmpcall,
1746		.Movw,
1747		.Sram,
1748	1713	.Break,
	1714	.Avr5,
	1715	}),
	1716	CpuInfo(@This(), FeatureType).create(.Atmega32hvbrevb, "atmega32hvbrevb", &[_]FeatureType {
	1717	.Lpm,
	1718	.Movw,
1749	1719	.Spm,
1750		.Lpmx,
1751	1720	.Avr0,
	1721	.Sram,
1752	1722	.Jmpcall,
1753	1723	.Addsubiw,
1754		.Lpm,
1755		.Avr35,
1756		},
1757		CpuInfo(@This()).create(.Atmega32u4, "atmega32u4", &[_]FeatureType {
1758		.Ijmpcall,
1759		.Movw,
1760	1724	.Mul,
1761		.Sram,
	1725	.Lpmx,
	1726	.Ijmpcall,
1762	1727	.Break,
	1728	.Avr5,
	1729	}),
	1730	CpuInfo(@This(), FeatureType).create(.Atmega32m1, "atmega32m1", &[_]FeatureType {
	1731	.Lpm,
	1732	.Movw,
1763	1733	.Spm,
1764		.Lpmx,
1765	1734	.Avr0,
	1735	.Sram,
1766	1736	.Jmpcall,
1767	1737	.Addsubiw,
1768		.Lpm,
1769		.Avr5,
1770		},
1771		CpuInfo(@This()).create(.Atmega32u6, "atmega32u6", &[_]FeatureType {
1772		.Ijmpcall,
1773		.Movw,
1774	1738	.Mul,
1775		.Sram,
	1739	.Lpmx,
	1740	.Ijmpcall,
1776	1741	.Break,
	1742	.Avr5,
	1743	}),
	1744	CpuInfo(@This(), FeatureType).create(.Atmega32u2, "atmega32u2", &[_]FeatureType {
	1745	.Lpm,
	1746	.Movw,
1777	1747	.Spm,
1778		.Lpmx,
1779	1748	.Avr0,
	1749	.Sram,
1780	1750	.Jmpcall,
1781	1751	.Addsubiw,
1782		.Lpm,
1783		.Avr5,
1784		},
1785		CpuInfo(@This()).create(.Atmega406, "atmega406", &[_]FeatureType {
	1752	.Lpmx,
1786	1753	.Ijmpcall,
1787		.Movw,
1788		.Mul,
1789		.Sram,
1790	1754	.Break,
	1755	.Avr35,
	1756	}),
	1757	CpuInfo(@This(), FeatureType).create(.Atmega32u4, "atmega32u4", &[_]FeatureType {
	1758	.Lpm,
	1759	.Movw,
1791	1760	.Spm,
1792		.Lpmx,
1793	1761	.Avr0,
	1762	.Sram,
1794	1763	.Jmpcall,
1795	1764	.Addsubiw,
1796		.Lpm,
1797		.Avr5,
1798		},
1799		CpuInfo(@This()).create(.Atmega48, "atmega48", &[_]FeatureType {
1800		.Ijmpcall,
1801		.Movw,
1802	1765	.Mul,
1803		.Sram,
	1766	.Lpmx,
	1767	.Ijmpcall,
1804	1768	.Break,
	1769	.Avr5,
	1770	}),
	1771	CpuInfo(@This(), FeatureType).create(.Atmega32u6, "atmega32u6", &[_]FeatureType {
	1772	.Lpm,
	1773	.Movw,
1805	1774	.Spm,
1806		.Lpmx,
1807	1775	.Avr0,
	1776	.Sram,
	1777	.Jmpcall,
1808	1778	.Addsubiw,
1809		.Lpm,
1810		.Avr4,
1811		},
1812		CpuInfo(@This()).create(.Atmega48a, "atmega48a", &[_]FeatureType {
1813		.Ijmpcall,
1814		.Movw,
1815	1779	.Mul,
1816		.Sram,
	1780	.Lpmx,
	1781	.Ijmpcall,
1817	1782	.Break,
	1783	.Avr5,
	1784	}),
	1785	CpuInfo(@This(), FeatureType).create(.Atmega406, "atmega406", &[_]FeatureType {
	1786	.Lpm,
	1787	.Movw,
1818	1788	.Spm,
1819		.Lpmx,
1820	1789	.Avr0,
	1790	.Sram,
	1791	.Jmpcall,
1821	1792	.Addsubiw,
1822		.Lpm,
1823		.Avr4,
1824		},
1825		CpuInfo(@This()).create(.Atmega48p, "atmega48p", &[_]FeatureType {
1826		.Ijmpcall,
1827		.Movw,
1828	1793	.Mul,
1829		.Sram,
	1794	.Lpmx,
	1795	.Ijmpcall,
1830	1796	.Break,
	1797	.Avr5,
	1798	}),
	1799	CpuInfo(@This(), FeatureType).create(.Atmega48, "atmega48", &[_]FeatureType {
	1800	.Lpm,
	1801	.Movw,
1831	1802	.Spm,
1832		.Lpmx,
1833	1803	.Avr0,
	1804	.Sram,
1834	1805	.Addsubiw,
1835		.Lpm,
1836		.Avr4,
1837		},
1838		CpuInfo(@This()).create(.Atmega48pa, "atmega48pa", &[_]FeatureType {
1839		.Ijmpcall,
1840		.Movw,
1841	1806	.Mul,
1842		.Sram,
	1807	.Lpmx,
	1808	.Ijmpcall,
1843	1809	.Break,
	1810	.Avr4,
	1811	}),
	1812	CpuInfo(@This(), FeatureType).create(.Atmega48a, "atmega48a", &[_]FeatureType {
	1813	.Lpm,
	1814	.Movw,
1844	1815	.Spm,
1845		.Lpmx,
1846	1816	.Avr0,
	1817	.Sram,
1847	1818	.Addsubiw,
1848		.Lpm,
1849		.Avr4,
1850		},
1851		CpuInfo(@This()).create(.Atmega64, "atmega64", &[_]FeatureType {
1852		.Ijmpcall,
1853		.Movw,
1854	1819	.Mul,
1855		.Sram,
	1820	.Lpmx,
	1821	.Ijmpcall,
1856	1822	.Break,
	1823	.Avr4,
	1824	}),
	1825	CpuInfo(@This(), FeatureType).create(.Atmega48p, "atmega48p", &[_]FeatureType {
	1826	.Lpm,
	1827	.Movw,
1857	1828	.Spm,
1858		.Lpmx,
1859	1829	.Avr0,
1860		.Jmpcall,
	1830	.Sram,
1861	1831	.Addsubiw,
1862		.Lpm,
1863		.Avr5,
1864		},
1865		CpuInfo(@This()).create(.Atmega640, "atmega640", &[_]FeatureType {
1866		.Ijmpcall,
1867		.Movw,
1868	1832	.Mul,
1869		.Sram,
	1833	.Lpmx,
	1834	.Ijmpcall,
1870	1835	.Break,
	1836	.Avr4,
	1837	}),
	1838	CpuInfo(@This(), FeatureType).create(.Atmega48pa, "atmega48pa", &[_]FeatureType {
	1839	.Lpm,
	1840	.Movw,
1871	1841	.Spm,
1872		.Lpmx,
1873	1842	.Avr0,
1874		.Jmpcall,
	1843	.Sram,
1875	1844	.Addsubiw,
1876		.Lpm,
1877		.Avr5,
1878		},
1879		CpuInfo(@This()).create(.Atmega644, "atmega644", &[_]FeatureType {
1880		.Ijmpcall,
1881		.Movw,
1882	1845	.Mul,
1883		.Sram,
	1846	.Lpmx,
	1847	.Ijmpcall,
1884	1848	.Break,
	1849	.Avr4,
	1850	}),
	1851	CpuInfo(@This(), FeatureType).create(.Atmega64, "atmega64", &[_]FeatureType {
	1852	.Lpm,
	1853	.Movw,
1885	1854	.Spm,
1886		.Lpmx,
1887	1855	.Avr0,
	1856	.Sram,
1888	1857	.Jmpcall,
1889	1858	.Addsubiw,
1890		.Lpm,
1891		.Avr5,
1892		},
1893		CpuInfo(@This()).create(.Atmega644a, "atmega644a", &[_]FeatureType {
1894		.Ijmpcall,
1895		.Movw,
1896	1859	.Mul,
1897		.Sram,
	1860	.Lpmx,
	1861	.Ijmpcall,
1898	1862	.Break,
	1863	.Avr5,
	1864	}),
	1865	CpuInfo(@This(), FeatureType).create(.Atmega640, "atmega640", &[_]FeatureType {
	1866	.Lpm,
	1867	.Movw,
1899	1868	.Spm,
1900		.Lpmx,
1901	1869	.Avr0,
	1870	.Sram,
1902	1871	.Jmpcall,
1903	1872	.Addsubiw,
1904		.Lpm,
1905		.Avr5,
1906		},
1907		CpuInfo(@This()).create(.Atmega644p, "atmega644p", &[_]FeatureType {
1908		.Ijmpcall,
1909		.Movw,
1910	1873	.Mul,
1911		.Sram,
	1874	.Lpmx,
	1875	.Ijmpcall,
1912	1876	.Break,
	1877	.Avr5,
	1878	}),
	1879	CpuInfo(@This(), FeatureType).create(.Atmega644, "atmega644", &[_]FeatureType {
	1880	.Lpm,
	1881	.Movw,
1913	1882	.Spm,
1914		.Lpmx,
1915	1883	.Avr0,
	1884	.Sram,
1916	1885	.Jmpcall,
1917	1886	.Addsubiw,
1918		.Lpm,
1919		.Avr5,
1920		},
1921		CpuInfo(@This()).create(.Atmega644pa, "atmega644pa", &[_]FeatureType {
1922		.Ijmpcall,
1923		.Movw,
1924	1887	.Mul,
1925		.Sram,
	1888	.Lpmx,
	1889	.Ijmpcall,
1926	1890	.Break,
	1891	.Avr5,
	1892	}),
	1893	CpuInfo(@This(), FeatureType).create(.Atmega644a, "atmega644a", &[_]FeatureType {
	1894	.Lpm,
	1895	.Movw,
1927	1896	.Spm,
1928		.Lpmx,
1929	1897	.Avr0,
	1898	.Sram,
1930	1899	.Jmpcall,
1931	1900	.Addsubiw,
1932		.Lpm,
1933		.Avr5,
1934		},
1935		CpuInfo(@This()).create(.Atmega644rfr2, "atmega644rfr2", &[_]FeatureType {
1936		.Ijmpcall,
1937		.Movw,
1938	1901	.Mul,
1939		.Sram,
	1902	.Lpmx,
	1903	.Ijmpcall,
1940	1904	.Break,
	1905	.Avr5,
	1906	}),
	1907	CpuInfo(@This(), FeatureType).create(.Atmega644p, "atmega644p", &[_]FeatureType {
	1908	.Lpm,
	1909	.Movw,
1941	1910	.Spm,
1942		.Lpmx,
1943	1911	.Avr0,
	1912	.Sram,
1944	1913	.Jmpcall,
1945	1914	.Addsubiw,
1946		.Lpm,
1947		.Avr5,
1948		},
1949		CpuInfo(@This()).create(.Atmega645, "atmega645", &[_]FeatureType {
1950		.Ijmpcall,
1951		.Movw,
1952	1915	.Mul,
1953		.Sram,
	1916	.Lpmx,
	1917	.Ijmpcall,
1954	1918	.Break,
	1919	.Avr5,
	1920	}),
	1921	CpuInfo(@This(), FeatureType).create(.Atmega644pa, "atmega644pa", &[_]FeatureType {
	1922	.Lpm,
	1923	.Movw,
1955	1924	.Spm,
1956		.Lpmx,
1957	1925	.Avr0,
	1926	.Sram,
1958	1927	.Jmpcall,
1959	1928	.Addsubiw,
1960		.Lpm,
1961		.Avr5,
1962		},
1963		CpuInfo(@This()).create(.Atmega6450, "atmega6450", &[_]FeatureType {
1964		.Ijmpcall,
1965		.Movw,
1966	1929	.Mul,
1967		.Sram,
	1930	.Lpmx,
	1931	.Ijmpcall,
1968	1932	.Break,
	1933	.Avr5,
	1934	}),
	1935	CpuInfo(@This(), FeatureType).create(.Atmega644rfr2, "atmega644rfr2", &[_]FeatureType {
	1936	.Lpm,
	1937	.Movw,
1969	1938	.Spm,
1970		.Lpmx,
1971	1939	.Avr0,
	1940	.Sram,
1972	1941	.Jmpcall,
1973	1942	.Addsubiw,
1974		.Lpm,
1975		.Avr5,
1976		},
1977		CpuInfo(@This()).create(.Atmega6450a, "atmega6450a", &[_]FeatureType {
1978		.Ijmpcall,
1979		.Movw,
1980	1943	.Mul,
1981		.Sram,
	1944	.Lpmx,
	1945	.Ijmpcall,
1982	1946	.Break,
	1947	.Avr5,
	1948	}),
	1949	CpuInfo(@This(), FeatureType).create(.Atmega645, "atmega645", &[_]FeatureType {
	1950	.Lpm,
	1951	.Movw,
1983	1952	.Spm,
1984		.Lpmx,
1985	1953	.Avr0,
	1954	.Sram,
1986	1955	.Jmpcall,
1987	1956	.Addsubiw,
1988		.Lpm,
1989		.Avr5,
1990		},
1991		CpuInfo(@This()).create(.Atmega6450p, "atmega6450p", &[_]FeatureType {
1992		.Ijmpcall,
1993		.Movw,
1994	1957	.Mul,
1995		.Sram,
	1958	.Lpmx,
	1959	.Ijmpcall,
1996	1960	.Break,
	1961	.Avr5,
	1962	}),
	1963	CpuInfo(@This(), FeatureType).create(.Atmega6450, "atmega6450", &[_]FeatureType {
	1964	.Lpm,
	1965	.Movw,
1997	1966	.Spm,
1998		.Lpmx,
1999	1967	.Avr0,
	1968	.Sram,
2000	1969	.Jmpcall,
2001	1970	.Addsubiw,
2002		.Lpm,
2003		.Avr5,
2004		},
2005		CpuInfo(@This()).create(.Atmega645a, "atmega645a", &[_]FeatureType {
2006		.Ijmpcall,
2007		.Movw,
2008	1971	.Mul,
2009		.Sram,
	1972	.Lpmx,
	1973	.Ijmpcall,
2010	1974	.Break,
	1975	.Avr5,
	1976	}),
	1977	CpuInfo(@This(), FeatureType).create(.Atmega6450a, "atmega6450a", &[_]FeatureType {
	1978	.Lpm,
	1979	.Movw,
2011	1980	.Spm,
2012		.Lpmx,
2013	1981	.Avr0,
	1982	.Sram,
2014	1983	.Jmpcall,
2015	1984	.Addsubiw,
2016		.Lpm,
2017		.Avr5,
2018		},
2019		CpuInfo(@This()).create(.Atmega645p, "atmega645p", &[_]FeatureType {
2020		.Ijmpcall,
2021		.Movw,
2022	1985	.Mul,
2023		.Sram,
	1986	.Lpmx,
	1987	.Ijmpcall,
2024	1988	.Break,
	1989	.Avr5,
	1990	}),
	1991	CpuInfo(@This(), FeatureType).create(.Atmega6450p, "atmega6450p", &[_]FeatureType {
	1992	.Lpm,
	1993	.Movw,
2025	1994	.Spm,
2026		.Lpmx,
2027	1995	.Avr0,
	1996	.Sram,
2028	1997	.Jmpcall,
2029	1998	.Addsubiw,
2030		.Lpm,
2031		.Avr5,
2032		},
2033		CpuInfo(@This()).create(.Atmega649, "atmega649", &[_]FeatureType {
2034		.Ijmpcall,
2035		.Movw,
2036	1999	.Mul,
2037		.Sram,
	2000	.Lpmx,
	2001	.Ijmpcall,
2038	2002	.Break,
	2003	.Avr5,
	2004	}),
	2005	CpuInfo(@This(), FeatureType).create(.Atmega645a, "atmega645a", &[_]FeatureType {
	2006	.Lpm,
	2007	.Movw,
2039	2008	.Spm,
2040		.Lpmx,
2041	2009	.Avr0,
	2010	.Sram,
2042	2011	.Jmpcall,
2043	2012	.Addsubiw,
2044		.Lpm,
2045		.Avr5,
2046		},
2047		CpuInfo(@This()).create(.Atmega6490, "atmega6490", &[_]FeatureType {
2048		.Ijmpcall,
2049		.Movw,
2050	2013	.Mul,
2051		.Sram,
	2014	.Lpmx,
	2015	.Ijmpcall,
2052	2016	.Break,
	2017	.Avr5,
	2018	}),
	2019	CpuInfo(@This(), FeatureType).create(.Atmega645p, "atmega645p", &[_]FeatureType {
	2020	.Lpm,
	2021	.Movw,
2053	2022	.Spm,
2054		.Lpmx,
2055	2023	.Avr0,
	2024	.Sram,
2056	2025	.Jmpcall,
2057	2026	.Addsubiw,
2058		.Lpm,
2059		.Avr5,
2060		},
2061		CpuInfo(@This()).create(.Atmega6490a, "atmega6490a", &[_]FeatureType {
2062		.Ijmpcall,
2063		.Movw,
2064	2027	.Mul,
2065		.Sram,
	2028	.Lpmx,
	2029	.Ijmpcall,
2066	2030	.Break,
	2031	.Avr5,
	2032	}),
	2033	CpuInfo(@This(), FeatureType).create(.Atmega649, "atmega649", &[_]FeatureType {
	2034	.Lpm,
	2035	.Movw,
2067	2036	.Spm,
2068		.Lpmx,
2069	2037	.Avr0,
	2038	.Sram,
2070	2039	.Jmpcall,
2071	2040	.Addsubiw,
2072		.Lpm,
2073		.Avr5,
2074		},
2075		CpuInfo(@This()).create(.Atmega6490p, "atmega6490p", &[_]FeatureType {
2076		.Ijmpcall,
2077		.Movw,
2078	2041	.Mul,
2079		.Sram,
	2042	.Lpmx,
	2043	.Ijmpcall,
2080	2044	.Break,
	2045	.Avr5,
	2046	}),
	2047	CpuInfo(@This(), FeatureType).create(.Atmega6490, "atmega6490", &[_]FeatureType {
	2048	.Lpm,
	2049	.Movw,
2081	2050	.Spm,
2082		.Lpmx,
2083	2051	.Avr0,
	2052	.Sram,
2084	2053	.Jmpcall,
2085	2054	.Addsubiw,
2086		.Lpm,
2087		.Avr5,
2088		},
2089		CpuInfo(@This()).create(.Atmega649a, "atmega649a", &[_]FeatureType {
2090		.Ijmpcall,
2091		.Movw,
2092	2055	.Mul,
2093		.Sram,
	2056	.Lpmx,
	2057	.Ijmpcall,
2094	2058	.Break,
	2059	.Avr5,
	2060	}),
	2061	CpuInfo(@This(), FeatureType).create(.Atmega6490a, "atmega6490a", &[_]FeatureType {
	2062	.Lpm,
	2063	.Movw,
2095	2064	.Spm,
2096		.Lpmx,
2097	2065	.Avr0,
	2066	.Sram,
2098	2067	.Jmpcall,
2099	2068	.Addsubiw,
2100		.Lpm,
2101		.Avr5,
2102		},
2103		CpuInfo(@This()).create(.Atmega649p, "atmega649p", &[_]FeatureType {
2104		.Ijmpcall,
2105		.Movw,
2106	2069	.Mul,
2107		.Sram,
	2070	.Lpmx,
	2071	.Ijmpcall,
2108	2072	.Break,
	2073	.Avr5,
	2074	}),
	2075	CpuInfo(@This(), FeatureType).create(.Atmega6490p, "atmega6490p", &[_]FeatureType {
	2076	.Lpm,
	2077	.Movw,
2109	2078	.Spm,
2110		.Lpmx,
2111	2079	.Avr0,
	2080	.Sram,
2112	2081	.Jmpcall,
2113	2082	.Addsubiw,
2114		.Lpm,
2115		.Avr5,
2116		},
2117		CpuInfo(@This()).create(.Atmega64a, "atmega64a", &[_]FeatureType {
2118		.Ijmpcall,
2119		.Movw,
2120	2083	.Mul,
2121		.Sram,
	2084	.Lpmx,
	2085	.Ijmpcall,
2122	2086	.Break,
	2087	.Avr5,
	2088	}),
	2089	CpuInfo(@This(), FeatureType).create(.Atmega649a, "atmega649a", &[_]FeatureType {
	2090	.Lpm,
	2091	.Movw,
2123	2092	.Spm,
2124		.Lpmx,
2125	2093	.Avr0,
	2094	.Sram,
2126	2095	.Jmpcall,
2127	2096	.Addsubiw,
2128		.Lpm,
2129		.Avr5,
2130		},
2131		CpuInfo(@This()).create(.Atmega64c1, "atmega64c1", &[_]FeatureType {
2132		.Ijmpcall,
2133		.Movw,
2134	2097	.Mul,
2135		.Sram,
	2098	.Lpmx,
	2099	.Ijmpcall,
2136	2100	.Break,
	2101	.Avr5,
	2102	}),
	2103	CpuInfo(@This(), FeatureType).create(.Atmega649p, "atmega649p", &[_]FeatureType {
	2104	.Lpm,
	2105	.Movw,
2137	2106	.Spm,
2138		.Lpmx,
2139	2107	.Avr0,
	2108	.Sram,
2140	2109	.Jmpcall,
2141	2110	.Addsubiw,
2142		.Lpm,
2143		.Avr5,
2144		},
2145		CpuInfo(@This()).create(.Atmega64hve, "atmega64hve", &[_]FeatureType {
2146		.Ijmpcall,
2147		.Movw,
2148	2111	.Mul,
2149		.Sram,
	2112	.Lpmx,
	2113	.Ijmpcall,
2150	2114	.Break,
	2115	.Avr5,
	2116	}),
	2117	CpuInfo(@This(), FeatureType).create(.Atmega64a, "atmega64a", &[_]FeatureType {
	2118	.Lpm,
	2119	.Movw,
2151	2120	.Spm,
2152		.Lpmx,
2153	2121	.Avr0,
	2122	.Sram,
2154	2123	.Jmpcall,
2155	2124	.Addsubiw,
2156		.Lpm,
2157		.Avr5,
2158		},
2159		CpuInfo(@This()).create(.Atmega64m1, "atmega64m1", &[_]FeatureType {
2160		.Ijmpcall,
2161		.Movw,
2162	2125	.Mul,
2163		.Sram,
	2126	.Lpmx,
	2127	.Ijmpcall,
2164	2128	.Break,
	2129	.Avr5,
	2130	}),
	2131	CpuInfo(@This(), FeatureType).create(.Atmega64c1, "atmega64c1", &[_]FeatureType {
	2132	.Lpm,
	2133	.Movw,
2165	2134	.Spm,
2166		.Lpmx,
2167	2135	.Avr0,
	2136	.Sram,
2168	2137	.Jmpcall,
2169	2138	.Addsubiw,
2170		.Lpm,
2171		.Avr5,
2172		},
2173		CpuInfo(@This()).create(.Atmega64rfr2, "atmega64rfr2", &[_]FeatureType {
	2139	.Mul,
	2140	.Lpmx,
2174	2141	.Ijmpcall,
	2142	.Break,
	2143	.Avr5,
	2144	}),
	2145	CpuInfo(@This(), FeatureType).create(.Atmega64hve, "atmega64hve", &[_]FeatureType {
	2146	.Lpm,
2175	2147	.Movw,
2176		.Mul,
	2148	.Spm,
	2149	.Avr0,
2177	2150	.Sram,
	2151	.Jmpcall,
	2152	.Addsubiw,
	2153	.Mul,
	2154	.Lpmx,
	2155	.Ijmpcall,
2178	2156	.Break,
	2157	.Avr5,
	2158	}),
	2159	CpuInfo(@This(), FeatureType).create(.Atmega64m1, "atmega64m1", &[_]FeatureType {
	2160	.Lpm,
	2161	.Movw,
2179	2162	.Spm,
2180		.Lpmx,
2181	2163	.Avr0,
	2164	.Sram,
2182	2165	.Jmpcall,
2183	2166	.Addsubiw,
2184		.Lpm,
2185		.Avr5,
2186		},
2187		CpuInfo(@This()).create(.Atmega8, "atmega8", &[_]FeatureType {
	2167	.Mul,
	2168	.Lpmx,
2188	2169	.Ijmpcall,
	2170	.Break,
	2171	.Avr5,
	2172	}),
	2173	CpuInfo(@This(), FeatureType).create(.Atmega64rfr2, "atmega64rfr2", &[_]FeatureType {
	2174	.Lpm,
2189	2175	.Movw,
2190		.Mul,
	2176	.Spm,
	2177	.Avr0,
2191	2178	.Sram,
	2179	.Jmpcall,
	2180	.Addsubiw,
	2181	.Mul,
	2182	.Lpmx,
	2183	.Ijmpcall,
2192	2184	.Break,
	2185	.Avr5,
	2186	}),
	2187	CpuInfo(@This(), FeatureType).create(.Atmega8, "atmega8", &[_]FeatureType {
	2188	.Lpm,
	2189	.Movw,
2193	2190	.Spm,
2194		.Lpmx,
2195	2191	.Avr0,
	2192	.Sram,
2196	2193	.Addsubiw,
2197		.Lpm,
2198		.Avr4,
2199		},
2200		CpuInfo(@This()).create(.Atmega8515, "atmega8515", &[_]FeatureType {
	2194	.Mul,
	2195	.Lpmx,
2201	2196	.Ijmpcall,
2202		.Sram,
	2197	.Break,
	2198	.Avr4,
	2199	}),
	2200	CpuInfo(@This(), FeatureType).create(.Atmega8515, "atmega8515", &[_]FeatureType {
	2201	.Lpm,
2203	2202	.Avr0,
	2203	.Sram,
2204	2204	.Addsubiw,
2205		.Lpm,
	2205	.Ijmpcall,
2206	2206	.Avr2,
2207	2207	.Lpmx,
2208	2208	.Movw,
2209	2209	.Mul,
2210	2210	.Spm,
2211		},
2212		CpuInfo(@This()).create(.Atmega8535, "atmega8535", &[_]FeatureType {
2213		.Ijmpcall,
2214		.Sram,
	2211	}),
	2212	CpuInfo(@This(), FeatureType).create(.Atmega8535, "atmega8535", &[_]FeatureType {
	2213	.Lpm,
2215	2214	.Avr0,
	2215	.Sram,
2216	2216	.Addsubiw,
2217		.Lpm,
	2217	.Ijmpcall,
2218	2218	.Avr2,
2219	2219	.Lpmx,
2220	2220	.Movw,
2221	2221	.Mul,
2222	2222	.Spm,
2223		},
2224		CpuInfo(@This()).create(.Atmega88, "atmega88", &[_]FeatureType {
2225		.Ijmpcall,
	2223	}),
	2224	CpuInfo(@This(), FeatureType).create(.Atmega88, "atmega88", &[_]FeatureType {
	2225	.Lpm,
2226	2226	.Movw,
2227		.Mul,
2228		.Sram,
2229		.Break,
2230	2227	.Spm,
2231		.Lpmx,
2232	2228	.Avr0,
	2229	.Sram,
2233	2230	.Addsubiw,
2234		.Lpm,
2235		.Avr4,
2236		},
2237		CpuInfo(@This()).create(.Atmega88a, "atmega88a", &[_]FeatureType {
2238		.Ijmpcall,
2239		.Movw,
2240	2231	.Mul,
2241		.Sram,
	2232	.Lpmx,
	2233	.Ijmpcall,
2242	2234	.Break,
	2235	.Avr4,
	2236	}),
	2237	CpuInfo(@This(), FeatureType).create(.Atmega88a, "atmega88a", &[_]FeatureType {
	2238	.Lpm,
	2239	.Movw,
2243	2240	.Spm,
2244		.Lpmx,
2245	2241	.Avr0,
	2242	.Sram,
2246	2243	.Addsubiw,
2247		.Lpm,
2248		.Avr4,
2249		},
2250		CpuInfo(@This()).create(.Atmega88p, "atmega88p", &[_]FeatureType {
2251		.Ijmpcall,
2252		.Movw,
2253	2244	.Mul,
2254		.Sram,
	2245	.Lpmx,
	2246	.Ijmpcall,
2255	2247	.Break,
	2248	.Avr4,
	2249	}),
	2250	CpuInfo(@This(), FeatureType).create(.Atmega88p, "atmega88p", &[_]FeatureType {
	2251	.Lpm,
	2252	.Movw,
2256	2253	.Spm,
2257		.Lpmx,
2258	2254	.Avr0,
	2255	.Sram,
2259	2256	.Addsubiw,
2260		.Lpm,
2261		.Avr4,
2262		},
2263		CpuInfo(@This()).create(.Atmega88pa, "atmega88pa", &[_]FeatureType {
2264		.Ijmpcall,
2265		.Movw,
2266	2257	.Mul,
2267		.Sram,
	2258	.Lpmx,
	2259	.Ijmpcall,
2268	2260	.Break,
	2261	.Avr4,
	2262	}),
	2263	CpuInfo(@This(), FeatureType).create(.Atmega88pa, "atmega88pa", &[_]FeatureType {
	2264	.Lpm,
	2265	.Movw,
2269	2266	.Spm,
2270		.Lpmx,
2271	2267	.Avr0,
	2268	.Sram,
2272	2269	.Addsubiw,
2273		.Lpm,
2274		.Avr4,
2275		},
2276		CpuInfo(@This()).create(.Atmega8a, "atmega8a", &[_]FeatureType {
2277		.Ijmpcall,
2278		.Movw,
2279	2270	.Mul,
2280		.Sram,
	2271	.Lpmx,
	2272	.Ijmpcall,
2281	2273	.Break,
	2274	.Avr4,
	2275	}),
	2276	CpuInfo(@This(), FeatureType).create(.Atmega8a, "atmega8a", &[_]FeatureType {
	2277	.Lpm,
	2278	.Movw,
2282	2279	.Spm,
2283		.Lpmx,
2284	2280	.Avr0,
	2281	.Sram,
2285	2282	.Addsubiw,
2286		.Lpm,
2287		.Avr4,
2288		},
2289		CpuInfo(@This()).create(.Atmega8hva, "atmega8hva", &[_]FeatureType {
2290		.Ijmpcall,
2291		.Movw,
2292	2283	.Mul,
2293		.Sram,
	2284	.Lpmx,
	2285	.Ijmpcall,
2294	2286	.Break,
	2287	.Avr4,
	2288	}),
	2289	CpuInfo(@This(), FeatureType).create(.Atmega8hva, "atmega8hva", &[_]FeatureType {
	2290	.Lpm,
	2291	.Movw,
2295	2292	.Spm,
2296		.Lpmx,
2297	2293	.Avr0,
	2294	.Sram,
2298	2295	.Addsubiw,
2299		.Lpm,
2300		.Avr4,
2301		},
2302		CpuInfo(@This()).create(.Atmega8u2, "atmega8u2", &[_]FeatureType {
	2296	.Mul,
	2297	.Lpmx,
2303	2298	.Ijmpcall,
2304		.Movw,
2305		.Sram,
2306	2299	.Break,
	2300	.Avr4,
	2301	}),
	2302	CpuInfo(@This(), FeatureType).create(.Atmega8u2, "atmega8u2", &[_]FeatureType {
	2303	.Lpm,
	2304	.Movw,
2307	2305	.Spm,
2308		.Lpmx,
2309	2306	.Avr0,
	2307	.Sram,
2310	2308	.Jmpcall,
2311	2309	.Addsubiw,
2312		.Lpm,
2313		.Avr35,
2314		},
2315		CpuInfo(@This()).create(.Attiny10, "attiny10", &[_]FeatureType {
	2310	.Lpmx,
	2311	.Ijmpcall,
2316	2312	.Break,
2317		.Tinyencoding,
	2313	.Avr35,
	2314	}),
	2315	CpuInfo(@This(), FeatureType).create(.Attiny10, "attiny10", &[_]FeatureType {
2318	2316	.Avr0,
2319	2317	.Sram,
2320		.Avrtiny,
2321		},
2322		CpuInfo(@This()).create(.Attiny102, "attiny102", &[_]FeatureType {
2323	2318	.Break,
2324	2319	.Tinyencoding,
	2320	.Avrtiny,
	2321	}),
	2322	CpuInfo(@This(), FeatureType).create(.Attiny102, "attiny102", &[_]FeatureType {
2325	2323	.Avr0,
2326	2324	.Sram,
2327		.Avrtiny,
2328		},
2329		CpuInfo(@This()).create(.Attiny104, "attiny104", &[_]FeatureType {
2330	2325	.Break,
2331	2326	.Tinyencoding,
	2327	.Avrtiny,
	2328	}),
	2329	CpuInfo(@This(), FeatureType).create(.Attiny104, "attiny104", &[_]FeatureType {
2332	2330	.Avr0,
2333	2331	.Sram,
	2332	.Break,
	2333	.Tinyencoding,
2334	2334	.Avrtiny,
2335		},
2336		CpuInfo(@This()).create(.Attiny11, "attiny11", &[_]FeatureType {
2337		.Lpm,
	2335	}),
	2336	CpuInfo(@This(), FeatureType).create(.Attiny11, "attiny11", &[_]FeatureType {
2338	2337	.Avr0,
2339		.Avr1,
2340		},
2341		CpuInfo(@This()).create(.Attiny12, "attiny12", &[_]FeatureType {
2342	2338	.Lpm,
	2339	.Avr1,
	2340	}),
	2341	CpuInfo(@This(), FeatureType).create(.Attiny12, "attiny12", &[_]FeatureType {
2343	2342	.Avr0,
	2343	.Lpm,
2344	2344	.Avr1,
2345		},
2346		CpuInfo(@This()).create(.Attiny13, "attiny13", &[_]FeatureType {
2347		.Ijmpcall,
	2345	}),
	2346	CpuInfo(@This(), FeatureType).create(.Attiny13, "attiny13", &[_]FeatureType {
	2347	.Lpm,
2348	2348	.Movw,
2349		.Sram,
2350		.Break,
2351	2349	.Spm,
2352		.Lpmx,
2353	2350	.Avr0,
	2351	.Sram,
2354	2352	.Addsubiw,
2355		.Lpm,
2356		.Avr25,
2357		},
2358		CpuInfo(@This()).create(.Attiny13a, "attiny13a", &[_]FeatureType {
	2353	.Lpmx,
2359	2354	.Ijmpcall,
2360		.Movw,
2361		.Sram,
2362	2355	.Break,
	2356	.Avr25,
	2357	}),
	2358	CpuInfo(@This(), FeatureType).create(.Attiny13a, "attiny13a", &[_]FeatureType {
	2359	.Lpm,
	2360	.Movw,
2363	2361	.Spm,
2364		.Lpmx,
2365	2362	.Avr0,
	2363	.Sram,
2366	2364	.Addsubiw,
2367		.Lpm,
	2365	.Lpmx,
	2366	.Ijmpcall,
	2367	.Break,
2368	2368	.Avr25,
2369		},
2370		CpuInfo(@This()).create(.Attiny15, "attiny15", &[_]FeatureType {
2371		.Lpm,
	2369	}),
	2370	CpuInfo(@This(), FeatureType).create(.Attiny15, "attiny15", &[_]FeatureType {
2372	2371	.Avr0,
	2372	.Lpm,
2373	2373	.Avr1,
2374		},
2375		CpuInfo(@This()).create(.Attiny1634, "attiny1634", &[_]FeatureType {
2376		.Ijmpcall,
	2374	}),
	2375	CpuInfo(@This(), FeatureType).create(.Attiny1634, "attiny1634", &[_]FeatureType {
	2376	.Lpm,
2377	2377	.Movw,
2378		.Sram,
2379		.Break,
2380	2378	.Spm,
2381		.Lpmx,
2382	2379	.Avr0,
	2380	.Sram,
2383	2381	.Jmpcall,
2384	2382	.Addsubiw,
2385		.Lpm,
2386		.Avr35,
2387		},
2388		CpuInfo(@This()).create(.Attiny167, "attiny167", &[_]FeatureType {
	2383	.Lpmx,
2389	2384	.Ijmpcall,
2390		.Movw,
2391		.Sram,
2392	2385	.Break,
	2386	.Avr35,
	2387	}),
	2388	CpuInfo(@This(), FeatureType).create(.Attiny167, "attiny167", &[_]FeatureType {
	2389	.Lpm,
	2390	.Movw,
2393	2391	.Spm,
2394		.Lpmx,
2395	2392	.Avr0,
	2393	.Sram,
2396	2394	.Jmpcall,
2397	2395	.Addsubiw,
2398		.Lpm,
2399		.Avr35,
2400		},
2401		CpuInfo(@This()).create(.Attiny20, "attiny20", &[_]FeatureType {
	2396	.Lpmx,
	2397	.Ijmpcall,
2402	2398	.Break,
2403		.Tinyencoding,
	2399	.Avr35,
	2400	}),
	2401	CpuInfo(@This(), FeatureType).create(.Attiny20, "attiny20", &[_]FeatureType {
2404	2402	.Avr0,
2405	2403	.Sram,
	2404	.Break,
	2405	.Tinyencoding,
2406	2406	.Avrtiny,
2407		},
2408		CpuInfo(@This()).create(.Attiny22, "attiny22", &[_]FeatureType {
2409		.Ijmpcall,
2410		.Sram,
	2407	}),
	2408	CpuInfo(@This(), FeatureType).create(.Attiny22, "attiny22", &[_]FeatureType {
	2409	.Lpm,
2411	2410	.Avr0,
	2411	.Sram,
2412	2412	.Addsubiw,
2413		.Lpm,
2414		.Avr2,
2415		},
2416		CpuInfo(@This()).create(.Attiny2313, "attiny2313", &[_]FeatureType {
2417	2413	.Ijmpcall,
	2414	.Avr2,
	2415	}),
	2416	CpuInfo(@This(), FeatureType).create(.Attiny2313, "attiny2313", &[_]FeatureType {
	2417	.Lpm,
2418	2418	.Movw,
2419		.Sram,
2420		.Break,
2421	2419	.Spm,
2422		.Lpmx,
2423	2420	.Avr0,
	2421	.Sram,
2424	2422	.Addsubiw,
2425		.Lpm,
2426		.Avr25,
2427		},
2428		CpuInfo(@This()).create(.Attiny2313a, "attiny2313a", &[_]FeatureType {
	2423	.Lpmx,
2429	2424	.Ijmpcall,
2430		.Movw,
2431		.Sram,
2432	2425	.Break,
	2426	.Avr25,
	2427	}),
	2428	CpuInfo(@This(), FeatureType).create(.Attiny2313a, "attiny2313a", &[_]FeatureType {
	2429	.Lpm,
	2430	.Movw,
2433	2431	.Spm,
2434		.Lpmx,
2435	2432	.Avr0,
	2433	.Sram,
2436	2434	.Addsubiw,
2437		.Lpm,
2438		.Avr25,
2439		},
2440		CpuInfo(@This()).create(.Attiny24, "attiny24", &[_]FeatureType {
	2435	.Lpmx,
2441	2436	.Ijmpcall,
2442		.Movw,
2443		.Sram,
2444	2437	.Break,
	2438	.Avr25,
	2439	}),
	2440	CpuInfo(@This(), FeatureType).create(.Attiny24, "attiny24", &[_]FeatureType {
	2441	.Lpm,
	2442	.Movw,
2445	2443	.Spm,
2446		.Lpmx,
2447	2444	.Avr0,
	2445	.Sram,
2448	2446	.Addsubiw,
2449		.Lpm,
2450		.Avr25,
2451		},
2452		CpuInfo(@This()).create(.Attiny24a, "attiny24a", &[_]FeatureType {
	2447	.Lpmx,
2453	2448	.Ijmpcall,
2454		.Movw,
2455		.Sram,
2456	2449	.Break,
	2450	.Avr25,
	2451	}),
	2452	CpuInfo(@This(), FeatureType).create(.Attiny24a, "attiny24a", &[_]FeatureType {
	2453	.Lpm,
	2454	.Movw,
2457	2455	.Spm,
2458		.Lpmx,
2459	2456	.Avr0,
	2457	.Sram,
2460	2458	.Addsubiw,
2461		.Lpm,
2462		.Avr25,
2463		},
2464		CpuInfo(@This()).create(.Attiny25, "attiny25", &[_]FeatureType {
	2459	.Lpmx,
2465	2460	.Ijmpcall,
2466		.Movw,
2467		.Sram,
2468	2461	.Break,
	2462	.Avr25,
	2463	}),
	2464	CpuInfo(@This(), FeatureType).create(.Attiny25, "attiny25", &[_]FeatureType {
	2465	.Lpm,
	2466	.Movw,
2469	2467	.Spm,
2470		.Lpmx,
2471	2468	.Avr0,
	2469	.Sram,
2472	2470	.Addsubiw,
2473		.Lpm,
2474		.Avr25,
2475		},
2476		CpuInfo(@This()).create(.Attiny26, "attiny26", &[_]FeatureType {
	2471	.Lpmx,
2477	2472	.Ijmpcall,
2478		.Sram,
	2473	.Break,
	2474	.Avr25,
	2475	}),
	2476	CpuInfo(@This(), FeatureType).create(.Attiny26, "attiny26", &[_]FeatureType {
	2477	.Lpm,
2479	2478	.Avr0,
	2479	.Sram,
2480	2480	.Addsubiw,
2481		.Lpm,
	2481	.Ijmpcall,
2482	2482	.Avr2,
2483	2483	.Lpmx,
2484		},
2485		CpuInfo(@This()).create(.Attiny261, "attiny261", &[_]FeatureType {
2486		.Ijmpcall,
	2484	}),
	2485	CpuInfo(@This(), FeatureType).create(.Attiny261, "attiny261", &[_]FeatureType {
	2486	.Lpm,
2487	2487	.Movw,
2488		.Sram,
2489		.Break,
2490	2488	.Spm,
2491		.Lpmx,
2492	2489	.Avr0,
	2490	.Sram,
2493	2491	.Addsubiw,
2494		.Lpm,
2495		.Avr25,
2496		},
2497		CpuInfo(@This()).create(.Attiny261a, "attiny261a", &[_]FeatureType {
	2492	.Lpmx,
2498	2493	.Ijmpcall,
2499		.Movw,
2500		.Sram,
2501	2494	.Break,
	2495	.Avr25,
	2496	}),
	2497	CpuInfo(@This(), FeatureType).create(.Attiny261a, "attiny261a", &[_]FeatureType {
	2498	.Lpm,
	2499	.Movw,
2502	2500	.Spm,
2503		.Lpmx,
2504	2501	.Avr0,
	2502	.Sram,
2505	2503	.Addsubiw,
2506		.Lpm,
	2504	.Lpmx,
	2505	.Ijmpcall,
	2506	.Break,
2507	2507	.Avr25,
2508		},
2509		CpuInfo(@This()).create(.Attiny28, "attiny28", &[_]FeatureType {
2510		.Lpm,
	2508	}),
	2509	CpuInfo(@This(), FeatureType).create(.Attiny28, "attiny28", &[_]FeatureType {
2511	2510	.Avr0,
	2511	.Lpm,
2512	2512	.Avr1,
2513		},
2514		CpuInfo(@This()).create(.Attiny4, "attiny4", &[_]FeatureType {
2515		.Break,
2516		.Tinyencoding,
	2513	}),
	2514	CpuInfo(@This(), FeatureType).create(.Attiny4, "attiny4", &[_]FeatureType {
2517	2515	.Avr0,
2518	2516	.Sram,
2519		.Avrtiny,
2520		},
2521		CpuInfo(@This()).create(.Attiny40, "attiny40", &[_]FeatureType {
2522	2517	.Break,
2523	2518	.Tinyencoding,
	2519	.Avrtiny,
	2520	}),
	2521	CpuInfo(@This(), FeatureType).create(.Attiny40, "attiny40", &[_]FeatureType {
2524	2522	.Avr0,
2525	2523	.Sram,
	2524	.Break,
	2525	.Tinyencoding,
2526	2526	.Avrtiny,
2527		},
2528		CpuInfo(@This()).create(.Attiny4313, "attiny4313", &[_]FeatureType {
2529		.Ijmpcall,
	2527	}),
	2528	CpuInfo(@This(), FeatureType).create(.Attiny4313, "attiny4313", &[_]FeatureType {
	2529	.Lpm,
2530	2530	.Movw,
2531		.Sram,
2532		.Break,
2533	2531	.Spm,
2534		.Lpmx,
2535	2532	.Avr0,
	2533	.Sram,
2536	2534	.Addsubiw,
2537		.Lpm,
2538		.Avr25,
2539		},
2540		CpuInfo(@This()).create(.Attiny43u, "attiny43u", &[_]FeatureType {
	2535	.Lpmx,
2541	2536	.Ijmpcall,
2542		.Movw,
2543		.Sram,
2544	2537	.Break,
	2538	.Avr25,
	2539	}),
	2540	CpuInfo(@This(), FeatureType).create(.Attiny43u, "attiny43u", &[_]FeatureType {
	2541	.Lpm,
	2542	.Movw,
2545	2543	.Spm,
2546		.Lpmx,
2547	2544	.Avr0,
	2545	.Sram,
2548	2546	.Addsubiw,
2549		.Lpm,
2550		.Avr25,
2551		},
2552		CpuInfo(@This()).create(.Attiny44, "attiny44", &[_]FeatureType {
	2547	.Lpmx,
2553	2548	.Ijmpcall,
2554		.Movw,
2555		.Sram,
2556	2549	.Break,
	2550	.Avr25,
	2551	}),
	2552	CpuInfo(@This(), FeatureType).create(.Attiny44, "attiny44", &[_]FeatureType {
	2553	.Lpm,
	2554	.Movw,
2557	2555	.Spm,
2558		.Lpmx,
2559	2556	.Avr0,
	2557	.Sram,
2560	2558	.Addsubiw,
2561		.Lpm,
2562		.Avr25,
2563		},
2564		CpuInfo(@This()).create(.Attiny44a, "attiny44a", &[_]FeatureType {
	2559	.Lpmx,
2565	2560	.Ijmpcall,
2566		.Movw,
2567		.Sram,
2568	2561	.Break,
	2562	.Avr25,
	2563	}),
	2564	CpuInfo(@This(), FeatureType).create(.Attiny44a, "attiny44a", &[_]FeatureType {
	2565	.Lpm,
	2566	.Movw,
2569	2567	.Spm,
2570		.Lpmx,
2571	2568	.Avr0,
	2569	.Sram,
2572	2570	.Addsubiw,
2573		.Lpm,
2574		.Avr25,
2575		},
2576		CpuInfo(@This()).create(.Attiny45, "attiny45", &[_]FeatureType {
	2571	.Lpmx,
2577	2572	.Ijmpcall,
2578		.Movw,
2579		.Sram,
2580	2573	.Break,
	2574	.Avr25,
	2575	}),
	2576	CpuInfo(@This(), FeatureType).create(.Attiny45, "attiny45", &[_]FeatureType {
	2577	.Lpm,
	2578	.Movw,
2581	2579	.Spm,
2582		.Lpmx,
2583	2580	.Avr0,
	2581	.Sram,
2584	2582	.Addsubiw,
2585		.Lpm,
2586		.Avr25,
2587		},
2588		CpuInfo(@This()).create(.Attiny461, "attiny461", &[_]FeatureType {
	2583	.Lpmx,
2589	2584	.Ijmpcall,
2590		.Movw,
2591		.Sram,
2592	2585	.Break,
	2586	.Avr25,
	2587	}),
	2588	CpuInfo(@This(), FeatureType).create(.Attiny461, "attiny461", &[_]FeatureType {
	2589	.Lpm,
	2590	.Movw,
2593	2591	.Spm,
2594		.Lpmx,
2595	2592	.Avr0,
	2593	.Sram,
2596	2594	.Addsubiw,
2597		.Lpm,
2598		.Avr25,
2599		},
2600		CpuInfo(@This()).create(.Attiny461a, "attiny461a", &[_]FeatureType {
	2595	.Lpmx,
2601	2596	.Ijmpcall,
2602		.Movw,
2603		.Sram,
2604	2597	.Break,
	2598	.Avr25,
	2599	}),
	2600	CpuInfo(@This(), FeatureType).create(.Attiny461a, "attiny461a", &[_]FeatureType {
	2601	.Lpm,
	2602	.Movw,
2605	2603	.Spm,
2606		.Lpmx,
2607	2604	.Avr0,
	2605	.Sram,
2608	2606	.Addsubiw,
2609		.Lpm,
2610		.Avr25,
2611		},
2612		CpuInfo(@This()).create(.Attiny48, "attiny48", &[_]FeatureType {
	2607	.Lpmx,
2613	2608	.Ijmpcall,
2614		.Movw,
2615		.Sram,
2616	2609	.Break,
	2610	.Avr25,
	2611	}),
	2612	CpuInfo(@This(), FeatureType).create(.Attiny48, "attiny48", &[_]FeatureType {
	2613	.Lpm,
	2614	.Movw,
2617	2615	.Spm,
2618		.Lpmx,
2619	2616	.Avr0,
	2617	.Sram,
2620	2618	.Addsubiw,
2621		.Lpm,
2622		.Avr25,
2623		},
2624		CpuInfo(@This()).create(.Attiny5, "attiny5", &[_]FeatureType {
	2619	.Lpmx,
	2620	.Ijmpcall,
2625	2621	.Break,
2626		.Tinyencoding,
	2622	.Avr25,
	2623	}),
	2624	CpuInfo(@This(), FeatureType).create(.Attiny5, "attiny5", &[_]FeatureType {
2627	2625	.Avr0,
2628	2626	.Sram,
	2627	.Break,
	2628	.Tinyencoding,
2629	2629	.Avrtiny,
2630		},
2631		CpuInfo(@This()).create(.Attiny828, "attiny828", &[_]FeatureType {
2632		.Ijmpcall,
	2630	}),
	2631	CpuInfo(@This(), FeatureType).create(.Attiny828, "attiny828", &[_]FeatureType {
	2632	.Lpm,
2633	2633	.Movw,
2634		.Sram,
2635		.Break,
2636	2634	.Spm,
2637		.Lpmx,
2638	2635	.Avr0,
	2636	.Sram,
2639	2637	.Addsubiw,
2640		.Lpm,
2641		.Avr25,
2642		},
2643		CpuInfo(@This()).create(.Attiny84, "attiny84", &[_]FeatureType {
	2638	.Lpmx,
2644	2639	.Ijmpcall,
2645		.Movw,
2646		.Sram,
2647	2640	.Break,
	2641	.Avr25,
	2642	}),
	2643	CpuInfo(@This(), FeatureType).create(.Attiny84, "attiny84", &[_]FeatureType {
	2644	.Lpm,
	2645	.Movw,
2648	2646	.Spm,
2649		.Lpmx,
2650	2647	.Avr0,
	2648	.Sram,
2651	2649	.Addsubiw,
2652		.Lpm,
2653		.Avr25,
2654		},
2655		CpuInfo(@This()).create(.Attiny84a, "attiny84a", &[_]FeatureType {
	2650	.Lpmx,
2656	2651	.Ijmpcall,
2657		.Movw,
2658		.Sram,
2659	2652	.Break,
	2653	.Avr25,
	2654	}),
	2655	CpuInfo(@This(), FeatureType).create(.Attiny84a, "attiny84a", &[_]FeatureType {
	2656	.Lpm,
	2657	.Movw,
2660	2658	.Spm,
2661		.Lpmx,
2662	2659	.Avr0,
	2660	.Sram,
2663	2661	.Addsubiw,
2664		.Lpm,
2665		.Avr25,
2666		},
2667		CpuInfo(@This()).create(.Attiny85, "attiny85", &[_]FeatureType {
	2662	.Lpmx,
2668	2663	.Ijmpcall,
2669		.Movw,
2670		.Sram,
2671	2664	.Break,
	2665	.Avr25,
	2666	}),
	2667	CpuInfo(@This(), FeatureType).create(.Attiny85, "attiny85", &[_]FeatureType {
	2668	.Lpm,
	2669	.Movw,
2672	2670	.Spm,
2673		.Lpmx,
2674	2671	.Avr0,
	2672	.Sram,
2675	2673	.Addsubiw,
2676		.Lpm,
2677		.Avr25,
2678		},
2679		CpuInfo(@This()).create(.Attiny861, "attiny861", &[_]FeatureType {
	2674	.Lpmx,
2680	2675	.Ijmpcall,
2681		.Movw,
2682		.Sram,
2683	2676	.Break,
	2677	.Avr25,
	2678	}),
	2679	CpuInfo(@This(), FeatureType).create(.Attiny861, "attiny861", &[_]FeatureType {
	2680	.Lpm,
	2681	.Movw,
2684	2682	.Spm,
2685		.Lpmx,
2686	2683	.Avr0,
	2684	.Sram,
2687	2685	.Addsubiw,
2688		.Lpm,
2689		.Avr25,
2690		},
2691		CpuInfo(@This()).create(.Attiny861a, "attiny861a", &[_]FeatureType {
	2686	.Lpmx,
2692	2687	.Ijmpcall,
2693		.Movw,
2694		.Sram,
2695	2688	.Break,
	2689	.Avr25,
	2690	}),
	2691	CpuInfo(@This(), FeatureType).create(.Attiny861a, "attiny861a", &[_]FeatureType {
	2692	.Lpm,
	2693	.Movw,
2696	2694	.Spm,
2697		.Lpmx,
2698	2695	.Avr0,
	2696	.Sram,
2699	2697	.Addsubiw,
2700		.Lpm,
2701		.Avr25,
2702		},
2703		CpuInfo(@This()).create(.Attiny87, "attiny87", &[_]FeatureType {
	2698	.Lpmx,
2704	2699	.Ijmpcall,
2705		.Movw,
2706		.Sram,
2707	2700	.Break,
	2701	.Avr25,
	2702	}),
	2703	CpuInfo(@This(), FeatureType).create(.Attiny87, "attiny87", &[_]FeatureType {
	2704	.Lpm,
	2705	.Movw,
2708	2706	.Spm,
2709		.Lpmx,
2710	2707	.Avr0,
	2708	.Sram,
2711	2709	.Addsubiw,
2712		.Lpm,
2713		.Avr25,
2714		},
2715		CpuInfo(@This()).create(.Attiny88, "attiny88", &[_]FeatureType {
	2710	.Lpmx,
2716	2711	.Ijmpcall,
2717		.Movw,
2718		.Sram,
2719	2712	.Break,
	2713	.Avr25,
	2714	}),
	2715	CpuInfo(@This(), FeatureType).create(.Attiny88, "attiny88", &[_]FeatureType {
	2716	.Lpm,
	2717	.Movw,
2720	2718	.Spm,
2721		.Lpmx,
2722	2719	.Avr0,
	2720	.Sram,
2723	2721	.Addsubiw,
2724		.Lpm,
2725		.Avr25,
2726		},
2727		CpuInfo(@This()).create(.Attiny9, "attiny9", &[_]FeatureType {
	2722	.Lpmx,
	2723	.Ijmpcall,
2728	2724	.Break,
2729		.Tinyencoding,
	2725	.Avr25,
	2726	}),
	2727	CpuInfo(@This(), FeatureType).create(.Attiny9, "attiny9", &[_]FeatureType {
2730	2728	.Avr0,
2731	2729	.Sram,
	2730	.Break,
	2731	.Tinyencoding,
2732	2732	.Avrtiny,
2733		},
2734		CpuInfo(@This()).create(.Atxmega128a1, "atxmega128a1", &[_]FeatureType {
2735		.Ijmpcall,
2736		.Elpmx,
	2733	}),
	2734	CpuInfo(@This(), FeatureType).create(.Atxmega128a1, "atxmega128a1", &[_]FeatureType {
	2735	.Lpm,
	2736	.Elpm,
2737	2737	.Movw,
2738		.Eijmpcall,
2739		.Mul,
2740		.Sram,
2741		.Break,
	2738	.Elpmx,
2742	2739	.Spm,
2743		.Elpm,
2744		.Lpmx,
2745		.Spmx,
2746	2740	.Avr0,
	2741	.Sram,
2747	2742	.Jmpcall,
	2743	.Eijmpcall,
	2744	.Spmx,
2748	2745	.Addsubiw,
2749		.Lpm,
	2746	.Mul,
	2747	.Lpmx,
2750	2748	.Des,
2751		.Xmega,
2752		},
2753		CpuInfo(@This()).create(.Atxmega128a1u, "atxmega128a1u", &[_]FeatureType {
2754	2749	.Ijmpcall,
2755		.Elpmx,
2756		.Movw,
2757		.Eijmpcall,
2758		.Mul,
2759		.Rmw,
2760		.Sram,
2761	2750	.Break,
2762		.Spm,
	2751	.Xmega,
	2752	}),
	2753	CpuInfo(@This(), FeatureType).create(.Atxmega128a1u, "atxmega128a1u", &[_]FeatureType {
	2754	.Lpm,
2763	2755	.Elpm,
2764		.Lpmx,
2765		.Spmx,
	2756	.Movw,
	2757	.Elpmx,
	2758	.Spm,
2766	2759	.Avr0,
	2760	.Sram,
2767	2761	.Jmpcall,
	2762	.Eijmpcall,
	2763	.Spmx,
2768	2764	.Addsubiw,
2769		.Lpm,
	2765	.Mul,
	2766	.Lpmx,
	2767	.Rmw,
2770	2768	.Des,
2771		.Xmegau,
2772		},
2773		CpuInfo(@This()).create(.Atxmega128a3, "atxmega128a3", &[_]FeatureType {
2774	2769	.Ijmpcall,
2775		.Elpmx,
2776		.Movw,
2777		.Eijmpcall,
2778		.Mul,
2779		.Sram,
2780	2770	.Break,
2781		.Spm,
	2771	.Xmegau,
	2772	}),
	2773	CpuInfo(@This(), FeatureType).create(.Atxmega128a3, "atxmega128a3", &[_]FeatureType {
	2774	.Lpm,
2782	2775	.Elpm,
2783		.Lpmx,
2784		.Spmx,
	2776	.Movw,
	2777	.Elpmx,
	2778	.Spm,
2785	2779	.Avr0,
	2780	.Sram,
2786	2781	.Jmpcall,
	2782	.Eijmpcall,
	2783	.Spmx,
2787	2784	.Addsubiw,
2788		.Lpm,
	2785	.Mul,
	2786	.Lpmx,
2789	2787	.Des,
2790		.Xmega,
2791		},
2792		CpuInfo(@This()).create(.Atxmega128a3u, "atxmega128a3u", &[_]FeatureType {
2793	2788	.Ijmpcall,
2794		.Elpmx,
	2789	.Break,
	2790	.Xmega,
	2791	}),
	2792	CpuInfo(@This(), FeatureType).create(.Atxmega128a3u, "atxmega128a3u", &[_]FeatureType {
	2793	.Lpm,
	2794	.Elpm,
2795	2795	.Movw,
	2796	.Elpmx,
	2797	.Spm,
	2798	.Avr0,
	2799	.Sram,
	2800	.Jmpcall,
2796	2801	.Eijmpcall,
	2802	.Spmx,
	2803	.Addsubiw,
2797	2804	.Mul,
	2805	.Lpmx,
2798	2806	.Rmw,
2799		.Sram,
	2807	.Des,
	2808	.Ijmpcall,
2800	2809	.Break,
2801		.Spm,
	2810	.Xmegau,
	2811	}),
	2812	CpuInfo(@This(), FeatureType).create(.Atxmega128a4u, "atxmega128a4u", &[_]FeatureType {
	2813	.Lpm,
2802	2814	.Elpm,
2803		.Lpmx,
2804		.Spmx,
	2815	.Movw,
	2816	.Elpmx,
	2817	.Spm,
2805	2818	.Avr0,
	2819	.Sram,
2806	2820	.Jmpcall,
	2821	.Eijmpcall,
	2822	.Spmx,
2807	2823	.Addsubiw,
2808		.Lpm,
	2824	.Mul,
	2825	.Lpmx,
	2826	.Rmw,
2809	2827	.Des,
2810		.Xmegau,
2811		},
2812		CpuInfo(@This()).create(.Atxmega128a4u, "atxmega128a4u", &[_]FeatureType {
2813	2828	.Ijmpcall,
2814		.Elpmx,
	2829	.Break,
	2830	.Xmegau,
	2831	}),
	2832	CpuInfo(@This(), FeatureType).create(.Atxmega128b1, "atxmega128b1", &[_]FeatureType {
	2833	.Lpm,
	2834	.Elpm,
2815	2835	.Movw,
	2836	.Elpmx,
	2837	.Spm,
	2838	.Avr0,
	2839	.Sram,
	2840	.Jmpcall,
2816	2841	.Eijmpcall,
	2842	.Spmx,
	2843	.Addsubiw,
2817	2844	.Mul,
	2845	.Lpmx,
2818	2846	.Rmw,
2819		.Sram,
	2847	.Des,
	2848	.Ijmpcall,
2820	2849	.Break,
2821		.Spm,
	2850	.Xmegau,
	2851	}),
	2852	CpuInfo(@This(), FeatureType).create(.Atxmega128b3, "atxmega128b3", &[_]FeatureType {
	2853	.Lpm,
2822	2854	.Elpm,
2823		.Lpmx,
2824		.Spmx,
	2855	.Movw,
	2856	.Elpmx,
	2857	.Spm,
2825	2858	.Avr0,
	2859	.Sram,
2826	2860	.Jmpcall,
	2861	.Eijmpcall,
	2862	.Spmx,
2827	2863	.Addsubiw,
2828		.Lpm,
	2864	.Mul,
	2865	.Lpmx,
	2866	.Rmw,
2829	2867	.Des,
2830		.Xmegau,
2831		},
2832		CpuInfo(@This()).create(.Atxmega128b1, "atxmega128b1", &[_]FeatureType {
2833	2868	.Ijmpcall,
2834		.Elpmx,
	2869	.Break,
	2870	.Xmegau,
	2871	}),
	2872	CpuInfo(@This(), FeatureType).create(.Atxmega128c3, "atxmega128c3", &[_]FeatureType {
	2873	.Lpm,
	2874	.Elpm,
2835	2875	.Movw,
	2876	.Elpmx,
	2877	.Spm,
	2878	.Avr0,
	2879	.Sram,
	2880	.Jmpcall,
2836	2881	.Eijmpcall,
	2882	.Spmx,
	2883	.Addsubiw,
2837	2884	.Mul,
	2885	.Lpmx,
2838	2886	.Rmw,
2839		.Sram,
	2887	.Des,
	2888	.Ijmpcall,
2840	2889	.Break,
2841		.Spm,
	2890	.Xmegau,
	2891	}),
	2892	CpuInfo(@This(), FeatureType).create(.Atxmega128d3, "atxmega128d3", &[_]FeatureType {
	2893	.Lpm,
2842	2894	.Elpm,
2843		.Lpmx,
2844		.Spmx,
	2895	.Movw,
	2896	.Elpmx,
	2897	.Spm,
2845	2898	.Avr0,
	2899	.Sram,
2846	2900	.Jmpcall,
	2901	.Eijmpcall,
	2902	.Spmx,
2847	2903	.Addsubiw,
2848		.Lpm,
	2904	.Mul,
	2905	.Lpmx,
2849	2906	.Des,
2850		.Xmegau,
2851		},
2852		CpuInfo(@This()).create(.Atxmega128b3, "atxmega128b3", &[_]FeatureType {
2853	2907	.Ijmpcall,
2854		.Elpmx,
2855		.Movw,
2856		.Eijmpcall,
2857		.Mul,
2858		.Rmw,
2859		.Sram,
2860	2908	.Break,
2861		.Spm,
	2909	.Xmega,
	2910	}),
	2911	CpuInfo(@This(), FeatureType).create(.Atxmega128d4, "atxmega128d4", &[_]FeatureType {
	2912	.Lpm,
2862	2913	.Elpm,
2863		.Lpmx,
2864		.Spmx,
	2914	.Movw,
	2915	.Elpmx,
	2916	.Spm,
2865	2917	.Avr0,
	2918	.Sram,
2866	2919	.Jmpcall,
	2920	.Eijmpcall,
	2921	.Spmx,
2867	2922	.Addsubiw,
2868		.Lpm,
	2923	.Mul,
	2924	.Lpmx,
2869	2925	.Des,
2870		.Xmegau,
2871		},
2872		CpuInfo(@This()).create(.Atxmega128c3, "atxmega128c3", &[_]FeatureType {
2873	2926	.Ijmpcall,
2874		.Elpmx,
2875		.Movw,
2876		.Eijmpcall,
2877		.Mul,
2878		.Rmw,
2879		.Sram,
2880	2927	.Break,
2881		.Spm,
	2928	.Xmega,
	2929	}),
	2930	CpuInfo(@This(), FeatureType).create(.Atxmega16a4, "atxmega16a4", &[_]FeatureType {
	2931	.Lpm,
2882	2932	.Elpm,
2883		.Lpmx,
2884		.Spmx,
	2933	.Movw,
	2934	.Elpmx,
	2935	.Spm,
2885	2936	.Avr0,
	2937	.Sram,
2886	2938	.Jmpcall,
	2939	.Eijmpcall,
	2940	.Spmx,
2887	2941	.Addsubiw,
2888		.Lpm,
	2942	.Mul,
	2943	.Lpmx,
2889	2944	.Des,
2890		.Xmegau,
2891		},
2892		CpuInfo(@This()).create(.Atxmega128d3, "atxmega128d3", &[_]FeatureType {
2893	2945	.Ijmpcall,
2894		.Elpmx,
2895		.Movw,
2896		.Eijmpcall,
2897		.Mul,
2898		.Sram,
2899	2946	.Break,
2900		.Spm,
	2947	.Xmega,
	2948	}),
	2949	CpuInfo(@This(), FeatureType).create(.Atxmega16a4u, "atxmega16a4u", &[_]FeatureType {
	2950	.Lpm,
2901	2951	.Elpm,
2902		.Lpmx,
2903		.Spmx,
	2952	.Movw,
	2953	.Elpmx,
	2954	.Spm,
2904	2955	.Avr0,
	2956	.Sram,
2905	2957	.Jmpcall,
	2958	.Eijmpcall,
	2959	.Spmx,
2906	2960	.Addsubiw,
2907		.Lpm,
	2961	.Mul,
	2962	.Lpmx,
	2963	.Rmw,
2908	2964	.Des,
2909		.Xmega,
2910		},
2911		CpuInfo(@This()).create(.Atxmega128d4, "atxmega128d4", &[_]FeatureType {
2912	2965	.Ijmpcall,
2913		.Elpmx,
2914		.Movw,
2915		.Eijmpcall,
2916		.Mul,
2917		.Sram,
2918	2966	.Break,
2919		.Spm,
2920		.Elpm,
2921		.Lpmx,
2922		.Spmx,
2923		.Avr0,
2924		.Jmpcall,
2925		.Addsubiw,
	2967	.Xmegau,
	2968	}),
	2969	CpuInfo(@This(), FeatureType).create(.Atxmega16c4, "atxmega16c4", &[_]FeatureType {
2926	2970	.Lpm,
2927		.Des,
2928		.Xmega,
2929		},
2930		CpuInfo(@This()).create(.Atxmega16a4, "atxmega16a4", &[_]FeatureType {
2931		.Ijmpcall,
2932		.Elpmx,
	2971	.Elpm,
2933	2972	.Movw,
2934		.Eijmpcall,
2935		.Mul,
2936		.Sram,
2937		.Break,
	2973	.Elpmx,
2938	2974	.Spm,
2939		.Elpm,
2940		.Lpmx,
2941		.Spmx,
2942	2975	.Avr0,
	2976	.Sram,
2943	2977	.Jmpcall,
2944		.Addsubiw,
2945		.Lpm,
2946		.Des,
2947		.Xmega,
2948		},
2949		CpuInfo(@This()).create(.Atxmega16a4u, "atxmega16a4u", &[_]FeatureType {
2950		.Ijmpcall,
2951		.Elpmx,
2952		.Movw,
2953	2978	.Eijmpcall,
2954		.Mul,
2955		.Rmw,
2956		.Sram,
2957		.Break,
2958		.Spm,
2959		.Elpm,
2960		.Lpmx,
2961	2979	.Spmx,
2962		.Avr0,
2963		.Jmpcall,
2964	2980	.Addsubiw,
2965		.Lpm,
2966		.Des,
2967		.Xmegau,
2968		},
2969		CpuInfo(@This()).create(.Atxmega16c4, "atxmega16c4", &[_]FeatureType {
2970		.Ijmpcall,
2971		.Elpmx,
2972		.Movw,
2973		.Eijmpcall,
2974	2981	.Mul,
2975		.Rmw,
2976		.Sram,
2977		.Break,
2978		.Spm,
2979		.Elpm,
2980	2982	.Lpmx,
2981		.Spmx,
2982		.Avr0,
2983		.Jmpcall,
2984		.Addsubiw,
2985		.Lpm,
	2983	.Rmw,
2986	2984	.Des,
2987		.Xmegau,
2988		},
2989		CpuInfo(@This()).create(.Atxmega16d4, "atxmega16d4", &[_]FeatureType {
2990	2985	.Ijmpcall,
2991		.Elpmx,
2992		.Movw,
2993		.Eijmpcall,
2994		.Mul,
2995		.Sram,
2996	2986	.Break,
2997		.Spm,
2998		.Elpm,
2999		.Lpmx,
3000		.Spmx,
3001		.Avr0,
3002		.Jmpcall,
3003		.Addsubiw,
	2987	.Xmegau,
	2988	}),
	2989	CpuInfo(@This(), FeatureType).create(.Atxmega16d4, "atxmega16d4", &[_]FeatureType {
3004	2990	.Lpm,
3005		.Des,
3006		.Xmega,
3007		},
3008		CpuInfo(@This()).create(.Atxmega16e5, "atxmega16e5", &[_]FeatureType {
3009		.Ijmpcall,
3010		.Elpmx,
	2991	.Elpm,
3011	2992	.Movw,
3012		.Eijmpcall,
3013		.Mul,
3014		.Sram,
3015		.Break,
	2993	.Elpmx,
3016	2994	.Spm,
3017		.Elpm,
3018		.Lpmx,
3019		.Spmx,
3020	2995	.Avr0,
	2996	.Sram,
3021	2997	.Jmpcall,
3022		.Addsubiw,
3023		.Lpm,
3024		.Des,
3025		.Xmega,
3026		},
3027		CpuInfo(@This()).create(.Atxmega192a3, "atxmega192a3", &[_]FeatureType {
3028		.Ijmpcall,
3029		.Elpmx,
3030		.Movw,
3031	2998	.Eijmpcall,
3032		.Mul,
3033		.Sram,
3034		.Break,
3035		.Spm,
3036		.Elpm,
3037		.Lpmx,
3038	2999	.Spmx,
3039		.Avr0,
3040		.Jmpcall,
3041	3000	.Addsubiw,
3042		.Lpm,
3043		.Des,
3044		.Xmega,
3045		},
3046		CpuInfo(@This()).create(.Atxmega192a3u, "atxmega192a3u", &[_]FeatureType {
3047		.Ijmpcall,
3048		.Elpmx,
3049		.Movw,
3050		.Eijmpcall,
3051	3001	.Mul,
3052		.Rmw,
3053		.Sram,
3054		.Break,
3055		.Spm,
3056		.Elpm,
3057	3002	.Lpmx,
3058		.Spmx,
3059		.Avr0,
3060		.Jmpcall,
3061		.Addsubiw,
3062		.Lpm,
3063	3003	.Des,
3064		.Xmegau,
3065		},
3066		CpuInfo(@This()).create(.Atxmega192c3, "atxmega192c3", &[_]FeatureType {
3067	3004	.Ijmpcall,
3068		.Elpmx,
3069		.Movw,
3070		.Eijmpcall,
3071		.Mul,
3072		.Rmw,
3073		.Sram,
3074	3005	.Break,
3075		.Spm,
3076		.Elpm,
3077		.Lpmx,
3078		.Spmx,
3079		.Avr0,
3080		.Jmpcall,
3081		.Addsubiw,
	3006	.Xmega,
	3007	}),
	3008	CpuInfo(@This(), FeatureType).create(.Atxmega16e5, "atxmega16e5", &[_]FeatureType {
3082	3009	.Lpm,
3083		.Des,
3084		.Xmegau,
3085		},
3086		CpuInfo(@This()).create(.Atxmega192d3, "atxmega192d3", &[_]FeatureType {
3087		.Ijmpcall,
3088		.Elpmx,
	3010	.Elpm,
3089	3011	.Movw,
3090		.Eijmpcall,
3091		.Mul,
3092		.Sram,
3093		.Break,
	3012	.Elpmx,
3094	3013	.Spm,
3095		.Elpm,
3096		.Lpmx,
3097		.Spmx,
3098	3014	.Avr0,
	3015	.Sram,
3099	3016	.Jmpcall,
3100		.Addsubiw,
3101		.Lpm,
3102		.Des,
3103		.Xmega,
3104		},
3105		CpuInfo(@This()).create(.Atxmega256a3, "atxmega256a3", &[_]FeatureType {
3106		.Ijmpcall,
3107		.Elpmx,
3108		.Movw,
3109	3017	.Eijmpcall,
3110		.Mul,
3111		.Sram,
3112		.Break,
3113		.Spm,
3114		.Elpm,
3115		.Lpmx,
3116	3018	.Spmx,
3117		.Avr0,
3118		.Jmpcall,
3119	3019	.Addsubiw,
3120		.Lpm,
3121		.Des,
3122		.Xmega,
3123		},
3124		CpuInfo(@This()).create(.Atxmega256a3b, "atxmega256a3b", &[_]FeatureType {
3125		.Ijmpcall,
3126		.Elpmx,
3127		.Movw,
3128		.Eijmpcall,
3129	3020	.Mul,
3130		.Sram,
3131		.Break,
3132		.Spm,
3133		.Elpm,
3134	3021	.Lpmx,
3135		.Spmx,
3136		.Avr0,
3137		.Jmpcall,
3138		.Addsubiw,
3139		.Lpm,
3140	3022	.Des,
3141		.Xmega,
3142		},
3143		CpuInfo(@This()).create(.Atxmega256a3bu, "atxmega256a3bu", &[_]FeatureType {
3144	3023	.Ijmpcall,
3145		.Elpmx,
3146		.Movw,
3147		.Eijmpcall,
3148		.Mul,
3149		.Rmw,
3150		.Sram,
3151	3024	.Break,
3152		.Spm,
	3025	.Xmega,
	3026	}),
	3027	CpuInfo(@This(), FeatureType).create(.Atxmega192a3, "atxmega192a3", &[_]FeatureType {
	3028	.Lpm,
3153	3029	.Elpm,
3154		.Lpmx,
3155		.Spmx,
	3030	.Movw,
	3031	.Elpmx,
	3032	.Spm,
3156	3033	.Avr0,
	3034	.Sram,
3157	3035	.Jmpcall,
	3036	.Eijmpcall,
	3037	.Spmx,
3158	3038	.Addsubiw,
3159		.Lpm,
	3039	.Mul,
	3040	.Lpmx,
3160	3041	.Des,
3161		.Xmegau,
3162		},
3163		CpuInfo(@This()).create(.Atxmega256a3u, "atxmega256a3u", &[_]FeatureType {
3164	3042	.Ijmpcall,
3165		.Elpmx,
3166		.Movw,
3167		.Eijmpcall,
3168		.Mul,
3169		.Rmw,
3170		.Sram,
3171	3043	.Break,
3172		.Spm,
	3044	.Xmega,
	3045	}),
	3046	CpuInfo(@This(), FeatureType).create(.Atxmega192a3u, "atxmega192a3u", &[_]FeatureType {
	3047	.Lpm,
3173	3048	.Elpm,
3174		.Lpmx,
3175		.Spmx,
	3049	.Movw,
	3050	.Elpmx,
	3051	.Spm,
3176	3052	.Avr0,
	3053	.Sram,
3177	3054	.Jmpcall,
3178		.Addsubiw,
3179		.Lpm,
3180		.Des,
3181		.Xmegau,
3182		},
3183		CpuInfo(@This()).create(.Atxmega256c3, "atxmega256c3", &[_]FeatureType {
3184		.Ijmpcall,
3185		.Elpmx,
3186		.Movw,
3187	3055	.Eijmpcall,
	3056	.Spmx,
	3057	.Addsubiw,
3188	3058	.Mul,
	3059	.Lpmx,
3189	3060	.Rmw,
3190		.Sram,
	3061	.Des,
	3062	.Ijmpcall,
3191	3063	.Break,
3192		.Spm,
	3064	.Xmegau,
	3065	}),
	3066	CpuInfo(@This(), FeatureType).create(.Atxmega192c3, "atxmega192c3", &[_]FeatureType {
	3067	.Lpm,
3193	3068	.Elpm,
3194		.Lpmx,
3195		.Spmx,
	3069	.Movw,
	3070	.Elpmx,
	3071	.Spm,
3196	3072	.Avr0,
	3073	.Sram,
3197	3074	.Jmpcall,
	3075	.Eijmpcall,
	3076	.Spmx,
3198	3077	.Addsubiw,
3199		.Lpm,
	3078	.Mul,
	3079	.Lpmx,
	3080	.Rmw,
3200	3081	.Des,
3201		.Xmegau,
3202		},
3203		CpuInfo(@This()).create(.Atxmega256d3, "atxmega256d3", &[_]FeatureType {
3204	3082	.Ijmpcall,
3205		.Elpmx,
3206		.Movw,
3207		.Eijmpcall,
3208		.Mul,
3209		.Sram,
3210	3083	.Break,
3211		.Spm,
	3084	.Xmegau,
	3085	}),
	3086	CpuInfo(@This(), FeatureType).create(.Atxmega192d3, "atxmega192d3", &[_]FeatureType {
	3087	.Lpm,
3212	3088	.Elpm,
3213		.Lpmx,
3214		.Spmx,
	3089	.Movw,
	3090	.Elpmx,
	3091	.Spm,
3215	3092	.Avr0,
	3093	.Sram,
3216	3094	.Jmpcall,
	3095	.Eijmpcall,
	3096	.Spmx,
3217	3097	.Addsubiw,
3218		.Lpm,
	3098	.Mul,
	3099	.Lpmx,
3219	3100	.Des,
3220		.Xmega,
3221		},
3222		CpuInfo(@This()).create(.Atxmega32a4, "atxmega32a4", &[_]FeatureType {
3223	3101	.Ijmpcall,
3224		.Elpmx,
3225		.Movw,
3226		.Eijmpcall,
3227		.Mul,
3228		.Sram,
3229	3102	.Break,
3230		.Spm,
	3103	.Xmega,
	3104	}),
	3105	CpuInfo(@This(), FeatureType).create(.Atxmega256a3, "atxmega256a3", &[_]FeatureType {
	3106	.Lpm,
3231	3107	.Elpm,
3232		.Lpmx,
3233		.Spmx,
	3108	.Movw,
	3109	.Elpmx,
	3110	.Spm,
3234	3111	.Avr0,
	3112	.Sram,
3235	3113	.Jmpcall,
	3114	.Eijmpcall,
	3115	.Spmx,
3236	3116	.Addsubiw,
3237		.Lpm,
	3117	.Mul,
	3118	.Lpmx,
3238	3119	.Des,
3239		.Xmega,
3240		},
3241		CpuInfo(@This()).create(.Atxmega32a4u, "atxmega32a4u", &[_]FeatureType {
3242	3120	.Ijmpcall,
3243		.Elpmx,
3244		.Movw,
3245		.Eijmpcall,
3246		.Mul,
3247		.Rmw,
3248		.Sram,
3249	3121	.Break,
3250		.Spm,
	3122	.Xmega,
	3123	}),
	3124	CpuInfo(@This(), FeatureType).create(.Atxmega256a3b, "atxmega256a3b", &[_]FeatureType {
	3125	.Lpm,
3251	3126	.Elpm,
3252		.Lpmx,
3253		.Spmx,
	3127	.Movw,
	3128	.Elpmx,
	3129	.Spm,
3254	3130	.Avr0,
	3131	.Sram,
3255	3132	.Jmpcall,
	3133	.Eijmpcall,
	3134	.Spmx,
3256	3135	.Addsubiw,
3257		.Lpm,
	3136	.Mul,
	3137	.Lpmx,
3258	3138	.Des,
3259		.Xmegau,
3260		},
3261		CpuInfo(@This()).create(.Atxmega32c4, "atxmega32c4", &[_]FeatureType {
3262	3139	.Ijmpcall,
3263		.Elpmx,
3264		.Movw,
3265		.Eijmpcall,
3266		.Mul,
3267		.Rmw,
3268		.Sram,
3269	3140	.Break,
3270		.Spm,
	3141	.Xmega,
	3142	}),
	3143	CpuInfo(@This(), FeatureType).create(.Atxmega256a3bu, "atxmega256a3bu", &[_]FeatureType {
	3144	.Lpm,
3271	3145	.Elpm,
3272		.Lpmx,
3273		.Spmx,
	3146	.Movw,
	3147	.Elpmx,
	3148	.Spm,
3274	3149	.Avr0,
	3150	.Sram,
3275	3151	.Jmpcall,
	3152	.Eijmpcall,
	3153	.Spmx,
3276	3154	.Addsubiw,
3277		.Lpm,
	3155	.Mul,
	3156	.Lpmx,
	3157	.Rmw,
3278	3158	.Des,
3279		.Xmegau,
3280		},
3281		CpuInfo(@This()).create(.Atxmega32d4, "atxmega32d4", &[_]FeatureType {
3282	3159	.Ijmpcall,
3283		.Elpmx,
3284		.Movw,
3285		.Eijmpcall,
3286		.Mul,
3287		.Sram,
3288	3160	.Break,
3289		.Spm,
	3161	.Xmegau,
	3162	}),
	3163	CpuInfo(@This(), FeatureType).create(.Atxmega256a3u, "atxmega256a3u", &[_]FeatureType {
	3164	.Lpm,
3290	3165	.Elpm,
3291		.Lpmx,
3292		.Spmx,
	3166	.Movw,
	3167	.Elpmx,
	3168	.Spm,
3293	3169	.Avr0,
	3170	.Sram,
3294	3171	.Jmpcall,
	3172	.Eijmpcall,
	3173	.Spmx,
3295	3174	.Addsubiw,
3296		.Lpm,
	3175	.Mul,
	3176	.Lpmx,
	3177	.Rmw,
3297	3178	.Des,
3298		.Xmega,
3299		},
3300		CpuInfo(@This()).create(.Atxmega32e5, "atxmega32e5", &[_]FeatureType {
3301	3179	.Ijmpcall,
3302		.Elpmx,
3303		.Movw,
3304		.Eijmpcall,
3305		.Mul,
3306		.Sram,
3307	3180	.Break,
3308		.Spm,
	3181	.Xmegau,
	3182	}),
	3183	CpuInfo(@This(), FeatureType).create(.Atxmega256c3, "atxmega256c3", &[_]FeatureType {
	3184	.Lpm,
3309	3185	.Elpm,
3310		.Lpmx,
3311		.Spmx,
	3186	.Movw,
	3187	.Elpmx,
	3188	.Spm,
3312	3189	.Avr0,
	3190	.Sram,
3313	3191	.Jmpcall,
	3192	.Eijmpcall,
	3193	.Spmx,
3314	3194	.Addsubiw,
3315		.Lpm,
	3195	.Mul,
	3196	.Lpmx,
	3197	.Rmw,
3316	3198	.Des,
3317		.Xmega,
3318		},
3319		CpuInfo(@This()).create(.Atxmega32x1, "atxmega32x1", &[_]FeatureType {
3320	3199	.Ijmpcall,
3321		.Elpmx,
3322		.Movw,
3323		.Eijmpcall,
3324		.Mul,
3325		.Sram,
3326	3200	.Break,
3327		.Spm,
	3201	.Xmegau,
	3202	}),
	3203	CpuInfo(@This(), FeatureType).create(.Atxmega256d3, "atxmega256d3", &[_]FeatureType {
	3204	.Lpm,
3328	3205	.Elpm,
3329		.Lpmx,
3330		.Spmx,
	3206	.Movw,
	3207	.Elpmx,
	3208	.Spm,
3331	3209	.Avr0,
	3210	.Sram,
3332	3211	.Jmpcall,
	3212	.Eijmpcall,
	3213	.Spmx,
3333	3214	.Addsubiw,
3334		.Lpm,
	3215	.Mul,
	3216	.Lpmx,
3335	3217	.Des,
3336		.Xmega,
3337		},
3338		CpuInfo(@This()).create(.Atxmega384c3, "atxmega384c3", &[_]FeatureType {
3339	3218	.Ijmpcall,
3340		.Elpmx,
3341		.Movw,
3342		.Eijmpcall,
3343		.Mul,
3344		.Rmw,
3345		.Sram,
3346	3219	.Break,
3347		.Spm,
	3220	.Xmega,
	3221	}),
	3222	CpuInfo(@This(), FeatureType).create(.Atxmega32a4, "atxmega32a4", &[_]FeatureType {
	3223	.Lpm,
3348	3224	.Elpm,
3349		.Lpmx,
3350		.Spmx,
	3225	.Movw,
	3226	.Elpmx,
	3227	.Spm,
3351	3228	.Avr0,
	3229	.Sram,
3352	3230	.Jmpcall,
	3231	.Eijmpcall,
	3232	.Spmx,
3353	3233	.Addsubiw,
3354		.Lpm,
	3234	.Mul,
	3235	.Lpmx,
3355	3236	.Des,
3356		.Xmegau,
3357		},
3358		CpuInfo(@This()).create(.Atxmega384d3, "atxmega384d3", &[_]FeatureType {
3359	3237	.Ijmpcall,
3360		.Elpmx,
3361		.Movw,
3362		.Eijmpcall,
3363		.Mul,
3364		.Sram,
3365	3238	.Break,
3366		.Spm,
	3239	.Xmega,
	3240	}),
	3241	CpuInfo(@This(), FeatureType).create(.Atxmega32a4u, "atxmega32a4u", &[_]FeatureType {
	3242	.Lpm,
3367	3243	.Elpm,
3368		.Lpmx,
3369		.Spmx,
	3244	.Movw,
	3245	.Elpmx,
	3246	.Spm,
3370	3247	.Avr0,
	3248	.Sram,
3371	3249	.Jmpcall,
	3250	.Eijmpcall,
	3251	.Spmx,
3372	3252	.Addsubiw,
3373		.Lpm,
	3253	.Mul,
	3254	.Lpmx,
	3255	.Rmw,
3374	3256	.Des,
3375		.Xmega,
3376		},
3377		CpuInfo(@This()).create(.Atxmega64a1, "atxmega64a1", &[_]FeatureType {
3378	3257	.Ijmpcall,
3379		.Elpmx,
3380		.Movw,
3381		.Eijmpcall,
3382		.Mul,
3383		.Sram,
3384	3258	.Break,
3385		.Spm,
	3259	.Xmegau,
	3260	}),
	3261	CpuInfo(@This(), FeatureType).create(.Atxmega32c4, "atxmega32c4", &[_]FeatureType {
	3262	.Lpm,
3386	3263	.Elpm,
3387		.Lpmx,
3388		.Spmx,
	3264	.Movw,
	3265	.Elpmx,
	3266	.Spm,
3389	3267	.Avr0,
	3268	.Sram,
3390	3269	.Jmpcall,
3391		.Addsubiw,
3392		.Lpm,
3393		.Des,
3394		.Xmega,
3395		},
3396		CpuInfo(@This()).create(.Atxmega64a1u, "atxmega64a1u", &[_]FeatureType {
3397		.Ijmpcall,
3398		.Elpmx,
3399		.Movw,
3400	3270	.Eijmpcall,
	3271	.Spmx,
	3272	.Addsubiw,
3401	3273	.Mul,
	3274	.Lpmx,
3402	3275	.Rmw,
3403		.Sram,
	3276	.Des,
	3277	.Ijmpcall,
3404	3278	.Break,
3405		.Spm,
	3279	.Xmegau,
	3280	}),
	3281	CpuInfo(@This(), FeatureType).create(.Atxmega32d4, "atxmega32d4", &[_]FeatureType {
	3282	.Lpm,
3406	3283	.Elpm,
3407		.Lpmx,
3408		.Spmx,
	3284	.Movw,
	3285	.Elpmx,
	3286	.Spm,
3409	3287	.Avr0,
	3288	.Sram,
3410	3289	.Jmpcall,
	3290	.Eijmpcall,
	3291	.Spmx,
3411	3292	.Addsubiw,
3412		.Lpm,
	3293	.Mul,
	3294	.Lpmx,
3413	3295	.Des,
3414		.Xmegau,
3415		},
3416		CpuInfo(@This()).create(.Atxmega64a3, "atxmega64a3", &[_]FeatureType {
3417	3296	.Ijmpcall,
3418		.Elpmx,
	3297	.Break,
	3298	.Xmega,
	3299	}),
	3300	CpuInfo(@This(), FeatureType).create(.Atxmega32e5, "atxmega32e5", &[_]FeatureType {
	3301	.Lpm,
	3302	.Elpm,
3419	3303	.Movw,
	3304	.Elpmx,
	3305	.Spm,
	3306	.Avr0,
	3307	.Sram,
	3308	.Jmpcall,
3420	3309	.Eijmpcall,
	3310	.Spmx,
	3311	.Addsubiw,
3421	3312	.Mul,
3422		.Sram,
	3313	.Lpmx,
	3314	.Des,
	3315	.Ijmpcall,
3423	3316	.Break,
3424		.Spm,
	3317	.Xmega,
	3318	}),
	3319	CpuInfo(@This(), FeatureType).create(.Atxmega32x1, "atxmega32x1", &[_]FeatureType {
	3320	.Lpm,
3425	3321	.Elpm,
3426		.Lpmx,
3427		.Spmx,
	3322	.Movw,
	3323	.Elpmx,
	3324	.Spm,
3428	3325	.Avr0,
	3326	.Sram,
3429	3327	.Jmpcall,
	3328	.Eijmpcall,
	3329	.Spmx,
3430	3330	.Addsubiw,
3431		.Lpm,
	3331	.Mul,
	3332	.Lpmx,
3432	3333	.Des,
3433		.Xmega,
3434		},
3435		CpuInfo(@This()).create(.Atxmega64a3u, "atxmega64a3u", &[_]FeatureType {
3436	3334	.Ijmpcall,
3437		.Elpmx,
	3335	.Break,
	3336	.Xmega,
	3337	}),
	3338	CpuInfo(@This(), FeatureType).create(.Atxmega384c3, "atxmega384c3", &[_]FeatureType {
	3339	.Lpm,
	3340	.Elpm,
3438	3341	.Movw,
	3342	.Elpmx,
	3343	.Spm,
	3344	.Avr0,
	3345	.Sram,
	3346	.Jmpcall,
3439	3347	.Eijmpcall,
	3348	.Spmx,
	3349	.Addsubiw,
3440	3350	.Mul,
	3351	.Lpmx,
3441	3352	.Rmw,
3442		.Sram,
	3353	.Des,
	3354	.Ijmpcall,
3443	3355	.Break,
3444		.Spm,
	3356	.Xmegau,
	3357	}),
	3358	CpuInfo(@This(), FeatureType).create(.Atxmega384d3, "atxmega384d3", &[_]FeatureType {
	3359	.Lpm,
3445	3360	.Elpm,
3446		.Lpmx,
3447		.Spmx,
	3361	.Movw,
	3362	.Elpmx,
	3363	.Spm,
3448	3364	.Avr0,
	3365	.Sram,
3449	3366	.Jmpcall,
	3367	.Eijmpcall,
	3368	.Spmx,
3450	3369	.Addsubiw,
3451		.Lpm,
	3370	.Mul,
	3371	.Lpmx,
3452	3372	.Des,
3453		.Xmegau,
3454		},
3455		CpuInfo(@This()).create(.Atxmega64a4u, "atxmega64a4u", &[_]FeatureType {
3456	3373	.Ijmpcall,
3457		.Elpmx,
3458		.Movw,
3459		.Eijmpcall,
3460		.Mul,
3461		.Rmw,
3462		.Sram,
3463	3374	.Break,
3464		.Spm,
	3375	.Xmega,
	3376	}),
	3377	CpuInfo(@This(), FeatureType).create(.Atxmega64a1, "atxmega64a1", &[_]FeatureType {
	3378	.Lpm,
3465	3379	.Elpm,
3466		.Lpmx,
3467		.Spmx,
	3380	.Movw,
	3381	.Elpmx,
	3382	.Spm,
3468	3383	.Avr0,
	3384	.Sram,
3469	3385	.Jmpcall,
	3386	.Eijmpcall,
	3387	.Spmx,
3470	3388	.Addsubiw,
3471		.Lpm,
	3389	.Mul,
	3390	.Lpmx,
3472	3391	.Des,
3473		.Xmegau,
3474		},
3475		CpuInfo(@This()).create(.Atxmega64b1, "atxmega64b1", &[_]FeatureType {
3476	3392	.Ijmpcall,
3477		.Elpmx,
	3393	.Break,
	3394	.Xmega,
	3395	}),
	3396	CpuInfo(@This(), FeatureType).create(.Atxmega64a1u, "atxmega64a1u", &[_]FeatureType {
	3397	.Lpm,
	3398	.Elpm,
3478	3399	.Movw,
	3400	.Elpmx,
	3401	.Spm,
	3402	.Avr0,
	3403	.Sram,
	3404	.Jmpcall,
3479	3405	.Eijmpcall,
	3406	.Spmx,
	3407	.Addsubiw,
3480	3408	.Mul,
	3409	.Lpmx,
3481	3410	.Rmw,
3482		.Sram,
	3411	.Des,
	3412	.Ijmpcall,
3483	3413	.Break,
3484		.Spm,
	3414	.Xmegau,
	3415	}),
	3416	CpuInfo(@This(), FeatureType).create(.Atxmega64a3, "atxmega64a3", &[_]FeatureType {
	3417	.Lpm,
3485	3418	.Elpm,
3486		.Lpmx,
3487		.Spmx,
	3419	.Movw,
	3420	.Elpmx,
	3421	.Spm,
3488	3422	.Avr0,
	3423	.Sram,
3489	3424	.Jmpcall,
	3425	.Eijmpcall,
	3426	.Spmx,
3490	3427	.Addsubiw,
3491		.Lpm,
	3428	.Mul,
	3429	.Lpmx,
3492	3430	.Des,
3493		.Xmegau,
3494		},
3495		CpuInfo(@This()).create(.Atxmega64b3, "atxmega64b3", &[_]FeatureType {
3496	3431	.Ijmpcall,
3497		.Elpmx,
	3432	.Break,
	3433	.Xmega,
	3434	}),
	3435	CpuInfo(@This(), FeatureType).create(.Atxmega64a3u, "atxmega64a3u", &[_]FeatureType {
	3436	.Lpm,
	3437	.Elpm,
3498	3438	.Movw,
	3439	.Elpmx,
	3440	.Spm,
	3441	.Avr0,
	3442	.Sram,
	3443	.Jmpcall,
3499	3444	.Eijmpcall,
	3445	.Spmx,
	3446	.Addsubiw,
3500	3447	.Mul,
	3448	.Lpmx,
3501	3449	.Rmw,
3502		.Sram,
	3450	.Des,
	3451	.Ijmpcall,
3503	3452	.Break,
3504		.Spm,
	3453	.Xmegau,
	3454	}),
	3455	CpuInfo(@This(), FeatureType).create(.Atxmega64a4u, "atxmega64a4u", &[_]FeatureType {
	3456	.Lpm,
3505	3457	.Elpm,
3506		.Lpmx,
3507		.Spmx,
	3458	.Movw,
	3459	.Elpmx,
	3460	.Spm,
3508	3461	.Avr0,
	3462	.Sram,
3509	3463	.Jmpcall,
	3464	.Eijmpcall,
	3465	.Spmx,
3510	3466	.Addsubiw,
3511		.Lpm,
	3467	.Mul,
	3468	.Lpmx,
	3469	.Rmw,
3512	3470	.Des,
3513		.Xmegau,
3514		},
3515		CpuInfo(@This()).create(.Atxmega64c3, "atxmega64c3", &[_]FeatureType {
3516	3471	.Ijmpcall,
3517		.Elpmx,
	3472	.Break,
	3473	.Xmegau,
	3474	}),
	3475	CpuInfo(@This(), FeatureType).create(.Atxmega64b1, "atxmega64b1", &[_]FeatureType {
	3476	.Lpm,
	3477	.Elpm,
3518	3478	.Movw,
	3479	.Elpmx,
	3480	.Spm,
	3481	.Avr0,
	3482	.Sram,
	3483	.Jmpcall,
3519	3484	.Eijmpcall,
	3485	.Spmx,
	3486	.Addsubiw,
3520	3487	.Mul,
	3488	.Lpmx,
3521	3489	.Rmw,
3522		.Sram,
	3490	.Des,
	3491	.Ijmpcall,
3523	3492	.Break,
3524		.Spm,
	3493	.Xmegau,
	3494	}),
	3495	CpuInfo(@This(), FeatureType).create(.Atxmega64b3, "atxmega64b3", &[_]FeatureType {
	3496	.Lpm,
3525	3497	.Elpm,
3526		.Lpmx,
3527		.Spmx,
	3498	.Movw,
	3499	.Elpmx,
	3500	.Spm,
3528	3501	.Avr0,
	3502	.Sram,
3529	3503	.Jmpcall,
	3504	.Eijmpcall,
	3505	.Spmx,
3530	3506	.Addsubiw,
3531		.Lpm,
	3507	.Mul,
	3508	.Lpmx,
	3509	.Rmw,
3532	3510	.Des,
3533		.Xmegau,
3534		},
3535		CpuInfo(@This()).create(.Atxmega64d3, "atxmega64d3", &[_]FeatureType {
3536	3511	.Ijmpcall,
3537		.Elpmx,
3538		.Movw,
3539		.Eijmpcall,
3540		.Mul,
3541		.Sram,
3542	3512	.Break,
3543		.Spm,
	3513	.Xmegau,
	3514	}),
	3515	CpuInfo(@This(), FeatureType).create(.Atxmega64c3, "atxmega64c3", &[_]FeatureType {
	3516	.Lpm,
3544	3517	.Elpm,
3545		.Lpmx,
3546		.Spmx,
	3518	.Movw,
	3519	.Elpmx,
	3520	.Spm,
3547	3521	.Avr0,
	3522	.Sram,
3548	3523	.Jmpcall,
	3524	.Eijmpcall,
	3525	.Spmx,
3549	3526	.Addsubiw,
3550		.Lpm,
	3527	.Mul,
	3528	.Lpmx,
	3529	.Rmw,
3551	3530	.Des,
3552		.Xmega,
3553		},
3554		CpuInfo(@This()).create(.Atxmega64d4, "atxmega64d4", &[_]FeatureType {
3555	3531	.Ijmpcall,
3556		.Elpmx,
3557		.Movw,
3558		.Eijmpcall,
3559		.Mul,
3560		.Sram,
3561	3532	.Break,
3562		.Spm,
	3533	.Xmegau,
	3534	}),
	3535	CpuInfo(@This(), FeatureType).create(.Atxmega64d3, "atxmega64d3", &[_]FeatureType {
	3536	.Lpm,
3563	3537	.Elpm,
3564		.Lpmx,
3565		.Spmx,
	3538	.Movw,
	3539	.Elpmx,
	3540	.Spm,
3566	3541	.Avr0,
	3542	.Sram,
3567	3543	.Jmpcall,
	3544	.Eijmpcall,
	3545	.Spmx,
3568	3546	.Addsubiw,
3569		.Lpm,
	3547	.Mul,
	3548	.Lpmx,
3570	3549	.Des,
3571		.Xmega,
3572		},
3573		CpuInfo(@This()).create(.Atxmega8e5, "atxmega8e5", &[_]FeatureType {
3574	3550	.Ijmpcall,
3575		.Elpmx,
	3551	.Break,
	3552	.Xmega,
	3553	}),
	3554	CpuInfo(@This(), FeatureType).create(.Atxmega64d4, "atxmega64d4", &[_]FeatureType {
	3555	.Lpm,
	3556	.Elpm,
3576	3557	.Movw,
	3558	.Elpmx,
	3559	.Spm,
	3560	.Avr0,
	3561	.Sram,
	3562	.Jmpcall,
3577	3563	.Eijmpcall,
	3564	.Spmx,
	3565	.Addsubiw,
3578	3566	.Mul,
3579		.Sram,
	3567	.Lpmx,
	3568	.Des,
	3569	.Ijmpcall,
3580	3570	.Break,
3581		.Spm,
	3571	.Xmega,
	3572	}),
	3573	CpuInfo(@This(), FeatureType).create(.Atxmega8e5, "atxmega8e5", &[_]FeatureType {
	3574	.Lpm,
3582	3575	.Elpm,
3583		.Lpmx,
3584		.Spmx,
	3576	.Movw,
	3577	.Elpmx,
	3578	.Spm,
3585	3579	.Avr0,
	3580	.Sram,
3586	3581	.Jmpcall,
	3582	.Eijmpcall,
	3583	.Spmx,
3587	3584	.Addsubiw,
3588		.Lpm,
	3585	.Mul,
	3586	.Lpmx,
3589	3587	.Des,
	3588	.Ijmpcall,
	3589	.Break,
3590	3590	.Xmega,
3591		},
3592		CpuInfo(@This()).create(.Avr1, "avr1", &[_]FeatureType {
3593		.Lpm,
	3591	}),
	3592	CpuInfo(@This(), FeatureType).create(.Avr1, "avr1", &[_]FeatureType {
3594	3593	.Avr0,
	3594	.Lpm,
3595	3595	.Avr1,
3596		},
3597		CpuInfo(@This()).create(.Avr2, "avr2", &[_]FeatureType {
3598		.Ijmpcall,
3599		.Sram,
	3596	}),
	3597	CpuInfo(@This(), FeatureType).create(.Avr2, "avr2", &[_]FeatureType {
	3598	.Lpm,
3600	3599	.Avr0,
	3600	.Sram,
3601	3601	.Addsubiw,
3602		.Lpm,
3603		.Avr2,
3604		},
3605		CpuInfo(@This()).create(.Avr25, "avr25", &[_]FeatureType {
3606	3602	.Ijmpcall,
	3603	.Avr2,
	3604	}),
	3605	CpuInfo(@This(), FeatureType).create(.Avr25, "avr25", &[_]FeatureType {
	3606	.Lpm,
3607	3607	.Movw,
3608		.Sram,
3609		.Break,
3610	3608	.Spm,
3611		.Lpmx,
3612	3609	.Avr0,
	3610	.Sram,
3613	3611	.Addsubiw,
3614		.Lpm,
3615		.Avr25,
3616		},
3617		CpuInfo(@This()).create(.Avr3, "avr3", &[_]FeatureType {
	3612	.Lpmx,
3618	3613	.Ijmpcall,
3619		.Sram,
	3614	.Break,
	3615	.Avr25,
	3616	}),
	3617	CpuInfo(@This(), FeatureType).create(.Avr3, "avr3", &[_]FeatureType {
	3618	.Lpm,
3620	3619	.Avr0,
	3620	.Sram,
3621	3621	.Jmpcall,
3622	3622	.Addsubiw,
3623		.Lpm,
3624		.Avr3,
3625		},
3626		CpuInfo(@This()).create(.Avr31, "avr31", &[_]FeatureType {
3627	3623	.Ijmpcall,
3628		.Sram,
	3624	.Avr3,
	3625	}),
	3626	CpuInfo(@This(), FeatureType).create(.Avr31, "avr31", &[_]FeatureType {
	3627	.Lpm,
3629	3628	.Elpm,
3630	3629	.Avr0,
	3630	.Sram,
3631	3631	.Jmpcall,
3632	3632	.Addsubiw,
3633		.Lpm,
3634		.Avr31,
3635		},
3636		CpuInfo(@This()).create(.Avr35, "avr35", &[_]FeatureType {
3637	3633	.Ijmpcall,
	3634	.Avr31,
	3635	}),
	3636	CpuInfo(@This(), FeatureType).create(.Avr35, "avr35", &[_]FeatureType {
	3637	.Lpm,
3638	3638	.Movw,
3639		.Sram,
3640		.Break,
3641	3639	.Spm,
3642		.Lpmx,
3643	3640	.Avr0,
	3641	.Sram,
3644	3642	.Jmpcall,
3645	3643	.Addsubiw,
3646		.Lpm,
3647		.Avr35,
3648		},
3649		CpuInfo(@This()).create(.Avr4, "avr4", &[_]FeatureType {
	3644	.Lpmx,
3650	3645	.Ijmpcall,
3651		.Movw,
3652		.Mul,
3653		.Sram,
3654	3646	.Break,
	3647	.Avr35,
	3648	}),
	3649	CpuInfo(@This(), FeatureType).create(.Avr4, "avr4", &[_]FeatureType {
	3650	.Lpm,
	3651	.Movw,
3655	3652	.Spm,
3656		.Lpmx,
3657	3653	.Avr0,
	3654	.Sram,
3658	3655	.Addsubiw,
3659		.Lpm,
3660		.Avr4,
3661		},
3662		CpuInfo(@This()).create(.Avr5, "avr5", &[_]FeatureType {
3663		.Ijmpcall,
3664		.Movw,
3665	3656	.Mul,
3666		.Sram,
	3657	.Lpmx,
	3658	.Ijmpcall,
3667	3659	.Break,
	3660	.Avr4,
	3661	}),
	3662	CpuInfo(@This(), FeatureType).create(.Avr5, "avr5", &[_]FeatureType {
	3663	.Lpm,
	3664	.Movw,
3668	3665	.Spm,
3669		.Lpmx,
3670	3666	.Avr0,
	3667	.Sram,
3671	3668	.Jmpcall,
3672	3669	.Addsubiw,
3673		.Lpm,
3674		.Avr5,
3675		},
3676		CpuInfo(@This()).create(.Avr51, "avr51", &[_]FeatureType {
3677		.Ijmpcall,
3678		.Elpmx,
3679		.Movw,
3680	3670	.Mul,
3681		.Sram,
	3671	.Lpmx,
	3672	.Ijmpcall,
3682	3673	.Break,
3683		.Spm,
	3674	.Avr5,
	3675	}),
	3676	CpuInfo(@This(), FeatureType).create(.Avr51, "avr51", &[_]FeatureType {
	3677	.Lpm,
3684	3678	.Elpm,
3685		.Lpmx,
	3679	.Movw,
	3680	.Elpmx,
	3681	.Spm,
3686	3682	.Avr0,
	3683	.Sram,
3687	3684	.Jmpcall,
3688	3685	.Addsubiw,
3689		.Lpm,
3690		.Avr51,
3691		},
3692		CpuInfo(@This()).create(.Avr6, "avr6", &[_]FeatureType {
3693		.Ijmpcall,
3694		.Elpmx,
3695		.Movw,
3696	3686	.Mul,
3697		.Sram,
	3687	.Lpmx,
	3688	.Ijmpcall,
3698	3689	.Break,
3699		.Spm,
	3690	.Avr51,
	3691	}),
	3692	CpuInfo(@This(), FeatureType).create(.Avr6, "avr6", &[_]FeatureType {
	3693	.Lpm,
3700	3694	.Elpm,
3701		.Lpmx,
	3695	.Movw,
	3696	.Elpmx,
	3697	.Spm,
3702	3698	.Avr0,
	3699	.Sram,
3703	3700	.Jmpcall,
3704	3701	.Addsubiw,
3705		.Lpm,
3706		.Avr6,
3707		},
3708		CpuInfo(@This()).create(.Avrtiny, "avrtiny", &[_]FeatureType {
	3702	.Mul,
	3703	.Lpmx,
	3704	.Ijmpcall,
3709	3705	.Break,
3710		.Tinyencoding,
	3706	.Avr6,
	3707	}),
	3708	CpuInfo(@This(), FeatureType).create(.Avrtiny, "avrtiny", &[_]FeatureType {
3711	3709	.Avr0,
3712	3710	.Sram,
	3711	.Break,
	3712	.Tinyencoding,
3713	3713	.Avrtiny,
3714		},
3715		CpuInfo(@This()).create(.Avrxmega1, "avrxmega1", &[_]FeatureType {
3716		.Ijmpcall,
3717		.Elpmx,
	3714	}),
	3715	CpuInfo(@This(), FeatureType).create(.Avrxmega1, "avrxmega1", &[_]FeatureType {
	3716	.Lpm,
	3717	.Elpm,
3718	3718	.Movw,
3719		.Eijmpcall,
3720		.Mul,
3721		.Sram,
3722		.Break,
	3719	.Elpmx,
3723	3720	.Spm,
3724		.Elpm,
3725		.Lpmx,
3726		.Spmx,
3727	3721	.Avr0,
	3722	.Sram,
3728	3723	.Jmpcall,
	3724	.Eijmpcall,
	3725	.Spmx,
3729	3726	.Addsubiw,
3730		.Lpm,
	3727	.Mul,
	3728	.Lpmx,
3731	3729	.Des,
3732		.Xmega,
3733		},
3734		CpuInfo(@This()).create(.Avrxmega2, "avrxmega2", &[_]FeatureType {
3735	3730	.Ijmpcall,
3736		.Elpmx,
3737		.Movw,
3738		.Eijmpcall,
3739		.Mul,
3740		.Sram,
3741	3731	.Break,
3742		.Spm,
	3732	.Xmega,
	3733	}),
	3734	CpuInfo(@This(), FeatureType).create(.Avrxmega2, "avrxmega2", &[_]FeatureType {
	3735	.Lpm,
3743	3736	.Elpm,
3744		.Lpmx,
3745		.Spmx,
	3737	.Movw,
	3738	.Elpmx,
	3739	.Spm,
3746	3740	.Avr0,
	3741	.Sram,
3747	3742	.Jmpcall,
	3743	.Eijmpcall,
	3744	.Spmx,
3748	3745	.Addsubiw,
3749		.Lpm,
	3746	.Mul,
	3747	.Lpmx,
3750	3748	.Des,
3751		.Xmega,
3752		},
3753		CpuInfo(@This()).create(.Avrxmega3, "avrxmega3", &[_]FeatureType {
3754	3749	.Ijmpcall,
3755		.Elpmx,
3756		.Movw,
3757		.Eijmpcall,
3758		.Mul,
3759		.Sram,
3760	3750	.Break,
3761		.Spm,
	3751	.Xmega,
	3752	}),
	3753	CpuInfo(@This(), FeatureType).create(.Avrxmega3, "avrxmega3", &[_]FeatureType {
	3754	.Lpm,
3762	3755	.Elpm,
3763		.Lpmx,
3764		.Spmx,
	3756	.Movw,
	3757	.Elpmx,
	3758	.Spm,
3765	3759	.Avr0,
	3760	.Sram,
3766	3761	.Jmpcall,
	3762	.Eijmpcall,
	3763	.Spmx,
3767	3764	.Addsubiw,
3768		.Lpm,
	3765	.Mul,
	3766	.Lpmx,
3769	3767	.Des,
3770		.Xmega,
3771		},
3772		CpuInfo(@This()).create(.Avrxmega4, "avrxmega4", &[_]FeatureType {
3773	3768	.Ijmpcall,
3774		.Elpmx,
3775		.Movw,
3776		.Eijmpcall,
3777		.Mul,
3778		.Sram,
3779	3769	.Break,
3780		.Spm,
	3770	.Xmega,
	3771	}),
	3772	CpuInfo(@This(), FeatureType).create(.Avrxmega4, "avrxmega4", &[_]FeatureType {
	3773	.Lpm,
3781	3774	.Elpm,
3782		.Lpmx,
3783		.Spmx,
	3775	.Movw,
	3776	.Elpmx,
	3777	.Spm,
3784	3778	.Avr0,
	3779	.Sram,
3785	3780	.Jmpcall,
	3781	.Eijmpcall,
	3782	.Spmx,
3786	3783	.Addsubiw,
3787		.Lpm,
	3784	.Mul,
	3785	.Lpmx,
3788	3786	.Des,
3789		.Xmega,
3790		},
3791		CpuInfo(@This()).create(.Avrxmega5, "avrxmega5", &[_]FeatureType {
3792	3787	.Ijmpcall,
3793		.Elpmx,
3794		.Movw,
3795		.Eijmpcall,
3796		.Mul,
3797		.Sram,
3798	3788	.Break,
3799		.Spm,
	3789	.Xmega,
	3790	}),
	3791	CpuInfo(@This(), FeatureType).create(.Avrxmega5, "avrxmega5", &[_]FeatureType {
	3792	.Lpm,
3800	3793	.Elpm,
3801		.Lpmx,
3802		.Spmx,
	3794	.Movw,
	3795	.Elpmx,
	3796	.Spm,
3803	3797	.Avr0,
	3798	.Sram,
3804	3799	.Jmpcall,
	3800	.Eijmpcall,
	3801	.Spmx,
3805	3802	.Addsubiw,
3806		.Lpm,
	3803	.Mul,
	3804	.Lpmx,
3807	3805	.Des,
3808		.Xmega,
3809		},
3810		CpuInfo(@This()).create(.Avrxmega6, "avrxmega6", &[_]FeatureType {
3811	3806	.Ijmpcall,
3812		.Elpmx,
3813		.Movw,
3814		.Eijmpcall,
3815		.Mul,
3816		.Sram,
3817	3807	.Break,
3818		.Spm,
	3808	.Xmega,
	3809	}),
	3810	CpuInfo(@This(), FeatureType).create(.Avrxmega6, "avrxmega6", &[_]FeatureType {
	3811	.Lpm,
3819	3812	.Elpm,
3820		.Lpmx,
3821		.Spmx,
	3813	.Movw,
	3814	.Elpmx,
	3815	.Spm,
3822	3816	.Avr0,
	3817	.Sram,
3823	3818	.Jmpcall,
	3819	.Eijmpcall,
	3820	.Spmx,
3824	3821	.Addsubiw,
3825		.Lpm,
	3822	.Mul,
	3823	.Lpmx,
3826	3824	.Des,
3827		.Xmega,
3828		},
3829		CpuInfo(@This()).create(.Avrxmega7, "avrxmega7", &[_]FeatureType {
3830	3825	.Ijmpcall,
3831		.Elpmx,
3832		.Movw,
3833		.Eijmpcall,
3834		.Mul,
3835		.Sram,
3836	3826	.Break,
3837		.Spm,
	3827	.Xmega,
	3828	}),
	3829	CpuInfo(@This(), FeatureType).create(.Avrxmega7, "avrxmega7", &[_]FeatureType {
	3830	.Lpm,
3838	3831	.Elpm,
3839		.Lpmx,
3840		.Spmx,
	3832	.Movw,
	3833	.Elpmx,
	3834	.Spm,
3841	3835	.Avr0,
	3836	.Sram,
3842	3837	.Jmpcall,
	3838	.Eijmpcall,
	3839	.Spmx,
3843	3840	.Addsubiw,
3844		.Lpm,
	3841	.Mul,
	3842	.Lpmx,
3845	3843	.Des,
3846		.Xmega,
3847		},
3848		CpuInfo(@This()).create(.M3000, "m3000", &[_]FeatureType {
3849	3844	.Ijmpcall,
3850		.Movw,
3851		.Mul,
3852		.Sram,
3853	3845	.Break,
	3846	.Xmega,
	3847	}),
	3848	CpuInfo(@This(), FeatureType).create(.M3000, "m3000", &[_]FeatureType {
	3849	.Lpm,
	3850	.Movw,
3854	3851	.Spm,
3855		.Lpmx,
3856	3852	.Avr0,
	3853	.Sram,
3857	3854	.Jmpcall,
3858	3855	.Addsubiw,
3859		.Lpm,
	3856	.Mul,
	3857	.Lpmx,
	3858	.Ijmpcall,
	3859	.Break,
3860	3860	.Avr5,
3861		},
	3861	}),
3862	3862	};
3863	3863	};

lib/std/target/cpu/BpfCpu.zig+14-14

...	...	@@ -8,22 +8,22 @@ pub const BpfCpu = enum {
8	8	V2,
9	9	V3,
10	10
11		pub fn getInfo(self: @This()) CpuInfo {
	11	const FeatureType = feature.BpfFeature;
	12
	13	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
12	14	return cpu_infos[@enumToInt(self)];
13	15	}
14	16
15		pub const FeatureType = feature.BpfFeature;
16
17		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
18		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
19		},
20		CpuInfo(@This()).create(.Probe, "probe", &[_]FeatureType {
21		},
22		CpuInfo(@This()).create(.V1, "v1", &[_]FeatureType {
23		},
24		CpuInfo(@This()).create(.V2, "v2", &[_]FeatureType {
25		},
26		CpuInfo(@This()).create(.V3, "v3", &[_]FeatureType {
27		},
	17	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	18	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
	19	}),
	20	CpuInfo(@This(), FeatureType).create(.Probe, "probe", &[_]FeatureType {
	21	}),
	22	CpuInfo(@This(), FeatureType).create(.V1, "v1", &[_]FeatureType {
	23	}),
	24	CpuInfo(@This(), FeatureType).create(.V2, "v2", &[_]FeatureType {
	25	}),
	26	CpuInfo(@This(), FeatureType).create(.V3, "v3", &[_]FeatureType {
	27	}),
28	28	};
29	29	};

lib/std/target/cpu/HexagonCpu.zig+18-18

...	...	@@ -10,14 +10,14 @@ pub const HexagonCpu = enum {
10	10	Hexagonv65,
11	11	Hexagonv66,
12	12
13		pub fn getInfo(self: @This()) CpuInfo {
	13	const FeatureType = feature.HexagonFeature;
	14
	15	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
14	16	return cpu_infos[@enumToInt(self)];
15	17	}
16	18
17		pub const FeatureType = feature.HexagonFeature;
18
19		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
20		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
	19	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	20	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
21	21	.V5,
22	22	.V55,
23	23	.V60,
...	...	@@ -27,8 +27,8 @@ pub const HexagonCpu = enum {
27	27	.Nvj,
28	28	.Nvs,
29	29	.SmallData,
30		},
31		CpuInfo(@This()).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
	30	}),
	31	CpuInfo(@This(), FeatureType).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
32	32	.V5,
33	33	.Duplex,
34	34	.Memops,
...	...	@@ -36,8 +36,8 @@ pub const HexagonCpu = enum {
36	36	.Nvj,
37	37	.Nvs,
38	38	.SmallData,
39		},
40		CpuInfo(@This()).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
	39	}),
	40	CpuInfo(@This(), FeatureType).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
41	41	.V5,
42	42	.V55,
43	43	.Duplex,
...	...	@@ -46,8 +46,8 @@ pub const HexagonCpu = enum {
46	46	.Nvj,
47	47	.Nvs,
48	48	.SmallData,
49		},
50		CpuInfo(@This()).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
	49	}),
	50	CpuInfo(@This(), FeatureType).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
51	51	.V5,
52	52	.V55,
53	53	.V60,
...	...	@@ -57,8 +57,8 @@ pub const HexagonCpu = enum {
57	57	.Nvj,
58	58	.Nvs,
59	59	.SmallData,
60		},
61		CpuInfo(@This()).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
	60	}),
	61	CpuInfo(@This(), FeatureType).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
62	62	.V5,
63	63	.V55,
64	64	.V60,
...	...	@@ -69,8 +69,8 @@ pub const HexagonCpu = enum {
69	69	.Nvj,
70	70	.Nvs,
71	71	.SmallData,
72		},
73		CpuInfo(@This()).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
	72	}),
	73	CpuInfo(@This(), FeatureType).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
74	74	.V5,
75	75	.V55,
76	76	.V60,
...	...	@@ -83,8 +83,8 @@ pub const HexagonCpu = enum {
83	83	.Nvj,
84	84	.Nvs,
85	85	.SmallData,
86		},
87		CpuInfo(@This()).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
	86	}),
	87	CpuInfo(@This(), FeatureType).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
88	88	.V5,
89	89	.V55,
90	90	.V60,
...	...	@@ -98,6 +98,6 @@ pub const HexagonCpu = enum {
98	98	.Nvj,
99	99	.Nvs,
100	100	.SmallData,
101		},
	101	}),
102	102	};
103	103	};

lib/std/target/cpu/MipsCpu.zig+110-110

...	...	@@ -20,171 +20,171 @@ pub const MipsCpu = enum {
20	20	Octeon,
21	21	P5600,
22	22
23		pub fn getInfo(self: @This()) CpuInfo {
	23	const FeatureType = feature.MipsFeature;
	24
	25	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
24	26	return cpu_infos[@enumToInt(self)];
25	27	}
26	28
27		pub const FeatureType = feature.MipsFeature;
28
29		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
30		CpuInfo(@This()).create(.Mips1, "mips1", &[_]FeatureType {
	29	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	30	CpuInfo(@This(), FeatureType).create(.Mips1, "mips1", &[_]FeatureType {
31	31	.Mips1,
32		},
33		CpuInfo(@This()).create(.Mips2, "mips2", &[_]FeatureType {
	32	}),
	33	CpuInfo(@This(), FeatureType).create(.Mips2, "mips2", &[_]FeatureType {
34	34	.Mips1,
35	35	.Mips2,
36		},
37		CpuInfo(@This()).create(.Mips3, "mips3", &[_]FeatureType {
38		.Mips3_32,
39		.Fp64,
	36	}),
	37	CpuInfo(@This(), FeatureType).create(.Mips3, "mips3", &[_]FeatureType {
40	38	.Mips3_32r2,
41		.Mips1,
	39	.Fp64,
42	40	.Gp64,
43		.Mips3,
44		},
45		CpuInfo(@This()).create(.Mips32, "mips32", &[_]FeatureType {
	41	.Mips1,
46	42	.Mips3_32,
	43	.Mips3,
	44	}),
	45	CpuInfo(@This(), FeatureType).create(.Mips32, "mips32", &[_]FeatureType {
47	46	.Mips4_32,
48	47	.Mips1,
49		.Mips32,
50		},
51		CpuInfo(@This()).create(.Mips32r2, "mips32r2", &[_]FeatureType {
52	48	.Mips3_32,
	49	.Mips32,
	50	}),
	51	CpuInfo(@This(), FeatureType).create(.Mips32r2, "mips32r2", &[_]FeatureType {
	52	.Mips5_32r2,
53	53	.Mips4_32r2,
54	54	.Mips3_32r2,
55		.Mips1,
56	55	.Mips4_32,
57		.Mips5_32r2,
58		.Mips32r2,
59		},
60		CpuInfo(@This()).create(.Mips32r3, "mips32r3", &[_]FeatureType {
	56	.Mips1,
61	57	.Mips3_32,
62		.Mips4_32r2,
	58	.Mips32r2,
	59	}),
	60	CpuInfo(@This(), FeatureType).create(.Mips32r3, "mips32r3", &[_]FeatureType {
	61	.Mips5_32r2,
63	62	.Mips3_32r2,
64		.Mips1,
	63	.Mips4_32r2,
65	64	.Mips4_32,
66		.Mips5_32r2,
67		.Mips32r3,
68		},
69		CpuInfo(@This()).create(.Mips32r5, "mips32r5", &[_]FeatureType {
	65	.Mips1,
70	66	.Mips3_32,
71		.Mips4_32r2,
	67	.Mips32r3,
	68	}),
	69	CpuInfo(@This(), FeatureType).create(.Mips32r5, "mips32r5", &[_]FeatureType {
	70	.Mips5_32r2,
72	71	.Mips3_32r2,
73		.Mips1,
	72	.Mips4_32r2,
74	73	.Mips4_32,
75		.Mips5_32r2,
76		.Mips32r5,
77		},
78		CpuInfo(@This()).create(.Mips32r6, "mips32r6", &[_]FeatureType {
	74	.Mips1,
79	75	.Mips3_32,
80		.Fp64,
	76	.Mips32r5,
	77	}),
	78	CpuInfo(@This(), FeatureType).create(.Mips32r6, "mips32r6", &[_]FeatureType {
	79	.Mips5_32r2,
	80	.Mips3_32r2,
81	81	.Mips4_32r2,
82	82	.Abs2008,
83		.Mips3_32r2,
84		.Mips1,
85		.Mips4_32,
86	83	.Nan2008,
87		.Mips5_32r2,
88		.Mips32r6,
89		},
90		CpuInfo(@This()).create(.Mips4, "mips4", &[_]FeatureType {
91		.Mips3_32,
92	84	.Fp64,
93		.Mips4_32r2,
94		.Mips3_32r2,
95		.Mips1,
96	85	.Mips4_32,
97		.Gp64,
98		.Mips4,
99		},
100		CpuInfo(@This()).create(.Mips5, "mips5", &[_]FeatureType {
	86	.Mips1,
101	87	.Mips3_32,
102		.Fp64,
103		.Mips4_32r2,
	88	.Mips32r6,
	89	}),
	90	CpuInfo(@This(), FeatureType).create(.Mips4, "mips4", &[_]FeatureType {
104	91	.Mips3_32r2,
105		.Mips1,
106		.Mips4_32,
	92	.Mips4_32r2,
	93	.Fp64,
107	94	.Gp64,
108		.Mips5_32r2,
109		.Mips5,
110		},
111		CpuInfo(@This()).create(.Mips64, "mips64", &[_]FeatureType {
	95	.Mips4_32,
	96	.Mips1,
112	97	.Mips3_32,
113		.Fp64,
	98	.Mips4,
	99	}),
	100	CpuInfo(@This(), FeatureType).create(.Mips5, "mips5", &[_]FeatureType {
	101	.Mips5_32r2,
114	102	.Mips4_32r2,
115	103	.Mips3_32r2,
116		.Mips1,
117		.Mips4_32,
118	104	.Gp64,
119		.Mips5_32r2,
120		.Mips64,
121		},
122		CpuInfo(@This()).create(.Mips64r2, "mips64r2", &[_]FeatureType {
123		.Mips3_32,
124	105	.Fp64,
125		.Mips4_32r2,
126		.Mips3_32r2,
127		.Mips1,
128	106	.Mips4_32,
129		.Gp64,
130		.Mips5_32r2,
131		.Mips64r2,
132		},
133		CpuInfo(@This()).create(.Mips64r3, "mips64r3", &[_]FeatureType {
	107	.Mips1,
134	108	.Mips3_32,
135		.Fp64,
136		.Mips4_32r2,
	109	.Mips5,
	110	}),
	111	CpuInfo(@This(), FeatureType).create(.Mips64, "mips64", &[_]FeatureType {
	112	.Mips5_32r2,
137	113	.Mips3_32r2,
138		.Mips1,
139		.Mips4_32,
	114	.Mips4_32r2,
140	115	.Gp64,
141		.Mips5_32r2,
142		.Mips64r3,
143		},
144		CpuInfo(@This()).create(.Mips64r5, "mips64r5", &[_]FeatureType {
145		.Mips3_32,
146	116	.Fp64,
147		.Mips4_32r2,
148		.Mips3_32r2,
149		.Mips1,
150	117	.Mips4_32,
151		.Gp64,
152		.Mips5_32r2,
153		.Mips64r5,
154		},
155		CpuInfo(@This()).create(.Mips64r6, "mips64r6", &[_]FeatureType {
	118	.Mips1,
156	119	.Mips3_32,
157		.Fp64,
	120	.Mips64,
	121	}),
	122	CpuInfo(@This(), FeatureType).create(.Mips64r2, "mips64r2", &[_]FeatureType {
	123	.Mips5_32r2,
	124	.Mips3_32r2,
158	125	.Mips4_32r2,
159		.Abs2008,
	126	.Gp64,
	127	.Fp64,
	128	.Mips4_32,
	129	.Mips1,
	130	.Mips3_32,
	131	.Mips64r2,
	132	}),
	133	CpuInfo(@This(), FeatureType).create(.Mips64r3, "mips64r3", &[_]FeatureType {
	134	.Mips5_32r2,
160	135	.Mips3_32r2,
	136	.Mips4_32r2,
	137	.Gp64,
	138	.Fp64,
	139	.Mips4_32,
161	140	.Mips1,
	141	.Mips3_32,
	142	.Mips64r3,
	143	}),
	144	CpuInfo(@This(), FeatureType).create(.Mips64r5, "mips64r5", &[_]FeatureType {
	145	.Mips5_32r2,
	146	.Mips3_32r2,
	147	.Mips4_32r2,
	148	.Gp64,
	149	.Fp64,
162	150	.Mips4_32,
	151	.Mips1,
	152	.Mips3_32,
	153	.Mips64r5,
	154	}),
	155	CpuInfo(@This(), FeatureType).create(.Mips64r6, "mips64r6", &[_]FeatureType {
	156	.Mips5_32r2,
	157	.Mips3_32r2,
163	158	.Nan2008,
	159	.Abs2008,
	160	.Mips4_32r2,
	161	.Fp64,
164	162	.Gp64,
165		.Mips5_32r2,
166		.Mips64r6,
167		},
168		CpuInfo(@This()).create(.Octeon, "octeon", &[_]FeatureType {
	163	.Mips4_32,
	164	.Mips1,
169	165	.Mips3_32,
170		.Fp64,
171		.Mips4_32r2,
	166	.Mips64r6,
	167	}),
	168	CpuInfo(@This(), FeatureType).create(.Octeon, "octeon", &[_]FeatureType {
	169	.Mips5_32r2,
172	170	.Mips3_32r2,
173		.Mips1,
174		.Mips4_32,
	171	.Mips4_32r2,
175	172	.Gp64,
176		.Mips5_32r2,
	173	.Fp64,
	174	.Mips4_32,
	175	.Mips1,
	176	.Mips3_32,
177	177	.Cnmips,
178	178	.Mips64r2,
179		},
180		CpuInfo(@This()).create(.P5600, "p5600", &[_]FeatureType {
181		.Mips3_32,
182		.Mips4_32r2,
	179	}),
	180	CpuInfo(@This(), FeatureType).create(.P5600, "p5600", &[_]FeatureType {
	181	.Mips5_32r2,
183	182	.Mips3_32r2,
184		.Mips1,
	183	.Mips4_32r2,
185	184	.Mips4_32,
186		.Mips5_32r2,
	185	.Mips1,
	186	.Mips3_32,
187	187	.P5600,
188		},
	188	}),
189	189	};
190	190	};

lib/std/target/cpu/Msp430Cpu.zig+10-10

...	...	@@ -6,19 +6,19 @@ pub const Msp430Cpu = enum {
6	6	Msp430,
7	7	Msp430x,
8	8
9		pub fn getInfo(self: @This()) CpuInfo {
	9	const FeatureType = feature.Msp430Feature;
	10
	11	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
10	12	return cpu_infos[@enumToInt(self)];
11	13	}
12	14
13		pub const FeatureType = feature.Msp430Feature;
14
15		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
16		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
17		},
18		CpuInfo(@This()).create(.Msp430, "msp430", &[_]FeatureType {
19		},
20		CpuInfo(@This()).create(.Msp430x, "msp430x", &[_]FeatureType {
	15	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	16	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
	17	}),
	18	CpuInfo(@This(), FeatureType).create(.Msp430, "msp430", &[_]FeatureType {
	19	}),
	20	CpuInfo(@This(), FeatureType).create(.Msp430x, "msp430x", &[_]FeatureType {
21	21	.Ext,
22		},
	22	}),
23	23	};
24	24	};

lib/std/target/cpu/NvptxCpu.zig+34-34

...	...	@@ -18,68 +18,68 @@ pub const NvptxCpu = enum {
18	18	Sm_72,
19	19	Sm_75,
20	20
21		pub fn getInfo(self: @This()) CpuInfo {
	21	const FeatureType = feature.NvptxFeature;
	22
	23	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
22	24	return cpu_infos[@enumToInt(self)];
23	25	}
24	26
25		pub const FeatureType = feature.NvptxFeature;
26
27		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
28		CpuInfo(@This()).create(.Sm_20, "sm_20", &[_]FeatureType {
	27	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	28	CpuInfo(@This(), FeatureType).create(.Sm_20, "sm_20", &[_]FeatureType {
29	29	.Sm_20,
30		},
31		CpuInfo(@This()).create(.Sm_21, "sm_21", &[_]FeatureType {
	30	}),
	31	CpuInfo(@This(), FeatureType).create(.Sm_21, "sm_21", &[_]FeatureType {
32	32	.Sm_21,
33		},
34		CpuInfo(@This()).create(.Sm_30, "sm_30", &[_]FeatureType {
	33	}),
	34	CpuInfo(@This(), FeatureType).create(.Sm_30, "sm_30", &[_]FeatureType {
35	35	.Sm_30,
36		},
37		CpuInfo(@This()).create(.Sm_32, "sm_32", &[_]FeatureType {
	36	}),
	37	CpuInfo(@This(), FeatureType).create(.Sm_32, "sm_32", &[_]FeatureType {
38	38	.Ptx40,
39	39	.Sm_32,
40		},
41		CpuInfo(@This()).create(.Sm_35, "sm_35", &[_]FeatureType {
	40	}),
	41	CpuInfo(@This(), FeatureType).create(.Sm_35, "sm_35", &[_]FeatureType {
42	42	.Sm_35,
43		},
44		CpuInfo(@This()).create(.Sm_37, "sm_37", &[_]FeatureType {
	43	}),
	44	CpuInfo(@This(), FeatureType).create(.Sm_37, "sm_37", &[_]FeatureType {
45	45	.Ptx41,
46	46	.Sm_37,
47		},
48		CpuInfo(@This()).create(.Sm_50, "sm_50", &[_]FeatureType {
	47	}),
	48	CpuInfo(@This(), FeatureType).create(.Sm_50, "sm_50", &[_]FeatureType {
49	49	.Ptx40,
50	50	.Sm_50,
51		},
52		CpuInfo(@This()).create(.Sm_52, "sm_52", &[_]FeatureType {
	51	}),
	52	CpuInfo(@This(), FeatureType).create(.Sm_52, "sm_52", &[_]FeatureType {
53	53	.Ptx41,
54	54	.Sm_52,
55		},
56		CpuInfo(@This()).create(.Sm_53, "sm_53", &[_]FeatureType {
	55	}),
	56	CpuInfo(@This(), FeatureType).create(.Sm_53, "sm_53", &[_]FeatureType {
57	57	.Ptx42,
58	58	.Sm_53,
59		},
60		CpuInfo(@This()).create(.Sm_60, "sm_60", &[_]FeatureType {
	59	}),
	60	CpuInfo(@This(), FeatureType).create(.Sm_60, "sm_60", &[_]FeatureType {
61	61	.Ptx50,
62	62	.Sm_60,
63		},
64		CpuInfo(@This()).create(.Sm_61, "sm_61", &[_]FeatureType {
	63	}),
	64	CpuInfo(@This(), FeatureType).create(.Sm_61, "sm_61", &[_]FeatureType {
65	65	.Ptx50,
66	66	.Sm_61,
67		},
68		CpuInfo(@This()).create(.Sm_62, "sm_62", &[_]FeatureType {
	67	}),
	68	CpuInfo(@This(), FeatureType).create(.Sm_62, "sm_62", &[_]FeatureType {
69	69	.Ptx50,
70	70	.Sm_62,
71		},
72		CpuInfo(@This()).create(.Sm_70, "sm_70", &[_]FeatureType {
	71	}),
	72	CpuInfo(@This(), FeatureType).create(.Sm_70, "sm_70", &[_]FeatureType {
73	73	.Ptx60,
74	74	.Sm_70,
75		},
76		CpuInfo(@This()).create(.Sm_72, "sm_72", &[_]FeatureType {
	75	}),
	76	CpuInfo(@This(), FeatureType).create(.Sm_72, "sm_72", &[_]FeatureType {
77	77	.Ptx61,
78	78	.Sm_72,
79		},
80		CpuInfo(@This()).create(.Sm_75, "sm_75", &[_]FeatureType {
	79	}),
	80	CpuInfo(@This(), FeatureType).create(.Sm_75, "sm_75", &[_]FeatureType {
81	81	.Ptx63,
82	82	.Sm_75,
83		},
	83	}),
84	84	};
85	85	};

lib/std/target/cpu/PowerPcCpu.zig+90-90

...	...	@@ -2,20 +2,20 @@ const feature = @import("std").target.feature;
2	2	const CpuInfo = @import("std").target.cpu.CpuInfo;
3	3
4	4	pub const PowerPcCpu = enum {
5		440,
6		450,
7		601,
8		602,
9		603,
	5	Cpu440,
	6	Cpu450,
	7	Cpu601,
	8	Cpu602,
	9	Cpu603,
10	10	E603,
11	11	Ev603,
12		604,
	12	Cpu604,
13	13	E604,
14		620,
15		7400,
16		7450,
17		750,
18		970,
	14	Cpu620,
	15	Cpu7400,
	16	Cpu7450,
	17	Cpu750,
	18	Cpu970,
19	19	A2,
20	20	A2q,
21	21	E500,
...	...	@@ -23,7 +23,7 @@ pub const PowerPcCpu = enum {
23	23	E5500,
24	24	G3,
25	25	G4,
26		G4+,
	26	G4plus,
27	27	G5,
28	28	Generic,
29	29	Ppc,
...	...	@@ -40,14 +40,14 @@ pub const PowerPcCpu = enum {
40	40	Pwr8,
41	41	Pwr9,
42	42
43		pub fn getInfo(self: @This()) CpuInfo {
	43	const FeatureType = feature.PowerPcFeature;
	44
	45	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
44	46	return cpu_infos[@enumToInt(self)];
45	47	}
46	48
47		pub const FeatureType = feature.PowerPcFeature;
48
49		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
50		CpuInfo(@This()).create(.440, "440", &[_]FeatureType {
	49	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	50	CpuInfo(@This(), FeatureType).create(.Cpu440, "440", &[_]FeatureType {
51	51	.Icbt,
52	52	.Booke,
53	53	.HardFloat,
...	...	@@ -55,8 +55,8 @@ pub const PowerPcCpu = enum {
55	55	.Frsqrte,
56	56	.Isel,
57	57	.Msync,
58		},
59		CpuInfo(@This()).create(.450, "450", &[_]FeatureType {
	58	}),
	59	CpuInfo(@This(), FeatureType).create(.Cpu450, "450", &[_]FeatureType {
60	60	.Icbt,
61	61	.Booke,
62	62	.HardFloat,
...	...	@@ -64,63 +64,63 @@ pub const PowerPcCpu = enum {
64	64	.Frsqrte,
65	65	.Isel,
66	66	.Msync,
67		},
68		CpuInfo(@This()).create(.601, "601", &[_]FeatureType {
	67	}),
	68	CpuInfo(@This(), FeatureType).create(.Cpu601, "601", &[_]FeatureType {
69	69	.HardFloat,
70	70	.Fpu,
71		},
72		CpuInfo(@This()).create(.602, "602", &[_]FeatureType {
	71	}),
	72	CpuInfo(@This(), FeatureType).create(.Cpu602, "602", &[_]FeatureType {
73	73	.HardFloat,
74	74	.Fpu,
75		},
76		CpuInfo(@This()).create(.603, "603", &[_]FeatureType {
	75	}),
	76	CpuInfo(@This(), FeatureType).create(.Cpu603, "603", &[_]FeatureType {
77	77	.HardFloat,
78	78	.Fres,
79	79	.Frsqrte,
80		},
81		CpuInfo(@This()).create(.E603, "603e", &[_]FeatureType {
	80	}),
	81	CpuInfo(@This(), FeatureType).create(.E603, "603e", &[_]FeatureType {
82	82	.HardFloat,
83	83	.Fres,
84	84	.Frsqrte,
85		},
86		CpuInfo(@This()).create(.Ev603, "603ev", &[_]FeatureType {
	85	}),
	86	CpuInfo(@This(), FeatureType).create(.Ev603, "603ev", &[_]FeatureType {
87	87	.HardFloat,
88	88	.Fres,
89	89	.Frsqrte,
90		},
91		CpuInfo(@This()).create(.604, "604", &[_]FeatureType {
	90	}),
	91	CpuInfo(@This(), FeatureType).create(.Cpu604, "604", &[_]FeatureType {
92	92	.HardFloat,
93	93	.Fres,
94	94	.Frsqrte,
95		},
96		CpuInfo(@This()).create(.E604, "604e", &[_]FeatureType {
	95	}),
	96	CpuInfo(@This(), FeatureType).create(.E604, "604e", &[_]FeatureType {
97	97	.HardFloat,
98	98	.Fres,
99	99	.Frsqrte,
100		},
101		CpuInfo(@This()).create(.620, "620", &[_]FeatureType {
	100	}),
	101	CpuInfo(@This(), FeatureType).create(.Cpu620, "620", &[_]FeatureType {
102	102	.HardFloat,
103	103	.Fres,
104	104	.Frsqrte,
105		},
106		CpuInfo(@This()).create(.7400, "7400", &[_]FeatureType {
	105	}),
	106	CpuInfo(@This(), FeatureType).create(.Cpu7400, "7400", &[_]FeatureType {
107	107	.HardFloat,
108	108	.Altivec,
109	109	.Fres,
110	110	.Frsqrte,
111		},
112		CpuInfo(@This()).create(.7450, "7450", &[_]FeatureType {
	111	}),
	112	CpuInfo(@This(), FeatureType).create(.Cpu7450, "7450", &[_]FeatureType {
113	113	.HardFloat,
114	114	.Altivec,
115	115	.Fres,
116	116	.Frsqrte,
117		},
118		CpuInfo(@This()).create(.750, "750", &[_]FeatureType {
	117	}),
	118	CpuInfo(@This(), FeatureType).create(.Cpu750, "750", &[_]FeatureType {
119	119	.HardFloat,
120	120	.Fres,
121	121	.Frsqrte,
122		},
123		CpuInfo(@This()).create(.970, "970", &[_]FeatureType {
	122	}),
	123	CpuInfo(@This(), FeatureType).create(.Cpu970, "970", &[_]FeatureType {
124	124	.Bit64,
125	125	.HardFloat,
126	126	.Altivec,
...	...	@@ -129,8 +129,8 @@ pub const PowerPcCpu = enum {
129	129	.Fsqrt,
130	130	.Mfocrf,
131	131	.Stfiwx,
132		},
133		CpuInfo(@This()).create(.A2, "a2", &[_]FeatureType {
	132	}),
	133	CpuInfo(@This(), FeatureType).create(.A2, "a2", &[_]FeatureType {
134	134	.Bit64,
135	135	.Icbt,
136	136	.Booke,
...	...	@@ -151,8 +151,8 @@ pub const PowerPcCpu = enum {
151	151	.Recipprec,
152	152	.Stfiwx,
153	153	.SlowPopcntd,
154		},
155		CpuInfo(@This()).create(.A2q, "a2q", &[_]FeatureType {
	154	}),
	155	CpuInfo(@This(), FeatureType).create(.A2q, "a2q", &[_]FeatureType {
156	156	.Bit64,
157	157	.Icbt,
158	158	.Booke,
...	...	@@ -174,20 +174,20 @@ pub const PowerPcCpu = enum {
174	174	.Recipprec,
175	175	.Stfiwx,
176	176	.SlowPopcntd,
177		},
178		CpuInfo(@This()).create(.E500, "e500", &[_]FeatureType {
	177	}),
	178	CpuInfo(@This(), FeatureType).create(.E500, "e500", &[_]FeatureType {
179	179	.Icbt,
180	180	.Booke,
181	181	.Isel,
182		},
183		CpuInfo(@This()).create(.E500mc, "e500mc", &[_]FeatureType {
	182	}),
	183	CpuInfo(@This(), FeatureType).create(.E500mc, "e500mc", &[_]FeatureType {
184	184	.Icbt,
185	185	.Booke,
186	186	.Isel,
187	187	.HardFloat,
188	188	.Stfiwx,
189		},
190		CpuInfo(@This()).create(.E5500, "e5500", &[_]FeatureType {
	189	}),
	190	CpuInfo(@This(), FeatureType).create(.E5500, "e5500", &[_]FeatureType {
191	191	.Bit64,
192	192	.Icbt,
193	193	.Booke,
...	...	@@ -195,25 +195,25 @@ pub const PowerPcCpu = enum {
195	195	.Mfocrf,
196	196	.HardFloat,
197	197	.Stfiwx,
198		},
199		CpuInfo(@This()).create(.G3, "g3", &[_]FeatureType {
	198	}),
	199	CpuInfo(@This(), FeatureType).create(.G3, "g3", &[_]FeatureType {
200	200	.HardFloat,
201	201	.Fres,
202	202	.Frsqrte,
203		},
204		CpuInfo(@This()).create(.G4, "g4", &[_]FeatureType {
	203	}),
	204	CpuInfo(@This(), FeatureType).create(.G4, "g4", &[_]FeatureType {
205	205	.HardFloat,
206	206	.Altivec,
207	207	.Fres,
208	208	.Frsqrte,
209		},
210		CpuInfo(@This()).create(.G4+, "g4+", &[_]FeatureType {
	209	}),
	210	CpuInfo(@This(), FeatureType).create(.G4plus, "g4+", &[_]FeatureType {
211	211	.HardFloat,
212	212	.Altivec,
213	213	.Fres,
214	214	.Frsqrte,
215		},
216		CpuInfo(@This()).create(.G5, "g5", &[_]FeatureType {
	215	}),
	216	CpuInfo(@This(), FeatureType).create(.G5, "g5", &[_]FeatureType {
217	217	.Bit64,
218	218	.HardFloat,
219	219	.Altivec,
...	...	@@ -222,17 +222,17 @@ pub const PowerPcCpu = enum {
222	222	.Fsqrt,
223	223	.Mfocrf,
224	224	.Stfiwx,
225		},
226		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
	225	}),
	226	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
227	227	.HardFloat,
228		},
229		CpuInfo(@This()).create(.Ppc, "ppc", &[_]FeatureType {
	228	}),
	229	CpuInfo(@This(), FeatureType).create(.Ppc, "ppc", &[_]FeatureType {
230	230	.HardFloat,
231		},
232		CpuInfo(@This()).create(.Ppc32, "ppc32", &[_]FeatureType {
	231	}),
	232	CpuInfo(@This(), FeatureType).create(.Ppc32, "ppc32", &[_]FeatureType {
233	233	.HardFloat,
234		},
235		CpuInfo(@This()).create(.Ppc64, "ppc64", &[_]FeatureType {
	234	}),
	235	CpuInfo(@This(), FeatureType).create(.Ppc64, "ppc64", &[_]FeatureType {
236	236	.Bit64,
237	237	.HardFloat,
238	238	.Altivec,
...	...	@@ -241,8 +241,8 @@ pub const PowerPcCpu = enum {
241	241	.Fsqrt,
242	242	.Mfocrf,
243	243	.Stfiwx,
244		},
245		CpuInfo(@This()).create(.Ppc64le, "ppc64le", &[_]FeatureType {
	244	}),
	245	CpuInfo(@This(), FeatureType).create(.Ppc64le, "ppc64le", &[_]FeatureType {
246	246	.Bit64,
247	247	.HardFloat,
248	248	.Altivec,
...	...	@@ -273,8 +273,8 @@ pub const PowerPcCpu = enum {
273	273	.Stfiwx,
274	274	.TwoConstNr,
275	275	.Vsx,
276		},
277		CpuInfo(@This()).create(.Pwr3, "pwr3", &[_]FeatureType {
	276	}),
	277	CpuInfo(@This(), FeatureType).create(.Pwr3, "pwr3", &[_]FeatureType {
278	278	.Bit64,
279	279	.HardFloat,
280	280	.Altivec,
...	...	@@ -282,8 +282,8 @@ pub const PowerPcCpu = enum {
282	282	.Frsqrte,
283	283	.Mfocrf,
284	284	.Stfiwx,
285		},
286		CpuInfo(@This()).create(.Pwr4, "pwr4", &[_]FeatureType {
	285	}),
	286	CpuInfo(@This(), FeatureType).create(.Pwr4, "pwr4", &[_]FeatureType {
287	287	.Bit64,
288	288	.HardFloat,
289	289	.Altivec,
...	...	@@ -292,8 +292,8 @@ pub const PowerPcCpu = enum {
292	292	.Fsqrt,
293	293	.Mfocrf,
294	294	.Stfiwx,
295		},
296		CpuInfo(@This()).create(.Pwr5, "pwr5", &[_]FeatureType {
	295	}),
	296	CpuInfo(@This(), FeatureType).create(.Pwr5, "pwr5", &[_]FeatureType {
297	297	.Bit64,
298	298	.HardFloat,
299	299	.Altivec,
...	...	@@ -304,8 +304,8 @@ pub const PowerPcCpu = enum {
304	304	.Fsqrt,
305	305	.Mfocrf,
306	306	.Stfiwx,
307		},
308		CpuInfo(@This()).create(.Pwr5x, "pwr5x", &[_]FeatureType {
	307	}),
	308	CpuInfo(@This(), FeatureType).create(.Pwr5x, "pwr5x", &[_]FeatureType {
309	309	.Bit64,
310	310	.HardFloat,
311	311	.Altivec,
...	...	@@ -317,8 +317,8 @@ pub const PowerPcCpu = enum {
317	317	.Fsqrt,
318	318	.Mfocrf,
319	319	.Stfiwx,
320		},
321		CpuInfo(@This()).create(.Pwr6, "pwr6", &[_]FeatureType {
	320	}),
	321	CpuInfo(@This(), FeatureType).create(.Pwr6, "pwr6", &[_]FeatureType {
322	322	.Bit64,
323	323	.HardFloat,
324	324	.Altivec,
...	...	@@ -334,8 +334,8 @@ pub const PowerPcCpu = enum {
334	334	.Mfocrf,
335	335	.Recipprec,
336	336	.Stfiwx,
337		},
338		CpuInfo(@This()).create(.Pwr6x, "pwr6x", &[_]FeatureType {
	337	}),
	338	CpuInfo(@This(), FeatureType).create(.Pwr6x, "pwr6x", &[_]FeatureType {
339	339	.Bit64,
340	340	.HardFloat,
341	341	.Altivec,
...	...	@@ -351,8 +351,8 @@ pub const PowerPcCpu = enum {
351	351	.Mfocrf,
352	352	.Recipprec,
353	353	.Stfiwx,
354		},
355		CpuInfo(@This()).create(.Pwr7, "pwr7", &[_]FeatureType {
	354	}),
	355	CpuInfo(@This(), FeatureType).create(.Pwr7, "pwr7", &[_]FeatureType {
356	356	.Bit64,
357	357	.HardFloat,
358	358	.Altivec,
...	...	@@ -376,8 +376,8 @@ pub const PowerPcCpu = enum {
376	376	.Stfiwx,
377	377	.TwoConstNr,
378	378	.Vsx,
379		},
380		CpuInfo(@This()).create(.Pwr8, "pwr8", &[_]FeatureType {
	379	}),
	380	CpuInfo(@This(), FeatureType).create(.Pwr8, "pwr8", &[_]FeatureType {
381	381	.Bit64,
382	382	.HardFloat,
383	383	.Altivec,
...	...	@@ -408,8 +408,8 @@ pub const PowerPcCpu = enum {
408	408	.Stfiwx,
409	409	.TwoConstNr,
410	410	.Vsx,
411		},
412		CpuInfo(@This()).create(.Pwr9, "pwr9", &[_]FeatureType {
	411	}),
	412	CpuInfo(@This(), FeatureType).create(.Pwr9, "pwr9", &[_]FeatureType {
413	413	.Bit64,
414	414	.HardFloat,
415	415	.Altivec,
...	...	@@ -446,6 +446,6 @@ pub const PowerPcCpu = enum {
446	446	.TwoConstNr,
447	447	.Vsx,
448	448	.VectorsUseTwoUnits,
449		},
	449	}),
450	450	};
451	451	};

lib/std/target/cpu/RiscVCpu.zig+8-8

...	...	@@ -5,19 +5,19 @@ pub const RiscVCpu = enum {
5	5	GenericRv32,
6	6	GenericRv64,
7	7
8		pub fn getInfo(self: @This()) CpuInfo {
	8	const FeatureType = feature.RiscVFeature;
	9
	10	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
9	11	return cpu_infos[@enumToInt(self)];
10	12	}
11	13
12		pub const FeatureType = feature.RiscVFeature;
13
14		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
15		CpuInfo(@This()).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
	14	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	15	CpuInfo(@This(), FeatureType).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
16	16	.RvcHints,
17		},
18		CpuInfo(@This()).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
	17	}),
	18	CpuInfo(@This(), FeatureType).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
19	19	.Bit64,
20	20	.RvcHints,
21		},
	21	}),
22	22	};
23	23	};

lib/std/target/cpu/SparcCpu.zig+84-84

...	...	@@ -43,174 +43,174 @@ pub const SparcCpu = enum {
43	43	V8,
44	44	V9,
45	45
46		pub fn getInfo(self: @This()) CpuInfo {
	46	const FeatureType = feature.SparcFeature;
	47
	48	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
47	49	return cpu_infos[@enumToInt(self)];
48	50	}
49	51
50		pub const FeatureType = feature.SparcFeature;
51
52		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
53		CpuInfo(@This()).create(.At697e, "at697e", &[_]FeatureType {
	52	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	53	CpuInfo(@This(), FeatureType).create(.At697e, "at697e", &[_]FeatureType {
54	54	.Leon,
55	55	.Insertnopload,
56		},
57		CpuInfo(@This()).create(.At697f, "at697f", &[_]FeatureType {
	56	}),
	57	CpuInfo(@This(), FeatureType).create(.At697f, "at697f", &[_]FeatureType {
58	58	.Leon,
59	59	.Insertnopload,
60		},
61		CpuInfo(@This()).create(.F934, "f934", &[_]FeatureType {
62		},
63		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
64		},
65		CpuInfo(@This()).create(.Gr712rc, "gr712rc", &[_]FeatureType {
	60	}),
	61	CpuInfo(@This(), FeatureType).create(.F934, "f934", &[_]FeatureType {
	62	}),
	63	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
	64	}),
	65	CpuInfo(@This(), FeatureType).create(.Gr712rc, "gr712rc", &[_]FeatureType {
66	66	.Leon,
67	67	.Hasleoncasa,
68		},
69		CpuInfo(@This()).create(.Gr740, "gr740", &[_]FeatureType {
	68	}),
	69	CpuInfo(@This(), FeatureType).create(.Gr740, "gr740", &[_]FeatureType {
70	70	.Leon,
71	71	.Leonpwrpsr,
72	72	.Hasleoncasa,
73	73	.Leoncyclecounter,
74	74	.Hasumacsmac,
75		},
76		CpuInfo(@This()).create(.Hypersparc, "hypersparc", &[_]FeatureType {
77		},
78		CpuInfo(@This()).create(.Leon2, "leon2", &[_]FeatureType {
	75	}),
	76	CpuInfo(@This(), FeatureType).create(.Hypersparc, "hypersparc", &[_]FeatureType {
	77	}),
	78	CpuInfo(@This(), FeatureType).create(.Leon2, "leon2", &[_]FeatureType {
79	79	.Leon,
80		},
81		CpuInfo(@This()).create(.Leon3, "leon3", &[_]FeatureType {
	80	}),
	81	CpuInfo(@This(), FeatureType).create(.Leon3, "leon3", &[_]FeatureType {
82	82	.Leon,
83	83	.Hasumacsmac,
84		},
85		CpuInfo(@This()).create(.Leon4, "leon4", &[_]FeatureType {
	84	}),
	85	CpuInfo(@This(), FeatureType).create(.Leon4, "leon4", &[_]FeatureType {
86	86	.Leon,
87	87	.Hasleoncasa,
88	88	.Hasumacsmac,
89		},
90		CpuInfo(@This()).create(.Ma2080, "ma2080", &[_]FeatureType {
	89	}),
	90	CpuInfo(@This(), FeatureType).create(.Ma2080, "ma2080", &[_]FeatureType {
91	91	.Leon,
92	92	.Hasleoncasa,
93		},
94		CpuInfo(@This()).create(.Ma2085, "ma2085", &[_]FeatureType {
	93	}),
	94	CpuInfo(@This(), FeatureType).create(.Ma2085, "ma2085", &[_]FeatureType {
95	95	.Leon,
96	96	.Hasleoncasa,
97		},
98		CpuInfo(@This()).create(.Ma2100, "ma2100", &[_]FeatureType {
	97	}),
	98	CpuInfo(@This(), FeatureType).create(.Ma2100, "ma2100", &[_]FeatureType {
99	99	.Leon,
100	100	.Hasleoncasa,
101		},
102		CpuInfo(@This()).create(.Ma2150, "ma2150", &[_]FeatureType {
	101	}),
	102	CpuInfo(@This(), FeatureType).create(.Ma2150, "ma2150", &[_]FeatureType {
103	103	.Leon,
104	104	.Hasleoncasa,
105		},
106		CpuInfo(@This()).create(.Ma2155, "ma2155", &[_]FeatureType {
	105	}),
	106	CpuInfo(@This(), FeatureType).create(.Ma2155, "ma2155", &[_]FeatureType {
107	107	.Leon,
108	108	.Hasleoncasa,
109		},
110		CpuInfo(@This()).create(.Ma2450, "ma2450", &[_]FeatureType {
	109	}),
	110	CpuInfo(@This(), FeatureType).create(.Ma2450, "ma2450", &[_]FeatureType {
111	111	.Leon,
112	112	.Hasleoncasa,
113		},
114		CpuInfo(@This()).create(.Ma2455, "ma2455", &[_]FeatureType {
	113	}),
	114	CpuInfo(@This(), FeatureType).create(.Ma2455, "ma2455", &[_]FeatureType {
115	115	.Leon,
116	116	.Hasleoncasa,
117		},
118		CpuInfo(@This()).create(.Ma2480, "ma2480", &[_]FeatureType {
	117	}),
	118	CpuInfo(@This(), FeatureType).create(.Ma2480, "ma2480", &[_]FeatureType {
119	119	.Leon,
120	120	.Hasleoncasa,
121		},
122		CpuInfo(@This()).create(.Ma2485, "ma2485", &[_]FeatureType {
	121	}),
	122	CpuInfo(@This(), FeatureType).create(.Ma2485, "ma2485", &[_]FeatureType {
123	123	.Leon,
124	124	.Hasleoncasa,
125		},
126		CpuInfo(@This()).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
	125	}),
	126	CpuInfo(@This(), FeatureType).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
127	127	.Leon,
128	128	.Hasleoncasa,
129		},
130		CpuInfo(@This()).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
	129	}),
	130	CpuInfo(@This(), FeatureType).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
131	131	.Leon,
132	132	.Hasleoncasa,
133		},
134		CpuInfo(@This()).create(.Myriad2, "myriad2", &[_]FeatureType {
	133	}),
	134	CpuInfo(@This(), FeatureType).create(.Myriad2, "myriad2", &[_]FeatureType {
135	135	.Leon,
136	136	.Hasleoncasa,
137		},
138		CpuInfo(@This()).create(.Myriad21, "myriad2.1", &[_]FeatureType {
	137	}),
	138	CpuInfo(@This(), FeatureType).create(.Myriad21, "myriad2.1", &[_]FeatureType {
139	139	.Leon,
140	140	.Hasleoncasa,
141		},
142		CpuInfo(@This()).create(.Myriad22, "myriad2.2", &[_]FeatureType {
	141	}),
	142	CpuInfo(@This(), FeatureType).create(.Myriad22, "myriad2.2", &[_]FeatureType {
143	143	.Leon,
144	144	.Hasleoncasa,
145		},
146		CpuInfo(@This()).create(.Myriad23, "myriad2.3", &[_]FeatureType {
	145	}),
	146	CpuInfo(@This(), FeatureType).create(.Myriad23, "myriad2.3", &[_]FeatureType {
147	147	.Leon,
148	148	.Hasleoncasa,
149		},
150		CpuInfo(@This()).create(.Niagara, "niagara", &[_]FeatureType {
	149	}),
	150	CpuInfo(@This(), FeatureType).create(.Niagara, "niagara", &[_]FeatureType {
151	151	.DeprecatedV8,
152	152	.V9,
153	153	.Vis,
154	154	.Vis2,
155		},
156		CpuInfo(@This()).create(.Niagara2, "niagara2", &[_]FeatureType {
	155	}),
	156	CpuInfo(@This(), FeatureType).create(.Niagara2, "niagara2", &[_]FeatureType {
157	157	.DeprecatedV8,
158	158	.V9,
159	159	.Vis,
160	160	.Vis2,
161	161	.Popc,
162		},
163		CpuInfo(@This()).create(.Niagara3, "niagara3", &[_]FeatureType {
	162	}),
	163	CpuInfo(@This(), FeatureType).create(.Niagara3, "niagara3", &[_]FeatureType {
164	164	.DeprecatedV8,
165	165	.V9,
166	166	.Vis,
167	167	.Vis2,
168	168	.Popc,
169		},
170		CpuInfo(@This()).create(.Niagara4, "niagara4", &[_]FeatureType {
	169	}),
	170	CpuInfo(@This(), FeatureType).create(.Niagara4, "niagara4", &[_]FeatureType {
171	171	.DeprecatedV8,
172	172	.V9,
173	173	.Vis,
174	174	.Vis2,
175	175	.Vis3,
176	176	.Popc,
177		},
178		CpuInfo(@This()).create(.Sparclet, "sparclet", &[_]FeatureType {
179		},
180		CpuInfo(@This()).create(.Sparclite, "sparclite", &[_]FeatureType {
181		},
182		CpuInfo(@This()).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
183		},
184		CpuInfo(@This()).create(.Supersparc, "supersparc", &[_]FeatureType {
185		},
186		CpuInfo(@This()).create(.Tsc701, "tsc701", &[_]FeatureType {
187		},
188		CpuInfo(@This()).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
	177	}),
	178	CpuInfo(@This(), FeatureType).create(.Sparclet, "sparclet", &[_]FeatureType {
	179	}),
	180	CpuInfo(@This(), FeatureType).create(.Sparclite, "sparclite", &[_]FeatureType {
	181	}),
	182	CpuInfo(@This(), FeatureType).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
	183	}),
	184	CpuInfo(@This(), FeatureType).create(.Supersparc, "supersparc", &[_]FeatureType {
	185	}),
	186	CpuInfo(@This(), FeatureType).create(.Tsc701, "tsc701", &[_]FeatureType {
	187	}),
	188	CpuInfo(@This(), FeatureType).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
189	189	.DeprecatedV8,
190	190	.V9,
191	191	.Vis,
192		},
193		CpuInfo(@This()).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
	192	}),
	193	CpuInfo(@This(), FeatureType).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
194	194	.DeprecatedV8,
195	195	.V9,
196	196	.Vis,
197	197	.Vis2,
198		},
199		CpuInfo(@This()).create(.Ut699, "ut699", &[_]FeatureType {
	198	}),
	199	CpuInfo(@This(), FeatureType).create(.Ut699, "ut699", &[_]FeatureType {
200	200	.Leon,
201	201	.NoFmuls,
202	202	.NoFsmuld,
203	203	.Fixallfdivsqrt,
204	204	.Insertnopload,
205		},
206		CpuInfo(@This()).create(.V7, "v7", &[_]FeatureType {
	205	}),
	206	CpuInfo(@This(), FeatureType).create(.V7, "v7", &[_]FeatureType {
207	207	.NoFsmuld,
208	208	.SoftMulDiv,
209		},
210		CpuInfo(@This()).create(.V8, "v8", &[_]FeatureType {
211		},
212		CpuInfo(@This()).create(.V9, "v9", &[_]FeatureType {
	209	}),
	210	CpuInfo(@This(), FeatureType).create(.V8, "v8", &[_]FeatureType {
	211	}),
	212	CpuInfo(@This(), FeatureType).create(.V9, "v9", &[_]FeatureType {
213	213	.V9,
214		},
	214	}),
215	215	};
216	216	};

lib/std/target/cpu/SystemZCpu.zig+30-30

...	...	@@ -16,14 +16,14 @@ pub const SystemZCpu = enum {
16	16	Z196,
17	17	ZEC12,
18	18
19		pub fn getInfo(self: @This()) CpuInfo {
	19	const FeatureType = feature.SystemZFeature;
	20
	21	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
20	22	return cpu_infos[@enumToInt(self)];
21	23	}
22	24
23		pub const FeatureType = feature.SystemZFeature;
24
25		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
26		CpuInfo(@This()).create(.Arch10, "arch10", &[_]FeatureType {
	25	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	26	CpuInfo(@This(), FeatureType).create(.Arch10, "arch10", &[_]FeatureType {
27	27	.DfpZonedConversion,
28	28	.DistinctOps,
29	29	.EnhancedDat2,
...	...	@@ -41,8 +41,8 @@ pub const SystemZCpu = enum {
41	41	.ProcessorAssist,
42	42	.ResetReferenceBitsMultiple,
43	43	.TransactionalExecution,
44		},
45		CpuInfo(@This()).create(.Arch11, "arch11", &[_]FeatureType {
	44	}),
	45	CpuInfo(@This(), FeatureType).create(.Arch11, "arch11", &[_]FeatureType {
46	46	.DfpPackedConversion,
47	47	.DfpZonedConversion,
48	48	.DistinctOps,
...	...	@@ -65,8 +65,8 @@ pub const SystemZCpu = enum {
65	65	.ResetReferenceBitsMultiple,
66	66	.TransactionalExecution,
67	67	.Vector,
68		},
69		CpuInfo(@This()).create(.Arch12, "arch12", &[_]FeatureType {
	68	}),
	69	CpuInfo(@This(), FeatureType).create(.Arch12, "arch12", &[_]FeatureType {
70	70	.DfpPackedConversion,
71	71	.DfpZonedConversion,
72	72	.DistinctOps,
...	...	@@ -96,8 +96,8 @@ pub const SystemZCpu = enum {
96	96	.Vector,
97	97	.VectorEnhancements1,
98	98	.VectorPackedDecimal,
99		},
100		CpuInfo(@This()).create(.Arch13, "arch13", &[_]FeatureType {
	99	}),
	100	CpuInfo(@This(), FeatureType).create(.Arch13, "arch13", &[_]FeatureType {
101	101	.DfpPackedConversion,
102	102	.DfpZonedConversion,
103	103	.DeflateConversion,
...	...	@@ -133,10 +133,10 @@ pub const SystemZCpu = enum {
133	133	.VectorEnhancements2,
134	134	.VectorPackedDecimal,
135	135	.VectorPackedDecimalEnhancement,
136		},
137		CpuInfo(@This()).create(.Arch8, "arch8", &[_]FeatureType {
138		},
139		CpuInfo(@This()).create(.Arch9, "arch9", &[_]FeatureType {
	136	}),
	137	CpuInfo(@This(), FeatureType).create(.Arch8, "arch8", &[_]FeatureType {
	138	}),
	139	CpuInfo(@This(), FeatureType).create(.Arch9, "arch9", &[_]FeatureType {
140	140	.DistinctOps,
141	141	.FpExtension,
142	142	.FastSerialization,
...	...	@@ -147,12 +147,12 @@ pub const SystemZCpu = enum {
147	147	.MessageSecurityAssistExtension4,
148	148	.PopulationCount,
149	149	.ResetReferenceBitsMultiple,
150		},
151		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
152		},
153		CpuInfo(@This()).create(.Z10, "z10", &[_]FeatureType {
154		},
155		CpuInfo(@This()).create(.Z13, "z13", &[_]FeatureType {
	150	}),
	151	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
	152	}),
	153	CpuInfo(@This(), FeatureType).create(.Z10, "z10", &[_]FeatureType {
	154	}),
	155	CpuInfo(@This(), FeatureType).create(.Z13, "z13", &[_]FeatureType {
156	156	.DfpPackedConversion,
157	157	.DfpZonedConversion,
158	158	.DistinctOps,
...	...	@@ -175,8 +175,8 @@ pub const SystemZCpu = enum {
175	175	.ResetReferenceBitsMultiple,
176	176	.TransactionalExecution,
177	177	.Vector,
178		},
179		CpuInfo(@This()).create(.Z14, "z14", &[_]FeatureType {
	178	}),
	179	CpuInfo(@This(), FeatureType).create(.Z14, "z14", &[_]FeatureType {
180	180	.DfpPackedConversion,
181	181	.DfpZonedConversion,
182	182	.DistinctOps,
...	...	@@ -206,8 +206,8 @@ pub const SystemZCpu = enum {
206	206	.Vector,
207	207	.VectorEnhancements1,
208	208	.VectorPackedDecimal,
209		},
210		CpuInfo(@This()).create(.Z15, "z15", &[_]FeatureType {
	209	}),
	210	CpuInfo(@This(), FeatureType).create(.Z15, "z15", &[_]FeatureType {
211	211	.DfpPackedConversion,
212	212	.DfpZonedConversion,
213	213	.DeflateConversion,
...	...	@@ -243,8 +243,8 @@ pub const SystemZCpu = enum {
243	243	.VectorEnhancements2,
244	244	.VectorPackedDecimal,
245	245	.VectorPackedDecimalEnhancement,
246		},
247		CpuInfo(@This()).create(.Z196, "z196", &[_]FeatureType {
	246	}),
	247	CpuInfo(@This(), FeatureType).create(.Z196, "z196", &[_]FeatureType {
248	248	.DistinctOps,
249	249	.FpExtension,
250	250	.FastSerialization,
...	...	@@ -255,8 +255,8 @@ pub const SystemZCpu = enum {
255	255	.MessageSecurityAssistExtension4,
256	256	.PopulationCount,
257	257	.ResetReferenceBitsMultiple,
258		},
259		CpuInfo(@This()).create(.ZEC12, "zEC12", &[_]FeatureType {
	258	}),
	259	CpuInfo(@This(), FeatureType).create(.ZEC12, "zEC12", &[_]FeatureType {
260	260	.DfpZonedConversion,
261	261	.DistinctOps,
262	262	.EnhancedDat2,
...	...	@@ -274,6 +274,6 @@ pub const SystemZCpu = enum {
274	274	.ProcessorAssist,
275	275	.ResetReferenceBitsMultiple,
276	276	.TransactionalExecution,
277		},
	277	}),
278	278	};
279	279	};

lib/std/target/cpu/WebAssemblyCpu.zig+10-10

...	...	@@ -6,23 +6,23 @@ pub const WebAssemblyCpu = enum {
6	6	Generic,
7	7	Mvp,
8	8
9		pub fn getInfo(self: @This()) CpuInfo {
	9	const FeatureType = feature.WebAssemblyFeature;
	10
	11	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
10	12	return cpu_infos[@enumToInt(self)];
11	13	}
12	14
13		pub const FeatureType = feature.WebAssemblyFeature;
14
15		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
16		CpuInfo(@This()).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
	15	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	16	CpuInfo(@This(), FeatureType).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
17	17	.Atomics,
18	18	.MutableGlobals,
19	19	.NontrappingFptoint,
20	20	.Simd128,
21	21	.SignExt,
22		},
23		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
24		},
25		CpuInfo(@This()).create(.Mvp, "mvp", &[_]FeatureType {
26		},
	22	}),
	23	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
	24	}),
	25	CpuInfo(@This(), FeatureType).create(.Mvp, "mvp", &[_]FeatureType {
	26	}),
27	27	};
28	28	};

lib/std/target/cpu/X86Cpu.zig+162-162

...	...	@@ -82,14 +82,14 @@ pub const X86Cpu = enum {
82	82	Znver1,
83	83	Znver2,
84	84
85		pub fn getInfo(self: @This()) CpuInfo {
	85	const FeatureType = feature.X86Feature;
	86
	87	pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
86	88	return cpu_infos[@enumToInt(self)];
87	89	}
88	90
89		pub const FeatureType = feature.X86Feature;
90
91		const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
92		CpuInfo(@This()).create(.Amdfam10, "amdfam10", &[_]FeatureType {
	91	pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
	92	CpuInfo(@This(), FeatureType).create(.Amdfam10, "amdfam10", &[_]FeatureType {
93	93	.Mmx,
94	94	.Dnowa3,
95	95	.Bit64,
...	...	@@ -106,8 +106,8 @@ pub const X86Cpu = enum {
106	106	.Sse4a,
107	107	.SlowShld,
108	108	.X87,
109		},
110		CpuInfo(@This()).create(.Athlon, "athlon", &[_]FeatureType {
	109	}),
	110	CpuInfo(@This(), FeatureType).create(.Athlon, "athlon", &[_]FeatureType {
111	111	.Mmx,
112	112	.Dnowa3,
113	113	.Cmov,
...	...	@@ -116,8 +116,8 @@ pub const X86Cpu = enum {
116	116	.SlowShld,
117	117	.SlowUnalignedMem16,
118	118	.X87,
119		},
120		CpuInfo(@This()).create(.Athlon4, "athlon-4", &[_]FeatureType {
	119	}),
	120	CpuInfo(@This(), FeatureType).create(.Athlon4, "athlon-4", &[_]FeatureType {
121	121	.Mmx,
122	122	.Dnowa3,
123	123	.Cmov,
...	...	@@ -128,8 +128,8 @@ pub const X86Cpu = enum {
128	128	.SlowShld,
129	129	.SlowUnalignedMem16,
130	130	.X87,
131		},
132		CpuInfo(@This()).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
	131	}),
	132	CpuInfo(@This(), FeatureType).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
133	133	.Mmx,
134	134	.Dnowa3,
135	135	.Bit64,
...	...	@@ -143,8 +143,8 @@ pub const X86Cpu = enum {
143	143	.SlowShld,
144	144	.SlowUnalignedMem16,
145	145	.X87,
146		},
147		CpuInfo(@This()).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
	146	}),
	147	CpuInfo(@This(), FeatureType).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
148	148	.Mmx,
149	149	.Dnowa3,
150	150	.Cmov,
...	...	@@ -155,8 +155,8 @@ pub const X86Cpu = enum {
155	155	.SlowShld,
156	156	.SlowUnalignedMem16,
157	157	.X87,
158		},
159		CpuInfo(@This()).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
	158	}),
	159	CpuInfo(@This(), FeatureType).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
160	160	.Mmx,
161	161	.Dnowa3,
162	162	.Cmov,
...	...	@@ -165,8 +165,8 @@ pub const X86Cpu = enum {
165	165	.SlowShld,
166	166	.SlowUnalignedMem16,
167	167	.X87,
168		},
169		CpuInfo(@This()).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
	168	}),
	169	CpuInfo(@This(), FeatureType).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
170	170	.Mmx,
171	171	.Dnowa3,
172	172	.Cmov,
...	...	@@ -177,8 +177,8 @@ pub const X86Cpu = enum {
177	177	.SlowShld,
178	178	.SlowUnalignedMem16,
179	179	.X87,
180		},
181		CpuInfo(@This()).create(.Athlon64, "athlon64", &[_]FeatureType {
	180	}),
	181	CpuInfo(@This(), FeatureType).create(.Athlon64, "athlon64", &[_]FeatureType {
182	182	.Mmx,
183	183	.Dnowa3,
184	184	.Bit64,
...	...	@@ -192,8 +192,8 @@ pub const X86Cpu = enum {
192	192	.SlowShld,
193	193	.SlowUnalignedMem16,
194	194	.X87,
195		},
196		CpuInfo(@This()).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
	195	}),
	196	CpuInfo(@This(), FeatureType).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
197	197	.Mmx,
198	198	.Dnowa3,
199	199	.Bit64,
...	...	@@ -208,8 +208,8 @@ pub const X86Cpu = enum {
208	208	.SlowShld,
209	209	.SlowUnalignedMem16,
210	210	.X87,
211		},
212		CpuInfo(@This()).create(.Atom, "atom", &[_]FeatureType {
	211	}),
	212	CpuInfo(@This(), FeatureType).create(.Atom, "atom", &[_]FeatureType {
213	213	.Bit64,
214	214	.Cmov,
215	215	.Cx8,
...	...	@@ -229,8 +229,8 @@ pub const X86Cpu = enum {
229	229	.SlowTwoMemOps,
230	230	.SlowUnalignedMem16,
231	231	.X87,
232		},
233		CpuInfo(@This()).create(.Barcelona, "barcelona", &[_]FeatureType {
	232	}),
	233	CpuInfo(@This(), FeatureType).create(.Barcelona, "barcelona", &[_]FeatureType {
234	234	.Mmx,
235	235	.Dnowa3,
236	236	.Bit64,
...	...	@@ -247,8 +247,8 @@ pub const X86Cpu = enum {
247	247	.Sse4a,
248	248	.SlowShld,
249	249	.X87,
250		},
251		CpuInfo(@This()).create(.Bdver1, "bdver1", &[_]FeatureType {
	250	}),
	251	CpuInfo(@This(), FeatureType).create(.Bdver1, "bdver1", &[_]FeatureType {
252	252	.Bit64,
253	253	.Sse,
254	254	.Aes,
...	...	@@ -271,8 +271,8 @@ pub const X86Cpu = enum {
271	271	.X87,
272	272	.Xop,
273	273	.Xsave,
274		},
275		CpuInfo(@This()).create(.Bdver2, "bdver2", &[_]FeatureType {
	274	}),
	275	CpuInfo(@This(), FeatureType).create(.Bdver2, "bdver2", &[_]FeatureType {
276	276	.Bit64,
277	277	.Sse,
278	278	.Aes,
...	...	@@ -300,8 +300,8 @@ pub const X86Cpu = enum {
300	300	.X87,
301	301	.Xop,
302	302	.Xsave,
303		},
304		CpuInfo(@This()).create(.Bdver3, "bdver3", &[_]FeatureType {
	303	}),
	304	CpuInfo(@This(), FeatureType).create(.Bdver3, "bdver3", &[_]FeatureType {
305	305	.Bit64,
306	306	.Sse,
307	307	.Aes,
...	...	@@ -331,8 +331,8 @@ pub const X86Cpu = enum {
331	331	.Xop,
332	332	.Xsave,
333	333	.Xsaveopt,
334		},
335		CpuInfo(@This()).create(.Bdver4, "bdver4", &[_]FeatureType {
	334	}),
	335	CpuInfo(@This(), FeatureType).create(.Bdver4, "bdver4", &[_]FeatureType {
336	336	.Bit64,
337	337	.Sse,
338	338	.Aes,
...	...	@@ -365,8 +365,8 @@ pub const X86Cpu = enum {
365	365	.Xop,
366	366	.Xsave,
367	367	.Xsaveopt,
368		},
369		CpuInfo(@This()).create(.Bonnell, "bonnell", &[_]FeatureType {
	368	}),
	369	CpuInfo(@This(), FeatureType).create(.Bonnell, "bonnell", &[_]FeatureType {
370	370	.Bit64,
371	371	.Cmov,
372	372	.Cx8,
...	...	@@ -386,8 +386,8 @@ pub const X86Cpu = enum {
386	386	.SlowTwoMemOps,
387	387	.SlowUnalignedMem16,
388	388	.X87,
389		},
390		CpuInfo(@This()).create(.Broadwell, "broadwell", &[_]FeatureType {
	389	}),
	390	CpuInfo(@This(), FeatureType).create(.Broadwell, "broadwell", &[_]FeatureType {
391	391	.Bit64,
392	392	.Adx,
393	393	.Sse,
...	...	@@ -427,8 +427,8 @@ pub const X86Cpu = enum {
427	427	.X87,
428	428	.Xsave,
429	429	.Xsaveopt,
430		},
431		CpuInfo(@This()).create(.Btver1, "btver1", &[_]FeatureType {
	430	}),
	431	CpuInfo(@This(), FeatureType).create(.Btver1, "btver1", &[_]FeatureType {
432	432	.Bit64,
433	433	.Cmov,
434	434	.Cx8,
...	...	@@ -448,8 +448,8 @@ pub const X86Cpu = enum {
448	448	.Ssse3,
449	449	.SlowShld,
450	450	.X87,
451		},
452		CpuInfo(@This()).create(.Btver2, "btver2", &[_]FeatureType {
	451	}),
	452	CpuInfo(@This(), FeatureType).create(.Btver2, "btver2", &[_]FeatureType {
453	453	.Bit64,
454	454	.Sse,
455	455	.Aes,
...	...	@@ -481,14 +481,14 @@ pub const X86Cpu = enum {
481	481	.X87,
482	482	.Xsave,
483	483	.Xsaveopt,
484		},
485		CpuInfo(@This()).create(.C3, "c3", &[_]FeatureType {
	484	}),
	485	CpuInfo(@This(), FeatureType).create(.C3, "c3", &[_]FeatureType {
486	486	.Mmx,
487	487	.Dnow3,
488	488	.SlowUnalignedMem16,
489	489	.X87,
490		},
491		CpuInfo(@This()).create(.C32, "c3-2", &[_]FeatureType {
	490	}),
	491	CpuInfo(@This(), FeatureType).create(.C32, "c3-2", &[_]FeatureType {
492	492	.Cmov,
493	493	.Cx8,
494	494	.Fxsr,
...	...	@@ -496,8 +496,8 @@ pub const X86Cpu = enum {
496	496	.Sse,
497	497	.SlowUnalignedMem16,
498	498	.X87,
499		},
500		CpuInfo(@This()).create(.Cannonlake, "cannonlake", &[_]FeatureType {
	499	}),
	500	CpuInfo(@This(), FeatureType).create(.Cannonlake, "cannonlake", &[_]FeatureType {
501	501	.Bit64,
502	502	.Adx,
503	503	.Sse,
...	...	@@ -552,8 +552,8 @@ pub const X86Cpu = enum {
552	552	.Xsavec,
553	553	.Xsaveopt,
554	554	.Xsaves,
555		},
556		CpuInfo(@This()).create(.Cascadelake, "cascadelake", &[_]FeatureType {
	555	}),
	556	CpuInfo(@This(), FeatureType).create(.Cascadelake, "cascadelake", &[_]FeatureType {
557	557	.Bit64,
558	558	.Adx,
559	559	.Sse,
...	...	@@ -607,8 +607,8 @@ pub const X86Cpu = enum {
607	607	.Xsavec,
608	608	.Xsaveopt,
609	609	.Xsaves,
610		},
611		CpuInfo(@This()).create(.Cooperlake, "cooperlake", &[_]FeatureType {
	610	}),
	611	CpuInfo(@This(), FeatureType).create(.Cooperlake, "cooperlake", &[_]FeatureType {
612	612	.Bit64,
613	613	.Adx,
614	614	.Sse,
...	...	@@ -663,8 +663,8 @@ pub const X86Cpu = enum {
663	663	.Xsavec,
664	664	.Xsaveopt,
665	665	.Xsaves,
666		},
667		CpuInfo(@This()).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
	666	}),
	667	CpuInfo(@This(), FeatureType).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
668	668	.Bit64,
669	669	.Sse,
670	670	.Avx,
...	...	@@ -692,8 +692,8 @@ pub const X86Cpu = enum {
692	692	.X87,
693	693	.Xsave,
694	694	.Xsaveopt,
695		},
696		CpuInfo(@This()).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
	695	}),
	696	CpuInfo(@This(), FeatureType).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
697	697	.Bit64,
698	698	.Sse,
699	699	.Avx,
...	...	@@ -730,8 +730,8 @@ pub const X86Cpu = enum {
730	730	.X87,
731	731	.Xsave,
732	732	.Xsaveopt,
733		},
734		CpuInfo(@This()).create(.Core2, "core2", &[_]FeatureType {
	733	}),
	734	CpuInfo(@This(), FeatureType).create(.Core2, "core2", &[_]FeatureType {
735	735	.Bit64,
736	736	.Cmov,
737	737	.Cx8,
...	...	@@ -745,8 +745,8 @@ pub const X86Cpu = enum {
745	745	.Ssse3,
746	746	.SlowUnalignedMem16,
747	747	.X87,
748		},
749		CpuInfo(@This()).create(.Corei7, "corei7", &[_]FeatureType {
	748	}),
	749	CpuInfo(@This(), FeatureType).create(.Corei7, "corei7", &[_]FeatureType {
750	750	.Bit64,
751	751	.Cmov,
752	752	.Cx8,
...	...	@@ -760,8 +760,8 @@ pub const X86Cpu = enum {
760	760	.Sse,
761	761	.Sse42,
762	762	.X87,
763		},
764		CpuInfo(@This()).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
	763	}),
	764	CpuInfo(@This(), FeatureType).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
765	765	.Bit64,
766	766	.Sse,
767	767	.Avx,
...	...	@@ -786,20 +786,20 @@ pub const X86Cpu = enum {
786	786	.X87,
787	787	.Xsave,
788	788	.Xsaveopt,
789		},
790		CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
	789	}),
	790	CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
791	791	.Cx8,
792	792	.SlowUnalignedMem16,
793	793	.X87,
794		},
795		CpuInfo(@This()).create(.Geode, "geode", &[_]FeatureType {
	794	}),
	795	CpuInfo(@This(), FeatureType).create(.Geode, "geode", &[_]FeatureType {
796	796	.Mmx,
797	797	.Dnowa3,
798	798	.Cx8,
799	799	.SlowUnalignedMem16,
800	800	.X87,
801		},
802		CpuInfo(@This()).create(.Goldmont, "goldmont", &[_]FeatureType {
	801	}),
	802	CpuInfo(@This(), FeatureType).create(.Goldmont, "goldmont", &[_]FeatureType {
803	803	.Bit64,
804	804	.Sse,
805	805	.Aes,
...	...	@@ -830,8 +830,8 @@ pub const X86Cpu = enum {
830	830	.Xsavec,
831	831	.Xsaveopt,
832	832	.Xsaves,
833		},
834		CpuInfo(@This()).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
	833	}),
	834	CpuInfo(@This(), FeatureType).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
835	835	.Bit64,
836	836	.Sse,
837	837	.Aes,
...	...	@@ -864,8 +864,8 @@ pub const X86Cpu = enum {
864	864	.Xsavec,
865	865	.Xsaveopt,
866	866	.Xsaves,
867		},
868		CpuInfo(@This()).create(.Haswell, "haswell", &[_]FeatureType {
	867	}),
	868	CpuInfo(@This(), FeatureType).create(.Haswell, "haswell", &[_]FeatureType {
869	869	.Bit64,
870	870	.Sse,
871	871	.Avx,
...	...	@@ -902,27 +902,27 @@ pub const X86Cpu = enum {
902	902	.X87,
903	903	.Xsave,
904	904	.Xsaveopt,
905		},
906		CpuInfo(@This()).create(.I386, "i386", &[_]FeatureType {
	905	}),
	906	CpuInfo(@This(), FeatureType).create(.I386, "i386", &[_]FeatureType {
907	907	.SlowUnalignedMem16,
908	908	.X87,
909		},
910		CpuInfo(@This()).create(.I486, "i486", &[_]FeatureType {
	909	}),
	910	CpuInfo(@This(), FeatureType).create(.I486, "i486", &[_]FeatureType {
911	911	.SlowUnalignedMem16,
912	912	.X87,
913		},
914		CpuInfo(@This()).create(.I586, "i586", &[_]FeatureType {
	913	}),
	914	CpuInfo(@This(), FeatureType).create(.I586, "i586", &[_]FeatureType {
915	915	.Cx8,
916	916	.SlowUnalignedMem16,
917	917	.X87,
918		},
919		CpuInfo(@This()).create(.I686, "i686", &[_]FeatureType {
	918	}),
	919	CpuInfo(@This(), FeatureType).create(.I686, "i686", &[_]FeatureType {
920	920	.Cmov,
921	921	.Cx8,
922	922	.SlowUnalignedMem16,
923	923	.X87,
924		},
925		CpuInfo(@This()).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
	924	}),
	925	CpuInfo(@This(), FeatureType).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
926	926	.Bit64,
927	927	.Adx,
928	928	.Sse,
...	...	@@ -986,8 +986,8 @@ pub const X86Cpu = enum {
986	986	.Xsavec,
987	987	.Xsaveopt,
988	988	.Xsaves,
989		},
990		CpuInfo(@This()).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
	989	}),
	990	CpuInfo(@This(), FeatureType).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
991	991	.Bit64,
992	992	.Adx,
993	993	.Sse,
...	...	@@ -1053,8 +1053,8 @@ pub const X86Cpu = enum {
1053	1053	.Xsavec,
1054	1054	.Xsaveopt,
1055	1055	.Xsaves,
1056		},
1057		CpuInfo(@This()).create(.Ivybridge, "ivybridge", &[_]FeatureType {
	1056	}),
	1057	CpuInfo(@This(), FeatureType).create(.Ivybridge, "ivybridge", &[_]FeatureType {
1058	1058	.Bit64,
1059	1059	.Sse,
1060	1060	.Avx,
...	...	@@ -1082,28 +1082,28 @@ pub const X86Cpu = enum {
1082	1082	.X87,
1083	1083	.Xsave,
1084	1084	.Xsaveopt,
1085		},
1086		CpuInfo(@This()).create(.K6, "k6", &[_]FeatureType {
	1085	}),
	1086	CpuInfo(@This(), FeatureType).create(.K6, "k6", &[_]FeatureType {
1087	1087	.Cx8,
1088	1088	.Mmx,
1089	1089	.SlowUnalignedMem16,
1090	1090	.X87,
1091		},
1092		CpuInfo(@This()).create(.K62, "k6-2", &[_]FeatureType {
	1091	}),
	1092	CpuInfo(@This(), FeatureType).create(.K62, "k6-2", &[_]FeatureType {
1093	1093	.Mmx,
1094	1094	.Dnow3,
1095	1095	.Cx8,
1096	1096	.SlowUnalignedMem16,
1097	1097	.X87,
1098		},
1099		CpuInfo(@This()).create(.K63, "k6-3", &[_]FeatureType {
	1098	}),
	1099	CpuInfo(@This(), FeatureType).create(.K63, "k6-3", &[_]FeatureType {
1100	1100	.Mmx,
1101	1101	.Dnow3,
1102	1102	.Cx8,
1103	1103	.SlowUnalignedMem16,
1104	1104	.X87,
1105		},
1106		CpuInfo(@This()).create(.K8, "k8", &[_]FeatureType {
	1105	}),
	1106	CpuInfo(@This(), FeatureType).create(.K8, "k8", &[_]FeatureType {
1107	1107	.Mmx,
1108	1108	.Dnowa3,
1109	1109	.Bit64,
...	...	@@ -1117,8 +1117,8 @@ pub const X86Cpu = enum {
1117	1117	.SlowShld,
1118	1118	.SlowUnalignedMem16,
1119	1119	.X87,
1120		},
1121		CpuInfo(@This()).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
	1120	}),
	1121	CpuInfo(@This(), FeatureType).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
1122	1122	.Mmx,
1123	1123	.Dnowa3,
1124	1124	.Bit64,
...	...	@@ -1133,8 +1133,8 @@ pub const X86Cpu = enum {
1133	1133	.SlowShld,
1134	1134	.SlowUnalignedMem16,
1135	1135	.X87,
1136		},
1137		CpuInfo(@This()).create(.Knl, "knl", &[_]FeatureType {
	1136	}),
	1137	CpuInfo(@This(), FeatureType).create(.Knl, "knl", &[_]FeatureType {
1138	1138	.Bit64,
1139	1139	.Adx,
1140	1140	.Sse,
...	...	@@ -1173,8 +1173,8 @@ pub const X86Cpu = enum {
1173	1173	.X87,
1174	1174	.Xsave,
1175	1175	.Xsaveopt,
1176		},
1177		CpuInfo(@This()).create(.Knm, "knm", &[_]FeatureType {
	1176	}),
	1177	CpuInfo(@This(), FeatureType).create(.Knm, "knm", &[_]FeatureType {
1178	1178	.Bit64,
1179	1179	.Adx,
1180	1180	.Sse,
...	...	@@ -1214,10 +1214,10 @@ pub const X86Cpu = enum {
1214	1214	.X87,
1215	1215	.Xsave,
1216	1216	.Xsaveopt,
1217		},
1218		CpuInfo(@This()).create(.Lakemont, "lakemont", &[_]FeatureType {
1219		},
1220		CpuInfo(@This()).create(.Nehalem, "nehalem", &[_]FeatureType {
	1217	}),
	1218	CpuInfo(@This(), FeatureType).create(.Lakemont, "lakemont", &[_]FeatureType {
	1219	}),
	1220	CpuInfo(@This(), FeatureType).create(.Nehalem, "nehalem", &[_]FeatureType {
1221	1221	.Bit64,
1222	1222	.Cmov,
1223	1223	.Cx8,
...	...	@@ -1231,8 +1231,8 @@ pub const X86Cpu = enum {
1231	1231	.Sse,
1232	1232	.Sse42,
1233	1233	.X87,
1234		},
1235		CpuInfo(@This()).create(.Nocona, "nocona", &[_]FeatureType {
	1234	}),
	1235	CpuInfo(@This(), FeatureType).create(.Nocona, "nocona", &[_]FeatureType {
1236	1236	.Bit64,
1237	1237	.Cmov,
1238	1238	.Cx8,
...	...	@@ -1244,8 +1244,8 @@ pub const X86Cpu = enum {
1244	1244	.Sse3,
1245	1245	.SlowUnalignedMem16,
1246	1246	.X87,
1247		},
1248		CpuInfo(@This()).create(.Opteron, "opteron", &[_]FeatureType {
	1247	}),
	1248	CpuInfo(@This(), FeatureType).create(.Opteron, "opteron", &[_]FeatureType {
1249	1249	.Mmx,
1250	1250	.Dnowa3,
1251	1251	.Bit64,
...	...	@@ -1259,8 +1259,8 @@ pub const X86Cpu = enum {
1259	1259	.SlowShld,
1260	1260	.SlowUnalignedMem16,
1261	1261	.X87,
1262		},
1263		CpuInfo(@This()).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
	1262	}),
	1263	CpuInfo(@This(), FeatureType).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
1264	1264	.Mmx,
1265	1265	.Dnowa3,
1266	1266	.Bit64,
...	...	@@ -1275,8 +1275,8 @@ pub const X86Cpu = enum {
1275	1275	.SlowShld,
1276	1276	.SlowUnalignedMem16,
1277	1277	.X87,
1278		},
1279		CpuInfo(@This()).create(.Penryn, "penryn", &[_]FeatureType {
	1278	}),
	1279	CpuInfo(@This(), FeatureType).create(.Penryn, "penryn", &[_]FeatureType {
1280	1280	.Bit64,
1281	1281	.Cmov,
1282	1282	.Cx8,
...	...	@@ -1290,13 +1290,13 @@ pub const X86Cpu = enum {
1290	1290	.Sse41,
1291	1291	.SlowUnalignedMem16,
1292	1292	.X87,
1293		},
1294		CpuInfo(@This()).create(.Pentium, "pentium", &[_]FeatureType {
	1293	}),
	1294	CpuInfo(@This(), FeatureType).create(.Pentium, "pentium", &[_]FeatureType {
1295	1295	.Cx8,
1296	1296	.SlowUnalignedMem16,
1297	1297	.X87,
1298		},
1299		CpuInfo(@This()).create(.PentiumM, "pentium-m", &[_]FeatureType {
	1298	}),
	1299	CpuInfo(@This(), FeatureType).create(.PentiumM, "pentium-m", &[_]FeatureType {
1300	1300	.Cmov,
1301	1301	.Cx8,
1302	1302	.Fxsr,
...	...	@@ -1306,14 +1306,14 @@ pub const X86Cpu = enum {
1306	1306	.Sse2,
1307	1307	.SlowUnalignedMem16,
1308	1308	.X87,
1309		},
1310		CpuInfo(@This()).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
	1309	}),
	1310	CpuInfo(@This(), FeatureType).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
1311	1311	.Cx8,
1312	1312	.Mmx,
1313	1313	.SlowUnalignedMem16,
1314	1314	.X87,
1315		},
1316		CpuInfo(@This()).create(.Pentium2, "pentium2", &[_]FeatureType {
	1315	}),
	1316	CpuInfo(@This(), FeatureType).create(.Pentium2, "pentium2", &[_]FeatureType {
1317	1317	.Cmov,
1318	1318	.Cx8,
1319	1319	.Fxsr,
...	...	@@ -1321,8 +1321,8 @@ pub const X86Cpu = enum {
1321	1321	.Nopl,
1322	1322	.SlowUnalignedMem16,
1323	1323	.X87,
1324		},
1325		CpuInfo(@This()).create(.Pentium3, "pentium3", &[_]FeatureType {
	1324	}),
	1325	CpuInfo(@This(), FeatureType).create(.Pentium3, "pentium3", &[_]FeatureType {
1326	1326	.Cmov,
1327	1327	.Cx8,
1328	1328	.Fxsr,
...	...	@@ -1331,8 +1331,8 @@ pub const X86Cpu = enum {
1331	1331	.Sse,
1332	1332	.SlowUnalignedMem16,
1333	1333	.X87,
1334		},
1335		CpuInfo(@This()).create(.Pentium3m, "pentium3m", &[_]FeatureType {
	1334	}),
	1335	CpuInfo(@This(), FeatureType).create(.Pentium3m, "pentium3m", &[_]FeatureType {
1336	1336	.Cmov,
1337	1337	.Cx8,
1338	1338	.Fxsr,
...	...	@@ -1341,8 +1341,8 @@ pub const X86Cpu = enum {
1341	1341	.Sse,
1342	1342	.SlowUnalignedMem16,
1343	1343	.X87,
1344		},
1345		CpuInfo(@This()).create(.Pentium4, "pentium4", &[_]FeatureType {
	1344	}),
	1345	CpuInfo(@This(), FeatureType).create(.Pentium4, "pentium4", &[_]FeatureType {
1346	1346	.Cmov,
1347	1347	.Cx8,
1348	1348	.Fxsr,
...	...	@@ -1352,8 +1352,8 @@ pub const X86Cpu = enum {
1352	1352	.Sse2,
1353	1353	.SlowUnalignedMem16,
1354	1354	.X87,
1355		},
1356		CpuInfo(@This()).create(.Pentium4m, "pentium4m", &[_]FeatureType {
	1355	}),
	1356	CpuInfo(@This(), FeatureType).create(.Pentium4m, "pentium4m", &[_]FeatureType {
1357	1357	.Cmov,
1358	1358	.Cx8,
1359	1359	.Fxsr,
...	...	@@ -1363,15 +1363,15 @@ pub const X86Cpu = enum {
1363	1363	.Sse2,
1364	1364	.SlowUnalignedMem16,
1365	1365	.X87,
1366		},
1367		CpuInfo(@This()).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
	1366	}),
	1367	CpuInfo(@This(), FeatureType).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
1368	1368	.Cmov,
1369	1369	.Cx8,
1370	1370	.Nopl,
1371	1371	.SlowUnalignedMem16,
1372	1372	.X87,
1373		},
1374		CpuInfo(@This()).create(.Prescott, "prescott", &[_]FeatureType {
	1373	}),
	1374	CpuInfo(@This(), FeatureType).create(.Prescott, "prescott", &[_]FeatureType {
1375	1375	.Cmov,
1376	1376	.Cx8,
1377	1377	.Fxsr,
...	...	@@ -1381,8 +1381,8 @@ pub const X86Cpu = enum {
1381	1381	.Sse3,
1382	1382	.SlowUnalignedMem16,
1383	1383	.X87,
1384		},
1385		CpuInfo(@This()).create(.Sandybridge, "sandybridge", &[_]FeatureType {
	1384	}),
	1385	CpuInfo(@This(), FeatureType).create(.Sandybridge, "sandybridge", &[_]FeatureType {
1386	1386	.Bit64,
1387	1387	.Sse,
1388	1388	.Avx,
...	...	@@ -1407,8 +1407,8 @@ pub const X86Cpu = enum {
1407	1407	.X87,
1408	1408	.Xsave,
1409	1409	.Xsaveopt,
1410		},
1411		CpuInfo(@This()).create(.Silvermont, "silvermont", &[_]FeatureType {
	1410	}),
	1411	CpuInfo(@This(), FeatureType).create(.Silvermont, "silvermont", &[_]FeatureType {
1412	1412	.Bit64,
1413	1413	.Cmov,
1414	1414	.Cx8,
...	...	@@ -1432,8 +1432,8 @@ pub const X86Cpu = enum {
1432	1432	.SlowPmulld,
1433	1433	.SlowTwoMemOps,
1434	1434	.X87,
1435		},
1436		CpuInfo(@This()).create(.Skx, "skx", &[_]FeatureType {
	1435	}),
	1436	CpuInfo(@This(), FeatureType).create(.Skx, "skx", &[_]FeatureType {
1437	1437	.Bit64,
1438	1438	.Adx,
1439	1439	.Sse,
...	...	@@ -1486,8 +1486,8 @@ pub const X86Cpu = enum {
1486	1486	.Xsavec,
1487	1487	.Xsaveopt,
1488	1488	.Xsaves,
1489		},
1490		CpuInfo(@This()).create(.Skylake, "skylake", &[_]FeatureType {
	1489	}),
	1490	CpuInfo(@This(), FeatureType).create(.Skylake, "skylake", &[_]FeatureType {
1491	1491	.Bit64,
1492	1492	.Adx,
1493	1493	.Sse,
...	...	@@ -1533,8 +1533,8 @@ pub const X86Cpu = enum {
1533	1533	.Xsavec,
1534	1534	.Xsaveopt,
1535	1535	.Xsaves,
1536		},
1537		CpuInfo(@This()).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
	1536	}),
	1537	CpuInfo(@This(), FeatureType).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
1538	1538	.Bit64,
1539	1539	.Adx,
1540	1540	.Sse,
...	...	@@ -1587,8 +1587,8 @@ pub const X86Cpu = enum {
1587	1587	.Xsavec,
1588	1588	.Xsaveopt,
1589	1589	.Xsaves,
1590		},
1591		CpuInfo(@This()).create(.Slm, "slm", &[_]FeatureType {
	1590	}),
	1591	CpuInfo(@This(), FeatureType).create(.Slm, "slm", &[_]FeatureType {
1592	1592	.Bit64,
1593	1593	.Cmov,
1594	1594	.Cx8,
...	...	@@ -1612,8 +1612,8 @@ pub const X86Cpu = enum {
1612	1612	.SlowPmulld,
1613	1613	.SlowTwoMemOps,
1614	1614	.X87,
1615		},
1616		CpuInfo(@This()).create(.Tigerlake, "tigerlake", &[_]FeatureType {
	1615	}),
	1616	CpuInfo(@This(), FeatureType).create(.Tigerlake, "tigerlake", &[_]FeatureType {
1617	1617	.Bit64,
1618	1618	.Adx,
1619	1619	.Sse,
...	...	@@ -1681,8 +1681,8 @@ pub const X86Cpu = enum {
1681	1681	.Xsavec,
1682	1682	.Xsaveopt,
1683	1683	.Xsaves,
1684		},
1685		CpuInfo(@This()).create(.Tremont, "tremont", &[_]FeatureType {
	1684	}),
	1685	CpuInfo(@This(), FeatureType).create(.Tremont, "tremont", &[_]FeatureType {
1686	1686	.Bit64,
1687	1687	.Sse,
1688	1688	.Aes,
...	...	@@ -1720,8 +1720,8 @@ pub const X86Cpu = enum {
1720	1720	.Xsavec,
1721	1721	.Xsaveopt,
1722	1722	.Xsaves,
1723		},
1724		CpuInfo(@This()).create(.Westmere, "westmere", &[_]FeatureType {
	1723	}),
	1724	CpuInfo(@This(), FeatureType).create(.Westmere, "westmere", &[_]FeatureType {
1725	1725	.Bit64,
1726	1726	.Cmov,
1727	1727	.Cx8,
...	...	@@ -1736,19 +1736,19 @@ pub const X86Cpu = enum {
1736	1736	.Popcnt,
1737	1737	.Sse42,
1738	1738	.X87,
1739		},
1740		CpuInfo(@This()).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
	1739	}),
	1740	CpuInfo(@This(), FeatureType).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
1741	1741	.Mmx,
1742	1742	.SlowUnalignedMem16,
1743	1743	.X87,
1744		},
1745		CpuInfo(@This()).create(.Winchip2, "winchip2", &[_]FeatureType {
	1744	}),
	1745	CpuInfo(@This(), FeatureType).create(.Winchip2, "winchip2", &[_]FeatureType {
1746	1746	.Mmx,
1747	1747	.Dnow3,
1748	1748	.SlowUnalignedMem16,
1749	1749	.X87,
1750		},
1751		CpuInfo(@This()).create(.X8664, "x86-64", &[_]FeatureType {
	1750	}),
	1751	CpuInfo(@This(), FeatureType).create(.X8664, "x86-64", &[_]FeatureType {
1752	1752	.Bit64,
1753	1753	.Cmov,
1754	1754	.Cx8,
...	...	@@ -1761,8 +1761,8 @@ pub const X86Cpu = enum {
1761	1761	.Slow3opsLea,
1762	1762	.SlowIncdec,
1763	1763	.X87,
1764		},
1765		CpuInfo(@This()).create(.Yonah, "yonah", &[_]FeatureType {
	1764	}),
	1765	CpuInfo(@This(), FeatureType).create(.Yonah, "yonah", &[_]FeatureType {
1766	1766	.Cmov,
1767	1767	.Cx8,
1768	1768	.Fxsr,
...	...	@@ -1772,8 +1772,8 @@ pub const X86Cpu = enum {
1772	1772	.Sse3,
1773	1773	.SlowUnalignedMem16,
1774	1774	.X87,
1775		},
1776		CpuInfo(@This()).create(.Znver1, "znver1", &[_]FeatureType {
	1775	}),
	1776	CpuInfo(@This(), FeatureType).create(.Znver1, "znver1", &[_]FeatureType {
1777	1777	.Bit64,
1778	1778	.Adx,
1779	1779	.Sse,
...	...	@@ -1814,8 +1814,8 @@ pub const X86Cpu = enum {
1814	1814	.Xsavec,
1815	1815	.Xsaveopt,
1816	1816	.Xsaves,
1817		},
1818		CpuInfo(@This()).create(.Znver2, "znver2", &[_]FeatureType {
	1817	}),
	1818	CpuInfo(@This(), FeatureType).create(.Znver2, "znver2", &[_]FeatureType {
1819	1819	.Bit64,
1820	1820	.Adx,
1821	1821	.Sse,
...	...	@@ -1859,6 +1859,6 @@ pub const X86Cpu = enum {
1859	1859	.Xsavec,
1860	1860	.Xsaveopt,
1861	1861	.Xsaves,
1862		},
	1862	}),
1863	1863	};
1864	1864	};

lib/std/target/cpu/empty.zig+2-2

...	...	@@ -1,6 +1,6 @@
1	1	const feature = @import("std").target.feature;
2	2	const CpuInfo = @import("std").target.cpu.CpuInfo;
3	3
4		pub const EmptyCpu = enum {
5		pub const cpu_infos = [0]CpuInfo(@This()) {};
	4	pub const EmptyCpu = struct {
	5	pub const cpu_infos = [0]CpuInfo(@This(), feature.EmptyFeature) {};
6	6	};

lib/std/target/feature.zig+9-3

...	...	@@ -17,7 +17,7 @@ pub const SystemZFeature = @import("feature/SystemZFeature.zig").SystemZFeature;
17	17	pub const WebAssemblyFeature = @import("feature/WebAssemblyFeature.zig").WebAssemblyFeature;
18	18	pub const X86Feature = @import("feature/X86Feature.zig").X86Feature;
19	19
20		const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
	20	pub const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
21	21
22	22	pub fn ArchFeature(comptime arch: @TagType(Arch)) type {
23	23	return switch (arch) {
...	...	@@ -49,24 +49,30 @@ pub fn FeatureInfo(comptime EnumType: type) type {
49	49	return struct {
50	50	value: EnumType,
51	51	name: []const u8,
	52	description: []const u8,
	53	llvm_name: []const u8,
52	54
53	55	subfeatures: []const EnumType,
54	56
55	57	const Self = @This();
56	58
57		fn create(value: EnumType, name: []const u8) Self {
	59	pub fn create(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8) Self {
58	60	return Self {
59	61	.value = value,
60	62	.name = name,
	63	.description = description,
	64	.llvm_name = llvm_name,
61	65
62	66	.subfeatures = &[_]EnumType{},
63	67	};
64	68	}
65	69
66		fn createWithSubfeatures(value: EnumType, name: []const u8, subfeatures: []const EnumType) Self {
	70	pub fn createWithSubfeatures(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8, subfeatures: []const EnumType) Self {
67	71	return Self {
68	72	.value = value,
69	73	.name = name,
	74	.description = description,
	75	.llvm_name = llvm_name,
70	76
71	77	.subfeatures = subfeatures,
72	78	};

lib/std/target/feature/AArch64Feature.zig+213-213

...	...	@@ -155,7 +155,7 @@ pub const AArch64Feature = enum {
155	155	Thunderxt83,
156	156	Thunderxt88,
157	157
158		pub fn getInfo(self: @This()) FeatureInfo {
	158	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
159	159	return feature_infos[@enumToInt(self)];
160	160	}
161	161
...	...	@@ -291,19 +291,19 @@ pub const AArch64Feature = enum {
291	291	.Sve,
292	292	}),
293	293	FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
294		.Sve,
295	294	.FpArmv8,
	295	.Sve,
296	296	}),
297	297	FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
298	298	.Sve,
299	299	}),
300	300	FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
301		.Sve,
302	301	.FpArmv8,
	302	.Sve,
303	303	}),
304	304	FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
305		.Sve,
306	305	.FpArmv8,
	306	.Sve,
307	307	}),
308	308	FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
309	309	FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
...	...	@@ -323,101 +323,101 @@ pub const AArch64Feature = enum {
323	323	FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
324	324	FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
325	325	FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
326		.ZczFp,
327	326	.ZczGp,
	327	.ZczFp,
328	328	}),
329	329	FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
330	330	FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
331	331	FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
332	332	FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
333		.Pan,
334		.Rdm,
335	333	.Lse,
	334	.Rdm,
336	335	.Crc,
337	336	.Lor,
	337	.Pan,
338	338	.Vh,
339	339	}),
340	340	FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
341		.Ccpp,
342		.Pan,
343		.Rdm,
344	341	.Lse,
	342	.Rdm,
	343	.Pan,
345	344	.Crc,
346	345	.Lor,
347	346	.Uaops,
348		.Vh,
349	347	.Ras,
	348	.Ccpp,
	349	.Vh,
350	350	}),
351	351	FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
352		.Rcpc,
353		.Ccpp,
354		.Pan,
355		.Rdm,
356		.FpArmv8,
357	352	.Lse,
358		.Ccidx,
	353	.Vh,
	354	.Pa,
	355	.Rdm,
	356	.Pan,
359	357	.Crc,
360	358	.Lor,
361		.Pa,
362	359	.Uaops,
363		.Vh,
364	360	.Ras,
	361	.Rcpc,
	362	.Ccpp,
	363	.Ccidx,
	364	.FpArmv8,
365	365	}),
366	366	FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
367		.Nv,
	367	.Rdm,
	368	.Dit,
368	369	.Am,
369		.Lse,
	370	.Ras,
	371	.Rcpc,
370	372	.Sel2,
371		.Lor,
372		.Tracev84,
373		.Uaops,
374	373	.Ccpp,
375		.TlbRmi,
376		.Fmi,
377		.Rcpc,
378		.Pan,
379		.Rdm,
380	374	.Pa,
381		.Dit,
382		.Ras,
	375	.Pan,
	376	.Uaops,
	377	.Tracev84,
383	378	.Mpam,
384		.FpArmv8,
385		.Ccidx,
	379	.Lse,
	380	.Nv,
386	381	.Dotprod,
	382	.TlbRmi,
	383	.Lor,
	384	.Ccidx,
	385	.FpArmv8,
387	386	.Crc,
	387	.Fmi,
388	388	.Vh,
389	389	}),
390	390	FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
391		.Nv,
	391	.Vh,
	392	.Rdm,
	393	.Dit,
392	394	.Am,
393		.Lse,
394		.Fptoint,
	395	.Ssbs,
	396	.Specrestrict,
	397	.Ras,
	398	.Rcpc,
395	399	.Sel2,
396		.Lor,
397		.Tracev84,
398		.Uaops,
399		.Sb,
400	400	.Ccpp,
401		.Specrestrict,
	401	.Pa,
402	402	.Bti,
403	403	.Ccdp,
404		.TlbRmi,
405		.Fmi,
406		.Rcpc,
407	404	.Pan,
408		.Rdm,
409		.Pa,
410		.Ssbs,
411		.Dit,
412		.Ras,
	405	.Uaops,
	406	.Tracev84,
413	407	.Mpam,
	408	.Lse,
	409	.Sb,
	410	.Nv,
414	411	.Altnzcv,
415		.FpArmv8,
416		.Ccidx,
417	412	.Dotprod,
418		.Crc,
	413	.TlbRmi,
	414	.Lor,
	415	.Ccidx,
419	416	.Predres,
420		.Vh,
	417	.Crc,
	418	.Fptoint,
	419	.Fmi,
	420	.FpArmv8,
421	421	}),
422	422	FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
423	423	.Perfmon,
...	...	@@ -425,325 +425,325 @@ pub const AArch64Feature = enum {
425	425	.Crc,
426	426	}),
427	427	FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
428		.UseAa,
429		.FuseAes,
430		.FpArmv8,
431	428	.Perfmon,
432		.Crc,
433		.BalanceFpOps,
434	429	.UsePostraScheduler,
	430	.Crc,
435	431	.CustomCheapAsMove,
	432	.BalanceFpOps,
	433	.UseAa,
	434	.FpArmv8,
	435	.FuseAes,
436	436	}),
437	437	FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
438		.Rcpc,
439		.Ccpp,
440		.Pan,
	438	.Lse,
	439	.Vh,
441	440	.Rdm,
442		.FuseAes,
443	441	.Perfmon,
444		.FpArmv8,
445		.Lse,
446		.Crc,
	442	.Pan,
447	443	.Dotprod,
	444	.Crc,
448	445	.Lor,
449	446	.Uaops,
450		.Vh,
451	447	.Ras,
	448	.Rcpc,
	449	.Ccpp,
	450	.FpArmv8,
	451	.FuseAes,
452	452	}),
453	453	FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
454		.FuseLiterals,
455		.FuseAes,
456		.FpArmv8,
457	454	.Perfmon,
458		.Crc,
459		.BalanceFpOps,
460	455	.UsePostraScheduler,
461		.CustomCheapAsMove,
	456	.Crc,
462	457	.PredictableSelectExpensive,
	458	.CustomCheapAsMove,
	459	.BalanceFpOps,
	460	.FuseLiterals,
	461	.FpArmv8,
	462	.FuseAes,
463	463	}),
464	464	FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
465		.Rcpc,
466		.Ccpp,
467		.Pan,
468		.Rdm,
469		.FpArmv8,
470	465	.Lse,
471		.Crc,
	466	.Vh,
	467	.Rdm,
	468	.Pan,
472	469	.Dotprod,
473		.Lor,
	470	.Crc,
474	471	.Ssbs,
	472	.Lor,
475	473	.Uaops,
476		.Vh,
477	474	.Ras,
	475	.Rcpc,
	476	.Ccpp,
	477	.FpArmv8,
478	478	}),
479	479	FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
480	480	.Perfmon,
481		.FuseAes,
482	481	.FpArmv8,
483	482	.Crc,
	483	.FuseAes,
484	484	}),
485	485	FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
486	486	.Perfmon,
487		.FuseAes,
488	487	.FpArmv8,
489	488	.Crc,
	489	.FuseAes,
490	490	}),
491	491	FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
492		.Rcpc,
493		.Ccpp,
494		.Pan,
	492	.Lse,
	493	.Vh,
495	494	.Rdm,
496		.FuseAes,
497	495	.Perfmon,
498		.FpArmv8,
499		.Lse,
500		.Crc,
	496	.Pan,
501	497	.Dotprod,
	498	.Crc,
502	499	.Lor,
503	500	.Uaops,
504		.Vh,
505	501	.Ras,
506		}),
507		FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
508	502	.Rcpc,
509	503	.Ccpp,
510		.Pan,
511		.Rdm,
512	504	.FpArmv8,
	505	.FuseAes,
	506	}),
	507	FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
513	508	.Lse,
514		.Crc,
	509	.Vh,
	510	.Rdm,
	511	.Pan,
515	512	.Dotprod,
516		.Lor,
	513	.Crc,
517	514	.Ssbs,
	515	.Lor,
518	516	.Uaops,
519		.Vh,
520	517	.Ras,
	518	.Rcpc,
	519	.Ccpp,
	520	.FpArmv8,
521	521	}),
522	522	FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
523		.ZczFp,
	523	.ArithBccFusion,
524	524	.ArithCbzFusion,
525		.FuseAes,
	525	.ZczFp,
526	526	.AlternateSextloadCvtF32Pattern,
527		.ZczFpWorkaround,
528		.FpArmv8,
529		.Perfmon,
530	527	.DisableLatencySchedHeuristic,
531		.Zcm,
	528	.Perfmon,
532	529	.ZczGp,
533		.ArithBccFusion,
	530	.ZczFpWorkaround,
	531	.Zcm,
	532	.FpArmv8,
534	533	.FuseCryptoEor,
	534	.FuseAes,
535	535	}),
536	536	FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
537	537	.ZczFp,
538		.FuseAes,
539		.SlowPaired128,
540		.Force32bitJumpTables,
541		.UseReciprocalSquareRoot,
542		.FpArmv8,
543	538	.Perfmon,
544		.SlowMisaligned128store,
545		.Crc,
546	539	.UsePostraScheduler,
	540	.Crc,
	541	.UseReciprocalSquareRoot,
547	542	.CustomCheapAsMove,
	543	.Force32bitJumpTables,
	544	.SlowMisaligned128store,
	545	.FpArmv8,
	546	.SlowPaired128,
	547	.FuseAes,
548	548	}),
549	549	FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
550	550	.ZczFp,
551		.FuseAes,
552		.SlowPaired128,
553		.Force32bitJumpTables,
554		.FpArmv8,
555	551	.Perfmon,
556		.SlowMisaligned128store,
557		.Crc,
558	552	.UsePostraScheduler,
	553	.Crc,
559	554	.CustomCheapAsMove,
	555	.Force32bitJumpTables,
	556	.SlowMisaligned128store,
	557	.FpArmv8,
	558	.SlowPaired128,
	559	.FuseAes,
560	560	}),
561	561	FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
	562	.FuseCsel,
562	563	.ZczFp,
563		.FuseLiterals,
564		.FuseAes,
565		.Force32bitJumpTables,
566		.FpArmv8,
567	564	.Perfmon,
568		.Crc,
569		.LslFast,
570		.FuseAddress,
571	565	.UsePostraScheduler,
572		.CustomCheapAsMove,
	566	.Crc,
573	567	.PredictableSelectExpensive,
574		.FuseCsel,
	568	.CustomCheapAsMove,
	569	.Force32bitJumpTables,
	570	.FuseLiterals,
	571	.FuseAddress,
	572	.LslFast,
	573	.FpArmv8,
	574	.FuseAes,
575	575	}),
576	576	FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
	577	.ArithBccFusion,
	578	.Vh,
	579	.ArithCbzFusion,
577	580	.ZczFp,
578		.Lse,
579		.FuseArithLogic,
580		.Lor,
	581	.Rdm,
581	582	.UsePostraScheduler,
582		.Uaops,
583		.CustomCheapAsMove,
584		.ArithBccFusion,
	583	.Ras,
	584	.Force32bitJumpTables,
585	585	.Ccpp,
586		.Perfmon,
	586	.FuseCsel,
587	587	.Pan,
588		.Rdm,
	588	.Uaops,
589	589	.FuseLiterals,
590		.Force32bitJumpTables,
591	590	.LslFast,
	591	.Lse,
	592	.Perfmon,
	593	.Dotprod,
	594	.Lor,
	595	.FuseArithLogic,
	596	.Crc,
	597	.CustomCheapAsMove,
592	598	.FuseAddress,
593	599	.ZczGp,
594		.Ras,
595		.FuseCsel,
596		.ArithCbzFusion,
597		.FuseAes,
598	600	.FpArmv8,
599		.Crc,
600		.Dotprod,
601		.Vh,
	601	.FuseAes,
602	602	}),
603	603	FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
604	604	.ZczFp,
605	605	.Rdm,
606		.SlowStrqroStore,
607	606	.Perfmon,
608		.FpArmv8,
609		.Crc,
610		.LslFast,
611	607	.UsePostraScheduler,
612		.ZczGp,
613		.CustomCheapAsMove,
	608	.Crc,
614	609	.PredictableSelectExpensive,
	610	.CustomCheapAsMove,
	611	.ZczGp,
	612	.FpArmv8,
	613	.SlowStrqroStore,
	614	.LslFast,
615	615	}),
616	616	FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
617	617	.ZczFp,
618	618	.Perfmon,
619		.FpArmv8,
620		.Crc,
621		.LslFast,
622	619	.UsePostraScheduler,
623		.ZczGp,
624		.CustomCheapAsMove,
	620	.Crc,
625	621	.PredictableSelectExpensive,
	622	.CustomCheapAsMove,
	623	.ZczGp,
	624	.FpArmv8,
	625	.LslFast,
626	626	}),
627	627	FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
628		.Rcpc,
629		.Ccpp,
630		.Pan,
631		.Rdm,
632		.FpArmv8,
633	628	.Lse,
634		.Crc,
	629	.Vh,
	630	.Rdm,
	631	.Pan,
635	632	.Dotprod,
636		.Lor,
	633	.Crc,
637	634	.Ssbs,
	635	.Lor,
638	636	.Uaops,
639		.Vh,
640	637	.Ras,
641		}),
642		FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
643	638	.Rcpc,
644		.Spe,
645	639	.Ccpp,
646		.Pan,
647		.Rdm,
648	640	.FpArmv8,
	641	}),
	642	FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
649	643	.Lse,
650		.Crc,
	644	.Spe,
	645	.Vh,
	646	.Rdm,
	647	.Pan,
651	648	.Dotprod,
652		.Lor,
	649	.Crc,
653	650	.Ssbs,
	651	.Lor,
654	652	.Uaops,
655		.Vh,
656	653	.Ras,
	654	.Rcpc,
	655	.Ccpp,
	656	.FpArmv8,
657	657	}),
658	658	FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
	659	.Spe,
	660	.Vh,
659	661	.ZczFp,
660		.Nv,
	662	.Rdm,
	663	.UsePostraScheduler,
	664	.Dit,
661	665	.Am,
662		.Lse,
	666	.Ras,
	667	.Rcpc,
663	668	.Sel2,
664		.Lor,
665		.Tracev84,
666		.Uaops,
667		.UsePostraScheduler,
668		.CustomCheapAsMove,
669	669	.Ccpp,
	670	.Pa,
	671	.Pan,
	672	.Uaops,
	673	.Tracev84,
	674	.Mpam,
	675	.LslFast,
	676	.Lse,
	677	.Nv,
670	678	.Perfmon,
	679	.Dotprod,
671	680	.TlbRmi,
	681	.Lor,
	682	.Ccidx,
672	683	.PredictableSelectExpensive,
	684	.Crc,
	685	.CustomCheapAsMove,
673	686	.Fmi,
674		.Rcpc,
675		.Pan,
676		.Rdm,
677		.LslFast,
678		.Pa,
679	687	.ZczGp,
680		.Dit,
681		.Ras,
682		.Spe,
683		.Mpam,
684	688	.FpArmv8,
685		.Ccidx,
686		.Dotprod,
687		.Crc,
688		.Vh,
689	689	}),
690	690	FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
691		.Uaops,
	691	.Lse,
692	692	.Spe,
693		.Ccpp,
694		.Pan,
695		.Rdm,
696		.FuseAes,
697	693	.Vh,
	694	.Rdm,
698	695	.Perfmon,
699		.FpArmv8,
700		.Lse,
701		.Crc,
	696	.UsePostraScheduler,
	697	.Pan,
702	698	.Dotprod,
	699	.Crc,
703	700	.Lor,
704		.UsePostraScheduler,
	701	.Uaops,
705	702	.CustomCheapAsMove,
706	703	.Ras,
	704	.Ccpp,
	705	.FpArmv8,
	706	.FuseAes,
707	707	}),
708	708	FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
709	709	.Perfmon,
710		.FpArmv8,
711		.Crc,
712	710	.UsePostraScheduler,
	711	.Crc,
	712	.FpArmv8,
713	713	.PredictableSelectExpensive,
714	714	}),
715	715	FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
716		.Pan,
717		.Rdm,
718		.Vh,
719		.AggressiveFma,
720		.FpArmv8,
721	716	.Lse,
	717	.ArithBccFusion,
	718	.Vh,
	719	.Rdm,
	720	.UsePostraScheduler,
722	721	.Crc,
723	722	.Lor,
724		.UsePostraScheduler,
725		.ArithBccFusion,
	723	.Pan,
	724	.AggressiveFma,
	725	.FpArmv8,
726	726	.PredictableSelectExpensive,
727	727	}),
728	728	FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
729	729	.Perfmon,
730		.FpArmv8,
731		.Crc,
732	730	.UsePostraScheduler,
	731	.Crc,
	732	.FpArmv8,
733	733	.PredictableSelectExpensive,
734	734	}),
735	735	FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
736	736	.Perfmon,
737		.FpArmv8,
738		.Crc,
739	737	.UsePostraScheduler,
	738	.Crc,
	739	.FpArmv8,
740	740	.PredictableSelectExpensive,
741	741	}),
742	742	FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
743	743	.Perfmon,
744		.FpArmv8,
745		.Crc,
746	744	.UsePostraScheduler,
	745	.Crc,
	746	.FpArmv8,
747	747	.PredictableSelectExpensive,
748	748	}),
749	749	};

lib/std/target/feature/AmdGpuFeature.zig+72-72

...	...	@@ -110,7 +110,7 @@ pub const AmdGpuFeature = enum {
110	110	Xnack,
111	111	HalfRate64Ops,
112	112
113		pub fn getInfo(self: @This()) FeatureInfo {
	113	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
114	114	return feature_infos[@enumToInt(self)];
115	115	}
116	116
...	...	@@ -166,73 +166,73 @@ pub const AmdGpuFeature = enum {
166	166	FeatureInfo(@This()).create(.Gfx7Gfx8Gfx9Insts, "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", "gfx7-gfx8-gfx9-insts"),
167	167	FeatureInfo(@This()).create(.Gfx8Insts, "gfx8-insts", "Additional instructions for GFX8+", "gfx8-insts"),
168	168	FeatureInfo(@This()).createWithSubfeatures(.Gfx9, "gfx9", "GFX9 GPU generation", "gfx9", &[_]@This() {
169		.Gfx9Insts,
170		.Wavefrontsize64,
171		.Fp64,
172		.Gcn3Encoding,
173		.FastFmaf,
174		.Sdwa,
	169	.ApertureRegs,
	170	.IntClampInsts,
	171	.SdwaOmod,
175	172	.SdwaScalar,
176		.VgprIndexMode,
177		.Dpp,
178	173	.AddNoCarryInsts,
179		.SdwaOmod,
180		.SdwaSdst,
181	174	.ScalarAtomics,
	175	.SMemrealtime,
	176	.Gcn3Encoding,
	177	.CiInsts,
182	178	.FlatAddressSpace,
183		.ScalarFlatScratchInsts,
184		.Gfx8Insts,
	179	.Sdwa,
	180	.Wavefrontsize64,
	181	.SdwaSdst,
	182	.FlatInstOffsets,
	183	.ScalarStores,
185	184	.Gfx7Gfx8Gfx9Insts,
186	185	.R128A16,
187		.IntClampInsts,
188		.ScalarStores,
189		.ApertureRegs,
190		.CiInsts,
191		.FlatGlobalInsts,
192		.BitInsts16,
193		.FlatScratchInsts,
194		.SMemrealtime,
	186	.Dpp,
	187	.Localmemorysize65536,
195	188	.Vop3p,
196		.FlatInstOffsets,
	189	.BitInsts16,
	190	.VgprIndexMode,
	191	.Gfx8Insts,
197	192	.Inv2piInlineImm,
198		.Localmemorysize65536,
199		}),
200		FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
201		FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
202	193	.Gfx9Insts,
203		.NoSdstCmpx,
	194	.ScalarFlatScratchInsts,
	195	.FlatGlobalInsts,
	196	.FlatScratchInsts,
204	197	.Fp64,
205	198	.FastFmaf,
206		.Sdwa,
207		.SdwaScalar,
208		.Dpp,
209		.RegisterBanking,
	199	}),
	200	FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
	201	FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
	202	.Vscnt,
	203	.ApertureRegs,
210	204	.Gfx10Insts,
211		.AddNoCarryInsts,
	205	.IntClampInsts,
	206	.PkFmacF16Inst,
212	207	.SdwaOmod,
213		.SdwaSdst,
	208	.SdwaScalar,
	209	.AddNoCarryInsts,
	210	.Movrel,
	211	.SMemrealtime,
	212	.NoSdstCmpx,
	213	.CiInsts,
214	214	.FlatAddressSpace,
	215	.Sdwa,
	216	.NoSramEccSupport,
	217	.SdwaSdst,
	218	.FlatInstOffsets,
	219	.RegisterBanking,
	220	.Dpp,
	221	.Localmemorysize65536,
	222	.Vop3p,
	223	.BitInsts16,
	224	.Dpp8,
215	225	.Gfx8Insts,
	226	.Inv2piInlineImm,
	227	.Gfx9Insts,
216	228	.FmaMixInsts,
217		.PkFmacF16Inst,
218		.Vop3Literal,
219	229	.MimgR128,
220		.NoSramEccSupport,
221		.IntClampInsts,
222		.Movrel,
223		.Dpp8,
224		.ApertureRegs,
225		.NoDataDepHazard,
226		.CiInsts,
	230	.Vop3Literal,
227	231	.FlatGlobalInsts,
228		.BitInsts16,
229	232	.FlatScratchInsts,
230		.SMemrealtime,
231		.Vop3p,
232		.FlatInstOffsets,
233		.Inv2piInlineImm,
234		.Localmemorysize65536,
235		.Vscnt,
	233	.Fp64,
	234	.FastFmaf,
	235	.NoDataDepHazard,
236	236	}),
237	237	FeatureInfo(@This()).create(.Gfx10Insts, "gfx10-insts", "Additional instructions for GFX10+", "gfx10-insts"),
238	238	FeatureInfo(@This()).create(.InstFwdPrefetchBug, "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", "inst-fwd-prefetch-bug"),
...	...	@@ -276,25 +276,25 @@ pub const AmdGpuFeature = enum {
276	276	FeatureInfo(@This()).create(.ScalarFlatScratchInsts, "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", "scalar-flat-scratch-insts"),
277	277	FeatureInfo(@This()).create(.ScalarStores, "scalar-stores", "Has store scalar memory instructions", "scalar-stores"),
278	278	FeatureInfo(@This()).createWithSubfeatures(.SeaIslands, "sea-islands", "SEA_ISLANDS GPU generation", "sea-islands", &[_]@This() {
279		.Wavefrontsize64,
280		.MimgR128,
	279	.Movrel,
	280	.Gfx7Gfx8Gfx9Insts,
281	281	.Fp64,
	282	.TrigReducedRange,
282	283	.CiInsts,
283	284	.FlatAddressSpace,
284		.TrigReducedRange,
285		.NoSramEccSupport,
286		.Movrel,
287	285	.Localmemorysize65536,
288		.Gfx7Gfx8Gfx9Insts,
	286	.Wavefrontsize64,
	287	.NoSramEccSupport,
	288	.MimgR128,
289	289	}),
290	290	FeatureInfo(@This()).createWithSubfeatures(.SouthernIslands, "southern-islands", "SOUTHERN_ISLANDS GPU generation", "southern-islands", &[_]@This() {
291		.Wavefrontsize64,
	291	.Movrel,
292	292	.MimgR128,
293	293	.Fp64,
294		.NoXnackSupport,
295	294	.TrigReducedRange,
	295	.NoXnackSupport,
	296	.Wavefrontsize64,
296	297	.NoSramEccSupport,
297		.Movrel,
298	298	.Ldsbankcount32,
299	299	.Localmemorysize32768,
300	300	}),
...	...	@@ -310,28 +310,28 @@ pub const AmdGpuFeature = enum {
310	310	FeatureInfo(@This()).create(.VcmpxExecWarHazard, "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", "vcmpx-exec-war-hazard"),
311	311	FeatureInfo(@This()).create(.VcmpxPermlaneHazard, "vcmpx-permlane-hazard", "TODO: describe me", "vcmpx-permlane-hazard"),
312	312	FeatureInfo(@This()).createWithSubfeatures(.VolcanicIslands, "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", "volcanic-islands", &[_]@This() {
313		.Wavefrontsize64,
314		.Fp64,
	313	.IntClampInsts,
	314	.SdwaMav,
	315	.Movrel,
	316	.SMemrealtime,
315	317	.Gcn3Encoding,
316	318	.TrigReducedRange,
317		.Sdwa,
318		.VgprIndexMode,
319		.Dpp,
	319	.CiInsts,
320	320	.FlatAddressSpace,
321		.Gfx8Insts,
322		.Gfx7Gfx8Gfx9Insts,
323		.MimgR128,
	321	.Sdwa,
	322	.Wavefrontsize64,
324	323	.NoSramEccSupport,
325		.IntClampInsts,
326	324	.ScalarStores,
327		.Movrel,
328		.SdwaMav,
329		.CiInsts,
	325	.Gfx7Gfx8Gfx9Insts,
	326	.Dpp,
	327	.Localmemorysize65536,
330	328	.BitInsts16,
331		.SMemrealtime,
	329	.VgprIndexMode,
	330	.Gfx8Insts,
332	331	.Inv2piInlineImm,
333		.Localmemorysize65536,
	332	.MimgR128,
334	333	.SdwaOutModsVopc,
	334	.Fp64,
335	335	}),
336	336	FeatureInfo(@This()).create(.Vscnt, "vscnt", "Has separate store vscnt counter", "vscnt"),
337	337	FeatureInfo(@This()).create(.Wavefrontsize16, "wavefrontsize16", "The number of threads per wavefront", "wavefrontsize16"),

lib/std/target/feature/ArmFeature.zig+196-196

...	...	@@ -177,7 +177,7 @@ pub const ArmFeature = enum {
177	177	Swift,
178	178	Xscale,
179	179
180		pub fn getInfo(self: @This()) FeatureInfo {
	180	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
181	181	return feature_infos[@enumToInt(self)];
182	182	}
183	183
...	...	@@ -215,283 +215,283 @@ pub const ArmFeature = enum {
215	215	.Trustzone,
216	216	}),
217	217	FeatureInfo(@This()).createWithSubfeatures(.Armv6M, "armv6-m", "ARMv6m architecture", "armv6-m", &[_]@This() {
218		.Mclass,
219		.StrictAlign,
	218	.V4t,
220	219	.ThumbMode,
221	220	.Db,
222		.V4t,
	221	.StrictAlign,
	222	.Mclass,
223	223	.Noarm,
224	224	}),
225	225	FeatureInfo(@This()).createWithSubfeatures(.Armv6sM, "armv6s-m", "ARMv6sm architecture", "armv6s-m", &[_]@This() {
226		.Mclass,
227		.StrictAlign,
	226	.V4t,
228	227	.ThumbMode,
229	228	.Db,
230		.V4t,
	229	.StrictAlign,
	230	.Mclass,
231	231	.Noarm,
232	232	}),
233	233	FeatureInfo(@This()).createWithSubfeatures(.Armv6t2, "armv6t2", "ARMv6t2 architecture", "armv6t2", &[_]@This() {
234		.Thumb2,
235	234	.V4t,
	235	.Thumb2,
236	236	.Dsp,
237	237	}),
238	238	FeatureInfo(@This()).createWithSubfeatures(.Armv7A, "armv7-a", "ARMv7a architecture", "armv7-a", &[_]@This() {
239		.Thumb2,
240	239	.Perfmon,
241		.Db,
242		.Dsp,
243		.V7clrex,
244	240	.V4t,
245		.Fpregs,
246	241	.D32,
	242	.Fpregs,
	243	.V7clrex,
	244	.Dsp,
	245	.Thumb2,
	246	.Db,
247	247	.Aclass,
248	248	}),
249	249	FeatureInfo(@This()).createWithSubfeatures(.Armv7eM, "armv7e-m", "ARMv7em architecture", "armv7e-m", &[_]@This() {
250		.Thumb2,
251		.Mclass,
252	250	.Perfmon,
	251	.V4t,
253	252	.ThumbMode,
254		.Db,
255		.Dsp,
256	253	.V7clrex,
257		.V4t,
258		.Hwdiv,
	254	.Dsp,
	255	.Thumb2,
	256	.Db,
	257	.Mclass,
259	258	.Noarm,
	259	.Hwdiv,
260	260	}),
261	261	FeatureInfo(@This()).createWithSubfeatures(.Armv7k, "armv7k", "ARMv7a architecture", "armv7k", &[_]@This() {
262		.Thumb2,
263	262	.Perfmon,
264		.Db,
265		.Dsp,
266		.V7clrex,
267	263	.V4t,
268		.Fpregs,
269	264	.D32,
	265	.Fpregs,
	266	.V7clrex,
	267	.Dsp,
	268	.Thumb2,
	269	.Db,
270	270	.Aclass,
271	271	}),
272	272	FeatureInfo(@This()).createWithSubfeatures(.Armv7M, "armv7-m", "ARMv7m architecture", "armv7-m", &[_]@This() {
273		.Thumb2,
274		.Mclass,
275	273	.Perfmon,
	274	.V4t,
276	275	.ThumbMode,
277		.Db,
278	276	.V7clrex,
279		.V4t,
280		.Hwdiv,
	277	.Thumb2,
	278	.Db,
	279	.Mclass,
281	280	.Noarm,
	281	.Hwdiv,
282	282	}),
283	283	FeatureInfo(@This()).createWithSubfeatures(.Armv7R, "armv7-r", "ARMv7r architecture", "armv7-r", &[_]@This() {
284		.Thumb2,
285	284	.Perfmon,
286		.Db,
287		.Dsp,
288		.Rclass,
289		.V7clrex,
290	285	.V4t,
	286	.V7clrex,
	287	.Dsp,
	288	.Thumb2,
	289	.Db,
291	290	.Hwdiv,
	291	.Rclass,
292	292	}),
293	293	FeatureInfo(@This()).createWithSubfeatures(.Armv7s, "armv7s", "ARMv7a architecture", "armv7s", &[_]@This() {
294		.Thumb2,
295	294	.Perfmon,
296		.Db,
297		.Dsp,
298		.V7clrex,
299	295	.V4t,
300		.Fpregs,
301	296	.D32,
	297	.Fpregs,
	298	.V7clrex,
	299	.Dsp,
	300	.Thumb2,
	301	.Db,
302	302	.Aclass,
303	303	}),
304	304	FeatureInfo(@This()).createWithSubfeatures(.Armv7ve, "armv7ve", "ARMv7ve architecture", "armv7ve", &[_]@This() {
305		.Thumb2,
306		.Mp,
	305	.HwdivArm,
307	306	.Perfmon,
308		.Db,
309		.Dsp,
310		.V7clrex,
311		.V4t,
312		.Fpregs,
313	307	.D32,
314		.Hwdiv,
315		.HwdivArm,
	308	.Mp,
	309	.Fpregs,
	310	.V4t,
	311	.V7clrex,
	312	.Dsp,
	313	.Thumb2,
	314	.Db,
316	315	.Aclass,
	316	.Hwdiv,
317	317	.Trustzone,
318	318	}),
319	319	FeatureInfo(@This()).createWithSubfeatures(.Armv8A, "armv8-a", "ARMv8a architecture", "armv8-a", &[_]@This() {
320		.Thumb2,
321		.Mp,
	320	.HwdivArm,
322	321	.Perfmon,
323		.Db,
	322	.D32,
	323	.Fpregs,
324	324	.Crc,
	325	.Mp,
325	326	.Fp16,
326	327	.Dsp,
327		.V7clrex,
328	328	.V4t,
329		.Fpregs,
330		.D32,
331		.Hwdiv,
332		.HwdivArm,
	329	.V7clrex,
	330	.Db,
333	331	.Aclass,
334		.Trustzone,
	332	.Thumb2,
335	333	.AcquireRelease,
	334	.Hwdiv,
	335	.Trustzone,
336	336	}),
337	337	FeatureInfo(@This()).createWithSubfeatures(.Armv8Mbase, "armv8-m.base", "ARMv8mBaseline architecture", "armv8-m.base", &[_]@This() {
338		.Mclass,
339		.StrictAlign,
	338	.V4t,
340	339	.ThumbMode,
341		.Db,
342	340	.Msecext8,
343	341	.V7clrex,
344		.V4t,
345		.Hwdiv,
	342	.Db,
	343	.StrictAlign,
	344	.Mclass,
346	345	.Noarm,
347	346	.AcquireRelease,
	347	.Hwdiv,
348	348	}),
349	349	FeatureInfo(@This()).createWithSubfeatures(.Armv8Mmain, "armv8-m.main", "ARMv8mMainline architecture", "armv8-m.main", &[_]@This() {
350		.Thumb2,
351		.Mclass,
352	350	.Perfmon,
	351	.V4t,
353	352	.ThumbMode,
354		.Db,
355	353	.Msecext8,
356	354	.V7clrex,
357		.V4t,
358		.Hwdiv,
	355	.Thumb2,
	356	.Db,
	357	.Mclass,
359	358	.Noarm,
360	359	.AcquireRelease,
	360	.Hwdiv,
361	361	}),
362	362	FeatureInfo(@This()).createWithSubfeatures(.Armv8R, "armv8-r", "ARMv8r architecture", "armv8-r", &[_]@This() {
363		.Thumb2,
364		.Mp,
	363	.HwdivArm,
365	364	.Perfmon,
366		.Db,
	365	.D32,
367	366	.Crc,
368		.Fp16,
	367	.Fpregs,
	368	.Mp,
369	369	.Dfb,
370	370	.Dsp,
371		.Rclass,
372		.V7clrex,
	371	.Fp16,
373	372	.V4t,
374		.Fpregs,
375		.D32,
376		.Hwdiv,
377		.HwdivArm,
	373	.Db,
	374	.V7clrex,
	375	.Thumb2,
378	376	.AcquireRelease,
	377	.Hwdiv,
	378	.Rclass,
379	379	}),
380	380	FeatureInfo(@This()).createWithSubfeatures(.Armv81A, "armv8.1-a", "ARMv81a architecture", "armv8.1-a", &[_]@This() {
381		.Thumb2,
382		.Mp,
	381	.HwdivArm,
383	382	.Perfmon,
384		.Db,
	383	.D32,
	384	.Fpregs,
385	385	.Crc,
	386	.Mp,
386	387	.Fp16,
387	388	.Dsp,
388		.V7clrex,
389	389	.V4t,
390		.Fpregs,
391		.D32,
392		.Hwdiv,
393		.HwdivArm,
	390	.V7clrex,
	391	.Db,
394	392	.Aclass,
395		.Trustzone,
	393	.Thumb2,
396	394	.AcquireRelease,
	395	.Hwdiv,
	396	.Trustzone,
397	397	}),
398	398	FeatureInfo(@This()).createWithSubfeatures(.Armv81Mmain, "armv8.1-m.main", "ARMv81mMainline architecture", "armv8.1-m.main", &[_]@This() {
399		.Thumb2,
400		.Mclass,
401	399	.Perfmon,
	400	.V4t,
402	401	.ThumbMode,
403		.Db,
404	402	.Msecext8,
405		.Ras,
406	403	.V7clrex,
407		.V4t,
408		.Hwdiv,
	404	.Thumb2,
	405	.Db,
	406	.Ras,
	407	.Mclass,
409	408	.Noarm,
410		.Lob,
411	409	.AcquireRelease,
	410	.Hwdiv,
	411	.Lob,
412	412	}),
413	413	FeatureInfo(@This()).createWithSubfeatures(.Armv82A, "armv8.2-a", "ARMv82a architecture", "armv8.2-a", &[_]@This() {
414		.Thumb2,
415		.Mp,
	414	.HwdivArm,
416	415	.Perfmon,
417		.Db,
	416	.D32,
	417	.Fpregs,
418	418	.Crc,
	419	.Mp,
419	420	.Fp16,
420		.Ras,
421	421	.Dsp,
422		.V7clrex,
423	422	.V4t,
424		.Fpregs,
425		.D32,
426		.Hwdiv,
427		.HwdivArm,
	423	.V7clrex,
	424	.Db,
428	425	.Aclass,
429		.Trustzone,
	426	.Thumb2,
	427	.Ras,
430	428	.AcquireRelease,
	429	.Hwdiv,
	430	.Trustzone,
431	431	}),
432	432	FeatureInfo(@This()).createWithSubfeatures(.Armv83A, "armv8.3-a", "ARMv83a architecture", "armv8.3-a", &[_]@This() {
433		.Thumb2,
434		.Mp,
	433	.HwdivArm,
435	434	.Perfmon,
436		.Db,
	435	.D32,
	436	.Fpregs,
437	437	.Crc,
	438	.Mp,
438	439	.Fp16,
439		.Ras,
440	440	.Dsp,
441		.V7clrex,
442	441	.V4t,
443		.Fpregs,
444		.D32,
445		.Hwdiv,
446		.HwdivArm,
	442	.V7clrex,
	443	.Db,
447	444	.Aclass,
448		.Trustzone,
	445	.Thumb2,
	446	.Ras,
449	447	.AcquireRelease,
	448	.Hwdiv,
	449	.Trustzone,
450	450	}),
451	451	FeatureInfo(@This()).createWithSubfeatures(.Armv84A, "armv8.4-a", "ARMv84a architecture", "armv8.4-a", &[_]@This() {
452		.Thumb2,
453		.Mp,
	452	.HwdivArm,
454	453	.Perfmon,
455		.Db,
	454	.D32,
	455	.Fpregs,
456	456	.Crc,
	457	.Mp,
457	458	.Fp16,
458		.Ras,
459	459	.Dsp,
460		.V7clrex,
461	460	.V4t,
462		.Fpregs,
463		.D32,
464		.Hwdiv,
465		.HwdivArm,
	461	.V7clrex,
	462	.Db,
466	463	.Aclass,
467		.Trustzone,
	464	.Thumb2,
	465	.Ras,
468	466	.AcquireRelease,
	467	.Hwdiv,
	468	.Trustzone,
469	469	}),
470	470	FeatureInfo(@This()).createWithSubfeatures(.Armv85A, "armv8.5-a", "ARMv85a architecture", "armv8.5-a", &[_]@This() {
471		.Thumb2,
472		.Mp,
	471	.HwdivArm,
473	472	.Perfmon,
474		.Sb,
475		.Db,
	473	.D32,
	474	.Fpregs,
476	475	.Crc,
	476	.Mp,
477	477	.Fp16,
478		.Ras,
479	478	.Dsp,
480		.V7clrex,
481	479	.V4t,
482		.Fpregs,
483		.D32,
484		.Hwdiv,
485		.HwdivArm,
	480	.V7clrex,
	481	.Db,
486	482	.Aclass,
487		.Trustzone,
	483	.Thumb2,
	484	.Ras,
	485	.Sb,
488	486	.AcquireRelease,
	487	.Hwdiv,
	488	.Trustzone,
489	489	}),
490	490	FeatureInfo(@This()).create(.Msecext8, "8msecext", "Enable support for ARMv8-M Security Extensions", "8msecext"),
491	491	FeatureInfo(@This()).create(.Aclass, "aclass", "Is application profile ('A' series)", "aclass"),
492	492	FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
493		.Fpregs,
494	493	.D32,
	494	.Fpregs,
495	495	}),
496	496	FeatureInfo(@This()).create(.AcquireRelease, "acquire-release", "Has v8 acquire/release (lda/ldaex etc) instructions", "acquire-release"),
497	497	FeatureInfo(@This()).create(.AvoidMovsShop, "avoid-movs-shop", "Avoid movs instructions with shifter operand", "avoid-movs-shop"),
...	...	@@ -500,8 +500,8 @@ pub const ArmFeature = enum {
500	500	FeatureInfo(@This()).create(.CheapPredicableCpsr, "cheap-predicable-cpsr", "Disable +1 predication cost for instructions updating CPSR", "cheap-predicable-cpsr"),
501	501	FeatureInfo(@This()).create(.VldnAlign, "vldn-align", "Check for VLDn unaligned access", "vldn-align"),
502	502	FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable support for Cryptography extensions", "crypto", &[_]@This() {
503		.Fpregs,
504	503	.D32,
	504	.Fpregs,
505	505	}),
506	506	FeatureInfo(@This()).create(.D32, "d32", "Extend FP to 32 double registers", "d32"),
507	507	FeatureInfo(@This()).create(.Db, "db", "Has data barrier (dmb/dsb) instructions", "db"),
...	...	@@ -509,37 +509,37 @@ pub const ArmFeature = enum {
509	509	FeatureInfo(@This()).create(.Dsp, "dsp", "Supports DSP instructions in ARM and/or Thumb2", "dsp"),
510	510	FeatureInfo(@This()).create(.DontWidenVmovs, "dont-widen-vmovs", "Don't widen VMOVS to VMOVD", "dont-widen-vmovs"),
511	511	FeatureInfo(@This()).createWithSubfeatures(.Dotprod, "dotprod", "Enable support for dot product instructions", "dotprod", &[_]@This() {
512		.Fpregs,
513	512	.D32,
	513	.Fpregs,
514	514	}),
515	515	FeatureInfo(@This()).create(.ExecuteOnly, "execute-only", "Enable the generation of execute only code.", "execute-only"),
516	516	FeatureInfo(@This()).create(.ExpandFpMlx, "expand-fp-mlx", "Expand VFP/NEON MLA/MLS instructions", "expand-fp-mlx"),
517	517	FeatureInfo(@This()).create(.Fp16, "fp16", "Enable half-precision floating point", "fp16"),
518	518	FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable full half-precision floating point fml instructions", "fp16fml", &[_]@This() {
519		.Fp16,
520	519	.Fpregs,
	520	.Fp16,
521	521	}),
522	522	FeatureInfo(@This()).createWithSubfeatures(.Fp64, "fp64", "Floating point unit supports double precision", "fp64", &[_]@This() {
523	523	.Fpregs,
524	524	}),
525	525	FeatureInfo(@This()).create(.Fpao, "fpao", "Enable fast computation of positive address offsets", "fpao"),
526	526	FeatureInfo(@This()).createWithSubfeatures(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8", &[_]@This() {
527		.Fp16,
528		.Fpregs,
529	527	.D32,
	528	.Fpregs,
	529	.Fp16,
530	530	}),
531	531	FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16, "fp-armv8d16", "Enable ARMv8 FP with only 16 d-registers", "fp-armv8d16", &[_]@This() {
532		.Fp16,
533	532	.Fpregs,
	533	.Fp16,
534	534	}),
535	535	FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16sp, "fp-armv8d16sp", "Enable ARMv8 FP with only 16 d-registers and no double precision", "fp-armv8d16sp", &[_]@This() {
536		.Fp16,
537	536	.Fpregs,
	537	.Fp16,
538	538	}),
539	539	FeatureInfo(@This()).createWithSubfeatures(.FpArmv8sp, "fp-armv8sp", "Enable ARMv8 FP with no double precision", "fp-armv8sp", &[_]@This() {
540		.Fp16,
541		.Fpregs,
542	540	.D32,
	541	.Fpregs,
	542	.Fp16,
543	543	}),
544	544	FeatureInfo(@This()).create(.Fpregs, "fpregs", "Enable FP registers", "fpregs"),
545	545	FeatureInfo(@This()).createWithSubfeatures(.Fpregs16, "fpregs16", "Enable 16-bit FP registers", "fpregs16", &[_]@This() {
...	...	@@ -549,8 +549,8 @@ pub const ArmFeature = enum {
549	549	.Fpregs,
550	550	}),
551	551	FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Enable full half-precision floating point", "fullfp16", &[_]@This() {
552		.Fp16,
553	552	.Fpregs,
	553	.Fp16,
554	554	}),
555	555	FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
556	556	FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
...	...	@@ -569,8 +569,8 @@ pub const ArmFeature = enum {
569	569	FeatureInfo(@This()).create(.Mve4beat, "mve4beat", "Model MVE instructions as a 4 beats per tick architecture", "mve4beat"),
570	570	FeatureInfo(@This()).create(.MuxedUnits, "muxed-units", "Has muxed AGU and NEON/FPU", "muxed-units"),
571	571	FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable NEON instructions", "neon", &[_]@This() {
572		.Fpregs,
573	572	.D32,
	573	.Fpregs,
574	574	}),
575	575	FeatureInfo(@This()).create(.Neonfp, "neonfp", "Use NEON for single precision FP", "neonfp"),
576	576	FeatureInfo(@This()).create(.NeonFpmovs, "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", "neon-fpmovs"),
...	...	@@ -592,8 +592,8 @@ pub const ArmFeature = enum {
592	592	FeatureInfo(@This()).create(.ReserveR9, "reserve-r9", "Reserve R9, making it unavailable as GPR", "reserve-r9"),
593	593	FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5a Speculation Barrier", "sb"),
594	594	FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
595		.Fpregs,
596	595	.D32,
	596	.Fpregs,
597	597	}),
598	598	FeatureInfo(@This()).create(.SlowFpBrcc, "slow-fp-brcc", "FP compare + branch is slow", "slow-fp-brcc"),
599	599	FeatureInfo(@This()).create(.SlowLoadDSubreg, "slow-load-D-subreg", "Loading into D subregs is slow", "slow-load-D-subreg"),
...	...	@@ -617,8 +617,8 @@ pub const ArmFeature = enum {
617	617	.Fpregs,
618	618	}),
619	619	FeatureInfo(@This()).createWithSubfeatures(.Vfp3, "vfp3", "Enable VFP3 instructions", "vfp3", &[_]@This() {
620		.Fpregs,
621	620	.D32,
	621	.Fpregs,
622	622	}),
623	623	FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16, "vfp3d16", "Enable VFP3 instructions with only 16 d-registers", "vfp3d16", &[_]@This() {
624	624	.Fpregs,
...	...	@@ -627,26 +627,26 @@ pub const ArmFeature = enum {
627	627	.Fpregs,
628	628	}),
629	629	FeatureInfo(@This()).createWithSubfeatures(.Vfp3sp, "vfp3sp", "Enable VFP3 instructions with no double precision", "vfp3sp", &[_]@This() {
630		.Fpregs,
631	630	.D32,
	631	.Fpregs,
632	632	}),
633	633	FeatureInfo(@This()).createWithSubfeatures(.Vfp4, "vfp4", "Enable VFP4 instructions", "vfp4", &[_]@This() {
634		.Fp16,
635		.Fpregs,
636	634	.D32,
	635	.Fpregs,
	636	.Fp16,
637	637	}),
638	638	FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16, "vfp4d16", "Enable VFP4 instructions with only 16 d-registers", "vfp4d16", &[_]@This() {
639		.Fp16,
640	639	.Fpregs,
	640	.Fp16,
641	641	}),
642	642	FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16sp, "vfp4d16sp", "Enable VFP4 instructions with only 16 d-registers and no double precision", "vfp4d16sp", &[_]@This() {
643		.Fp16,
644	643	.Fpregs,
	644	.Fp16,
645	645	}),
646	646	FeatureInfo(@This()).createWithSubfeatures(.Vfp4sp, "vfp4sp", "Enable VFP4 instructions with no double precision", "vfp4sp", &[_]@This() {
647		.Fp16,
648		.Fpregs,
649	647	.D32,
	648	.Fpregs,
	649	.Fp16,
650	650	}),
651	651	FeatureInfo(@This()).create(.VmlxForwarding, "vmlx-forwarding", "Has multiplier accumulator forwarding", "vmlx-forwarding"),
652	652	FeatureInfo(@This()).createWithSubfeatures(.Virtualization, "virtualization", "Supports Virtualization extension", "virtualization", &[_]@This() {
...	...	@@ -655,21 +655,21 @@ pub const ArmFeature = enum {
655	655	}),
656	656	FeatureInfo(@This()).create(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz"),
657	657	FeatureInfo(@This()).createWithSubfeatures(.Mvefp, "mve.fp", "Support M-Class Vector Extension with integer and floating ops", "mve.fp", &[_]@This() {
658		.Thumb2,
659	658	.Perfmon,
660		.Fp16,
661		.Dsp,
662		.V7clrex,
663	659	.V4t,
664	660	.Fpregs,
	661	.V7clrex,
	662	.Fp16,
	663	.Dsp,
	664	.Thumb2,
665	665	}),
666	666	FeatureInfo(@This()).createWithSubfeatures(.Mve, "mve", "Support M-Class Vector Extension with integer ops", "mve", &[_]@This() {
667		.Thumb2,
668	667	.Perfmon,
669		.Dsp,
670		.V7clrex,
671	668	.V4t,
672	669	.Fpregs,
	670	.V7clrex,
	671	.Dsp,
	672	.Thumb2,
673	673	}),
674	674	FeatureInfo(@This()).create(.V4t, "v4t", "Support ARM v4T instructions", "v4t"),
675	675	FeatureInfo(@This()).createWithSubfeatures(.V5te, "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", "v5te", &[_]@This() {
...	...	@@ -688,76 +688,76 @@ pub const ArmFeature = enum {
688	688	.V4t,
689	689	}),
690	690	FeatureInfo(@This()).createWithSubfeatures(.V6t2, "v6t2", "Support ARM v6t2 instructions", "v6t2", &[_]@This() {
691		.Thumb2,
692	691	.V4t,
	692	.Thumb2,
693	693	}),
694	694	FeatureInfo(@This()).createWithSubfeatures(.V7, "v7", "Support ARM v7 instructions", "v7", &[_]@This() {
695		.V7clrex,
696		.V4t,
697	695	.Perfmon,
698	696	.Thumb2,
	697	.V4t,
	698	.V7clrex,
699	699	}),
700	700	FeatureInfo(@This()).createWithSubfeatures(.V8m, "v8m", "Support ARM v8M Baseline instructions", "v8m", &[_]@This() {
701	701	.V4t,
702	702	}),
703	703	FeatureInfo(@This()).createWithSubfeatures(.V8mmain, "v8m.main", "Support ARM v8M Mainline instructions", "v8m.main", &[_]@This() {
704		.V7clrex,
705		.V4t,
706	704	.Perfmon,
707	705	.Thumb2,
	706	.V4t,
	707	.V7clrex,
708	708	}),
709	709	FeatureInfo(@This()).createWithSubfeatures(.V8, "v8", "Support ARM v8 instructions", "v8", &[_]@This() {
710		.Thumb2,
711	710	.Perfmon,
712		.V7clrex,
713	711	.V4t,
	712	.V7clrex,
	713	.Thumb2,
714	714	.AcquireRelease,
715	715	}),
716	716	FeatureInfo(@This()).createWithSubfeatures(.V81mmain, "v8.1m.main", "Support ARM v8-1M Mainline instructions", "v8.1m.main", &[_]@This() {
717		.V7clrex,
718		.V4t,
719	717	.Perfmon,
720	718	.Thumb2,
	719	.V4t,
	720	.V7clrex,
721	721	}),
722	722	FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
723		.Thumb2,
724	723	.Perfmon,
725		.V7clrex,
726	724	.V4t,
	725	.V7clrex,
	726	.Thumb2,
727	727	.AcquireRelease,
728	728	}),
729	729	FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
730		.Thumb2,
731	730	.Perfmon,
732		.V7clrex,
733	731	.V4t,
	732	.V7clrex,
	733	.Thumb2,
734	734	.AcquireRelease,
735	735	}),
736	736	FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
737		.Thumb2,
738	737	.Perfmon,
739		.V7clrex,
740	738	.V4t,
	739	.V7clrex,
	740	.Thumb2,
741	741	.AcquireRelease,
742	742	}),
743	743	FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
744		.Thumb2,
745	744	.Perfmon,
746		.V7clrex,
747	745	.V4t,
748		.Fpregs,
749	746	.D32,
	747	.Fpregs,
	748	.V7clrex,
	749	.Thumb2,
750	750	.AcquireRelease,
751	751	}),
752	752	FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
753		.Thumb2,
754	753	.Perfmon,
755		.Sb,
756		.V7clrex,
757	754	.V4t,
758		.Fpregs,
759	755	.D32,
	756	.Fpregs,
	757	.V7clrex,
	758	.Thumb2,
760	759	.AcquireRelease,
	760	.Sb,
761	761	}),
762	762	FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt, "iwmmxt", "ARMv5te architecture", "iwmmxt", &[_]@This() {
763	763	.V4t,
...	...	@@ -784,24 +784,24 @@ pub const ArmFeature = enum {
784	784	FeatureInfo(@This()).create(.A75, "a75", "Cortex-A75 ARM processors", "a75"),
785	785	FeatureInfo(@This()).create(.A76, "a76", "Cortex-A76 ARM processors", "a76"),
786	786	FeatureInfo(@This()).createWithSubfeatures(.Exynos, "exynos", "Samsung Exynos processors", "exynos", &[_]@This() {
787		.Zcz,
788		.SlowVdup32,
789		.SlowVgetlni32,
790		.DontWidenVmovs,
	787	.HwdivArm,
	788	.D32,
791	789	.Crc,
792		.FuseAes,
	790	.Fpregs,
	791	.RetAddrStack,
	792	.SlowVgetlni32,
793	793	.WideStrideVfp,
	794	.SlowVdup32,
	795	.SlowFpBrcc,
794	796	.ProfUnpr,
	797	.DontWidenVmovs,
	798	.Zcz,
	799	.Hwdiv,
	800	.FuseAes,
795	801	.Slowfpvmlx,
796		.SlowFpBrcc,
	802	.UseAa,
797	803	.FuseLiterals,
798		.Fpregs,
799		.D32,
800	804	.ExpandFpMlx,
801		.Hwdiv,
802		.HwdivArm,
803		.RetAddrStack,
804		.UseAa,
805	805	}),
806	806	FeatureInfo(@This()).create(.Krait, "krait", "Qualcomm Krait processors", "krait"),
807	807	FeatureInfo(@This()).create(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo"),

lib/std/target/feature/AvrFeature.zig+81-81

...	...	@@ -35,160 +35,160 @@ pub const AvrFeature = enum {
35	35	Smallstack,
36	36	Tinyencoding,
37	37
38		pub fn getInfo(self: @This()) FeatureInfo {
	38	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
39	39	return feature_infos[@enumToInt(self)];
40	40	}
41	41
42	42	pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
43	43	FeatureInfo(@This()).create(.Avr0, "avr0", "The device is a part of the avr0 family", "avr0"),
44	44	FeatureInfo(@This()).createWithSubfeatures(.Avr1, "avr1", "The device is a part of the avr1 family", "avr1", &[_]@This() {
45		.Lpm,
46	45	.Avr0,
	46	.Lpm,
47	47	}),
48	48	FeatureInfo(@This()).createWithSubfeatures(.Avr2, "avr2", "The device is a part of the avr2 family", "avr2", &[_]@This() {
49		.Ijmpcall,
50		.Sram,
	49	.Lpm,
51	50	.Avr0,
	51	.Sram,
52	52	.Addsubiw,
53		.Lpm,
	53	.Ijmpcall,
54	54	}),
55	55	FeatureInfo(@This()).createWithSubfeatures(.Avr3, "avr3", "The device is a part of the avr3 family", "avr3", &[_]@This() {
56		.Ijmpcall,
57		.Sram,
	56	.Lpm,
58	57	.Avr0,
	58	.Sram,
59	59	.Jmpcall,
60	60	.Addsubiw,
61		.Lpm,
	61	.Ijmpcall,
62	62	}),
63	63	FeatureInfo(@This()).createWithSubfeatures(.Avr4, "avr4", "The device is a part of the avr4 family", "avr4", &[_]@This() {
64		.Ijmpcall,
	64	.Lpm,
65	65	.Movw,
66		.Mul,
67		.Sram,
68		.Break,
69	66	.Spm,
70		.Lpmx,
71	67	.Avr0,
	68	.Sram,
72	69	.Addsubiw,
73		.Lpm,
	70	.Mul,
	71	.Lpmx,
	72	.Ijmpcall,
	73	.Break,
74	74	}),
75	75	FeatureInfo(@This()).createWithSubfeatures(.Avr5, "avr5", "The device is a part of the avr5 family", "avr5", &[_]@This() {
76		.Ijmpcall,
	76	.Lpm,
77	77	.Movw,
78		.Mul,
79		.Sram,
80		.Break,
81	78	.Spm,
82		.Lpmx,
83	79	.Avr0,
	80	.Sram,
84	81	.Jmpcall,
85	82	.Addsubiw,
86		.Lpm,
	83	.Mul,
	84	.Lpmx,
	85	.Ijmpcall,
	86	.Break,
87	87	}),
88	88	FeatureInfo(@This()).createWithSubfeatures(.Avr6, "avr6", "The device is a part of the avr6 family", "avr6", &[_]@This() {
89		.Ijmpcall,
90		.Elpmx,
	89	.Lpm,
	90	.Elpm,
91	91	.Movw,
92		.Mul,
93		.Sram,
94		.Break,
	92	.Elpmx,
95	93	.Spm,
96		.Elpm,
97		.Lpmx,
98	94	.Avr0,
	95	.Sram,
99	96	.Jmpcall,
100	97	.Addsubiw,
101		.Lpm,
	98	.Mul,
	99	.Lpmx,
	100	.Ijmpcall,
	101	.Break,
102	102	}),
103	103	FeatureInfo(@This()).createWithSubfeatures(.Avr25, "avr25", "The device is a part of the avr25 family", "avr25", &[_]@This() {
104		.Ijmpcall,
	104	.Lpm,
105	105	.Movw,
106		.Sram,
107		.Break,
108	106	.Spm,
109		.Lpmx,
110	107	.Avr0,
	108	.Sram,
111	109	.Addsubiw,
112		.Lpm,
	110	.Lpmx,
	111	.Ijmpcall,
	112	.Break,
113	113	}),
114	114	FeatureInfo(@This()).createWithSubfeatures(.Avr31, "avr31", "The device is a part of the avr31 family", "avr31", &[_]@This() {
115		.Ijmpcall,
116		.Sram,
	115	.Lpm,
117	116	.Elpm,
118	117	.Avr0,
	118	.Sram,
119	119	.Jmpcall,
120	120	.Addsubiw,
121		.Lpm,
	121	.Ijmpcall,
122	122	}),
123	123	FeatureInfo(@This()).createWithSubfeatures(.Avr35, "avr35", "The device is a part of the avr35 family", "avr35", &[_]@This() {
124		.Ijmpcall,
	124	.Lpm,
125	125	.Movw,
126		.Sram,
127		.Break,
128	126	.Spm,
129		.Lpmx,
130	127	.Avr0,
	128	.Sram,
131	129	.Jmpcall,
132	130	.Addsubiw,
133		.Lpm,
	131	.Lpmx,
	132	.Ijmpcall,
	133	.Break,
134	134	}),
135	135	FeatureInfo(@This()).createWithSubfeatures(.Avr51, "avr51", "The device is a part of the avr51 family", "avr51", &[_]@This() {
136		.Ijmpcall,
137		.Elpmx,
	136	.Lpm,
	137	.Elpm,
138	138	.Movw,
139		.Mul,
140		.Sram,
141		.Break,
	139	.Elpmx,
142	140	.Spm,
143		.Elpm,
144		.Lpmx,
145	141	.Avr0,
	142	.Sram,
146	143	.Jmpcall,
147	144	.Addsubiw,
148		.Lpm,
	145	.Mul,
	146	.Lpmx,
	147	.Ijmpcall,
	148	.Break,
149	149	}),
150	150	FeatureInfo(@This()).createWithSubfeatures(.Avrtiny, "avrtiny", "The device is a part of the avrtiny family", "avrtiny", &[_]@This() {
151		.Break,
152		.Tinyencoding,
153	151	.Avr0,
154	152	.Sram,
	153	.Break,
	154	.Tinyencoding,
155	155	}),
156	156	FeatureInfo(@This()).createWithSubfeatures(.Xmega, "xmega", "The device is a part of the xmega family", "xmega", &[_]@This() {
157		.Ijmpcall,
158		.Elpmx,
	157	.Lpm,
	158	.Elpm,
159	159	.Movw,
160		.Eijmpcall,
161		.Mul,
162		.Sram,
163		.Break,
	160	.Elpmx,
164	161	.Spm,
165		.Elpm,
166		.Lpmx,
167		.Spmx,
168	162	.Avr0,
	163	.Sram,
169	164	.Jmpcall,
	165	.Eijmpcall,
	166	.Spmx,
170	167	.Addsubiw,
171		.Lpm,
	168	.Mul,
	169	.Lpmx,
172	170	.Des,
	171	.Ijmpcall,
	172	.Break,
173	173	}),
174	174	FeatureInfo(@This()).createWithSubfeatures(.Xmegau, "xmegau", "The device is a part of the xmegau family", "xmegau", &[_]@This() {
175		.Ijmpcall,
176		.Elpmx,
	175	.Lpm,
	176	.Elpm,
177	177	.Movw,
178		.Eijmpcall,
179		.Mul,
180		.Rmw,
181		.Sram,
182		.Break,
	178	.Elpmx,
183	179	.Spm,
184		.Elpm,
185		.Lpmx,
186		.Spmx,
187	180	.Avr0,
	181	.Sram,
188	182	.Jmpcall,
	183	.Eijmpcall,
	184	.Spmx,
189	185	.Addsubiw,
190		.Lpm,
	186	.Mul,
	187	.Lpmx,
	188	.Rmw,
191	189	.Des,
	190	.Ijmpcall,
	191	.Break,
192	192	}),
193	193	FeatureInfo(@This()).create(.Addsubiw, "addsubiw", "Enable 16-bit register-immediate addition and subtraction instructions", "addsubiw"),
194	194	FeatureInfo(@This()).create(.Break, "break", "The device supports the `BREAK` debugging instruction", "break"),
...	...	@@ -207,22 +207,22 @@ pub const AvrFeature = enum {
207	207	FeatureInfo(@This()).create(.Spmx, "spmx", "The device supports the `SPM Z+` instruction", "spmx"),
208	208	FeatureInfo(@This()).create(.Sram, "sram", "The device has random access memory", "sram"),
209	209	FeatureInfo(@This()).createWithSubfeatures(.Special, "special", "Enable use of the entire instruction set - used for debugging", "special", &[_]@This() {
210		.Ijmpcall,
	210	.Lpm,
	211	.Elpm,
211	212	.Elpmx,
212	213	.Movw,
213		.Eijmpcall,
214		.Mul,
215		.Rmw,
216		.Sram,
217		.Break,
218		.Elpm,
219	214	.Spm,
220		.Lpmx,
	215	.Eijmpcall,
221	216	.Spmx,
222	217	.Jmpcall,
	218	.Sram,
223	219	.Addsubiw,
224		.Lpm,
	220	.Mul,
	221	.Lpmx,
	222	.Rmw,
225	223	.Des,
	224	.Ijmpcall,
	225	.Break,
226	226	}),
227	227	FeatureInfo(@This()).create(.Smallstack, "smallstack", "The device has an 8-bit stack pointer", "smallstack"),
228	228	FeatureInfo(@This()).create(.Tinyencoding, "tinyencoding", "The device has Tiny core specific instruction encodings", "tinyencoding"),

lib/std/target/feature/BpfFeature.zig+1-1

...	...	@@ -5,7 +5,7 @@ pub const BpfFeature = enum {
5	5	Dummy,
6	6	Dwarfris,
7	7
8		pub fn getInfo(self: @This()) FeatureInfo {
	8	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
9	9	return feature_infos[@enumToInt(self)];
10	10	}
11	11

lib/std/target/feature/HexagonFeature.zig+1-1

...	...	@@ -26,7 +26,7 @@ pub const HexagonFeature = enum {
26	26	ReservedR19,
27	27	SmallData,
28	28
29		pub fn getInfo(self: @This()) FeatureInfo {
	29	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
30	30	return feature_infos[@enumToInt(self)];
31	31	}
32	32

lib/std/target/feature/MipsFeature.zig+73-73

...	...	@@ -52,7 +52,7 @@ pub const MipsFeature = enum {
52	52	Xgot,
53	53	P5600,
54	54
55		pub fn getInfo(self: @This()) FeatureInfo {
	55	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
56	56	return feature_infos[@enumToInt(self)];
57	57	}
58	58
...	...	@@ -60,14 +60,14 @@ pub const MipsFeature = enum {
60	60	FeatureInfo(@This()).create(.Abs2008, "abs2008", "Disable IEEE 754-2008 abs.fmt mode", "abs2008"),
61	61	FeatureInfo(@This()).create(.Crc, "crc", "Mips R6 CRC ASE", "crc"),
62	62	FeatureInfo(@This()).createWithSubfeatures(.Cnmips, "cnmips", "Octeon cnMIPS Support", "cnmips", &[_]@This() {
63		.Mips3_32,
64		.Fp64,
65		.Mips4_32r2,
	63	.Mips5_32r2,
66	64	.Mips3_32r2,
67		.Mips1,
68		.Mips4_32,
	65	.Mips4_32r2,
69	66	.Gp64,
70		.Mips5_32r2,
	67	.Fp64,
	68	.Mips4_32,
	69	.Mips1,
	70	.Mips3_32,
71	71	}),
72	72	FeatureInfo(@This()).create(.Dsp, "dsp", "Mips DSP ASE", "dsp"),
73	73	FeatureInfo(@This()).createWithSubfeatures(.Dspr2, "dspr2", "Mips DSP-R2 ASE", "dspr2", &[_]@This() {
...	...	@@ -91,128 +91,128 @@ pub const MipsFeature = enum {
91	91	.Mips1,
92	92	}),
93	93	FeatureInfo(@This()).createWithSubfeatures(.Mips3, "mips3", "MIPS III ISA Support [highly experimental]", "mips3", &[_]@This() {
94		.Mips3_32,
95		.Fp64,
96	94	.Mips3_32r2,
97		.Mips1,
	95	.Fp64,
98	96	.Gp64,
	97	.Mips1,
	98	.Mips3_32,
99	99	}),
100	100	FeatureInfo(@This()).create(.Mips3_32, "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", "mips3_32"),
101	101	FeatureInfo(@This()).create(.Mips3_32r2, "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", "mips3_32r2"),
102	102	FeatureInfo(@This()).createWithSubfeatures(.Mips4, "mips4", "MIPS IV ISA Support", "mips4", &[_]@This() {
103		.Mips3_32,
104		.Fp64,
105		.Mips4_32r2,
106	103	.Mips3_32r2,
107		.Mips1,
108		.Mips4_32,
	104	.Mips4_32r2,
	105	.Fp64,
109	106	.Gp64,
	107	.Mips4_32,
	108	.Mips1,
	109	.Mips3_32,
110	110	}),
111	111	FeatureInfo(@This()).create(.Mips4_32, "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", "mips4_32"),
112	112	FeatureInfo(@This()).create(.Mips4_32r2, "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", "mips4_32r2"),
113	113	FeatureInfo(@This()).createWithSubfeatures(.Mips5, "mips5", "MIPS V ISA Support [highly experimental]", "mips5", &[_]@This() {
114		.Mips3_32,
115		.Fp64,
	114	.Mips5_32r2,
116	115	.Mips4_32r2,
117	116	.Mips3_32r2,
118		.Mips1,
119		.Mips4_32,
120	117	.Gp64,
121		.Mips5_32r2,
	118	.Fp64,
	119	.Mips4_32,
	120	.Mips1,
	121	.Mips3_32,
122	122	}),
123	123	FeatureInfo(@This()).create(.Mips5_32r2, "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", "mips5_32r2"),
124	124	FeatureInfo(@This()).create(.Mips16, "mips16", "Mips16 mode", "mips16"),
125	125	FeatureInfo(@This()).createWithSubfeatures(.Mips32, "mips32", "Mips32 ISA Support", "mips32", &[_]@This() {
126		.Mips3_32,
127	126	.Mips4_32,
128	127	.Mips1,
	128	.Mips3_32,
129	129	}),
130	130	FeatureInfo(@This()).createWithSubfeatures(.Mips32r2, "mips32r2", "Mips32r2 ISA Support", "mips32r2", &[_]@This() {
131		.Mips3_32,
	131	.Mips5_32r2,
132	132	.Mips4_32r2,
133	133	.Mips3_32r2,
134		.Mips1,
135	134	.Mips4_32,
136		.Mips5_32r2,
	135	.Mips1,
	136	.Mips3_32,
137	137	}),
138	138	FeatureInfo(@This()).createWithSubfeatures(.Mips32r3, "mips32r3", "Mips32r3 ISA Support", "mips32r3", &[_]@This() {
139		.Mips3_32,
140		.Mips4_32r2,
	139	.Mips5_32r2,
141	140	.Mips3_32r2,
142		.Mips1,
	141	.Mips4_32r2,
143	142	.Mips4_32,
144		.Mips5_32r2,
	143	.Mips1,
	144	.Mips3_32,
145	145	}),
146	146	FeatureInfo(@This()).createWithSubfeatures(.Mips32r5, "mips32r5", "Mips32r5 ISA Support", "mips32r5", &[_]@This() {
147		.Mips3_32,
148		.Mips4_32r2,
	147	.Mips5_32r2,
149	148	.Mips3_32r2,
150		.Mips1,
	149	.Mips4_32r2,
151	150	.Mips4_32,
152		.Mips5_32r2,
	151	.Mips1,
	152	.Mips3_32,
153	153	}),
154	154	FeatureInfo(@This()).createWithSubfeatures(.Mips32r6, "mips32r6", "Mips32r6 ISA Support [experimental]", "mips32r6", &[_]@This() {
155		.Mips3_32,
156		.Fp64,
	155	.Mips5_32r2,
	156	.Mips3_32r2,
157	157	.Mips4_32r2,
158	158	.Abs2008,
159		.Mips3_32r2,
160		.Mips1,
161		.Mips4_32,
162	159	.Nan2008,
163		.Mips5_32r2,
	160	.Fp64,
	161	.Mips4_32,
	162	.Mips1,
	163	.Mips3_32,
164	164	}),
165	165	FeatureInfo(@This()).createWithSubfeatures(.Mips64, "mips64", "Mips64 ISA Support", "mips64", &[_]@This() {
166		.Mips3_32,
167		.Fp64,
168		.Mips4_32r2,
	166	.Mips5_32r2,
169	167	.Mips3_32r2,
170		.Mips1,
171		.Mips4_32,
	168	.Mips4_32r2,
172	169	.Gp64,
173		.Mips5_32r2,
	170	.Fp64,
	171	.Mips4_32,
	172	.Mips1,
	173	.Mips3_32,
174	174	}),
175	175	FeatureInfo(@This()).createWithSubfeatures(.Mips64r2, "mips64r2", "Mips64r2 ISA Support", "mips64r2", &[_]@This() {
176		.Mips3_32,
177		.Fp64,
178		.Mips4_32r2,
	176	.Mips5_32r2,
179	177	.Mips3_32r2,
180		.Mips1,
181		.Mips4_32,
	178	.Mips4_32r2,
182	179	.Gp64,
183		.Mips5_32r2,
	180	.Fp64,
	181	.Mips4_32,
	182	.Mips1,
	183	.Mips3_32,
184	184	}),
185	185	FeatureInfo(@This()).createWithSubfeatures(.Mips64r3, "mips64r3", "Mips64r3 ISA Support", "mips64r3", &[_]@This() {
186		.Mips3_32,
187		.Fp64,
188		.Mips4_32r2,
	186	.Mips5_32r2,
189	187	.Mips3_32r2,
190		.Mips1,
191		.Mips4_32,
	188	.Mips4_32r2,
192	189	.Gp64,
193		.Mips5_32r2,
	190	.Fp64,
	191	.Mips4_32,
	192	.Mips1,
	193	.Mips3_32,
194	194	}),
195	195	FeatureInfo(@This()).createWithSubfeatures(.Mips64r5, "mips64r5", "Mips64r5 ISA Support", "mips64r5", &[_]@This() {
196		.Mips3_32,
197		.Fp64,
198		.Mips4_32r2,
	196	.Mips5_32r2,
199	197	.Mips3_32r2,
200		.Mips1,
201		.Mips4_32,
	198	.Mips4_32r2,
202	199	.Gp64,
203		.Mips5_32r2,
	200	.Fp64,
	201	.Mips4_32,
	202	.Mips1,
	203	.Mips3_32,
204	204	}),
205	205	FeatureInfo(@This()).createWithSubfeatures(.Mips64r6, "mips64r6", "Mips64r6 ISA Support [experimental]", "mips64r6", &[_]@This() {
206		.Mips3_32,
207		.Fp64,
208		.Mips4_32r2,
209		.Abs2008,
	206	.Mips5_32r2,
210	207	.Mips3_32r2,
211		.Mips1,
212		.Mips4_32,
213	208	.Nan2008,
	209	.Abs2008,
	210	.Mips4_32r2,
	211	.Fp64,
214	212	.Gp64,
215		.Mips5_32r2,
	213	.Mips4_32,
	214	.Mips1,
	215	.Mips3_32,
216	216	}),
217	217	FeatureInfo(@This()).create(.Nan2008, "nan2008", "IEEE 754-2008 NaN encoding", "nan2008"),
218	218	FeatureInfo(@This()).create(.Noabicalls, "noabicalls", "Disable SVR4-style position-independent code", "noabicalls"),
...	...	@@ -227,12 +227,12 @@ pub const MipsFeature = enum {
227	227	FeatureInfo(@This()).create(.Virt, "virt", "Mips Virtualization ASE", "virt"),
228	228	FeatureInfo(@This()).create(.Xgot, "xgot", "Assume 32-bit GOT", "xgot"),
229	229	FeatureInfo(@This()).createWithSubfeatures(.P5600, "p5600", "The P5600 Processor", "p5600", &[_]@This() {
230		.Mips3_32,
231		.Mips4_32r2,
	230	.Mips5_32r2,
232	231	.Mips3_32r2,
233		.Mips1,
	232	.Mips4_32r2,
234	233	.Mips4_32,
235		.Mips5_32r2,
	234	.Mips1,
	235	.Mips3_32,
236	236	}),
237	237	};
238	238	};

lib/std/target/feature/Msp430Feature.zig+1-1

...	...	@@ -6,7 +6,7 @@ pub const Msp430Feature = enum {
6	6	Hwmultf5,
7	7	Ext,
8	8
9		pub fn getInfo(self: @This()) FeatureInfo {
	9	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
10	10	return feature_infos[@enumToInt(self)];
11	11	}
12	12

lib/std/target/feature/NvptxFeature.zig+1-1

...	...	@@ -27,7 +27,7 @@ pub const NvptxFeature = enum {
27	27	Sm_72,
28	28	Sm_75,
29	29
30		pub fn getInfo(self: @This()) FeatureInfo {
	30	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
31	31	return feature_infos[@enumToInt(self)];
32	32	}
33	33

lib/std/target/feature/PowerPcFeature.zig+1-1

...	...	@@ -53,7 +53,7 @@ pub const PowerPcFeature = enum {
53	53	Vsx,
54	54	VectorsUseTwoUnits,
55	55
56		pub fn getInfo(self: @This()) FeatureInfo {
	56	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
57	57	return feature_infos[@enumToInt(self)];
58	58	}
59	59

lib/std/target/feature/RiscVFeature.zig+1-1

...	...	@@ -11,7 +11,7 @@ pub const RiscVFeature = enum {
11	11	F,
12	12	M,
13	13
14		pub fn getInfo(self: @This()) FeatureInfo {
	14	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
15	15	return feature_infos[@enumToInt(self)];
16	16	}
17	17

lib/std/target/feature/SparcFeature.zig+1-1

...	...	@@ -21,7 +21,7 @@ pub const SparcFeature = enum {
21	21	Hasumacsmac,
22	22	Popc,
23	23
24		pub fn getInfo(self: @This()) FeatureInfo {
	24	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
25	25	return feature_infos[@enumToInt(self)];
26	26	}
27	27

lib/std/target/feature/SystemZFeature.zig+1-1

...	...	@@ -37,7 +37,7 @@ pub const SystemZFeature = enum {
37	37	VectorPackedDecimal,
38	38	VectorPackedDecimalEnhancement,
39	39
40		pub fn getInfo(self: @This()) FeatureInfo {
	40	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
41	41	return feature_infos[@enumToInt(self)];
42	42	}
43	43

lib/std/target/feature/WebAssemblyFeature.zig+1-1

...	...	@@ -12,7 +12,7 @@ pub const WebAssemblyFeature = enum {
12	12	TailCall,
13	13	UnimplementedSimd128,
14	14
15		pub fn getInfo(self: @This()) FeatureInfo {
	15	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
16	16	return feature_infos[@enumToInt(self)];
17	17	}
18	18

lib/std/target/feature/X86Feature.zig+2-2

...	...	@@ -128,7 +128,7 @@ pub const X86Feature = enum {
128	128	BitMode32,
129	129	BitMode64,
130	130
131		pub fn getInfo(self: @This()) FeatureInfo {
	131	pub fn getInfo(self: @This()) FeatureInfo(@This()) {
132	132	return feature_infos[@enumToInt(self)];
133	133	}
134	134
...	...	@@ -254,8 +254,8 @@ pub const X86Feature = enum {
254	254	FeatureInfo(@This()).create(.Rdseed, "rdseed", "Support RDSEED instruction", "rdseed"),
255	255	FeatureInfo(@This()).create(.Rtm, "rtm", "Support RTM instructions", "rtm"),
256	256	FeatureInfo(@This()).createWithSubfeatures(.Retpoline, "retpoline", "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", "retpoline", &[_]@This() {
257		.RetpolineIndirectBranches,
258	257	.RetpolineIndirectCalls,
	258	.RetpolineIndirectBranches,
259	259	}),
260	260	FeatureInfo(@This()).createWithSubfeatures(.RetpolineExternalThunk, "retpoline-external-thunk", "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", "retpoline-external-thunk", &[_]@This() {
261	261	.RetpolineIndirectCalls,

lib/std/target/feature/empty.zig+2-2

...	...	@@ -1,5 +1,5 @@
1	1	const FeatureInfo = @import("std").target.feature.FeatureInfo;
2	2
3		pub const EmptyFeature = enum {
	3	pub const EmptyFeature = struct {
4	4	pub const feature_infos = [0]FeatureInfo(@This()) {};
5		}
	5	};