| ... | ... | @@ -343,27 +343,46 @@ fn _start() callconv(.naked) noreturn { |
| 343 | 343 | \\ subu $sp, $sp, 16 |
| 344 | 344 | \\ jalr $t9 |
| 345 | 345 | , |
| 346 | | .mips64, .mips64el => |
| 347 | | \\ move $fp, $zero |
| 348 | | // This is needed because early MIPS versions don't support misaligned loads. Without |
| 349 | | // this directive, the hidden `nop` inserted to fill the delay slot after `bal` would |
| 350 | | // cause the two doublewords to be aligned to 4 bytes instead of 8. |
| 351 | | \\ .balign 8 |
| 352 | | \\ bal 1f |
| 353 | | \\ .gpdword . |
| 354 | | \\ .gpdword %[posixCallMainAndExit] |
| 355 | | \\1: |
| 356 | | // The `gp` register on MIPS serves a similar purpose to `r2` (ToC pointer) on PPC64. |
| 357 | | \\ ld $gp, 0($ra) |
| 358 | | \\ dsubu $gp, $ra, $gp |
| 359 | | \\ ld $t9, 8($ra) |
| 360 | | \\ daddu $t9, $t9, $gp |
| 361 | | \\ move $ra, $zero |
| 362 | | \\ move $a0, $sp |
| 363 | | \\ and $sp, -16 |
| 364 | | \\ dsubu $sp, $sp, 16 |
| 365 | | \\ jalr $t9 |
| 366 | | , |
| 346 | .mips64, .mips64el => switch (builtin.abi) { |
| 347 | .gnuabin32, .muslabin32 => |
| 348 | \\ move $fp, $zero |
| 349 | \\ bal 1f |
| 350 | \\ .gpword . |
| 351 | \\ .gpword %[posixCallMainAndExit] |
| 352 | \\1: |
| 353 | // The `gp` register on MIPS serves a similar purpose to `r2` (ToC pointer) on PPC64. |
| 354 | \\ lw $gp, 0($ra) |
| 355 | \\ subu $gp, $ra, $gp |
| 356 | \\ lw $t9, 4($ra) |
| 357 | \\ addu $t9, $t9, $gp |
| 358 | \\ move $ra, $zero |
| 359 | \\ move $a0, $sp |
| 360 | \\ and $sp, -8 |
| 361 | \\ subu $sp, $sp, 16 |
| 362 | \\ jalr $t9 |
| 363 | , |
| 364 | else => |
| 365 | \\ move $fp, $zero |
| 366 | // This is needed because early MIPS versions don't support misaligned loads. Without |
| 367 | // this directive, the hidden `nop` inserted to fill the delay slot after `bal` would |
| 368 | // cause the two doublewords to be aligned to 4 bytes instead of 8. |
| 369 | \\ .balign 8 |
| 370 | \\ bal 1f |
| 371 | \\ .gpdword . |
| 372 | \\ .gpdword %[posixCallMainAndExit] |
| 373 | \\1: |
| 374 | // The `gp` register on MIPS serves a similar purpose to `r2` (ToC pointer) on PPC64. |
| 375 | \\ ld $gp, 0($ra) |
| 376 | \\ dsubu $gp, $ra, $gp |
| 377 | \\ ld $t9, 8($ra) |
| 378 | \\ daddu $t9, $t9, $gp |
| 379 | \\ move $ra, $zero |
| 380 | \\ move $a0, $sp |
| 381 | \\ and $sp, -16 |
| 382 | \\ dsubu $sp, $sp, 16 |
| 383 | \\ jalr $t9 |
| 384 | , |
| 385 | }, |
| 367 | 386 | .powerpc, .powerpcle => |
| 368 | 387 | // Set up the initial stack frame, and clear the back chain pointer. |
| 369 | 388 | // r1 = SP, r31 = FP |
Alex Rønne Petersen <alex@alexrp.com> 2025-10-18 12:11:27+02:00
Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM
lib