authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-02-16 00:48:22+01:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-02-19 12:04:54+01:00
log23915c2c444b257009816d00c15d6f2475a161b0
treefb714f87d739708eb049ab8d399e90ff3580b023
parent2f0204aca303daf899a97c740719a62398adc206
signature Commit is signed but in an unrecognized format.

stage2 ARM: simplify invocations of genInlineMemcpy

1 files changed, 4 insertions(+), 45 deletions(-)

src/arch/arm/CodeGen.zig+4-45
......@@ -1499,31 +1499,10 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14991499 const tmp_reg = regs[3];
15001500
15011501 // sub dst_reg, fp, #off
1502 const adj_off = off + elem_size;
1503 const offset_op: Instruction.Operand = if (Instruction.Operand.fromU32(adj_off)) |x| x else {
1504 return self.fail("TODO load: set reg to stack offset with all possible offsets", .{});
1505 };
1506 _ = try self.addInst(.{
1507 .tag = .sub,
1508 .data = .{ .rr_op = .{
1509 .rd = dst_reg,
1510 .rn = .fp,
1511 .op = offset_op,
1512 } },
1513 });
1502 try self.genSetReg(ptr_ty, dst_reg, .{ .ptr_stack_offset = off });
15141503
15151504 // mov len, #elem_size
1516 const len_op: Instruction.Operand = if (Instruction.Operand.fromU32(elem_size)) |x| x else {
1517 return self.fail("TODO load: set reg to elem_size with all possible sizes", .{});
1518 };
1519 _ = try self.addInst(.{
1520 .tag = .mov,
1521 .data = .{ .rr_op = .{
1522 .rd = len_reg,
1523 .rn = .r0,
1524 .op = len_op,
1525 } },
1526 });
1505 try self.genSetReg(Type.usize, len_reg, .{ .immediate = elem_size });
15271506
15281507 // memcpy(src, dst, len)
15291508 try self.genInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
......@@ -3342,17 +3321,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
33423321 });
33433322
33443323 // mov len, #abi_size
3345 const len_op: Instruction.Operand = if (Instruction.Operand.fromU32(abi_size)) |x| x else {
3346 return self.fail("TODO load: set reg to elem_size with all possible sizes", .{});
3347 };
3348 _ = try self.addInst(.{
3349 .tag = .mov,
3350 .data = .{ .rr_op = .{
3351 .rd = len_reg,
3352 .rn = .r0,
3353 .op = len_op,
3354 } },
3355 });
3324 try self.genSetReg(Type.usize, len_reg, .{ .immediate = abi_size });
33563325
33573326 // memcpy(src, dst, len)
33583327 try self.genInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);
......@@ -3738,17 +3707,7 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
37383707 });
37393708
37403709 // mov len, #abi_size
3741 const len_op: Instruction.Operand = if (Instruction.Operand.fromU32(abi_size)) |x| x else {
3742 return self.fail("TODO load: set reg to elem_size with all possible sizes", .{});
3743 };
3744 _ = try self.addInst(.{
3745 .tag = .mov,
3746 .data = .{ .rr_op = .{
3747 .rd = len_reg,
3748 .rn = .r0,
3749 .op = len_op,
3750 } },
3751 });
3710 try self.genSetReg(Type.usize, len_reg, .{ .immediate = abi_size });
37523711
37533712 // memcpy(src, dst, len)
37543713 try self.genInlineMemcpy(src_reg, dst_reg, len_reg, count_reg, tmp_reg);