authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 02:51:35-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-27 02:51:35-07:00
log280195038a8f3a364ff95adb5d3799f586e5b695
treeb80510e9735b396dd6b79cad984ee8bd50aebc46
parent9e8943736e34d28d1ea62229d6ca708303cd0eba

std.Target: add powerpcle

3 files changed, 12 insertions(+), 6 deletions(-)

lib/std/target.zig+10-6
......@@ -722,6 +722,7 @@ pub const Target = struct {
722722 mips64el,
723723 msp430,
724724 powerpc,
725 powerpcle,
725726 powerpc64,
726727 powerpc64le,
727728 r600,
......@@ -832,7 +833,7 @@ pub const Target = struct {
832833 .le32 => ._NONE,
833834 .mips => ._MIPS,
834835 .mipsel => ._MIPS_RS3_LE,
835 .powerpc => ._PPC,
836 .powerpc, .powerpcle => ._PPC,
836837 .r600 => ._NONE,
837838 .riscv32 => ._RISCV,
838839 .sparc => ._SPARC,
......@@ -892,7 +893,7 @@ pub const Target = struct {
892893 .le32 => .Unknown,
893894 .mips => .Unknown,
894895 .mipsel => .Unknown,
895 .powerpc => .POWERPC,
896 .powerpc, .powerpcle => .POWERPC,
896897 .r600 => .Unknown,
897898 .riscv32 => .RISCV32,
898899 .sparc => .Unknown,
......@@ -965,6 +966,7 @@ pub const Target = struct {
965966 .nvptx64,
966967 .sparcel,
967968 .tcele,
969 .powerpcle,
968970 .powerpc64le,
969971 .r600,
970972 .riscv32,
......@@ -1021,6 +1023,7 @@ pub const Target = struct {
10211023 .mips,
10221024 .mipsel,
10231025 .powerpc,
1026 .powerpcle,
10241027 .r600,
10251028 .riscv32,
10261029 .sparc,
......@@ -1077,7 +1080,7 @@ pub const Target = struct {
10771080 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",
10781081 .bpfel, .bpfeb => "bpf",
10791082 .mips, .mipsel, .mips64, .mips64el => "mips",
1080 .powerpc, .powerpc64, .powerpc64le => "powerpc",
1083 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
10811084 .amdgcn => "amdgpu",
10821085 .riscv32, .riscv64 => "riscv",
10831086 .sparc, .sparcv9, .sparcel => "sparc",
......@@ -1100,7 +1103,7 @@ pub const Target = struct {
11001103 .hexagon => &hexagon.all_features,
11011104 .mips, .mipsel, .mips64, .mips64el => &mips.all_features,
11021105 .msp430 => &msp430.all_features,
1103 .powerpc, .powerpc64, .powerpc64le => &powerpc.all_features,
1106 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
11041107 .amdgcn => &amdgpu.all_features,
11051108 .riscv32, .riscv64 => &riscv.all_features,
11061109 .sparc, .sparcv9, .sparcel => &sparc.all_features,
......@@ -1124,7 +1127,7 @@ pub const Target = struct {
11241127 .hexagon => comptime allCpusFromDecls(hexagon.cpu),
11251128 .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),
11261129 .msp430 => comptime allCpusFromDecls(msp430.cpu),
1127 .powerpc, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
1130 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
11281131 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
11291132 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
11301133 .sparc, .sparcv9, .sparcel => comptime allCpusFromDecls(sparc.cpu),
......@@ -1181,6 +1184,7 @@ pub const Target = struct {
11811184 .mips64, .mips64el => &mips.cpu.mips64,
11821185 .msp430 => &msp430.cpu.generic,
11831186 .powerpc => &powerpc.cpu.ppc32,
1187 .powerpcle => &powerpc.cpu.ppc32,
11841188 .powerpc64 => &powerpc.cpu.ppc64,
11851189 .powerpc64le => &powerpc.cpu.ppc64le,
11861190 .amdgcn => &amdgpu.cpu.generic,
......@@ -1496,7 +1500,7 @@ pub const Target = struct {
14961500 return print(&result, "/lib{s}/{s}", .{ lib_suffix, loader });
14971501 },
14981502
1499 .powerpc => return copy(&result, "/lib/ld.so.1"),
1503 .powerpc, .powerpcle => return copy(&result, "/lib/ld.so.1"),
15001504 .powerpc64, .powerpc64le => return copy(&result, "/lib64/ld64.so.2"),
15011505 .s390x => return copy(&result, "/lib64/ld64.so.1"),
15021506 .sparcv9 => return copy(&result, "/lib64/ld-linux.so.2"),
src/codegen/llvm.zig+1
......@@ -34,6 +34,7 @@ pub fn targetTriple(allocator: *Allocator, target: std.Target) ![:0]u8 {
3434 .mips64el => "mips64el",
3535 .msp430 => "msp430",
3636 .powerpc => "powerpc",
37 .powerpcle => "powerpcle",
3738 .powerpc64 => "powerpc64",
3839 .powerpc64le => "powerpc64le",
3940 .r600 => "r600",
src/target.zig+1
......@@ -246,6 +246,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
246246 .mips64el => .mips64el,
247247 .msp430 => .msp430,
248248 .powerpc => .ppc,
249 .powerpcle => .ppcle,
249250 .powerpc64 => .ppc64,
250251 .powerpc64le => .ppc64le,
251252 .r600 => .r600,