| ... | @@ -5,6 +5,7 @@ | ... | @@ -5,6 +5,7 @@ |
| 5 | // and substantial portions of the software. | 5 | // and substantial portions of the software. |
| 6 | usingnamespace std.os; | 6 | usingnamespace std.os; |
| 7 | const std = @import("../../std.zig"); | 7 | const std = @import("../../std.zig"); |
| | 8 | const builtin = @import("builtin"); |
| 8 | const expectEqual = std.testing.expectEqual; | 9 | const expectEqual = std.testing.expectEqual; |
| 9 | | 10 | |
| 10 | // instruction classes | 11 | // instruction classes |
| ... | @@ -328,6 +329,8 @@ pub const Helper = enum(i32) { | ... | @@ -328,6 +329,8 @@ pub const Helper = enum(i32) { |
| 328 | _, | 329 | _, |
| 329 | }; | 330 | }; |
| 330 | | 331 | |
| | 332 | // TODO: determine that this is the expected bit layout for both little and big |
| | 333 | // endian systems |
| 331 | /// a single BPF instruction | 334 | /// a single BPF instruction |
| 332 | pub const Insn = packed struct { | 335 | pub const Insn = packed struct { |
| 333 | code: u8, | 336 | code: u8, |
| ... | @@ -340,19 +343,30 @@ pub const Insn = packed struct { | ... | @@ -340,19 +343,30 @@ pub const Insn = packed struct { |
| 340 | /// frame | 343 | /// frame |
| 341 | pub const Reg = packed enum(u4) { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 }; | 344 | pub const Reg = packed enum(u4) { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 }; |
| 342 | const Source = packed enum(u1) { reg, imm }; | 345 | const Source = packed enum(u1) { reg, imm }; |
| | 346 | |
| | 347 | const Mode = packed enum(u8) { |
| | 348 | imm = IMM, |
| | 349 | abs = ABS, |
| | 350 | ind = IND, |
| | 351 | mem = MEM, |
| | 352 | len = LEN, |
| | 353 | msh = MSH, |
| | 354 | }; |
| | 355 | |
| 343 | const AluOp = packed enum(u8) { | 356 | const AluOp = packed enum(u8) { |
| 344 | add = ADD, | 357 | add = ADD, |
| 345 | sub = SUB, | 358 | sub = SUB, |
| 346 | mul = MUL, | 359 | mul = MUL, |
| 347 | div = DIV, | 360 | div = DIV, |
| 348 | op_or = OR, | 361 | alu_or = OR, |
| 349 | op_and = AND, | 362 | alu_and = AND, |
| 350 | lsh = LSH, | 363 | lsh = LSH, |
| 351 | rsh = RSH, | 364 | rsh = RSH, |
| 352 | neg = NEG, | 365 | neg = NEG, |
| 353 | mod = MOD, | 366 | mod = MOD, |
| 354 | xor = XOR, | 367 | xor = XOR, |
| 355 | mov = MOV, | 368 | mov = MOV, |
| | 369 | arsh = ARSH, |
| 356 | }; | 370 | }; |
| 357 | | 371 | |
| 358 | pub const Size = packed enum(u8) { | 372 | pub const Size = packed enum(u8) { |
| ... | @@ -368,6 +382,13 @@ pub const Insn = packed struct { | ... | @@ -368,6 +382,13 @@ pub const Insn = packed struct { |
| 368 | jgt = JGT, | 382 | jgt = JGT, |
| 369 | jge = JGE, | 383 | jge = JGE, |
| 370 | jset = JSET, | 384 | jset = JSET, |
| | 385 | jlt = JLT, |
| | 386 | jle = JLE, |
| | 387 | jne = JNE, |
| | 388 | jsgt = JSGT, |
| | 389 | jsge = JSGE, |
| | 390 | jslt = JSLT, |
| | 391 | jsle = JSLE, |
| 371 | }; | 392 | }; |
| 372 | | 393 | |
| 373 | const ImmOrReg = union(Source) { | 394 | const ImmOrReg = union(Source) { |
| ... | @@ -419,14 +440,102 @@ pub const Insn = packed struct { | ... | @@ -419,14 +440,102 @@ pub const Insn = packed struct { |
| 419 | return alu(64, .add, dst, src); | 440 | return alu(64, .add, dst, src); |
| 420 | } | 441 | } |
| 421 | | 442 | |
| | 443 | pub fn sub(dst: Reg, src: anytype) Insn { |
| | 444 | return alu(64, .sub, dst, src); |
| | 445 | } |
| | 446 | |
| | 447 | pub fn mul(dst: Reg, src: anytype) Insn { |
| | 448 | return alu(64, .mul, dst, src); |
| | 449 | } |
| | 450 | |
| | 451 | pub fn div(dst: Reg, src: anytype) Insn { |
| | 452 | return alu(64, .div, dst, src); |
| | 453 | } |
| | 454 | |
| | 455 | pub fn alu_or(dst: Reg, src: anytype) Insn { |
| | 456 | return alu(64, .alu_or, dst, src); |
| | 457 | } |
| | 458 | |
| | 459 | pub fn alu_and(dst: Reg, src: anytype) Insn { |
| | 460 | return alu(64, .alu_and, dst, src); |
| | 461 | } |
| | 462 | |
| | 463 | pub fn lsh(dst: Reg, src: anytype) Insn { |
| | 464 | return alu(64, .lsh, dst, src); |
| | 465 | } |
| | 466 | |
| | 467 | pub fn rsh(dst: Reg, src: anytype) Insn { |
| | 468 | return alu(64, .rsh, dst, src); |
| | 469 | } |
| | 470 | |
| | 471 | pub fn neg(dst: Reg) Insn { |
| | 472 | return alu(64, .neg, dst, 0); |
| | 473 | } |
| | 474 | |
| | 475 | pub fn mod(dst: Reg, src: anytype) Insn { |
| | 476 | return alu(64, .mod, dst, src); |
| | 477 | } |
| | 478 | |
| | 479 | pub fn xor(dst: Reg, src: anytype) Insn { |
| | 480 | return alu(64, .xor, dst, src); |
| | 481 | } |
| | 482 | |
| | 483 | pub fn arsh(dst: Reg, src: anytype) Insn { |
| | 484 | return alu(64, .arsh, dst, src); |
| | 485 | } |
| | 486 | |
| 422 | fn jmp(op: JmpOp, dst: Reg, src: anytype, off: i16) Insn { | 487 | fn jmp(op: JmpOp, dst: Reg, src: anytype, off: i16) Insn { |
| 423 | return imm_reg(JMP | @enumToInt(op), dst, src, off); | 488 | return imm_reg(JMP | @enumToInt(op), dst, src, off); |
| 424 | } | 489 | } |
| 425 | | 490 | |
| | 491 | pub fn ja(off: i16) Insn { |
| | 492 | return jmp(.ja, .r0, 0, off); |
| | 493 | } |
| | 494 | |
| 426 | pub fn jeq(dst: Reg, src: anytype, off: i16) Insn { | 495 | pub fn jeq(dst: Reg, src: anytype, off: i16) Insn { |
| 427 | return jmp(.jeq, dst, src, off); | 496 | return jmp(.jeq, dst, src, off); |
| 428 | } | 497 | } |
| 429 | | 498 | |
| | 499 | pub fn jgt(dst: Reg, src: anytype, off: i16) Insn { |
| | 500 | return jmp(.jgt, dst, src, off); |
| | 501 | } |
| | 502 | |
| | 503 | pub fn jge(dst: Reg, src: anytype, off: i16) Insn { |
| | 504 | return jmp(.jge, dst, src, off); |
| | 505 | } |
| | 506 | |
| | 507 | pub fn jlt(dst: Reg, src: anytype, off: i16) Insn { |
| | 508 | return jmp(.jlt, dst, src, off); |
| | 509 | } |
| | 510 | |
| | 511 | pub fn jle(dst: Reg, src: anytype, off: i16) Insn { |
| | 512 | return jmp(.jle, dst, src, off); |
| | 513 | } |
| | 514 | |
| | 515 | pub fn jset(dst: Reg, src: anytype, off: i16) Insn { |
| | 516 | return jmp(.jset, dst, src, off); |
| | 517 | } |
| | 518 | |
| | 519 | pub fn jne(dst: Reg, src: anytype, off: i16) Insn { |
| | 520 | return jmp(.jne, dst, src, off); |
| | 521 | } |
| | 522 | |
| | 523 | pub fn jsgt(dst: Reg, src: anytype, off: i16) Insn { |
| | 524 | return jmp(.jsgt, dst, src, off); |
| | 525 | } |
| | 526 | |
| | 527 | pub fn jsge(dst: Reg, src: anytype, off: i16) Insn { |
| | 528 | return jmp(.jsge, dst, src, off); |
| | 529 | } |
| | 530 | |
| | 531 | pub fn jslt(dst: Reg, src: anytype, off: i16) Insn { |
| | 532 | return jmp(.jslt, dst, src, off); |
| | 533 | } |
| | 534 | |
| | 535 | pub fn jsle(dst: Reg, src: anytype, off: i16) Insn { |
| | 536 | return jmp(.jsle, dst, src, off); |
| | 537 | } |
| | 538 | |
| 430 | pub fn stx_mem(size: Size, dst: Reg, src: Reg, off: i16) Insn { | 539 | pub fn stx_mem(size: Size, dst: Reg, src: Reg, off: i16) Insn { |
| 431 | return Insn{ | 540 | return Insn{ |
| 432 | .code = STX | @enumToInt(size) | MEM, | 541 | .code = STX | @enumToInt(size) | MEM, |
| ... | @@ -447,17 +556,34 @@ pub const Insn = packed struct { | ... | @@ -447,17 +556,34 @@ pub const Insn = packed struct { |
| 447 | }; | 556 | }; |
| 448 | } | 557 | } |
| 449 | | 558 | |
| 450 | /// direct packet access, R0 = *(uint *)(skb->data + imm32) | 559 | fn ld(mode: Mode, size: Size, dst: Reg, src: Reg, imm: i32) Insn { |
| 451 | pub fn ld_abs(size: Size, imm: i32) Insn { | | |
| 452 | return Insn{ | 560 | return Insn{ |
| 453 | .code = LD | @enumToInt(size) | ABS, | 561 | .code = @enumToInt(mode) | @enumToInt(size) | LD, |
| 454 | .dst = 0, | 562 | .dst = @enumToInt(dst), |
| 455 | .src = 0, | 563 | .src = @enumToInt(src), |
| 456 | .off = 0, | 564 | .off = 0, |
| 457 | .imm = imm, | 565 | .imm = imm, |
| 458 | }; | 566 | }; |
| 459 | } | 567 | } |
| 460 | | 568 | |
| | 569 | pub fn ld_abs(size: Size, dst: Reg, src: Reg, imm: i32) Insn { |
| | 570 | return ld(.abs, size, dst, src, imm); |
| | 571 | } |
| | 572 | |
| | 573 | pub fn ld_ind(size: Size, dst: Reg, src: Reg, imm: i32) Insn { |
| | 574 | return ld(.ind, size, dst, src, imm); |
| | 575 | } |
| | 576 | |
| | 577 | pub fn ldx(size: Size, dst: Reg, src: Reg, off: i16) Insn { |
| | 578 | return Insn{ |
| | 579 | .code = MEM | @enumToInt(size) | LDX, |
| | 580 | .dst = @enumToInt(dst), |
| | 581 | .src = @enumToInt(src), |
| | 582 | .off = off, |
| | 583 | .imm = 0, |
| | 584 | }; |
| | 585 | } |
| | 586 | |
| 461 | fn ld_imm_impl1(dst: Reg, src: Reg, imm: u64) Insn { | 587 | fn ld_imm_impl1(dst: Reg, src: Reg, imm: u64) Insn { |
| 462 | return Insn{ | 588 | return Insn{ |
| 463 | .code = LD | DW | IMM, | 589 | .code = LD | DW | IMM, |
| ... | @@ -478,6 +604,14 @@ pub const Insn = packed struct { | ... | @@ -478,6 +604,14 @@ pub const Insn = packed struct { |
| 478 | }; | 604 | }; |
| 479 | } | 605 | } |
| 480 | | 606 | |
| | 607 | pub fn ld_dw1(dst: Reg, imm: u64) Insn { |
| | 608 | return ld_imm_impl1(dst, .r0, imm); |
| | 609 | } |
| | 610 | |
| | 611 | pub fn ld_dw2(imm: u64) Insn { |
| | 612 | return ld_imm_impl2(imm); |
| | 613 | } |
| | 614 | |
| 481 | pub fn ld_map_fd1(dst: Reg, map_fd: fd_t) Insn { | 615 | pub fn ld_map_fd1(dst: Reg, map_fd: fd_t) Insn { |
| 482 | return ld_imm_impl1(dst, @intToEnum(Reg, PSEUDO_MAP_FD), @intCast(u64, map_fd)); | 616 | return ld_imm_impl1(dst, @intToEnum(Reg, PSEUDO_MAP_FD), @intCast(u64, map_fd)); |
| 483 | } | 617 | } |
| ... | @@ -486,6 +620,53 @@ pub const Insn = packed struct { | ... | @@ -486,6 +620,53 @@ pub const Insn = packed struct { |
| 486 | return ld_imm_impl2(@intCast(u64, map_fd)); | 620 | return ld_imm_impl2(@intCast(u64, map_fd)); |
| 487 | } | 621 | } |
| 488 | | 622 | |
| | 623 | pub fn st(comptime size: Size, dst: Reg, off: i16, imm: i32) Insn { |
| | 624 | if (size == .double_word) @compileError("TODO: implement st_dw"); |
| | 625 | return Insn{ |
| | 626 | .code = MEM | @enumToInt(size) | ST, |
| | 627 | .dst = @enumToInt(dst), |
| | 628 | .src = 0, |
| | 629 | .off = off, |
| | 630 | .imm = imm, |
| | 631 | }; |
| | 632 | } |
| | 633 | |
| | 634 | pub fn stx(size: Size, dst: Reg, off: i16, src: Reg) Insn { |
| | 635 | return Insn{ |
| | 636 | .code = MEM | @enumToInt(size) | STX, |
| | 637 | .dst = @enumToInt(dst), |
| | 638 | .src = @enumToInt(src), |
| | 639 | .off = off, |
| | 640 | .imm = 0, |
| | 641 | }; |
| | 642 | } |
| | 643 | |
| | 644 | fn endian_swap(endian: builtin.Endian, comptime size: Size, dst: Reg) Insn { |
| | 645 | return Insn{ |
| | 646 | .code = switch (endian) { |
| | 647 | .Big => 0xdc, |
| | 648 | .Little => 0xd4, |
| | 649 | }, |
| | 650 | .dst = @enumToInt(dst), |
| | 651 | .src = 0, |
| | 652 | .off = 0, |
| | 653 | .imm = switch (size) { |
| | 654 | .byte => @compileError("can't swap a single byte"), |
| | 655 | .half_word => 16, |
| | 656 | .word => 32, |
| | 657 | .double_word => 64, |
| | 658 | }, |
| | 659 | }; |
| | 660 | } |
| | 661 | |
| | 662 | pub fn le(comptime size: Size, dst: Reg) Insn { |
| | 663 | return endian_swap(.Little, size, dst); |
| | 664 | } |
| | 665 | |
| | 666 | pub fn be(comptime size: Size, dst: Reg) Insn { |
| | 667 | return endian_swap(.Big, size, dst); |
| | 668 | } |
| | 669 | |
| 489 | pub fn call(helper: Helper) Insn { | 670 | pub fn call(helper: Helper) Insn { |
| 490 | return Insn{ | 671 | return Insn{ |
| 491 | .code = JMP | CALL, | 672 | .code = JMP | CALL, |
| ... | @@ -508,59 +689,122 @@ pub const Insn = packed struct { | ... | @@ -508,59 +689,122 @@ pub const Insn = packed struct { |
| 508 | } | 689 | } |
| 509 | }; | 690 | }; |
| 510 | | 691 | |
| 511 | fn expect_insn(insn: Insn, val: u64) void { | | |
| 512 | expectEqual(@bitCast(u64, insn), val); | | |
| 513 | } | | |
| 514 | | | |
| 515 | test "insn bitsize" { | 692 | test "insn bitsize" { |
| 516 | expectEqual(@bitSizeOf(Insn), 64); | 693 | expectEqual(@bitSizeOf(Insn), 64); |
| 517 | } | 694 | } |
| 518 | | 695 | |
| 519 | // mov instructions | 696 | fn expect_opcode(code: u8, insn: Insn) void { |
| 520 | test "mov imm" { | 697 | expectEqual(code, insn.code); |
| 521 | expect_insn(Insn.mov(.r1, 1), 0x00000001000001b7); | | |
| 522 | } | | |
| 523 | | | |
| 524 | test "mov reg" { | | |
| 525 | expect_insn(Insn.mov(.r6, .r1), 0x00000000000016bf); | | |
| 526 | } | | |
| 527 | | | |
| 528 | // alu instructions | | |
| 529 | test "add imm" { | | |
| 530 | expect_insn(Insn.add(.r2, -4), 0xfffffffc00000207); | | |
| 531 | } | | |
| 532 | | | |
| 533 | // ld instructions | | |
| 534 | test "ld_abs" { | | |
| 535 | expect_insn(Insn.ld_abs(.byte, 42), 0x0000002a00000030); | | |
| 536 | } | | |
| 537 | | | |
| 538 | test "ld_map_fd" { | | |
| 539 | expect_insn(Insn.ld_map_fd1(.r1, 42), 0x0000002a00001118); | | |
| 540 | expect_insn(Insn.ld_map_fd2(42), 0x0000000000000000); | | |
| 541 | } | | |
| 542 | | | |
| 543 | // st instructions | | |
| 544 | test "stx_mem" { | | |
| 545 | expect_insn(Insn.stx_mem(.word, .r10, .r0, -4), 0x00000000fffc0a63); | | |
| 546 | } | | |
| 547 | | | |
| 548 | test "xadd" { | | |
| 549 | expect_insn(Insn.xadd(.r0, .r1), 0x00000000000010db); | | |
| 550 | } | | |
| 551 | | | |
| 552 | // jmp instructions | | |
| 553 | test "jeq imm" { | | |
| 554 | expect_insn(Insn.jeq(.r0, 0, 2), 0x0000000000020015); | | |
| 555 | } | | |
| 556 | | | |
| 557 | // other instructions | | |
| 558 | test "call" { | | |
| 559 | expect_insn(Insn.call(.map_lookup_elem), 0x0000000100000085); | | |
| 560 | } | 698 | } |
| 561 | | 699 | |
| 562 | test "exit" { | 700 | // The opcodes were grabbed from https://github.com/iovisor/bpf-docs/blob/master/eBPF.md |
| 563 | expect_insn(Insn.exit(), 0x0000000000000095); | 701 | test "opcodes" { |
| | 702 | // instructions that have a name that end with 1 or 2 are consecutive for |
| | 703 | // loading 64-bit immediates (imm is only 32 bits wide) |
| | 704 | |
| | 705 | // alu instructions |
| | 706 | expect_opcode(0x07, Insn.add(.r1, 0)); |
| | 707 | expect_opcode(0x0f, Insn.add(.r1, .r2)); |
| | 708 | expect_opcode(0x17, Insn.sub(.r1, 0)); |
| | 709 | expect_opcode(0x1f, Insn.sub(.r1, .r2)); |
| | 710 | expect_opcode(0x27, Insn.mul(.r1, 0)); |
| | 711 | expect_opcode(0x2f, Insn.mul(.r1, .r2)); |
| | 712 | expect_opcode(0x37, Insn.div(.r1, 0)); |
| | 713 | expect_opcode(0x3f, Insn.div(.r1, .r2)); |
| | 714 | expect_opcode(0x47, Insn.alu_or(.r1, 0)); |
| | 715 | expect_opcode(0x4f, Insn.alu_or(.r1, .r2)); |
| | 716 | expect_opcode(0x57, Insn.alu_and(.r1, 0)); |
| | 717 | expect_opcode(0x5f, Insn.alu_and(.r1, .r2)); |
| | 718 | expect_opcode(0x67, Insn.lsh(.r1, 0)); |
| | 719 | expect_opcode(0x6f, Insn.lsh(.r1, .r2)); |
| | 720 | expect_opcode(0x77, Insn.rsh(.r1, 0)); |
| | 721 | expect_opcode(0x7f, Insn.rsh(.r1, .r2)); |
| | 722 | expect_opcode(0x87, Insn.neg(.r1)); |
| | 723 | expect_opcode(0x97, Insn.mod(.r1, 0)); |
| | 724 | expect_opcode(0x9f, Insn.mod(.r1, .r2)); |
| | 725 | expect_opcode(0xa7, Insn.xor(.r1, 0)); |
| | 726 | expect_opcode(0xaf, Insn.xor(.r1, .r2)); |
| | 727 | expect_opcode(0xb7, Insn.mov(.r1, 0)); |
| | 728 | expect_opcode(0xbf, Insn.mov(.r1, .r2)); |
| | 729 | expect_opcode(0xc7, Insn.arsh(.r1, 0)); |
| | 730 | expect_opcode(0xcf, Insn.arsh(.r1, .r2)); |
| | 731 | |
| | 732 | // atomic instructions: might be more of these not documented in the wild |
| | 733 | expect_opcode(0xdb, Insn.xadd(.r1, .r2)); |
| | 734 | |
| | 735 | // TODO: byteswap instructions |
| | 736 | expect_opcode(0xd4, Insn.le(.half_word, .r1)); |
| | 737 | expectEqual(@intCast(i32, 16), Insn.le(.half_word, .r1).imm); |
| | 738 | expect_opcode(0xd4, Insn.le(.word, .r1)); |
| | 739 | expectEqual(@intCast(i32, 32), Insn.le(.word, .r1).imm); |
| | 740 | expect_opcode(0xd4, Insn.le(.double_word, .r1)); |
| | 741 | expectEqual(@intCast(i32, 64), Insn.le(.double_word, .r1).imm); |
| | 742 | expect_opcode(0xdc, Insn.be(.half_word, .r1)); |
| | 743 | expectEqual(@intCast(i32, 16), Insn.be(.half_word, .r1).imm); |
| | 744 | expect_opcode(0xdc, Insn.be(.word, .r1)); |
| | 745 | expectEqual(@intCast(i32, 32), Insn.be(.word, .r1).imm); |
| | 746 | expect_opcode(0xdc, Insn.be(.double_word, .r1)); |
| | 747 | expectEqual(@intCast(i32, 64), Insn.be(.double_word, .r1).imm); |
| | 748 | |
| | 749 | // memory instructions |
| | 750 | expect_opcode(0x18, Insn.ld_dw1(.r1, 0)); |
| | 751 | expect_opcode(0x00, Insn.ld_dw2(0)); |
| | 752 | |
| | 753 | // loading a map fd |
| | 754 | expect_opcode(0x18, Insn.ld_map_fd1(.r1, 0)); |
| | 755 | expectEqual(@intCast(u4, PSEUDO_MAP_FD), Insn.ld_map_fd1(.r1, 0).src); |
| | 756 | expect_opcode(0x00, Insn.ld_map_fd2(0)); |
| | 757 | |
| | 758 | expect_opcode(0x38, Insn.ld_abs(.double_word, .r1, .r2, 0)); |
| | 759 | expect_opcode(0x20, Insn.ld_abs(.word, .r1, .r2, 0)); |
| | 760 | expect_opcode(0x28, Insn.ld_abs(.half_word, .r1, .r2, 0)); |
| | 761 | expect_opcode(0x30, Insn.ld_abs(.byte, .r1, .r2, 0)); |
| | 762 | |
| | 763 | expect_opcode(0x58, Insn.ld_ind(.double_word, .r1, .r2, 0)); |
| | 764 | expect_opcode(0x40, Insn.ld_ind(.word, .r1, .r2, 0)); |
| | 765 | expect_opcode(0x48, Insn.ld_ind(.half_word, .r1, .r2, 0)); |
| | 766 | expect_opcode(0x50, Insn.ld_ind(.byte, .r1, .r2, 0)); |
| | 767 | |
| | 768 | expect_opcode(0x79, Insn.ldx(.double_word, .r1, .r2, 0)); |
| | 769 | expect_opcode(0x61, Insn.ldx(.word, .r1, .r2, 0)); |
| | 770 | expect_opcode(0x69, Insn.ldx(.half_word, .r1, .r2, 0)); |
| | 771 | expect_opcode(0x71, Insn.ldx(.byte, .r1, .r2, 0)); |
| | 772 | |
| | 773 | expect_opcode(0x62, Insn.st(.word, .r1, 0, 0)); |
| | 774 | expect_opcode(0x6a, Insn.st(.half_word, .r1, 0, 0)); |
| | 775 | expect_opcode(0x72, Insn.st(.byte, .r1, 0, 0)); |
| | 776 | |
| | 777 | expect_opcode(0x63, Insn.stx(.word, .r1, 0, .r2)); |
| | 778 | expect_opcode(0x6b, Insn.stx(.half_word, .r1, 0, .r2)); |
| | 779 | expect_opcode(0x73, Insn.stx(.byte, .r1, 0, .r2)); |
| | 780 | expect_opcode(0x7b, Insn.stx(.double_word, .r1, 0, .r2)); |
| | 781 | |
| | 782 | // branch instructions |
| | 783 | expect_opcode(0x05, Insn.ja(0)); |
| | 784 | expect_opcode(0x15, Insn.jeq(.r1, 0, 0)); |
| | 785 | expect_opcode(0x1d, Insn.jeq(.r1, .r2, 0)); |
| | 786 | expect_opcode(0x25, Insn.jgt(.r1, 0, 0)); |
| | 787 | expect_opcode(0x2d, Insn.jgt(.r1, .r2, 0)); |
| | 788 | expect_opcode(0x35, Insn.jge(.r1, 0, 0)); |
| | 789 | expect_opcode(0x3d, Insn.jge(.r1, .r2, 0)); |
| | 790 | expect_opcode(0xa5, Insn.jlt(.r1, 0, 0)); |
| | 791 | expect_opcode(0xad, Insn.jlt(.r1, .r2, 0)); |
| | 792 | expect_opcode(0xb5, Insn.jle(.r1, 0, 0)); |
| | 793 | expect_opcode(0xbd, Insn.jle(.r1, .r2, 0)); |
| | 794 | expect_opcode(0x45, Insn.jset(.r1, 0, 0)); |
| | 795 | expect_opcode(0x4d, Insn.jset(.r1, .r2, 0)); |
| | 796 | expect_opcode(0x55, Insn.jne(.r1, 0, 0)); |
| | 797 | expect_opcode(0x5d, Insn.jne(.r1, .r2, 0)); |
| | 798 | expect_opcode(0x65, Insn.jsgt(.r1, 0, 0)); |
| | 799 | expect_opcode(0x6d, Insn.jsgt(.r1, .r2, 0)); |
| | 800 | expect_opcode(0x75, Insn.jsge(.r1, 0, 0)); |
| | 801 | expect_opcode(0x7d, Insn.jsge(.r1, .r2, 0)); |
| | 802 | expect_opcode(0xc5, Insn.jslt(.r1, 0, 0)); |
| | 803 | expect_opcode(0xcd, Insn.jslt(.r1, .r2, 0)); |
| | 804 | expect_opcode(0xd5, Insn.jsle(.r1, 0, 0)); |
| | 805 | expect_opcode(0xdd, Insn.jsle(.r1, .r2, 0)); |
| | 806 | expect_opcode(0x85, Insn.call(.unspec)); |
| | 807 | expect_opcode(0x95, Insn.exit()); |
| 564 | } | 808 | } |
| 565 | | 809 | |
| 566 | pub const Cmd = extern enum(usize) { | 810 | pub const Cmd = extern enum(usize) { |
Matt Knight <mattnite@protonmail.com> 2020-09-06 16:12:27-07:00
Commit is signed but in an unrecognized format.
lib