| author |  Andrew Kelley <andrew@ziglang.org> 2020-02-26 12:37:13-05:00 |
| committer | Andrew Kelley <andrew@ziglang.org> 2020-02-26 12:37:13-05:00 |
| log | 2b33e27e1c72703deb50bef5c486b86130a75687 |
| tree | 88aacd682c7d7ec2c123089319c0dd901da61e99 |
| parent | 6291e8e4926c2e7dbd5cfa651f862c7dbd2e5bda |
| signature |  Commit is signed but in an unrecognized format. |
arm baseline CPU is v7a rather than v6m
v6m is thumb-mode and the baseline should probably be an 'a' variant.1 files changed, 1 insertions(+), 1 deletions(-)
lib- std
- target
lib/std/target/arm.zig+1-1
| ... | ... | @@ -1509,7 +1509,7 @@ pub const cpu = struct { |
| 1509 | 1509 | .name = "baseline", |
| 1510 | 1510 | .llvm_name = "generic", |
| 1511 | 1511 | .features = featureSet(&[_]Feature{ |
| 1512 | .v6m, | |
| 1512 | .v7a, | |
| 1513 | 1513 | }), |
| 1514 | 1514 | }; |
| 1515 | 1515 | pub const cortex_a12 = CpuModel{ |