| author | |
| committer | |
| log | 2c470d24b3c3c939a0ec20292b5d28d92c16b431 |
| tree | ce332a6d8d2e529cb187faae5d848c7791fa8ba2 |
| parent | 5358af7ba4cf16bef1734729646b99842e439916 |
| signature |
8 files changed, 139 insertions(+), 1 deletions(-)
lib/compiler/aro/aro/target.zig+4-1| ... | ... | @@ -477,6 +477,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { |
| 477 | 477 | .ve, |
| 478 | 478 | .bpfel, |
| 479 | 479 | .bpfeb, |
| 480 | .kvx, | |
| 480 | 481 | .s390x, |
| 481 | 482 | => return null, |
| 482 | 483 | |
| ... | ... | @@ -551,6 +552,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { |
| 551 | 552 | .nvptx64, |
| 552 | 553 | .wasm64, |
| 553 | 554 | .spirv64, |
| 555 | .kvx, | |
| 554 | 556 | .loongarch64, |
| 555 | 557 | .mips64, |
| 556 | 558 | .mips64el, |
| ... | ... | @@ -636,8 +638,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { |
| 636 | 638 | .wasm32 => "wasm32", |
| 637 | 639 | .wasm64 => "wasm64", |
| 638 | 640 | .ve => "ve", |
| 639 | // Note: propeller1, kalimba and or1k are not supported in LLVM; this is the Zig arch name | |
| 641 | // Note: propeller1, kalimba, kvx, and or1k are not supported in LLVM; this is the Zig arch name | |
| 640 | 642 | .kalimba => "kalimba", |
| 643 | .kvx => "kvx", | |
| 641 | 644 | .propeller => "propeller", |
| 642 | 645 | .or1k => "or1k", |
| 643 | 646 | }; |
lib/std/Target.zig+22| ... | ... | @@ -710,6 +710,7 @@ pub const csky = @import("Target/csky.zig"); |
| 710 | 710 | pub const hexagon = @import("Target/hexagon.zig"); |
| 711 | 711 | pub const hppa = @import("Target/generic.zig"); |
| 712 | 712 | pub const kalimba = @import("Target/generic.zig"); |
| 713 | pub const kvx = @import("Target/kvx.zig"); | |
| 713 | 714 | pub const lanai = @import("Target/lanai.zig"); |
| 714 | 715 | pub const loongarch = @import("Target/loongarch.zig"); |
| 715 | 716 | pub const m68k = @import("Target/m68k.zig"); |
| ... | ... | @@ -1043,6 +1044,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM { |
| 1043 | 1044 | .hexagon => .QDSP6, |
| 1044 | 1045 | .hppa, .hppa64 => .PARISC, |
| 1045 | 1046 | .kalimba => .CSR_KALIMBA, |
| 1047 | .kvx => .KVX, | |
| 1046 | 1048 | .lanai => .LANAI, |
| 1047 | 1049 | .loongarch32, .loongarch64 => .LOONGARCH, |
| 1048 | 1050 | .m68k => .@"68K", |
| ... | ... | @@ -1105,6 +1107,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE { |
| 1105 | 1107 | .hppa, |
| 1106 | 1108 | .hppa64, |
| 1107 | 1109 | .kalimba, |
| 1110 | .kvx, | |
| 1108 | 1111 | .lanai, |
| 1109 | 1112 | .m68k, |
| 1110 | 1113 | .microblaze, |
| ... | ... | @@ -1310,6 +1313,7 @@ pub const Cpu = struct { |
| 1310 | 1313 | hppa, |
| 1311 | 1314 | hppa64, |
| 1312 | 1315 | kalimba, |
| 1316 | kvx, | |
| 1313 | 1317 | lanai, |
| 1314 | 1318 | loongarch32, |
| 1315 | 1319 | loongarch64, |
| ... | ... | @@ -1385,6 +1389,7 @@ pub const Cpu = struct { |
| 1385 | 1389 | hexagon, |
| 1386 | 1390 | hppa, |
| 1387 | 1391 | kalimba, |
| 1392 | kvx, | |
| 1388 | 1393 | lanai, |
| 1389 | 1394 | loongarch, |
| 1390 | 1395 | m68k, |
| ... | ... | @@ -1420,6 +1425,7 @@ pub const Cpu = struct { |
| 1420 | 1425 | .hexagon => .hexagon, |
| 1421 | 1426 | .hppa, .hppa64 => .hppa, |
| 1422 | 1427 | .kalimba => .kalimba, |
| 1428 | .kvx => .kvx, | |
| 1423 | 1429 | .lanai => .lanai, |
| 1424 | 1430 | .loongarch32, .loongarch64 => .loongarch, |
| 1425 | 1431 | .m68k => .m68k, |
| ... | ... | @@ -1623,6 +1629,7 @@ pub const Cpu = struct { |
| 1623 | 1629 | .csky, |
| 1624 | 1630 | .hexagon, |
| 1625 | 1631 | .kalimba, |
| 1632 | .kvx, | |
| 1626 | 1633 | .loongarch32, |
| 1627 | 1634 | .loongarch64, |
| 1628 | 1635 | .microblazeel, |
| ... | ... | @@ -1847,6 +1854,10 @@ pub const Cpu = struct { |
| 1847 | 1854 | .hppa64_elf, |
| 1848 | 1855 | => &.{.hppa64}, |
| 1849 | 1856 | |
| 1857 | .kvx_lp64, | |
| 1858 | .kvx_ilp32, | |
| 1859 | => &.{.kvx}, | |
| 1860 | ||
| 1850 | 1861 | .lanai_sysv, |
| 1851 | 1862 | => &.{.lanai}, |
| 1852 | 1863 | |
| ... | ... | @@ -1936,6 +1947,7 @@ pub const Cpu = struct { |
| 1936 | 1947 | return switch (arch) { |
| 1937 | 1948 | .amdgcn => &amdgcn.cpu.gfx600, |
| 1938 | 1949 | .avr => &avr.cpu.avr1, |
| 1950 | .kvx => &kvx.cpu.coolidge_v1, | |
| 1939 | 1951 | .loongarch32 => &loongarch.cpu.generic_la32, |
| 1940 | 1952 | .loongarch64 => &loongarch.cpu.generic_la64, |
| 1941 | 1953 | .mips, .mipsel => &mips.cpu.mips32, |
| ... | ... | @@ -1987,6 +1999,7 @@ pub const Cpu = struct { |
| 1987 | 1999 | .bpfel, .bpfeb => &bpf.cpu.v3, |
| 1988 | 2000 | .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model. |
| 1989 | 2001 | .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model. |
| 2002 | .kvx => &kvx.cpu.coolidge_v2, | |
| 1990 | 2003 | .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. |
| 1991 | 2004 | .loongarch64 => &loongarch.cpu.la64v1_0, |
| 1992 | 2005 | .m68k => &m68k.cpu.M68000, |
| ... | ... | @@ -2440,6 +2453,7 @@ pub const DynamicLinker = struct { |
| 2440 | 2453 | .aarch64, |
| 2441 | 2454 | .aarch64_be, |
| 2442 | 2455 | .hexagon, |
| 2456 | .kvx, | |
| 2443 | 2457 | .m68k, |
| 2444 | 2458 | .microblaze, |
| 2445 | 2459 | .microblazeel, |
| ... | ... | @@ -2817,6 +2831,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 { |
| 2817 | 2831 | .bpfeb, |
| 2818 | 2832 | .bpfel, |
| 2819 | 2833 | .hppa64, |
| 2834 | .kvx, | |
| 2820 | 2835 | .loongarch64, |
| 2821 | 2836 | .mips64, |
| 2822 | 2837 | .mips64el, |
| ... | ... | @@ -3375,6 +3390,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 { |
| 3375 | 3390 | .aarch64_be, |
| 3376 | 3391 | .alpha, |
| 3377 | 3392 | .hppa64, |
| 3393 | .kvx, | |
| 3378 | 3394 | .loongarch32, |
| 3379 | 3395 | .loongarch64, |
| 3380 | 3396 | .mips64, |
| ... | ... | @@ -3482,6 +3498,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 { |
| 3482 | 3498 | .aarch64_be, |
| 3483 | 3499 | .alpha, |
| 3484 | 3500 | .hppa64, |
| 3501 | .kvx, | |
| 3485 | 3502 | .loongarch32, |
| 3486 | 3503 | .loongarch64, |
| 3487 | 3504 | .mips64, |
| ... | ... | @@ -3557,6 +3574,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 { |
| 3557 | 3574 | .bpfel, |
| 3558 | 3575 | .bpfeb, |
| 3559 | 3576 | .hppa64, |
| 3577 | .kvx, | |
| 3560 | 3578 | .loongarch64, |
| 3561 | 3579 | .mips64, |
| 3562 | 3580 | .mips64el, |
| ... | ... | @@ -3626,6 +3644,10 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention |
| 3626 | 3644 | .hppa => .{ .hppa_elf = .{} }, |
| 3627 | 3645 | .hppa64 => .{ .hppa64_elf = .{} }, |
| 3628 | 3646 | .kalimba => null, |
| 3647 | .kvx => switch (target.abi) { | |
| 3648 | .ilp32 => .{ .kvx_ilp32 = .{} }, | |
| 3649 | else => .{ .kvx_lp64 = .{} }, | |
| 3650 | }, | |
| 3629 | 3651 | .lanai => .{ .lanai_sysv = .{} }, |
| 3630 | 3652 | .loongarch64 => .{ .loongarch64_lp64 = .{} }, |
| 3631 | 3653 | .loongarch32 => .{ .loongarch32_ilp32 = .{} }, |
lib/std/Target/kvx.zig created+64| ... | ... | @@ -0,0 +1,64 @@ |
| 1 | //! This file is auto-generated by tools/update_cpu_features.zig. | |
| 2 | ||
| 3 | const std = @import("../std.zig"); | |
| 4 | const CpuFeature = std.Target.Cpu.Feature; | |
| 5 | const CpuModel = std.Target.Cpu.Model; | |
| 6 | ||
| 7 | pub const Feature = enum { | |
| 8 | v3_1, | |
| 9 | v3_2, | |
| 10 | v4_1, | |
| 11 | }; | |
| 12 | ||
| 13 | pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; | |
| 14 | pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; | |
| 15 | pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; | |
| 16 | pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; | |
| 17 | ||
| 18 | pub const all_features = blk: { | |
| 19 | const len = @typeInfo(Feature).@"enum".fields.len; | |
| 20 | std.debug.assert(len <= CpuFeature.Set.needed_bit_count); | |
| 21 | var result: [len]CpuFeature = undefined; | |
| 22 | result[@intFromEnum(Feature.v3_1)] = .{ | |
| 23 | .llvm_name = null, | |
| 24 | .description = "Enable ISA v3.1", | |
| 25 | .dependencies = featureSet(&[_]Feature{}), | |
| 26 | }; | |
| 27 | result[@intFromEnum(Feature.v3_2)] = .{ | |
| 28 | .llvm_name = null, | |
| 29 | .description = "Enable ISA v3.2", | |
| 30 | .dependencies = featureSet(&[_]Feature{ | |
| 31 | .v3_1, | |
| 32 | }), | |
| 33 | }; | |
| 34 | result[@intFromEnum(Feature.v4_1)] = .{ | |
| 35 | .llvm_name = null, | |
| 36 | .description = "Enable ISA v4.1", | |
| 37 | .dependencies = featureSet(&[_]Feature{ | |
| 38 | .v3_2, | |
| 39 | }), | |
| 40 | }; | |
| 41 | const ti = @typeInfo(Feature); | |
| 42 | for (&result, 0..) |*elem, i| { | |
| 43 | elem.index = i; | |
| 44 | elem.name = ti.@"enum".fields[i].name; | |
| 45 | } | |
| 46 | break :blk result; | |
| 47 | }; | |
| 48 | ||
| 49 | pub const cpu = struct { | |
| 50 | pub const coolidge_v1: CpuModel = .{ | |
| 51 | .name = "coolidge_v1", | |
| 52 | .llvm_name = null, | |
| 53 | .features = featureSet(&[_]Feature{ | |
| 54 | .v3_1, | |
| 55 | }), | |
| 56 | }; | |
| 57 | pub const coolidge_v2: CpuModel = .{ | |
| 58 | .name = "coolidge_v2", | |
| 59 | .llvm_name = null, | |
| 60 | .features = featureSet(&[_]Feature{ | |
| 61 | .v3_2, | |
| 62 | }), | |
| 63 | }; | |
| 64 | }; |
lib/std/builtin.zig+4| ... | ... | @@ -274,6 +274,9 @@ pub const CallingConvention = union(enum(u8)) { |
| 274 | 274 | /// The standard `hppa64` calling convention. |
| 275 | 275 | hppa64_elf: CommonOptions, |
| 276 | 276 | |
| 277 | kvx_lp64: CommonOptions, | |
| 278 | kvx_ilp32: CommonOptions, | |
| 279 | ||
| 277 | 280 | /// The standard `lanai` calling convention. |
| 278 | 281 | lanai_sysv: CommonOptions, |
| 279 | 282 | |
| ... | ... | @@ -959,6 +962,7 @@ pub const VaList = switch (builtin.cpu.arch) { |
| 959 | 962 | .csky, |
| 960 | 963 | .hppa, |
| 961 | 964 | .hppa64, |
| 965 | .kvx, | |
| 962 | 966 | .lanai, |
| 963 | 967 | .loongarch32, |
| 964 | 968 | .loongarch64, |
src/Sema.zig+2| ... | ... | @@ -9074,6 +9074,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention |
| 9074 | 9074 | .hexagon_sysv_hvx, |
| 9075 | 9075 | .hppa_elf, |
| 9076 | 9076 | .hppa64_elf, |
| 9077 | .kvx_lp64, | |
| 9078 | .kvx_ilp32, | |
| 9077 | 9079 | .lanai_sysv, |
| 9078 | 9080 | .loongarch64_lp64, |
| 9079 | 9081 | .loongarch32_ilp32, |
src/codegen/llvm.zig+5| ... | ... | @@ -111,6 +111,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8 |
| 111 | 111 | .hppa, |
| 112 | 112 | .hppa64, |
| 113 | 113 | .kalimba, |
| 114 | .kvx, | |
| 114 | 115 | .microblaze, |
| 115 | 116 | .microblazeel, |
| 116 | 117 | .or1k, |
| ... | ... | @@ -476,6 +477,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 { |
| 476 | 477 | .hppa, |
| 477 | 478 | .hppa64, |
| 478 | 479 | .kalimba, |
| 480 | .kvx, | |
| 479 | 481 | .microblaze, |
| 480 | 482 | .microblazeel, |
| 481 | 483 | .or1k, |
| ... | ... | @@ -11930,6 +11932,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s |
| 11930 | 11932 | .hexagon_sysv_hvx, |
| 11931 | 11933 | .hppa_elf, |
| 11932 | 11934 | .hppa64_elf, |
| 11935 | .kvx_lp64, | |
| 11936 | .kvx_ilp32, | |
| 11933 | 11937 | .lanai_sysv, |
| 11934 | 11938 | .loongarch64_lp64, |
| 11935 | 11939 | .loongarch32_ilp32, |
| ... | ... | @@ -13113,6 +13117,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { |
| 13113 | 13117 | .hppa, |
| 13114 | 13118 | .hppa64, |
| 13115 | 13119 | .kalimba, |
| 13120 | .kvx, | |
| 13116 | 13121 | .microblaze, |
| 13117 | 13122 | .microblazeel, |
| 13118 | 13123 | .or1k, |
src/target.zig+1| ... | ... | @@ -219,6 +219,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat) |
| 219 | 219 | .hppa, |
| 220 | 220 | .hppa64, |
| 221 | 221 | .kalimba, |
| 222 | .kvx, | |
| 222 | 223 | .microblaze, |
| 223 | 224 | .microblazeel, |
| 224 | 225 | .or1k, |
tools/update_cpu_features.zig+37| ... | ... | @@ -973,6 +973,43 @@ const targets = [_]ArchTarget{ |
| 973 | 973 | .td_name = "Hexagon", |
| 974 | 974 | }, |
| 975 | 975 | }, |
| 976 | .{ | |
| 977 | .zig_name = "kvx", | |
| 978 | .llvm = null, | |
| 979 | .extra_features = &.{ | |
| 980 | .{ | |
| 981 | .zig_name = "v3_1", | |
| 982 | .desc = "Enable ISA v3.1", | |
| 983 | .deps = &.{}, | |
| 984 | }, | |
| 985 | .{ | |
| 986 | .zig_name = "v3_2", | |
| 987 | .desc = "Enable ISA v3.2", | |
| 988 | .deps = &.{"v3_1"}, | |
| 989 | }, | |
| 990 | .{ | |
| 991 | .zig_name = "v4_1", | |
| 992 | .desc = "Enable ISA v4.1", | |
| 993 | .deps = &.{"v3_2"}, | |
| 994 | }, | |
| 995 | }, | |
| 996 | .extra_cpus = &.{ | |
| 997 | .{ | |
| 998 | .llvm_name = null, | |
| 999 | .zig_name = "coolidge_v1", | |
| 1000 | .features = &.{ | |
| 1001 | "v3_1", | |
| 1002 | }, | |
| 1003 | }, | |
| 1004 | .{ | |
| 1005 | .llvm_name = null, | |
| 1006 | .zig_name = "coolidge_v2", | |
| 1007 | .features = &.{ | |
| 1008 | "v3_2", | |
| 1009 | }, | |
| 1010 | }, | |
| 1011 | }, | |
| 1012 | }, | |
| 976 | 1013 | .{ |
| 977 | 1014 | .zig_name = "lanai", |
| 978 | 1015 | .llvm = .{ |