Commit 4955c4b8f99bc45ad9aacb13de691614c4e0ad38 | zig

author	Andrew Kelley <andrew@ziglang.org> 2018-02-23 13:15:16-05:00
committer	Andrew Kelley <andrew@ziglang.org> 2018-02-23 13:15:16-05:00
log	4955c4b8f99bc45ad9aacb13de691614c4e0ad38
tree	fb918ba58cfc7da81ab747fe2bc51cfc316d45ec
parent	1ba6e1641a4c5ea1d0d665fe500c9c66d69443a4

update C headers to clang 6.0.0rc3

34 files changed, 9004 insertions(+), 3855 deletions(-)

CMakeLists.txt+13

...	...	@@ -541,10 +541,12 @@ set(ZIG_C_HEADER_FILES
541	541	"adxintrin.h"
542	542	"altivec.h"
543	543	"ammintrin.h"
	544	"arm64intr.h"
544	545	"arm_acle.h"
545	546	"arm_neon.h"
546	547	"armintr.h"
547	548	"avx2intrin.h"
	549	"avx512bitalgintrin.h"
548	550	"avx512bwintrin.h"
549	551	"avx512cdintrin.h"
550	552	"avx512dqintrin.h"
...	...	@@ -553,17 +555,25 @@ set(ZIG_C_HEADER_FILES
553	555	"avx512ifmaintrin.h"
554	556	"avx512ifmavlintrin.h"
555	557	"avx512pfintrin.h"
	558	"avx512vbmi2intrin.h"
556	559	"avx512vbmiintrin.h"
557	560	"avx512vbmivlintrin.h"
	561	"avx512vlbitalgintrin.h"
558	562	"avx512vlbwintrin.h"
559	563	"avx512vlcdintrin.h"
560	564	"avx512vldqintrin.h"
561	565	"avx512vlintrin.h"
	566	"avx512vlvbmi2intrin.h"
	567	"avx512vlvnniintrin.h"
	568	"avx512vnniintrin.h"
562	569	"avx512vpopcntdqintrin.h"
	570	"avx512vpopcntdqvlintrin.h"
563	571	"avxintrin.h"
564	572	"bmi2intrin.h"
565	573	"bmiintrin.h"
	574	"cetintrin.h"
566	575	"clflushoptintrin.h"
	576	"clwbintrin.h"
567	577	"clzerointrin.h"
568	578	"cpuid.h"
569	579	"cuda_wrappers/algorithm"
...	...	@@ -575,6 +585,7 @@ set(ZIG_C_HEADER_FILES
575	585	"fma4intrin.h"
576	586	"fmaintrin.h"
577	587	"fxsrintrin.h"
	588	"gfniintrin.h"
578	589	"htmintrin.h"
579	590	"htmxlintrin.h"
580	591	"ia32intrin.h"
...	...	@@ -614,8 +625,10 @@ set(ZIG_C_HEADER_FILES
614	625	"tmmintrin.h"
615	626	"unwind.h"
616	627	"vadefs.h"
	628	"vaesintrin.h"
617	629	"varargs.h"
618	630	"vecintrin.h"
	631	"vpclmulqdqintrin.h"
619	632	"wmmintrin.h"
620	633	"x86intrin.h"
621	634	"xmmintrin.h"

c_headers/__clang_cuda_cmath.h+4-19

...	...	@@ -131,15 +131,6 @@ __DEVICE__ float ldexp(float __arg, int __exp) {
131	131	__DEVICE__ float log(float __x) { return ::logf(__x); }
132	132	__DEVICE__ float log10(float __x) { return ::log10f(__x); }
133	133	__DEVICE__ float modf(float __x, float *__iptr) { return ::modff(__x, __iptr); }
134		__DEVICE__ float nexttoward(float __from, double __to) {
135		return __builtin_nexttowardf(__from, __to);
136		}
137		__DEVICE__ double nexttoward(double __from, double __to) {
138		return __builtin_nexttoward(__from, __to);
139		}
140		__DEVICE__ float nexttowardf(float __from, double __to) {
141		return __builtin_nexttowardf(__from, __to);
142		}
143	134	__DEVICE__ float pow(float __base, float __exp) {
144	135	return ::powf(__base, __exp);
145	136	}
...	...	@@ -157,6 +148,10 @@ __DEVICE__ float sqrt(float __x) { return ::sqrtf(__x); }
157	148	__DEVICE__ float tan(float __x) { return ::tanf(__x); }
158	149	__DEVICE__ float tanh(float __x) { return ::tanhf(__x); }
159	150
	151	// Notably missing above is nexttoward. We omit it because
	152	// libdevice doesn't provide an implementation, and we don't want to be in the
	153	// business of implementing tricky libm functions in this header.
	154
160	155	// Now we've defined everything we promised we'd define in
161	156	// __clang_cuda_math_forward_declares.h. We need to do two additional things to
162	157	// fix up our math functions.
...	...	@@ -295,13 +290,6 @@ ldexp(__T __x, int __exp) {
295	290	return std::ldexp((double)__x, __exp);
296	291	}
297	292
298		template <typename __T>
299		__DEVICE__ typename __clang_cuda_enable_if<std::numeric_limits<__T>::is_integer,
300		double>::type
301		nexttoward(__T __from, double __to) {
302		return std::nexttoward((double)__from, __to);
303		}
304
305	293	template <typename __T1, typename __T2>
306	294	__DEVICE__ typename __clang_cuda_enable_if<
307	295	std::numeric_limits<__T1>::is_specialized &&
...	...	@@ -388,7 +376,6 @@ using ::lrint;
388	376	using ::lround;
389	377	using ::nearbyint;
390	378	using ::nextafter;
391		using ::nexttoward;
392	379	using ::pow;
393	380	using ::remainder;
394	381	using ::remquo;
...	...	@@ -456,8 +443,6 @@ using ::lroundf;
456	443	using ::modff;
457	444	using ::nearbyintf;
458	445	using ::nextafterf;
459		using ::nexttowardf;
460		using ::nexttowardf;
461	446	using ::powf;
462	447	using ::remainderf;
463	448	using ::remquof;

c_headers/__clang_cuda_intrinsics.h+67-24

...	...	@@ -34,23 +34,24 @@
34	34	#if !defined(__CUDA_ARCH__) \|\| __CUDA_ARCH__ >= 300
35	35
36	36	#pragma push_macro("__MAKE_SHUFFLES")
37		#define __MAKE_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, __Mask) \
38		inline __device__ int __FnName(int __val, int __offset, \
	37	#define __MAKE_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, __Mask, \
	38	__Type) \
	39	inline __device__ int __FnName(int __val, __Type __offset, \
39	40	int __width = warpSize) { \
40	41	return __IntIntrinsic(__val, __offset, \
41	42	((warpSize - __width) << 8) \| (__Mask)); \
42	43	} \
43		inline __device__ float __FnName(float __val, int __offset, \
	44	inline __device__ float __FnName(float __val, __Type __offset, \
44	45	int __width = warpSize) { \
45	46	return __FloatIntrinsic(__val, __offset, \
46	47	((warpSize - __width) << 8) \| (__Mask)); \
47	48	} \
48		inline __device__ unsigned int __FnName(unsigned int __val, int __offset, \
	49	inline __device__ unsigned int __FnName(unsigned int __val, __Type __offset, \
49	50	int __width = warpSize) { \
50	51	return static_cast<unsigned int>( \
51	52	::__FnName(static_cast<int>(__val), __offset, __width)); \
52	53	} \
53		inline __device__ long long __FnName(long long __val, int __offset, \
	54	inline __device__ long long __FnName(long long __val, __Type __offset, \
54	55	int __width = warpSize) { \
55	56	struct __Bits { \
56	57	int __a, __b; \
...	...	@@ -65,12 +66,29 @@
65	66	memcpy(&__ret, &__tmp, sizeof(__tmp)); \
66	67	return __ret; \
67	68	} \
	69	inline __device__ long __FnName(long __val, __Type __offset, \
	70	int __width = warpSize) { \
	71	_Static_assert(sizeof(long) == sizeof(long long) \|\| \
	72	sizeof(long) == sizeof(int)); \
	73	if (sizeof(long) == sizeof(long long)) { \
	74	return static_cast<long>( \
	75	::__FnName(static_cast<long long>(__val), __offset, __width)); \
	76	} else if (sizeof(long) == sizeof(int)) { \
	77	return static_cast<long>( \
	78	::__FnName(static_cast<int>(__val), __offset, __width)); \
	79	} \
	80	} \
	81	inline __device__ unsigned long __FnName( \
	82	unsigned long __val, __Type __offset, int __width = warpSize) { \
	83	return static_cast<unsigned long>( \
	84	::__FnName(static_cast<long>(__val), __offset, __width)); \
	85	} \
68	86	inline __device__ unsigned long long __FnName( \
69		unsigned long long __val, int __offset, int __width = warpSize) { \
	87	unsigned long long __val, __Type __offset, int __width = warpSize) { \
70	88	return static_cast<unsigned long long>(::__FnName( \
71	89	static_cast<unsigned long long>(__val), __offset, __width)); \
72	90	} \
73		inline __device__ double __FnName(double __val, int __offset, \
	91	inline __device__ double __FnName(double __val, __Type __offset, \
74	92	int __width = warpSize) { \
75	93	long long __tmp; \
76	94	_Static_assert(sizeof(__tmp) == sizeof(__val)); \
...	...	@@ -81,13 +99,15 @@
81	99	return __ret; \
82	100	}
83	101
84		__MAKE_SHUFFLES(__shfl, __nvvm_shfl_idx_i32, __nvvm_shfl_idx_f32, 0x1f);
	102	__MAKE_SHUFFLES(__shfl, __nvvm_shfl_idx_i32, __nvvm_shfl_idx_f32, 0x1f, int);
85	103	// We use 0 rather than 31 as our mask, because shfl.up applies to lanes >=
86	104	// maxLane.
87		__MAKE_SHUFFLES(__shfl_up, __nvvm_shfl_up_i32, __nvvm_shfl_up_f32, 0);
88		__MAKE_SHUFFLES(__shfl_down, __nvvm_shfl_down_i32, __nvvm_shfl_down_f32, 0x1f);
89		__MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f);
90
	105	__MAKE_SHUFFLES(__shfl_up, __nvvm_shfl_up_i32, __nvvm_shfl_up_f32, 0,
	106	unsigned int);
	107	__MAKE_SHUFFLES(__shfl_down, __nvvm_shfl_down_i32, __nvvm_shfl_down_f32, 0x1f,
	108	unsigned int);
	109	__MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f,
	110	int);
91	111	#pragma pop_macro("__MAKE_SHUFFLES")
92	112
93	113	#endif // !defined(__CUDA_ARCH__) \|\| __CUDA_ARCH__ >= 300
...	...	@@ -97,25 +117,26 @@ __MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f);
97	117	// __shfl_sync_* variants available in CUDA-9
98	118	#pragma push_macro("__MAKE_SYNC_SHUFFLES")
99	119	#define __MAKE_SYNC_SHUFFLES(__FnName, __IntIntrinsic, __FloatIntrinsic, \
100		__Mask) \
101		inline __device__ int __FnName(unsigned int __mask, int __val, int __offset, \
102		int __width = warpSize) { \
	120	__Mask, __Type) \
	121	inline __device__ int __FnName(unsigned int __mask, int __val, \
	122	__Type __offset, int __width = warpSize) { \
103	123	return __IntIntrinsic(__mask, __val, __offset, \
104	124	((warpSize - __width) << 8) \| (__Mask)); \
105	125	} \
106	126	inline __device__ float __FnName(unsigned int __mask, float __val, \
107		int __offset, int __width = warpSize) { \
	127	__Type __offset, int __width = warpSize) { \
108	128	return __FloatIntrinsic(__mask, __val, __offset, \
109	129	((warpSize - __width) << 8) \| (__Mask)); \
110	130	} \
111	131	inline __device__ unsigned int __FnName(unsigned int __mask, \
112		unsigned int __val, int __offset, \
	132	unsigned int __val, __Type __offset, \
113	133	int __width = warpSize) { \
114	134	return static_cast<unsigned int>( \
115	135	::__FnName(__mask, static_cast<int>(__val), __offset, __width)); \
116	136	} \
117	137	inline __device__ long long __FnName(unsigned int __mask, long long __val, \
118		int __offset, int __width = warpSize) { \
	138	__Type __offset, \
	139	int __width = warpSize) { \
119	140	struct __Bits { \
120	141	int __a, __b; \
121	142	}; \
...	...	@@ -130,13 +151,31 @@ __MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f);
130	151	return __ret; \
131	152	} \
132	153	inline __device__ unsigned long long __FnName( \
133		unsigned int __mask, unsigned long long __val, int __offset, \
	154	unsigned int __mask, unsigned long long __val, __Type __offset, \
134	155	int __width = warpSize) { \
135	156	return static_cast<unsigned long long>(::__FnName( \
136	157	__mask, static_cast<unsigned long long>(__val), __offset, __width)); \
137	158	} \
	159	inline __device__ long __FnName(unsigned int __mask, long __val, \
	160	__Type __offset, int __width = warpSize) { \
	161	_Static_assert(sizeof(long) == sizeof(long long) \|\| \
	162	sizeof(long) == sizeof(int)); \
	163	if (sizeof(long) == sizeof(long long)) { \
	164	return static_cast<long>(::__FnName( \
	165	__mask, static_cast<long long>(__val), __offset, __width)); \
	166	} else if (sizeof(long) == sizeof(int)) { \
	167	return static_cast<long>( \
	168	::__FnName(__mask, static_cast<int>(__val), __offset, __width)); \
	169	} \
	170	} \
	171	inline __device__ unsigned long __FnName( \
	172	unsigned int __mask, unsigned long __val, __Type __offset, \
	173	int __width = warpSize) { \
	174	return static_cast<unsigned long>( \
	175	::__FnName(__mask, static_cast<long>(__val), __offset, __width)); \
	176	} \
138	177	inline __device__ double __FnName(unsigned int __mask, double __val, \
139		int __offset, int __width = warpSize) { \
	178	__Type __offset, int __width = warpSize) { \
140	179	long long __tmp; \
141	180	_Static_assert(sizeof(__tmp) == sizeof(__val)); \
142	181	memcpy(&__tmp, &__val, sizeof(__val)); \
...	...	@@ -146,15 +185,15 @@ __MAKE_SHUFFLES(__shfl_xor, __nvvm_shfl_bfly_i32, __nvvm_shfl_bfly_f32, 0x1f);
146	185	return __ret; \
147	186	}
148	187	__MAKE_SYNC_SHUFFLES(__shfl_sync, __nvvm_shfl_sync_idx_i32,
149		__nvvm_shfl_sync_idx_f32, 0x1f);
	188	__nvvm_shfl_sync_idx_f32, 0x1f, int);
150	189	// We use 0 rather than 31 as our mask, because shfl.up applies to lanes >=
151	190	// maxLane.
152	191	__MAKE_SYNC_SHUFFLES(__shfl_up_sync, __nvvm_shfl_sync_up_i32,
153		__nvvm_shfl_sync_up_f32, 0);
	192	__nvvm_shfl_sync_up_f32, 0, unsigned int);
154	193	__MAKE_SYNC_SHUFFLES(__shfl_down_sync, __nvvm_shfl_sync_down_i32,
155		__nvvm_shfl_sync_down_f32, 0x1f);
	194	__nvvm_shfl_sync_down_f32, 0x1f, unsigned int);
156	195	__MAKE_SYNC_SHUFFLES(__shfl_xor_sync, __nvvm_shfl_sync_bfly_i32,
157		__nvvm_shfl_sync_bfly_f32, 0x1f);
	196	__nvvm_shfl_sync_bfly_f32, 0x1f, int);
158	197	#pragma pop_macro("__MAKE_SYNC_SHUFFLES")
159	198
160	199	inline __device__ void __syncwarp(unsigned int mask = 0xffffffff) {
...	...	@@ -188,6 +227,10 @@ inline __device__ unsigned int __ballot_sync(unsigned int mask, int pred) {
188	227
189	228	inline __device__ unsigned int __activemask() { return __nvvm_vote_ballot(1); }
190	229
	230	inline __device__ unsigned int __fns(unsigned mask, unsigned base, int offset) {
	231	return __nvvm_fns(mask, base, offset);
	232	}
	233
191	234	#endif // !defined(__CUDA_ARCH__) \|\| __CUDA_ARCH__ >= 300
192	235
193	236	// Define __match* builtins CUDA-9 headers expect to see.

c_headers/__clang_cuda_math_forward_declares.h+4-4

...	...	@@ -149,9 +149,6 @@ __DEVICE__ double nearbyint(double);
149	149	__DEVICE__ float nearbyint(float);
150	150	__DEVICE__ double nextafter(double, double);
151	151	__DEVICE__ float nextafter(float, float);
152		__DEVICE__ double nexttoward(double, double);
153		__DEVICE__ float nexttoward(float, double);
154		__DEVICE__ float nexttowardf(float, double);
155	152	__DEVICE__ double pow(double, double);
156	153	__DEVICE__ double pow(double, int);
157	154	__DEVICE__ float pow(float, float);
...	...	@@ -185,6 +182,10 @@ __DEVICE__ float tgamma(float);
185	182	__DEVICE__ double trunc(double);
186	183	__DEVICE__ float trunc(float);
187	184
	185	// Notably missing above is nexttoward, which we don't define on
	186	// the device side because libdevice doesn't give us an implementation, and we
	187	// don't want to be in the business of writing one ourselves.
	188
188	189	// We need to define these overloads in exactly the namespace our standard
189	190	// library uses (including the right inline namespace), otherwise they won't be
190	191	// picked up by other functions in the standard library (e.g. functions in
...	...	@@ -255,7 +256,6 @@ using ::nan;
255	256	using ::nanf;
256	257	using ::nearbyint;
257	258	using ::nextafter;
258		using ::nexttoward;
259	259	using ::pow;
260	260	using ::remainder;
261	261	using ::remquo;

c_headers/__clang_cuda_runtime_wrapper.h+6

...	...	@@ -270,12 +270,18 @@ static inline __device__ void __brkpt(int __c) { __brkpt(); }
270	270	// include guard from math.h wrapper from libstdc++. We have to undo the header
271	271	// guard temporarily to get the definitions we need.
272	272	#pragma push_macro("_GLIBCXX_MATH_H")
	273	#pragma push_macro("_LIBCPP_VERSION")
273	274	#if CUDA_VERSION >= 9000
274	275	#undef _GLIBCXX_MATH_H
	276	// We also need to undo another guard that checks for libc++ 3.8+
	277	#ifdef _LIBCPP_VERSION
	278	#define _LIBCPP_VERSION 3700
	279	#endif
275	280	#endif
276	281
277	282	#include "math_functions.hpp"
278	283	#pragma pop_macro("_GLIBCXX_MATH_H")
	284	#pragma pop_macro("_LIBCPP_VERSION")
279	285	#pragma pop_macro("__GNUC__")
280	286	#pragma pop_macro("signbit")
281	287

c_headers/arm_neon.h+5360-1992

...	...	@@ -40460,6 +40460,3318 @@ __ai float32x2_t vfms_f32(float32x2_t __p0, float32x2_t __p1, float32x2_t __p2)
40460	40460	}
40461	40461	#endif
40462	40462
	40463	#endif
	40464	#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)
	40465	#ifdef __LITTLE_ENDIAN__
	40466	__ai float16x8_t vabdq_f16(float16x8_t __p0, float16x8_t __p1) {
	40467	float16x8_t __ret;
	40468	__ret = (float16x8_t) __builtin_neon_vabdq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	40469	return __ret;
	40470	}
	40471	#else
	40472	__ai float16x8_t vabdq_f16(float16x8_t __p0, float16x8_t __p1) {
	40473	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40474	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40475	float16x8_t __ret;
	40476	__ret = (float16x8_t) __builtin_neon_vabdq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	40477	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40478	return __ret;
	40479	}
	40480	#endif
	40481
	40482	#ifdef __LITTLE_ENDIAN__
	40483	__ai float16x4_t vabd_f16(float16x4_t __p0, float16x4_t __p1) {
	40484	float16x4_t __ret;
	40485	__ret = (float16x4_t) __builtin_neon_vabd_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	40486	return __ret;
	40487	}
	40488	#else
	40489	__ai float16x4_t vabd_f16(float16x4_t __p0, float16x4_t __p1) {
	40490	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40491	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40492	float16x4_t __ret;
	40493	__ret = (float16x4_t) __builtin_neon_vabd_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	40494	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40495	return __ret;
	40496	}
	40497	#endif
	40498
	40499	#ifdef __LITTLE_ENDIAN__
	40500	__ai float16x8_t vabsq_f16(float16x8_t __p0) {
	40501	float16x8_t __ret;
	40502	__ret = (float16x8_t) __builtin_neon_vabsq_v((int8x16_t)__p0, 40);
	40503	return __ret;
	40504	}
	40505	#else
	40506	__ai float16x8_t vabsq_f16(float16x8_t __p0) {
	40507	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40508	float16x8_t __ret;
	40509	__ret = (float16x8_t) __builtin_neon_vabsq_v((int8x16_t)__rev0, 40);
	40510	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40511	return __ret;
	40512	}
	40513	#endif
	40514
	40515	#ifdef __LITTLE_ENDIAN__
	40516	__ai float16x4_t vabs_f16(float16x4_t __p0) {
	40517	float16x4_t __ret;
	40518	__ret = (float16x4_t) __builtin_neon_vabs_v((int8x8_t)__p0, 8);
	40519	return __ret;
	40520	}
	40521	#else
	40522	__ai float16x4_t vabs_f16(float16x4_t __p0) {
	40523	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40524	float16x4_t __ret;
	40525	__ret = (float16x4_t) __builtin_neon_vabs_v((int8x8_t)__rev0, 8);
	40526	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40527	return __ret;
	40528	}
	40529	#endif
	40530
	40531	#ifdef __LITTLE_ENDIAN__
	40532	__ai float16x8_t vaddq_f16(float16x8_t __p0, float16x8_t __p1) {
	40533	float16x8_t __ret;
	40534	__ret = __p0 + __p1;
	40535	return __ret;
	40536	}
	40537	#else
	40538	__ai float16x8_t vaddq_f16(float16x8_t __p0, float16x8_t __p1) {
	40539	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40540	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40541	float16x8_t __ret;
	40542	__ret = __rev0 + __rev1;
	40543	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40544	return __ret;
	40545	}
	40546	#endif
	40547
	40548	#ifdef __LITTLE_ENDIAN__
	40549	__ai float16x4_t vadd_f16(float16x4_t __p0, float16x4_t __p1) {
	40550	float16x4_t __ret;
	40551	__ret = __p0 + __p1;
	40552	return __ret;
	40553	}
	40554	#else
	40555	__ai float16x4_t vadd_f16(float16x4_t __p0, float16x4_t __p1) {
	40556	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40557	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40558	float16x4_t __ret;
	40559	__ret = __rev0 + __rev1;
	40560	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40561	return __ret;
	40562	}
	40563	#endif
	40564
	40565	#ifdef __LITTLE_ENDIAN__
	40566	__ai float16x8_t vbslq_f16(uint16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	40567	float16x8_t __ret;
	40568	__ret = (float16x8_t) __builtin_neon_vbslq_v((int8x16_t)__p0, (int8x16_t)__p1, (int8x16_t)__p2, 40);
	40569	return __ret;
	40570	}
	40571	#else
	40572	__ai float16x8_t vbslq_f16(uint16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	40573	uint16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40574	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40575	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, 7, 6, 5, 4, 3, 2, 1, 0);
	40576	float16x8_t __ret;
	40577	__ret = (float16x8_t) __builtin_neon_vbslq_v((int8x16_t)__rev0, (int8x16_t)__rev1, (int8x16_t)__rev2, 40);
	40578	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40579	return __ret;
	40580	}
	40581	#endif
	40582
	40583	#ifdef __LITTLE_ENDIAN__
	40584	__ai float16x4_t vbsl_f16(uint16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	40585	float16x4_t __ret;
	40586	__ret = (float16x4_t) __builtin_neon_vbsl_v((int8x8_t)__p0, (int8x8_t)__p1, (int8x8_t)__p2, 8);
	40587	return __ret;
	40588	}
	40589	#else
	40590	__ai float16x4_t vbsl_f16(uint16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	40591	uint16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40592	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40593	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, 3, 2, 1, 0);
	40594	float16x4_t __ret;
	40595	__ret = (float16x4_t) __builtin_neon_vbsl_v((int8x8_t)__rev0, (int8x8_t)__rev1, (int8x8_t)__rev2, 8);
	40596	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40597	return __ret;
	40598	}
	40599	#endif
	40600
	40601	#ifdef __LITTLE_ENDIAN__
	40602	__ai uint16x8_t vcageq_f16(float16x8_t __p0, float16x8_t __p1) {
	40603	uint16x8_t __ret;
	40604	__ret = (uint16x8_t) __builtin_neon_vcageq_v((int8x16_t)__p0, (int8x16_t)__p1, 49);
	40605	return __ret;
	40606	}
	40607	#else
	40608	__ai uint16x8_t vcageq_f16(float16x8_t __p0, float16x8_t __p1) {
	40609	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40610	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40611	uint16x8_t __ret;
	40612	__ret = (uint16x8_t) __builtin_neon_vcageq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 49);
	40613	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40614	return __ret;
	40615	}
	40616	#endif
	40617
	40618	#ifdef __LITTLE_ENDIAN__
	40619	__ai uint16x4_t vcage_f16(float16x4_t __p0, float16x4_t __p1) {
	40620	uint16x4_t __ret;
	40621	__ret = (uint16x4_t) __builtin_neon_vcage_v((int8x8_t)__p0, (int8x8_t)__p1, 17);
	40622	return __ret;
	40623	}
	40624	#else
	40625	__ai uint16x4_t vcage_f16(float16x4_t __p0, float16x4_t __p1) {
	40626	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40627	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40628	uint16x4_t __ret;
	40629	__ret = (uint16x4_t) __builtin_neon_vcage_v((int8x8_t)__rev0, (int8x8_t)__rev1, 17);
	40630	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40631	return __ret;
	40632	}
	40633	#endif
	40634
	40635	#ifdef __LITTLE_ENDIAN__
	40636	__ai uint16x8_t vcagtq_f16(float16x8_t __p0, float16x8_t __p1) {
	40637	uint16x8_t __ret;
	40638	__ret = (uint16x8_t) __builtin_neon_vcagtq_v((int8x16_t)__p0, (int8x16_t)__p1, 49);
	40639	return __ret;
	40640	}
	40641	#else
	40642	__ai uint16x8_t vcagtq_f16(float16x8_t __p0, float16x8_t __p1) {
	40643	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40644	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40645	uint16x8_t __ret;
	40646	__ret = (uint16x8_t) __builtin_neon_vcagtq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 49);
	40647	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40648	return __ret;
	40649	}
	40650	#endif
	40651
	40652	#ifdef __LITTLE_ENDIAN__
	40653	__ai uint16x4_t vcagt_f16(float16x4_t __p0, float16x4_t __p1) {
	40654	uint16x4_t __ret;
	40655	__ret = (uint16x4_t) __builtin_neon_vcagt_v((int8x8_t)__p0, (int8x8_t)__p1, 17);
	40656	return __ret;
	40657	}
	40658	#else
	40659	__ai uint16x4_t vcagt_f16(float16x4_t __p0, float16x4_t __p1) {
	40660	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40661	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40662	uint16x4_t __ret;
	40663	__ret = (uint16x4_t) __builtin_neon_vcagt_v((int8x8_t)__rev0, (int8x8_t)__rev1, 17);
	40664	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40665	return __ret;
	40666	}
	40667	#endif
	40668
	40669	#ifdef __LITTLE_ENDIAN__
	40670	__ai uint16x8_t vcaleq_f16(float16x8_t __p0, float16x8_t __p1) {
	40671	uint16x8_t __ret;
	40672	__ret = (uint16x8_t) __builtin_neon_vcaleq_v((int8x16_t)__p0, (int8x16_t)__p1, 49);
	40673	return __ret;
	40674	}
	40675	#else
	40676	__ai uint16x8_t vcaleq_f16(float16x8_t __p0, float16x8_t __p1) {
	40677	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40678	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40679	uint16x8_t __ret;
	40680	__ret = (uint16x8_t) __builtin_neon_vcaleq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 49);
	40681	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40682	return __ret;
	40683	}
	40684	#endif
	40685
	40686	#ifdef __LITTLE_ENDIAN__
	40687	__ai uint16x4_t vcale_f16(float16x4_t __p0, float16x4_t __p1) {
	40688	uint16x4_t __ret;
	40689	__ret = (uint16x4_t) __builtin_neon_vcale_v((int8x8_t)__p0, (int8x8_t)__p1, 17);
	40690	return __ret;
	40691	}
	40692	#else
	40693	__ai uint16x4_t vcale_f16(float16x4_t __p0, float16x4_t __p1) {
	40694	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40695	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40696	uint16x4_t __ret;
	40697	__ret = (uint16x4_t) __builtin_neon_vcale_v((int8x8_t)__rev0, (int8x8_t)__rev1, 17);
	40698	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40699	return __ret;
	40700	}
	40701	#endif
	40702
	40703	#ifdef __LITTLE_ENDIAN__
	40704	__ai uint16x8_t vcaltq_f16(float16x8_t __p0, float16x8_t __p1) {
	40705	uint16x8_t __ret;
	40706	__ret = (uint16x8_t) __builtin_neon_vcaltq_v((int8x16_t)__p0, (int8x16_t)__p1, 49);
	40707	return __ret;
	40708	}
	40709	#else
	40710	__ai uint16x8_t vcaltq_f16(float16x8_t __p0, float16x8_t __p1) {
	40711	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40712	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40713	uint16x8_t __ret;
	40714	__ret = (uint16x8_t) __builtin_neon_vcaltq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 49);
	40715	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40716	return __ret;
	40717	}
	40718	#endif
	40719
	40720	#ifdef __LITTLE_ENDIAN__
	40721	__ai uint16x4_t vcalt_f16(float16x4_t __p0, float16x4_t __p1) {
	40722	uint16x4_t __ret;
	40723	__ret = (uint16x4_t) __builtin_neon_vcalt_v((int8x8_t)__p0, (int8x8_t)__p1, 17);
	40724	return __ret;
	40725	}
	40726	#else
	40727	__ai uint16x4_t vcalt_f16(float16x4_t __p0, float16x4_t __p1) {
	40728	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40729	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40730	uint16x4_t __ret;
	40731	__ret = (uint16x4_t) __builtin_neon_vcalt_v((int8x8_t)__rev0, (int8x8_t)__rev1, 17);
	40732	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40733	return __ret;
	40734	}
	40735	#endif
	40736
	40737	#ifdef __LITTLE_ENDIAN__
	40738	__ai uint16x8_t vceqq_f16(float16x8_t __p0, float16x8_t __p1) {
	40739	uint16x8_t __ret;
	40740	__ret = (uint16x8_t)(__p0 == __p1);
	40741	return __ret;
	40742	}
	40743	#else
	40744	__ai uint16x8_t vceqq_f16(float16x8_t __p0, float16x8_t __p1) {
	40745	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40746	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40747	uint16x8_t __ret;
	40748	__ret = (uint16x8_t)(__rev0 == __rev1);
	40749	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40750	return __ret;
	40751	}
	40752	#endif
	40753
	40754	#ifdef __LITTLE_ENDIAN__
	40755	__ai uint16x4_t vceq_f16(float16x4_t __p0, float16x4_t __p1) {
	40756	uint16x4_t __ret;
	40757	__ret = (uint16x4_t)(__p0 == __p1);
	40758	return __ret;
	40759	}
	40760	#else
	40761	__ai uint16x4_t vceq_f16(float16x4_t __p0, float16x4_t __p1) {
	40762	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40763	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40764	uint16x4_t __ret;
	40765	__ret = (uint16x4_t)(__rev0 == __rev1);
	40766	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40767	return __ret;
	40768	}
	40769	#endif
	40770
	40771	#ifdef __LITTLE_ENDIAN__
	40772	__ai uint16x8_t vceqzq_f16(float16x8_t __p0) {
	40773	uint16x8_t __ret;
	40774	__ret = (uint16x8_t) __builtin_neon_vceqzq_v((int8x16_t)__p0, 49);
	40775	return __ret;
	40776	}
	40777	#else
	40778	__ai uint16x8_t vceqzq_f16(float16x8_t __p0) {
	40779	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40780	uint16x8_t __ret;
	40781	__ret = (uint16x8_t) __builtin_neon_vceqzq_v((int8x16_t)__rev0, 49);
	40782	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40783	return __ret;
	40784	}
	40785	#endif
	40786
	40787	#ifdef __LITTLE_ENDIAN__
	40788	__ai uint16x4_t vceqz_f16(float16x4_t __p0) {
	40789	uint16x4_t __ret;
	40790	__ret = (uint16x4_t) __builtin_neon_vceqz_v((int8x8_t)__p0, 17);
	40791	return __ret;
	40792	}
	40793	#else
	40794	__ai uint16x4_t vceqz_f16(float16x4_t __p0) {
	40795	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40796	uint16x4_t __ret;
	40797	__ret = (uint16x4_t) __builtin_neon_vceqz_v((int8x8_t)__rev0, 17);
	40798	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40799	return __ret;
	40800	}
	40801	#endif
	40802
	40803	#ifdef __LITTLE_ENDIAN__
	40804	__ai uint16x8_t vcgeq_f16(float16x8_t __p0, float16x8_t __p1) {
	40805	uint16x8_t __ret;
	40806	__ret = (uint16x8_t)(__p0 >= __p1);
	40807	return __ret;
	40808	}
	40809	#else
	40810	__ai uint16x8_t vcgeq_f16(float16x8_t __p0, float16x8_t __p1) {
	40811	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40812	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40813	uint16x8_t __ret;
	40814	__ret = (uint16x8_t)(__rev0 >= __rev1);
	40815	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40816	return __ret;
	40817	}
	40818	#endif
	40819
	40820	#ifdef __LITTLE_ENDIAN__
	40821	__ai uint16x4_t vcge_f16(float16x4_t __p0, float16x4_t __p1) {
	40822	uint16x4_t __ret;
	40823	__ret = (uint16x4_t)(__p0 >= __p1);
	40824	return __ret;
	40825	}
	40826	#else
	40827	__ai uint16x4_t vcge_f16(float16x4_t __p0, float16x4_t __p1) {
	40828	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40829	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40830	uint16x4_t __ret;
	40831	__ret = (uint16x4_t)(__rev0 >= __rev1);
	40832	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40833	return __ret;
	40834	}
	40835	#endif
	40836
	40837	#ifdef __LITTLE_ENDIAN__
	40838	__ai uint16x8_t vcgezq_f16(float16x8_t __p0) {
	40839	uint16x8_t __ret;
	40840	__ret = (uint16x8_t) __builtin_neon_vcgezq_v((int8x16_t)__p0, 49);
	40841	return __ret;
	40842	}
	40843	#else
	40844	__ai uint16x8_t vcgezq_f16(float16x8_t __p0) {
	40845	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40846	uint16x8_t __ret;
	40847	__ret = (uint16x8_t) __builtin_neon_vcgezq_v((int8x16_t)__rev0, 49);
	40848	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40849	return __ret;
	40850	}
	40851	#endif
	40852
	40853	#ifdef __LITTLE_ENDIAN__
	40854	__ai uint16x4_t vcgez_f16(float16x4_t __p0) {
	40855	uint16x4_t __ret;
	40856	__ret = (uint16x4_t) __builtin_neon_vcgez_v((int8x8_t)__p0, 17);
	40857	return __ret;
	40858	}
	40859	#else
	40860	__ai uint16x4_t vcgez_f16(float16x4_t __p0) {
	40861	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40862	uint16x4_t __ret;
	40863	__ret = (uint16x4_t) __builtin_neon_vcgez_v((int8x8_t)__rev0, 17);
	40864	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40865	return __ret;
	40866	}
	40867	#endif
	40868
	40869	#ifdef __LITTLE_ENDIAN__
	40870	__ai uint16x8_t vcgtq_f16(float16x8_t __p0, float16x8_t __p1) {
	40871	uint16x8_t __ret;
	40872	__ret = (uint16x8_t)(__p0 > __p1);
	40873	return __ret;
	40874	}
	40875	#else
	40876	__ai uint16x8_t vcgtq_f16(float16x8_t __p0, float16x8_t __p1) {
	40877	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40878	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40879	uint16x8_t __ret;
	40880	__ret = (uint16x8_t)(__rev0 > __rev1);
	40881	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40882	return __ret;
	40883	}
	40884	#endif
	40885
	40886	#ifdef __LITTLE_ENDIAN__
	40887	__ai uint16x4_t vcgt_f16(float16x4_t __p0, float16x4_t __p1) {
	40888	uint16x4_t __ret;
	40889	__ret = (uint16x4_t)(__p0 > __p1);
	40890	return __ret;
	40891	}
	40892	#else
	40893	__ai uint16x4_t vcgt_f16(float16x4_t __p0, float16x4_t __p1) {
	40894	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40895	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40896	uint16x4_t __ret;
	40897	__ret = (uint16x4_t)(__rev0 > __rev1);
	40898	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40899	return __ret;
	40900	}
	40901	#endif
	40902
	40903	#ifdef __LITTLE_ENDIAN__
	40904	__ai uint16x8_t vcgtzq_f16(float16x8_t __p0) {
	40905	uint16x8_t __ret;
	40906	__ret = (uint16x8_t) __builtin_neon_vcgtzq_v((int8x16_t)__p0, 49);
	40907	return __ret;
	40908	}
	40909	#else
	40910	__ai uint16x8_t vcgtzq_f16(float16x8_t __p0) {
	40911	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40912	uint16x8_t __ret;
	40913	__ret = (uint16x8_t) __builtin_neon_vcgtzq_v((int8x16_t)__rev0, 49);
	40914	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40915	return __ret;
	40916	}
	40917	#endif
	40918
	40919	#ifdef __LITTLE_ENDIAN__
	40920	__ai uint16x4_t vcgtz_f16(float16x4_t __p0) {
	40921	uint16x4_t __ret;
	40922	__ret = (uint16x4_t) __builtin_neon_vcgtz_v((int8x8_t)__p0, 17);
	40923	return __ret;
	40924	}
	40925	#else
	40926	__ai uint16x4_t vcgtz_f16(float16x4_t __p0) {
	40927	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40928	uint16x4_t __ret;
	40929	__ret = (uint16x4_t) __builtin_neon_vcgtz_v((int8x8_t)__rev0, 17);
	40930	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40931	return __ret;
	40932	}
	40933	#endif
	40934
	40935	#ifdef __LITTLE_ENDIAN__
	40936	__ai uint16x8_t vcleq_f16(float16x8_t __p0, float16x8_t __p1) {
	40937	uint16x8_t __ret;
	40938	__ret = (uint16x8_t)(__p0 <= __p1);
	40939	return __ret;
	40940	}
	40941	#else
	40942	__ai uint16x8_t vcleq_f16(float16x8_t __p0, float16x8_t __p1) {
	40943	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40944	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	40945	uint16x8_t __ret;
	40946	__ret = (uint16x8_t)(__rev0 <= __rev1);
	40947	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40948	return __ret;
	40949	}
	40950	#endif
	40951
	40952	#ifdef __LITTLE_ENDIAN__
	40953	__ai uint16x4_t vcle_f16(float16x4_t __p0, float16x4_t __p1) {
	40954	uint16x4_t __ret;
	40955	__ret = (uint16x4_t)(__p0 <= __p1);
	40956	return __ret;
	40957	}
	40958	#else
	40959	__ai uint16x4_t vcle_f16(float16x4_t __p0, float16x4_t __p1) {
	40960	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40961	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	40962	uint16x4_t __ret;
	40963	__ret = (uint16x4_t)(__rev0 <= __rev1);
	40964	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40965	return __ret;
	40966	}
	40967	#endif
	40968
	40969	#ifdef __LITTLE_ENDIAN__
	40970	__ai uint16x8_t vclezq_f16(float16x8_t __p0) {
	40971	uint16x8_t __ret;
	40972	__ret = (uint16x8_t) __builtin_neon_vclezq_v((int8x16_t)__p0, 49);
	40973	return __ret;
	40974	}
	40975	#else
	40976	__ai uint16x8_t vclezq_f16(float16x8_t __p0) {
	40977	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	40978	uint16x8_t __ret;
	40979	__ret = (uint16x8_t) __builtin_neon_vclezq_v((int8x16_t)__rev0, 49);
	40980	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	40981	return __ret;
	40982	}
	40983	#endif
	40984
	40985	#ifdef __LITTLE_ENDIAN__
	40986	__ai uint16x4_t vclez_f16(float16x4_t __p0) {
	40987	uint16x4_t __ret;
	40988	__ret = (uint16x4_t) __builtin_neon_vclez_v((int8x8_t)__p0, 17);
	40989	return __ret;
	40990	}
	40991	#else
	40992	__ai uint16x4_t vclez_f16(float16x4_t __p0) {
	40993	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	40994	uint16x4_t __ret;
	40995	__ret = (uint16x4_t) __builtin_neon_vclez_v((int8x8_t)__rev0, 17);
	40996	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	40997	return __ret;
	40998	}
	40999	#endif
	41000
	41001	#ifdef __LITTLE_ENDIAN__
	41002	__ai uint16x8_t vcltq_f16(float16x8_t __p0, float16x8_t __p1) {
	41003	uint16x8_t __ret;
	41004	__ret = (uint16x8_t)(__p0 < __p1);
	41005	return __ret;
	41006	}
	41007	#else
	41008	__ai uint16x8_t vcltq_f16(float16x8_t __p0, float16x8_t __p1) {
	41009	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41010	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	41011	uint16x8_t __ret;
	41012	__ret = (uint16x8_t)(__rev0 < __rev1);
	41013	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41014	return __ret;
	41015	}
	41016	#endif
	41017
	41018	#ifdef __LITTLE_ENDIAN__
	41019	__ai uint16x4_t vclt_f16(float16x4_t __p0, float16x4_t __p1) {
	41020	uint16x4_t __ret;
	41021	__ret = (uint16x4_t)(__p0 < __p1);
	41022	return __ret;
	41023	}
	41024	#else
	41025	__ai uint16x4_t vclt_f16(float16x4_t __p0, float16x4_t __p1) {
	41026	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41027	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	41028	uint16x4_t __ret;
	41029	__ret = (uint16x4_t)(__rev0 < __rev1);
	41030	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41031	return __ret;
	41032	}
	41033	#endif
	41034
	41035	#ifdef __LITTLE_ENDIAN__
	41036	__ai uint16x8_t vcltzq_f16(float16x8_t __p0) {
	41037	uint16x8_t __ret;
	41038	__ret = (uint16x8_t) __builtin_neon_vcltzq_v((int8x16_t)__p0, 49);
	41039	return __ret;
	41040	}
	41041	#else
	41042	__ai uint16x8_t vcltzq_f16(float16x8_t __p0) {
	41043	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41044	uint16x8_t __ret;
	41045	__ret = (uint16x8_t) __builtin_neon_vcltzq_v((int8x16_t)__rev0, 49);
	41046	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41047	return __ret;
	41048	}
	41049	#endif
	41050
	41051	#ifdef __LITTLE_ENDIAN__
	41052	__ai uint16x4_t vcltz_f16(float16x4_t __p0) {
	41053	uint16x4_t __ret;
	41054	__ret = (uint16x4_t) __builtin_neon_vcltz_v((int8x8_t)__p0, 17);
	41055	return __ret;
	41056	}
	41057	#else
	41058	__ai uint16x4_t vcltz_f16(float16x4_t __p0) {
	41059	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41060	uint16x4_t __ret;
	41061	__ret = (uint16x4_t) __builtin_neon_vcltz_v((int8x8_t)__rev0, 17);
	41062	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41063	return __ret;
	41064	}
	41065	#endif
	41066
	41067	#ifdef __LITTLE_ENDIAN__
	41068	__ai float16x8_t vcvtq_f16_u16(uint16x8_t __p0) {
	41069	float16x8_t __ret;
	41070	__ret = (float16x8_t) __builtin_neon_vcvtq_f16_v((int8x16_t)__p0, 49);
	41071	return __ret;
	41072	}
	41073	#else
	41074	__ai float16x8_t vcvtq_f16_u16(uint16x8_t __p0) {
	41075	uint16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41076	float16x8_t __ret;
	41077	__ret = (float16x8_t) __builtin_neon_vcvtq_f16_v((int8x16_t)__rev0, 49);
	41078	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41079	return __ret;
	41080	}
	41081	#endif
	41082
	41083	#ifdef __LITTLE_ENDIAN__
	41084	__ai float16x8_t vcvtq_f16_s16(int16x8_t __p0) {
	41085	float16x8_t __ret;
	41086	__ret = (float16x8_t) __builtin_neon_vcvtq_f16_v((int8x16_t)__p0, 33);
	41087	return __ret;
	41088	}
	41089	#else
	41090	__ai float16x8_t vcvtq_f16_s16(int16x8_t __p0) {
	41091	int16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41092	float16x8_t __ret;
	41093	__ret = (float16x8_t) __builtin_neon_vcvtq_f16_v((int8x16_t)__rev0, 33);
	41094	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41095	return __ret;
	41096	}
	41097	#endif
	41098
	41099	#ifdef __LITTLE_ENDIAN__
	41100	__ai float16x4_t vcvt_f16_u16(uint16x4_t __p0) {
	41101	float16x4_t __ret;
	41102	__ret = (float16x4_t) __builtin_neon_vcvt_f16_v((int8x8_t)__p0, 17);
	41103	return __ret;
	41104	}
	41105	#else
	41106	__ai float16x4_t vcvt_f16_u16(uint16x4_t __p0) {
	41107	uint16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41108	float16x4_t __ret;
	41109	__ret = (float16x4_t) __builtin_neon_vcvt_f16_v((int8x8_t)__rev0, 17);
	41110	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41111	return __ret;
	41112	}
	41113	#endif
	41114
	41115	#ifdef __LITTLE_ENDIAN__
	41116	__ai float16x4_t vcvt_f16_s16(int16x4_t __p0) {
	41117	float16x4_t __ret;
	41118	__ret = (float16x4_t) __builtin_neon_vcvt_f16_v((int8x8_t)__p0, 1);
	41119	return __ret;
	41120	}
	41121	#else
	41122	__ai float16x4_t vcvt_f16_s16(int16x4_t __p0) {
	41123	int16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41124	float16x4_t __ret;
	41125	__ret = (float16x4_t) __builtin_neon_vcvt_f16_v((int8x8_t)__rev0, 1);
	41126	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41127	return __ret;
	41128	}
	41129	#endif
	41130
	41131	#ifdef __LITTLE_ENDIAN__
	41132	#define vcvtq_n_f16_u16(__p0, __p1) __extension__ ({ \
	41133	uint16x8_t __s0 = __p0; \
	41134	float16x8_t __ret; \
	41135	__ret = (float16x8_t) __builtin_neon_vcvtq_n_f16_v((int8x16_t)__s0, __p1, 49); \
	41136	__ret; \
	41137	})
	41138	#else
	41139	#define vcvtq_n_f16_u16(__p0, __p1) __extension__ ({ \
	41140	uint16x8_t __s0 = __p0; \
	41141	uint16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41142	float16x8_t __ret; \
	41143	__ret = (float16x8_t) __builtin_neon_vcvtq_n_f16_v((int8x16_t)__rev0, __p1, 49); \
	41144	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41145	__ret; \
	41146	})
	41147	#endif
	41148
	41149	#ifdef __LITTLE_ENDIAN__
	41150	#define vcvtq_n_f16_s16(__p0, __p1) __extension__ ({ \
	41151	int16x8_t __s0 = __p0; \
	41152	float16x8_t __ret; \
	41153	__ret = (float16x8_t) __builtin_neon_vcvtq_n_f16_v((int8x16_t)__s0, __p1, 33); \
	41154	__ret; \
	41155	})
	41156	#else
	41157	#define vcvtq_n_f16_s16(__p0, __p1) __extension__ ({ \
	41158	int16x8_t __s0 = __p0; \
	41159	int16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41160	float16x8_t __ret; \
	41161	__ret = (float16x8_t) __builtin_neon_vcvtq_n_f16_v((int8x16_t)__rev0, __p1, 33); \
	41162	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41163	__ret; \
	41164	})
	41165	#endif
	41166
	41167	#ifdef __LITTLE_ENDIAN__
	41168	#define vcvt_n_f16_u16(__p0, __p1) __extension__ ({ \
	41169	uint16x4_t __s0 = __p0; \
	41170	float16x4_t __ret; \
	41171	__ret = (float16x4_t) __builtin_neon_vcvt_n_f16_v((int8x8_t)__s0, __p1, 17); \
	41172	__ret; \
	41173	})
	41174	#else
	41175	#define vcvt_n_f16_u16(__p0, __p1) __extension__ ({ \
	41176	uint16x4_t __s0 = __p0; \
	41177	uint16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41178	float16x4_t __ret; \
	41179	__ret = (float16x4_t) __builtin_neon_vcvt_n_f16_v((int8x8_t)__rev0, __p1, 17); \
	41180	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41181	__ret; \
	41182	})
	41183	#endif
	41184
	41185	#ifdef __LITTLE_ENDIAN__
	41186	#define vcvt_n_f16_s16(__p0, __p1) __extension__ ({ \
	41187	int16x4_t __s0 = __p0; \
	41188	float16x4_t __ret; \
	41189	__ret = (float16x4_t) __builtin_neon_vcvt_n_f16_v((int8x8_t)__s0, __p1, 1); \
	41190	__ret; \
	41191	})
	41192	#else
	41193	#define vcvt_n_f16_s16(__p0, __p1) __extension__ ({ \
	41194	int16x4_t __s0 = __p0; \
	41195	int16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41196	float16x4_t __ret; \
	41197	__ret = (float16x4_t) __builtin_neon_vcvt_n_f16_v((int8x8_t)__rev0, __p1, 1); \
	41198	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41199	__ret; \
	41200	})
	41201	#endif
	41202
	41203	#ifdef __LITTLE_ENDIAN__
	41204	#define vcvtq_n_s16_f16(__p0, __p1) __extension__ ({ \
	41205	float16x8_t __s0 = __p0; \
	41206	int16x8_t __ret; \
	41207	__ret = (int16x8_t) __builtin_neon_vcvtq_n_s16_v((int8x16_t)__s0, __p1, 33); \
	41208	__ret; \
	41209	})
	41210	#else
	41211	#define vcvtq_n_s16_f16(__p0, __p1) __extension__ ({ \
	41212	float16x8_t __s0 = __p0; \
	41213	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41214	int16x8_t __ret; \
	41215	__ret = (int16x8_t) __builtin_neon_vcvtq_n_s16_v((int8x16_t)__rev0, __p1, 33); \
	41216	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41217	__ret; \
	41218	})
	41219	#endif
	41220
	41221	#ifdef __LITTLE_ENDIAN__
	41222	#define vcvt_n_s16_f16(__p0, __p1) __extension__ ({ \
	41223	float16x4_t __s0 = __p0; \
	41224	int16x4_t __ret; \
	41225	__ret = (int16x4_t) __builtin_neon_vcvt_n_s16_v((int8x8_t)__s0, __p1, 1); \
	41226	__ret; \
	41227	})
	41228	#else
	41229	#define vcvt_n_s16_f16(__p0, __p1) __extension__ ({ \
	41230	float16x4_t __s0 = __p0; \
	41231	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41232	int16x4_t __ret; \
	41233	__ret = (int16x4_t) __builtin_neon_vcvt_n_s16_v((int8x8_t)__rev0, __p1, 1); \
	41234	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41235	__ret; \
	41236	})
	41237	#endif
	41238
	41239	#ifdef __LITTLE_ENDIAN__
	41240	#define vcvtq_n_u16_f16(__p0, __p1) __extension__ ({ \
	41241	float16x8_t __s0 = __p0; \
	41242	uint16x8_t __ret; \
	41243	__ret = (uint16x8_t) __builtin_neon_vcvtq_n_u16_v((int8x16_t)__s0, __p1, 49); \
	41244	__ret; \
	41245	})
	41246	#else
	41247	#define vcvtq_n_u16_f16(__p0, __p1) __extension__ ({ \
	41248	float16x8_t __s0 = __p0; \
	41249	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41250	uint16x8_t __ret; \
	41251	__ret = (uint16x8_t) __builtin_neon_vcvtq_n_u16_v((int8x16_t)__rev0, __p1, 49); \
	41252	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41253	__ret; \
	41254	})
	41255	#endif
	41256
	41257	#ifdef __LITTLE_ENDIAN__
	41258	#define vcvt_n_u16_f16(__p0, __p1) __extension__ ({ \
	41259	float16x4_t __s0 = __p0; \
	41260	uint16x4_t __ret; \
	41261	__ret = (uint16x4_t) __builtin_neon_vcvt_n_u16_v((int8x8_t)__s0, __p1, 17); \
	41262	__ret; \
	41263	})
	41264	#else
	41265	#define vcvt_n_u16_f16(__p0, __p1) __extension__ ({ \
	41266	float16x4_t __s0 = __p0; \
	41267	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41268	uint16x4_t __ret; \
	41269	__ret = (uint16x4_t) __builtin_neon_vcvt_n_u16_v((int8x8_t)__rev0, __p1, 17); \
	41270	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41271	__ret; \
	41272	})
	41273	#endif
	41274
	41275	#ifdef __LITTLE_ENDIAN__
	41276	__ai int16x8_t vcvtq_s16_f16(float16x8_t __p0) {
	41277	int16x8_t __ret;
	41278	__ret = (int16x8_t) __builtin_neon_vcvtq_s16_v((int8x16_t)__p0, 33);
	41279	return __ret;
	41280	}
	41281	#else
	41282	__ai int16x8_t vcvtq_s16_f16(float16x8_t __p0) {
	41283	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41284	int16x8_t __ret;
	41285	__ret = (int16x8_t) __builtin_neon_vcvtq_s16_v((int8x16_t)__rev0, 33);
	41286	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41287	return __ret;
	41288	}
	41289	#endif
	41290
	41291	#ifdef __LITTLE_ENDIAN__
	41292	__ai int16x4_t vcvt_s16_f16(float16x4_t __p0) {
	41293	int16x4_t __ret;
	41294	__ret = (int16x4_t) __builtin_neon_vcvt_s16_v((int8x8_t)__p0, 1);
	41295	return __ret;
	41296	}
	41297	#else
	41298	__ai int16x4_t vcvt_s16_f16(float16x4_t __p0) {
	41299	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41300	int16x4_t __ret;
	41301	__ret = (int16x4_t) __builtin_neon_vcvt_s16_v((int8x8_t)__rev0, 1);
	41302	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41303	return __ret;
	41304	}
	41305	#endif
	41306
	41307	#ifdef __LITTLE_ENDIAN__
	41308	__ai uint16x8_t vcvtq_u16_f16(float16x8_t __p0) {
	41309	uint16x8_t __ret;
	41310	__ret = (uint16x8_t) __builtin_neon_vcvtq_u16_v((int8x16_t)__p0, 49);
	41311	return __ret;
	41312	}
	41313	#else
	41314	__ai uint16x8_t vcvtq_u16_f16(float16x8_t __p0) {
	41315	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41316	uint16x8_t __ret;
	41317	__ret = (uint16x8_t) __builtin_neon_vcvtq_u16_v((int8x16_t)__rev0, 49);
	41318	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41319	return __ret;
	41320	}
	41321	#endif
	41322
	41323	#ifdef __LITTLE_ENDIAN__
	41324	__ai uint16x4_t vcvt_u16_f16(float16x4_t __p0) {
	41325	uint16x4_t __ret;
	41326	__ret = (uint16x4_t) __builtin_neon_vcvt_u16_v((int8x8_t)__p0, 17);
	41327	return __ret;
	41328	}
	41329	#else
	41330	__ai uint16x4_t vcvt_u16_f16(float16x4_t __p0) {
	41331	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41332	uint16x4_t __ret;
	41333	__ret = (uint16x4_t) __builtin_neon_vcvt_u16_v((int8x8_t)__rev0, 17);
	41334	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41335	return __ret;
	41336	}
	41337	#endif
	41338
	41339	#ifdef __LITTLE_ENDIAN__
	41340	__ai int16x8_t vcvtaq_s16_f16(float16x8_t __p0) {
	41341	int16x8_t __ret;
	41342	__ret = (int16x8_t) __builtin_neon_vcvtaq_s16_v((int8x16_t)__p0, 33);
	41343	return __ret;
	41344	}
	41345	#else
	41346	__ai int16x8_t vcvtaq_s16_f16(float16x8_t __p0) {
	41347	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41348	int16x8_t __ret;
	41349	__ret = (int16x8_t) __builtin_neon_vcvtaq_s16_v((int8x16_t)__rev0, 33);
	41350	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41351	return __ret;
	41352	}
	41353	#endif
	41354
	41355	#ifdef __LITTLE_ENDIAN__
	41356	__ai int16x4_t vcvta_s16_f16(float16x4_t __p0) {
	41357	int16x4_t __ret;
	41358	__ret = (int16x4_t) __builtin_neon_vcvta_s16_v((int8x8_t)__p0, 1);
	41359	return __ret;
	41360	}
	41361	#else
	41362	__ai int16x4_t vcvta_s16_f16(float16x4_t __p0) {
	41363	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41364	int16x4_t __ret;
	41365	__ret = (int16x4_t) __builtin_neon_vcvta_s16_v((int8x8_t)__rev0, 1);
	41366	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41367	return __ret;
	41368	}
	41369	#endif
	41370
	41371	#ifdef __LITTLE_ENDIAN__
	41372	__ai uint16x8_t vcvtaq_u16_f16(float16x8_t __p0) {
	41373	uint16x8_t __ret;
	41374	__ret = (uint16x8_t) __builtin_neon_vcvtaq_u16_v((int8x16_t)__p0, 49);
	41375	return __ret;
	41376	}
	41377	#else
	41378	__ai uint16x8_t vcvtaq_u16_f16(float16x8_t __p0) {
	41379	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41380	uint16x8_t __ret;
	41381	__ret = (uint16x8_t) __builtin_neon_vcvtaq_u16_v((int8x16_t)__rev0, 49);
	41382	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41383	return __ret;
	41384	}
	41385	#endif
	41386
	41387	#ifdef __LITTLE_ENDIAN__
	41388	__ai uint16x4_t vcvta_u16_f16(float16x4_t __p0) {
	41389	uint16x4_t __ret;
	41390	__ret = (uint16x4_t) __builtin_neon_vcvta_u16_v((int8x8_t)__p0, 17);
	41391	return __ret;
	41392	}
	41393	#else
	41394	__ai uint16x4_t vcvta_u16_f16(float16x4_t __p0) {
	41395	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41396	uint16x4_t __ret;
	41397	__ret = (uint16x4_t) __builtin_neon_vcvta_u16_v((int8x8_t)__rev0, 17);
	41398	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41399	return __ret;
	41400	}
	41401	#endif
	41402
	41403	#ifdef __LITTLE_ENDIAN__
	41404	__ai int16x8_t vcvtmq_s16_f16(float16x8_t __p0) {
	41405	int16x8_t __ret;
	41406	__ret = (int16x8_t) __builtin_neon_vcvtmq_s16_v((int8x16_t)__p0, 33);
	41407	return __ret;
	41408	}
	41409	#else
	41410	__ai int16x8_t vcvtmq_s16_f16(float16x8_t __p0) {
	41411	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41412	int16x8_t __ret;
	41413	__ret = (int16x8_t) __builtin_neon_vcvtmq_s16_v((int8x16_t)__rev0, 33);
	41414	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41415	return __ret;
	41416	}
	41417	#endif
	41418
	41419	#ifdef __LITTLE_ENDIAN__
	41420	__ai int16x4_t vcvtm_s16_f16(float16x4_t __p0) {
	41421	int16x4_t __ret;
	41422	__ret = (int16x4_t) __builtin_neon_vcvtm_s16_v((int8x8_t)__p0, 1);
	41423	return __ret;
	41424	}
	41425	#else
	41426	__ai int16x4_t vcvtm_s16_f16(float16x4_t __p0) {
	41427	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41428	int16x4_t __ret;
	41429	__ret = (int16x4_t) __builtin_neon_vcvtm_s16_v((int8x8_t)__rev0, 1);
	41430	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41431	return __ret;
	41432	}
	41433	#endif
	41434
	41435	#ifdef __LITTLE_ENDIAN__
	41436	__ai uint16x8_t vcvtmq_u16_f16(float16x8_t __p0) {
	41437	uint16x8_t __ret;
	41438	__ret = (uint16x8_t) __builtin_neon_vcvtmq_u16_v((int8x16_t)__p0, 49);
	41439	return __ret;
	41440	}
	41441	#else
	41442	__ai uint16x8_t vcvtmq_u16_f16(float16x8_t __p0) {
	41443	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41444	uint16x8_t __ret;
	41445	__ret = (uint16x8_t) __builtin_neon_vcvtmq_u16_v((int8x16_t)__rev0, 49);
	41446	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41447	return __ret;
	41448	}
	41449	#endif
	41450
	41451	#ifdef __LITTLE_ENDIAN__
	41452	__ai uint16x4_t vcvtm_u16_f16(float16x4_t __p0) {
	41453	uint16x4_t __ret;
	41454	__ret = (uint16x4_t) __builtin_neon_vcvtm_u16_v((int8x8_t)__p0, 17);
	41455	return __ret;
	41456	}
	41457	#else
	41458	__ai uint16x4_t vcvtm_u16_f16(float16x4_t __p0) {
	41459	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41460	uint16x4_t __ret;
	41461	__ret = (uint16x4_t) __builtin_neon_vcvtm_u16_v((int8x8_t)__rev0, 17);
	41462	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41463	return __ret;
	41464	}
	41465	#endif
	41466
	41467	#ifdef __LITTLE_ENDIAN__
	41468	__ai int16x8_t vcvtnq_s16_f16(float16x8_t __p0) {
	41469	int16x8_t __ret;
	41470	__ret = (int16x8_t) __builtin_neon_vcvtnq_s16_v((int8x16_t)__p0, 33);
	41471	return __ret;
	41472	}
	41473	#else
	41474	__ai int16x8_t vcvtnq_s16_f16(float16x8_t __p0) {
	41475	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41476	int16x8_t __ret;
	41477	__ret = (int16x8_t) __builtin_neon_vcvtnq_s16_v((int8x16_t)__rev0, 33);
	41478	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41479	return __ret;
	41480	}
	41481	#endif
	41482
	41483	#ifdef __LITTLE_ENDIAN__
	41484	__ai int16x4_t vcvtn_s16_f16(float16x4_t __p0) {
	41485	int16x4_t __ret;
	41486	__ret = (int16x4_t) __builtin_neon_vcvtn_s16_v((int8x8_t)__p0, 1);
	41487	return __ret;
	41488	}
	41489	#else
	41490	__ai int16x4_t vcvtn_s16_f16(float16x4_t __p0) {
	41491	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41492	int16x4_t __ret;
	41493	__ret = (int16x4_t) __builtin_neon_vcvtn_s16_v((int8x8_t)__rev0, 1);
	41494	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41495	return __ret;
	41496	}
	41497	#endif
	41498
	41499	#ifdef __LITTLE_ENDIAN__
	41500	__ai uint16x8_t vcvtnq_u16_f16(float16x8_t __p0) {
	41501	uint16x8_t __ret;
	41502	__ret = (uint16x8_t) __builtin_neon_vcvtnq_u16_v((int8x16_t)__p0, 49);
	41503	return __ret;
	41504	}
	41505	#else
	41506	__ai uint16x8_t vcvtnq_u16_f16(float16x8_t __p0) {
	41507	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41508	uint16x8_t __ret;
	41509	__ret = (uint16x8_t) __builtin_neon_vcvtnq_u16_v((int8x16_t)__rev0, 49);
	41510	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41511	return __ret;
	41512	}
	41513	#endif
	41514
	41515	#ifdef __LITTLE_ENDIAN__
	41516	__ai uint16x4_t vcvtn_u16_f16(float16x4_t __p0) {
	41517	uint16x4_t __ret;
	41518	__ret = (uint16x4_t) __builtin_neon_vcvtn_u16_v((int8x8_t)__p0, 17);
	41519	return __ret;
	41520	}
	41521	#else
	41522	__ai uint16x4_t vcvtn_u16_f16(float16x4_t __p0) {
	41523	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41524	uint16x4_t __ret;
	41525	__ret = (uint16x4_t) __builtin_neon_vcvtn_u16_v((int8x8_t)__rev0, 17);
	41526	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41527	return __ret;
	41528	}
	41529	#endif
	41530
	41531	#ifdef __LITTLE_ENDIAN__
	41532	__ai int16x8_t vcvtpq_s16_f16(float16x8_t __p0) {
	41533	int16x8_t __ret;
	41534	__ret = (int16x8_t) __builtin_neon_vcvtpq_s16_v((int8x16_t)__p0, 33);
	41535	return __ret;
	41536	}
	41537	#else
	41538	__ai int16x8_t vcvtpq_s16_f16(float16x8_t __p0) {
	41539	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41540	int16x8_t __ret;
	41541	__ret = (int16x8_t) __builtin_neon_vcvtpq_s16_v((int8x16_t)__rev0, 33);
	41542	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41543	return __ret;
	41544	}
	41545	#endif
	41546
	41547	#ifdef __LITTLE_ENDIAN__
	41548	__ai int16x4_t vcvtp_s16_f16(float16x4_t __p0) {
	41549	int16x4_t __ret;
	41550	__ret = (int16x4_t) __builtin_neon_vcvtp_s16_v((int8x8_t)__p0, 1);
	41551	return __ret;
	41552	}
	41553	#else
	41554	__ai int16x4_t vcvtp_s16_f16(float16x4_t __p0) {
	41555	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41556	int16x4_t __ret;
	41557	__ret = (int16x4_t) __builtin_neon_vcvtp_s16_v((int8x8_t)__rev0, 1);
	41558	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41559	return __ret;
	41560	}
	41561	#endif
	41562
	41563	#ifdef __LITTLE_ENDIAN__
	41564	__ai uint16x8_t vcvtpq_u16_f16(float16x8_t __p0) {
	41565	uint16x8_t __ret;
	41566	__ret = (uint16x8_t) __builtin_neon_vcvtpq_u16_v((int8x16_t)__p0, 49);
	41567	return __ret;
	41568	}
	41569	#else
	41570	__ai uint16x8_t vcvtpq_u16_f16(float16x8_t __p0) {
	41571	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41572	uint16x8_t __ret;
	41573	__ret = (uint16x8_t) __builtin_neon_vcvtpq_u16_v((int8x16_t)__rev0, 49);
	41574	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41575	return __ret;
	41576	}
	41577	#endif
	41578
	41579	#ifdef __LITTLE_ENDIAN__
	41580	__ai uint16x4_t vcvtp_u16_f16(float16x4_t __p0) {
	41581	uint16x4_t __ret;
	41582	__ret = (uint16x4_t) __builtin_neon_vcvtp_u16_v((int8x8_t)__p0, 17);
	41583	return __ret;
	41584	}
	41585	#else
	41586	__ai uint16x4_t vcvtp_u16_f16(float16x4_t __p0) {
	41587	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41588	uint16x4_t __ret;
	41589	__ret = (uint16x4_t) __builtin_neon_vcvtp_u16_v((int8x8_t)__rev0, 17);
	41590	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41591	return __ret;
	41592	}
	41593	#endif
	41594
	41595	#ifdef __LITTLE_ENDIAN__
	41596	__ai float16x8_t vdivq_f16(float16x8_t __p0, float16x8_t __p1) {
	41597	float16x8_t __ret;
	41598	__ret = __p0 / __p1;
	41599	return __ret;
	41600	}
	41601	#else
	41602	__ai float16x8_t vdivq_f16(float16x8_t __p0, float16x8_t __p1) {
	41603	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41604	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	41605	float16x8_t __ret;
	41606	__ret = __rev0 / __rev1;
	41607	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41608	return __ret;
	41609	}
	41610	#endif
	41611
	41612	#ifdef __LITTLE_ENDIAN__
	41613	__ai float16x4_t vdiv_f16(float16x4_t __p0, float16x4_t __p1) {
	41614	float16x4_t __ret;
	41615	__ret = __p0 / __p1;
	41616	return __ret;
	41617	}
	41618	#else
	41619	__ai float16x4_t vdiv_f16(float16x4_t __p0, float16x4_t __p1) {
	41620	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41621	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	41622	float16x4_t __ret;
	41623	__ret = __rev0 / __rev1;
	41624	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41625	return __ret;
	41626	}
	41627	#endif
	41628
	41629	#ifdef __LITTLE_ENDIAN__
	41630	#define vduph_lane_f16(__p0, __p1) __extension__ ({ \
	41631	float16x4_t __s0 = __p0; \
	41632	float16_t __ret; \
	41633	__ret = (float16_t) __builtin_neon_vduph_lane_f16((int8x8_t)__s0, __p1); \
	41634	__ret; \
	41635	})
	41636	#else
	41637	#define vduph_lane_f16(__p0, __p1) __extension__ ({ \
	41638	float16x4_t __s0 = __p0; \
	41639	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41640	float16_t __ret; \
	41641	__ret = (float16_t) __builtin_neon_vduph_lane_f16((int8x8_t)__rev0, __p1); \
	41642	__ret; \
	41643	})
	41644	#endif
	41645
	41646	#ifdef __LITTLE_ENDIAN__
	41647	#define vduph_laneq_f16(__p0, __p1) __extension__ ({ \
	41648	float16x8_t __s0 = __p0; \
	41649	float16_t __ret; \
	41650	__ret = (float16_t) __builtin_neon_vduph_laneq_f16((int8x16_t)__s0, __p1); \
	41651	__ret; \
	41652	})
	41653	#else
	41654	#define vduph_laneq_f16(__p0, __p1) __extension__ ({ \
	41655	float16x8_t __s0 = __p0; \
	41656	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41657	float16_t __ret; \
	41658	__ret = (float16_t) __builtin_neon_vduph_laneq_f16((int8x16_t)__rev0, __p1); \
	41659	__ret; \
	41660	})
	41661	#endif
	41662
	41663	#ifdef __LITTLE_ENDIAN__
	41664	#define vextq_f16(__p0, __p1, __p2) __extension__ ({ \
	41665	float16x8_t __s0 = __p0; \
	41666	float16x8_t __s1 = __p1; \
	41667	float16x8_t __ret; \
	41668	__ret = (float16x8_t) __builtin_neon_vextq_v((int8x16_t)__s0, (int8x16_t)__s1, __p2, 40); \
	41669	__ret; \
	41670	})
	41671	#else
	41672	#define vextq_f16(__p0, __p1, __p2) __extension__ ({ \
	41673	float16x8_t __s0 = __p0; \
	41674	float16x8_t __s1 = __p1; \
	41675	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41676	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	41677	float16x8_t __ret; \
	41678	__ret = (float16x8_t) __builtin_neon_vextq_v((int8x16_t)__rev0, (int8x16_t)__rev1, __p2, 40); \
	41679	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41680	__ret; \
	41681	})
	41682	#endif
	41683
	41684	#ifdef __LITTLE_ENDIAN__
	41685	#define vext_f16(__p0, __p1, __p2) __extension__ ({ \
	41686	float16x4_t __s0 = __p0; \
	41687	float16x4_t __s1 = __p1; \
	41688	float16x4_t __ret; \
	41689	__ret = (float16x4_t) __builtin_neon_vext_v((int8x8_t)__s0, (int8x8_t)__s1, __p2, 8); \
	41690	__ret; \
	41691	})
	41692	#else
	41693	#define vext_f16(__p0, __p1, __p2) __extension__ ({ \
	41694	float16x4_t __s0 = __p0; \
	41695	float16x4_t __s1 = __p1; \
	41696	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41697	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	41698	float16x4_t __ret; \
	41699	__ret = (float16x4_t) __builtin_neon_vext_v((int8x8_t)__rev0, (int8x8_t)__rev1, __p2, 8); \
	41700	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41701	__ret; \
	41702	})
	41703	#endif
	41704
	41705	#ifdef __LITTLE_ENDIAN__
	41706	__ai float16x8_t vfmaq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41707	float16x8_t __ret;
	41708	__ret = (float16x8_t) __builtin_neon_vfmaq_v((int8x16_t)__p0, (int8x16_t)__p1, (int8x16_t)__p2, 40);
	41709	return __ret;
	41710	}
	41711	#else
	41712	__ai float16x8_t vfmaq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41713	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41714	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	41715	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, 7, 6, 5, 4, 3, 2, 1, 0);
	41716	float16x8_t __ret;
	41717	__ret = (float16x8_t) __builtin_neon_vfmaq_v((int8x16_t)__rev0, (int8x16_t)__rev1, (int8x16_t)__rev2, 40);
	41718	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41719	return __ret;
	41720	}
	41721	__ai float16x8_t __noswap_vfmaq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41722	float16x8_t __ret;
	41723	__ret = (float16x8_t) __builtin_neon_vfmaq_v((int8x16_t)__p0, (int8x16_t)__p1, (int8x16_t)__p2, 40);
	41724	return __ret;
	41725	}
	41726	#endif
	41727
	41728	#ifdef __LITTLE_ENDIAN__
	41729	__ai float16x4_t vfma_f16(float16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	41730	float16x4_t __ret;
	41731	__ret = (float16x4_t) __builtin_neon_vfma_v((int8x8_t)__p0, (int8x8_t)__p1, (int8x8_t)__p2, 8);
	41732	return __ret;
	41733	}
	41734	#else
	41735	__ai float16x4_t vfma_f16(float16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	41736	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	41737	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	41738	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, 3, 2, 1, 0);
	41739	float16x4_t __ret;
	41740	__ret = (float16x4_t) __builtin_neon_vfma_v((int8x8_t)__rev0, (int8x8_t)__rev1, (int8x8_t)__rev2, 8);
	41741	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	41742	return __ret;
	41743	}
	41744	__ai float16x4_t __noswap_vfma_f16(float16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	41745	float16x4_t __ret;
	41746	__ret = (float16x4_t) __builtin_neon_vfma_v((int8x8_t)__p0, (int8x8_t)__p1, (int8x8_t)__p2, 8);
	41747	return __ret;
	41748	}
	41749	#endif
	41750
	41751	#ifdef __LITTLE_ENDIAN__
	41752	#define vfmah_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41753	float16_t __s0 = __p0; \
	41754	float16_t __s1 = __p1; \
	41755	float16x4_t __s2 = __p2; \
	41756	float16_t __ret; \
	41757	__ret = (float16_t) __builtin_neon_vfmah_lane_f16(__s0, __s1, (int8x8_t)__s2, __p3); \
	41758	__ret; \
	41759	})
	41760	#else
	41761	#define vfmah_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41762	float16_t __s0 = __p0; \
	41763	float16_t __s1 = __p1; \
	41764	float16x4_t __s2 = __p2; \
	41765	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, 3, 2, 1, 0); \
	41766	float16_t __ret; \
	41767	__ret = (float16_t) __builtin_neon_vfmah_lane_f16(__s0, __s1, (int8x8_t)__rev2, __p3); \
	41768	__ret; \
	41769	})
	41770	#define __noswap_vfmah_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41771	float16_t __s0 = __p0; \
	41772	float16_t __s1 = __p1; \
	41773	float16x4_t __s2 = __p2; \
	41774	float16_t __ret; \
	41775	__ret = (float16_t) __builtin_neon_vfmah_lane_f16(__s0, __s1, (int8x8_t)__s2, __p3); \
	41776	__ret; \
	41777	})
	41778	#endif
	41779
	41780	#ifdef __LITTLE_ENDIAN__
	41781	#define vfmaq_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41782	float16x8_t __s0 = __p0; \
	41783	float16x8_t __s1 = __p1; \
	41784	float16x4_t __s2 = __p2; \
	41785	float16x8_t __ret; \
	41786	__ret = (float16x8_t) __builtin_neon_vfmaq_lane_v((int8x16_t)__s0, (int8x16_t)__s1, (int8x8_t)__s2, __p3, 40); \
	41787	__ret; \
	41788	})
	41789	#else
	41790	#define vfmaq_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41791	float16x8_t __s0 = __p0; \
	41792	float16x8_t __s1 = __p1; \
	41793	float16x4_t __s2 = __p2; \
	41794	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41795	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	41796	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, 3, 2, 1, 0); \
	41797	float16x8_t __ret; \
	41798	__ret = (float16x8_t) __builtin_neon_vfmaq_lane_v((int8x16_t)__rev0, (int8x16_t)__rev1, (int8x8_t)__rev2, __p3, 40); \
	41799	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41800	__ret; \
	41801	})
	41802	#define __noswap_vfmaq_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41803	float16x8_t __s0 = __p0; \
	41804	float16x8_t __s1 = __p1; \
	41805	float16x4_t __s2 = __p2; \
	41806	float16x8_t __ret; \
	41807	__ret = (float16x8_t) __builtin_neon_vfmaq_lane_v((int8x16_t)__s0, (int8x16_t)__s1, (int8x8_t)__s2, __p3, 40); \
	41808	__ret; \
	41809	})
	41810	#endif
	41811
	41812	#ifdef __LITTLE_ENDIAN__
	41813	#define vfma_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41814	float16x4_t __s0 = __p0; \
	41815	float16x4_t __s1 = __p1; \
	41816	float16x4_t __s2 = __p2; \
	41817	float16x4_t __ret; \
	41818	__ret = (float16x4_t) __builtin_neon_vfma_lane_v((int8x8_t)__s0, (int8x8_t)__s1, (int8x8_t)__s2, __p3, 8); \
	41819	__ret; \
	41820	})
	41821	#else
	41822	#define vfma_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41823	float16x4_t __s0 = __p0; \
	41824	float16x4_t __s1 = __p1; \
	41825	float16x4_t __s2 = __p2; \
	41826	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41827	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	41828	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, 3, 2, 1, 0); \
	41829	float16x4_t __ret; \
	41830	__ret = (float16x4_t) __builtin_neon_vfma_lane_v((int8x8_t)__rev0, (int8x8_t)__rev1, (int8x8_t)__rev2, __p3, 8); \
	41831	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41832	__ret; \
	41833	})
	41834	#define __noswap_vfma_lane_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41835	float16x4_t __s0 = __p0; \
	41836	float16x4_t __s1 = __p1; \
	41837	float16x4_t __s2 = __p2; \
	41838	float16x4_t __ret; \
	41839	__ret = (float16x4_t) __builtin_neon_vfma_lane_v((int8x8_t)__s0, (int8x8_t)__s1, (int8x8_t)__s2, __p3, 8); \
	41840	__ret; \
	41841	})
	41842	#endif
	41843
	41844	#ifdef __LITTLE_ENDIAN__
	41845	#define vfmah_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41846	float16_t __s0 = __p0; \
	41847	float16_t __s1 = __p1; \
	41848	float16x8_t __s2 = __p2; \
	41849	float16_t __ret; \
	41850	__ret = (float16_t) __builtin_neon_vfmah_laneq_f16(__s0, __s1, (int8x16_t)__s2, __p3); \
	41851	__ret; \
	41852	})
	41853	#else
	41854	#define vfmah_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41855	float16_t __s0 = __p0; \
	41856	float16_t __s1 = __p1; \
	41857	float16x8_t __s2 = __p2; \
	41858	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, 7, 6, 5, 4, 3, 2, 1, 0); \
	41859	float16_t __ret; \
	41860	__ret = (float16_t) __builtin_neon_vfmah_laneq_f16(__s0, __s1, (int8x16_t)__rev2, __p3); \
	41861	__ret; \
	41862	})
	41863	#define __noswap_vfmah_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41864	float16_t __s0 = __p0; \
	41865	float16_t __s1 = __p1; \
	41866	float16x8_t __s2 = __p2; \
	41867	float16_t __ret; \
	41868	__ret = (float16_t) __builtin_neon_vfmah_laneq_f16(__s0, __s1, (int8x16_t)__s2, __p3); \
	41869	__ret; \
	41870	})
	41871	#endif
	41872
	41873	#ifdef __LITTLE_ENDIAN__
	41874	#define vfmaq_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41875	float16x8_t __s0 = __p0; \
	41876	float16x8_t __s1 = __p1; \
	41877	float16x8_t __s2 = __p2; \
	41878	float16x8_t __ret; \
	41879	__ret = (float16x8_t) __builtin_neon_vfmaq_laneq_v((int8x16_t)__s0, (int8x16_t)__s1, (int8x16_t)__s2, __p3, 40); \
	41880	__ret; \
	41881	})
	41882	#else
	41883	#define vfmaq_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41884	float16x8_t __s0 = __p0; \
	41885	float16x8_t __s1 = __p1; \
	41886	float16x8_t __s2 = __p2; \
	41887	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41888	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	41889	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, 7, 6, 5, 4, 3, 2, 1, 0); \
	41890	float16x8_t __ret; \
	41891	__ret = (float16x8_t) __builtin_neon_vfmaq_laneq_v((int8x16_t)__rev0, (int8x16_t)__rev1, (int8x16_t)__rev2, __p3, 40); \
	41892	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41893	__ret; \
	41894	})
	41895	#define __noswap_vfmaq_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41896	float16x8_t __s0 = __p0; \
	41897	float16x8_t __s1 = __p1; \
	41898	float16x8_t __s2 = __p2; \
	41899	float16x8_t __ret; \
	41900	__ret = (float16x8_t) __builtin_neon_vfmaq_laneq_v((int8x16_t)__s0, (int8x16_t)__s1, (int8x16_t)__s2, __p3, 40); \
	41901	__ret; \
	41902	})
	41903	#endif
	41904
	41905	#ifdef __LITTLE_ENDIAN__
	41906	#define vfma_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41907	float16x4_t __s0 = __p0; \
	41908	float16x4_t __s1 = __p1; \
	41909	float16x8_t __s2 = __p2; \
	41910	float16x4_t __ret; \
	41911	__ret = (float16x4_t) __builtin_neon_vfma_laneq_v((int8x8_t)__s0, (int8x8_t)__s1, (int8x16_t)__s2, __p3, 8); \
	41912	__ret; \
	41913	})
	41914	#else
	41915	#define vfma_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41916	float16x4_t __s0 = __p0; \
	41917	float16x4_t __s1 = __p1; \
	41918	float16x8_t __s2 = __p2; \
	41919	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41920	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	41921	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__s2, __s2, 7, 6, 5, 4, 3, 2, 1, 0); \
	41922	float16x4_t __ret; \
	41923	__ret = (float16x4_t) __builtin_neon_vfma_laneq_v((int8x8_t)__rev0, (int8x8_t)__rev1, (int8x16_t)__rev2, __p3, 8); \
	41924	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41925	__ret; \
	41926	})
	41927	#define __noswap_vfma_laneq_f16(__p0, __p1, __p2, __p3) __extension__ ({ \
	41928	float16x4_t __s0 = __p0; \
	41929	float16x4_t __s1 = __p1; \
	41930	float16x8_t __s2 = __p2; \
	41931	float16x4_t __ret; \
	41932	__ret = (float16x4_t) __builtin_neon_vfma_laneq_v((int8x8_t)__s0, (int8x8_t)__s1, (int8x16_t)__s2, __p3, 8); \
	41933	__ret; \
	41934	})
	41935	#endif
	41936
	41937	#ifdef __LITTLE_ENDIAN__
	41938	#define vfmaq_n_f16(__p0, __p1, __p2) __extension__ ({ \
	41939	float16x8_t __s0 = __p0; \
	41940	float16x8_t __s1 = __p1; \
	41941	float16_t __s2 = __p2; \
	41942	float16x8_t __ret; \
	41943	__ret = vfmaq_f16(__s0, __s1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	41944	__ret; \
	41945	})
	41946	#else
	41947	#define vfmaq_n_f16(__p0, __p1, __p2) __extension__ ({ \
	41948	float16x8_t __s0 = __p0; \
	41949	float16x8_t __s1 = __p1; \
	41950	float16_t __s2 = __p2; \
	41951	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	41952	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	41953	float16x8_t __ret; \
	41954	__ret = __noswap_vfmaq_f16(__rev0, __rev1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	41955	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	41956	__ret; \
	41957	})
	41958	#endif
	41959
	41960	#ifdef __LITTLE_ENDIAN__
	41961	#define vfma_n_f16(__p0, __p1, __p2) __extension__ ({ \
	41962	float16x4_t __s0 = __p0; \
	41963	float16x4_t __s1 = __p1; \
	41964	float16_t __s2 = __p2; \
	41965	float16x4_t __ret; \
	41966	__ret = vfma_f16(__s0, __s1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
	41967	__ret; \
	41968	})
	41969	#else
	41970	#define vfma_n_f16(__p0, __p1, __p2) __extension__ ({ \
	41971	float16x4_t __s0 = __p0; \
	41972	float16x4_t __s1 = __p1; \
	41973	float16_t __s2 = __p2; \
	41974	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	41975	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	41976	float16x4_t __ret; \
	41977	__ret = __noswap_vfma_f16(__rev0, __rev1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
	41978	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	41979	__ret; \
	41980	})
	41981	#endif
	41982
	41983	#ifdef __LITTLE_ENDIAN__
	41984	__ai float16x8_t vfmsq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41985	float16x8_t __ret;
	41986	__ret = vfmaq_f16(__p0, -__p1, __p2);
	41987	return __ret;
	41988	}
	41989	#else
	41990	__ai float16x8_t vfmsq_f16(float16x8_t __p0, float16x8_t __p1, float16x8_t __p2) {
	41991	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	41992	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	41993	float16x8_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, 7, 6, 5, 4, 3, 2, 1, 0);
	41994	float16x8_t __ret;
	41995	__ret = __noswap_vfmaq_f16(__rev0, -__rev1, __rev2);
	41996	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	41997	return __ret;
	41998	}
	41999	#endif
	42000
	42001	#ifdef __LITTLE_ENDIAN__
	42002	__ai float16x4_t vfms_f16(float16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	42003	float16x4_t __ret;
	42004	__ret = vfma_f16(__p0, -__p1, __p2);
	42005	return __ret;
	42006	}
	42007	#else
	42008	__ai float16x4_t vfms_f16(float16x4_t __p0, float16x4_t __p1, float16x4_t __p2) {
	42009	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42010	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42011	float16x4_t __rev2; __rev2 = __builtin_shufflevector(__p2, __p2, 3, 2, 1, 0);
	42012	float16x4_t __ret;
	42013	__ret = __noswap_vfma_f16(__rev0, -__rev1, __rev2);
	42014	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42015	return __ret;
	42016	}
	42017	#endif
	42018
	42019	#ifdef __LITTLE_ENDIAN__
	42020	#define vfmsh_lane_f16(__p0_0, __p1_0, __p2_0, __p3_0) __extension__ ({ \
	42021	float16_t __s0_0 = __p0_0; \
	42022	float16_t __s1_0 = __p1_0; \
	42023	float16x4_t __s2_0 = __p2_0; \
	42024	float16_t __ret_0; \
	42025	__ret_0 = vfmah_lane_f16(__s0_0, -__s1_0, __s2_0, __p3_0); \
	42026	__ret_0; \
	42027	})
	42028	#else
	42029	#define vfmsh_lane_f16(__p0_1, __p1_1, __p2_1, __p3_1) __extension__ ({ \
	42030	float16_t __s0_1 = __p0_1; \
	42031	float16_t __s1_1 = __p1_1; \
	42032	float16x4_t __s2_1 = __p2_1; \
	42033	float16x4_t __rev2_1; __rev2_1 = __builtin_shufflevector(__s2_1, __s2_1, 3, 2, 1, 0); \
	42034	float16_t __ret_1; \
	42035	__ret_1 = __noswap_vfmah_lane_f16(__s0_1, -__s1_1, __rev2_1, __p3_1); \
	42036	__ret_1; \
	42037	})
	42038	#endif
	42039
	42040	#ifdef __LITTLE_ENDIAN__
	42041	#define vfmsq_lane_f16(__p0_2, __p1_2, __p2_2, __p3_2) __extension__ ({ \
	42042	float16x8_t __s0_2 = __p0_2; \
	42043	float16x8_t __s1_2 = __p1_2; \
	42044	float16x4_t __s2_2 = __p2_2; \
	42045	float16x8_t __ret_2; \
	42046	__ret_2 = vfmaq_lane_f16(__s0_2, -__s1_2, __s2_2, __p3_2); \
	42047	__ret_2; \
	42048	})
	42049	#else
	42050	#define vfmsq_lane_f16(__p0_3, __p1_3, __p2_3, __p3_3) __extension__ ({ \
	42051	float16x8_t __s0_3 = __p0_3; \
	42052	float16x8_t __s1_3 = __p1_3; \
	42053	float16x4_t __s2_3 = __p2_3; \
	42054	float16x8_t __rev0_3; __rev0_3 = __builtin_shufflevector(__s0_3, __s0_3, 7, 6, 5, 4, 3, 2, 1, 0); \
	42055	float16x8_t __rev1_3; __rev1_3 = __builtin_shufflevector(__s1_3, __s1_3, 7, 6, 5, 4, 3, 2, 1, 0); \
	42056	float16x4_t __rev2_3; __rev2_3 = __builtin_shufflevector(__s2_3, __s2_3, 3, 2, 1, 0); \
	42057	float16x8_t __ret_3; \
	42058	__ret_3 = __noswap_vfmaq_lane_f16(__rev0_3, -__rev1_3, __rev2_3, __p3_3); \
	42059	__ret_3 = __builtin_shufflevector(__ret_3, __ret_3, 7, 6, 5, 4, 3, 2, 1, 0); \
	42060	__ret_3; \
	42061	})
	42062	#endif
	42063
	42064	#ifdef __LITTLE_ENDIAN__
	42065	#define vfms_lane_f16(__p0_4, __p1_4, __p2_4, __p3_4) __extension__ ({ \
	42066	float16x4_t __s0_4 = __p0_4; \
	42067	float16x4_t __s1_4 = __p1_4; \
	42068	float16x4_t __s2_4 = __p2_4; \
	42069	float16x4_t __ret_4; \
	42070	__ret_4 = vfma_lane_f16(__s0_4, -__s1_4, __s2_4, __p3_4); \
	42071	__ret_4; \
	42072	})
	42073	#else
	42074	#define vfms_lane_f16(__p0_5, __p1_5, __p2_5, __p3_5) __extension__ ({ \
	42075	float16x4_t __s0_5 = __p0_5; \
	42076	float16x4_t __s1_5 = __p1_5; \
	42077	float16x4_t __s2_5 = __p2_5; \
	42078	float16x4_t __rev0_5; __rev0_5 = __builtin_shufflevector(__s0_5, __s0_5, 3, 2, 1, 0); \
	42079	float16x4_t __rev1_5; __rev1_5 = __builtin_shufflevector(__s1_5, __s1_5, 3, 2, 1, 0); \
	42080	float16x4_t __rev2_5; __rev2_5 = __builtin_shufflevector(__s2_5, __s2_5, 3, 2, 1, 0); \
	42081	float16x4_t __ret_5; \
	42082	__ret_5 = __noswap_vfma_lane_f16(__rev0_5, -__rev1_5, __rev2_5, __p3_5); \
	42083	__ret_5 = __builtin_shufflevector(__ret_5, __ret_5, 3, 2, 1, 0); \
	42084	__ret_5; \
	42085	})
	42086	#endif
	42087
	42088	#ifdef __LITTLE_ENDIAN__
	42089	#define vfmsh_laneq_f16(__p0_6, __p1_6, __p2_6, __p3_6) __extension__ ({ \
	42090	float16_t __s0_6 = __p0_6; \
	42091	float16_t __s1_6 = __p1_6; \
	42092	float16x8_t __s2_6 = __p2_6; \
	42093	float16_t __ret_6; \
	42094	__ret_6 = vfmah_laneq_f16(__s0_6, -__s1_6, __s2_6, __p3_6); \
	42095	__ret_6; \
	42096	})
	42097	#else
	42098	#define vfmsh_laneq_f16(__p0_7, __p1_7, __p2_7, __p3_7) __extension__ ({ \
	42099	float16_t __s0_7 = __p0_7; \
	42100	float16_t __s1_7 = __p1_7; \
	42101	float16x8_t __s2_7 = __p2_7; \
	42102	float16x8_t __rev2_7; __rev2_7 = __builtin_shufflevector(__s2_7, __s2_7, 7, 6, 5, 4, 3, 2, 1, 0); \
	42103	float16_t __ret_7; \
	42104	__ret_7 = __noswap_vfmah_laneq_f16(__s0_7, -__s1_7, __rev2_7, __p3_7); \
	42105	__ret_7; \
	42106	})
	42107	#endif
	42108
	42109	#ifdef __LITTLE_ENDIAN__
	42110	#define vfmsq_laneq_f16(__p0_8, __p1_8, __p2_8, __p3_8) __extension__ ({ \
	42111	float16x8_t __s0_8 = __p0_8; \
	42112	float16x8_t __s1_8 = __p1_8; \
	42113	float16x8_t __s2_8 = __p2_8; \
	42114	float16x8_t __ret_8; \
	42115	__ret_8 = vfmaq_laneq_f16(__s0_8, -__s1_8, __s2_8, __p3_8); \
	42116	__ret_8; \
	42117	})
	42118	#else
	42119	#define vfmsq_laneq_f16(__p0_9, __p1_9, __p2_9, __p3_9) __extension__ ({ \
	42120	float16x8_t __s0_9 = __p0_9; \
	42121	float16x8_t __s1_9 = __p1_9; \
	42122	float16x8_t __s2_9 = __p2_9; \
	42123	float16x8_t __rev0_9; __rev0_9 = __builtin_shufflevector(__s0_9, __s0_9, 7, 6, 5, 4, 3, 2, 1, 0); \
	42124	float16x8_t __rev1_9; __rev1_9 = __builtin_shufflevector(__s1_9, __s1_9, 7, 6, 5, 4, 3, 2, 1, 0); \
	42125	float16x8_t __rev2_9; __rev2_9 = __builtin_shufflevector(__s2_9, __s2_9, 7, 6, 5, 4, 3, 2, 1, 0); \
	42126	float16x8_t __ret_9; \
	42127	__ret_9 = __noswap_vfmaq_laneq_f16(__rev0_9, -__rev1_9, __rev2_9, __p3_9); \
	42128	__ret_9 = __builtin_shufflevector(__ret_9, __ret_9, 7, 6, 5, 4, 3, 2, 1, 0); \
	42129	__ret_9; \
	42130	})
	42131	#endif
	42132
	42133	#ifdef __LITTLE_ENDIAN__
	42134	#define vfms_laneq_f16(__p0_10, __p1_10, __p2_10, __p3_10) __extension__ ({ \
	42135	float16x4_t __s0_10 = __p0_10; \
	42136	float16x4_t __s1_10 = __p1_10; \
	42137	float16x8_t __s2_10 = __p2_10; \
	42138	float16x4_t __ret_10; \
	42139	__ret_10 = vfma_laneq_f16(__s0_10, -__s1_10, __s2_10, __p3_10); \
	42140	__ret_10; \
	42141	})
	42142	#else
	42143	#define vfms_laneq_f16(__p0_11, __p1_11, __p2_11, __p3_11) __extension__ ({ \
	42144	float16x4_t __s0_11 = __p0_11; \
	42145	float16x4_t __s1_11 = __p1_11; \
	42146	float16x8_t __s2_11 = __p2_11; \
	42147	float16x4_t __rev0_11; __rev0_11 = __builtin_shufflevector(__s0_11, __s0_11, 3, 2, 1, 0); \
	42148	float16x4_t __rev1_11; __rev1_11 = __builtin_shufflevector(__s1_11, __s1_11, 3, 2, 1, 0); \
	42149	float16x8_t __rev2_11; __rev2_11 = __builtin_shufflevector(__s2_11, __s2_11, 7, 6, 5, 4, 3, 2, 1, 0); \
	42150	float16x4_t __ret_11; \
	42151	__ret_11 = __noswap_vfma_laneq_f16(__rev0_11, -__rev1_11, __rev2_11, __p3_11); \
	42152	__ret_11 = __builtin_shufflevector(__ret_11, __ret_11, 3, 2, 1, 0); \
	42153	__ret_11; \
	42154	})
	42155	#endif
	42156
	42157	#ifdef __LITTLE_ENDIAN__
	42158	#define vfmsq_n_f16(__p0, __p1, __p2) __extension__ ({ \
	42159	float16x8_t __s0 = __p0; \
	42160	float16x8_t __s1 = __p1; \
	42161	float16_t __s2 = __p2; \
	42162	float16x8_t __ret; \
	42163	__ret = vfmaq_f16(__s0, -__s1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	42164	__ret; \
	42165	})
	42166	#else
	42167	#define vfmsq_n_f16(__p0, __p1, __p2) __extension__ ({ \
	42168	float16x8_t __s0 = __p0; \
	42169	float16x8_t __s1 = __p1; \
	42170	float16_t __s2 = __p2; \
	42171	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42172	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	42173	float16x8_t __ret; \
	42174	__ret = __noswap_vfmaq_f16(__rev0, -__rev1, (float16x8_t) {__s2, __s2, __s2, __s2, __s2, __s2, __s2, __s2}); \
	42175	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42176	__ret; \
	42177	})
	42178	#endif
	42179
	42180	#ifdef __LITTLE_ENDIAN__
	42181	#define vfms_n_f16(__p0, __p1, __p2) __extension__ ({ \
	42182	float16x4_t __s0 = __p0; \
	42183	float16x4_t __s1 = __p1; \
	42184	float16_t __s2 = __p2; \
	42185	float16x4_t __ret; \
	42186	__ret = vfma_f16(__s0, -__s1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
	42187	__ret; \
	42188	})
	42189	#else
	42190	#define vfms_n_f16(__p0, __p1, __p2) __extension__ ({ \
	42191	float16x4_t __s0 = __p0; \
	42192	float16x4_t __s1 = __p1; \
	42193	float16_t __s2 = __p2; \
	42194	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42195	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	42196	float16x4_t __ret; \
	42197	__ret = __noswap_vfma_f16(__rev0, -__rev1, (float16x4_t) {__s2, __s2, __s2, __s2}); \
	42198	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42199	__ret; \
	42200	})
	42201	#endif
	42202
	42203	#ifdef __LITTLE_ENDIAN__
	42204	__ai float16x8_t vmaxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42205	float16x8_t __ret;
	42206	__ret = (float16x8_t) __builtin_neon_vmaxq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42207	return __ret;
	42208	}
	42209	#else
	42210	__ai float16x8_t vmaxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42211	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42212	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42213	float16x8_t __ret;
	42214	__ret = (float16x8_t) __builtin_neon_vmaxq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42215	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42216	return __ret;
	42217	}
	42218	#endif
	42219
	42220	#ifdef __LITTLE_ENDIAN__
	42221	__ai float16x4_t vmax_f16(float16x4_t __p0, float16x4_t __p1) {
	42222	float16x4_t __ret;
	42223	__ret = (float16x4_t) __builtin_neon_vmax_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42224	return __ret;
	42225	}
	42226	#else
	42227	__ai float16x4_t vmax_f16(float16x4_t __p0, float16x4_t __p1) {
	42228	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42229	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42230	float16x4_t __ret;
	42231	__ret = (float16x4_t) __builtin_neon_vmax_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42232	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42233	return __ret;
	42234	}
	42235	#endif
	42236
	42237	#ifdef __LITTLE_ENDIAN__
	42238	__ai float16x8_t vmaxnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42239	float16x8_t __ret;
	42240	__ret = (float16x8_t) __builtin_neon_vmaxnmq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42241	return __ret;
	42242	}
	42243	#else
	42244	__ai float16x8_t vmaxnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42245	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42246	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42247	float16x8_t __ret;
	42248	__ret = (float16x8_t) __builtin_neon_vmaxnmq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42249	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42250	return __ret;
	42251	}
	42252	#endif
	42253
	42254	#ifdef __LITTLE_ENDIAN__
	42255	__ai float16x4_t vmaxnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42256	float16x4_t __ret;
	42257	__ret = (float16x4_t) __builtin_neon_vmaxnm_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42258	return __ret;
	42259	}
	42260	#else
	42261	__ai float16x4_t vmaxnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42262	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42263	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42264	float16x4_t __ret;
	42265	__ret = (float16x4_t) __builtin_neon_vmaxnm_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42266	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42267	return __ret;
	42268	}
	42269	#endif
	42270
	42271	#ifdef __LITTLE_ENDIAN__
	42272	#define vmaxnmvq_f16(__p0) __extension__ ({ \
	42273	float16x8_t __s0 = __p0; \
	42274	float16_t __ret; \
	42275	__ret = (float16_t) __builtin_neon_vmaxnmvq_f16((int8x16_t)__s0); \
	42276	__ret; \
	42277	})
	42278	#else
	42279	#define vmaxnmvq_f16(__p0) __extension__ ({ \
	42280	float16x8_t __s0 = __p0; \
	42281	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42282	float16_t __ret; \
	42283	__ret = (float16_t) __builtin_neon_vmaxnmvq_f16((int8x16_t)__rev0); \
	42284	__ret; \
	42285	})
	42286	#endif
	42287
	42288	#ifdef __LITTLE_ENDIAN__
	42289	#define vmaxnmv_f16(__p0) __extension__ ({ \
	42290	float16x4_t __s0 = __p0; \
	42291	float16_t __ret; \
	42292	__ret = (float16_t) __builtin_neon_vmaxnmv_f16((int8x8_t)__s0); \
	42293	__ret; \
	42294	})
	42295	#else
	42296	#define vmaxnmv_f16(__p0) __extension__ ({ \
	42297	float16x4_t __s0 = __p0; \
	42298	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42299	float16_t __ret; \
	42300	__ret = (float16_t) __builtin_neon_vmaxnmv_f16((int8x8_t)__rev0); \
	42301	__ret; \
	42302	})
	42303	#endif
	42304
	42305	#ifdef __LITTLE_ENDIAN__
	42306	#define vmaxvq_f16(__p0) __extension__ ({ \
	42307	float16x8_t __s0 = __p0; \
	42308	float16_t __ret; \
	42309	__ret = (float16_t) __builtin_neon_vmaxvq_f16((int8x16_t)__s0); \
	42310	__ret; \
	42311	})
	42312	#else
	42313	#define vmaxvq_f16(__p0) __extension__ ({ \
	42314	float16x8_t __s0 = __p0; \
	42315	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42316	float16_t __ret; \
	42317	__ret = (float16_t) __builtin_neon_vmaxvq_f16((int8x16_t)__rev0); \
	42318	__ret; \
	42319	})
	42320	#endif
	42321
	42322	#ifdef __LITTLE_ENDIAN__
	42323	#define vmaxv_f16(__p0) __extension__ ({ \
	42324	float16x4_t __s0 = __p0; \
	42325	float16_t __ret; \
	42326	__ret = (float16_t) __builtin_neon_vmaxv_f16((int8x8_t)__s0); \
	42327	__ret; \
	42328	})
	42329	#else
	42330	#define vmaxv_f16(__p0) __extension__ ({ \
	42331	float16x4_t __s0 = __p0; \
	42332	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42333	float16_t __ret; \
	42334	__ret = (float16_t) __builtin_neon_vmaxv_f16((int8x8_t)__rev0); \
	42335	__ret; \
	42336	})
	42337	#endif
	42338
	42339	#ifdef __LITTLE_ENDIAN__
	42340	__ai float16x8_t vminq_f16(float16x8_t __p0, float16x8_t __p1) {
	42341	float16x8_t __ret;
	42342	__ret = (float16x8_t) __builtin_neon_vminq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42343	return __ret;
	42344	}
	42345	#else
	42346	__ai float16x8_t vminq_f16(float16x8_t __p0, float16x8_t __p1) {
	42347	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42348	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42349	float16x8_t __ret;
	42350	__ret = (float16x8_t) __builtin_neon_vminq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42351	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42352	return __ret;
	42353	}
	42354	#endif
	42355
	42356	#ifdef __LITTLE_ENDIAN__
	42357	__ai float16x4_t vmin_f16(float16x4_t __p0, float16x4_t __p1) {
	42358	float16x4_t __ret;
	42359	__ret = (float16x4_t) __builtin_neon_vmin_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42360	return __ret;
	42361	}
	42362	#else
	42363	__ai float16x4_t vmin_f16(float16x4_t __p0, float16x4_t __p1) {
	42364	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42365	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42366	float16x4_t __ret;
	42367	__ret = (float16x4_t) __builtin_neon_vmin_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42368	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42369	return __ret;
	42370	}
	42371	#endif
	42372
	42373	#ifdef __LITTLE_ENDIAN__
	42374	__ai float16x8_t vminnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42375	float16x8_t __ret;
	42376	__ret = (float16x8_t) __builtin_neon_vminnmq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42377	return __ret;
	42378	}
	42379	#else
	42380	__ai float16x8_t vminnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42381	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42382	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42383	float16x8_t __ret;
	42384	__ret = (float16x8_t) __builtin_neon_vminnmq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42385	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42386	return __ret;
	42387	}
	42388	#endif
	42389
	42390	#ifdef __LITTLE_ENDIAN__
	42391	__ai float16x4_t vminnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42392	float16x4_t __ret;
	42393	__ret = (float16x4_t) __builtin_neon_vminnm_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42394	return __ret;
	42395	}
	42396	#else
	42397	__ai float16x4_t vminnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42398	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42399	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42400	float16x4_t __ret;
	42401	__ret = (float16x4_t) __builtin_neon_vminnm_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42402	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42403	return __ret;
	42404	}
	42405	#endif
	42406
	42407	#ifdef __LITTLE_ENDIAN__
	42408	#define vminnmvq_f16(__p0) __extension__ ({ \
	42409	float16x8_t __s0 = __p0; \
	42410	float16_t __ret; \
	42411	__ret = (float16_t) __builtin_neon_vminnmvq_f16((int8x16_t)__s0); \
	42412	__ret; \
	42413	})
	42414	#else
	42415	#define vminnmvq_f16(__p0) __extension__ ({ \
	42416	float16x8_t __s0 = __p0; \
	42417	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42418	float16_t __ret; \
	42419	__ret = (float16_t) __builtin_neon_vminnmvq_f16((int8x16_t)__rev0); \
	42420	__ret; \
	42421	})
	42422	#endif
	42423
	42424	#ifdef __LITTLE_ENDIAN__
	42425	#define vminnmv_f16(__p0) __extension__ ({ \
	42426	float16x4_t __s0 = __p0; \
	42427	float16_t __ret; \
	42428	__ret = (float16_t) __builtin_neon_vminnmv_f16((int8x8_t)__s0); \
	42429	__ret; \
	42430	})
	42431	#else
	42432	#define vminnmv_f16(__p0) __extension__ ({ \
	42433	float16x4_t __s0 = __p0; \
	42434	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42435	float16_t __ret; \
	42436	__ret = (float16_t) __builtin_neon_vminnmv_f16((int8x8_t)__rev0); \
	42437	__ret; \
	42438	})
	42439	#endif
	42440
	42441	#ifdef __LITTLE_ENDIAN__
	42442	#define vminvq_f16(__p0) __extension__ ({ \
	42443	float16x8_t __s0 = __p0; \
	42444	float16_t __ret; \
	42445	__ret = (float16_t) __builtin_neon_vminvq_f16((int8x16_t)__s0); \
	42446	__ret; \
	42447	})
	42448	#else
	42449	#define vminvq_f16(__p0) __extension__ ({ \
	42450	float16x8_t __s0 = __p0; \
	42451	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42452	float16_t __ret; \
	42453	__ret = (float16_t) __builtin_neon_vminvq_f16((int8x16_t)__rev0); \
	42454	__ret; \
	42455	})
	42456	#endif
	42457
	42458	#ifdef __LITTLE_ENDIAN__
	42459	#define vminv_f16(__p0) __extension__ ({ \
	42460	float16x4_t __s0 = __p0; \
	42461	float16_t __ret; \
	42462	__ret = (float16_t) __builtin_neon_vminv_f16((int8x8_t)__s0); \
	42463	__ret; \
	42464	})
	42465	#else
	42466	#define vminv_f16(__p0) __extension__ ({ \
	42467	float16x4_t __s0 = __p0; \
	42468	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42469	float16_t __ret; \
	42470	__ret = (float16_t) __builtin_neon_vminv_f16((int8x8_t)__rev0); \
	42471	__ret; \
	42472	})
	42473	#endif
	42474
	42475	#ifdef __LITTLE_ENDIAN__
	42476	__ai float16x8_t vmulq_f16(float16x8_t __p0, float16x8_t __p1) {
	42477	float16x8_t __ret;
	42478	__ret = __p0 * __p1;
	42479	return __ret;
	42480	}
	42481	#else
	42482	__ai float16x8_t vmulq_f16(float16x8_t __p0, float16x8_t __p1) {
	42483	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42484	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42485	float16x8_t __ret;
	42486	__ret = __rev0 * __rev1;
	42487	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42488	return __ret;
	42489	}
	42490	#endif
	42491
	42492	#ifdef __LITTLE_ENDIAN__
	42493	__ai float16x4_t vmul_f16(float16x4_t __p0, float16x4_t __p1) {
	42494	float16x4_t __ret;
	42495	__ret = __p0 * __p1;
	42496	return __ret;
	42497	}
	42498	#else
	42499	__ai float16x4_t vmul_f16(float16x4_t __p0, float16x4_t __p1) {
	42500	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42501	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42502	float16x4_t __ret;
	42503	__ret = __rev0 * __rev1;
	42504	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42505	return __ret;
	42506	}
	42507	#endif
	42508
	42509	#ifdef __LITTLE_ENDIAN__
	42510	#define vmulq_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42511	float16x8_t __s0 = __p0; \
	42512	float16x4_t __s1 = __p1; \
	42513	float16x8_t __ret; \
	42514	__ret = __s0 * __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2); \
	42515	__ret; \
	42516	})
	42517	#else
	42518	#define vmulq_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42519	float16x8_t __s0 = __p0; \
	42520	float16x4_t __s1 = __p1; \
	42521	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42522	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	42523	float16x8_t __ret; \
	42524	__ret = __rev0 * __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2); \
	42525	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42526	__ret; \
	42527	})
	42528	#endif
	42529
	42530	#ifdef __LITTLE_ENDIAN__
	42531	#define vmul_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42532	float16x4_t __s0 = __p0; \
	42533	float16x4_t __s1 = __p1; \
	42534	float16x4_t __ret; \
	42535	__ret = __s0 * __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2); \
	42536	__ret; \
	42537	})
	42538	#else
	42539	#define vmul_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42540	float16x4_t __s0 = __p0; \
	42541	float16x4_t __s1 = __p1; \
	42542	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42543	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	42544	float16x4_t __ret; \
	42545	__ret = __rev0 * __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2); \
	42546	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42547	__ret; \
	42548	})
	42549	#endif
	42550
	42551	#ifdef __LITTLE_ENDIAN__
	42552	#define vmulq_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42553	float16x8_t __s0 = __p0; \
	42554	float16x8_t __s1 = __p1; \
	42555	float16x8_t __ret; \
	42556	__ret = __s0 * __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2); \
	42557	__ret; \
	42558	})
	42559	#else
	42560	#define vmulq_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42561	float16x8_t __s0 = __p0; \
	42562	float16x8_t __s1 = __p1; \
	42563	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42564	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	42565	float16x8_t __ret; \
	42566	__ret = __rev0 * __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2); \
	42567	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42568	__ret; \
	42569	})
	42570	#endif
	42571
	42572	#ifdef __LITTLE_ENDIAN__
	42573	#define vmul_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42574	float16x4_t __s0 = __p0; \
	42575	float16x8_t __s1 = __p1; \
	42576	float16x4_t __ret; \
	42577	__ret = __s0 * __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2); \
	42578	__ret; \
	42579	})
	42580	#else
	42581	#define vmul_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42582	float16x4_t __s0 = __p0; \
	42583	float16x8_t __s1 = __p1; \
	42584	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42585	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	42586	float16x4_t __ret; \
	42587	__ret = __rev0 * __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2); \
	42588	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42589	__ret; \
	42590	})
	42591	#endif
	42592
	42593	#ifdef __LITTLE_ENDIAN__
	42594	#define vmulq_n_f16(__p0, __p1) __extension__ ({ \
	42595	float16x8_t __s0 = __p0; \
	42596	float16_t __s1 = __p1; \
	42597	float16x8_t __ret; \
	42598	__ret = __s0 * (float16x8_t) {__s1, __s1, __s1, __s1, __s1, __s1, __s1, __s1}; \
	42599	__ret; \
	42600	})
	42601	#else
	42602	#define vmulq_n_f16(__p0, __p1) __extension__ ({ \
	42603	float16x8_t __s0 = __p0; \
	42604	float16_t __s1 = __p1; \
	42605	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42606	float16x8_t __ret; \
	42607	__ret = __rev0 * (float16x8_t) {__s1, __s1, __s1, __s1, __s1, __s1, __s1, __s1}; \
	42608	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42609	__ret; \
	42610	})
	42611	#endif
	42612
	42613	#ifdef __LITTLE_ENDIAN__
	42614	#define vmul_n_f16(__p0, __p1) __extension__ ({ \
	42615	float16x4_t __s0 = __p0; \
	42616	float16_t __s1 = __p1; \
	42617	float16x4_t __ret; \
	42618	__ret = __s0 * (float16x4_t) {__s1, __s1, __s1, __s1}; \
	42619	__ret; \
	42620	})
	42621	#else
	42622	#define vmul_n_f16(__p0, __p1) __extension__ ({ \
	42623	float16x4_t __s0 = __p0; \
	42624	float16_t __s1 = __p1; \
	42625	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42626	float16x4_t __ret; \
	42627	__ret = __rev0 * (float16x4_t) {__s1, __s1, __s1, __s1}; \
	42628	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42629	__ret; \
	42630	})
	42631	#endif
	42632
	42633	#ifdef __LITTLE_ENDIAN__
	42634	__ai float16x8_t vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42635	float16x8_t __ret;
	42636	__ret = (float16x8_t) __builtin_neon_vmulxq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42637	return __ret;
	42638	}
	42639	#else
	42640	__ai float16x8_t vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42641	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42642	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42643	float16x8_t __ret;
	42644	__ret = (float16x8_t) __builtin_neon_vmulxq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42645	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42646	return __ret;
	42647	}
	42648	__ai float16x8_t __noswap_vmulxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42649	float16x8_t __ret;
	42650	__ret = (float16x8_t) __builtin_neon_vmulxq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42651	return __ret;
	42652	}
	42653	#endif
	42654
	42655	#ifdef __LITTLE_ENDIAN__
	42656	__ai float16x4_t vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
	42657	float16x4_t __ret;
	42658	__ret = (float16x4_t) __builtin_neon_vmulx_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42659	return __ret;
	42660	}
	42661	#else
	42662	__ai float16x4_t vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
	42663	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42664	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42665	float16x4_t __ret;
	42666	__ret = (float16x4_t) __builtin_neon_vmulx_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42667	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42668	return __ret;
	42669	}
	42670	__ai float16x4_t __noswap_vmulx_f16(float16x4_t __p0, float16x4_t __p1) {
	42671	float16x4_t __ret;
	42672	__ret = (float16x4_t) __builtin_neon_vmulx_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42673	return __ret;
	42674	}
	42675	#endif
	42676
	42677	#ifdef __LITTLE_ENDIAN__
	42678	#define vmulxq_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42679	float16x8_t __s0 = __p0; \
	42680	float16x4_t __s1 = __p1; \
	42681	float16x8_t __ret; \
	42682	__ret = vmulxq_f16(__s0, __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2)); \
	42683	__ret; \
	42684	})
	42685	#else
	42686	#define vmulxq_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42687	float16x8_t __s0 = __p0; \
	42688	float16x4_t __s1 = __p1; \
	42689	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42690	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	42691	float16x8_t __ret; \
	42692	__ret = __noswap_vmulxq_f16(__rev0, __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2)); \
	42693	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42694	__ret; \
	42695	})
	42696	#endif
	42697
	42698	#ifdef __LITTLE_ENDIAN__
	42699	#define vmulx_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42700	float16x4_t __s0 = __p0; \
	42701	float16x4_t __s1 = __p1; \
	42702	float16x4_t __ret; \
	42703	__ret = vmulx_f16(__s0, __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2)); \
	42704	__ret; \
	42705	})
	42706	#else
	42707	#define vmulx_lane_f16(__p0, __p1, __p2) __extension__ ({ \
	42708	float16x4_t __s0 = __p0; \
	42709	float16x4_t __s1 = __p1; \
	42710	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42711	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 3, 2, 1, 0); \
	42712	float16x4_t __ret; \
	42713	__ret = __noswap_vmulx_f16(__rev0, __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2)); \
	42714	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42715	__ret; \
	42716	})
	42717	#endif
	42718
	42719	#ifdef __LITTLE_ENDIAN__
	42720	#define vmulxq_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42721	float16x8_t __s0 = __p0; \
	42722	float16x8_t __s1 = __p1; \
	42723	float16x8_t __ret; \
	42724	__ret = vmulxq_f16(__s0, __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2)); \
	42725	__ret; \
	42726	})
	42727	#else
	42728	#define vmulxq_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42729	float16x8_t __s0 = __p0; \
	42730	float16x8_t __s1 = __p1; \
	42731	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42732	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	42733	float16x8_t __ret; \
	42734	__ret = __noswap_vmulxq_f16(__rev0, __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2, __p2, __p2, __p2, __p2)); \
	42735	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42736	__ret; \
	42737	})
	42738	#endif
	42739
	42740	#ifdef __LITTLE_ENDIAN__
	42741	#define vmulx_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42742	float16x4_t __s0 = __p0; \
	42743	float16x8_t __s1 = __p1; \
	42744	float16x4_t __ret; \
	42745	__ret = vmulx_f16(__s0, __builtin_shufflevector(__s1, __s1, __p2, __p2, __p2, __p2)); \
	42746	__ret; \
	42747	})
	42748	#else
	42749	#define vmulx_laneq_f16(__p0, __p1, __p2) __extension__ ({ \
	42750	float16x4_t __s0 = __p0; \
	42751	float16x8_t __s1 = __p1; \
	42752	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42753	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__s1, __s1, 7, 6, 5, 4, 3, 2, 1, 0); \
	42754	float16x4_t __ret; \
	42755	__ret = __noswap_vmulx_f16(__rev0, __builtin_shufflevector(__rev1, __rev1, __p2, __p2, __p2, __p2)); \
	42756	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42757	__ret; \
	42758	})
	42759	#endif
	42760
	42761	#ifdef __LITTLE_ENDIAN__
	42762	#define vmulxq_n_f16(__p0, __p1) __extension__ ({ \
	42763	float16x8_t __s0 = __p0; \
	42764	float16_t __s1 = __p1; \
	42765	float16x8_t __ret; \
	42766	__ret = vmulxq_f16(__s0, (float16x8_t) {__s1, __s1, __s1, __s1, __s1, __s1, __s1, __s1}); \
	42767	__ret; \
	42768	})
	42769	#else
	42770	#define vmulxq_n_f16(__p0, __p1) __extension__ ({ \
	42771	float16x8_t __s0 = __p0; \
	42772	float16_t __s1 = __p1; \
	42773	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 7, 6, 5, 4, 3, 2, 1, 0); \
	42774	float16x8_t __ret; \
	42775	__ret = __noswap_vmulxq_f16(__rev0, (float16x8_t) {__s1, __s1, __s1, __s1, __s1, __s1, __s1, __s1}); \
	42776	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0); \
	42777	__ret; \
	42778	})
	42779	#endif
	42780
	42781	#ifdef __LITTLE_ENDIAN__
	42782	#define vmulx_n_f16(__p0, __p1) __extension__ ({ \
	42783	float16x4_t __s0 = __p0; \
	42784	float16_t __s1 = __p1; \
	42785	float16x4_t __ret; \
	42786	__ret = vmulx_f16(__s0, (float16x4_t) {__s1, __s1, __s1, __s1}); \
	42787	__ret; \
	42788	})
	42789	#else
	42790	#define vmulx_n_f16(__p0, __p1) __extension__ ({ \
	42791	float16x4_t __s0 = __p0; \
	42792	float16_t __s1 = __p1; \
	42793	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__s0, __s0, 3, 2, 1, 0); \
	42794	float16x4_t __ret; \
	42795	__ret = __noswap_vmulx_f16(__rev0, (float16x4_t) {__s1, __s1, __s1, __s1}); \
	42796	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0); \
	42797	__ret; \
	42798	})
	42799	#endif
	42800
	42801	#ifdef __LITTLE_ENDIAN__
	42802	__ai float16x8_t vnegq_f16(float16x8_t __p0) {
	42803	float16x8_t __ret;
	42804	__ret = -__p0;
	42805	return __ret;
	42806	}
	42807	#else
	42808	__ai float16x8_t vnegq_f16(float16x8_t __p0) {
	42809	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42810	float16x8_t __ret;
	42811	__ret = -__rev0;
	42812	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42813	return __ret;
	42814	}
	42815	#endif
	42816
	42817	#ifdef __LITTLE_ENDIAN__
	42818	__ai float16x4_t vneg_f16(float16x4_t __p0) {
	42819	float16x4_t __ret;
	42820	__ret = -__p0;
	42821	return __ret;
	42822	}
	42823	#else
	42824	__ai float16x4_t vneg_f16(float16x4_t __p0) {
	42825	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42826	float16x4_t __ret;
	42827	__ret = -__rev0;
	42828	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42829	return __ret;
	42830	}
	42831	#endif
	42832
	42833	#ifdef __LITTLE_ENDIAN__
	42834	__ai float16x8_t vpaddq_f16(float16x8_t __p0, float16x8_t __p1) {
	42835	float16x8_t __ret;
	42836	__ret = (float16x8_t) __builtin_neon_vpaddq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42837	return __ret;
	42838	}
	42839	#else
	42840	__ai float16x8_t vpaddq_f16(float16x8_t __p0, float16x8_t __p1) {
	42841	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42842	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42843	float16x8_t __ret;
	42844	__ret = (float16x8_t) __builtin_neon_vpaddq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42845	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42846	return __ret;
	42847	}
	42848	#endif
	42849
	42850	#ifdef __LITTLE_ENDIAN__
	42851	__ai float16x4_t vpadd_f16(float16x4_t __p0, float16x4_t __p1) {
	42852	float16x4_t __ret;
	42853	__ret = (float16x4_t) __builtin_neon_vpadd_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42854	return __ret;
	42855	}
	42856	#else
	42857	__ai float16x4_t vpadd_f16(float16x4_t __p0, float16x4_t __p1) {
	42858	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42859	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42860	float16x4_t __ret;
	42861	__ret = (float16x4_t) __builtin_neon_vpadd_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42862	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42863	return __ret;
	42864	}
	42865	#endif
	42866
	42867	#ifdef __LITTLE_ENDIAN__
	42868	__ai float16x8_t vpmaxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42869	float16x8_t __ret;
	42870	__ret = (float16x8_t) __builtin_neon_vpmaxq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42871	return __ret;
	42872	}
	42873	#else
	42874	__ai float16x8_t vpmaxq_f16(float16x8_t __p0, float16x8_t __p1) {
	42875	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42876	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42877	float16x8_t __ret;
	42878	__ret = (float16x8_t) __builtin_neon_vpmaxq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42879	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42880	return __ret;
	42881	}
	42882	#endif
	42883
	42884	#ifdef __LITTLE_ENDIAN__
	42885	__ai float16x4_t vpmax_f16(float16x4_t __p0, float16x4_t __p1) {
	42886	float16x4_t __ret;
	42887	__ret = (float16x4_t) __builtin_neon_vpmax_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42888	return __ret;
	42889	}
	42890	#else
	42891	__ai float16x4_t vpmax_f16(float16x4_t __p0, float16x4_t __p1) {
	42892	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42893	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42894	float16x4_t __ret;
	42895	__ret = (float16x4_t) __builtin_neon_vpmax_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42896	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42897	return __ret;
	42898	}
	42899	#endif
	42900
	42901	#ifdef __LITTLE_ENDIAN__
	42902	__ai float16x8_t vpmaxnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42903	float16x8_t __ret;
	42904	__ret = (float16x8_t) __builtin_neon_vpmaxnmq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42905	return __ret;
	42906	}
	42907	#else
	42908	__ai float16x8_t vpmaxnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42909	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42910	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42911	float16x8_t __ret;
	42912	__ret = (float16x8_t) __builtin_neon_vpmaxnmq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42913	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42914	return __ret;
	42915	}
	42916	#endif
	42917
	42918	#ifdef __LITTLE_ENDIAN__
	42919	__ai float16x4_t vpmaxnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42920	float16x4_t __ret;
	42921	__ret = (float16x4_t) __builtin_neon_vpmaxnm_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42922	return __ret;
	42923	}
	42924	#else
	42925	__ai float16x4_t vpmaxnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42926	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42927	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42928	float16x4_t __ret;
	42929	__ret = (float16x4_t) __builtin_neon_vpmaxnm_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42930	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42931	return __ret;
	42932	}
	42933	#endif
	42934
	42935	#ifdef __LITTLE_ENDIAN__
	42936	__ai float16x8_t vpminq_f16(float16x8_t __p0, float16x8_t __p1) {
	42937	float16x8_t __ret;
	42938	__ret = (float16x8_t) __builtin_neon_vpminq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42939	return __ret;
	42940	}
	42941	#else
	42942	__ai float16x8_t vpminq_f16(float16x8_t __p0, float16x8_t __p1) {
	42943	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42944	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42945	float16x8_t __ret;
	42946	__ret = (float16x8_t) __builtin_neon_vpminq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42947	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42948	return __ret;
	42949	}
	42950	#endif
	42951
	42952	#ifdef __LITTLE_ENDIAN__
	42953	__ai float16x4_t vpmin_f16(float16x4_t __p0, float16x4_t __p1) {
	42954	float16x4_t __ret;
	42955	__ret = (float16x4_t) __builtin_neon_vpmin_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42956	return __ret;
	42957	}
	42958	#else
	42959	__ai float16x4_t vpmin_f16(float16x4_t __p0, float16x4_t __p1) {
	42960	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42961	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42962	float16x4_t __ret;
	42963	__ret = (float16x4_t) __builtin_neon_vpmin_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42964	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42965	return __ret;
	42966	}
	42967	#endif
	42968
	42969	#ifdef __LITTLE_ENDIAN__
	42970	__ai float16x8_t vpminnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42971	float16x8_t __ret;
	42972	__ret = (float16x8_t) __builtin_neon_vpminnmq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	42973	return __ret;
	42974	}
	42975	#else
	42976	__ai float16x8_t vpminnmq_f16(float16x8_t __p0, float16x8_t __p1) {
	42977	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	42978	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	42979	float16x8_t __ret;
	42980	__ret = (float16x8_t) __builtin_neon_vpminnmq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	42981	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	42982	return __ret;
	42983	}
	42984	#endif
	42985
	42986	#ifdef __LITTLE_ENDIAN__
	42987	__ai float16x4_t vpminnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42988	float16x4_t __ret;
	42989	__ret = (float16x4_t) __builtin_neon_vpminnm_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	42990	return __ret;
	42991	}
	42992	#else
	42993	__ai float16x4_t vpminnm_f16(float16x4_t __p0, float16x4_t __p1) {
	42994	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	42995	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	42996	float16x4_t __ret;
	42997	__ret = (float16x4_t) __builtin_neon_vpminnm_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	42998	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	42999	return __ret;
	43000	}
	43001	#endif
	43002
	43003	#ifdef __LITTLE_ENDIAN__
	43004	__ai float16x8_t vrecpeq_f16(float16x8_t __p0) {
	43005	float16x8_t __ret;
	43006	__ret = (float16x8_t) __builtin_neon_vrecpeq_v((int8x16_t)__p0, 40);
	43007	return __ret;
	43008	}
	43009	#else
	43010	__ai float16x8_t vrecpeq_f16(float16x8_t __p0) {
	43011	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43012	float16x8_t __ret;
	43013	__ret = (float16x8_t) __builtin_neon_vrecpeq_v((int8x16_t)__rev0, 40);
	43014	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43015	return __ret;
	43016	}
	43017	#endif
	43018
	43019	#ifdef __LITTLE_ENDIAN__
	43020	__ai float16x4_t vrecpe_f16(float16x4_t __p0) {
	43021	float16x4_t __ret;
	43022	__ret = (float16x4_t) __builtin_neon_vrecpe_v((int8x8_t)__p0, 8);
	43023	return __ret;
	43024	}
	43025	#else
	43026	__ai float16x4_t vrecpe_f16(float16x4_t __p0) {
	43027	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43028	float16x4_t __ret;
	43029	__ret = (float16x4_t) __builtin_neon_vrecpe_v((int8x8_t)__rev0, 8);
	43030	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43031	return __ret;
	43032	}
	43033	#endif
	43034
	43035	#ifdef __LITTLE_ENDIAN__
	43036	__ai float16x8_t vrecpsq_f16(float16x8_t __p0, float16x8_t __p1) {
	43037	float16x8_t __ret;
	43038	__ret = (float16x8_t) __builtin_neon_vrecpsq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	43039	return __ret;
	43040	}
	43041	#else
	43042	__ai float16x8_t vrecpsq_f16(float16x8_t __p0, float16x8_t __p1) {
	43043	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43044	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43045	float16x8_t __ret;
	43046	__ret = (float16x8_t) __builtin_neon_vrecpsq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	43047	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43048	return __ret;
	43049	}
	43050	#endif
	43051
	43052	#ifdef __LITTLE_ENDIAN__
	43053	__ai float16x4_t vrecps_f16(float16x4_t __p0, float16x4_t __p1) {
	43054	float16x4_t __ret;
	43055	__ret = (float16x4_t) __builtin_neon_vrecps_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	43056	return __ret;
	43057	}
	43058	#else
	43059	__ai float16x4_t vrecps_f16(float16x4_t __p0, float16x4_t __p1) {
	43060	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43061	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43062	float16x4_t __ret;
	43063	__ret = (float16x4_t) __builtin_neon_vrecps_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	43064	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43065	return __ret;
	43066	}
	43067	#endif
	43068
	43069	#ifdef __LITTLE_ENDIAN__
	43070	__ai float16x8_t vrev64q_f16(float16x8_t __p0) {
	43071	float16x8_t __ret;
	43072	__ret = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0, 7, 6, 5, 4);
	43073	return __ret;
	43074	}
	43075	#else
	43076	__ai float16x8_t vrev64q_f16(float16x8_t __p0) {
	43077	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43078	float16x8_t __ret;
	43079	__ret = __builtin_shufflevector(__rev0, __rev0, 3, 2, 1, 0, 7, 6, 5, 4);
	43080	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43081	return __ret;
	43082	}
	43083	#endif
	43084
	43085	#ifdef __LITTLE_ENDIAN__
	43086	__ai float16x4_t vrev64_f16(float16x4_t __p0) {
	43087	float16x4_t __ret;
	43088	__ret = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43089	return __ret;
	43090	}
	43091	#else
	43092	__ai float16x4_t vrev64_f16(float16x4_t __p0) {
	43093	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43094	float16x4_t __ret;
	43095	__ret = __builtin_shufflevector(__rev0, __rev0, 3, 2, 1, 0);
	43096	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43097	return __ret;
	43098	}
	43099	#endif
	43100
	43101	#ifdef __LITTLE_ENDIAN__
	43102	__ai float16x8_t vrndq_f16(float16x8_t __p0) {
	43103	float16x8_t __ret;
	43104	__ret = (float16x8_t) __builtin_neon_vrndq_v((int8x16_t)__p0, 40);
	43105	return __ret;
	43106	}
	43107	#else
	43108	__ai float16x8_t vrndq_f16(float16x8_t __p0) {
	43109	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43110	float16x8_t __ret;
	43111	__ret = (float16x8_t) __builtin_neon_vrndq_v((int8x16_t)__rev0, 40);
	43112	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43113	return __ret;
	43114	}
	43115	#endif
	43116
	43117	#ifdef __LITTLE_ENDIAN__
	43118	__ai float16x4_t vrnd_f16(float16x4_t __p0) {
	43119	float16x4_t __ret;
	43120	__ret = (float16x4_t) __builtin_neon_vrnd_v((int8x8_t)__p0, 8);
	43121	return __ret;
	43122	}
	43123	#else
	43124	__ai float16x4_t vrnd_f16(float16x4_t __p0) {
	43125	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43126	float16x4_t __ret;
	43127	__ret = (float16x4_t) __builtin_neon_vrnd_v((int8x8_t)__rev0, 8);
	43128	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43129	return __ret;
	43130	}
	43131	#endif
	43132
	43133	#ifdef __LITTLE_ENDIAN__
	43134	__ai float16x8_t vrndaq_f16(float16x8_t __p0) {
	43135	float16x8_t __ret;
	43136	__ret = (float16x8_t) __builtin_neon_vrndaq_v((int8x16_t)__p0, 40);
	43137	return __ret;
	43138	}
	43139	#else
	43140	__ai float16x8_t vrndaq_f16(float16x8_t __p0) {
	43141	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43142	float16x8_t __ret;
	43143	__ret = (float16x8_t) __builtin_neon_vrndaq_v((int8x16_t)__rev0, 40);
	43144	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43145	return __ret;
	43146	}
	43147	#endif
	43148
	43149	#ifdef __LITTLE_ENDIAN__
	43150	__ai float16x4_t vrnda_f16(float16x4_t __p0) {
	43151	float16x4_t __ret;
	43152	__ret = (float16x4_t) __builtin_neon_vrnda_v((int8x8_t)__p0, 8);
	43153	return __ret;
	43154	}
	43155	#else
	43156	__ai float16x4_t vrnda_f16(float16x4_t __p0) {
	43157	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43158	float16x4_t __ret;
	43159	__ret = (float16x4_t) __builtin_neon_vrnda_v((int8x8_t)__rev0, 8);
	43160	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43161	return __ret;
	43162	}
	43163	#endif
	43164
	43165	#ifdef __LITTLE_ENDIAN__
	43166	__ai float16x8_t vrndiq_f16(float16x8_t __p0) {
	43167	float16x8_t __ret;
	43168	__ret = (float16x8_t) __builtin_neon_vrndiq_v((int8x16_t)__p0, 40);
	43169	return __ret;
	43170	}
	43171	#else
	43172	__ai float16x8_t vrndiq_f16(float16x8_t __p0) {
	43173	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43174	float16x8_t __ret;
	43175	__ret = (float16x8_t) __builtin_neon_vrndiq_v((int8x16_t)__rev0, 40);
	43176	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43177	return __ret;
	43178	}
	43179	#endif
	43180
	43181	#ifdef __LITTLE_ENDIAN__
	43182	__ai float16x4_t vrndi_f16(float16x4_t __p0) {
	43183	float16x4_t __ret;
	43184	__ret = (float16x4_t) __builtin_neon_vrndi_v((int8x8_t)__p0, 8);
	43185	return __ret;
	43186	}
	43187	#else
	43188	__ai float16x4_t vrndi_f16(float16x4_t __p0) {
	43189	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43190	float16x4_t __ret;
	43191	__ret = (float16x4_t) __builtin_neon_vrndi_v((int8x8_t)__rev0, 8);
	43192	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43193	return __ret;
	43194	}
	43195	#endif
	43196
	43197	#ifdef __LITTLE_ENDIAN__
	43198	__ai float16x8_t vrndmq_f16(float16x8_t __p0) {
	43199	float16x8_t __ret;
	43200	__ret = (float16x8_t) __builtin_neon_vrndmq_v((int8x16_t)__p0, 40);
	43201	return __ret;
	43202	}
	43203	#else
	43204	__ai float16x8_t vrndmq_f16(float16x8_t __p0) {
	43205	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43206	float16x8_t __ret;
	43207	__ret = (float16x8_t) __builtin_neon_vrndmq_v((int8x16_t)__rev0, 40);
	43208	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43209	return __ret;
	43210	}
	43211	#endif
	43212
	43213	#ifdef __LITTLE_ENDIAN__
	43214	__ai float16x4_t vrndm_f16(float16x4_t __p0) {
	43215	float16x4_t __ret;
	43216	__ret = (float16x4_t) __builtin_neon_vrndm_v((int8x8_t)__p0, 8);
	43217	return __ret;
	43218	}
	43219	#else
	43220	__ai float16x4_t vrndm_f16(float16x4_t __p0) {
	43221	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43222	float16x4_t __ret;
	43223	__ret = (float16x4_t) __builtin_neon_vrndm_v((int8x8_t)__rev0, 8);
	43224	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43225	return __ret;
	43226	}
	43227	#endif
	43228
	43229	#ifdef __LITTLE_ENDIAN__
	43230	__ai float16x8_t vrndnq_f16(float16x8_t __p0) {
	43231	float16x8_t __ret;
	43232	__ret = (float16x8_t) __builtin_neon_vrndnq_v((int8x16_t)__p0, 40);
	43233	return __ret;
	43234	}
	43235	#else
	43236	__ai float16x8_t vrndnq_f16(float16x8_t __p0) {
	43237	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43238	float16x8_t __ret;
	43239	__ret = (float16x8_t) __builtin_neon_vrndnq_v((int8x16_t)__rev0, 40);
	43240	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43241	return __ret;
	43242	}
	43243	#endif
	43244
	43245	#ifdef __LITTLE_ENDIAN__
	43246	__ai float16x4_t vrndn_f16(float16x4_t __p0) {
	43247	float16x4_t __ret;
	43248	__ret = (float16x4_t) __builtin_neon_vrndn_v((int8x8_t)__p0, 8);
	43249	return __ret;
	43250	}
	43251	#else
	43252	__ai float16x4_t vrndn_f16(float16x4_t __p0) {
	43253	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43254	float16x4_t __ret;
	43255	__ret = (float16x4_t) __builtin_neon_vrndn_v((int8x8_t)__rev0, 8);
	43256	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43257	return __ret;
	43258	}
	43259	#endif
	43260
	43261	#ifdef __LITTLE_ENDIAN__
	43262	__ai float16x8_t vrndpq_f16(float16x8_t __p0) {
	43263	float16x8_t __ret;
	43264	__ret = (float16x8_t) __builtin_neon_vrndpq_v((int8x16_t)__p0, 40);
	43265	return __ret;
	43266	}
	43267	#else
	43268	__ai float16x8_t vrndpq_f16(float16x8_t __p0) {
	43269	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43270	float16x8_t __ret;
	43271	__ret = (float16x8_t) __builtin_neon_vrndpq_v((int8x16_t)__rev0, 40);
	43272	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43273	return __ret;
	43274	}
	43275	#endif
	43276
	43277	#ifdef __LITTLE_ENDIAN__
	43278	__ai float16x4_t vrndp_f16(float16x4_t __p0) {
	43279	float16x4_t __ret;
	43280	__ret = (float16x4_t) __builtin_neon_vrndp_v((int8x8_t)__p0, 8);
	43281	return __ret;
	43282	}
	43283	#else
	43284	__ai float16x4_t vrndp_f16(float16x4_t __p0) {
	43285	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43286	float16x4_t __ret;
	43287	__ret = (float16x4_t) __builtin_neon_vrndp_v((int8x8_t)__rev0, 8);
	43288	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43289	return __ret;
	43290	}
	43291	#endif
	43292
	43293	#ifdef __LITTLE_ENDIAN__
	43294	__ai float16x8_t vrndxq_f16(float16x8_t __p0) {
	43295	float16x8_t __ret;
	43296	__ret = (float16x8_t) __builtin_neon_vrndxq_v((int8x16_t)__p0, 40);
	43297	return __ret;
	43298	}
	43299	#else
	43300	__ai float16x8_t vrndxq_f16(float16x8_t __p0) {
	43301	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43302	float16x8_t __ret;
	43303	__ret = (float16x8_t) __builtin_neon_vrndxq_v((int8x16_t)__rev0, 40);
	43304	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43305	return __ret;
	43306	}
	43307	#endif
	43308
	43309	#ifdef __LITTLE_ENDIAN__
	43310	__ai float16x4_t vrndx_f16(float16x4_t __p0) {
	43311	float16x4_t __ret;
	43312	__ret = (float16x4_t) __builtin_neon_vrndx_v((int8x8_t)__p0, 8);
	43313	return __ret;
	43314	}
	43315	#else
	43316	__ai float16x4_t vrndx_f16(float16x4_t __p0) {
	43317	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43318	float16x4_t __ret;
	43319	__ret = (float16x4_t) __builtin_neon_vrndx_v((int8x8_t)__rev0, 8);
	43320	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43321	return __ret;
	43322	}
	43323	#endif
	43324
	43325	#ifdef __LITTLE_ENDIAN__
	43326	__ai float16x8_t vrsqrteq_f16(float16x8_t __p0) {
	43327	float16x8_t __ret;
	43328	__ret = (float16x8_t) __builtin_neon_vrsqrteq_v((int8x16_t)__p0, 40);
	43329	return __ret;
	43330	}
	43331	#else
	43332	__ai float16x8_t vrsqrteq_f16(float16x8_t __p0) {
	43333	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43334	float16x8_t __ret;
	43335	__ret = (float16x8_t) __builtin_neon_vrsqrteq_v((int8x16_t)__rev0, 40);
	43336	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43337	return __ret;
	43338	}
	43339	#endif
	43340
	43341	#ifdef __LITTLE_ENDIAN__
	43342	__ai float16x4_t vrsqrte_f16(float16x4_t __p0) {
	43343	float16x4_t __ret;
	43344	__ret = (float16x4_t) __builtin_neon_vrsqrte_v((int8x8_t)__p0, 8);
	43345	return __ret;
	43346	}
	43347	#else
	43348	__ai float16x4_t vrsqrte_f16(float16x4_t __p0) {
	43349	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43350	float16x4_t __ret;
	43351	__ret = (float16x4_t) __builtin_neon_vrsqrte_v((int8x8_t)__rev0, 8);
	43352	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43353	return __ret;
	43354	}
	43355	#endif
	43356
	43357	#ifdef __LITTLE_ENDIAN__
	43358	__ai float16x8_t vrsqrtsq_f16(float16x8_t __p0, float16x8_t __p1) {
	43359	float16x8_t __ret;
	43360	__ret = (float16x8_t) __builtin_neon_vrsqrtsq_v((int8x16_t)__p0, (int8x16_t)__p1, 40);
	43361	return __ret;
	43362	}
	43363	#else
	43364	__ai float16x8_t vrsqrtsq_f16(float16x8_t __p0, float16x8_t __p1) {
	43365	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43366	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43367	float16x8_t __ret;
	43368	__ret = (float16x8_t) __builtin_neon_vrsqrtsq_v((int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	43369	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43370	return __ret;
	43371	}
	43372	#endif
	43373
	43374	#ifdef __LITTLE_ENDIAN__
	43375	__ai float16x4_t vrsqrts_f16(float16x4_t __p0, float16x4_t __p1) {
	43376	float16x4_t __ret;
	43377	__ret = (float16x4_t) __builtin_neon_vrsqrts_v((int8x8_t)__p0, (int8x8_t)__p1, 8);
	43378	return __ret;
	43379	}
	43380	#else
	43381	__ai float16x4_t vrsqrts_f16(float16x4_t __p0, float16x4_t __p1) {
	43382	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43383	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43384	float16x4_t __ret;
	43385	__ret = (float16x4_t) __builtin_neon_vrsqrts_v((int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	43386	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43387	return __ret;
	43388	}
	43389	#endif
	43390
	43391	#ifdef __LITTLE_ENDIAN__
	43392	__ai float16x8_t vsqrtq_f16(float16x8_t __p0) {
	43393	float16x8_t __ret;
	43394	__ret = (float16x8_t) __builtin_neon_vsqrtq_v((int8x16_t)__p0, 40);
	43395	return __ret;
	43396	}
	43397	#else
	43398	__ai float16x8_t vsqrtq_f16(float16x8_t __p0) {
	43399	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43400	float16x8_t __ret;
	43401	__ret = (float16x8_t) __builtin_neon_vsqrtq_v((int8x16_t)__rev0, 40);
	43402	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43403	return __ret;
	43404	}
	43405	#endif
	43406
	43407	#ifdef __LITTLE_ENDIAN__
	43408	__ai float16x4_t vsqrt_f16(float16x4_t __p0) {
	43409	float16x4_t __ret;
	43410	__ret = (float16x4_t) __builtin_neon_vsqrt_v((int8x8_t)__p0, 8);
	43411	return __ret;
	43412	}
	43413	#else
	43414	__ai float16x4_t vsqrt_f16(float16x4_t __p0) {
	43415	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43416	float16x4_t __ret;
	43417	__ret = (float16x4_t) __builtin_neon_vsqrt_v((int8x8_t)__rev0, 8);
	43418	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43419	return __ret;
	43420	}
	43421	#endif
	43422
	43423	#ifdef __LITTLE_ENDIAN__
	43424	__ai float16x8_t vsubq_f16(float16x8_t __p0, float16x8_t __p1) {
	43425	float16x8_t __ret;
	43426	__ret = __p0 - __p1;
	43427	return __ret;
	43428	}
	43429	#else
	43430	__ai float16x8_t vsubq_f16(float16x8_t __p0, float16x8_t __p1) {
	43431	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43432	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43433	float16x8_t __ret;
	43434	__ret = __rev0 - __rev1;
	43435	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43436	return __ret;
	43437	}
	43438	#endif
	43439
	43440	#ifdef __LITTLE_ENDIAN__
	43441	__ai float16x4_t vsub_f16(float16x4_t __p0, float16x4_t __p1) {
	43442	float16x4_t __ret;
	43443	__ret = __p0 - __p1;
	43444	return __ret;
	43445	}
	43446	#else
	43447	__ai float16x4_t vsub_f16(float16x4_t __p0, float16x4_t __p1) {
	43448	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43449	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43450	float16x4_t __ret;
	43451	__ret = __rev0 - __rev1;
	43452	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43453	return __ret;
	43454	}
	43455	#endif
	43456
	43457	#ifdef __LITTLE_ENDIAN__
	43458	__ai float16x8x2_t vtrnq_f16(float16x8_t __p0, float16x8_t __p1) {
	43459	float16x8x2_t __ret;
	43460	__builtin_neon_vtrnq_v(&__ret, (int8x16_t)__p0, (int8x16_t)__p1, 40);
	43461	return __ret;
	43462	}
	43463	#else
	43464	__ai float16x8x2_t vtrnq_f16(float16x8_t __p0, float16x8_t __p1) {
	43465	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43466	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43467	float16x8x2_t __ret;
	43468	__builtin_neon_vtrnq_v(&__ret, (int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	43469
	43470	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], 7, 6, 5, 4, 3, 2, 1, 0);
	43471	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], 7, 6, 5, 4, 3, 2, 1, 0);
	43472	return __ret;
	43473	}
	43474	#endif
	43475
	43476	#ifdef __LITTLE_ENDIAN__
	43477	__ai float16x4x2_t vtrn_f16(float16x4_t __p0, float16x4_t __p1) {
	43478	float16x4x2_t __ret;
	43479	__builtin_neon_vtrn_v(&__ret, (int8x8_t)__p0, (int8x8_t)__p1, 8);
	43480	return __ret;
	43481	}
	43482	#else
	43483	__ai float16x4x2_t vtrn_f16(float16x4_t __p0, float16x4_t __p1) {
	43484	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43485	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43486	float16x4x2_t __ret;
	43487	__builtin_neon_vtrn_v(&__ret, (int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	43488
	43489	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], 3, 2, 1, 0);
	43490	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], 3, 2, 1, 0);
	43491	return __ret;
	43492	}
	43493	#endif
	43494
	43495	#ifdef __LITTLE_ENDIAN__
	43496	__ai float16x8_t vtrn1q_f16(float16x8_t __p0, float16x8_t __p1) {
	43497	float16x8_t __ret;
	43498	__ret = __builtin_shufflevector(__p0, __p1, 0, 8, 2, 10, 4, 12, 6, 14);
	43499	return __ret;
	43500	}
	43501	#else
	43502	__ai float16x8_t vtrn1q_f16(float16x8_t __p0, float16x8_t __p1) {
	43503	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43504	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43505	float16x8_t __ret;
	43506	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 8, 2, 10, 4, 12, 6, 14);
	43507	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43508	return __ret;
	43509	}
	43510	#endif
	43511
	43512	#ifdef __LITTLE_ENDIAN__
	43513	__ai float16x4_t vtrn1_f16(float16x4_t __p0, float16x4_t __p1) {
	43514	float16x4_t __ret;
	43515	__ret = __builtin_shufflevector(__p0, __p1, 0, 4, 2, 6);
	43516	return __ret;
	43517	}
	43518	#else
	43519	__ai float16x4_t vtrn1_f16(float16x4_t __p0, float16x4_t __p1) {
	43520	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43521	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43522	float16x4_t __ret;
	43523	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 4, 2, 6);
	43524	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43525	return __ret;
	43526	}
	43527	#endif
	43528
	43529	#ifdef __LITTLE_ENDIAN__
	43530	__ai float16x8_t vtrn2q_f16(float16x8_t __p0, float16x8_t __p1) {
	43531	float16x8_t __ret;
	43532	__ret = __builtin_shufflevector(__p0, __p1, 1, 9, 3, 11, 5, 13, 7, 15);
	43533	return __ret;
	43534	}
	43535	#else
	43536	__ai float16x8_t vtrn2q_f16(float16x8_t __p0, float16x8_t __p1) {
	43537	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43538	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43539	float16x8_t __ret;
	43540	__ret = __builtin_shufflevector(__rev0, __rev1, 1, 9, 3, 11, 5, 13, 7, 15);
	43541	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43542	return __ret;
	43543	}
	43544	#endif
	43545
	43546	#ifdef __LITTLE_ENDIAN__
	43547	__ai float16x4_t vtrn2_f16(float16x4_t __p0, float16x4_t __p1) {
	43548	float16x4_t __ret;
	43549	__ret = __builtin_shufflevector(__p0, __p1, 1, 5, 3, 7);
	43550	return __ret;
	43551	}
	43552	#else
	43553	__ai float16x4_t vtrn2_f16(float16x4_t __p0, float16x4_t __p1) {
	43554	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43555	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43556	float16x4_t __ret;
	43557	__ret = __builtin_shufflevector(__rev0, __rev1, 1, 5, 3, 7);
	43558	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43559	return __ret;
	43560	}
	43561	#endif
	43562
	43563	#ifdef __LITTLE_ENDIAN__
	43564	__ai float16x8x2_t vuzpq_f16(float16x8_t __p0, float16x8_t __p1) {
	43565	float16x8x2_t __ret;
	43566	__builtin_neon_vuzpq_v(&__ret, (int8x16_t)__p0, (int8x16_t)__p1, 40);
	43567	return __ret;
	43568	}
	43569	#else
	43570	__ai float16x8x2_t vuzpq_f16(float16x8_t __p0, float16x8_t __p1) {
	43571	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43572	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43573	float16x8x2_t __ret;
	43574	__builtin_neon_vuzpq_v(&__ret, (int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	43575
	43576	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], 7, 6, 5, 4, 3, 2, 1, 0);
	43577	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], 7, 6, 5, 4, 3, 2, 1, 0);
	43578	return __ret;
	43579	}
	43580	#endif
	43581
	43582	#ifdef __LITTLE_ENDIAN__
	43583	__ai float16x4x2_t vuzp_f16(float16x4_t __p0, float16x4_t __p1) {
	43584	float16x4x2_t __ret;
	43585	__builtin_neon_vuzp_v(&__ret, (int8x8_t)__p0, (int8x8_t)__p1, 8);
	43586	return __ret;
	43587	}
	43588	#else
	43589	__ai float16x4x2_t vuzp_f16(float16x4_t __p0, float16x4_t __p1) {
	43590	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43591	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43592	float16x4x2_t __ret;
	43593	__builtin_neon_vuzp_v(&__ret, (int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	43594
	43595	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], 3, 2, 1, 0);
	43596	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], 3, 2, 1, 0);
	43597	return __ret;
	43598	}
	43599	#endif
	43600
	43601	#ifdef __LITTLE_ENDIAN__
	43602	__ai float16x8_t vuzp1q_f16(float16x8_t __p0, float16x8_t __p1) {
	43603	float16x8_t __ret;
	43604	__ret = __builtin_shufflevector(__p0, __p1, 0, 2, 4, 6, 8, 10, 12, 14);
	43605	return __ret;
	43606	}
	43607	#else
	43608	__ai float16x8_t vuzp1q_f16(float16x8_t __p0, float16x8_t __p1) {
	43609	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43610	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43611	float16x8_t __ret;
	43612	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 2, 4, 6, 8, 10, 12, 14);
	43613	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43614	return __ret;
	43615	}
	43616	#endif
	43617
	43618	#ifdef __LITTLE_ENDIAN__
	43619	__ai float16x4_t vuzp1_f16(float16x4_t __p0, float16x4_t __p1) {
	43620	float16x4_t __ret;
	43621	__ret = __builtin_shufflevector(__p0, __p1, 0, 2, 4, 6);
	43622	return __ret;
	43623	}
	43624	#else
	43625	__ai float16x4_t vuzp1_f16(float16x4_t __p0, float16x4_t __p1) {
	43626	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43627	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43628	float16x4_t __ret;
	43629	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 2, 4, 6);
	43630	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43631	return __ret;
	43632	}
	43633	#endif
	43634
	43635	#ifdef __LITTLE_ENDIAN__
	43636	__ai float16x8_t vuzp2q_f16(float16x8_t __p0, float16x8_t __p1) {
	43637	float16x8_t __ret;
	43638	__ret = __builtin_shufflevector(__p0, __p1, 1, 3, 5, 7, 9, 11, 13, 15);
	43639	return __ret;
	43640	}
	43641	#else
	43642	__ai float16x8_t vuzp2q_f16(float16x8_t __p0, float16x8_t __p1) {
	43643	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43644	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43645	float16x8_t __ret;
	43646	__ret = __builtin_shufflevector(__rev0, __rev1, 1, 3, 5, 7, 9, 11, 13, 15);
	43647	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43648	return __ret;
	43649	}
	43650	#endif
	43651
	43652	#ifdef __LITTLE_ENDIAN__
	43653	__ai float16x4_t vuzp2_f16(float16x4_t __p0, float16x4_t __p1) {
	43654	float16x4_t __ret;
	43655	__ret = __builtin_shufflevector(__p0, __p1, 1, 3, 5, 7);
	43656	return __ret;
	43657	}
	43658	#else
	43659	__ai float16x4_t vuzp2_f16(float16x4_t __p0, float16x4_t __p1) {
	43660	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43661	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43662	float16x4_t __ret;
	43663	__ret = __builtin_shufflevector(__rev0, __rev1, 1, 3, 5, 7);
	43664	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43665	return __ret;
	43666	}
	43667	#endif
	43668
	43669	#ifdef __LITTLE_ENDIAN__
	43670	__ai float16x8x2_t vzipq_f16(float16x8_t __p0, float16x8_t __p1) {
	43671	float16x8x2_t __ret;
	43672	__builtin_neon_vzipq_v(&__ret, (int8x16_t)__p0, (int8x16_t)__p1, 40);
	43673	return __ret;
	43674	}
	43675	#else
	43676	__ai float16x8x2_t vzipq_f16(float16x8_t __p0, float16x8_t __p1) {
	43677	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43678	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43679	float16x8x2_t __ret;
	43680	__builtin_neon_vzipq_v(&__ret, (int8x16_t)__rev0, (int8x16_t)__rev1, 40);
	43681
	43682	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], 7, 6, 5, 4, 3, 2, 1, 0);
	43683	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], 7, 6, 5, 4, 3, 2, 1, 0);
	43684	return __ret;
	43685	}
	43686	#endif
	43687
	43688	#ifdef __LITTLE_ENDIAN__
	43689	__ai float16x4x2_t vzip_f16(float16x4_t __p0, float16x4_t __p1) {
	43690	float16x4x2_t __ret;
	43691	__builtin_neon_vzip_v(&__ret, (int8x8_t)__p0, (int8x8_t)__p1, 8);
	43692	return __ret;
	43693	}
	43694	#else
	43695	__ai float16x4x2_t vzip_f16(float16x4_t __p0, float16x4_t __p1) {
	43696	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43697	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43698	float16x4x2_t __ret;
	43699	__builtin_neon_vzip_v(&__ret, (int8x8_t)__rev0, (int8x8_t)__rev1, 8);
	43700
	43701	__ret.val[0] = __builtin_shufflevector(__ret.val[0], __ret.val[0], 3, 2, 1, 0);
	43702	__ret.val[1] = __builtin_shufflevector(__ret.val[1], __ret.val[1], 3, 2, 1, 0);
	43703	return __ret;
	43704	}
	43705	#endif
	43706
	43707	#ifdef __LITTLE_ENDIAN__
	43708	__ai float16x8_t vzip1q_f16(float16x8_t __p0, float16x8_t __p1) {
	43709	float16x8_t __ret;
	43710	__ret = __builtin_shufflevector(__p0, __p1, 0, 8, 1, 9, 2, 10, 3, 11);
	43711	return __ret;
	43712	}
	43713	#else
	43714	__ai float16x8_t vzip1q_f16(float16x8_t __p0, float16x8_t __p1) {
	43715	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43716	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43717	float16x8_t __ret;
	43718	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 8, 1, 9, 2, 10, 3, 11);
	43719	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43720	return __ret;
	43721	}
	43722	#endif
	43723
	43724	#ifdef __LITTLE_ENDIAN__
	43725	__ai float16x4_t vzip1_f16(float16x4_t __p0, float16x4_t __p1) {
	43726	float16x4_t __ret;
	43727	__ret = __builtin_shufflevector(__p0, __p1, 0, 4, 1, 5);
	43728	return __ret;
	43729	}
	43730	#else
	43731	__ai float16x4_t vzip1_f16(float16x4_t __p0, float16x4_t __p1) {
	43732	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43733	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43734	float16x4_t __ret;
	43735	__ret = __builtin_shufflevector(__rev0, __rev1, 0, 4, 1, 5);
	43736	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43737	return __ret;
	43738	}
	43739	#endif
	43740
	43741	#ifdef __LITTLE_ENDIAN__
	43742	__ai float16x8_t vzip2q_f16(float16x8_t __p0, float16x8_t __p1) {
	43743	float16x8_t __ret;
	43744	__ret = __builtin_shufflevector(__p0, __p1, 4, 12, 5, 13, 6, 14, 7, 15);
	43745	return __ret;
	43746	}
	43747	#else
	43748	__ai float16x8_t vzip2q_f16(float16x8_t __p0, float16x8_t __p1) {
	43749	float16x8_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 7, 6, 5, 4, 3, 2, 1, 0);
	43750	float16x8_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 7, 6, 5, 4, 3, 2, 1, 0);
	43751	float16x8_t __ret;
	43752	__ret = __builtin_shufflevector(__rev0, __rev1, 4, 12, 5, 13, 6, 14, 7, 15);
	43753	__ret = __builtin_shufflevector(__ret, __ret, 7, 6, 5, 4, 3, 2, 1, 0);
	43754	return __ret;
	43755	}
	43756	#endif
	43757
	43758	#ifdef __LITTLE_ENDIAN__
	43759	__ai float16x4_t vzip2_f16(float16x4_t __p0, float16x4_t __p1) {
	43760	float16x4_t __ret;
	43761	__ret = __builtin_shufflevector(__p0, __p1, 2, 6, 3, 7);
	43762	return __ret;
	43763	}
	43764	#else
	43765	__ai float16x4_t vzip2_f16(float16x4_t __p0, float16x4_t __p1) {
	43766	float16x4_t __rev0; __rev0 = __builtin_shufflevector(__p0, __p0, 3, 2, 1, 0);
	43767	float16x4_t __rev1; __rev1 = __builtin_shufflevector(__p1, __p1, 3, 2, 1, 0);
	43768	float16x4_t __ret;
	43769	__ret = __builtin_shufflevector(__rev0, __rev1, 2, 6, 3, 7);
	43770	__ret = __builtin_shufflevector(__ret, __ret, 3, 2, 1, 0);
	43771	return __ret;
	43772	}
	43773	#endif
	43774
40463	43775	#endif
40464	43776	#if defined(__ARM_FEATURE_QRDMX)
40465	43777	#ifdef __LITTLE_ENDIAN__
...	...	@@ -44220,917 +47532,917 @@ __ai float64x2_t vcombine_f64(float64x1_t __p0, float64x1_t __p1) {
44220	47532	#endif
44221	47533
44222	47534	#ifdef __LITTLE_ENDIAN__
44223		#define vcopyq_lane_p8(__p0_0, __p1_0, __p2_0, __p3_0) __extension__ ({ \
44224		poly8x16_t __s0_0 = __p0_0; \
44225		poly8x8_t __s2_0 = __p2_0; \
44226		poly8x16_t __ret_0; \
44227		__ret_0 = vsetq_lane_p8(vget_lane_p8(__s2_0, __p3_0), __s0_0, __p1_0); \
44228		__ret_0; \
44229		})
44230		#else
44231		#define vcopyq_lane_p8(__p0_1, __p1_1, __p2_1, __p3_1) __extension__ ({ \
44232		poly8x16_t __s0_1 = __p0_1; \
44233		poly8x8_t __s2_1 = __p2_1; \
44234		poly8x16_t __rev0_1; __rev0_1 = __builtin_shufflevector(__s0_1, __s0_1, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44235		poly8x8_t __rev2_1; __rev2_1 = __builtin_shufflevector(__s2_1, __s2_1, 7, 6, 5, 4, 3, 2, 1, 0); \
44236		poly8x16_t __ret_1; \
44237		__ret_1 = __noswap_vsetq_lane_p8(__noswap_vget_lane_p8(__rev2_1, __p3_1), __rev0_1, __p1_1); \
44238		__ret_1 = __builtin_shufflevector(__ret_1, __ret_1, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44239		__ret_1; \
44240		})
44241		#endif
44242
44243		#ifdef __LITTLE_ENDIAN__
44244		#define vcopyq_lane_p16(__p0_2, __p1_2, __p2_2, __p3_2) __extension__ ({ \
44245		poly16x8_t __s0_2 = __p0_2; \
44246		poly16x4_t __s2_2 = __p2_2; \
44247		poly16x8_t __ret_2; \
44248		__ret_2 = vsetq_lane_p16(vget_lane_p16(__s2_2, __p3_2), __s0_2, __p1_2); \
44249		__ret_2; \
44250		})
44251		#else
44252		#define vcopyq_lane_p16(__p0_3, __p1_3, __p2_3, __p3_3) __extension__ ({ \
44253		poly16x8_t __s0_3 = __p0_3; \
44254		poly16x4_t __s2_3 = __p2_3; \
44255		poly16x8_t __rev0_3; __rev0_3 = __builtin_shufflevector(__s0_3, __s0_3, 7, 6, 5, 4, 3, 2, 1, 0); \
44256		poly16x4_t __rev2_3; __rev2_3 = __builtin_shufflevector(__s2_3, __s2_3, 3, 2, 1, 0); \
44257		poly16x8_t __ret_3; \
44258		__ret_3 = __noswap_vsetq_lane_p16(__noswap_vget_lane_p16(__rev2_3, __p3_3), __rev0_3, __p1_3); \
44259		__ret_3 = __builtin_shufflevector(__ret_3, __ret_3, 7, 6, 5, 4, 3, 2, 1, 0); \
44260		__ret_3; \
44261		})
44262		#endif
44263
44264		#ifdef __LITTLE_ENDIAN__
44265		#define vcopyq_lane_u8(__p0_4, __p1_4, __p2_4, __p3_4) __extension__ ({ \
44266		uint8x16_t __s0_4 = __p0_4; \
44267		uint8x8_t __s2_4 = __p2_4; \
44268		uint8x16_t __ret_4; \
44269		__ret_4 = vsetq_lane_u8(vget_lane_u8(__s2_4, __p3_4), __s0_4, __p1_4); \
44270		__ret_4; \
44271		})
44272		#else
44273		#define vcopyq_lane_u8(__p0_5, __p1_5, __p2_5, __p3_5) __extension__ ({ \
44274		uint8x16_t __s0_5 = __p0_5; \
44275		uint8x8_t __s2_5 = __p2_5; \
44276		uint8x16_t __rev0_5; __rev0_5 = __builtin_shufflevector(__s0_5, __s0_5, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44277		uint8x8_t __rev2_5; __rev2_5 = __builtin_shufflevector(__s2_5, __s2_5, 7, 6, 5, 4, 3, 2, 1, 0); \
44278		uint8x16_t __ret_5; \
44279		__ret_5 = __noswap_vsetq_lane_u8(__noswap_vget_lane_u8(__rev2_5, __p3_5), __rev0_5, __p1_5); \
44280		__ret_5 = __builtin_shufflevector(__ret_5, __ret_5, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44281		__ret_5; \
44282		})
44283		#endif
44284
44285		#ifdef __LITTLE_ENDIAN__
44286		#define vcopyq_lane_u32(__p0_6, __p1_6, __p2_6, __p3_6) __extension__ ({ \
44287		uint32x4_t __s0_6 = __p0_6; \
44288		uint32x2_t __s2_6 = __p2_6; \
44289		uint32x4_t __ret_6; \
44290		__ret_6 = vsetq_lane_u32(vget_lane_u32(__s2_6, __p3_6), __s0_6, __p1_6); \
44291		__ret_6; \
44292		})
44293		#else
44294		#define vcopyq_lane_u32(__p0_7, __p1_7, __p2_7, __p3_7) __extension__ ({ \
44295		uint32x4_t __s0_7 = __p0_7; \
44296		uint32x2_t __s2_7 = __p2_7; \
44297		uint32x4_t __rev0_7; __rev0_7 = __builtin_shufflevector(__s0_7, __s0_7, 3, 2, 1, 0); \
44298		uint32x2_t __rev2_7; __rev2_7 = __builtin_shufflevector(__s2_7, __s2_7, 1, 0); \
44299		uint32x4_t __ret_7; \
44300		__ret_7 = __noswap_vsetq_lane_u32(__noswap_vget_lane_u32(__rev2_7, __p3_7), __rev0_7, __p1_7); \
44301		__ret_7 = __builtin_shufflevector(__ret_7, __ret_7, 3, 2, 1, 0); \
44302		__ret_7; \
44303		})
44304		#endif
44305
44306		#ifdef __LITTLE_ENDIAN__
44307		#define vcopyq_lane_u64(__p0_8, __p1_8, __p2_8, __p3_8) __extension__ ({ \
44308		uint64x2_t __s0_8 = __p0_8; \
44309		uint64x1_t __s2_8 = __p2_8; \
44310		uint64x2_t __ret_8; \
44311		__ret_8 = vsetq_lane_u64(vget_lane_u64(__s2_8, __p3_8), __s0_8, __p1_8); \
44312		__ret_8; \
44313		})
44314		#else
44315		#define vcopyq_lane_u64(__p0_9, __p1_9, __p2_9, __p3_9) __extension__ ({ \
44316		uint64x2_t __s0_9 = __p0_9; \
44317		uint64x1_t __s2_9 = __p2_9; \
44318		uint64x2_t __rev0_9; __rev0_9 = __builtin_shufflevector(__s0_9, __s0_9, 1, 0); \
44319		uint64x2_t __ret_9; \
44320		__ret_9 = __noswap_vsetq_lane_u64(__noswap_vget_lane_u64(__s2_9, __p3_9), __rev0_9, __p1_9); \
44321		__ret_9 = __builtin_shufflevector(__ret_9, __ret_9, 1, 0); \
44322		__ret_9; \
44323		})
44324		#endif
44325
44326		#ifdef __LITTLE_ENDIAN__
44327		#define vcopyq_lane_u16(__p0_10, __p1_10, __p2_10, __p3_10) __extension__ ({ \
44328		uint16x8_t __s0_10 = __p0_10; \
44329		uint16x4_t __s2_10 = __p2_10; \
44330		uint16x8_t __ret_10; \
44331		__ret_10 = vsetq_lane_u16(vget_lane_u16(__s2_10, __p3_10), __s0_10, __p1_10); \
44332		__ret_10; \
44333		})
44334		#else
44335		#define vcopyq_lane_u16(__p0_11, __p1_11, __p2_11, __p3_11) __extension__ ({ \
44336		uint16x8_t __s0_11 = __p0_11; \
44337		uint16x4_t __s2_11 = __p2_11; \
44338		uint16x8_t __rev0_11; __rev0_11 = __builtin_shufflevector(__s0_11, __s0_11, 7, 6, 5, 4, 3, 2, 1, 0); \
44339		uint16x4_t __rev2_11; __rev2_11 = __builtin_shufflevector(__s2_11, __s2_11, 3, 2, 1, 0); \
44340		uint16x8_t __ret_11; \
44341		__ret_11 = __noswap_vsetq_lane_u16(__noswap_vget_lane_u16(__rev2_11, __p3_11), __rev0_11, __p1_11); \
44342		__ret_11 = __builtin_shufflevector(__ret_11, __ret_11, 7, 6, 5, 4, 3, 2, 1, 0); \
44343		__ret_11; \
44344		})
44345		#endif
44346
44347		#ifdef __LITTLE_ENDIAN__
44348		#define vcopyq_lane_s8(__p0_12, __p1_12, __p2_12, __p3_12) __extension__ ({ \
44349		int8x16_t __s0_12 = __p0_12; \
44350		int8x8_t __s2_12 = __p2_12; \
44351		int8x16_t __ret_12; \
44352		__ret_12 = vsetq_lane_s8(vget_lane_s8(__s2_12, __p3_12), __s0_12, __p1_12); \
	47535	#define vcopyq_lane_p8(__p0_12, __p1_12, __p2_12, __p3_12) __extension__ ({ \
	47536	poly8x16_t __s0_12 = __p0_12; \
	47537	poly8x8_t __s2_12 = __p2_12; \
	47538	poly8x16_t __ret_12; \
	47539	__ret_12 = vsetq_lane_p8(vget_lane_p8(__s2_12, __p3_12), __s0_12, __p1_12); \
44353	47540	__ret_12; \
44354	47541	})
44355	47542	#else
44356		#define vcopyq_lane_s8(__p0_13, __p1_13, __p2_13, __p3_13) __extension__ ({ \
44357		int8x16_t __s0_13 = __p0_13; \
44358		int8x8_t __s2_13 = __p2_13; \
44359		int8x16_t __rev0_13; __rev0_13 = __builtin_shufflevector(__s0_13, __s0_13, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44360		int8x8_t __rev2_13; __rev2_13 = __builtin_shufflevector(__s2_13, __s2_13, 7, 6, 5, 4, 3, 2, 1, 0); \
44361		int8x16_t __ret_13; \
44362		__ret_13 = __noswap_vsetq_lane_s8(__noswap_vget_lane_s8(__rev2_13, __p3_13), __rev0_13, __p1_13); \
	47543	#define vcopyq_lane_p8(__p0_13, __p1_13, __p2_13, __p3_13) __extension__ ({ \
	47544	poly8x16_t __s0_13 = __p0_13; \
	47545	poly8x8_t __s2_13 = __p2_13; \
	47546	poly8x16_t __rev0_13; __rev0_13 = __builtin_shufflevector(__s0_13, __s0_13, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	47547	poly8x8_t __rev2_13; __rev2_13 = __builtin_shufflevector(__s2_13, __s2_13, 7, 6, 5, 4, 3, 2, 1, 0); \
	47548	poly8x16_t __ret_13; \
	47549	__ret_13 = __noswap_vsetq_lane_p8(__noswap_vget_lane_p8(__rev2_13, __p3_13), __rev0_13, __p1_13); \
44363	47550	__ret_13 = __builtin_shufflevector(__ret_13, __ret_13, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44364	47551	__ret_13; \
44365	47552	})
44366	47553	#endif
44367	47554
44368	47555	#ifdef __LITTLE_ENDIAN__
44369		#define vcopyq_lane_f32(__p0_14, __p1_14, __p2_14, __p3_14) __extension__ ({ \
44370		float32x4_t __s0_14 = __p0_14; \
44371		float32x2_t __s2_14 = __p2_14; \
44372		float32x4_t __ret_14; \
44373		__ret_14 = vsetq_lane_f32(vget_lane_f32(__s2_14, __p3_14), __s0_14, __p1_14); \
	47556	#define vcopyq_lane_p16(__p0_14, __p1_14, __p2_14, __p3_14) __extension__ ({ \
	47557	poly16x8_t __s0_14 = __p0_14; \
	47558	poly16x4_t __s2_14 = __p2_14; \
	47559	poly16x8_t __ret_14; \
	47560	__ret_14 = vsetq_lane_p16(vget_lane_p16(__s2_14, __p3_14), __s0_14, __p1_14); \
44374	47561	__ret_14; \
44375	47562	})
44376	47563	#else
44377		#define vcopyq_lane_f32(__p0_15, __p1_15, __p2_15, __p3_15) __extension__ ({ \
44378		float32x4_t __s0_15 = __p0_15; \
44379		float32x2_t __s2_15 = __p2_15; \
44380		float32x4_t __rev0_15; __rev0_15 = __builtin_shufflevector(__s0_15, __s0_15, 3, 2, 1, 0); \
44381		float32x2_t __rev2_15; __rev2_15 = __builtin_shufflevector(__s2_15, __s2_15, 1, 0); \
44382		float32x4_t __ret_15; \
44383		__ret_15 = __noswap_vsetq_lane_f32(__noswap_vget_lane_f32(__rev2_15, __p3_15), __rev0_15, __p1_15); \
44384		__ret_15 = __builtin_shufflevector(__ret_15, __ret_15, 3, 2, 1, 0); \
	47564	#define vcopyq_lane_p16(__p0_15, __p1_15, __p2_15, __p3_15) __extension__ ({ \
	47565	poly16x8_t __s0_15 = __p0_15; \
	47566	poly16x4_t __s2_15 = __p2_15; \
	47567	poly16x8_t __rev0_15; __rev0_15 = __builtin_shufflevector(__s0_15, __s0_15, 7, 6, 5, 4, 3, 2, 1, 0); \
	47568	poly16x4_t __rev2_15; __rev2_15 = __builtin_shufflevector(__s2_15, __s2_15, 3, 2, 1, 0); \
	47569	poly16x8_t __ret_15; \
	47570	__ret_15 = __noswap_vsetq_lane_p16(__noswap_vget_lane_p16(__rev2_15, __p3_15), __rev0_15, __p1_15); \
	47571	__ret_15 = __builtin_shufflevector(__ret_15, __ret_15, 7, 6, 5, 4, 3, 2, 1, 0); \
44385	47572	__ret_15; \
44386	47573	})
44387	47574	#endif
44388	47575
44389	47576	#ifdef __LITTLE_ENDIAN__
44390		#define vcopyq_lane_s32(__p0_16, __p1_16, __p2_16, __p3_16) __extension__ ({ \
44391		int32x4_t __s0_16 = __p0_16; \
44392		int32x2_t __s2_16 = __p2_16; \
44393		int32x4_t __ret_16; \
44394		__ret_16 = vsetq_lane_s32(vget_lane_s32(__s2_16, __p3_16), __s0_16, __p1_16); \
	47577	#define vcopyq_lane_u8(__p0_16, __p1_16, __p2_16, __p3_16) __extension__ ({ \
	47578	uint8x16_t __s0_16 = __p0_16; \
	47579	uint8x8_t __s2_16 = __p2_16; \
	47580	uint8x16_t __ret_16; \
	47581	__ret_16 = vsetq_lane_u8(vget_lane_u8(__s2_16, __p3_16), __s0_16, __p1_16); \
44395	47582	__ret_16; \
44396	47583	})
44397	47584	#else
44398		#define vcopyq_lane_s32(__p0_17, __p1_17, __p2_17, __p3_17) __extension__ ({ \
44399		int32x4_t __s0_17 = __p0_17; \
44400		int32x2_t __s2_17 = __p2_17; \
44401		int32x4_t __rev0_17; __rev0_17 = __builtin_shufflevector(__s0_17, __s0_17, 3, 2, 1, 0); \
44402		int32x2_t __rev2_17; __rev2_17 = __builtin_shufflevector(__s2_17, __s2_17, 1, 0); \
44403		int32x4_t __ret_17; \
44404		__ret_17 = __noswap_vsetq_lane_s32(__noswap_vget_lane_s32(__rev2_17, __p3_17), __rev0_17, __p1_17); \
44405		__ret_17 = __builtin_shufflevector(__ret_17, __ret_17, 3, 2, 1, 0); \
	47585	#define vcopyq_lane_u8(__p0_17, __p1_17, __p2_17, __p3_17) __extension__ ({ \
	47586	uint8x16_t __s0_17 = __p0_17; \
	47587	uint8x8_t __s2_17 = __p2_17; \
	47588	uint8x16_t __rev0_17; __rev0_17 = __builtin_shufflevector(__s0_17, __s0_17, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	47589	uint8x8_t __rev2_17; __rev2_17 = __builtin_shufflevector(__s2_17, __s2_17, 7, 6, 5, 4, 3, 2, 1, 0); \
	47590	uint8x16_t __ret_17; \
	47591	__ret_17 = __noswap_vsetq_lane_u8(__noswap_vget_lane_u8(__rev2_17, __p3_17), __rev0_17, __p1_17); \
	47592	__ret_17 = __builtin_shufflevector(__ret_17, __ret_17, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44406	47593	__ret_17; \
44407	47594	})
44408	47595	#endif
44409	47596
44410	47597	#ifdef __LITTLE_ENDIAN__
44411		#define vcopyq_lane_s64(__p0_18, __p1_18, __p2_18, __p3_18) __extension__ ({ \
44412		int64x2_t __s0_18 = __p0_18; \
44413		int64x1_t __s2_18 = __p2_18; \
44414		int64x2_t __ret_18; \
44415		__ret_18 = vsetq_lane_s64(vget_lane_s64(__s2_18, __p3_18), __s0_18, __p1_18); \
	47598	#define vcopyq_lane_u32(__p0_18, __p1_18, __p2_18, __p3_18) __extension__ ({ \
	47599	uint32x4_t __s0_18 = __p0_18; \
	47600	uint32x2_t __s2_18 = __p2_18; \
	47601	uint32x4_t __ret_18; \
	47602	__ret_18 = vsetq_lane_u32(vget_lane_u32(__s2_18, __p3_18), __s0_18, __p1_18); \
44416	47603	__ret_18; \
44417	47604	})
44418	47605	#else
44419		#define vcopyq_lane_s64(__p0_19, __p1_19, __p2_19, __p3_19) __extension__ ({ \
44420		int64x2_t __s0_19 = __p0_19; \
44421		int64x1_t __s2_19 = __p2_19; \
44422		int64x2_t __rev0_19; __rev0_19 = __builtin_shufflevector(__s0_19, __s0_19, 1, 0); \
44423		int64x2_t __ret_19; \
44424		__ret_19 = __noswap_vsetq_lane_s64(__noswap_vget_lane_s64(__s2_19, __p3_19), __rev0_19, __p1_19); \
44425		__ret_19 = __builtin_shufflevector(__ret_19, __ret_19, 1, 0); \
	47606	#define vcopyq_lane_u32(__p0_19, __p1_19, __p2_19, __p3_19) __extension__ ({ \
	47607	uint32x4_t __s0_19 = __p0_19; \
	47608	uint32x2_t __s2_19 = __p2_19; \
	47609	uint32x4_t __rev0_19; __rev0_19 = __builtin_shufflevector(__s0_19, __s0_19, 3, 2, 1, 0); \
	47610	uint32x2_t __rev2_19; __rev2_19 = __builtin_shufflevector(__s2_19, __s2_19, 1, 0); \
	47611	uint32x4_t __ret_19; \
	47612	__ret_19 = __noswap_vsetq_lane_u32(__noswap_vget_lane_u32(__rev2_19, __p3_19), __rev0_19, __p1_19); \
	47613	__ret_19 = __builtin_shufflevector(__ret_19, __ret_19, 3, 2, 1, 0); \
44426	47614	__ret_19; \
44427	47615	})
44428	47616	#endif
44429	47617
44430	47618	#ifdef __LITTLE_ENDIAN__
44431		#define vcopyq_lane_s16(__p0_20, __p1_20, __p2_20, __p3_20) __extension__ ({ \
44432		int16x8_t __s0_20 = __p0_20; \
44433		int16x4_t __s2_20 = __p2_20; \
44434		int16x8_t __ret_20; \
44435		__ret_20 = vsetq_lane_s16(vget_lane_s16(__s2_20, __p3_20), __s0_20, __p1_20); \
	47619	#define vcopyq_lane_u64(__p0_20, __p1_20, __p2_20, __p3_20) __extension__ ({ \
	47620	uint64x2_t __s0_20 = __p0_20; \
	47621	uint64x1_t __s2_20 = __p2_20; \
	47622	uint64x2_t __ret_20; \
	47623	__ret_20 = vsetq_lane_u64(vget_lane_u64(__s2_20, __p3_20), __s0_20, __p1_20); \
44436	47624	__ret_20; \
44437	47625	})
44438	47626	#else
44439		#define vcopyq_lane_s16(__p0_21, __p1_21, __p2_21, __p3_21) __extension__ ({ \
44440		int16x8_t __s0_21 = __p0_21; \
44441		int16x4_t __s2_21 = __p2_21; \
44442		int16x8_t __rev0_21; __rev0_21 = __builtin_shufflevector(__s0_21, __s0_21, 7, 6, 5, 4, 3, 2, 1, 0); \
44443		int16x4_t __rev2_21; __rev2_21 = __builtin_shufflevector(__s2_21, __s2_21, 3, 2, 1, 0); \
44444		int16x8_t __ret_21; \
44445		__ret_21 = __noswap_vsetq_lane_s16(__noswap_vget_lane_s16(__rev2_21, __p3_21), __rev0_21, __p1_21); \
44446		__ret_21 = __builtin_shufflevector(__ret_21, __ret_21, 7, 6, 5, 4, 3, 2, 1, 0); \
	47627	#define vcopyq_lane_u64(__p0_21, __p1_21, __p2_21, __p3_21) __extension__ ({ \
	47628	uint64x2_t __s0_21 = __p0_21; \
	47629	uint64x1_t __s2_21 = __p2_21; \
	47630	uint64x2_t __rev0_21; __rev0_21 = __builtin_shufflevector(__s0_21, __s0_21, 1, 0); \
	47631	uint64x2_t __ret_21; \
	47632	__ret_21 = __noswap_vsetq_lane_u64(__noswap_vget_lane_u64(__s2_21, __p3_21), __rev0_21, __p1_21); \
	47633	__ret_21 = __builtin_shufflevector(__ret_21, __ret_21, 1, 0); \
44447	47634	__ret_21; \
44448	47635	})
44449	47636	#endif
44450	47637
44451	47638	#ifdef __LITTLE_ENDIAN__
44452		#define vcopy_lane_p8(__p0_22, __p1_22, __p2_22, __p3_22) __extension__ ({ \
44453		poly8x8_t __s0_22 = __p0_22; \
44454		poly8x8_t __s2_22 = __p2_22; \
44455		poly8x8_t __ret_22; \
44456		__ret_22 = vset_lane_p8(vget_lane_p8(__s2_22, __p3_22), __s0_22, __p1_22); \
	47639	#define vcopyq_lane_u16(__p0_22, __p1_22, __p2_22, __p3_22) __extension__ ({ \
	47640	uint16x8_t __s0_22 = __p0_22; \
	47641	uint16x4_t __s2_22 = __p2_22; \
	47642	uint16x8_t __ret_22; \
	47643	__ret_22 = vsetq_lane_u16(vget_lane_u16(__s2_22, __p3_22), __s0_22, __p1_22); \
44457	47644	__ret_22; \
44458	47645	})
44459	47646	#else
44460		#define vcopy_lane_p8(__p0_23, __p1_23, __p2_23, __p3_23) __extension__ ({ \
44461		poly8x8_t __s0_23 = __p0_23; \
44462		poly8x8_t __s2_23 = __p2_23; \
44463		poly8x8_t __rev0_23; __rev0_23 = __builtin_shufflevector(__s0_23, __s0_23, 7, 6, 5, 4, 3, 2, 1, 0); \
44464		poly8x8_t __rev2_23; __rev2_23 = __builtin_shufflevector(__s2_23, __s2_23, 7, 6, 5, 4, 3, 2, 1, 0); \
44465		poly8x8_t __ret_23; \
44466		__ret_23 = __noswap_vset_lane_p8(__noswap_vget_lane_p8(__rev2_23, __p3_23), __rev0_23, __p1_23); \
	47647	#define vcopyq_lane_u16(__p0_23, __p1_23, __p2_23, __p3_23) __extension__ ({ \
	47648	uint16x8_t __s0_23 = __p0_23; \
	47649	uint16x4_t __s2_23 = __p2_23; \
	47650	uint16x8_t __rev0_23; __rev0_23 = __builtin_shufflevector(__s0_23, __s0_23, 7, 6, 5, 4, 3, 2, 1, 0); \
	47651	uint16x4_t __rev2_23; __rev2_23 = __builtin_shufflevector(__s2_23, __s2_23, 3, 2, 1, 0); \
	47652	uint16x8_t __ret_23; \
	47653	__ret_23 = __noswap_vsetq_lane_u16(__noswap_vget_lane_u16(__rev2_23, __p3_23), __rev0_23, __p1_23); \
44467	47654	__ret_23 = __builtin_shufflevector(__ret_23, __ret_23, 7, 6, 5, 4, 3, 2, 1, 0); \
44468	47655	__ret_23; \
44469	47656	})
44470	47657	#endif
44471	47658
44472	47659	#ifdef __LITTLE_ENDIAN__
44473		#define vcopy_lane_p16(__p0_24, __p1_24, __p2_24, __p3_24) __extension__ ({ \
44474		poly16x4_t __s0_24 = __p0_24; \
44475		poly16x4_t __s2_24 = __p2_24; \
44476		poly16x4_t __ret_24; \
44477		__ret_24 = vset_lane_p16(vget_lane_p16(__s2_24, __p3_24), __s0_24, __p1_24); \
	47660	#define vcopyq_lane_s8(__p0_24, __p1_24, __p2_24, __p3_24) __extension__ ({ \
	47661	int8x16_t __s0_24 = __p0_24; \
	47662	int8x8_t __s2_24 = __p2_24; \
	47663	int8x16_t __ret_24; \
	47664	__ret_24 = vsetq_lane_s8(vget_lane_s8(__s2_24, __p3_24), __s0_24, __p1_24); \
44478	47665	__ret_24; \
44479	47666	})
44480	47667	#else
44481		#define vcopy_lane_p16(__p0_25, __p1_25, __p2_25, __p3_25) __extension__ ({ \
44482		poly16x4_t __s0_25 = __p0_25; \
44483		poly16x4_t __s2_25 = __p2_25; \
44484		poly16x4_t __rev0_25; __rev0_25 = __builtin_shufflevector(__s0_25, __s0_25, 3, 2, 1, 0); \
44485		poly16x4_t __rev2_25; __rev2_25 = __builtin_shufflevector(__s2_25, __s2_25, 3, 2, 1, 0); \
44486		poly16x4_t __ret_25; \
44487		__ret_25 = __noswap_vset_lane_p16(__noswap_vget_lane_p16(__rev2_25, __p3_25), __rev0_25, __p1_25); \
44488		__ret_25 = __builtin_shufflevector(__ret_25, __ret_25, 3, 2, 1, 0); \
	47668	#define vcopyq_lane_s8(__p0_25, __p1_25, __p2_25, __p3_25) __extension__ ({ \
	47669	int8x16_t __s0_25 = __p0_25; \
	47670	int8x8_t __s2_25 = __p2_25; \
	47671	int8x16_t __rev0_25; __rev0_25 = __builtin_shufflevector(__s0_25, __s0_25, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	47672	int8x8_t __rev2_25; __rev2_25 = __builtin_shufflevector(__s2_25, __s2_25, 7, 6, 5, 4, 3, 2, 1, 0); \
	47673	int8x16_t __ret_25; \
	47674	__ret_25 = __noswap_vsetq_lane_s8(__noswap_vget_lane_s8(__rev2_25, __p3_25), __rev0_25, __p1_25); \
	47675	__ret_25 = __builtin_shufflevector(__ret_25, __ret_25, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44489	47676	__ret_25; \
44490	47677	})
44491	47678	#endif
44492	47679
44493	47680	#ifdef __LITTLE_ENDIAN__
44494		#define vcopy_lane_u8(__p0_26, __p1_26, __p2_26, __p3_26) __extension__ ({ \
44495		uint8x8_t __s0_26 = __p0_26; \
44496		uint8x8_t __s2_26 = __p2_26; \
44497		uint8x8_t __ret_26; \
44498		__ret_26 = vset_lane_u8(vget_lane_u8(__s2_26, __p3_26), __s0_26, __p1_26); \
	47681	#define vcopyq_lane_f32(__p0_26, __p1_26, __p2_26, __p3_26) __extension__ ({ \
	47682	float32x4_t __s0_26 = __p0_26; \
	47683	float32x2_t __s2_26 = __p2_26; \
	47684	float32x4_t __ret_26; \
	47685	__ret_26 = vsetq_lane_f32(vget_lane_f32(__s2_26, __p3_26), __s0_26, __p1_26); \
44499	47686	__ret_26; \
44500	47687	})
44501	47688	#else
44502		#define vcopy_lane_u8(__p0_27, __p1_27, __p2_27, __p3_27) __extension__ ({ \
44503		uint8x8_t __s0_27 = __p0_27; \
44504		uint8x8_t __s2_27 = __p2_27; \
44505		uint8x8_t __rev0_27; __rev0_27 = __builtin_shufflevector(__s0_27, __s0_27, 7, 6, 5, 4, 3, 2, 1, 0); \
44506		uint8x8_t __rev2_27; __rev2_27 = __builtin_shufflevector(__s2_27, __s2_27, 7, 6, 5, 4, 3, 2, 1, 0); \
44507		uint8x8_t __ret_27; \
44508		__ret_27 = __noswap_vset_lane_u8(__noswap_vget_lane_u8(__rev2_27, __p3_27), __rev0_27, __p1_27); \
44509		__ret_27 = __builtin_shufflevector(__ret_27, __ret_27, 7, 6, 5, 4, 3, 2, 1, 0); \
	47689	#define vcopyq_lane_f32(__p0_27, __p1_27, __p2_27, __p3_27) __extension__ ({ \
	47690	float32x4_t __s0_27 = __p0_27; \
	47691	float32x2_t __s2_27 = __p2_27; \
	47692	float32x4_t __rev0_27; __rev0_27 = __builtin_shufflevector(__s0_27, __s0_27, 3, 2, 1, 0); \
	47693	float32x2_t __rev2_27; __rev2_27 = __builtin_shufflevector(__s2_27, __s2_27, 1, 0); \
	47694	float32x4_t __ret_27; \
	47695	__ret_27 = __noswap_vsetq_lane_f32(__noswap_vget_lane_f32(__rev2_27, __p3_27), __rev0_27, __p1_27); \
	47696	__ret_27 = __builtin_shufflevector(__ret_27, __ret_27, 3, 2, 1, 0); \
44510	47697	__ret_27; \
44511	47698	})
44512	47699	#endif
44513	47700
44514	47701	#ifdef __LITTLE_ENDIAN__
44515		#define vcopy_lane_u32(__p0_28, __p1_28, __p2_28, __p3_28) __extension__ ({ \
44516		uint32x2_t __s0_28 = __p0_28; \
44517		uint32x2_t __s2_28 = __p2_28; \
44518		uint32x2_t __ret_28; \
44519		__ret_28 = vset_lane_u32(vget_lane_u32(__s2_28, __p3_28), __s0_28, __p1_28); \
	47702	#define vcopyq_lane_s32(__p0_28, __p1_28, __p2_28, __p3_28) __extension__ ({ \
	47703	int32x4_t __s0_28 = __p0_28; \
	47704	int32x2_t __s2_28 = __p2_28; \
	47705	int32x4_t __ret_28; \
	47706	__ret_28 = vsetq_lane_s32(vget_lane_s32(__s2_28, __p3_28), __s0_28, __p1_28); \
44520	47707	__ret_28; \
44521	47708	})
44522	47709	#else
44523		#define vcopy_lane_u32(__p0_29, __p1_29, __p2_29, __p3_29) __extension__ ({ \
44524		uint32x2_t __s0_29 = __p0_29; \
44525		uint32x2_t __s2_29 = __p2_29; \
44526		uint32x2_t __rev0_29; __rev0_29 = __builtin_shufflevector(__s0_29, __s0_29, 1, 0); \
44527		uint32x2_t __rev2_29; __rev2_29 = __builtin_shufflevector(__s2_29, __s2_29, 1, 0); \
44528		uint32x2_t __ret_29; \
44529		__ret_29 = __noswap_vset_lane_u32(__noswap_vget_lane_u32(__rev2_29, __p3_29), __rev0_29, __p1_29); \
44530		__ret_29 = __builtin_shufflevector(__ret_29, __ret_29, 1, 0); \
	47710	#define vcopyq_lane_s32(__p0_29, __p1_29, __p2_29, __p3_29) __extension__ ({ \
	47711	int32x4_t __s0_29 = __p0_29; \
	47712	int32x2_t __s2_29 = __p2_29; \
	47713	int32x4_t __rev0_29; __rev0_29 = __builtin_shufflevector(__s0_29, __s0_29, 3, 2, 1, 0); \
	47714	int32x2_t __rev2_29; __rev2_29 = __builtin_shufflevector(__s2_29, __s2_29, 1, 0); \
	47715	int32x4_t __ret_29; \
	47716	__ret_29 = __noswap_vsetq_lane_s32(__noswap_vget_lane_s32(__rev2_29, __p3_29), __rev0_29, __p1_29); \
	47717	__ret_29 = __builtin_shufflevector(__ret_29, __ret_29, 3, 2, 1, 0); \
44531	47718	__ret_29; \
44532	47719	})
44533	47720	#endif
44534	47721
44535	47722	#ifdef __LITTLE_ENDIAN__
44536		#define vcopy_lane_u64(__p0_30, __p1_30, __p2_30, __p3_30) __extension__ ({ \
44537		uint64x1_t __s0_30 = __p0_30; \
44538		uint64x1_t __s2_30 = __p2_30; \
44539		uint64x1_t __ret_30; \
44540		__ret_30 = vset_lane_u64(vget_lane_u64(__s2_30, __p3_30), __s0_30, __p1_30); \
	47723	#define vcopyq_lane_s64(__p0_30, __p1_30, __p2_30, __p3_30) __extension__ ({ \
	47724	int64x2_t __s0_30 = __p0_30; \
	47725	int64x1_t __s2_30 = __p2_30; \
	47726	int64x2_t __ret_30; \
	47727	__ret_30 = vsetq_lane_s64(vget_lane_s64(__s2_30, __p3_30), __s0_30, __p1_30); \
44541	47728	__ret_30; \
44542	47729	})
44543	47730	#else
44544		#define vcopy_lane_u64(__p0_31, __p1_31, __p2_31, __p3_31) __extension__ ({ \
44545		uint64x1_t __s0_31 = __p0_31; \
44546		uint64x1_t __s2_31 = __p2_31; \
44547		uint64x1_t __ret_31; \
44548		__ret_31 = __noswap_vset_lane_u64(__noswap_vget_lane_u64(__s2_31, __p3_31), __s0_31, __p1_31); \
	47731	#define vcopyq_lane_s64(__p0_31, __p1_31, __p2_31, __p3_31) __extension__ ({ \
	47732	int64x2_t __s0_31 = __p0_31; \
	47733	int64x1_t __s2_31 = __p2_31; \
	47734	int64x2_t __rev0_31; __rev0_31 = __builtin_shufflevector(__s0_31, __s0_31, 1, 0); \
	47735	int64x2_t __ret_31; \
	47736	__ret_31 = __noswap_vsetq_lane_s64(__noswap_vget_lane_s64(__s2_31, __p3_31), __rev0_31, __p1_31); \
	47737	__ret_31 = __builtin_shufflevector(__ret_31, __ret_31, 1, 0); \
44549	47738	__ret_31; \
44550	47739	})
44551	47740	#endif
44552	47741
44553	47742	#ifdef __LITTLE_ENDIAN__
44554		#define vcopy_lane_u16(__p0_32, __p1_32, __p2_32, __p3_32) __extension__ ({ \
44555		uint16x4_t __s0_32 = __p0_32; \
44556		uint16x4_t __s2_32 = __p2_32; \
44557		uint16x4_t __ret_32; \
44558		__ret_32 = vset_lane_u16(vget_lane_u16(__s2_32, __p3_32), __s0_32, __p1_32); \
	47743	#define vcopyq_lane_s16(__p0_32, __p1_32, __p2_32, __p3_32) __extension__ ({ \
	47744	int16x8_t __s0_32 = __p0_32; \
	47745	int16x4_t __s2_32 = __p2_32; \
	47746	int16x8_t __ret_32; \
	47747	__ret_32 = vsetq_lane_s16(vget_lane_s16(__s2_32, __p3_32), __s0_32, __p1_32); \
44559	47748	__ret_32; \
44560	47749	})
44561	47750	#else
44562		#define vcopy_lane_u16(__p0_33, __p1_33, __p2_33, __p3_33) __extension__ ({ \
44563		uint16x4_t __s0_33 = __p0_33; \
44564		uint16x4_t __s2_33 = __p2_33; \
44565		uint16x4_t __rev0_33; __rev0_33 = __builtin_shufflevector(__s0_33, __s0_33, 3, 2, 1, 0); \
44566		uint16x4_t __rev2_33; __rev2_33 = __builtin_shufflevector(__s2_33, __s2_33, 3, 2, 1, 0); \
44567		uint16x4_t __ret_33; \
44568		__ret_33 = __noswap_vset_lane_u16(__noswap_vget_lane_u16(__rev2_33, __p3_33), __rev0_33, __p1_33); \
44569		__ret_33 = __builtin_shufflevector(__ret_33, __ret_33, 3, 2, 1, 0); \
	47751	#define vcopyq_lane_s16(__p0_33, __p1_33, __p2_33, __p3_33) __extension__ ({ \
	47752	int16x8_t __s0_33 = __p0_33; \
	47753	int16x4_t __s2_33 = __p2_33; \
	47754	int16x8_t __rev0_33; __rev0_33 = __builtin_shufflevector(__s0_33, __s0_33, 7, 6, 5, 4, 3, 2, 1, 0); \
	47755	int16x4_t __rev2_33; __rev2_33 = __builtin_shufflevector(__s2_33, __s2_33, 3, 2, 1, 0); \
	47756	int16x8_t __ret_33; \
	47757	__ret_33 = __noswap_vsetq_lane_s16(__noswap_vget_lane_s16(__rev2_33, __p3_33), __rev0_33, __p1_33); \
	47758	__ret_33 = __builtin_shufflevector(__ret_33, __ret_33, 7, 6, 5, 4, 3, 2, 1, 0); \
44570	47759	__ret_33; \
44571	47760	})
44572	47761	#endif
44573	47762
44574	47763	#ifdef __LITTLE_ENDIAN__
44575		#define vcopy_lane_s8(__p0_34, __p1_34, __p2_34, __p3_34) __extension__ ({ \
44576		int8x8_t __s0_34 = __p0_34; \
44577		int8x8_t __s2_34 = __p2_34; \
44578		int8x8_t __ret_34; \
44579		__ret_34 = vset_lane_s8(vget_lane_s8(__s2_34, __p3_34), __s0_34, __p1_34); \
	47764	#define vcopy_lane_p8(__p0_34, __p1_34, __p2_34, __p3_34) __extension__ ({ \
	47765	poly8x8_t __s0_34 = __p0_34; \
	47766	poly8x8_t __s2_34 = __p2_34; \
	47767	poly8x8_t __ret_34; \
	47768	__ret_34 = vset_lane_p8(vget_lane_p8(__s2_34, __p3_34), __s0_34, __p1_34); \
44580	47769	__ret_34; \
44581	47770	})
44582	47771	#else
44583		#define vcopy_lane_s8(__p0_35, __p1_35, __p2_35, __p3_35) __extension__ ({ \
44584		int8x8_t __s0_35 = __p0_35; \
44585		int8x8_t __s2_35 = __p2_35; \
44586		int8x8_t __rev0_35; __rev0_35 = __builtin_shufflevector(__s0_35, __s0_35, 7, 6, 5, 4, 3, 2, 1, 0); \
44587		int8x8_t __rev2_35; __rev2_35 = __builtin_shufflevector(__s2_35, __s2_35, 7, 6, 5, 4, 3, 2, 1, 0); \
44588		int8x8_t __ret_35; \
44589		__ret_35 = __noswap_vset_lane_s8(__noswap_vget_lane_s8(__rev2_35, __p3_35), __rev0_35, __p1_35); \
	47772	#define vcopy_lane_p8(__p0_35, __p1_35, __p2_35, __p3_35) __extension__ ({ \
	47773	poly8x8_t __s0_35 = __p0_35; \
	47774	poly8x8_t __s2_35 = __p2_35; \
	47775	poly8x8_t __rev0_35; __rev0_35 = __builtin_shufflevector(__s0_35, __s0_35, 7, 6, 5, 4, 3, 2, 1, 0); \
	47776	poly8x8_t __rev2_35; __rev2_35 = __builtin_shufflevector(__s2_35, __s2_35, 7, 6, 5, 4, 3, 2, 1, 0); \
	47777	poly8x8_t __ret_35; \
	47778	__ret_35 = __noswap_vset_lane_p8(__noswap_vget_lane_p8(__rev2_35, __p3_35), __rev0_35, __p1_35); \
44590	47779	__ret_35 = __builtin_shufflevector(__ret_35, __ret_35, 7, 6, 5, 4, 3, 2, 1, 0); \
44591	47780	__ret_35; \
44592	47781	})
44593	47782	#endif
44594	47783
44595	47784	#ifdef __LITTLE_ENDIAN__
44596		#define vcopy_lane_f32(__p0_36, __p1_36, __p2_36, __p3_36) __extension__ ({ \
44597		float32x2_t __s0_36 = __p0_36; \
44598		float32x2_t __s2_36 = __p2_36; \
44599		float32x2_t __ret_36; \
44600		__ret_36 = vset_lane_f32(vget_lane_f32(__s2_36, __p3_36), __s0_36, __p1_36); \
	47785	#define vcopy_lane_p16(__p0_36, __p1_36, __p2_36, __p3_36) __extension__ ({ \
	47786	poly16x4_t __s0_36 = __p0_36; \
	47787	poly16x4_t __s2_36 = __p2_36; \
	47788	poly16x4_t __ret_36; \
	47789	__ret_36 = vset_lane_p16(vget_lane_p16(__s2_36, __p3_36), __s0_36, __p1_36); \
44601	47790	__ret_36; \
44602	47791	})
44603	47792	#else
44604		#define vcopy_lane_f32(__p0_37, __p1_37, __p2_37, __p3_37) __extension__ ({ \
44605		float32x2_t __s0_37 = __p0_37; \
44606		float32x2_t __s2_37 = __p2_37; \
44607		float32x2_t __rev0_37; __rev0_37 = __builtin_shufflevector(__s0_37, __s0_37, 1, 0); \
44608		float32x2_t __rev2_37; __rev2_37 = __builtin_shufflevector(__s2_37, __s2_37, 1, 0); \
44609		float32x2_t __ret_37; \
44610		__ret_37 = __noswap_vset_lane_f32(__noswap_vget_lane_f32(__rev2_37, __p3_37), __rev0_37, __p1_37); \
44611		__ret_37 = __builtin_shufflevector(__ret_37, __ret_37, 1, 0); \
	47793	#define vcopy_lane_p16(__p0_37, __p1_37, __p2_37, __p3_37) __extension__ ({ \
	47794	poly16x4_t __s0_37 = __p0_37; \
	47795	poly16x4_t __s2_37 = __p2_37; \
	47796	poly16x4_t __rev0_37; __rev0_37 = __builtin_shufflevector(__s0_37, __s0_37, 3, 2, 1, 0); \
	47797	poly16x4_t __rev2_37; __rev2_37 = __builtin_shufflevector(__s2_37, __s2_37, 3, 2, 1, 0); \
	47798	poly16x4_t __ret_37; \
	47799	__ret_37 = __noswap_vset_lane_p16(__noswap_vget_lane_p16(__rev2_37, __p3_37), __rev0_37, __p1_37); \
	47800	__ret_37 = __builtin_shufflevector(__ret_37, __ret_37, 3, 2, 1, 0); \
44612	47801	__ret_37; \
44613	47802	})
44614	47803	#endif
44615	47804
44616	47805	#ifdef __LITTLE_ENDIAN__
44617		#define vcopy_lane_s32(__p0_38, __p1_38, __p2_38, __p3_38) __extension__ ({ \
44618		int32x2_t __s0_38 = __p0_38; \
44619		int32x2_t __s2_38 = __p2_38; \
44620		int32x2_t __ret_38; \
44621		__ret_38 = vset_lane_s32(vget_lane_s32(__s2_38, __p3_38), __s0_38, __p1_38); \
	47806	#define vcopy_lane_u8(__p0_38, __p1_38, __p2_38, __p3_38) __extension__ ({ \
	47807	uint8x8_t __s0_38 = __p0_38; \
	47808	uint8x8_t __s2_38 = __p2_38; \
	47809	uint8x8_t __ret_38; \
	47810	__ret_38 = vset_lane_u8(vget_lane_u8(__s2_38, __p3_38), __s0_38, __p1_38); \
44622	47811	__ret_38; \
44623	47812	})
44624	47813	#else
44625		#define vcopy_lane_s32(__p0_39, __p1_39, __p2_39, __p3_39) __extension__ ({ \
44626		int32x2_t __s0_39 = __p0_39; \
44627		int32x2_t __s2_39 = __p2_39; \
44628		int32x2_t __rev0_39; __rev0_39 = __builtin_shufflevector(__s0_39, __s0_39, 1, 0); \
44629		int32x2_t __rev2_39; __rev2_39 = __builtin_shufflevector(__s2_39, __s2_39, 1, 0); \
44630		int32x2_t __ret_39; \
44631		__ret_39 = __noswap_vset_lane_s32(__noswap_vget_lane_s32(__rev2_39, __p3_39), __rev0_39, __p1_39); \
44632		__ret_39 = __builtin_shufflevector(__ret_39, __ret_39, 1, 0); \
	47814	#define vcopy_lane_u8(__p0_39, __p1_39, __p2_39, __p3_39) __extension__ ({ \
	47815	uint8x8_t __s0_39 = __p0_39; \
	47816	uint8x8_t __s2_39 = __p2_39; \
	47817	uint8x8_t __rev0_39; __rev0_39 = __builtin_shufflevector(__s0_39, __s0_39, 7, 6, 5, 4, 3, 2, 1, 0); \
	47818	uint8x8_t __rev2_39; __rev2_39 = __builtin_shufflevector(__s2_39, __s2_39, 7, 6, 5, 4, 3, 2, 1, 0); \
	47819	uint8x8_t __ret_39; \
	47820	__ret_39 = __noswap_vset_lane_u8(__noswap_vget_lane_u8(__rev2_39, __p3_39), __rev0_39, __p1_39); \
	47821	__ret_39 = __builtin_shufflevector(__ret_39, __ret_39, 7, 6, 5, 4, 3, 2, 1, 0); \
44633	47822	__ret_39; \
44634	47823	})
44635	47824	#endif
44636	47825
44637	47826	#ifdef __LITTLE_ENDIAN__
44638		#define vcopy_lane_s64(__p0_40, __p1_40, __p2_40, __p3_40) __extension__ ({ \
44639		int64x1_t __s0_40 = __p0_40; \
44640		int64x1_t __s2_40 = __p2_40; \
44641		int64x1_t __ret_40; \
44642		__ret_40 = vset_lane_s64(vget_lane_s64(__s2_40, __p3_40), __s0_40, __p1_40); \
	47827	#define vcopy_lane_u32(__p0_40, __p1_40, __p2_40, __p3_40) __extension__ ({ \
	47828	uint32x2_t __s0_40 = __p0_40; \
	47829	uint32x2_t __s2_40 = __p2_40; \
	47830	uint32x2_t __ret_40; \
	47831	__ret_40 = vset_lane_u32(vget_lane_u32(__s2_40, __p3_40), __s0_40, __p1_40); \
44643	47832	__ret_40; \
44644	47833	})
44645	47834	#else
44646		#define vcopy_lane_s64(__p0_41, __p1_41, __p2_41, __p3_41) __extension__ ({ \
44647		int64x1_t __s0_41 = __p0_41; \
44648		int64x1_t __s2_41 = __p2_41; \
44649		int64x1_t __ret_41; \
44650		__ret_41 = __noswap_vset_lane_s64(__noswap_vget_lane_s64(__s2_41, __p3_41), __s0_41, __p1_41); \
	47835	#define vcopy_lane_u32(__p0_41, __p1_41, __p2_41, __p3_41) __extension__ ({ \
	47836	uint32x2_t __s0_41 = __p0_41; \
	47837	uint32x2_t __s2_41 = __p2_41; \
	47838	uint32x2_t __rev0_41; __rev0_41 = __builtin_shufflevector(__s0_41, __s0_41, 1, 0); \
	47839	uint32x2_t __rev2_41; __rev2_41 = __builtin_shufflevector(__s2_41, __s2_41, 1, 0); \
	47840	uint32x2_t __ret_41; \
	47841	__ret_41 = __noswap_vset_lane_u32(__noswap_vget_lane_u32(__rev2_41, __p3_41), __rev0_41, __p1_41); \
	47842	__ret_41 = __builtin_shufflevector(__ret_41, __ret_41, 1, 0); \
44651	47843	__ret_41; \
44652	47844	})
44653	47845	#endif
44654	47846
44655	47847	#ifdef __LITTLE_ENDIAN__
44656		#define vcopy_lane_s16(__p0_42, __p1_42, __p2_42, __p3_42) __extension__ ({ \
44657		int16x4_t __s0_42 = __p0_42; \
44658		int16x4_t __s2_42 = __p2_42; \
44659		int16x4_t __ret_42; \
44660		__ret_42 = vset_lane_s16(vget_lane_s16(__s2_42, __p3_42), __s0_42, __p1_42); \
	47848	#define vcopy_lane_u64(__p0_42, __p1_42, __p2_42, __p3_42) __extension__ ({ \
	47849	uint64x1_t __s0_42 = __p0_42; \
	47850	uint64x1_t __s2_42 = __p2_42; \
	47851	uint64x1_t __ret_42; \
	47852	__ret_42 = vset_lane_u64(vget_lane_u64(__s2_42, __p3_42), __s0_42, __p1_42); \
44661	47853	__ret_42; \
44662	47854	})
44663	47855	#else
44664		#define vcopy_lane_s16(__p0_43, __p1_43, __p2_43, __p3_43) __extension__ ({ \
44665		int16x4_t __s0_43 = __p0_43; \
44666		int16x4_t __s2_43 = __p2_43; \
44667		int16x4_t __rev0_43; __rev0_43 = __builtin_shufflevector(__s0_43, __s0_43, 3, 2, 1, 0); \
44668		int16x4_t __rev2_43; __rev2_43 = __builtin_shufflevector(__s2_43, __s2_43, 3, 2, 1, 0); \
44669		int16x4_t __ret_43; \
44670		__ret_43 = __noswap_vset_lane_s16(__noswap_vget_lane_s16(__rev2_43, __p3_43), __rev0_43, __p1_43); \
44671		__ret_43 = __builtin_shufflevector(__ret_43, __ret_43, 3, 2, 1, 0); \
	47856	#define vcopy_lane_u64(__p0_43, __p1_43, __p2_43, __p3_43) __extension__ ({ \
	47857	uint64x1_t __s0_43 = __p0_43; \
	47858	uint64x1_t __s2_43 = __p2_43; \
	47859	uint64x1_t __ret_43; \
	47860	__ret_43 = __noswap_vset_lane_u64(__noswap_vget_lane_u64(__s2_43, __p3_43), __s0_43, __p1_43); \
44672	47861	__ret_43; \
44673	47862	})
44674	47863	#endif
44675	47864
44676	47865	#ifdef __LITTLE_ENDIAN__
44677		#define vcopyq_laneq_p8(__p0_44, __p1_44, __p2_44, __p3_44) __extension__ ({ \
44678		poly8x16_t __s0_44 = __p0_44; \
44679		poly8x16_t __s2_44 = __p2_44; \
44680		poly8x16_t __ret_44; \
44681		__ret_44 = vsetq_lane_p8(vgetq_lane_p8(__s2_44, __p3_44), __s0_44, __p1_44); \
	47866	#define vcopy_lane_u16(__p0_44, __p1_44, __p2_44, __p3_44) __extension__ ({ \
	47867	uint16x4_t __s0_44 = __p0_44; \
	47868	uint16x4_t __s2_44 = __p2_44; \
	47869	uint16x4_t __ret_44; \
	47870	__ret_44 = vset_lane_u16(vget_lane_u16(__s2_44, __p3_44), __s0_44, __p1_44); \
44682	47871	__ret_44; \
44683	47872	})
44684	47873	#else
44685		#define vcopyq_laneq_p8(__p0_45, __p1_45, __p2_45, __p3_45) __extension__ ({ \
44686		poly8x16_t __s0_45 = __p0_45; \
44687		poly8x16_t __s2_45 = __p2_45; \
44688		poly8x16_t __rev0_45; __rev0_45 = __builtin_shufflevector(__s0_45, __s0_45, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44689		poly8x16_t __rev2_45; __rev2_45 = __builtin_shufflevector(__s2_45, __s2_45, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44690		poly8x16_t __ret_45; \
44691		__ret_45 = __noswap_vsetq_lane_p8(__noswap_vgetq_lane_p8(__rev2_45, __p3_45), __rev0_45, __p1_45); \
44692		__ret_45 = __builtin_shufflevector(__ret_45, __ret_45, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	47874	#define vcopy_lane_u16(__p0_45, __p1_45, __p2_45, __p3_45) __extension__ ({ \
	47875	uint16x4_t __s0_45 = __p0_45; \
	47876	uint16x4_t __s2_45 = __p2_45; \
	47877	uint16x4_t __rev0_45; __rev0_45 = __builtin_shufflevector(__s0_45, __s0_45, 3, 2, 1, 0); \
	47878	uint16x4_t __rev2_45; __rev2_45 = __builtin_shufflevector(__s2_45, __s2_45, 3, 2, 1, 0); \
	47879	uint16x4_t __ret_45; \
	47880	__ret_45 = __noswap_vset_lane_u16(__noswap_vget_lane_u16(__rev2_45, __p3_45), __rev0_45, __p1_45); \
	47881	__ret_45 = __builtin_shufflevector(__ret_45, __ret_45, 3, 2, 1, 0); \
44693	47882	__ret_45; \
44694	47883	})
44695	47884	#endif
44696	47885
44697	47886	#ifdef __LITTLE_ENDIAN__
44698		#define vcopyq_laneq_p16(__p0_46, __p1_46, __p2_46, __p3_46) __extension__ ({ \
44699		poly16x8_t __s0_46 = __p0_46; \
44700		poly16x8_t __s2_46 = __p2_46; \
44701		poly16x8_t __ret_46; \
44702		__ret_46 = vsetq_lane_p16(vgetq_lane_p16(__s2_46, __p3_46), __s0_46, __p1_46); \
	47887	#define vcopy_lane_s8(__p0_46, __p1_46, __p2_46, __p3_46) __extension__ ({ \
	47888	int8x8_t __s0_46 = __p0_46; \
	47889	int8x8_t __s2_46 = __p2_46; \
	47890	int8x8_t __ret_46; \
	47891	__ret_46 = vset_lane_s8(vget_lane_s8(__s2_46, __p3_46), __s0_46, __p1_46); \
44703	47892	__ret_46; \
44704	47893	})
44705	47894	#else
44706		#define vcopyq_laneq_p16(__p0_47, __p1_47, __p2_47, __p3_47) __extension__ ({ \
44707		poly16x8_t __s0_47 = __p0_47; \
44708		poly16x8_t __s2_47 = __p2_47; \
44709		poly16x8_t __rev0_47; __rev0_47 = __builtin_shufflevector(__s0_47, __s0_47, 7, 6, 5, 4, 3, 2, 1, 0); \
44710		poly16x8_t __rev2_47; __rev2_47 = __builtin_shufflevector(__s2_47, __s2_47, 7, 6, 5, 4, 3, 2, 1, 0); \
44711		poly16x8_t __ret_47; \
44712		__ret_47 = __noswap_vsetq_lane_p16(__noswap_vgetq_lane_p16(__rev2_47, __p3_47), __rev0_47, __p1_47); \
	47895	#define vcopy_lane_s8(__p0_47, __p1_47, __p2_47, __p3_47) __extension__ ({ \
	47896	int8x8_t __s0_47 = __p0_47; \
	47897	int8x8_t __s2_47 = __p2_47; \
	47898	int8x8_t __rev0_47; __rev0_47 = __builtin_shufflevector(__s0_47, __s0_47, 7, 6, 5, 4, 3, 2, 1, 0); \
	47899	int8x8_t __rev2_47; __rev2_47 = __builtin_shufflevector(__s2_47, __s2_47, 7, 6, 5, 4, 3, 2, 1, 0); \
	47900	int8x8_t __ret_47; \
	47901	__ret_47 = __noswap_vset_lane_s8(__noswap_vget_lane_s8(__rev2_47, __p3_47), __rev0_47, __p1_47); \
44713	47902	__ret_47 = __builtin_shufflevector(__ret_47, __ret_47, 7, 6, 5, 4, 3, 2, 1, 0); \
44714	47903	__ret_47; \
44715	47904	})
44716	47905	#endif
44717	47906
44718	47907	#ifdef __LITTLE_ENDIAN__
44719		#define vcopyq_laneq_u8(__p0_48, __p1_48, __p2_48, __p3_48) __extension__ ({ \
44720		uint8x16_t __s0_48 = __p0_48; \
44721		uint8x16_t __s2_48 = __p2_48; \
44722		uint8x16_t __ret_48; \
44723		__ret_48 = vsetq_lane_u8(vgetq_lane_u8(__s2_48, __p3_48), __s0_48, __p1_48); \
	47908	#define vcopy_lane_f32(__p0_48, __p1_48, __p2_48, __p3_48) __extension__ ({ \
	47909	float32x2_t __s0_48 = __p0_48; \
	47910	float32x2_t __s2_48 = __p2_48; \
	47911	float32x2_t __ret_48; \
	47912	__ret_48 = vset_lane_f32(vget_lane_f32(__s2_48, __p3_48), __s0_48, __p1_48); \
44724	47913	__ret_48; \
44725	47914	})
44726	47915	#else
44727		#define vcopyq_laneq_u8(__p0_49, __p1_49, __p2_49, __p3_49) __extension__ ({ \
44728		uint8x16_t __s0_49 = __p0_49; \
44729		uint8x16_t __s2_49 = __p2_49; \
44730		uint8x16_t __rev0_49; __rev0_49 = __builtin_shufflevector(__s0_49, __s0_49, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44731		uint8x16_t __rev2_49; __rev2_49 = __builtin_shufflevector(__s2_49, __s2_49, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44732		uint8x16_t __ret_49; \
44733		__ret_49 = __noswap_vsetq_lane_u8(__noswap_vgetq_lane_u8(__rev2_49, __p3_49), __rev0_49, __p1_49); \
44734		__ret_49 = __builtin_shufflevector(__ret_49, __ret_49, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	47916	#define vcopy_lane_f32(__p0_49, __p1_49, __p2_49, __p3_49) __extension__ ({ \
	47917	float32x2_t __s0_49 = __p0_49; \
	47918	float32x2_t __s2_49 = __p2_49; \
	47919	float32x2_t __rev0_49; __rev0_49 = __builtin_shufflevector(__s0_49, __s0_49, 1, 0); \
	47920	float32x2_t __rev2_49; __rev2_49 = __builtin_shufflevector(__s2_49, __s2_49, 1, 0); \
	47921	float32x2_t __ret_49; \
	47922	__ret_49 = __noswap_vset_lane_f32(__noswap_vget_lane_f32(__rev2_49, __p3_49), __rev0_49, __p1_49); \
	47923	__ret_49 = __builtin_shufflevector(__ret_49, __ret_49, 1, 0); \
44735	47924	__ret_49; \
44736	47925	})
44737	47926	#endif
44738	47927
44739	47928	#ifdef __LITTLE_ENDIAN__
44740		#define vcopyq_laneq_u32(__p0_50, __p1_50, __p2_50, __p3_50) __extension__ ({ \
44741		uint32x4_t __s0_50 = __p0_50; \
44742		uint32x4_t __s2_50 = __p2_50; \
44743		uint32x4_t __ret_50; \
44744		__ret_50 = vsetq_lane_u32(vgetq_lane_u32(__s2_50, __p3_50), __s0_50, __p1_50); \
	47929	#define vcopy_lane_s32(__p0_50, __p1_50, __p2_50, __p3_50) __extension__ ({ \
	47930	int32x2_t __s0_50 = __p0_50; \
	47931	int32x2_t __s2_50 = __p2_50; \
	47932	int32x2_t __ret_50; \
	47933	__ret_50 = vset_lane_s32(vget_lane_s32(__s2_50, __p3_50), __s0_50, __p1_50); \
44745	47934	__ret_50; \
44746	47935	})
44747	47936	#else
44748		#define vcopyq_laneq_u32(__p0_51, __p1_51, __p2_51, __p3_51) __extension__ ({ \
44749		uint32x4_t __s0_51 = __p0_51; \
44750		uint32x4_t __s2_51 = __p2_51; \
44751		uint32x4_t __rev0_51; __rev0_51 = __builtin_shufflevector(__s0_51, __s0_51, 3, 2, 1, 0); \
44752		uint32x4_t __rev2_51; __rev2_51 = __builtin_shufflevector(__s2_51, __s2_51, 3, 2, 1, 0); \
44753		uint32x4_t __ret_51; \
44754		__ret_51 = __noswap_vsetq_lane_u32(__noswap_vgetq_lane_u32(__rev2_51, __p3_51), __rev0_51, __p1_51); \
44755		__ret_51 = __builtin_shufflevector(__ret_51, __ret_51, 3, 2, 1, 0); \
	47937	#define vcopy_lane_s32(__p0_51, __p1_51, __p2_51, __p3_51) __extension__ ({ \
	47938	int32x2_t __s0_51 = __p0_51; \
	47939	int32x2_t __s2_51 = __p2_51; \
	47940	int32x2_t __rev0_51; __rev0_51 = __builtin_shufflevector(__s0_51, __s0_51, 1, 0); \
	47941	int32x2_t __rev2_51; __rev2_51 = __builtin_shufflevector(__s2_51, __s2_51, 1, 0); \
	47942	int32x2_t __ret_51; \
	47943	__ret_51 = __noswap_vset_lane_s32(__noswap_vget_lane_s32(__rev2_51, __p3_51), __rev0_51, __p1_51); \
	47944	__ret_51 = __builtin_shufflevector(__ret_51, __ret_51, 1, 0); \
44756	47945	__ret_51; \
44757	47946	})
44758	47947	#endif
44759	47948
44760	47949	#ifdef __LITTLE_ENDIAN__
44761		#define vcopyq_laneq_u64(__p0_52, __p1_52, __p2_52, __p3_52) __extension__ ({ \
44762		uint64x2_t __s0_52 = __p0_52; \
44763		uint64x2_t __s2_52 = __p2_52; \
44764		uint64x2_t __ret_52; \
44765		__ret_52 = vsetq_lane_u64(vgetq_lane_u64(__s2_52, __p3_52), __s0_52, __p1_52); \
	47950	#define vcopy_lane_s64(__p0_52, __p1_52, __p2_52, __p3_52) __extension__ ({ \
	47951	int64x1_t __s0_52 = __p0_52; \
	47952	int64x1_t __s2_52 = __p2_52; \
	47953	int64x1_t __ret_52; \
	47954	__ret_52 = vset_lane_s64(vget_lane_s64(__s2_52, __p3_52), __s0_52, __p1_52); \
44766	47955	__ret_52; \
44767	47956	})
44768	47957	#else
44769		#define vcopyq_laneq_u64(__p0_53, __p1_53, __p2_53, __p3_53) __extension__ ({ \
44770		uint64x2_t __s0_53 = __p0_53; \
44771		uint64x2_t __s2_53 = __p2_53; \
44772		uint64x2_t __rev0_53; __rev0_53 = __builtin_shufflevector(__s0_53, __s0_53, 1, 0); \
44773		uint64x2_t __rev2_53; __rev2_53 = __builtin_shufflevector(__s2_53, __s2_53, 1, 0); \
44774		uint64x2_t __ret_53; \
44775		__ret_53 = __noswap_vsetq_lane_u64(__noswap_vgetq_lane_u64(__rev2_53, __p3_53), __rev0_53, __p1_53); \
44776		__ret_53 = __builtin_shufflevector(__ret_53, __ret_53, 1, 0); \
	47958	#define vcopy_lane_s64(__p0_53, __p1_53, __p2_53, __p3_53) __extension__ ({ \
	47959	int64x1_t __s0_53 = __p0_53; \
	47960	int64x1_t __s2_53 = __p2_53; \
	47961	int64x1_t __ret_53; \
	47962	__ret_53 = __noswap_vset_lane_s64(__noswap_vget_lane_s64(__s2_53, __p3_53), __s0_53, __p1_53); \
44777	47963	__ret_53; \
44778	47964	})
44779	47965	#endif
44780	47966
44781	47967	#ifdef __LITTLE_ENDIAN__
44782		#define vcopyq_laneq_u16(__p0_54, __p1_54, __p2_54, __p3_54) __extension__ ({ \
44783		uint16x8_t __s0_54 = __p0_54; \
44784		uint16x8_t __s2_54 = __p2_54; \
44785		uint16x8_t __ret_54; \
44786		__ret_54 = vsetq_lane_u16(vgetq_lane_u16(__s2_54, __p3_54), __s0_54, __p1_54); \
	47968	#define vcopy_lane_s16(__p0_54, __p1_54, __p2_54, __p3_54) __extension__ ({ \
	47969	int16x4_t __s0_54 = __p0_54; \
	47970	int16x4_t __s2_54 = __p2_54; \
	47971	int16x4_t __ret_54; \
	47972	__ret_54 = vset_lane_s16(vget_lane_s16(__s2_54, __p3_54), __s0_54, __p1_54); \
44787	47973	__ret_54; \
44788	47974	})
44789	47975	#else
44790		#define vcopyq_laneq_u16(__p0_55, __p1_55, __p2_55, __p3_55) __extension__ ({ \
44791		uint16x8_t __s0_55 = __p0_55; \
44792		uint16x8_t __s2_55 = __p2_55; \
44793		uint16x8_t __rev0_55; __rev0_55 = __builtin_shufflevector(__s0_55, __s0_55, 7, 6, 5, 4, 3, 2, 1, 0); \
44794		uint16x8_t __rev2_55; __rev2_55 = __builtin_shufflevector(__s2_55, __s2_55, 7, 6, 5, 4, 3, 2, 1, 0); \
44795		uint16x8_t __ret_55; \
44796		__ret_55 = __noswap_vsetq_lane_u16(__noswap_vgetq_lane_u16(__rev2_55, __p3_55), __rev0_55, __p1_55); \
44797		__ret_55 = __builtin_shufflevector(__ret_55, __ret_55, 7, 6, 5, 4, 3, 2, 1, 0); \
	47976	#define vcopy_lane_s16(__p0_55, __p1_55, __p2_55, __p3_55) __extension__ ({ \
	47977	int16x4_t __s0_55 = __p0_55; \
	47978	int16x4_t __s2_55 = __p2_55; \
	47979	int16x4_t __rev0_55; __rev0_55 = __builtin_shufflevector(__s0_55, __s0_55, 3, 2, 1, 0); \
	47980	int16x4_t __rev2_55; __rev2_55 = __builtin_shufflevector(__s2_55, __s2_55, 3, 2, 1, 0); \
	47981	int16x4_t __ret_55; \
	47982	__ret_55 = __noswap_vset_lane_s16(__noswap_vget_lane_s16(__rev2_55, __p3_55), __rev0_55, __p1_55); \
	47983	__ret_55 = __builtin_shufflevector(__ret_55, __ret_55, 3, 2, 1, 0); \
44798	47984	__ret_55; \
44799	47985	})
44800	47986	#endif
44801	47987
44802	47988	#ifdef __LITTLE_ENDIAN__
44803		#define vcopyq_laneq_s8(__p0_56, __p1_56, __p2_56, __p3_56) __extension__ ({ \
44804		int8x16_t __s0_56 = __p0_56; \
44805		int8x16_t __s2_56 = __p2_56; \
44806		int8x16_t __ret_56; \
44807		__ret_56 = vsetq_lane_s8(vgetq_lane_s8(__s2_56, __p3_56), __s0_56, __p1_56); \
	47989	#define vcopyq_laneq_p8(__p0_56, __p1_56, __p2_56, __p3_56) __extension__ ({ \
	47990	poly8x16_t __s0_56 = __p0_56; \
	47991	poly8x16_t __s2_56 = __p2_56; \
	47992	poly8x16_t __ret_56; \
	47993	__ret_56 = vsetq_lane_p8(vgetq_lane_p8(__s2_56, __p3_56), __s0_56, __p1_56); \
44808	47994	__ret_56; \
44809	47995	})
44810	47996	#else
44811		#define vcopyq_laneq_s8(__p0_57, __p1_57, __p2_57, __p3_57) __extension__ ({ \
44812		int8x16_t __s0_57 = __p0_57; \
44813		int8x16_t __s2_57 = __p2_57; \
44814		int8x16_t __rev0_57; __rev0_57 = __builtin_shufflevector(__s0_57, __s0_57, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44815		int8x16_t __rev2_57; __rev2_57 = __builtin_shufflevector(__s2_57, __s2_57, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44816		int8x16_t __ret_57; \
44817		__ret_57 = __noswap_vsetq_lane_s8(__noswap_vgetq_lane_s8(__rev2_57, __p3_57), __rev0_57, __p1_57); \
	47997	#define vcopyq_laneq_p8(__p0_57, __p1_57, __p2_57, __p3_57) __extension__ ({ \
	47998	poly8x16_t __s0_57 = __p0_57; \
	47999	poly8x16_t __s2_57 = __p2_57; \
	48000	poly8x16_t __rev0_57; __rev0_57 = __builtin_shufflevector(__s0_57, __s0_57, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48001	poly8x16_t __rev2_57; __rev2_57 = __builtin_shufflevector(__s2_57, __s2_57, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48002	poly8x16_t __ret_57; \
	48003	__ret_57 = __noswap_vsetq_lane_p8(__noswap_vgetq_lane_p8(__rev2_57, __p3_57), __rev0_57, __p1_57); \
44818	48004	__ret_57 = __builtin_shufflevector(__ret_57, __ret_57, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44819	48005	__ret_57; \
44820	48006	})
44821	48007	#endif
44822	48008
44823	48009	#ifdef __LITTLE_ENDIAN__
44824		#define vcopyq_laneq_f32(__p0_58, __p1_58, __p2_58, __p3_58) __extension__ ({ \
44825		float32x4_t __s0_58 = __p0_58; \
44826		float32x4_t __s2_58 = __p2_58; \
44827		float32x4_t __ret_58; \
44828		__ret_58 = vsetq_lane_f32(vgetq_lane_f32(__s2_58, __p3_58), __s0_58, __p1_58); \
	48010	#define vcopyq_laneq_p16(__p0_58, __p1_58, __p2_58, __p3_58) __extension__ ({ \
	48011	poly16x8_t __s0_58 = __p0_58; \
	48012	poly16x8_t __s2_58 = __p2_58; \
	48013	poly16x8_t __ret_58; \
	48014	__ret_58 = vsetq_lane_p16(vgetq_lane_p16(__s2_58, __p3_58), __s0_58, __p1_58); \
44829	48015	__ret_58; \
44830	48016	})
44831	48017	#else
44832		#define vcopyq_laneq_f32(__p0_59, __p1_59, __p2_59, __p3_59) __extension__ ({ \
44833		float32x4_t __s0_59 = __p0_59; \
44834		float32x4_t __s2_59 = __p2_59; \
44835		float32x4_t __rev0_59; __rev0_59 = __builtin_shufflevector(__s0_59, __s0_59, 3, 2, 1, 0); \
44836		float32x4_t __rev2_59; __rev2_59 = __builtin_shufflevector(__s2_59, __s2_59, 3, 2, 1, 0); \
44837		float32x4_t __ret_59; \
44838		__ret_59 = __noswap_vsetq_lane_f32(__noswap_vgetq_lane_f32(__rev2_59, __p3_59), __rev0_59, __p1_59); \
44839		__ret_59 = __builtin_shufflevector(__ret_59, __ret_59, 3, 2, 1, 0); \
	48018	#define vcopyq_laneq_p16(__p0_59, __p1_59, __p2_59, __p3_59) __extension__ ({ \
	48019	poly16x8_t __s0_59 = __p0_59; \
	48020	poly16x8_t __s2_59 = __p2_59; \
	48021	poly16x8_t __rev0_59; __rev0_59 = __builtin_shufflevector(__s0_59, __s0_59, 7, 6, 5, 4, 3, 2, 1, 0); \
	48022	poly16x8_t __rev2_59; __rev2_59 = __builtin_shufflevector(__s2_59, __s2_59, 7, 6, 5, 4, 3, 2, 1, 0); \
	48023	poly16x8_t __ret_59; \
	48024	__ret_59 = __noswap_vsetq_lane_p16(__noswap_vgetq_lane_p16(__rev2_59, __p3_59), __rev0_59, __p1_59); \
	48025	__ret_59 = __builtin_shufflevector(__ret_59, __ret_59, 7, 6, 5, 4, 3, 2, 1, 0); \
44840	48026	__ret_59; \
44841	48027	})
44842	48028	#endif
44843	48029
44844	48030	#ifdef __LITTLE_ENDIAN__
44845		#define vcopyq_laneq_s32(__p0_60, __p1_60, __p2_60, __p3_60) __extension__ ({ \
44846		int32x4_t __s0_60 = __p0_60; \
44847		int32x4_t __s2_60 = __p2_60; \
44848		int32x4_t __ret_60; \
44849		__ret_60 = vsetq_lane_s32(vgetq_lane_s32(__s2_60, __p3_60), __s0_60, __p1_60); \
	48031	#define vcopyq_laneq_u8(__p0_60, __p1_60, __p2_60, __p3_60) __extension__ ({ \
	48032	uint8x16_t __s0_60 = __p0_60; \
	48033	uint8x16_t __s2_60 = __p2_60; \
	48034	uint8x16_t __ret_60; \
	48035	__ret_60 = vsetq_lane_u8(vgetq_lane_u8(__s2_60, __p3_60), __s0_60, __p1_60); \
44850	48036	__ret_60; \
44851	48037	})
44852	48038	#else
44853		#define vcopyq_laneq_s32(__p0_61, __p1_61, __p2_61, __p3_61) __extension__ ({ \
44854		int32x4_t __s0_61 = __p0_61; \
44855		int32x4_t __s2_61 = __p2_61; \
44856		int32x4_t __rev0_61; __rev0_61 = __builtin_shufflevector(__s0_61, __s0_61, 3, 2, 1, 0); \
44857		int32x4_t __rev2_61; __rev2_61 = __builtin_shufflevector(__s2_61, __s2_61, 3, 2, 1, 0); \
44858		int32x4_t __ret_61; \
44859		__ret_61 = __noswap_vsetq_lane_s32(__noswap_vgetq_lane_s32(__rev2_61, __p3_61), __rev0_61, __p1_61); \
44860		__ret_61 = __builtin_shufflevector(__ret_61, __ret_61, 3, 2, 1, 0); \
	48039	#define vcopyq_laneq_u8(__p0_61, __p1_61, __p2_61, __p3_61) __extension__ ({ \
	48040	uint8x16_t __s0_61 = __p0_61; \
	48041	uint8x16_t __s2_61 = __p2_61; \
	48042	uint8x16_t __rev0_61; __rev0_61 = __builtin_shufflevector(__s0_61, __s0_61, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48043	uint8x16_t __rev2_61; __rev2_61 = __builtin_shufflevector(__s2_61, __s2_61, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48044	uint8x16_t __ret_61; \
	48045	__ret_61 = __noswap_vsetq_lane_u8(__noswap_vgetq_lane_u8(__rev2_61, __p3_61), __rev0_61, __p1_61); \
	48046	__ret_61 = __builtin_shufflevector(__ret_61, __ret_61, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44861	48047	__ret_61; \
44862	48048	})
44863	48049	#endif
44864	48050
44865	48051	#ifdef __LITTLE_ENDIAN__
44866		#define vcopyq_laneq_s64(__p0_62, __p1_62, __p2_62, __p3_62) __extension__ ({ \
44867		int64x2_t __s0_62 = __p0_62; \
44868		int64x2_t __s2_62 = __p2_62; \
44869		int64x2_t __ret_62; \
44870		__ret_62 = vsetq_lane_s64(vgetq_lane_s64(__s2_62, __p3_62), __s0_62, __p1_62); \
	48052	#define vcopyq_laneq_u32(__p0_62, __p1_62, __p2_62, __p3_62) __extension__ ({ \
	48053	uint32x4_t __s0_62 = __p0_62; \
	48054	uint32x4_t __s2_62 = __p2_62; \
	48055	uint32x4_t __ret_62; \
	48056	__ret_62 = vsetq_lane_u32(vgetq_lane_u32(__s2_62, __p3_62), __s0_62, __p1_62); \
44871	48057	__ret_62; \
44872	48058	})
44873	48059	#else
44874		#define vcopyq_laneq_s64(__p0_63, __p1_63, __p2_63, __p3_63) __extension__ ({ \
44875		int64x2_t __s0_63 = __p0_63; \
44876		int64x2_t __s2_63 = __p2_63; \
44877		int64x2_t __rev0_63; __rev0_63 = __builtin_shufflevector(__s0_63, __s0_63, 1, 0); \
44878		int64x2_t __rev2_63; __rev2_63 = __builtin_shufflevector(__s2_63, __s2_63, 1, 0); \
44879		int64x2_t __ret_63; \
44880		__ret_63 = __noswap_vsetq_lane_s64(__noswap_vgetq_lane_s64(__rev2_63, __p3_63), __rev0_63, __p1_63); \
44881		__ret_63 = __builtin_shufflevector(__ret_63, __ret_63, 1, 0); \
	48060	#define vcopyq_laneq_u32(__p0_63, __p1_63, __p2_63, __p3_63) __extension__ ({ \
	48061	uint32x4_t __s0_63 = __p0_63; \
	48062	uint32x4_t __s2_63 = __p2_63; \
	48063	uint32x4_t __rev0_63; __rev0_63 = __builtin_shufflevector(__s0_63, __s0_63, 3, 2, 1, 0); \
	48064	uint32x4_t __rev2_63; __rev2_63 = __builtin_shufflevector(__s2_63, __s2_63, 3, 2, 1, 0); \
	48065	uint32x4_t __ret_63; \
	48066	__ret_63 = __noswap_vsetq_lane_u32(__noswap_vgetq_lane_u32(__rev2_63, __p3_63), __rev0_63, __p1_63); \
	48067	__ret_63 = __builtin_shufflevector(__ret_63, __ret_63, 3, 2, 1, 0); \
44882	48068	__ret_63; \
44883	48069	})
44884	48070	#endif
44885	48071
44886	48072	#ifdef __LITTLE_ENDIAN__
44887		#define vcopyq_laneq_s16(__p0_64, __p1_64, __p2_64, __p3_64) __extension__ ({ \
44888		int16x8_t __s0_64 = __p0_64; \
44889		int16x8_t __s2_64 = __p2_64; \
44890		int16x8_t __ret_64; \
44891		__ret_64 = vsetq_lane_s16(vgetq_lane_s16(__s2_64, __p3_64), __s0_64, __p1_64); \
	48073	#define vcopyq_laneq_u64(__p0_64, __p1_64, __p2_64, __p3_64) __extension__ ({ \
	48074	uint64x2_t __s0_64 = __p0_64; \
	48075	uint64x2_t __s2_64 = __p2_64; \
	48076	uint64x2_t __ret_64; \
	48077	__ret_64 = vsetq_lane_u64(vgetq_lane_u64(__s2_64, __p3_64), __s0_64, __p1_64); \
44892	48078	__ret_64; \
44893	48079	})
44894	48080	#else
44895		#define vcopyq_laneq_s16(__p0_65, __p1_65, __p2_65, __p3_65) __extension__ ({ \
44896		int16x8_t __s0_65 = __p0_65; \
44897		int16x8_t __s2_65 = __p2_65; \
44898		int16x8_t __rev0_65; __rev0_65 = __builtin_shufflevector(__s0_65, __s0_65, 7, 6, 5, 4, 3, 2, 1, 0); \
44899		int16x8_t __rev2_65; __rev2_65 = __builtin_shufflevector(__s2_65, __s2_65, 7, 6, 5, 4, 3, 2, 1, 0); \
44900		int16x8_t __ret_65; \
44901		__ret_65 = __noswap_vsetq_lane_s16(__noswap_vgetq_lane_s16(__rev2_65, __p3_65), __rev0_65, __p1_65); \
44902		__ret_65 = __builtin_shufflevector(__ret_65, __ret_65, 7, 6, 5, 4, 3, 2, 1, 0); \
	48081	#define vcopyq_laneq_u64(__p0_65, __p1_65, __p2_65, __p3_65) __extension__ ({ \
	48082	uint64x2_t __s0_65 = __p0_65; \
	48083	uint64x2_t __s2_65 = __p2_65; \
	48084	uint64x2_t __rev0_65; __rev0_65 = __builtin_shufflevector(__s0_65, __s0_65, 1, 0); \
	48085	uint64x2_t __rev2_65; __rev2_65 = __builtin_shufflevector(__s2_65, __s2_65, 1, 0); \
	48086	uint64x2_t __ret_65; \
	48087	__ret_65 = __noswap_vsetq_lane_u64(__noswap_vgetq_lane_u64(__rev2_65, __p3_65), __rev0_65, __p1_65); \
	48088	__ret_65 = __builtin_shufflevector(__ret_65, __ret_65, 1, 0); \
44903	48089	__ret_65; \
44904	48090	})
44905	48091	#endif
44906	48092
44907	48093	#ifdef __LITTLE_ENDIAN__
44908		#define vcopy_laneq_p8(__p0_66, __p1_66, __p2_66, __p3_66) __extension__ ({ \
44909		poly8x8_t __s0_66 = __p0_66; \
44910		poly8x16_t __s2_66 = __p2_66; \
44911		poly8x8_t __ret_66; \
44912		__ret_66 = vset_lane_p8(vgetq_lane_p8(__s2_66, __p3_66), __s0_66, __p1_66); \
	48094	#define vcopyq_laneq_u16(__p0_66, __p1_66, __p2_66, __p3_66) __extension__ ({ \
	48095	uint16x8_t __s0_66 = __p0_66; \
	48096	uint16x8_t __s2_66 = __p2_66; \
	48097	uint16x8_t __ret_66; \
	48098	__ret_66 = vsetq_lane_u16(vgetq_lane_u16(__s2_66, __p3_66), __s0_66, __p1_66); \
44913	48099	__ret_66; \
44914	48100	})
44915	48101	#else
44916		#define vcopy_laneq_p8(__p0_67, __p1_67, __p2_67, __p3_67) __extension__ ({ \
44917		poly8x8_t __s0_67 = __p0_67; \
44918		poly8x16_t __s2_67 = __p2_67; \
44919		poly8x8_t __rev0_67; __rev0_67 = __builtin_shufflevector(__s0_67, __s0_67, 7, 6, 5, 4, 3, 2, 1, 0); \
44920		poly8x16_t __rev2_67; __rev2_67 = __builtin_shufflevector(__s2_67, __s2_67, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44921		poly8x8_t __ret_67; \
44922		__ret_67 = __noswap_vset_lane_p8(__noswap_vgetq_lane_p8(__rev2_67, __p3_67), __rev0_67, __p1_67); \
	48102	#define vcopyq_laneq_u16(__p0_67, __p1_67, __p2_67, __p3_67) __extension__ ({ \
	48103	uint16x8_t __s0_67 = __p0_67; \
	48104	uint16x8_t __s2_67 = __p2_67; \
	48105	uint16x8_t __rev0_67; __rev0_67 = __builtin_shufflevector(__s0_67, __s0_67, 7, 6, 5, 4, 3, 2, 1, 0); \
	48106	uint16x8_t __rev2_67; __rev2_67 = __builtin_shufflevector(__s2_67, __s2_67, 7, 6, 5, 4, 3, 2, 1, 0); \
	48107	uint16x8_t __ret_67; \
	48108	__ret_67 = __noswap_vsetq_lane_u16(__noswap_vgetq_lane_u16(__rev2_67, __p3_67), __rev0_67, __p1_67); \
44923	48109	__ret_67 = __builtin_shufflevector(__ret_67, __ret_67, 7, 6, 5, 4, 3, 2, 1, 0); \
44924	48110	__ret_67; \
44925	48111	})
44926	48112	#endif
44927	48113
44928	48114	#ifdef __LITTLE_ENDIAN__
44929		#define vcopy_laneq_p16(__p0_68, __p1_68, __p2_68, __p3_68) __extension__ ({ \
44930		poly16x4_t __s0_68 = __p0_68; \
44931		poly16x8_t __s2_68 = __p2_68; \
44932		poly16x4_t __ret_68; \
44933		__ret_68 = vset_lane_p16(vgetq_lane_p16(__s2_68, __p3_68), __s0_68, __p1_68); \
	48115	#define vcopyq_laneq_s8(__p0_68, __p1_68, __p2_68, __p3_68) __extension__ ({ \
	48116	int8x16_t __s0_68 = __p0_68; \
	48117	int8x16_t __s2_68 = __p2_68; \
	48118	int8x16_t __ret_68; \
	48119	__ret_68 = vsetq_lane_s8(vgetq_lane_s8(__s2_68, __p3_68), __s0_68, __p1_68); \
44934	48120	__ret_68; \
44935	48121	})
44936	48122	#else
44937		#define vcopy_laneq_p16(__p0_69, __p1_69, __p2_69, __p3_69) __extension__ ({ \
44938		poly16x4_t __s0_69 = __p0_69; \
44939		poly16x8_t __s2_69 = __p2_69; \
44940		poly16x4_t __rev0_69; __rev0_69 = __builtin_shufflevector(__s0_69, __s0_69, 3, 2, 1, 0); \
44941		poly16x8_t __rev2_69; __rev2_69 = __builtin_shufflevector(__s2_69, __s2_69, 7, 6, 5, 4, 3, 2, 1, 0); \
44942		poly16x4_t __ret_69; \
44943		__ret_69 = __noswap_vset_lane_p16(__noswap_vgetq_lane_p16(__rev2_69, __p3_69), __rev0_69, __p1_69); \
44944		__ret_69 = __builtin_shufflevector(__ret_69, __ret_69, 3, 2, 1, 0); \
	48123	#define vcopyq_laneq_s8(__p0_69, __p1_69, __p2_69, __p3_69) __extension__ ({ \
	48124	int8x16_t __s0_69 = __p0_69; \
	48125	int8x16_t __s2_69 = __p2_69; \
	48126	int8x16_t __rev0_69; __rev0_69 = __builtin_shufflevector(__s0_69, __s0_69, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48127	int8x16_t __rev2_69; __rev2_69 = __builtin_shufflevector(__s2_69, __s2_69, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48128	int8x16_t __ret_69; \
	48129	__ret_69 = __noswap_vsetq_lane_s8(__noswap_vgetq_lane_s8(__rev2_69, __p3_69), __rev0_69, __p1_69); \
	48130	__ret_69 = __builtin_shufflevector(__ret_69, __ret_69, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44945	48131	__ret_69; \
44946	48132	})
44947	48133	#endif
44948	48134
44949	48135	#ifdef __LITTLE_ENDIAN__
44950		#define vcopy_laneq_u8(__p0_70, __p1_70, __p2_70, __p3_70) __extension__ ({ \
44951		uint8x8_t __s0_70 = __p0_70; \
44952		uint8x16_t __s2_70 = __p2_70; \
44953		uint8x8_t __ret_70; \
44954		__ret_70 = vset_lane_u8(vgetq_lane_u8(__s2_70, __p3_70), __s0_70, __p1_70); \
	48136	#define vcopyq_laneq_f32(__p0_70, __p1_70, __p2_70, __p3_70) __extension__ ({ \
	48137	float32x4_t __s0_70 = __p0_70; \
	48138	float32x4_t __s2_70 = __p2_70; \
	48139	float32x4_t __ret_70; \
	48140	__ret_70 = vsetq_lane_f32(vgetq_lane_f32(__s2_70, __p3_70), __s0_70, __p1_70); \
44955	48141	__ret_70; \
44956	48142	})
44957	48143	#else
44958		#define vcopy_laneq_u8(__p0_71, __p1_71, __p2_71, __p3_71) __extension__ ({ \
44959		uint8x8_t __s0_71 = __p0_71; \
44960		uint8x16_t __s2_71 = __p2_71; \
44961		uint8x8_t __rev0_71; __rev0_71 = __builtin_shufflevector(__s0_71, __s0_71, 7, 6, 5, 4, 3, 2, 1, 0); \
44962		uint8x16_t __rev2_71; __rev2_71 = __builtin_shufflevector(__s2_71, __s2_71, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
44963		uint8x8_t __ret_71; \
44964		__ret_71 = __noswap_vset_lane_u8(__noswap_vgetq_lane_u8(__rev2_71, __p3_71), __rev0_71, __p1_71); \
44965		__ret_71 = __builtin_shufflevector(__ret_71, __ret_71, 7, 6, 5, 4, 3, 2, 1, 0); \
	48144	#define vcopyq_laneq_f32(__p0_71, __p1_71, __p2_71, __p3_71) __extension__ ({ \
	48145	float32x4_t __s0_71 = __p0_71; \
	48146	float32x4_t __s2_71 = __p2_71; \
	48147	float32x4_t __rev0_71; __rev0_71 = __builtin_shufflevector(__s0_71, __s0_71, 3, 2, 1, 0); \
	48148	float32x4_t __rev2_71; __rev2_71 = __builtin_shufflevector(__s2_71, __s2_71, 3, 2, 1, 0); \
	48149	float32x4_t __ret_71; \
	48150	__ret_71 = __noswap_vsetq_lane_f32(__noswap_vgetq_lane_f32(__rev2_71, __p3_71), __rev0_71, __p1_71); \
	48151	__ret_71 = __builtin_shufflevector(__ret_71, __ret_71, 3, 2, 1, 0); \
44966	48152	__ret_71; \
44967	48153	})
44968	48154	#endif
44969	48155
44970	48156	#ifdef __LITTLE_ENDIAN__
44971		#define vcopy_laneq_u32(__p0_72, __p1_72, __p2_72, __p3_72) __extension__ ({ \
44972		uint32x2_t __s0_72 = __p0_72; \
44973		uint32x4_t __s2_72 = __p2_72; \
44974		uint32x2_t __ret_72; \
44975		__ret_72 = vset_lane_u32(vgetq_lane_u32(__s2_72, __p3_72), __s0_72, __p1_72); \
	48157	#define vcopyq_laneq_s32(__p0_72, __p1_72, __p2_72, __p3_72) __extension__ ({ \
	48158	int32x4_t __s0_72 = __p0_72; \
	48159	int32x4_t __s2_72 = __p2_72; \
	48160	int32x4_t __ret_72; \
	48161	__ret_72 = vsetq_lane_s32(vgetq_lane_s32(__s2_72, __p3_72), __s0_72, __p1_72); \
44976	48162	__ret_72; \
44977	48163	})
44978	48164	#else
44979		#define vcopy_laneq_u32(__p0_73, __p1_73, __p2_73, __p3_73) __extension__ ({ \
44980		uint32x2_t __s0_73 = __p0_73; \
44981		uint32x4_t __s2_73 = __p2_73; \
44982		uint32x2_t __rev0_73; __rev0_73 = __builtin_shufflevector(__s0_73, __s0_73, 1, 0); \
44983		uint32x4_t __rev2_73; __rev2_73 = __builtin_shufflevector(__s2_73, __s2_73, 3, 2, 1, 0); \
44984		uint32x2_t __ret_73; \
44985		__ret_73 = __noswap_vset_lane_u32(__noswap_vgetq_lane_u32(__rev2_73, __p3_73), __rev0_73, __p1_73); \
44986		__ret_73 = __builtin_shufflevector(__ret_73, __ret_73, 1, 0); \
	48165	#define vcopyq_laneq_s32(__p0_73, __p1_73, __p2_73, __p3_73) __extension__ ({ \
	48166	int32x4_t __s0_73 = __p0_73; \
	48167	int32x4_t __s2_73 = __p2_73; \
	48168	int32x4_t __rev0_73; __rev0_73 = __builtin_shufflevector(__s0_73, __s0_73, 3, 2, 1, 0); \
	48169	int32x4_t __rev2_73; __rev2_73 = __builtin_shufflevector(__s2_73, __s2_73, 3, 2, 1, 0); \
	48170	int32x4_t __ret_73; \
	48171	__ret_73 = __noswap_vsetq_lane_s32(__noswap_vgetq_lane_s32(__rev2_73, __p3_73), __rev0_73, __p1_73); \
	48172	__ret_73 = __builtin_shufflevector(__ret_73, __ret_73, 3, 2, 1, 0); \
44987	48173	__ret_73; \
44988	48174	})
44989	48175	#endif
44990	48176
44991	48177	#ifdef __LITTLE_ENDIAN__
44992		#define vcopy_laneq_u64(__p0_74, __p1_74, __p2_74, __p3_74) __extension__ ({ \
44993		uint64x1_t __s0_74 = __p0_74; \
44994		uint64x2_t __s2_74 = __p2_74; \
44995		uint64x1_t __ret_74; \
44996		__ret_74 = vset_lane_u64(vgetq_lane_u64(__s2_74, __p3_74), __s0_74, __p1_74); \
	48178	#define vcopyq_laneq_s64(__p0_74, __p1_74, __p2_74, __p3_74) __extension__ ({ \
	48179	int64x2_t __s0_74 = __p0_74; \
	48180	int64x2_t __s2_74 = __p2_74; \
	48181	int64x2_t __ret_74; \
	48182	__ret_74 = vsetq_lane_s64(vgetq_lane_s64(__s2_74, __p3_74), __s0_74, __p1_74); \
44997	48183	__ret_74; \
44998	48184	})
44999	48185	#else
45000		#define vcopy_laneq_u64(__p0_75, __p1_75, __p2_75, __p3_75) __extension__ ({ \
45001		uint64x1_t __s0_75 = __p0_75; \
45002		uint64x2_t __s2_75 = __p2_75; \
45003		uint64x2_t __rev2_75; __rev2_75 = __builtin_shufflevector(__s2_75, __s2_75, 1, 0); \
45004		uint64x1_t __ret_75; \
45005		__ret_75 = __noswap_vset_lane_u64(__noswap_vgetq_lane_u64(__rev2_75, __p3_75), __s0_75, __p1_75); \
	48186	#define vcopyq_laneq_s64(__p0_75, __p1_75, __p2_75, __p3_75) __extension__ ({ \
	48187	int64x2_t __s0_75 = __p0_75; \
	48188	int64x2_t __s2_75 = __p2_75; \
	48189	int64x2_t __rev0_75; __rev0_75 = __builtin_shufflevector(__s0_75, __s0_75, 1, 0); \
	48190	int64x2_t __rev2_75; __rev2_75 = __builtin_shufflevector(__s2_75, __s2_75, 1, 0); \
	48191	int64x2_t __ret_75; \
	48192	__ret_75 = __noswap_vsetq_lane_s64(__noswap_vgetq_lane_s64(__rev2_75, __p3_75), __rev0_75, __p1_75); \
	48193	__ret_75 = __builtin_shufflevector(__ret_75, __ret_75, 1, 0); \
45006	48194	__ret_75; \
45007	48195	})
45008	48196	#endif
45009	48197
45010	48198	#ifdef __LITTLE_ENDIAN__
45011		#define vcopy_laneq_u16(__p0_76, __p1_76, __p2_76, __p3_76) __extension__ ({ \
45012		uint16x4_t __s0_76 = __p0_76; \
45013		uint16x8_t __s2_76 = __p2_76; \
45014		uint16x4_t __ret_76; \
45015		__ret_76 = vset_lane_u16(vgetq_lane_u16(__s2_76, __p3_76), __s0_76, __p1_76); \
	48199	#define vcopyq_laneq_s16(__p0_76, __p1_76, __p2_76, __p3_76) __extension__ ({ \
	48200	int16x8_t __s0_76 = __p0_76; \
	48201	int16x8_t __s2_76 = __p2_76; \
	48202	int16x8_t __ret_76; \
	48203	__ret_76 = vsetq_lane_s16(vgetq_lane_s16(__s2_76, __p3_76), __s0_76, __p1_76); \
45016	48204	__ret_76; \
45017	48205	})
45018	48206	#else
45019		#define vcopy_laneq_u16(__p0_77, __p1_77, __p2_77, __p3_77) __extension__ ({ \
45020		uint16x4_t __s0_77 = __p0_77; \
45021		uint16x8_t __s2_77 = __p2_77; \
45022		uint16x4_t __rev0_77; __rev0_77 = __builtin_shufflevector(__s0_77, __s0_77, 3, 2, 1, 0); \
45023		uint16x8_t __rev2_77; __rev2_77 = __builtin_shufflevector(__s2_77, __s2_77, 7, 6, 5, 4, 3, 2, 1, 0); \
45024		uint16x4_t __ret_77; \
45025		__ret_77 = __noswap_vset_lane_u16(__noswap_vgetq_lane_u16(__rev2_77, __p3_77), __rev0_77, __p1_77); \
45026		__ret_77 = __builtin_shufflevector(__ret_77, __ret_77, 3, 2, 1, 0); \
	48207	#define vcopyq_laneq_s16(__p0_77, __p1_77, __p2_77, __p3_77) __extension__ ({ \
	48208	int16x8_t __s0_77 = __p0_77; \
	48209	int16x8_t __s2_77 = __p2_77; \
	48210	int16x8_t __rev0_77; __rev0_77 = __builtin_shufflevector(__s0_77, __s0_77, 7, 6, 5, 4, 3, 2, 1, 0); \
	48211	int16x8_t __rev2_77; __rev2_77 = __builtin_shufflevector(__s2_77, __s2_77, 7, 6, 5, 4, 3, 2, 1, 0); \
	48212	int16x8_t __ret_77; \
	48213	__ret_77 = __noswap_vsetq_lane_s16(__noswap_vgetq_lane_s16(__rev2_77, __p3_77), __rev0_77, __p1_77); \
	48214	__ret_77 = __builtin_shufflevector(__ret_77, __ret_77, 7, 6, 5, 4, 3, 2, 1, 0); \
45027	48215	__ret_77; \
45028	48216	})
45029	48217	#endif
45030	48218
45031	48219	#ifdef __LITTLE_ENDIAN__
45032		#define vcopy_laneq_s8(__p0_78, __p1_78, __p2_78, __p3_78) __extension__ ({ \
45033		int8x8_t __s0_78 = __p0_78; \
45034		int8x16_t __s2_78 = __p2_78; \
45035		int8x8_t __ret_78; \
45036		__ret_78 = vset_lane_s8(vgetq_lane_s8(__s2_78, __p3_78), __s0_78, __p1_78); \
	48220	#define vcopy_laneq_p8(__p0_78, __p1_78, __p2_78, __p3_78) __extension__ ({ \
	48221	poly8x8_t __s0_78 = __p0_78; \
	48222	poly8x16_t __s2_78 = __p2_78; \
	48223	poly8x8_t __ret_78; \
	48224	__ret_78 = vset_lane_p8(vgetq_lane_p8(__s2_78, __p3_78), __s0_78, __p1_78); \
45037	48225	__ret_78; \
45038	48226	})
45039	48227	#else
45040		#define vcopy_laneq_s8(__p0_79, __p1_79, __p2_79, __p3_79) __extension__ ({ \
45041		int8x8_t __s0_79 = __p0_79; \
45042		int8x16_t __s2_79 = __p2_79; \
45043		int8x8_t __rev0_79; __rev0_79 = __builtin_shufflevector(__s0_79, __s0_79, 7, 6, 5, 4, 3, 2, 1, 0); \
45044		int8x16_t __rev2_79; __rev2_79 = __builtin_shufflevector(__s2_79, __s2_79, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
45045		int8x8_t __ret_79; \
45046		__ret_79 = __noswap_vset_lane_s8(__noswap_vgetq_lane_s8(__rev2_79, __p3_79), __rev0_79, __p1_79); \
	48228	#define vcopy_laneq_p8(__p0_79, __p1_79, __p2_79, __p3_79) __extension__ ({ \
	48229	poly8x8_t __s0_79 = __p0_79; \
	48230	poly8x16_t __s2_79 = __p2_79; \
	48231	poly8x8_t __rev0_79; __rev0_79 = __builtin_shufflevector(__s0_79, __s0_79, 7, 6, 5, 4, 3, 2, 1, 0); \
	48232	poly8x16_t __rev2_79; __rev2_79 = __builtin_shufflevector(__s2_79, __s2_79, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48233	poly8x8_t __ret_79; \
	48234	__ret_79 = __noswap_vset_lane_p8(__noswap_vgetq_lane_p8(__rev2_79, __p3_79), __rev0_79, __p1_79); \
45047	48235	__ret_79 = __builtin_shufflevector(__ret_79, __ret_79, 7, 6, 5, 4, 3, 2, 1, 0); \
45048	48236	__ret_79; \
45049	48237	})
45050	48238	#endif
45051	48239
45052	48240	#ifdef __LITTLE_ENDIAN__
45053		#define vcopy_laneq_f32(__p0_80, __p1_80, __p2_80, __p3_80) __extension__ ({ \
45054		float32x2_t __s0_80 = __p0_80; \
45055		float32x4_t __s2_80 = __p2_80; \
45056		float32x2_t __ret_80; \
45057		__ret_80 = vset_lane_f32(vgetq_lane_f32(__s2_80, __p3_80), __s0_80, __p1_80); \
	48241	#define vcopy_laneq_p16(__p0_80, __p1_80, __p2_80, __p3_80) __extension__ ({ \
	48242	poly16x4_t __s0_80 = __p0_80; \
	48243	poly16x8_t __s2_80 = __p2_80; \
	48244	poly16x4_t __ret_80; \
	48245	__ret_80 = vset_lane_p16(vgetq_lane_p16(__s2_80, __p3_80), __s0_80, __p1_80); \
45058	48246	__ret_80; \
45059	48247	})
45060	48248	#else
45061		#define vcopy_laneq_f32(__p0_81, __p1_81, __p2_81, __p3_81) __extension__ ({ \
45062		float32x2_t __s0_81 = __p0_81; \
45063		float32x4_t __s2_81 = __p2_81; \
45064		float32x2_t __rev0_81; __rev0_81 = __builtin_shufflevector(__s0_81, __s0_81, 1, 0); \
45065		float32x4_t __rev2_81; __rev2_81 = __builtin_shufflevector(__s2_81, __s2_81, 3, 2, 1, 0); \
45066		float32x2_t __ret_81; \
45067		__ret_81 = __noswap_vset_lane_f32(__noswap_vgetq_lane_f32(__rev2_81, __p3_81), __rev0_81, __p1_81); \
45068		__ret_81 = __builtin_shufflevector(__ret_81, __ret_81, 1, 0); \
	48249	#define vcopy_laneq_p16(__p0_81, __p1_81, __p2_81, __p3_81) __extension__ ({ \
	48250	poly16x4_t __s0_81 = __p0_81; \
	48251	poly16x8_t __s2_81 = __p2_81; \
	48252	poly16x4_t __rev0_81; __rev0_81 = __builtin_shufflevector(__s0_81, __s0_81, 3, 2, 1, 0); \
	48253	poly16x8_t __rev2_81; __rev2_81 = __builtin_shufflevector(__s2_81, __s2_81, 7, 6, 5, 4, 3, 2, 1, 0); \
	48254	poly16x4_t __ret_81; \
	48255	__ret_81 = __noswap_vset_lane_p16(__noswap_vgetq_lane_p16(__rev2_81, __p3_81), __rev0_81, __p1_81); \
	48256	__ret_81 = __builtin_shufflevector(__ret_81, __ret_81, 3, 2, 1, 0); \
45069	48257	__ret_81; \
45070	48258	})
45071	48259	#endif
45072	48260
45073	48261	#ifdef __LITTLE_ENDIAN__
45074		#define vcopy_laneq_s32(__p0_82, __p1_82, __p2_82, __p3_82) __extension__ ({ \
45075		int32x2_t __s0_82 = __p0_82; \
45076		int32x4_t __s2_82 = __p2_82; \
45077		int32x2_t __ret_82; \
45078		__ret_82 = vset_lane_s32(vgetq_lane_s32(__s2_82, __p3_82), __s0_82, __p1_82); \
	48262	#define vcopy_laneq_u8(__p0_82, __p1_82, __p2_82, __p3_82) __extension__ ({ \
	48263	uint8x8_t __s0_82 = __p0_82; \
	48264	uint8x16_t __s2_82 = __p2_82; \
	48265	uint8x8_t __ret_82; \
	48266	__ret_82 = vset_lane_u8(vgetq_lane_u8(__s2_82, __p3_82), __s0_82, __p1_82); \
45079	48267	__ret_82; \
45080	48268	})
45081	48269	#else
45082		#define vcopy_laneq_s32(__p0_83, __p1_83, __p2_83, __p3_83) __extension__ ({ \
45083		int32x2_t __s0_83 = __p0_83; \
45084		int32x4_t __s2_83 = __p2_83; \
45085		int32x2_t __rev0_83; __rev0_83 = __builtin_shufflevector(__s0_83, __s0_83, 1, 0); \
45086		int32x4_t __rev2_83; __rev2_83 = __builtin_shufflevector(__s2_83, __s2_83, 3, 2, 1, 0); \
45087		int32x2_t __ret_83; \
45088		__ret_83 = __noswap_vset_lane_s32(__noswap_vgetq_lane_s32(__rev2_83, __p3_83), __rev0_83, __p1_83); \
45089		__ret_83 = __builtin_shufflevector(__ret_83, __ret_83, 1, 0); \
	48270	#define vcopy_laneq_u8(__p0_83, __p1_83, __p2_83, __p3_83) __extension__ ({ \
	48271	uint8x8_t __s0_83 = __p0_83; \
	48272	uint8x16_t __s2_83 = __p2_83; \
	48273	uint8x8_t __rev0_83; __rev0_83 = __builtin_shufflevector(__s0_83, __s0_83, 7, 6, 5, 4, 3, 2, 1, 0); \
	48274	uint8x16_t __rev2_83; __rev2_83 = __builtin_shufflevector(__s2_83, __s2_83, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48275	uint8x8_t __ret_83; \
	48276	__ret_83 = __noswap_vset_lane_u8(__noswap_vgetq_lane_u8(__rev2_83, __p3_83), __rev0_83, __p1_83); \
	48277	__ret_83 = __builtin_shufflevector(__ret_83, __ret_83, 7, 6, 5, 4, 3, 2, 1, 0); \
45090	48278	__ret_83; \
45091	48279	})
45092	48280	#endif
45093	48281
45094	48282	#ifdef __LITTLE_ENDIAN__
45095		#define vcopy_laneq_s64(__p0_84, __p1_84, __p2_84, __p3_84) __extension__ ({ \
45096		int64x1_t __s0_84 = __p0_84; \
45097		int64x2_t __s2_84 = __p2_84; \
45098		int64x1_t __ret_84; \
45099		__ret_84 = vset_lane_s64(vgetq_lane_s64(__s2_84, __p3_84), __s0_84, __p1_84); \
	48283	#define vcopy_laneq_u32(__p0_84, __p1_84, __p2_84, __p3_84) __extension__ ({ \
	48284	uint32x2_t __s0_84 = __p0_84; \
	48285	uint32x4_t __s2_84 = __p2_84; \
	48286	uint32x2_t __ret_84; \
	48287	__ret_84 = vset_lane_u32(vgetq_lane_u32(__s2_84, __p3_84), __s0_84, __p1_84); \
45100	48288	__ret_84; \
45101	48289	})
45102	48290	#else
45103		#define vcopy_laneq_s64(__p0_85, __p1_85, __p2_85, __p3_85) __extension__ ({ \
45104		int64x1_t __s0_85 = __p0_85; \
45105		int64x2_t __s2_85 = __p2_85; \
45106		int64x2_t __rev2_85; __rev2_85 = __builtin_shufflevector(__s2_85, __s2_85, 1, 0); \
45107		int64x1_t __ret_85; \
45108		__ret_85 = __noswap_vset_lane_s64(__noswap_vgetq_lane_s64(__rev2_85, __p3_85), __s0_85, __p1_85); \
	48291	#define vcopy_laneq_u32(__p0_85, __p1_85, __p2_85, __p3_85) __extension__ ({ \
	48292	uint32x2_t __s0_85 = __p0_85; \
	48293	uint32x4_t __s2_85 = __p2_85; \
	48294	uint32x2_t __rev0_85; __rev0_85 = __builtin_shufflevector(__s0_85, __s0_85, 1, 0); \
	48295	uint32x4_t __rev2_85; __rev2_85 = __builtin_shufflevector(__s2_85, __s2_85, 3, 2, 1, 0); \
	48296	uint32x2_t __ret_85; \
	48297	__ret_85 = __noswap_vset_lane_u32(__noswap_vgetq_lane_u32(__rev2_85, __p3_85), __rev0_85, __p1_85); \
	48298	__ret_85 = __builtin_shufflevector(__ret_85, __ret_85, 1, 0); \
45109	48299	__ret_85; \
45110	48300	})
45111	48301	#endif
45112	48302
45113	48303	#ifdef __LITTLE_ENDIAN__
45114		#define vcopy_laneq_s16(__p0_86, __p1_86, __p2_86, __p3_86) __extension__ ({ \
45115		int16x4_t __s0_86 = __p0_86; \
45116		int16x8_t __s2_86 = __p2_86; \
45117		int16x4_t __ret_86; \
45118		__ret_86 = vset_lane_s16(vgetq_lane_s16(__s2_86, __p3_86), __s0_86, __p1_86); \
	48304	#define vcopy_laneq_u64(__p0_86, __p1_86, __p2_86, __p3_86) __extension__ ({ \
	48305	uint64x1_t __s0_86 = __p0_86; \
	48306	uint64x2_t __s2_86 = __p2_86; \
	48307	uint64x1_t __ret_86; \
	48308	__ret_86 = vset_lane_u64(vgetq_lane_u64(__s2_86, __p3_86), __s0_86, __p1_86); \
45119	48309	__ret_86; \
45120	48310	})
45121	48311	#else
45122		#define vcopy_laneq_s16(__p0_87, __p1_87, __p2_87, __p3_87) __extension__ ({ \
45123		int16x4_t __s0_87 = __p0_87; \
45124		int16x8_t __s2_87 = __p2_87; \
45125		int16x4_t __rev0_87; __rev0_87 = __builtin_shufflevector(__s0_87, __s0_87, 3, 2, 1, 0); \
45126		int16x8_t __rev2_87; __rev2_87 = __builtin_shufflevector(__s2_87, __s2_87, 7, 6, 5, 4, 3, 2, 1, 0); \
45127		int16x4_t __ret_87; \
45128		__ret_87 = __noswap_vset_lane_s16(__noswap_vgetq_lane_s16(__rev2_87, __p3_87), __rev0_87, __p1_87); \
45129		__ret_87 = __builtin_shufflevector(__ret_87, __ret_87, 3, 2, 1, 0); \
	48312	#define vcopy_laneq_u64(__p0_87, __p1_87, __p2_87, __p3_87) __extension__ ({ \
	48313	uint64x1_t __s0_87 = __p0_87; \
	48314	uint64x2_t __s2_87 = __p2_87; \
	48315	uint64x2_t __rev2_87; __rev2_87 = __builtin_shufflevector(__s2_87, __s2_87, 1, 0); \
	48316	uint64x1_t __ret_87; \
	48317	__ret_87 = __noswap_vset_lane_u64(__noswap_vgetq_lane_u64(__rev2_87, __p3_87), __s0_87, __p1_87); \
45130	48318	__ret_87; \
45131	48319	})
45132	48320	#endif
45133	48321
	48322	#ifdef __LITTLE_ENDIAN__
	48323	#define vcopy_laneq_u16(__p0_88, __p1_88, __p2_88, __p3_88) __extension__ ({ \
	48324	uint16x4_t __s0_88 = __p0_88; \
	48325	uint16x8_t __s2_88 = __p2_88; \
	48326	uint16x4_t __ret_88; \
	48327	__ret_88 = vset_lane_u16(vgetq_lane_u16(__s2_88, __p3_88), __s0_88, __p1_88); \
	48328	__ret_88; \
	48329	})
	48330	#else
	48331	#define vcopy_laneq_u16(__p0_89, __p1_89, __p2_89, __p3_89) __extension__ ({ \
	48332	uint16x4_t __s0_89 = __p0_89; \
	48333	uint16x8_t __s2_89 = __p2_89; \
	48334	uint16x4_t __rev0_89; __rev0_89 = __builtin_shufflevector(__s0_89, __s0_89, 3, 2, 1, 0); \
	48335	uint16x8_t __rev2_89; __rev2_89 = __builtin_shufflevector(__s2_89, __s2_89, 7, 6, 5, 4, 3, 2, 1, 0); \
	48336	uint16x4_t __ret_89; \
	48337	__ret_89 = __noswap_vset_lane_u16(__noswap_vgetq_lane_u16(__rev2_89, __p3_89), __rev0_89, __p1_89); \
	48338	__ret_89 = __builtin_shufflevector(__ret_89, __ret_89, 3, 2, 1, 0); \
	48339	__ret_89; \
	48340	})
	48341	#endif
	48342
	48343	#ifdef __LITTLE_ENDIAN__
	48344	#define vcopy_laneq_s8(__p0_90, __p1_90, __p2_90, __p3_90) __extension__ ({ \
	48345	int8x8_t __s0_90 = __p0_90; \
	48346	int8x16_t __s2_90 = __p2_90; \
	48347	int8x8_t __ret_90; \
	48348	__ret_90 = vset_lane_s8(vgetq_lane_s8(__s2_90, __p3_90), __s0_90, __p1_90); \
	48349	__ret_90; \
	48350	})
	48351	#else
	48352	#define vcopy_laneq_s8(__p0_91, __p1_91, __p2_91, __p3_91) __extension__ ({ \
	48353	int8x8_t __s0_91 = __p0_91; \
	48354	int8x16_t __s2_91 = __p2_91; \
	48355	int8x8_t __rev0_91; __rev0_91 = __builtin_shufflevector(__s0_91, __s0_91, 7, 6, 5, 4, 3, 2, 1, 0); \
	48356	int8x16_t __rev2_91; __rev2_91 = __builtin_shufflevector(__s2_91, __s2_91, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	48357	int8x8_t __ret_91; \
	48358	__ret_91 = __noswap_vset_lane_s8(__noswap_vgetq_lane_s8(__rev2_91, __p3_91), __rev0_91, __p1_91); \
	48359	__ret_91 = __builtin_shufflevector(__ret_91, __ret_91, 7, 6, 5, 4, 3, 2, 1, 0); \
	48360	__ret_91; \
	48361	})
	48362	#endif
	48363
	48364	#ifdef __LITTLE_ENDIAN__
	48365	#define vcopy_laneq_f32(__p0_92, __p1_92, __p2_92, __p3_92) __extension__ ({ \
	48366	float32x2_t __s0_92 = __p0_92; \
	48367	float32x4_t __s2_92 = __p2_92; \
	48368	float32x2_t __ret_92; \
	48369	__ret_92 = vset_lane_f32(vgetq_lane_f32(__s2_92, __p3_92), __s0_92, __p1_92); \
	48370	__ret_92; \
	48371	})
	48372	#else
	48373	#define vcopy_laneq_f32(__p0_93, __p1_93, __p2_93, __p3_93) __extension__ ({ \
	48374	float32x2_t __s0_93 = __p0_93; \
	48375	float32x4_t __s2_93 = __p2_93; \
	48376	float32x2_t __rev0_93; __rev0_93 = __builtin_shufflevector(__s0_93, __s0_93, 1, 0); \
	48377	float32x4_t __rev2_93; __rev2_93 = __builtin_shufflevector(__s2_93, __s2_93, 3, 2, 1, 0); \
	48378	float32x2_t __ret_93; \
	48379	__ret_93 = __noswap_vset_lane_f32(__noswap_vgetq_lane_f32(__rev2_93, __p3_93), __rev0_93, __p1_93); \
	48380	__ret_93 = __builtin_shufflevector(__ret_93, __ret_93, 1, 0); \
	48381	__ret_93; \
	48382	})
	48383	#endif
	48384
	48385	#ifdef __LITTLE_ENDIAN__
	48386	#define vcopy_laneq_s32(__p0_94, __p1_94, __p2_94, __p3_94) __extension__ ({ \
	48387	int32x2_t __s0_94 = __p0_94; \
	48388	int32x4_t __s2_94 = __p2_94; \
	48389	int32x2_t __ret_94; \
	48390	__ret_94 = vset_lane_s32(vgetq_lane_s32(__s2_94, __p3_94), __s0_94, __p1_94); \
	48391	__ret_94; \
	48392	})
	48393	#else
	48394	#define vcopy_laneq_s32(__p0_95, __p1_95, __p2_95, __p3_95) __extension__ ({ \
	48395	int32x2_t __s0_95 = __p0_95; \
	48396	int32x4_t __s2_95 = __p2_95; \
	48397	int32x2_t __rev0_95; __rev0_95 = __builtin_shufflevector(__s0_95, __s0_95, 1, 0); \
	48398	int32x4_t __rev2_95; __rev2_95 = __builtin_shufflevector(__s2_95, __s2_95, 3, 2, 1, 0); \
	48399	int32x2_t __ret_95; \
	48400	__ret_95 = __noswap_vset_lane_s32(__noswap_vgetq_lane_s32(__rev2_95, __p3_95), __rev0_95, __p1_95); \
	48401	__ret_95 = __builtin_shufflevector(__ret_95, __ret_95, 1, 0); \
	48402	__ret_95; \
	48403	})
	48404	#endif
	48405
	48406	#ifdef __LITTLE_ENDIAN__
	48407	#define vcopy_laneq_s64(__p0_96, __p1_96, __p2_96, __p3_96) __extension__ ({ \
	48408	int64x1_t __s0_96 = __p0_96; \
	48409	int64x2_t __s2_96 = __p2_96; \
	48410	int64x1_t __ret_96; \
	48411	__ret_96 = vset_lane_s64(vgetq_lane_s64(__s2_96, __p3_96), __s0_96, __p1_96); \
	48412	__ret_96; \
	48413	})
	48414	#else
	48415	#define vcopy_laneq_s64(__p0_97, __p1_97, __p2_97, __p3_97) __extension__ ({ \
	48416	int64x1_t __s0_97 = __p0_97; \
	48417	int64x2_t __s2_97 = __p2_97; \
	48418	int64x2_t __rev2_97; __rev2_97 = __builtin_shufflevector(__s2_97, __s2_97, 1, 0); \
	48419	int64x1_t __ret_97; \
	48420	__ret_97 = __noswap_vset_lane_s64(__noswap_vgetq_lane_s64(__rev2_97, __p3_97), __s0_97, __p1_97); \
	48421	__ret_97; \
	48422	})
	48423	#endif
	48424
	48425	#ifdef __LITTLE_ENDIAN__
	48426	#define vcopy_laneq_s16(__p0_98, __p1_98, __p2_98, __p3_98) __extension__ ({ \
	48427	int16x4_t __s0_98 = __p0_98; \
	48428	int16x8_t __s2_98 = __p2_98; \
	48429	int16x4_t __ret_98; \
	48430	__ret_98 = vset_lane_s16(vgetq_lane_s16(__s2_98, __p3_98), __s0_98, __p1_98); \
	48431	__ret_98; \
	48432	})
	48433	#else
	48434	#define vcopy_laneq_s16(__p0_99, __p1_99, __p2_99, __p3_99) __extension__ ({ \
	48435	int16x4_t __s0_99 = __p0_99; \
	48436	int16x8_t __s2_99 = __p2_99; \
	48437	int16x4_t __rev0_99; __rev0_99 = __builtin_shufflevector(__s0_99, __s0_99, 3, 2, 1, 0); \
	48438	int16x8_t __rev2_99; __rev2_99 = __builtin_shufflevector(__s2_99, __s2_99, 7, 6, 5, 4, 3, 2, 1, 0); \
	48439	int16x4_t __ret_99; \
	48440	__ret_99 = __noswap_vset_lane_s16(__noswap_vgetq_lane_s16(__rev2_99, __p3_99), __rev0_99, __p1_99); \
	48441	__ret_99 = __builtin_shufflevector(__ret_99, __ret_99, 3, 2, 1, 0); \
	48442	__ret_99; \
	48443	})
	48444	#endif
	48445
45134	48446	#ifdef __LITTLE_ENDIAN__
45135	48447	__ai poly64x1_t vcreate_p64(uint64_t __p0) {
45136	48448	poly64x1_t __ret;
...	...	@@ -47736,272 +51048,272 @@ __ai float64x1_t vfms_f64(float64x1_t __p0, float64x1_t __p1, float64x1_t __p2)
47736	51048	#endif
47737	51049
47738	51050	#ifdef __LITTLE_ENDIAN__
47739		#define vfmsd_lane_f64(__p0_88, __p1_88, __p2_88, __p3_88) __extension__ ({ \
47740		float64_t __s0_88 = __p0_88; \
47741		float64_t __s1_88 = __p1_88; \
47742		float64x1_t __s2_88 = __p2_88; \
47743		float64_t __ret_88; \
47744		__ret_88 = vfmad_lane_f64(__s0_88, -__s1_88, __s2_88, __p3_88); \
47745		__ret_88; \
47746		})
47747		#else
47748		#define vfmsd_lane_f64(__p0_89, __p1_89, __p2_89, __p3_89) __extension__ ({ \
47749		float64_t __s0_89 = __p0_89; \
47750		float64_t __s1_89 = __p1_89; \
47751		float64x1_t __s2_89 = __p2_89; \
47752		float64_t __ret_89; \
47753		__ret_89 = __noswap_vfmad_lane_f64(__s0_89, -__s1_89, __s2_89, __p3_89); \
47754		__ret_89; \
47755		})
47756		#endif
47757
47758		#ifdef __LITTLE_ENDIAN__
47759		#define vfmss_lane_f32(__p0_90, __p1_90, __p2_90, __p3_90) __extension__ ({ \
47760		float32_t __s0_90 = __p0_90; \
47761		float32_t __s1_90 = __p1_90; \
47762		float32x2_t __s2_90 = __p2_90; \
47763		float32_t __ret_90; \
47764		__ret_90 = vfmas_lane_f32(__s0_90, -__s1_90, __s2_90, __p3_90); \
47765		__ret_90; \
47766		})
47767		#else
47768		#define vfmss_lane_f32(__p0_91, __p1_91, __p2_91, __p3_91) __extension__ ({ \
47769		float32_t __s0_91 = __p0_91; \
47770		float32_t __s1_91 = __p1_91; \
47771		float32x2_t __s2_91 = __p2_91; \
47772		float32x2_t __rev2_91; __rev2_91 = __builtin_shufflevector(__s2_91, __s2_91, 1, 0); \
47773		float32_t __ret_91; \
47774		__ret_91 = __noswap_vfmas_lane_f32(__s0_91, -__s1_91, __rev2_91, __p3_91); \
47775		__ret_91; \
47776		})
47777		#endif
47778
47779		#ifdef __LITTLE_ENDIAN__
47780		#define vfmsq_lane_f64(__p0_92, __p1_92, __p2_92, __p3_92) __extension__ ({ \
47781		float64x2_t __s0_92 = __p0_92; \
47782		float64x2_t __s1_92 = __p1_92; \
47783		float64x1_t __s2_92 = __p2_92; \
47784		float64x2_t __ret_92; \
47785		__ret_92 = vfmaq_lane_f64(__s0_92, -__s1_92, __s2_92, __p3_92); \
47786		__ret_92; \
47787		})
47788		#else
47789		#define vfmsq_lane_f64(__p0_93, __p1_93, __p2_93, __p3_93) __extension__ ({ \
47790		float64x2_t __s0_93 = __p0_93; \
47791		float64x2_t __s1_93 = __p1_93; \
47792		float64x1_t __s2_93 = __p2_93; \
47793		float64x2_t __rev0_93; __rev0_93 = __builtin_shufflevector(__s0_93, __s0_93, 1, 0); \
47794		float64x2_t __rev1_93; __rev1_93 = __builtin_shufflevector(__s1_93, __s1_93, 1, 0); \
47795		float64x2_t __ret_93; \
47796		__ret_93 = __noswap_vfmaq_lane_f64(__rev0_93, -__rev1_93, __s2_93, __p3_93); \
47797		__ret_93 = __builtin_shufflevector(__ret_93, __ret_93, 1, 0); \
47798		__ret_93; \
47799		})
47800		#endif
47801
47802		#ifdef __LITTLE_ENDIAN__
47803		#define vfmsq_lane_f32(__p0_94, __p1_94, __p2_94, __p3_94) __extension__ ({ \
47804		float32x4_t __s0_94 = __p0_94; \
47805		float32x4_t __s1_94 = __p1_94; \
47806		float32x2_t __s2_94 = __p2_94; \
47807		float32x4_t __ret_94; \
47808		__ret_94 = vfmaq_lane_f32(__s0_94, -__s1_94, __s2_94, __p3_94); \
47809		__ret_94; \
47810		})
47811		#else
47812		#define vfmsq_lane_f32(__p0_95, __p1_95, __p2_95, __p3_95) __extension__ ({ \
47813		float32x4_t __s0_95 = __p0_95; \
47814		float32x4_t __s1_95 = __p1_95; \
47815		float32x2_t __s2_95 = __p2_95; \
47816		float32x4_t __rev0_95; __rev0_95 = __builtin_shufflevector(__s0_95, __s0_95, 3, 2, 1, 0); \
47817		float32x4_t __rev1_95; __rev1_95 = __builtin_shufflevector(__s1_95, __s1_95, 3, 2, 1, 0); \
47818		float32x2_t __rev2_95; __rev2_95 = __builtin_shufflevector(__s2_95, __s2_95, 1, 0); \
47819		float32x4_t __ret_95; \
47820		__ret_95 = __noswap_vfmaq_lane_f32(__rev0_95, -__rev1_95, __rev2_95, __p3_95); \
47821		__ret_95 = __builtin_shufflevector(__ret_95, __ret_95, 3, 2, 1, 0); \
47822		__ret_95; \
47823		})
47824		#endif
47825
47826		#ifdef __LITTLE_ENDIAN__
47827		#define vfms_lane_f64(__p0_96, __p1_96, __p2_96, __p3_96) __extension__ ({ \
47828		float64x1_t __s0_96 = __p0_96; \
47829		float64x1_t __s1_96 = __p1_96; \
47830		float64x1_t __s2_96 = __p2_96; \
47831		float64x1_t __ret_96; \
47832		__ret_96 = vfma_lane_f64(__s0_96, -__s1_96, __s2_96, __p3_96); \
47833		__ret_96; \
47834		})
47835		#else
47836		#define vfms_lane_f64(__p0_97, __p1_97, __p2_97, __p3_97) __extension__ ({ \
47837		float64x1_t __s0_97 = __p0_97; \
47838		float64x1_t __s1_97 = __p1_97; \
47839		float64x1_t __s2_97 = __p2_97; \
47840		float64x1_t __ret_97; \
47841		__ret_97 = __noswap_vfma_lane_f64(__s0_97, -__s1_97, __s2_97, __p3_97); \
47842		__ret_97; \
47843		})
47844		#endif
47845
47846		#ifdef __LITTLE_ENDIAN__
47847		#define vfms_lane_f32(__p0_98, __p1_98, __p2_98, __p3_98) __extension__ ({ \
47848		float32x2_t __s0_98 = __p0_98; \
47849		float32x2_t __s1_98 = __p1_98; \
47850		float32x2_t __s2_98 = __p2_98; \
47851		float32x2_t __ret_98; \
47852		__ret_98 = vfma_lane_f32(__s0_98, -__s1_98, __s2_98, __p3_98); \
47853		__ret_98; \
47854		})
47855		#else
47856		#define vfms_lane_f32(__p0_99, __p1_99, __p2_99, __p3_99) __extension__ ({ \
47857		float32x2_t __s0_99 = __p0_99; \
47858		float32x2_t __s1_99 = __p1_99; \
47859		float32x2_t __s2_99 = __p2_99; \
47860		float32x2_t __rev0_99; __rev0_99 = __builtin_shufflevector(__s0_99, __s0_99, 1, 0); \
47861		float32x2_t __rev1_99; __rev1_99 = __builtin_shufflevector(__s1_99, __s1_99, 1, 0); \
47862		float32x2_t __rev2_99; __rev2_99 = __builtin_shufflevector(__s2_99, __s2_99, 1, 0); \
47863		float32x2_t __ret_99; \
47864		__ret_99 = __noswap_vfma_lane_f32(__rev0_99, -__rev1_99, __rev2_99, __p3_99); \
47865		__ret_99 = __builtin_shufflevector(__ret_99, __ret_99, 1, 0); \
47866		__ret_99; \
47867		})
47868		#endif
47869
47870		#ifdef __LITTLE_ENDIAN__
47871		#define vfmsd_laneq_f64(__p0_100, __p1_100, __p2_100, __p3_100) __extension__ ({ \
	51051	#define vfmsd_lane_f64(__p0_100, __p1_100, __p2_100, __p3_100) __extension__ ({ \
47872	51052	float64_t __s0_100 = __p0_100; \
47873	51053	float64_t __s1_100 = __p1_100; \
47874		float64x2_t __s2_100 = __p2_100; \
	51054	float64x1_t __s2_100 = __p2_100; \
47875	51055	float64_t __ret_100; \
47876		__ret_100 = vfmad_laneq_f64(__s0_100, -__s1_100, __s2_100, __p3_100); \
	51056	__ret_100 = vfmad_lane_f64(__s0_100, -__s1_100, __s2_100, __p3_100); \
47877	51057	__ret_100; \
47878	51058	})
47879	51059	#else
47880		#define vfmsd_laneq_f64(__p0_101, __p1_101, __p2_101, __p3_101) __extension__ ({ \
	51060	#define vfmsd_lane_f64(__p0_101, __p1_101, __p2_101, __p3_101) __extension__ ({ \
47881	51061	float64_t __s0_101 = __p0_101; \
47882	51062	float64_t __s1_101 = __p1_101; \
47883		float64x2_t __s2_101 = __p2_101; \
47884		float64x2_t __rev2_101; __rev2_101 = __builtin_shufflevector(__s2_101, __s2_101, 1, 0); \
	51063	float64x1_t __s2_101 = __p2_101; \
47885	51064	float64_t __ret_101; \
47886		__ret_101 = __noswap_vfmad_laneq_f64(__s0_101, -__s1_101, __rev2_101, __p3_101); \
	51065	__ret_101 = __noswap_vfmad_lane_f64(__s0_101, -__s1_101, __s2_101, __p3_101); \
47887	51066	__ret_101; \
47888	51067	})
47889	51068	#endif
47890	51069
47891	51070	#ifdef __LITTLE_ENDIAN__
47892		#define vfmss_laneq_f32(__p0_102, __p1_102, __p2_102, __p3_102) __extension__ ({ \
	51071	#define vfmss_lane_f32(__p0_102, __p1_102, __p2_102, __p3_102) __extension__ ({ \
47893	51072	float32_t __s0_102 = __p0_102; \
47894	51073	float32_t __s1_102 = __p1_102; \
47895		float32x4_t __s2_102 = __p2_102; \
	51074	float32x2_t __s2_102 = __p2_102; \
47896	51075	float32_t __ret_102; \
47897		__ret_102 = vfmas_laneq_f32(__s0_102, -__s1_102, __s2_102, __p3_102); \
	51076	__ret_102 = vfmas_lane_f32(__s0_102, -__s1_102, __s2_102, __p3_102); \
47898	51077	__ret_102; \
47899	51078	})
47900	51079	#else
47901		#define vfmss_laneq_f32(__p0_103, __p1_103, __p2_103, __p3_103) __extension__ ({ \
	51080	#define vfmss_lane_f32(__p0_103, __p1_103, __p2_103, __p3_103) __extension__ ({ \
47902	51081	float32_t __s0_103 = __p0_103; \
47903	51082	float32_t __s1_103 = __p1_103; \
47904		float32x4_t __s2_103 = __p2_103; \
47905		float32x4_t __rev2_103; __rev2_103 = __builtin_shufflevector(__s2_103, __s2_103, 3, 2, 1, 0); \
	51083	float32x2_t __s2_103 = __p2_103; \
	51084	float32x2_t __rev2_103; __rev2_103 = __builtin_shufflevector(__s2_103, __s2_103, 1, 0); \
47906	51085	float32_t __ret_103; \
47907		__ret_103 = __noswap_vfmas_laneq_f32(__s0_103, -__s1_103, __rev2_103, __p3_103); \
	51086	__ret_103 = __noswap_vfmas_lane_f32(__s0_103, -__s1_103, __rev2_103, __p3_103); \
47908	51087	__ret_103; \
47909	51088	})
47910	51089	#endif
47911	51090
47912	51091	#ifdef __LITTLE_ENDIAN__
47913		#define vfmsq_laneq_f64(__p0_104, __p1_104, __p2_104, __p3_104) __extension__ ({ \
	51092	#define vfmsq_lane_f64(__p0_104, __p1_104, __p2_104, __p3_104) __extension__ ({ \
47914	51093	float64x2_t __s0_104 = __p0_104; \
47915	51094	float64x2_t __s1_104 = __p1_104; \
47916		float64x2_t __s2_104 = __p2_104; \
	51095	float64x1_t __s2_104 = __p2_104; \
47917	51096	float64x2_t __ret_104; \
47918		__ret_104 = vfmaq_laneq_f64(__s0_104, -__s1_104, __s2_104, __p3_104); \
	51097	__ret_104 = vfmaq_lane_f64(__s0_104, -__s1_104, __s2_104, __p3_104); \
47919	51098	__ret_104; \
47920	51099	})
47921	51100	#else
47922		#define vfmsq_laneq_f64(__p0_105, __p1_105, __p2_105, __p3_105) __extension__ ({ \
	51101	#define vfmsq_lane_f64(__p0_105, __p1_105, __p2_105, __p3_105) __extension__ ({ \
47923	51102	float64x2_t __s0_105 = __p0_105; \
47924	51103	float64x2_t __s1_105 = __p1_105; \
47925		float64x2_t __s2_105 = __p2_105; \
	51104	float64x1_t __s2_105 = __p2_105; \
47926	51105	float64x2_t __rev0_105; __rev0_105 = __builtin_shufflevector(__s0_105, __s0_105, 1, 0); \
47927	51106	float64x2_t __rev1_105; __rev1_105 = __builtin_shufflevector(__s1_105, __s1_105, 1, 0); \
47928		float64x2_t __rev2_105; __rev2_105 = __builtin_shufflevector(__s2_105, __s2_105, 1, 0); \
47929	51107	float64x2_t __ret_105; \
47930		__ret_105 = __noswap_vfmaq_laneq_f64(__rev0_105, -__rev1_105, __rev2_105, __p3_105); \
	51108	__ret_105 = __noswap_vfmaq_lane_f64(__rev0_105, -__rev1_105, __s2_105, __p3_105); \
47931	51109	__ret_105 = __builtin_shufflevector(__ret_105, __ret_105, 1, 0); \
47932	51110	__ret_105; \
47933	51111	})
47934	51112	#endif
47935	51113
47936	51114	#ifdef __LITTLE_ENDIAN__
47937		#define vfmsq_laneq_f32(__p0_106, __p1_106, __p2_106, __p3_106) __extension__ ({ \
	51115	#define vfmsq_lane_f32(__p0_106, __p1_106, __p2_106, __p3_106) __extension__ ({ \
47938	51116	float32x4_t __s0_106 = __p0_106; \
47939	51117	float32x4_t __s1_106 = __p1_106; \
47940		float32x4_t __s2_106 = __p2_106; \
	51118	float32x2_t __s2_106 = __p2_106; \
47941	51119	float32x4_t __ret_106; \
47942		__ret_106 = vfmaq_laneq_f32(__s0_106, -__s1_106, __s2_106, __p3_106); \
	51120	__ret_106 = vfmaq_lane_f32(__s0_106, -__s1_106, __s2_106, __p3_106); \
47943	51121	__ret_106; \
47944	51122	})
47945	51123	#else
47946		#define vfmsq_laneq_f32(__p0_107, __p1_107, __p2_107, __p3_107) __extension__ ({ \
	51124	#define vfmsq_lane_f32(__p0_107, __p1_107, __p2_107, __p3_107) __extension__ ({ \
47947	51125	float32x4_t __s0_107 = __p0_107; \
47948	51126	float32x4_t __s1_107 = __p1_107; \
47949		float32x4_t __s2_107 = __p2_107; \
	51127	float32x2_t __s2_107 = __p2_107; \
47950	51128	float32x4_t __rev0_107; __rev0_107 = __builtin_shufflevector(__s0_107, __s0_107, 3, 2, 1, 0); \
47951	51129	float32x4_t __rev1_107; __rev1_107 = __builtin_shufflevector(__s1_107, __s1_107, 3, 2, 1, 0); \
47952		float32x4_t __rev2_107; __rev2_107 = __builtin_shufflevector(__s2_107, __s2_107, 3, 2, 1, 0); \
	51130	float32x2_t __rev2_107; __rev2_107 = __builtin_shufflevector(__s2_107, __s2_107, 1, 0); \
47953	51131	float32x4_t __ret_107; \
47954		__ret_107 = __noswap_vfmaq_laneq_f32(__rev0_107, -__rev1_107, __rev2_107, __p3_107); \
	51132	__ret_107 = __noswap_vfmaq_lane_f32(__rev0_107, -__rev1_107, __rev2_107, __p3_107); \
47955	51133	__ret_107 = __builtin_shufflevector(__ret_107, __ret_107, 3, 2, 1, 0); \
47956	51134	__ret_107; \
47957	51135	})
47958	51136	#endif
47959	51137
47960	51138	#ifdef __LITTLE_ENDIAN__
47961		#define vfms_laneq_f64(__p0_108, __p1_108, __p2_108, __p3_108) __extension__ ({ \
	51139	#define vfms_lane_f64(__p0_108, __p1_108, __p2_108, __p3_108) __extension__ ({ \
47962	51140	float64x1_t __s0_108 = __p0_108; \
47963	51141	float64x1_t __s1_108 = __p1_108; \
47964		float64x2_t __s2_108 = __p2_108; \
	51142	float64x1_t __s2_108 = __p2_108; \
47965	51143	float64x1_t __ret_108; \
47966		__ret_108 = vfma_laneq_f64(__s0_108, -__s1_108, __s2_108, __p3_108); \
	51144	__ret_108 = vfma_lane_f64(__s0_108, -__s1_108, __s2_108, __p3_108); \
47967	51145	__ret_108; \
47968	51146	})
47969	51147	#else
47970		#define vfms_laneq_f64(__p0_109, __p1_109, __p2_109, __p3_109) __extension__ ({ \
	51148	#define vfms_lane_f64(__p0_109, __p1_109, __p2_109, __p3_109) __extension__ ({ \
47971	51149	float64x1_t __s0_109 = __p0_109; \
47972	51150	float64x1_t __s1_109 = __p1_109; \
47973		float64x2_t __s2_109 = __p2_109; \
47974		float64x2_t __rev2_109; __rev2_109 = __builtin_shufflevector(__s2_109, __s2_109, 1, 0); \
	51151	float64x1_t __s2_109 = __p2_109; \
47975	51152	float64x1_t __ret_109; \
47976		__ret_109 = __noswap_vfma_laneq_f64(__s0_109, -__s1_109, __rev2_109, __p3_109); \
	51153	__ret_109 = __noswap_vfma_lane_f64(__s0_109, -__s1_109, __s2_109, __p3_109); \
47977	51154	__ret_109; \
47978	51155	})
47979	51156	#endif
47980	51157
47981	51158	#ifdef __LITTLE_ENDIAN__
47982		#define vfms_laneq_f32(__p0_110, __p1_110, __p2_110, __p3_110) __extension__ ({ \
	51159	#define vfms_lane_f32(__p0_110, __p1_110, __p2_110, __p3_110) __extension__ ({ \
47983	51160	float32x2_t __s0_110 = __p0_110; \
47984	51161	float32x2_t __s1_110 = __p1_110; \
47985		float32x4_t __s2_110 = __p2_110; \
	51162	float32x2_t __s2_110 = __p2_110; \
47986	51163	float32x2_t __ret_110; \
47987		__ret_110 = vfma_laneq_f32(__s0_110, -__s1_110, __s2_110, __p3_110); \
	51164	__ret_110 = vfma_lane_f32(__s0_110, -__s1_110, __s2_110, __p3_110); \
47988	51165	__ret_110; \
47989	51166	})
47990	51167	#else
47991		#define vfms_laneq_f32(__p0_111, __p1_111, __p2_111, __p3_111) __extension__ ({ \
	51168	#define vfms_lane_f32(__p0_111, __p1_111, __p2_111, __p3_111) __extension__ ({ \
47992	51169	float32x2_t __s0_111 = __p0_111; \
47993	51170	float32x2_t __s1_111 = __p1_111; \
47994		float32x4_t __s2_111 = __p2_111; \
	51171	float32x2_t __s2_111 = __p2_111; \
47995	51172	float32x2_t __rev0_111; __rev0_111 = __builtin_shufflevector(__s0_111, __s0_111, 1, 0); \
47996	51173	float32x2_t __rev1_111; __rev1_111 = __builtin_shufflevector(__s1_111, __s1_111, 1, 0); \
47997		float32x4_t __rev2_111; __rev2_111 = __builtin_shufflevector(__s2_111, __s2_111, 3, 2, 1, 0); \
	51174	float32x2_t __rev2_111; __rev2_111 = __builtin_shufflevector(__s2_111, __s2_111, 1, 0); \
47998	51175	float32x2_t __ret_111; \
47999		__ret_111 = __noswap_vfma_laneq_f32(__rev0_111, -__rev1_111, __rev2_111, __p3_111); \
	51176	__ret_111 = __noswap_vfma_lane_f32(__rev0_111, -__rev1_111, __rev2_111, __p3_111); \
48000	51177	__ret_111 = __builtin_shufflevector(__ret_111, __ret_111, 1, 0); \
48001	51178	__ret_111; \
48002	51179	})
48003	51180	#endif
48004	51181
	51182	#ifdef __LITTLE_ENDIAN__
	51183	#define vfmsd_laneq_f64(__p0_112, __p1_112, __p2_112, __p3_112) __extension__ ({ \
	51184	float64_t __s0_112 = __p0_112; \
	51185	float64_t __s1_112 = __p1_112; \
	51186	float64x2_t __s2_112 = __p2_112; \
	51187	float64_t __ret_112; \
	51188	__ret_112 = vfmad_laneq_f64(__s0_112, -__s1_112, __s2_112, __p3_112); \
	51189	__ret_112; \
	51190	})
	51191	#else
	51192	#define vfmsd_laneq_f64(__p0_113, __p1_113, __p2_113, __p3_113) __extension__ ({ \
	51193	float64_t __s0_113 = __p0_113; \
	51194	float64_t __s1_113 = __p1_113; \
	51195	float64x2_t __s2_113 = __p2_113; \
	51196	float64x2_t __rev2_113; __rev2_113 = __builtin_shufflevector(__s2_113, __s2_113, 1, 0); \
	51197	float64_t __ret_113; \
	51198	__ret_113 = __noswap_vfmad_laneq_f64(__s0_113, -__s1_113, __rev2_113, __p3_113); \
	51199	__ret_113; \
	51200	})
	51201	#endif
	51202
	51203	#ifdef __LITTLE_ENDIAN__
	51204	#define vfmss_laneq_f32(__p0_114, __p1_114, __p2_114, __p3_114) __extension__ ({ \
	51205	float32_t __s0_114 = __p0_114; \
	51206	float32_t __s1_114 = __p1_114; \
	51207	float32x4_t __s2_114 = __p2_114; \
	51208	float32_t __ret_114; \
	51209	__ret_114 = vfmas_laneq_f32(__s0_114, -__s1_114, __s2_114, __p3_114); \
	51210	__ret_114; \
	51211	})
	51212	#else
	51213	#define vfmss_laneq_f32(__p0_115, __p1_115, __p2_115, __p3_115) __extension__ ({ \
	51214	float32_t __s0_115 = __p0_115; \
	51215	float32_t __s1_115 = __p1_115; \
	51216	float32x4_t __s2_115 = __p2_115; \
	51217	float32x4_t __rev2_115; __rev2_115 = __builtin_shufflevector(__s2_115, __s2_115, 3, 2, 1, 0); \
	51218	float32_t __ret_115; \
	51219	__ret_115 = __noswap_vfmas_laneq_f32(__s0_115, -__s1_115, __rev2_115, __p3_115); \
	51220	__ret_115; \
	51221	})
	51222	#endif
	51223
	51224	#ifdef __LITTLE_ENDIAN__
	51225	#define vfmsq_laneq_f64(__p0_116, __p1_116, __p2_116, __p3_116) __extension__ ({ \
	51226	float64x2_t __s0_116 = __p0_116; \
	51227	float64x2_t __s1_116 = __p1_116; \
	51228	float64x2_t __s2_116 = __p2_116; \
	51229	float64x2_t __ret_116; \
	51230	__ret_116 = vfmaq_laneq_f64(__s0_116, -__s1_116, __s2_116, __p3_116); \
	51231	__ret_116; \
	51232	})
	51233	#else
	51234	#define vfmsq_laneq_f64(__p0_117, __p1_117, __p2_117, __p3_117) __extension__ ({ \
	51235	float64x2_t __s0_117 = __p0_117; \
	51236	float64x2_t __s1_117 = __p1_117; \
	51237	float64x2_t __s2_117 = __p2_117; \
	51238	float64x2_t __rev0_117; __rev0_117 = __builtin_shufflevector(__s0_117, __s0_117, 1, 0); \
	51239	float64x2_t __rev1_117; __rev1_117 = __builtin_shufflevector(__s1_117, __s1_117, 1, 0); \
	51240	float64x2_t __rev2_117; __rev2_117 = __builtin_shufflevector(__s2_117, __s2_117, 1, 0); \
	51241	float64x2_t __ret_117; \
	51242	__ret_117 = __noswap_vfmaq_laneq_f64(__rev0_117, -__rev1_117, __rev2_117, __p3_117); \
	51243	__ret_117 = __builtin_shufflevector(__ret_117, __ret_117, 1, 0); \
	51244	__ret_117; \
	51245	})
	51246	#endif
	51247
	51248	#ifdef __LITTLE_ENDIAN__
	51249	#define vfmsq_laneq_f32(__p0_118, __p1_118, __p2_118, __p3_118) __extension__ ({ \
	51250	float32x4_t __s0_118 = __p0_118; \
	51251	float32x4_t __s1_118 = __p1_118; \
	51252	float32x4_t __s2_118 = __p2_118; \
	51253	float32x4_t __ret_118; \
	51254	__ret_118 = vfmaq_laneq_f32(__s0_118, -__s1_118, __s2_118, __p3_118); \
	51255	__ret_118; \
	51256	})
	51257	#else
	51258	#define vfmsq_laneq_f32(__p0_119, __p1_119, __p2_119, __p3_119) __extension__ ({ \
	51259	float32x4_t __s0_119 = __p0_119; \
	51260	float32x4_t __s1_119 = __p1_119; \
	51261	float32x4_t __s2_119 = __p2_119; \
	51262	float32x4_t __rev0_119; __rev0_119 = __builtin_shufflevector(__s0_119, __s0_119, 3, 2, 1, 0); \
	51263	float32x4_t __rev1_119; __rev1_119 = __builtin_shufflevector(__s1_119, __s1_119, 3, 2, 1, 0); \
	51264	float32x4_t __rev2_119; __rev2_119 = __builtin_shufflevector(__s2_119, __s2_119, 3, 2, 1, 0); \
	51265	float32x4_t __ret_119; \
	51266	__ret_119 = __noswap_vfmaq_laneq_f32(__rev0_119, -__rev1_119, __rev2_119, __p3_119); \
	51267	__ret_119 = __builtin_shufflevector(__ret_119, __ret_119, 3, 2, 1, 0); \
	51268	__ret_119; \
	51269	})
	51270	#endif
	51271
	51272	#ifdef __LITTLE_ENDIAN__
	51273	#define vfms_laneq_f64(__p0_120, __p1_120, __p2_120, __p3_120) __extension__ ({ \
	51274	float64x1_t __s0_120 = __p0_120; \
	51275	float64x1_t __s1_120 = __p1_120; \
	51276	float64x2_t __s2_120 = __p2_120; \
	51277	float64x1_t __ret_120; \
	51278	__ret_120 = vfma_laneq_f64(__s0_120, -__s1_120, __s2_120, __p3_120); \
	51279	__ret_120; \
	51280	})
	51281	#else
	51282	#define vfms_laneq_f64(__p0_121, __p1_121, __p2_121, __p3_121) __extension__ ({ \
	51283	float64x1_t __s0_121 = __p0_121; \
	51284	float64x1_t __s1_121 = __p1_121; \
	51285	float64x2_t __s2_121 = __p2_121; \
	51286	float64x2_t __rev2_121; __rev2_121 = __builtin_shufflevector(__s2_121, __s2_121, 1, 0); \
	51287	float64x1_t __ret_121; \
	51288	__ret_121 = __noswap_vfma_laneq_f64(__s0_121, -__s1_121, __rev2_121, __p3_121); \
	51289	__ret_121; \
	51290	})
	51291	#endif
	51292
	51293	#ifdef __LITTLE_ENDIAN__
	51294	#define vfms_laneq_f32(__p0_122, __p1_122, __p2_122, __p3_122) __extension__ ({ \
	51295	float32x2_t __s0_122 = __p0_122; \
	51296	float32x2_t __s1_122 = __p1_122; \
	51297	float32x4_t __s2_122 = __p2_122; \
	51298	float32x2_t __ret_122; \
	51299	__ret_122 = vfma_laneq_f32(__s0_122, -__s1_122, __s2_122, __p3_122); \
	51300	__ret_122; \
	51301	})
	51302	#else
	51303	#define vfms_laneq_f32(__p0_123, __p1_123, __p2_123, __p3_123) __extension__ ({ \
	51304	float32x2_t __s0_123 = __p0_123; \
	51305	float32x2_t __s1_123 = __p1_123; \
	51306	float32x4_t __s2_123 = __p2_123; \
	51307	float32x2_t __rev0_123; __rev0_123 = __builtin_shufflevector(__s0_123, __s0_123, 1, 0); \
	51308	float32x2_t __rev1_123; __rev1_123 = __builtin_shufflevector(__s1_123, __s1_123, 1, 0); \
	51309	float32x4_t __rev2_123; __rev2_123 = __builtin_shufflevector(__s2_123, __s2_123, 3, 2, 1, 0); \
	51310	float32x2_t __ret_123; \
	51311	__ret_123 = __noswap_vfma_laneq_f32(__rev0_123, -__rev1_123, __rev2_123, __p3_123); \
	51312	__ret_123 = __builtin_shufflevector(__ret_123, __ret_123, 1, 0); \
	51313	__ret_123; \
	51314	})
	51315	#endif
	51316
48005	51317	#ifdef __LITTLE_ENDIAN__
48006	51318	__ai float64x2_t vfmsq_n_f64(float64x2_t __p0, float64x2_t __p1, float64_t __p2) {
48007	51319	float64x2_t __ret;
...	...	@@ -53521,146 +56833,146 @@ __ai float64x1_t vmov_n_f64(float64_t __p0) {
53521	56833	#endif
53522	56834
53523	56835	#ifdef __LITTLE_ENDIAN__
53524		__ai uint16x8_t vmovl_high_u8(uint8x16_t __p0_112) {
53525		uint16x8_t __ret_112;
53526		uint8x8_t __a1_112 = vget_high_u8(__p0_112);
53527		__ret_112 = (uint16x8_t)(vshll_n_u8(__a1_112, 0));
53528		return __ret_112;
	56836	__ai uint16x8_t vmovl_high_u8(uint8x16_t __p0_124) {
	56837	uint16x8_t __ret_124;
	56838	uint8x8_t __a1_124 = vget_high_u8(__p0_124);
	56839	__ret_124 = (uint16x8_t)(vshll_n_u8(__a1_124, 0));
	56840	return __ret_124;
53529	56841	}
53530	56842	#else
53531		__ai uint16x8_t vmovl_high_u8(uint8x16_t __p0_113) {
53532		uint8x16_t __rev0_113; __rev0_113 = __builtin_shufflevector(__p0_113, __p0_113, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
53533		uint16x8_t __ret_113;
53534		uint8x8_t __a1_113 = __noswap_vget_high_u8(__rev0_113);
53535		__ret_113 = (uint16x8_t)(__noswap_vshll_n_u8(__a1_113, 0));
53536		__ret_113 = __builtin_shufflevector(__ret_113, __ret_113, 7, 6, 5, 4, 3, 2, 1, 0);
53537		return __ret_113;
	56843	__ai uint16x8_t vmovl_high_u8(uint8x16_t __p0_125) {
	56844	uint8x16_t __rev0_125; __rev0_125 = __builtin_shufflevector(__p0_125, __p0_125, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
	56845	uint16x8_t __ret_125;
	56846	uint8x8_t __a1_125 = __noswap_vget_high_u8(__rev0_125);
	56847	__ret_125 = (uint16x8_t)(__noswap_vshll_n_u8(__a1_125, 0));
	56848	__ret_125 = __builtin_shufflevector(__ret_125, __ret_125, 7, 6, 5, 4, 3, 2, 1, 0);
	56849	return __ret_125;
53538	56850	}
53539		__ai uint16x8_t __noswap_vmovl_high_u8(uint8x16_t __p0_114) {
53540		uint16x8_t __ret_114;
53541		uint8x8_t __a1_114 = __noswap_vget_high_u8(__p0_114);
53542		__ret_114 = (uint16x8_t)(__noswap_vshll_n_u8(__a1_114, 0));
53543		return __ret_114;
	56851	__ai uint16x8_t __noswap_vmovl_high_u8(uint8x16_t __p0_126) {
	56852	uint16x8_t __ret_126;
	56853	uint8x8_t __a1_126 = __noswap_vget_high_u8(__p0_126);
	56854	__ret_126 = (uint16x8_t)(__noswap_vshll_n_u8(__a1_126, 0));
	56855	return __ret_126;
53544	56856	}
53545	56857	#endif
53546	56858
53547	56859	#ifdef __LITTLE_ENDIAN__
53548		__ai uint64x2_t vmovl_high_u32(uint32x4_t __p0_115) {
53549		uint64x2_t __ret_115;
53550		uint32x2_t __a1_115 = vget_high_u32(__p0_115);
53551		__ret_115 = (uint64x2_t)(vshll_n_u32(__a1_115, 0));
53552		return __ret_115;
	56860	__ai uint64x2_t vmovl_high_u32(uint32x4_t __p0_127) {
	56861	uint64x2_t __ret_127;
	56862	uint32x2_t __a1_127 = vget_high_u32(__p0_127);
	56863	__ret_127 = (uint64x2_t)(vshll_n_u32(__a1_127, 0));
	56864	return __ret_127;
53553	56865	}
53554	56866	#else
53555		__ai uint64x2_t vmovl_high_u32(uint32x4_t __p0_116) {
53556		uint32x4_t __rev0_116; __rev0_116 = __builtin_shufflevector(__p0_116, __p0_116, 3, 2, 1, 0);
53557		uint64x2_t __ret_116;
53558		uint32x2_t __a1_116 = __noswap_vget_high_u32(__rev0_116);
53559		__ret_116 = (uint64x2_t)(__noswap_vshll_n_u32(__a1_116, 0));
53560		__ret_116 = __builtin_shufflevector(__ret_116, __ret_116, 1, 0);
53561		return __ret_116;
	56867	__ai uint64x2_t vmovl_high_u32(uint32x4_t __p0_128) {
	56868	uint32x4_t __rev0_128; __rev0_128 = __builtin_shufflevector(__p0_128, __p0_128, 3, 2, 1, 0);
	56869	uint64x2_t __ret_128;
	56870	uint32x2_t __a1_128 = __noswap_vget_high_u32(__rev0_128);
	56871	__ret_128 = (uint64x2_t)(__noswap_vshll_n_u32(__a1_128, 0));
	56872	__ret_128 = __builtin_shufflevector(__ret_128, __ret_128, 1, 0);
	56873	return __ret_128;
53562	56874	}
53563		__ai uint64x2_t __noswap_vmovl_high_u32(uint32x4_t __p0_117) {
53564		uint64x2_t __ret_117;
53565		uint32x2_t __a1_117 = __noswap_vget_high_u32(__p0_117);
53566		__ret_117 = (uint64x2_t)(__noswap_vshll_n_u32(__a1_117, 0));
53567		return __ret_117;
	56875	__ai uint64x2_t __noswap_vmovl_high_u32(uint32x4_t __p0_129) {
	56876	uint64x2_t __ret_129;
	56877	uint32x2_t __a1_129 = __noswap_vget_high_u32(__p0_129);
	56878	__ret_129 = (uint64x2_t)(__noswap_vshll_n_u32(__a1_129, 0));
	56879	return __ret_129;
53568	56880	}
53569	56881	#endif
53570	56882
53571	56883	#ifdef __LITTLE_ENDIAN__
53572		__ai uint32x4_t vmovl_high_u16(uint16x8_t __p0_118) {
53573		uint32x4_t __ret_118;
53574		uint16x4_t __a1_118 = vget_high_u16(__p0_118);
53575		__ret_118 = (uint32x4_t)(vshll_n_u16(__a1_118, 0));
53576		return __ret_118;
	56884	__ai uint32x4_t vmovl_high_u16(uint16x8_t __p0_130) {
	56885	uint32x4_t __ret_130;
	56886	uint16x4_t __a1_130 = vget_high_u16(__p0_130);
	56887	__ret_130 = (uint32x4_t)(vshll_n_u16(__a1_130, 0));
	56888	return __ret_130;
53577	56889	}
53578	56890	#else
53579		__ai uint32x4_t vmovl_high_u16(uint16x8_t __p0_119) {
53580		uint16x8_t __rev0_119; __rev0_119 = __builtin_shufflevector(__p0_119, __p0_119, 7, 6, 5, 4, 3, 2, 1, 0);
53581		uint32x4_t __ret_119;
53582		uint16x4_t __a1_119 = __noswap_vget_high_u16(__rev0_119);
53583		__ret_119 = (uint32x4_t)(__noswap_vshll_n_u16(__a1_119, 0));
53584		__ret_119 = __builtin_shufflevector(__ret_119, __ret_119, 3, 2, 1, 0);
53585		return __ret_119;
	56891	__ai uint32x4_t vmovl_high_u16(uint16x8_t __p0_131) {
	56892	uint16x8_t __rev0_131; __rev0_131 = __builtin_shufflevector(__p0_131, __p0_131, 7, 6, 5, 4, 3, 2, 1, 0);
	56893	uint32x4_t __ret_131;
	56894	uint16x4_t __a1_131 = __noswap_vget_high_u16(__rev0_131);
	56895	__ret_131 = (uint32x4_t)(__noswap_vshll_n_u16(__a1_131, 0));
	56896	__ret_131 = __builtin_shufflevector(__ret_131, __ret_131, 3, 2, 1, 0);
	56897	return __ret_131;
53586	56898	}
53587		__ai uint32x4_t __noswap_vmovl_high_u16(uint16x8_t __p0_120) {
53588		uint32x4_t __ret_120;
53589		uint16x4_t __a1_120 = __noswap_vget_high_u16(__p0_120);
53590		__ret_120 = (uint32x4_t)(__noswap_vshll_n_u16(__a1_120, 0));
53591		return __ret_120;
	56899	__ai uint32x4_t __noswap_vmovl_high_u16(uint16x8_t __p0_132) {
	56900	uint32x4_t __ret_132;
	56901	uint16x4_t __a1_132 = __noswap_vget_high_u16(__p0_132);
	56902	__ret_132 = (uint32x4_t)(__noswap_vshll_n_u16(__a1_132, 0));
	56903	return __ret_132;
53592	56904	}
53593	56905	#endif
53594	56906
53595	56907	#ifdef __LITTLE_ENDIAN__
53596		__ai int16x8_t vmovl_high_s8(int8x16_t __p0_121) {
53597		int16x8_t __ret_121;
53598		int8x8_t __a1_121 = vget_high_s8(__p0_121);
53599		__ret_121 = (int16x8_t)(vshll_n_s8(__a1_121, 0));
53600		return __ret_121;
	56908	__ai int16x8_t vmovl_high_s8(int8x16_t __p0_133) {
	56909	int16x8_t __ret_133;
	56910	int8x8_t __a1_133 = vget_high_s8(__p0_133);
	56911	__ret_133 = (int16x8_t)(vshll_n_s8(__a1_133, 0));
	56912	return __ret_133;
53601	56913	}
53602	56914	#else
53603		__ai int16x8_t vmovl_high_s8(int8x16_t __p0_122) {
53604		int8x16_t __rev0_122; __rev0_122 = __builtin_shufflevector(__p0_122, __p0_122, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
53605		int16x8_t __ret_122;
53606		int8x8_t __a1_122 = __noswap_vget_high_s8(__rev0_122);
53607		__ret_122 = (int16x8_t)(__noswap_vshll_n_s8(__a1_122, 0));
53608		__ret_122 = __builtin_shufflevector(__ret_122, __ret_122, 7, 6, 5, 4, 3, 2, 1, 0);
53609		return __ret_122;
	56915	__ai int16x8_t vmovl_high_s8(int8x16_t __p0_134) {
	56916	int8x16_t __rev0_134; __rev0_134 = __builtin_shufflevector(__p0_134, __p0_134, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
	56917	int16x8_t __ret_134;
	56918	int8x8_t __a1_134 = __noswap_vget_high_s8(__rev0_134);
	56919	__ret_134 = (int16x8_t)(__noswap_vshll_n_s8(__a1_134, 0));
	56920	__ret_134 = __builtin_shufflevector(__ret_134, __ret_134, 7, 6, 5, 4, 3, 2, 1, 0);
	56921	return __ret_134;
53610	56922	}
53611		__ai int16x8_t __noswap_vmovl_high_s8(int8x16_t __p0_123) {
53612		int16x8_t __ret_123;
53613		int8x8_t __a1_123 = __noswap_vget_high_s8(__p0_123);
53614		__ret_123 = (int16x8_t)(__noswap_vshll_n_s8(__a1_123, 0));
53615		return __ret_123;
	56923	__ai int16x8_t __noswap_vmovl_high_s8(int8x16_t __p0_135) {
	56924	int16x8_t __ret_135;
	56925	int8x8_t __a1_135 = __noswap_vget_high_s8(__p0_135);
	56926	__ret_135 = (int16x8_t)(__noswap_vshll_n_s8(__a1_135, 0));
	56927	return __ret_135;
53616	56928	}
53617	56929	#endif
53618	56930
53619	56931	#ifdef __LITTLE_ENDIAN__
53620		__ai int64x2_t vmovl_high_s32(int32x4_t __p0_124) {
53621		int64x2_t __ret_124;
53622		int32x2_t __a1_124 = vget_high_s32(__p0_124);
53623		__ret_124 = (int64x2_t)(vshll_n_s32(__a1_124, 0));
53624		return __ret_124;
	56932	__ai int64x2_t vmovl_high_s32(int32x4_t __p0_136) {
	56933	int64x2_t __ret_136;
	56934	int32x2_t __a1_136 = vget_high_s32(__p0_136);
	56935	__ret_136 = (int64x2_t)(vshll_n_s32(__a1_136, 0));
	56936	return __ret_136;
53625	56937	}
53626	56938	#else
53627		__ai int64x2_t vmovl_high_s32(int32x4_t __p0_125) {
53628		int32x4_t __rev0_125; __rev0_125 = __builtin_shufflevector(__p0_125, __p0_125, 3, 2, 1, 0);
53629		int64x2_t __ret_125;
53630		int32x2_t __a1_125 = __noswap_vget_high_s32(__rev0_125);
53631		__ret_125 = (int64x2_t)(__noswap_vshll_n_s32(__a1_125, 0));
53632		__ret_125 = __builtin_shufflevector(__ret_125, __ret_125, 1, 0);
53633		return __ret_125;
	56939	__ai int64x2_t vmovl_high_s32(int32x4_t __p0_137) {
	56940	int32x4_t __rev0_137; __rev0_137 = __builtin_shufflevector(__p0_137, __p0_137, 3, 2, 1, 0);
	56941	int64x2_t __ret_137;
	56942	int32x2_t __a1_137 = __noswap_vget_high_s32(__rev0_137);
	56943	__ret_137 = (int64x2_t)(__noswap_vshll_n_s32(__a1_137, 0));
	56944	__ret_137 = __builtin_shufflevector(__ret_137, __ret_137, 1, 0);
	56945	return __ret_137;
53634	56946	}
53635		__ai int64x2_t __noswap_vmovl_high_s32(int32x4_t __p0_126) {
53636		int64x2_t __ret_126;
53637		int32x2_t __a1_126 = __noswap_vget_high_s32(__p0_126);
53638		__ret_126 = (int64x2_t)(__noswap_vshll_n_s32(__a1_126, 0));
53639		return __ret_126;
	56947	__ai int64x2_t __noswap_vmovl_high_s32(int32x4_t __p0_138) {
	56948	int64x2_t __ret_138;
	56949	int32x2_t __a1_138 = __noswap_vget_high_s32(__p0_138);
	56950	__ret_138 = (int64x2_t)(__noswap_vshll_n_s32(__a1_138, 0));
	56951	return __ret_138;
53640	56952	}
53641	56953	#endif
53642	56954
53643	56955	#ifdef __LITTLE_ENDIAN__
53644		__ai int32x4_t vmovl_high_s16(int16x8_t __p0_127) {
53645		int32x4_t __ret_127;
53646		int16x4_t __a1_127 = vget_high_s16(__p0_127);
53647		__ret_127 = (int32x4_t)(vshll_n_s16(__a1_127, 0));
53648		return __ret_127;
	56956	__ai int32x4_t vmovl_high_s16(int16x8_t __p0_139) {
	56957	int32x4_t __ret_139;
	56958	int16x4_t __a1_139 = vget_high_s16(__p0_139);
	56959	__ret_139 = (int32x4_t)(vshll_n_s16(__a1_139, 0));
	56960	return __ret_139;
53649	56961	}
53650	56962	#else
53651		__ai int32x4_t vmovl_high_s16(int16x8_t __p0_128) {
53652		int16x8_t __rev0_128; __rev0_128 = __builtin_shufflevector(__p0_128, __p0_128, 7, 6, 5, 4, 3, 2, 1, 0);
53653		int32x4_t __ret_128;
53654		int16x4_t __a1_128 = __noswap_vget_high_s16(__rev0_128);
53655		__ret_128 = (int32x4_t)(__noswap_vshll_n_s16(__a1_128, 0));
53656		__ret_128 = __builtin_shufflevector(__ret_128, __ret_128, 3, 2, 1, 0);
53657		return __ret_128;
	56963	__ai int32x4_t vmovl_high_s16(int16x8_t __p0_140) {
	56964	int16x8_t __rev0_140; __rev0_140 = __builtin_shufflevector(__p0_140, __p0_140, 7, 6, 5, 4, 3, 2, 1, 0);
	56965	int32x4_t __ret_140;
	56966	int16x4_t __a1_140 = __noswap_vget_high_s16(__rev0_140);
	56967	__ret_140 = (int32x4_t)(__noswap_vshll_n_s16(__a1_140, 0));
	56968	__ret_140 = __builtin_shufflevector(__ret_140, __ret_140, 3, 2, 1, 0);
	56969	return __ret_140;
53658	56970	}
53659		__ai int32x4_t __noswap_vmovl_high_s16(int16x8_t __p0_129) {
53660		int32x4_t __ret_129;
53661		int16x4_t __a1_129 = __noswap_vget_high_s16(__p0_129);
53662		__ret_129 = (int32x4_t)(__noswap_vshll_n_s16(__a1_129, 0));
53663		return __ret_129;
	56971	__ai int32x4_t __noswap_vmovl_high_s16(int16x8_t __p0_141) {
	56972	int32x4_t __ret_141;
	56973	int16x4_t __a1_141 = __noswap_vget_high_s16(__p0_141);
	56974	__ret_141 = (int32x4_t)(__noswap_vshll_n_s16(__a1_141, 0));
	56975	return __ret_141;
53664	56976	}
53665	56977	#endif
53666	56978
...	...	@@ -53798,39 +57110,39 @@ __ai float64x1_t vmul_f64(float64x1_t __p0, float64x1_t __p1) {
53798	57110	#endif
53799	57111
53800	57112	#ifdef __LITTLE_ENDIAN__
53801		#define vmuld_lane_f64(__p0_130, __p1_130, __p2_130) __extension__ ({ \
53802		float64_t __s0_130 = __p0_130; \
53803		float64x1_t __s1_130 = __p1_130; \
53804		float64_t __ret_130; \
53805		__ret_130 = __s0_130 * vget_lane_f64(__s1_130, __p2_130); \
53806		__ret_130; \
	57113	#define vmuld_lane_f64(__p0_142, __p1_142, __p2_142) __extension__ ({ \
	57114	float64_t __s0_142 = __p0_142; \
	57115	float64x1_t __s1_142 = __p1_142; \
	57116	float64_t __ret_142; \
	57117	__ret_142 = __s0_142 * vget_lane_f64(__s1_142, __p2_142); \
	57118	__ret_142; \
53807	57119	})
53808	57120	#else
53809		#define vmuld_lane_f64(__p0_131, __p1_131, __p2_131) __extension__ ({ \
53810		float64_t __s0_131 = __p0_131; \
53811		float64x1_t __s1_131 = __p1_131; \
53812		float64_t __ret_131; \
53813		__ret_131 = __s0_131 * __noswap_vget_lane_f64(__s1_131, __p2_131); \
53814		__ret_131; \
	57121	#define vmuld_lane_f64(__p0_143, __p1_143, __p2_143) __extension__ ({ \
	57122	float64_t __s0_143 = __p0_143; \
	57123	float64x1_t __s1_143 = __p1_143; \
	57124	float64_t __ret_143; \
	57125	__ret_143 = __s0_143 * __noswap_vget_lane_f64(__s1_143, __p2_143); \
	57126	__ret_143; \
53815	57127	})
53816	57128	#endif
53817	57129
53818	57130	#ifdef __LITTLE_ENDIAN__
53819		#define vmuls_lane_f32(__p0_132, __p1_132, __p2_132) __extension__ ({ \
53820		float32_t __s0_132 = __p0_132; \
53821		float32x2_t __s1_132 = __p1_132; \
53822		float32_t __ret_132; \
53823		__ret_132 = __s0_132 * vget_lane_f32(__s1_132, __p2_132); \
53824		__ret_132; \
	57131	#define vmuls_lane_f32(__p0_144, __p1_144, __p2_144) __extension__ ({ \
	57132	float32_t __s0_144 = __p0_144; \
	57133	float32x2_t __s1_144 = __p1_144; \
	57134	float32_t __ret_144; \
	57135	__ret_144 = __s0_144 * vget_lane_f32(__s1_144, __p2_144); \
	57136	__ret_144; \
53825	57137	})
53826	57138	#else
53827		#define vmuls_lane_f32(__p0_133, __p1_133, __p2_133) __extension__ ({ \
53828		float32_t __s0_133 = __p0_133; \
53829		float32x2_t __s1_133 = __p1_133; \
53830		float32x2_t __rev1_133; __rev1_133 = __builtin_shufflevector(__s1_133, __s1_133, 1, 0); \
53831		float32_t __ret_133; \
53832		__ret_133 = __s0_133 * __noswap_vget_lane_f32(__rev1_133, __p2_133); \
53833		__ret_133; \
	57139	#define vmuls_lane_f32(__p0_145, __p1_145, __p2_145) __extension__ ({ \
	57140	float32_t __s0_145 = __p0_145; \
	57141	float32x2_t __s1_145 = __p1_145; \
	57142	float32x2_t __rev1_145; __rev1_145 = __builtin_shufflevector(__s1_145, __s1_145, 1, 0); \
	57143	float32_t __ret_145; \
	57144	__ret_145 = __s0_145 * __noswap_vget_lane_f32(__rev1_145, __p2_145); \
	57145	__ret_145; \
53834	57146	})
53835	57147	#endif
53836	57148
...	...	@@ -53873,40 +57185,40 @@ __ai float64x1_t vmul_f64(float64x1_t __p0, float64x1_t __p1) {
53873	57185	#endif
53874	57186
53875	57187	#ifdef __LITTLE_ENDIAN__
53876		#define vmuld_laneq_f64(__p0_134, __p1_134, __p2_134) __extension__ ({ \
53877		float64_t __s0_134 = __p0_134; \
53878		float64x2_t __s1_134 = __p1_134; \
53879		float64_t __ret_134; \
53880		__ret_134 = __s0_134 * vgetq_lane_f64(__s1_134, __p2_134); \
53881		__ret_134; \
	57188	#define vmuld_laneq_f64(__p0_146, __p1_146, __p2_146) __extension__ ({ \
	57189	float64_t __s0_146 = __p0_146; \
	57190	float64x2_t __s1_146 = __p1_146; \
	57191	float64_t __ret_146; \
	57192	__ret_146 = __s0_146 * vgetq_lane_f64(__s1_146, __p2_146); \
	57193	__ret_146; \
53882	57194	})
53883	57195	#else
53884		#define vmuld_laneq_f64(__p0_135, __p1_135, __p2_135) __extension__ ({ \
53885		float64_t __s0_135 = __p0_135; \
53886		float64x2_t __s1_135 = __p1_135; \
53887		float64x2_t __rev1_135; __rev1_135 = __builtin_shufflevector(__s1_135, __s1_135, 1, 0); \
53888		float64_t __ret_135; \
53889		__ret_135 = __s0_135 * __noswap_vgetq_lane_f64(__rev1_135, __p2_135); \
53890		__ret_135; \
	57196	#define vmuld_laneq_f64(__p0_147, __p1_147, __p2_147) __extension__ ({ \
	57197	float64_t __s0_147 = __p0_147; \
	57198	float64x2_t __s1_147 = __p1_147; \
	57199	float64x2_t __rev1_147; __rev1_147 = __builtin_shufflevector(__s1_147, __s1_147, 1, 0); \
	57200	float64_t __ret_147; \
	57201	__ret_147 = __s0_147 * __noswap_vgetq_lane_f64(__rev1_147, __p2_147); \
	57202	__ret_147; \
53891	57203	})
53892	57204	#endif
53893	57205
53894	57206	#ifdef __LITTLE_ENDIAN__
53895		#define vmuls_laneq_f32(__p0_136, __p1_136, __p2_136) __extension__ ({ \
53896		float32_t __s0_136 = __p0_136; \
53897		float32x4_t __s1_136 = __p1_136; \
53898		float32_t __ret_136; \
53899		__ret_136 = __s0_136 * vgetq_lane_f32(__s1_136, __p2_136); \
53900		__ret_136; \
	57207	#define vmuls_laneq_f32(__p0_148, __p1_148, __p2_148) __extension__ ({ \
	57208	float32_t __s0_148 = __p0_148; \
	57209	float32x4_t __s1_148 = __p1_148; \
	57210	float32_t __ret_148; \
	57211	__ret_148 = __s0_148 * vgetq_lane_f32(__s1_148, __p2_148); \
	57212	__ret_148; \
53901	57213	})
53902	57214	#else
53903		#define vmuls_laneq_f32(__p0_137, __p1_137, __p2_137) __extension__ ({ \
53904		float32_t __s0_137 = __p0_137; \
53905		float32x4_t __s1_137 = __p1_137; \
53906		float32x4_t __rev1_137; __rev1_137 = __builtin_shufflevector(__s1_137, __s1_137, 3, 2, 1, 0); \
53907		float32_t __ret_137; \
53908		__ret_137 = __s0_137 * __noswap_vgetq_lane_f32(__rev1_137, __p2_137); \
53909		__ret_137; \
	57215	#define vmuls_laneq_f32(__p0_149, __p1_149, __p2_149) __extension__ ({ \
	57216	float32_t __s0_149 = __p0_149; \
	57217	float32x4_t __s1_149 = __p1_149; \
	57218	float32x4_t __rev1_149; __rev1_149 = __builtin_shufflevector(__s1_149, __s1_149, 3, 2, 1, 0); \
	57219	float32_t __ret_149; \
	57220	__ret_149 = __s0_149 * __noswap_vgetq_lane_f32(__rev1_149, __p2_149); \
	57221	__ret_149; \
53910	57222	})
53911	57223	#endif
53912	57224
...	...	@@ -54779,39 +58091,39 @@ __ai float32_t __noswap_vmulxs_f32(float32_t __p0, float32_t __p1) {
54779	58091	#endif
54780	58092
54781	58093	#ifdef __LITTLE_ENDIAN__
54782		#define vmulxd_lane_f64(__p0_138, __p1_138, __p2_138) __extension__ ({ \
54783		float64_t __s0_138 = __p0_138; \
54784		float64x1_t __s1_138 = __p1_138; \
54785		float64_t __ret_138; \
54786		__ret_138 = vmulxd_f64(__s0_138, vget_lane_f64(__s1_138, __p2_138)); \
54787		__ret_138; \
	58094	#define vmulxd_lane_f64(__p0_150, __p1_150, __p2_150) __extension__ ({ \
	58095	float64_t __s0_150 = __p0_150; \
	58096	float64x1_t __s1_150 = __p1_150; \
	58097	float64_t __ret_150; \
	58098	__ret_150 = vmulxd_f64(__s0_150, vget_lane_f64(__s1_150, __p2_150)); \
	58099	__ret_150; \
54788	58100	})
54789	58101	#else
54790		#define vmulxd_lane_f64(__p0_139, __p1_139, __p2_139) __extension__ ({ \
54791		float64_t __s0_139 = __p0_139; \
54792		float64x1_t __s1_139 = __p1_139; \
54793		float64_t __ret_139; \
54794		__ret_139 = __noswap_vmulxd_f64(__s0_139, __noswap_vget_lane_f64(__s1_139, __p2_139)); \
54795		__ret_139; \
	58102	#define vmulxd_lane_f64(__p0_151, __p1_151, __p2_151) __extension__ ({ \
	58103	float64_t __s0_151 = __p0_151; \
	58104	float64x1_t __s1_151 = __p1_151; \
	58105	float64_t __ret_151; \
	58106	__ret_151 = __noswap_vmulxd_f64(__s0_151, __noswap_vget_lane_f64(__s1_151, __p2_151)); \
	58107	__ret_151; \
54796	58108	})
54797	58109	#endif
54798	58110
54799	58111	#ifdef __LITTLE_ENDIAN__
54800		#define vmulxs_lane_f32(__p0_140, __p1_140, __p2_140) __extension__ ({ \
54801		float32_t __s0_140 = __p0_140; \
54802		float32x2_t __s1_140 = __p1_140; \
54803		float32_t __ret_140; \
54804		__ret_140 = vmulxs_f32(__s0_140, vget_lane_f32(__s1_140, __p2_140)); \
54805		__ret_140; \
	58112	#define vmulxs_lane_f32(__p0_152, __p1_152, __p2_152) __extension__ ({ \
	58113	float32_t __s0_152 = __p0_152; \
	58114	float32x2_t __s1_152 = __p1_152; \
	58115	float32_t __ret_152; \
	58116	__ret_152 = vmulxs_f32(__s0_152, vget_lane_f32(__s1_152, __p2_152)); \
	58117	__ret_152; \
54806	58118	})
54807	58119	#else
54808		#define vmulxs_lane_f32(__p0_141, __p1_141, __p2_141) __extension__ ({ \
54809		float32_t __s0_141 = __p0_141; \
54810		float32x2_t __s1_141 = __p1_141; \
54811		float32x2_t __rev1_141; __rev1_141 = __builtin_shufflevector(__s1_141, __s1_141, 1, 0); \
54812		float32_t __ret_141; \
54813		__ret_141 = __noswap_vmulxs_f32(__s0_141, __noswap_vget_lane_f32(__rev1_141, __p2_141)); \
54814		__ret_141; \
	58120	#define vmulxs_lane_f32(__p0_153, __p1_153, __p2_153) __extension__ ({ \
	58121	float32_t __s0_153 = __p0_153; \
	58122	float32x2_t __s1_153 = __p1_153; \
	58123	float32x2_t __rev1_153; __rev1_153 = __builtin_shufflevector(__s1_153, __s1_153, 1, 0); \
	58124	float32_t __ret_153; \
	58125	__ret_153 = __noswap_vmulxs_f32(__s0_153, __noswap_vget_lane_f32(__rev1_153, __p2_153)); \
	58126	__ret_153; \
54815	58127	})
54816	58128	#endif
54817	58129
...	...	@@ -54878,40 +58190,40 @@ __ai float32_t __noswap_vmulxs_f32(float32_t __p0, float32_t __p1) {
54878	58190	#endif
54879	58191
54880	58192	#ifdef __LITTLE_ENDIAN__
54881		#define vmulxd_laneq_f64(__p0_142, __p1_142, __p2_142) __extension__ ({ \
54882		float64_t __s0_142 = __p0_142; \
54883		float64x2_t __s1_142 = __p1_142; \
54884		float64_t __ret_142; \
54885		__ret_142 = vmulxd_f64(__s0_142, vgetq_lane_f64(__s1_142, __p2_142)); \
54886		__ret_142; \
	58193	#define vmulxd_laneq_f64(__p0_154, __p1_154, __p2_154) __extension__ ({ \
	58194	float64_t __s0_154 = __p0_154; \
	58195	float64x2_t __s1_154 = __p1_154; \
	58196	float64_t __ret_154; \
	58197	__ret_154 = vmulxd_f64(__s0_154, vgetq_lane_f64(__s1_154, __p2_154)); \
	58198	__ret_154; \
54887	58199	})
54888	58200	#else
54889		#define vmulxd_laneq_f64(__p0_143, __p1_143, __p2_143) __extension__ ({ \
54890		float64_t __s0_143 = __p0_143; \
54891		float64x2_t __s1_143 = __p1_143; \
54892		float64x2_t __rev1_143; __rev1_143 = __builtin_shufflevector(__s1_143, __s1_143, 1, 0); \
54893		float64_t __ret_143; \
54894		__ret_143 = __noswap_vmulxd_f64(__s0_143, __noswap_vgetq_lane_f64(__rev1_143, __p2_143)); \
54895		__ret_143; \
	58201	#define vmulxd_laneq_f64(__p0_155, __p1_155, __p2_155) __extension__ ({ \
	58202	float64_t __s0_155 = __p0_155; \
	58203	float64x2_t __s1_155 = __p1_155; \
	58204	float64x2_t __rev1_155; __rev1_155 = __builtin_shufflevector(__s1_155, __s1_155, 1, 0); \
	58205	float64_t __ret_155; \
	58206	__ret_155 = __noswap_vmulxd_f64(__s0_155, __noswap_vgetq_lane_f64(__rev1_155, __p2_155)); \
	58207	__ret_155; \
54896	58208	})
54897	58209	#endif
54898	58210
54899	58211	#ifdef __LITTLE_ENDIAN__
54900		#define vmulxs_laneq_f32(__p0_144, __p1_144, __p2_144) __extension__ ({ \
54901		float32_t __s0_144 = __p0_144; \
54902		float32x4_t __s1_144 = __p1_144; \
54903		float32_t __ret_144; \
54904		__ret_144 = vmulxs_f32(__s0_144, vgetq_lane_f32(__s1_144, __p2_144)); \
54905		__ret_144; \
	58212	#define vmulxs_laneq_f32(__p0_156, __p1_156, __p2_156) __extension__ ({ \
	58213	float32_t __s0_156 = __p0_156; \
	58214	float32x4_t __s1_156 = __p1_156; \
	58215	float32_t __ret_156; \
	58216	__ret_156 = vmulxs_f32(__s0_156, vgetq_lane_f32(__s1_156, __p2_156)); \
	58217	__ret_156; \
54906	58218	})
54907	58219	#else
54908		#define vmulxs_laneq_f32(__p0_145, __p1_145, __p2_145) __extension__ ({ \
54909		float32_t __s0_145 = __p0_145; \
54910		float32x4_t __s1_145 = __p1_145; \
54911		float32x4_t __rev1_145; __rev1_145 = __builtin_shufflevector(__s1_145, __s1_145, 3, 2, 1, 0); \
54912		float32_t __ret_145; \
54913		__ret_145 = __noswap_vmulxs_f32(__s0_145, __noswap_vgetq_lane_f32(__rev1_145, __p2_145)); \
54914		__ret_145; \
	58220	#define vmulxs_laneq_f32(__p0_157, __p1_157, __p2_157) __extension__ ({ \
	58221	float32_t __s0_157 = __p0_157; \
	58222	float32x4_t __s1_157 = __p1_157; \
	58223	float32x4_t __rev1_157; __rev1_157 = __builtin_shufflevector(__s1_157, __s1_157, 3, 2, 1, 0); \
	58224	float32_t __ret_157; \
	58225	__ret_157 = __noswap_vmulxs_f32(__s0_157, __noswap_vgetq_lane_f32(__rev1_157, __p2_157)); \
	58226	__ret_157; \
54915	58227	})
54916	58228	#endif
54917	58229
...	...	@@ -56675,78 +59987,78 @@ __ai int16_t __noswap_vqdmulhh_s16(int16_t __p0, int16_t __p1) {
56675	59987	#endif
56676	59988
56677	59989	#ifdef __LITTLE_ENDIAN__
56678		#define vqdmulhs_lane_s32(__p0_146, __p1_146, __p2_146) __extension__ ({ \
56679		int32_t __s0_146 = __p0_146; \
56680		int32x2_t __s1_146 = __p1_146; \
56681		int32_t __ret_146; \
56682		__ret_146 = vqdmulhs_s32(__s0_146, vget_lane_s32(__s1_146, __p2_146)); \
56683		__ret_146; \
	59990	#define vqdmulhs_lane_s32(__p0_158, __p1_158, __p2_158) __extension__ ({ \
	59991	int32_t __s0_158 = __p0_158; \
	59992	int32x2_t __s1_158 = __p1_158; \
	59993	int32_t __ret_158; \
	59994	__ret_158 = vqdmulhs_s32(__s0_158, vget_lane_s32(__s1_158, __p2_158)); \
	59995	__ret_158; \
56684	59996	})
56685	59997	#else
56686		#define vqdmulhs_lane_s32(__p0_147, __p1_147, __p2_147) __extension__ ({ \
56687		int32_t __s0_147 = __p0_147; \
56688		int32x2_t __s1_147 = __p1_147; \
56689		int32x2_t __rev1_147; __rev1_147 = __builtin_shufflevector(__s1_147, __s1_147, 1, 0); \
56690		int32_t __ret_147; \
56691		__ret_147 = __noswap_vqdmulhs_s32(__s0_147, __noswap_vget_lane_s32(__rev1_147, __p2_147)); \
56692		__ret_147; \
	59998	#define vqdmulhs_lane_s32(__p0_159, __p1_159, __p2_159) __extension__ ({ \
	59999	int32_t __s0_159 = __p0_159; \
	60000	int32x2_t __s1_159 = __p1_159; \
	60001	int32x2_t __rev1_159; __rev1_159 = __builtin_shufflevector(__s1_159, __s1_159, 1, 0); \
	60002	int32_t __ret_159; \
	60003	__ret_159 = __noswap_vqdmulhs_s32(__s0_159, __noswap_vget_lane_s32(__rev1_159, __p2_159)); \
	60004	__ret_159; \
56693	60005	})
56694	60006	#endif
56695	60007
56696	60008	#ifdef __LITTLE_ENDIAN__
56697		#define vqdmulhh_lane_s16(__p0_148, __p1_148, __p2_148) __extension__ ({ \
56698		int16_t __s0_148 = __p0_148; \
56699		int16x4_t __s1_148 = __p1_148; \
56700		int16_t __ret_148; \
56701		__ret_148 = vqdmulhh_s16(__s0_148, vget_lane_s16(__s1_148, __p2_148)); \
56702		__ret_148; \
	60009	#define vqdmulhh_lane_s16(__p0_160, __p1_160, __p2_160) __extension__ ({ \
	60010	int16_t __s0_160 = __p0_160; \
	60011	int16x4_t __s1_160 = __p1_160; \
	60012	int16_t __ret_160; \
	60013	__ret_160 = vqdmulhh_s16(__s0_160, vget_lane_s16(__s1_160, __p2_160)); \
	60014	__ret_160; \
56703	60015	})
56704	60016	#else
56705		#define vqdmulhh_lane_s16(__p0_149, __p1_149, __p2_149) __extension__ ({ \
56706		int16_t __s0_149 = __p0_149; \
56707		int16x4_t __s1_149 = __p1_149; \
56708		int16x4_t __rev1_149; __rev1_149 = __builtin_shufflevector(__s1_149, __s1_149, 3, 2, 1, 0); \
56709		int16_t __ret_149; \
56710		__ret_149 = __noswap_vqdmulhh_s16(__s0_149, __noswap_vget_lane_s16(__rev1_149, __p2_149)); \
56711		__ret_149; \
	60017	#define vqdmulhh_lane_s16(__p0_161, __p1_161, __p2_161) __extension__ ({ \
	60018	int16_t __s0_161 = __p0_161; \
	60019	int16x4_t __s1_161 = __p1_161; \
	60020	int16x4_t __rev1_161; __rev1_161 = __builtin_shufflevector(__s1_161, __s1_161, 3, 2, 1, 0); \
	60021	int16_t __ret_161; \
	60022	__ret_161 = __noswap_vqdmulhh_s16(__s0_161, __noswap_vget_lane_s16(__rev1_161, __p2_161)); \
	60023	__ret_161; \
56712	60024	})
56713	60025	#endif
56714	60026
56715	60027	#ifdef __LITTLE_ENDIAN__
56716		#define vqdmulhs_laneq_s32(__p0_150, __p1_150, __p2_150) __extension__ ({ \
56717		int32_t __s0_150 = __p0_150; \
56718		int32x4_t __s1_150 = __p1_150; \
56719		int32_t __ret_150; \
56720		__ret_150 = vqdmulhs_s32(__s0_150, vgetq_lane_s32(__s1_150, __p2_150)); \
56721		__ret_150; \
	60028	#define vqdmulhs_laneq_s32(__p0_162, __p1_162, __p2_162) __extension__ ({ \
	60029	int32_t __s0_162 = __p0_162; \
	60030	int32x4_t __s1_162 = __p1_162; \
	60031	int32_t __ret_162; \
	60032	__ret_162 = vqdmulhs_s32(__s0_162, vgetq_lane_s32(__s1_162, __p2_162)); \
	60033	__ret_162; \
56722	60034	})
56723	60035	#else
56724		#define vqdmulhs_laneq_s32(__p0_151, __p1_151, __p2_151) __extension__ ({ \
56725		int32_t __s0_151 = __p0_151; \
56726		int32x4_t __s1_151 = __p1_151; \
56727		int32x4_t __rev1_151; __rev1_151 = __builtin_shufflevector(__s1_151, __s1_151, 3, 2, 1, 0); \
56728		int32_t __ret_151; \
56729		__ret_151 = __noswap_vqdmulhs_s32(__s0_151, __noswap_vgetq_lane_s32(__rev1_151, __p2_151)); \
56730		__ret_151; \
	60036	#define vqdmulhs_laneq_s32(__p0_163, __p1_163, __p2_163) __extension__ ({ \
	60037	int32_t __s0_163 = __p0_163; \
	60038	int32x4_t __s1_163 = __p1_163; \
	60039	int32x4_t __rev1_163; __rev1_163 = __builtin_shufflevector(__s1_163, __s1_163, 3, 2, 1, 0); \
	60040	int32_t __ret_163; \
	60041	__ret_163 = __noswap_vqdmulhs_s32(__s0_163, __noswap_vgetq_lane_s32(__rev1_163, __p2_163)); \
	60042	__ret_163; \
56731	60043	})
56732	60044	#endif
56733	60045
56734	60046	#ifdef __LITTLE_ENDIAN__
56735		#define vqdmulhh_laneq_s16(__p0_152, __p1_152, __p2_152) __extension__ ({ \
56736		int16_t __s0_152 = __p0_152; \
56737		int16x8_t __s1_152 = __p1_152; \
56738		int16_t __ret_152; \
56739		__ret_152 = vqdmulhh_s16(__s0_152, vgetq_lane_s16(__s1_152, __p2_152)); \
56740		__ret_152; \
	60047	#define vqdmulhh_laneq_s16(__p0_164, __p1_164, __p2_164) __extension__ ({ \
	60048	int16_t __s0_164 = __p0_164; \
	60049	int16x8_t __s1_164 = __p1_164; \
	60050	int16_t __ret_164; \
	60051	__ret_164 = vqdmulhh_s16(__s0_164, vgetq_lane_s16(__s1_164, __p2_164)); \
	60052	__ret_164; \
56741	60053	})
56742	60054	#else
56743		#define vqdmulhh_laneq_s16(__p0_153, __p1_153, __p2_153) __extension__ ({ \
56744		int16_t __s0_153 = __p0_153; \
56745		int16x8_t __s1_153 = __p1_153; \
56746		int16x8_t __rev1_153; __rev1_153 = __builtin_shufflevector(__s1_153, __s1_153, 7, 6, 5, 4, 3, 2, 1, 0); \
56747		int16_t __ret_153; \
56748		__ret_153 = __noswap_vqdmulhh_s16(__s0_153, __noswap_vgetq_lane_s16(__rev1_153, __p2_153)); \
56749		__ret_153; \
	60055	#define vqdmulhh_laneq_s16(__p0_165, __p1_165, __p2_165) __extension__ ({ \
	60056	int16_t __s0_165 = __p0_165; \
	60057	int16x8_t __s1_165 = __p1_165; \
	60058	int16x8_t __rev1_165; __rev1_165 = __builtin_shufflevector(__s1_165, __s1_165, 7, 6, 5, 4, 3, 2, 1, 0); \
	60059	int16_t __ret_165; \
	60060	__ret_165 = __noswap_vqdmulhh_s16(__s0_165, __noswap_vgetq_lane_s16(__rev1_165, __p2_165)); \
	60061	__ret_165; \
56750	60062	})
56751	60063	#endif
56752	60064
...	...	@@ -57023,78 +60335,78 @@ __ai int32x4_t vqdmull_high_n_s16(int16x8_t __p0, int16_t __p1) {
57023	60335	#endif
57024	60336
57025	60337	#ifdef __LITTLE_ENDIAN__
57026		#define vqdmulls_lane_s32(__p0_154, __p1_154, __p2_154) __extension__ ({ \
57027		int32_t __s0_154 = __p0_154; \
57028		int32x2_t __s1_154 = __p1_154; \
57029		int64_t __ret_154; \
57030		__ret_154 = vqdmulls_s32(__s0_154, vget_lane_s32(__s1_154, __p2_154)); \
57031		__ret_154; \
	60338	#define vqdmulls_lane_s32(__p0_166, __p1_166, __p2_166) __extension__ ({ \
	60339	int32_t __s0_166 = __p0_166; \
	60340	int32x2_t __s1_166 = __p1_166; \
	60341	int64_t __ret_166; \
	60342	__ret_166 = vqdmulls_s32(__s0_166, vget_lane_s32(__s1_166, __p2_166)); \
	60343	__ret_166; \
57032	60344	})
57033	60345	#else
57034		#define vqdmulls_lane_s32(__p0_155, __p1_155, __p2_155) __extension__ ({ \
57035		int32_t __s0_155 = __p0_155; \
57036		int32x2_t __s1_155 = __p1_155; \
57037		int32x2_t __rev1_155; __rev1_155 = __builtin_shufflevector(__s1_155, __s1_155, 1, 0); \
57038		int64_t __ret_155; \
57039		__ret_155 = __noswap_vqdmulls_s32(__s0_155, __noswap_vget_lane_s32(__rev1_155, __p2_155)); \
57040		__ret_155; \
	60346	#define vqdmulls_lane_s32(__p0_167, __p1_167, __p2_167) __extension__ ({ \
	60347	int32_t __s0_167 = __p0_167; \
	60348	int32x2_t __s1_167 = __p1_167; \
	60349	int32x2_t __rev1_167; __rev1_167 = __builtin_shufflevector(__s1_167, __s1_167, 1, 0); \
	60350	int64_t __ret_167; \
	60351	__ret_167 = __noswap_vqdmulls_s32(__s0_167, __noswap_vget_lane_s32(__rev1_167, __p2_167)); \
	60352	__ret_167; \
57041	60353	})
57042	60354	#endif
57043	60355
57044	60356	#ifdef __LITTLE_ENDIAN__
57045		#define vqdmullh_lane_s16(__p0_156, __p1_156, __p2_156) __extension__ ({ \
57046		int16_t __s0_156 = __p0_156; \
57047		int16x4_t __s1_156 = __p1_156; \
57048		int32_t __ret_156; \
57049		__ret_156 = vqdmullh_s16(__s0_156, vget_lane_s16(__s1_156, __p2_156)); \
57050		__ret_156; \
	60357	#define vqdmullh_lane_s16(__p0_168, __p1_168, __p2_168) __extension__ ({ \
	60358	int16_t __s0_168 = __p0_168; \
	60359	int16x4_t __s1_168 = __p1_168; \
	60360	int32_t __ret_168; \
	60361	__ret_168 = vqdmullh_s16(__s0_168, vget_lane_s16(__s1_168, __p2_168)); \
	60362	__ret_168; \
57051	60363	})
57052	60364	#else
57053		#define vqdmullh_lane_s16(__p0_157, __p1_157, __p2_157) __extension__ ({ \
57054		int16_t __s0_157 = __p0_157; \
57055		int16x4_t __s1_157 = __p1_157; \
57056		int16x4_t __rev1_157; __rev1_157 = __builtin_shufflevector(__s1_157, __s1_157, 3, 2, 1, 0); \
57057		int32_t __ret_157; \
57058		__ret_157 = __noswap_vqdmullh_s16(__s0_157, __noswap_vget_lane_s16(__rev1_157, __p2_157)); \
57059		__ret_157; \
	60365	#define vqdmullh_lane_s16(__p0_169, __p1_169, __p2_169) __extension__ ({ \
	60366	int16_t __s0_169 = __p0_169; \
	60367	int16x4_t __s1_169 = __p1_169; \
	60368	int16x4_t __rev1_169; __rev1_169 = __builtin_shufflevector(__s1_169, __s1_169, 3, 2, 1, 0); \
	60369	int32_t __ret_169; \
	60370	__ret_169 = __noswap_vqdmullh_s16(__s0_169, __noswap_vget_lane_s16(__rev1_169, __p2_169)); \
	60371	__ret_169; \
57060	60372	})
57061	60373	#endif
57062	60374
57063	60375	#ifdef __LITTLE_ENDIAN__
57064		#define vqdmulls_laneq_s32(__p0_158, __p1_158, __p2_158) __extension__ ({ \
57065		int32_t __s0_158 = __p0_158; \
57066		int32x4_t __s1_158 = __p1_158; \
57067		int64_t __ret_158; \
57068		__ret_158 = vqdmulls_s32(__s0_158, vgetq_lane_s32(__s1_158, __p2_158)); \
57069		__ret_158; \
	60376	#define vqdmulls_laneq_s32(__p0_170, __p1_170, __p2_170) __extension__ ({ \
	60377	int32_t __s0_170 = __p0_170; \
	60378	int32x4_t __s1_170 = __p1_170; \
	60379	int64_t __ret_170; \
	60380	__ret_170 = vqdmulls_s32(__s0_170, vgetq_lane_s32(__s1_170, __p2_170)); \
	60381	__ret_170; \
57070	60382	})
57071	60383	#else
57072		#define vqdmulls_laneq_s32(__p0_159, __p1_159, __p2_159) __extension__ ({ \
57073		int32_t __s0_159 = __p0_159; \
57074		int32x4_t __s1_159 = __p1_159; \
57075		int32x4_t __rev1_159; __rev1_159 = __builtin_shufflevector(__s1_159, __s1_159, 3, 2, 1, 0); \
57076		int64_t __ret_159; \
57077		__ret_159 = __noswap_vqdmulls_s32(__s0_159, __noswap_vgetq_lane_s32(__rev1_159, __p2_159)); \
57078		__ret_159; \
	60384	#define vqdmulls_laneq_s32(__p0_171, __p1_171, __p2_171) __extension__ ({ \
	60385	int32_t __s0_171 = __p0_171; \
	60386	int32x4_t __s1_171 = __p1_171; \
	60387	int32x4_t __rev1_171; __rev1_171 = __builtin_shufflevector(__s1_171, __s1_171, 3, 2, 1, 0); \
	60388	int64_t __ret_171; \
	60389	__ret_171 = __noswap_vqdmulls_s32(__s0_171, __noswap_vgetq_lane_s32(__rev1_171, __p2_171)); \
	60390	__ret_171; \
57079	60391	})
57080	60392	#endif
57081	60393
57082	60394	#ifdef __LITTLE_ENDIAN__
57083		#define vqdmullh_laneq_s16(__p0_160, __p1_160, __p2_160) __extension__ ({ \
57084		int16_t __s0_160 = __p0_160; \
57085		int16x8_t __s1_160 = __p1_160; \
57086		int32_t __ret_160; \
57087		__ret_160 = vqdmullh_s16(__s0_160, vgetq_lane_s16(__s1_160, __p2_160)); \
57088		__ret_160; \
	60395	#define vqdmullh_laneq_s16(__p0_172, __p1_172, __p2_172) __extension__ ({ \
	60396	int16_t __s0_172 = __p0_172; \
	60397	int16x8_t __s1_172 = __p1_172; \
	60398	int32_t __ret_172; \
	60399	__ret_172 = vqdmullh_s16(__s0_172, vgetq_lane_s16(__s1_172, __p2_172)); \
	60400	__ret_172; \
57089	60401	})
57090	60402	#else
57091		#define vqdmullh_laneq_s16(__p0_161, __p1_161, __p2_161) __extension__ ({ \
57092		int16_t __s0_161 = __p0_161; \
57093		int16x8_t __s1_161 = __p1_161; \
57094		int16x8_t __rev1_161; __rev1_161 = __builtin_shufflevector(__s1_161, __s1_161, 7, 6, 5, 4, 3, 2, 1, 0); \
57095		int32_t __ret_161; \
57096		__ret_161 = __noswap_vqdmullh_s16(__s0_161, __noswap_vgetq_lane_s16(__rev1_161, __p2_161)); \
57097		__ret_161; \
	60403	#define vqdmullh_laneq_s16(__p0_173, __p1_173, __p2_173) __extension__ ({ \
	60404	int16_t __s0_173 = __p0_173; \
	60405	int16x8_t __s1_173 = __p1_173; \
	60406	int16x8_t __rev1_173; __rev1_173 = __builtin_shufflevector(__s1_173, __s1_173, 7, 6, 5, 4, 3, 2, 1, 0); \
	60407	int32_t __ret_173; \
	60408	__ret_173 = __noswap_vqdmullh_s16(__s0_173, __noswap_vgetq_lane_s16(__rev1_173, __p2_173)); \
	60409	__ret_173; \
57098	60410	})
57099	60411	#endif
57100	60412
...	...	@@ -57544,78 +60856,78 @@ __ai int16_t __noswap_vqrdmulhh_s16(int16_t __p0, int16_t __p1) {
57544	60856	#endif
57545	60857
57546	60858	#ifdef __LITTLE_ENDIAN__
57547		#define vqrdmulhs_lane_s32(__p0_162, __p1_162, __p2_162) __extension__ ({ \
57548		int32_t __s0_162 = __p0_162; \
57549		int32x2_t __s1_162 = __p1_162; \
57550		int32_t __ret_162; \
57551		__ret_162 = vqrdmulhs_s32(__s0_162, vget_lane_s32(__s1_162, __p2_162)); \
57552		__ret_162; \
	60859	#define vqrdmulhs_lane_s32(__p0_174, __p1_174, __p2_174) __extension__ ({ \
	60860	int32_t __s0_174 = __p0_174; \
	60861	int32x2_t __s1_174 = __p1_174; \
	60862	int32_t __ret_174; \
	60863	__ret_174 = vqrdmulhs_s32(__s0_174, vget_lane_s32(__s1_174, __p2_174)); \
	60864	__ret_174; \
57553	60865	})
57554	60866	#else
57555		#define vqrdmulhs_lane_s32(__p0_163, __p1_163, __p2_163) __extension__ ({ \
57556		int32_t __s0_163 = __p0_163; \
57557		int32x2_t __s1_163 = __p1_163; \
57558		int32x2_t __rev1_163; __rev1_163 = __builtin_shufflevector(__s1_163, __s1_163, 1, 0); \
57559		int32_t __ret_163; \
57560		__ret_163 = __noswap_vqrdmulhs_s32(__s0_163, __noswap_vget_lane_s32(__rev1_163, __p2_163)); \
57561		__ret_163; \
	60867	#define vqrdmulhs_lane_s32(__p0_175, __p1_175, __p2_175) __extension__ ({ \
	60868	int32_t __s0_175 = __p0_175; \
	60869	int32x2_t __s1_175 = __p1_175; \
	60870	int32x2_t __rev1_175; __rev1_175 = __builtin_shufflevector(__s1_175, __s1_175, 1, 0); \
	60871	int32_t __ret_175; \
	60872	__ret_175 = __noswap_vqrdmulhs_s32(__s0_175, __noswap_vget_lane_s32(__rev1_175, __p2_175)); \
	60873	__ret_175; \
57562	60874	})
57563	60875	#endif
57564	60876
57565	60877	#ifdef __LITTLE_ENDIAN__
57566		#define vqrdmulhh_lane_s16(__p0_164, __p1_164, __p2_164) __extension__ ({ \
57567		int16_t __s0_164 = __p0_164; \
57568		int16x4_t __s1_164 = __p1_164; \
57569		int16_t __ret_164; \
57570		__ret_164 = vqrdmulhh_s16(__s0_164, vget_lane_s16(__s1_164, __p2_164)); \
57571		__ret_164; \
	60878	#define vqrdmulhh_lane_s16(__p0_176, __p1_176, __p2_176) __extension__ ({ \
	60879	int16_t __s0_176 = __p0_176; \
	60880	int16x4_t __s1_176 = __p1_176; \
	60881	int16_t __ret_176; \
	60882	__ret_176 = vqrdmulhh_s16(__s0_176, vget_lane_s16(__s1_176, __p2_176)); \
	60883	__ret_176; \
57572	60884	})
57573	60885	#else
57574		#define vqrdmulhh_lane_s16(__p0_165, __p1_165, __p2_165) __extension__ ({ \
57575		int16_t __s0_165 = __p0_165; \
57576		int16x4_t __s1_165 = __p1_165; \
57577		int16x4_t __rev1_165; __rev1_165 = __builtin_shufflevector(__s1_165, __s1_165, 3, 2, 1, 0); \
57578		int16_t __ret_165; \
57579		__ret_165 = __noswap_vqrdmulhh_s16(__s0_165, __noswap_vget_lane_s16(__rev1_165, __p2_165)); \
57580		__ret_165; \
	60886	#define vqrdmulhh_lane_s16(__p0_177, __p1_177, __p2_177) __extension__ ({ \
	60887	int16_t __s0_177 = __p0_177; \
	60888	int16x4_t __s1_177 = __p1_177; \
	60889	int16x4_t __rev1_177; __rev1_177 = __builtin_shufflevector(__s1_177, __s1_177, 3, 2, 1, 0); \
	60890	int16_t __ret_177; \
	60891	__ret_177 = __noswap_vqrdmulhh_s16(__s0_177, __noswap_vget_lane_s16(__rev1_177, __p2_177)); \
	60892	__ret_177; \
57581	60893	})
57582	60894	#endif
57583	60895
57584	60896	#ifdef __LITTLE_ENDIAN__
57585		#define vqrdmulhs_laneq_s32(__p0_166, __p1_166, __p2_166) __extension__ ({ \
57586		int32_t __s0_166 = __p0_166; \
57587		int32x4_t __s1_166 = __p1_166; \
57588		int32_t __ret_166; \
57589		__ret_166 = vqrdmulhs_s32(__s0_166, vgetq_lane_s32(__s1_166, __p2_166)); \
57590		__ret_166; \
	60897	#define vqrdmulhs_laneq_s32(__p0_178, __p1_178, __p2_178) __extension__ ({ \
	60898	int32_t __s0_178 = __p0_178; \
	60899	int32x4_t __s1_178 = __p1_178; \
	60900	int32_t __ret_178; \
	60901	__ret_178 = vqrdmulhs_s32(__s0_178, vgetq_lane_s32(__s1_178, __p2_178)); \
	60902	__ret_178; \
57591	60903	})
57592	60904	#else
57593		#define vqrdmulhs_laneq_s32(__p0_167, __p1_167, __p2_167) __extension__ ({ \
57594		int32_t __s0_167 = __p0_167; \
57595		int32x4_t __s1_167 = __p1_167; \
57596		int32x4_t __rev1_167; __rev1_167 = __builtin_shufflevector(__s1_167, __s1_167, 3, 2, 1, 0); \
57597		int32_t __ret_167; \
57598		__ret_167 = __noswap_vqrdmulhs_s32(__s0_167, __noswap_vgetq_lane_s32(__rev1_167, __p2_167)); \
57599		__ret_167; \
	60905	#define vqrdmulhs_laneq_s32(__p0_179, __p1_179, __p2_179) __extension__ ({ \
	60906	int32_t __s0_179 = __p0_179; \
	60907	int32x4_t __s1_179 = __p1_179; \
	60908	int32x4_t __rev1_179; __rev1_179 = __builtin_shufflevector(__s1_179, __s1_179, 3, 2, 1, 0); \
	60909	int32_t __ret_179; \
	60910	__ret_179 = __noswap_vqrdmulhs_s32(__s0_179, __noswap_vgetq_lane_s32(__rev1_179, __p2_179)); \
	60911	__ret_179; \
57600	60912	})
57601	60913	#endif
57602	60914
57603	60915	#ifdef __LITTLE_ENDIAN__
57604		#define vqrdmulhh_laneq_s16(__p0_168, __p1_168, __p2_168) __extension__ ({ \
57605		int16_t __s0_168 = __p0_168; \
57606		int16x8_t __s1_168 = __p1_168; \
57607		int16_t __ret_168; \
57608		__ret_168 = vqrdmulhh_s16(__s0_168, vgetq_lane_s16(__s1_168, __p2_168)); \
57609		__ret_168; \
	60916	#define vqrdmulhh_laneq_s16(__p0_180, __p1_180, __p2_180) __extension__ ({ \
	60917	int16_t __s0_180 = __p0_180; \
	60918	int16x8_t __s1_180 = __p1_180; \
	60919	int16_t __ret_180; \
	60920	__ret_180 = vqrdmulhh_s16(__s0_180, vgetq_lane_s16(__s1_180, __p2_180)); \
	60921	__ret_180; \
57610	60922	})
57611	60923	#else
57612		#define vqrdmulhh_laneq_s16(__p0_169, __p1_169, __p2_169) __extension__ ({ \
57613		int16_t __s0_169 = __p0_169; \
57614		int16x8_t __s1_169 = __p1_169; \
57615		int16x8_t __rev1_169; __rev1_169 = __builtin_shufflevector(__s1_169, __s1_169, 7, 6, 5, 4, 3, 2, 1, 0); \
57616		int16_t __ret_169; \
57617		__ret_169 = __noswap_vqrdmulhh_s16(__s0_169, __noswap_vgetq_lane_s16(__rev1_169, __p2_169)); \
57618		__ret_169; \
	60924	#define vqrdmulhh_laneq_s16(__p0_181, __p1_181, __p2_181) __extension__ ({ \
	60925	int16_t __s0_181 = __p0_181; \
	60926	int16x8_t __s1_181 = __p1_181; \
	60927	int16x8_t __rev1_181; __rev1_181 = __builtin_shufflevector(__s1_181, __s1_181, 7, 6, 5, 4, 3, 2, 1, 0); \
	60928	int16_t __ret_181; \
	60929	__ret_181 = __noswap_vqrdmulhh_s16(__s0_181, __noswap_vgetq_lane_s16(__rev1_181, __p2_181)); \
	60930	__ret_181; \
57619	60931	})
57620	60932	#endif
57621	60933
...	...	@@ -57816,128 +61128,128 @@ __ai int16_t vqrshlh_s16(int16_t __p0, int16_t __p1) {
57816	61128	#endif
57817	61129
57818	61130	#ifdef __LITTLE_ENDIAN__
57819		#define vqrshrn_high_n_u32(__p0_170, __p1_170, __p2_170) __extension__ ({ \
57820		uint16x4_t __s0_170 = __p0_170; \
57821		uint32x4_t __s1_170 = __p1_170; \
57822		uint16x8_t __ret_170; \
57823		__ret_170 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_170), (uint16x4_t)(vqrshrn_n_u32(__s1_170, __p2_170)))); \
57824		__ret_170; \
	61131	#define vqrshrn_high_n_u32(__p0_182, __p1_182, __p2_182) __extension__ ({ \
	61132	uint16x4_t __s0_182 = __p0_182; \
	61133	uint32x4_t __s1_182 = __p1_182; \
	61134	uint16x8_t __ret_182; \
	61135	__ret_182 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_182), (uint16x4_t)(vqrshrn_n_u32(__s1_182, __p2_182)))); \
	61136	__ret_182; \
57825	61137	})
57826	61138	#else
57827		#define vqrshrn_high_n_u32(__p0_171, __p1_171, __p2_171) __extension__ ({ \
57828		uint16x4_t __s0_171 = __p0_171; \
57829		uint32x4_t __s1_171 = __p1_171; \
57830		uint16x4_t __rev0_171; __rev0_171 = __builtin_shufflevector(__s0_171, __s0_171, 3, 2, 1, 0); \
57831		uint32x4_t __rev1_171; __rev1_171 = __builtin_shufflevector(__s1_171, __s1_171, 3, 2, 1, 0); \
57832		uint16x8_t __ret_171; \
57833		__ret_171 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_171), (uint16x4_t)(__noswap_vqrshrn_n_u32(__rev1_171, __p2_171)))); \
57834		__ret_171 = __builtin_shufflevector(__ret_171, __ret_171, 7, 6, 5, 4, 3, 2, 1, 0); \
57835		__ret_171; \
	61139	#define vqrshrn_high_n_u32(__p0_183, __p1_183, __p2_183) __extension__ ({ \
	61140	uint16x4_t __s0_183 = __p0_183; \
	61141	uint32x4_t __s1_183 = __p1_183; \
	61142	uint16x4_t __rev0_183; __rev0_183 = __builtin_shufflevector(__s0_183, __s0_183, 3, 2, 1, 0); \
	61143	uint32x4_t __rev1_183; __rev1_183 = __builtin_shufflevector(__s1_183, __s1_183, 3, 2, 1, 0); \
	61144	uint16x8_t __ret_183; \
	61145	__ret_183 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_183), (uint16x4_t)(__noswap_vqrshrn_n_u32(__rev1_183, __p2_183)))); \
	61146	__ret_183 = __builtin_shufflevector(__ret_183, __ret_183, 7, 6, 5, 4, 3, 2, 1, 0); \
	61147	__ret_183; \
57836	61148	})
57837	61149	#endif
57838	61150
57839	61151	#ifdef __LITTLE_ENDIAN__
57840		#define vqrshrn_high_n_u64(__p0_172, __p1_172, __p2_172) __extension__ ({ \
57841		uint32x2_t __s0_172 = __p0_172; \
57842		uint64x2_t __s1_172 = __p1_172; \
57843		uint32x4_t __ret_172; \
57844		__ret_172 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_172), (uint32x2_t)(vqrshrn_n_u64(__s1_172, __p2_172)))); \
57845		__ret_172; \
	61152	#define vqrshrn_high_n_u64(__p0_184, __p1_184, __p2_184) __extension__ ({ \
	61153	uint32x2_t __s0_184 = __p0_184; \
	61154	uint64x2_t __s1_184 = __p1_184; \
	61155	uint32x4_t __ret_184; \
	61156	__ret_184 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_184), (uint32x2_t)(vqrshrn_n_u64(__s1_184, __p2_184)))); \
	61157	__ret_184; \
57846	61158	})
57847	61159	#else
57848		#define vqrshrn_high_n_u64(__p0_173, __p1_173, __p2_173) __extension__ ({ \
57849		uint32x2_t __s0_173 = __p0_173; \
57850		uint64x2_t __s1_173 = __p1_173; \
57851		uint32x2_t __rev0_173; __rev0_173 = __builtin_shufflevector(__s0_173, __s0_173, 1, 0); \
57852		uint64x2_t __rev1_173; __rev1_173 = __builtin_shufflevector(__s1_173, __s1_173, 1, 0); \
57853		uint32x4_t __ret_173; \
57854		__ret_173 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_173), (uint32x2_t)(__noswap_vqrshrn_n_u64(__rev1_173, __p2_173)))); \
57855		__ret_173 = __builtin_shufflevector(__ret_173, __ret_173, 3, 2, 1, 0); \
57856		__ret_173; \
	61160	#define vqrshrn_high_n_u64(__p0_185, __p1_185, __p2_185) __extension__ ({ \
	61161	uint32x2_t __s0_185 = __p0_185; \
	61162	uint64x2_t __s1_185 = __p1_185; \
	61163	uint32x2_t __rev0_185; __rev0_185 = __builtin_shufflevector(__s0_185, __s0_185, 1, 0); \
	61164	uint64x2_t __rev1_185; __rev1_185 = __builtin_shufflevector(__s1_185, __s1_185, 1, 0); \
	61165	uint32x4_t __ret_185; \
	61166	__ret_185 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_185), (uint32x2_t)(__noswap_vqrshrn_n_u64(__rev1_185, __p2_185)))); \
	61167	__ret_185 = __builtin_shufflevector(__ret_185, __ret_185, 3, 2, 1, 0); \
	61168	__ret_185; \
57857	61169	})
57858	61170	#endif
57859	61171
57860	61172	#ifdef __LITTLE_ENDIAN__
57861		#define vqrshrn_high_n_u16(__p0_174, __p1_174, __p2_174) __extension__ ({ \
57862		uint8x8_t __s0_174 = __p0_174; \
57863		uint16x8_t __s1_174 = __p1_174; \
57864		uint8x16_t __ret_174; \
57865		__ret_174 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_174), (uint8x8_t)(vqrshrn_n_u16(__s1_174, __p2_174)))); \
57866		__ret_174; \
	61173	#define vqrshrn_high_n_u16(__p0_186, __p1_186, __p2_186) __extension__ ({ \
	61174	uint8x8_t __s0_186 = __p0_186; \
	61175	uint16x8_t __s1_186 = __p1_186; \
	61176	uint8x16_t __ret_186; \
	61177	__ret_186 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_186), (uint8x8_t)(vqrshrn_n_u16(__s1_186, __p2_186)))); \
	61178	__ret_186; \
57867	61179	})
57868	61180	#else
57869		#define vqrshrn_high_n_u16(__p0_175, __p1_175, __p2_175) __extension__ ({ \
57870		uint8x8_t __s0_175 = __p0_175; \
57871		uint16x8_t __s1_175 = __p1_175; \
57872		uint8x8_t __rev0_175; __rev0_175 = __builtin_shufflevector(__s0_175, __s0_175, 7, 6, 5, 4, 3, 2, 1, 0); \
57873		uint16x8_t __rev1_175; __rev1_175 = __builtin_shufflevector(__s1_175, __s1_175, 7, 6, 5, 4, 3, 2, 1, 0); \
57874		uint8x16_t __ret_175; \
57875		__ret_175 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_175), (uint8x8_t)(__noswap_vqrshrn_n_u16(__rev1_175, __p2_175)))); \
57876		__ret_175 = __builtin_shufflevector(__ret_175, __ret_175, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
57877		__ret_175; \
	61181	#define vqrshrn_high_n_u16(__p0_187, __p1_187, __p2_187) __extension__ ({ \
	61182	uint8x8_t __s0_187 = __p0_187; \
	61183	uint16x8_t __s1_187 = __p1_187; \
	61184	uint8x8_t __rev0_187; __rev0_187 = __builtin_shufflevector(__s0_187, __s0_187, 7, 6, 5, 4, 3, 2, 1, 0); \
	61185	uint16x8_t __rev1_187; __rev1_187 = __builtin_shufflevector(__s1_187, __s1_187, 7, 6, 5, 4, 3, 2, 1, 0); \
	61186	uint8x16_t __ret_187; \
	61187	__ret_187 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_187), (uint8x8_t)(__noswap_vqrshrn_n_u16(__rev1_187, __p2_187)))); \
	61188	__ret_187 = __builtin_shufflevector(__ret_187, __ret_187, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	61189	__ret_187; \
57878	61190	})
57879	61191	#endif
57880	61192
57881	61193	#ifdef __LITTLE_ENDIAN__
57882		#define vqrshrn_high_n_s32(__p0_176, __p1_176, __p2_176) __extension__ ({ \
57883		int16x4_t __s0_176 = __p0_176; \
57884		int32x4_t __s1_176 = __p1_176; \
57885		int16x8_t __ret_176; \
57886		__ret_176 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_176), (int16x4_t)(vqrshrn_n_s32(__s1_176, __p2_176)))); \
57887		__ret_176; \
	61194	#define vqrshrn_high_n_s32(__p0_188, __p1_188, __p2_188) __extension__ ({ \
	61195	int16x4_t __s0_188 = __p0_188; \
	61196	int32x4_t __s1_188 = __p1_188; \
	61197	int16x8_t __ret_188; \
	61198	__ret_188 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_188), (int16x4_t)(vqrshrn_n_s32(__s1_188, __p2_188)))); \
	61199	__ret_188; \
57888	61200	})
57889	61201	#else
57890		#define vqrshrn_high_n_s32(__p0_177, __p1_177, __p2_177) __extension__ ({ \
57891		int16x4_t __s0_177 = __p0_177; \
57892		int32x4_t __s1_177 = __p1_177; \
57893		int16x4_t __rev0_177; __rev0_177 = __builtin_shufflevector(__s0_177, __s0_177, 3, 2, 1, 0); \
57894		int32x4_t __rev1_177; __rev1_177 = __builtin_shufflevector(__s1_177, __s1_177, 3, 2, 1, 0); \
57895		int16x8_t __ret_177; \
57896		__ret_177 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_177), (int16x4_t)(__noswap_vqrshrn_n_s32(__rev1_177, __p2_177)))); \
57897		__ret_177 = __builtin_shufflevector(__ret_177, __ret_177, 7, 6, 5, 4, 3, 2, 1, 0); \
57898		__ret_177; \
	61202	#define vqrshrn_high_n_s32(__p0_189, __p1_189, __p2_189) __extension__ ({ \
	61203	int16x4_t __s0_189 = __p0_189; \
	61204	int32x4_t __s1_189 = __p1_189; \
	61205	int16x4_t __rev0_189; __rev0_189 = __builtin_shufflevector(__s0_189, __s0_189, 3, 2, 1, 0); \
	61206	int32x4_t __rev1_189; __rev1_189 = __builtin_shufflevector(__s1_189, __s1_189, 3, 2, 1, 0); \
	61207	int16x8_t __ret_189; \
	61208	__ret_189 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_189), (int16x4_t)(__noswap_vqrshrn_n_s32(__rev1_189, __p2_189)))); \
	61209	__ret_189 = __builtin_shufflevector(__ret_189, __ret_189, 7, 6, 5, 4, 3, 2, 1, 0); \
	61210	__ret_189; \
57899	61211	})
57900	61212	#endif
57901	61213
57902	61214	#ifdef __LITTLE_ENDIAN__
57903		#define vqrshrn_high_n_s64(__p0_178, __p1_178, __p2_178) __extension__ ({ \
57904		int32x2_t __s0_178 = __p0_178; \
57905		int64x2_t __s1_178 = __p1_178; \
57906		int32x4_t __ret_178; \
57907		__ret_178 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_178), (int32x2_t)(vqrshrn_n_s64(__s1_178, __p2_178)))); \
57908		__ret_178; \
	61215	#define vqrshrn_high_n_s64(__p0_190, __p1_190, __p2_190) __extension__ ({ \
	61216	int32x2_t __s0_190 = __p0_190; \
	61217	int64x2_t __s1_190 = __p1_190; \
	61218	int32x4_t __ret_190; \
	61219	__ret_190 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_190), (int32x2_t)(vqrshrn_n_s64(__s1_190, __p2_190)))); \
	61220	__ret_190; \
57909	61221	})
57910	61222	#else
57911		#define vqrshrn_high_n_s64(__p0_179, __p1_179, __p2_179) __extension__ ({ \
57912		int32x2_t __s0_179 = __p0_179; \
57913		int64x2_t __s1_179 = __p1_179; \
57914		int32x2_t __rev0_179; __rev0_179 = __builtin_shufflevector(__s0_179, __s0_179, 1, 0); \
57915		int64x2_t __rev1_179; __rev1_179 = __builtin_shufflevector(__s1_179, __s1_179, 1, 0); \
57916		int32x4_t __ret_179; \
57917		__ret_179 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_179), (int32x2_t)(__noswap_vqrshrn_n_s64(__rev1_179, __p2_179)))); \
57918		__ret_179 = __builtin_shufflevector(__ret_179, __ret_179, 3, 2, 1, 0); \
57919		__ret_179; \
	61223	#define vqrshrn_high_n_s64(__p0_191, __p1_191, __p2_191) __extension__ ({ \
	61224	int32x2_t __s0_191 = __p0_191; \
	61225	int64x2_t __s1_191 = __p1_191; \
	61226	int32x2_t __rev0_191; __rev0_191 = __builtin_shufflevector(__s0_191, __s0_191, 1, 0); \
	61227	int64x2_t __rev1_191; __rev1_191 = __builtin_shufflevector(__s1_191, __s1_191, 1, 0); \
	61228	int32x4_t __ret_191; \
	61229	__ret_191 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_191), (int32x2_t)(__noswap_vqrshrn_n_s64(__rev1_191, __p2_191)))); \
	61230	__ret_191 = __builtin_shufflevector(__ret_191, __ret_191, 3, 2, 1, 0); \
	61231	__ret_191; \
57920	61232	})
57921	61233	#endif
57922	61234
57923	61235	#ifdef __LITTLE_ENDIAN__
57924		#define vqrshrn_high_n_s16(__p0_180, __p1_180, __p2_180) __extension__ ({ \
57925		int8x8_t __s0_180 = __p0_180; \
57926		int16x8_t __s1_180 = __p1_180; \
57927		int8x16_t __ret_180; \
57928		__ret_180 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_180), (int8x8_t)(vqrshrn_n_s16(__s1_180, __p2_180)))); \
57929		__ret_180; \
	61236	#define vqrshrn_high_n_s16(__p0_192, __p1_192, __p2_192) __extension__ ({ \
	61237	int8x8_t __s0_192 = __p0_192; \
	61238	int16x8_t __s1_192 = __p1_192; \
	61239	int8x16_t __ret_192; \
	61240	__ret_192 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_192), (int8x8_t)(vqrshrn_n_s16(__s1_192, __p2_192)))); \
	61241	__ret_192; \
57930	61242	})
57931	61243	#else
57932		#define vqrshrn_high_n_s16(__p0_181, __p1_181, __p2_181) __extension__ ({ \
57933		int8x8_t __s0_181 = __p0_181; \
57934		int16x8_t __s1_181 = __p1_181; \
57935		int8x8_t __rev0_181; __rev0_181 = __builtin_shufflevector(__s0_181, __s0_181, 7, 6, 5, 4, 3, 2, 1, 0); \
57936		int16x8_t __rev1_181; __rev1_181 = __builtin_shufflevector(__s1_181, __s1_181, 7, 6, 5, 4, 3, 2, 1, 0); \
57937		int8x16_t __ret_181; \
57938		__ret_181 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_181), (int8x8_t)(__noswap_vqrshrn_n_s16(__rev1_181, __p2_181)))); \
57939		__ret_181 = __builtin_shufflevector(__ret_181, __ret_181, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
57940		__ret_181; \
	61244	#define vqrshrn_high_n_s16(__p0_193, __p1_193, __p2_193) __extension__ ({ \
	61245	int8x8_t __s0_193 = __p0_193; \
	61246	int16x8_t __s1_193 = __p1_193; \
	61247	int8x8_t __rev0_193; __rev0_193 = __builtin_shufflevector(__s0_193, __s0_193, 7, 6, 5, 4, 3, 2, 1, 0); \
	61248	int16x8_t __rev1_193; __rev1_193 = __builtin_shufflevector(__s1_193, __s1_193, 7, 6, 5, 4, 3, 2, 1, 0); \
	61249	int8x16_t __ret_193; \
	61250	__ret_193 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_193), (int8x8_t)(__noswap_vqrshrn_n_s16(__rev1_193, __p2_193)))); \
	61251	__ret_193 = __builtin_shufflevector(__ret_193, __ret_193, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	61252	__ret_193; \
57941	61253	})
57942	61254	#endif
57943	61255
...	...	@@ -58038,65 +61350,65 @@ __ai int16_t vqrshlh_s16(int16_t __p0, int16_t __p1) {
58038	61350	#endif
58039	61351
58040	61352	#ifdef __LITTLE_ENDIAN__
58041		#define vqrshrun_high_n_s32(__p0_182, __p1_182, __p2_182) __extension__ ({ \
58042		int16x4_t __s0_182 = __p0_182; \
58043		int32x4_t __s1_182 = __p1_182; \
58044		int16x8_t __ret_182; \
58045		__ret_182 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_182), (int16x4_t)(vqrshrun_n_s32(__s1_182, __p2_182)))); \
58046		__ret_182; \
	61353	#define vqrshrun_high_n_s32(__p0_194, __p1_194, __p2_194) __extension__ ({ \
	61354	int16x4_t __s0_194 = __p0_194; \
	61355	int32x4_t __s1_194 = __p1_194; \
	61356	int16x8_t __ret_194; \
	61357	__ret_194 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_194), (int16x4_t)(vqrshrun_n_s32(__s1_194, __p2_194)))); \
	61358	__ret_194; \
58047	61359	})
58048	61360	#else
58049		#define vqrshrun_high_n_s32(__p0_183, __p1_183, __p2_183) __extension__ ({ \
58050		int16x4_t __s0_183 = __p0_183; \
58051		int32x4_t __s1_183 = __p1_183; \
58052		int16x4_t __rev0_183; __rev0_183 = __builtin_shufflevector(__s0_183, __s0_183, 3, 2, 1, 0); \
58053		int32x4_t __rev1_183; __rev1_183 = __builtin_shufflevector(__s1_183, __s1_183, 3, 2, 1, 0); \
58054		int16x8_t __ret_183; \
58055		__ret_183 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_183), (int16x4_t)(__noswap_vqrshrun_n_s32(__rev1_183, __p2_183)))); \
58056		__ret_183 = __builtin_shufflevector(__ret_183, __ret_183, 7, 6, 5, 4, 3, 2, 1, 0); \
58057		__ret_183; \
	61361	#define vqrshrun_high_n_s32(__p0_195, __p1_195, __p2_195) __extension__ ({ \
	61362	int16x4_t __s0_195 = __p0_195; \
	61363	int32x4_t __s1_195 = __p1_195; \
	61364	int16x4_t __rev0_195; __rev0_195 = __builtin_shufflevector(__s0_195, __s0_195, 3, 2, 1, 0); \
	61365	int32x4_t __rev1_195; __rev1_195 = __builtin_shufflevector(__s1_195, __s1_195, 3, 2, 1, 0); \
	61366	int16x8_t __ret_195; \
	61367	__ret_195 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_195), (int16x4_t)(__noswap_vqrshrun_n_s32(__rev1_195, __p2_195)))); \
	61368	__ret_195 = __builtin_shufflevector(__ret_195, __ret_195, 7, 6, 5, 4, 3, 2, 1, 0); \
	61369	__ret_195; \
58058	61370	})
58059	61371	#endif
58060	61372
58061	61373	#ifdef __LITTLE_ENDIAN__
58062		#define vqrshrun_high_n_s64(__p0_184, __p1_184, __p2_184) __extension__ ({ \
58063		int32x2_t __s0_184 = __p0_184; \
58064		int64x2_t __s1_184 = __p1_184; \
58065		int32x4_t __ret_184; \
58066		__ret_184 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_184), (int32x2_t)(vqrshrun_n_s64(__s1_184, __p2_184)))); \
58067		__ret_184; \
	61374	#define vqrshrun_high_n_s64(__p0_196, __p1_196, __p2_196) __extension__ ({ \
	61375	int32x2_t __s0_196 = __p0_196; \
	61376	int64x2_t __s1_196 = __p1_196; \
	61377	int32x4_t __ret_196; \
	61378	__ret_196 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_196), (int32x2_t)(vqrshrun_n_s64(__s1_196, __p2_196)))); \
	61379	__ret_196; \
58068	61380	})
58069	61381	#else
58070		#define vqrshrun_high_n_s64(__p0_185, __p1_185, __p2_185) __extension__ ({ \
58071		int32x2_t __s0_185 = __p0_185; \
58072		int64x2_t __s1_185 = __p1_185; \
58073		int32x2_t __rev0_185; __rev0_185 = __builtin_shufflevector(__s0_185, __s0_185, 1, 0); \
58074		int64x2_t __rev1_185; __rev1_185 = __builtin_shufflevector(__s1_185, __s1_185, 1, 0); \
58075		int32x4_t __ret_185; \
58076		__ret_185 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_185), (int32x2_t)(__noswap_vqrshrun_n_s64(__rev1_185, __p2_185)))); \
58077		__ret_185 = __builtin_shufflevector(__ret_185, __ret_185, 3, 2, 1, 0); \
58078		__ret_185; \
	61382	#define vqrshrun_high_n_s64(__p0_197, __p1_197, __p2_197) __extension__ ({ \
	61383	int32x2_t __s0_197 = __p0_197; \
	61384	int64x2_t __s1_197 = __p1_197; \
	61385	int32x2_t __rev0_197; __rev0_197 = __builtin_shufflevector(__s0_197, __s0_197, 1, 0); \
	61386	int64x2_t __rev1_197; __rev1_197 = __builtin_shufflevector(__s1_197, __s1_197, 1, 0); \
	61387	int32x4_t __ret_197; \
	61388	__ret_197 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_197), (int32x2_t)(__noswap_vqrshrun_n_s64(__rev1_197, __p2_197)))); \
	61389	__ret_197 = __builtin_shufflevector(__ret_197, __ret_197, 3, 2, 1, 0); \
	61390	__ret_197; \
58079	61391	})
58080	61392	#endif
58081	61393
58082	61394	#ifdef __LITTLE_ENDIAN__
58083		#define vqrshrun_high_n_s16(__p0_186, __p1_186, __p2_186) __extension__ ({ \
58084		int8x8_t __s0_186 = __p0_186; \
58085		int16x8_t __s1_186 = __p1_186; \
58086		int8x16_t __ret_186; \
58087		__ret_186 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_186), (int8x8_t)(vqrshrun_n_s16(__s1_186, __p2_186)))); \
58088		__ret_186; \
	61395	#define vqrshrun_high_n_s16(__p0_198, __p1_198, __p2_198) __extension__ ({ \
	61396	int8x8_t __s0_198 = __p0_198; \
	61397	int16x8_t __s1_198 = __p1_198; \
	61398	int8x16_t __ret_198; \
	61399	__ret_198 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_198), (int8x8_t)(vqrshrun_n_s16(__s1_198, __p2_198)))); \
	61400	__ret_198; \
58089	61401	})
58090	61402	#else
58091		#define vqrshrun_high_n_s16(__p0_187, __p1_187, __p2_187) __extension__ ({ \
58092		int8x8_t __s0_187 = __p0_187; \
58093		int16x8_t __s1_187 = __p1_187; \
58094		int8x8_t __rev0_187; __rev0_187 = __builtin_shufflevector(__s0_187, __s0_187, 7, 6, 5, 4, 3, 2, 1, 0); \
58095		int16x8_t __rev1_187; __rev1_187 = __builtin_shufflevector(__s1_187, __s1_187, 7, 6, 5, 4, 3, 2, 1, 0); \
58096		int8x16_t __ret_187; \
58097		__ret_187 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_187), (int8x8_t)(__noswap_vqrshrun_n_s16(__rev1_187, __p2_187)))); \
58098		__ret_187 = __builtin_shufflevector(__ret_187, __ret_187, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
58099		__ret_187; \
	61403	#define vqrshrun_high_n_s16(__p0_199, __p1_199, __p2_199) __extension__ ({ \
	61404	int8x8_t __s0_199 = __p0_199; \
	61405	int16x8_t __s1_199 = __p1_199; \
	61406	int8x8_t __rev0_199; __rev0_199 = __builtin_shufflevector(__s0_199, __s0_199, 7, 6, 5, 4, 3, 2, 1, 0); \
	61407	int16x8_t __rev1_199; __rev1_199 = __builtin_shufflevector(__s1_199, __s1_199, 7, 6, 5, 4, 3, 2, 1, 0); \
	61408	int8x16_t __ret_199; \
	61409	__ret_199 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_199), (int8x8_t)(__noswap_vqrshrun_n_s16(__rev1_199, __p2_199)))); \
	61410	__ret_199 = __builtin_shufflevector(__ret_199, __ret_199, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	61411	__ret_199; \
58100	61412	})
58101	61413	#endif
58102	61414
...	...	@@ -58453,128 +61765,128 @@ __ai int16_t vqshlh_s16(int16_t __p0, int16_t __p1) {
58453	61765	#endif
58454	61766
58455	61767	#ifdef __LITTLE_ENDIAN__
58456		#define vqshrn_high_n_u32(__p0_188, __p1_188, __p2_188) __extension__ ({ \
58457		uint16x4_t __s0_188 = __p0_188; \
58458		uint32x4_t __s1_188 = __p1_188; \
58459		uint16x8_t __ret_188; \
58460		__ret_188 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_188), (uint16x4_t)(vqshrn_n_u32(__s1_188, __p2_188)))); \
58461		__ret_188; \
	61768	#define vqshrn_high_n_u32(__p0_200, __p1_200, __p2_200) __extension__ ({ \
	61769	uint16x4_t __s0_200 = __p0_200; \
	61770	uint32x4_t __s1_200 = __p1_200; \
	61771	uint16x8_t __ret_200; \
	61772	__ret_200 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_200), (uint16x4_t)(vqshrn_n_u32(__s1_200, __p2_200)))); \
	61773	__ret_200; \
58462	61774	})
58463	61775	#else
58464		#define vqshrn_high_n_u32(__p0_189, __p1_189, __p2_189) __extension__ ({ \
58465		uint16x4_t __s0_189 = __p0_189; \
58466		uint32x4_t __s1_189 = __p1_189; \
58467		uint16x4_t __rev0_189; __rev0_189 = __builtin_shufflevector(__s0_189, __s0_189, 3, 2, 1, 0); \
58468		uint32x4_t __rev1_189; __rev1_189 = __builtin_shufflevector(__s1_189, __s1_189, 3, 2, 1, 0); \
58469		uint16x8_t __ret_189; \
58470		__ret_189 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_189), (uint16x4_t)(__noswap_vqshrn_n_u32(__rev1_189, __p2_189)))); \
58471		__ret_189 = __builtin_shufflevector(__ret_189, __ret_189, 7, 6, 5, 4, 3, 2, 1, 0); \
58472		__ret_189; \
	61776	#define vqshrn_high_n_u32(__p0_201, __p1_201, __p2_201) __extension__ ({ \
	61777	uint16x4_t __s0_201 = __p0_201; \
	61778	uint32x4_t __s1_201 = __p1_201; \
	61779	uint16x4_t __rev0_201; __rev0_201 = __builtin_shufflevector(__s0_201, __s0_201, 3, 2, 1, 0); \
	61780	uint32x4_t __rev1_201; __rev1_201 = __builtin_shufflevector(__s1_201, __s1_201, 3, 2, 1, 0); \
	61781	uint16x8_t __ret_201; \
	61782	__ret_201 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_201), (uint16x4_t)(__noswap_vqshrn_n_u32(__rev1_201, __p2_201)))); \
	61783	__ret_201 = __builtin_shufflevector(__ret_201, __ret_201, 7, 6, 5, 4, 3, 2, 1, 0); \
	61784	__ret_201; \
58473	61785	})
58474	61786	#endif
58475	61787
58476	61788	#ifdef __LITTLE_ENDIAN__
58477		#define vqshrn_high_n_u64(__p0_190, __p1_190, __p2_190) __extension__ ({ \
58478		uint32x2_t __s0_190 = __p0_190; \
58479		uint64x2_t __s1_190 = __p1_190; \
58480		uint32x4_t __ret_190; \
58481		__ret_190 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_190), (uint32x2_t)(vqshrn_n_u64(__s1_190, __p2_190)))); \
58482		__ret_190; \
	61789	#define vqshrn_high_n_u64(__p0_202, __p1_202, __p2_202) __extension__ ({ \
	61790	uint32x2_t __s0_202 = __p0_202; \
	61791	uint64x2_t __s1_202 = __p1_202; \
	61792	uint32x4_t __ret_202; \
	61793	__ret_202 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_202), (uint32x2_t)(vqshrn_n_u64(__s1_202, __p2_202)))); \
	61794	__ret_202; \
58483	61795	})
58484	61796	#else
58485		#define vqshrn_high_n_u64(__p0_191, __p1_191, __p2_191) __extension__ ({ \
58486		uint32x2_t __s0_191 = __p0_191; \
58487		uint64x2_t __s1_191 = __p1_191; \
58488		uint32x2_t __rev0_191; __rev0_191 = __builtin_shufflevector(__s0_191, __s0_191, 1, 0); \
58489		uint64x2_t __rev1_191; __rev1_191 = __builtin_shufflevector(__s1_191, __s1_191, 1, 0); \
58490		uint32x4_t __ret_191; \
58491		__ret_191 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_191), (uint32x2_t)(__noswap_vqshrn_n_u64(__rev1_191, __p2_191)))); \
58492		__ret_191 = __builtin_shufflevector(__ret_191, __ret_191, 3, 2, 1, 0); \
58493		__ret_191; \
	61797	#define vqshrn_high_n_u64(__p0_203, __p1_203, __p2_203) __extension__ ({ \
	61798	uint32x2_t __s0_203 = __p0_203; \
	61799	uint64x2_t __s1_203 = __p1_203; \
	61800	uint32x2_t __rev0_203; __rev0_203 = __builtin_shufflevector(__s0_203, __s0_203, 1, 0); \
	61801	uint64x2_t __rev1_203; __rev1_203 = __builtin_shufflevector(__s1_203, __s1_203, 1, 0); \
	61802	uint32x4_t __ret_203; \
	61803	__ret_203 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_203), (uint32x2_t)(__noswap_vqshrn_n_u64(__rev1_203, __p2_203)))); \
	61804	__ret_203 = __builtin_shufflevector(__ret_203, __ret_203, 3, 2, 1, 0); \
	61805	__ret_203; \
58494	61806	})
58495	61807	#endif
58496	61808
58497	61809	#ifdef __LITTLE_ENDIAN__
58498		#define vqshrn_high_n_u16(__p0_192, __p1_192, __p2_192) __extension__ ({ \
58499		uint8x8_t __s0_192 = __p0_192; \
58500		uint16x8_t __s1_192 = __p1_192; \
58501		uint8x16_t __ret_192; \
58502		__ret_192 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_192), (uint8x8_t)(vqshrn_n_u16(__s1_192, __p2_192)))); \
58503		__ret_192; \
	61810	#define vqshrn_high_n_u16(__p0_204, __p1_204, __p2_204) __extension__ ({ \
	61811	uint8x8_t __s0_204 = __p0_204; \
	61812	uint16x8_t __s1_204 = __p1_204; \
	61813	uint8x16_t __ret_204; \
	61814	__ret_204 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_204), (uint8x8_t)(vqshrn_n_u16(__s1_204, __p2_204)))); \
	61815	__ret_204; \
58504	61816	})
58505	61817	#else
58506		#define vqshrn_high_n_u16(__p0_193, __p1_193, __p2_193) __extension__ ({ \
58507		uint8x8_t __s0_193 = __p0_193; \
58508		uint16x8_t __s1_193 = __p1_193; \
58509		uint8x8_t __rev0_193; __rev0_193 = __builtin_shufflevector(__s0_193, __s0_193, 7, 6, 5, 4, 3, 2, 1, 0); \
58510		uint16x8_t __rev1_193; __rev1_193 = __builtin_shufflevector(__s1_193, __s1_193, 7, 6, 5, 4, 3, 2, 1, 0); \
58511		uint8x16_t __ret_193; \
58512		__ret_193 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_193), (uint8x8_t)(__noswap_vqshrn_n_u16(__rev1_193, __p2_193)))); \
58513		__ret_193 = __builtin_shufflevector(__ret_193, __ret_193, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
58514		__ret_193; \
	61818	#define vqshrn_high_n_u16(__p0_205, __p1_205, __p2_205) __extension__ ({ \
	61819	uint8x8_t __s0_205 = __p0_205; \
	61820	uint16x8_t __s1_205 = __p1_205; \
	61821	uint8x8_t __rev0_205; __rev0_205 = __builtin_shufflevector(__s0_205, __s0_205, 7, 6, 5, 4, 3, 2, 1, 0); \
	61822	uint16x8_t __rev1_205; __rev1_205 = __builtin_shufflevector(__s1_205, __s1_205, 7, 6, 5, 4, 3, 2, 1, 0); \
	61823	uint8x16_t __ret_205; \
	61824	__ret_205 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_205), (uint8x8_t)(__noswap_vqshrn_n_u16(__rev1_205, __p2_205)))); \
	61825	__ret_205 = __builtin_shufflevector(__ret_205, __ret_205, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	61826	__ret_205; \
58515	61827	})
58516	61828	#endif
58517	61829
58518	61830	#ifdef __LITTLE_ENDIAN__
58519		#define vqshrn_high_n_s32(__p0_194, __p1_194, __p2_194) __extension__ ({ \
58520		int16x4_t __s0_194 = __p0_194; \
58521		int32x4_t __s1_194 = __p1_194; \
58522		int16x8_t __ret_194; \
58523		__ret_194 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_194), (int16x4_t)(vqshrn_n_s32(__s1_194, __p2_194)))); \
58524		__ret_194; \
	61831	#define vqshrn_high_n_s32(__p0_206, __p1_206, __p2_206) __extension__ ({ \
	61832	int16x4_t __s0_206 = __p0_206; \
	61833	int32x4_t __s1_206 = __p1_206; \
	61834	int16x8_t __ret_206; \
	61835	__ret_206 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_206), (int16x4_t)(vqshrn_n_s32(__s1_206, __p2_206)))); \
	61836	__ret_206; \
58525	61837	})
58526	61838	#else
58527		#define vqshrn_high_n_s32(__p0_195, __p1_195, __p2_195) __extension__ ({ \
58528		int16x4_t __s0_195 = __p0_195; \
58529		int32x4_t __s1_195 = __p1_195; \
58530		int16x4_t __rev0_195; __rev0_195 = __builtin_shufflevector(__s0_195, __s0_195, 3, 2, 1, 0); \
58531		int32x4_t __rev1_195; __rev1_195 = __builtin_shufflevector(__s1_195, __s1_195, 3, 2, 1, 0); \
58532		int16x8_t __ret_195; \
58533		__ret_195 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_195), (int16x4_t)(__noswap_vqshrn_n_s32(__rev1_195, __p2_195)))); \
58534		__ret_195 = __builtin_shufflevector(__ret_195, __ret_195, 7, 6, 5, 4, 3, 2, 1, 0); \
58535		__ret_195; \
	61839	#define vqshrn_high_n_s32(__p0_207, __p1_207, __p2_207) __extension__ ({ \
	61840	int16x4_t __s0_207 = __p0_207; \
	61841	int32x4_t __s1_207 = __p1_207; \
	61842	int16x4_t __rev0_207; __rev0_207 = __builtin_shufflevector(__s0_207, __s0_207, 3, 2, 1, 0); \
	61843	int32x4_t __rev1_207; __rev1_207 = __builtin_shufflevector(__s1_207, __s1_207, 3, 2, 1, 0); \
	61844	int16x8_t __ret_207; \
	61845	__ret_207 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_207), (int16x4_t)(__noswap_vqshrn_n_s32(__rev1_207, __p2_207)))); \
	61846	__ret_207 = __builtin_shufflevector(__ret_207, __ret_207, 7, 6, 5, 4, 3, 2, 1, 0); \
	61847	__ret_207; \
58536	61848	})
58537	61849	#endif
58538	61850
58539	61851	#ifdef __LITTLE_ENDIAN__
58540		#define vqshrn_high_n_s64(__p0_196, __p1_196, __p2_196) __extension__ ({ \
58541		int32x2_t __s0_196 = __p0_196; \
58542		int64x2_t __s1_196 = __p1_196; \
58543		int32x4_t __ret_196; \
58544		__ret_196 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_196), (int32x2_t)(vqshrn_n_s64(__s1_196, __p2_196)))); \
58545		__ret_196; \
	61852	#define vqshrn_high_n_s64(__p0_208, __p1_208, __p2_208) __extension__ ({ \
	61853	int32x2_t __s0_208 = __p0_208; \
	61854	int64x2_t __s1_208 = __p1_208; \
	61855	int32x4_t __ret_208; \
	61856	__ret_208 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_208), (int32x2_t)(vqshrn_n_s64(__s1_208, __p2_208)))); \
	61857	__ret_208; \
58546	61858	})
58547	61859	#else
58548		#define vqshrn_high_n_s64(__p0_197, __p1_197, __p2_197) __extension__ ({ \
58549		int32x2_t __s0_197 = __p0_197; \
58550		int64x2_t __s1_197 = __p1_197; \
58551		int32x2_t __rev0_197; __rev0_197 = __builtin_shufflevector(__s0_197, __s0_197, 1, 0); \
58552		int64x2_t __rev1_197; __rev1_197 = __builtin_shufflevector(__s1_197, __s1_197, 1, 0); \
58553		int32x4_t __ret_197; \
58554		__ret_197 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_197), (int32x2_t)(__noswap_vqshrn_n_s64(__rev1_197, __p2_197)))); \
58555		__ret_197 = __builtin_shufflevector(__ret_197, __ret_197, 3, 2, 1, 0); \
58556		__ret_197; \
	61860	#define vqshrn_high_n_s64(__p0_209, __p1_209, __p2_209) __extension__ ({ \
	61861	int32x2_t __s0_209 = __p0_209; \
	61862	int64x2_t __s1_209 = __p1_209; \
	61863	int32x2_t __rev0_209; __rev0_209 = __builtin_shufflevector(__s0_209, __s0_209, 1, 0); \
	61864	int64x2_t __rev1_209; __rev1_209 = __builtin_shufflevector(__s1_209, __s1_209, 1, 0); \
	61865	int32x4_t __ret_209; \
	61866	__ret_209 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_209), (int32x2_t)(__noswap_vqshrn_n_s64(__rev1_209, __p2_209)))); \
	61867	__ret_209 = __builtin_shufflevector(__ret_209, __ret_209, 3, 2, 1, 0); \
	61868	__ret_209; \
58557	61869	})
58558	61870	#endif
58559	61871
58560	61872	#ifdef __LITTLE_ENDIAN__
58561		#define vqshrn_high_n_s16(__p0_198, __p1_198, __p2_198) __extension__ ({ \
58562		int8x8_t __s0_198 = __p0_198; \
58563		int16x8_t __s1_198 = __p1_198; \
58564		int8x16_t __ret_198; \
58565		__ret_198 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_198), (int8x8_t)(vqshrn_n_s16(__s1_198, __p2_198)))); \
58566		__ret_198; \
	61873	#define vqshrn_high_n_s16(__p0_210, __p1_210, __p2_210) __extension__ ({ \
	61874	int8x8_t __s0_210 = __p0_210; \
	61875	int16x8_t __s1_210 = __p1_210; \
	61876	int8x16_t __ret_210; \
	61877	__ret_210 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_210), (int8x8_t)(vqshrn_n_s16(__s1_210, __p2_210)))); \
	61878	__ret_210; \
58567	61879	})
58568	61880	#else
58569		#define vqshrn_high_n_s16(__p0_199, __p1_199, __p2_199) __extension__ ({ \
58570		int8x8_t __s0_199 = __p0_199; \
58571		int16x8_t __s1_199 = __p1_199; \
58572		int8x8_t __rev0_199; __rev0_199 = __builtin_shufflevector(__s0_199, __s0_199, 7, 6, 5, 4, 3, 2, 1, 0); \
58573		int16x8_t __rev1_199; __rev1_199 = __builtin_shufflevector(__s1_199, __s1_199, 7, 6, 5, 4, 3, 2, 1, 0); \
58574		int8x16_t __ret_199; \
58575		__ret_199 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_199), (int8x8_t)(__noswap_vqshrn_n_s16(__rev1_199, __p2_199)))); \
58576		__ret_199 = __builtin_shufflevector(__ret_199, __ret_199, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
58577		__ret_199; \
	61881	#define vqshrn_high_n_s16(__p0_211, __p1_211, __p2_211) __extension__ ({ \
	61882	int8x8_t __s0_211 = __p0_211; \
	61883	int16x8_t __s1_211 = __p1_211; \
	61884	int8x8_t __rev0_211; __rev0_211 = __builtin_shufflevector(__s0_211, __s0_211, 7, 6, 5, 4, 3, 2, 1, 0); \
	61885	int16x8_t __rev1_211; __rev1_211 = __builtin_shufflevector(__s1_211, __s1_211, 7, 6, 5, 4, 3, 2, 1, 0); \
	61886	int8x16_t __ret_211; \
	61887	__ret_211 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_211), (int8x8_t)(__noswap_vqshrn_n_s16(__rev1_211, __p2_211)))); \
	61888	__ret_211 = __builtin_shufflevector(__ret_211, __ret_211, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	61889	__ret_211; \
58578	61890	})
58579	61891	#endif
58580	61892
...	...	@@ -58675,65 +61987,65 @@ __ai int16_t vqshlh_s16(int16_t __p0, int16_t __p1) {
58675	61987	#endif
58676	61988
58677	61989	#ifdef __LITTLE_ENDIAN__
58678		#define vqshrun_high_n_s32(__p0_200, __p1_200, __p2_200) __extension__ ({ \
58679		int16x4_t __s0_200 = __p0_200; \
58680		int32x4_t __s1_200 = __p1_200; \
58681		int16x8_t __ret_200; \
58682		__ret_200 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_200), (int16x4_t)(vqshrun_n_s32(__s1_200, __p2_200)))); \
58683		__ret_200; \
	61990	#define vqshrun_high_n_s32(__p0_212, __p1_212, __p2_212) __extension__ ({ \
	61991	int16x4_t __s0_212 = __p0_212; \
	61992	int32x4_t __s1_212 = __p1_212; \
	61993	int16x8_t __ret_212; \
	61994	__ret_212 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_212), (int16x4_t)(vqshrun_n_s32(__s1_212, __p2_212)))); \
	61995	__ret_212; \
58684	61996	})
58685	61997	#else
58686		#define vqshrun_high_n_s32(__p0_201, __p1_201, __p2_201) __extension__ ({ \
58687		int16x4_t __s0_201 = __p0_201; \
58688		int32x4_t __s1_201 = __p1_201; \
58689		int16x4_t __rev0_201; __rev0_201 = __builtin_shufflevector(__s0_201, __s0_201, 3, 2, 1, 0); \
58690		int32x4_t __rev1_201; __rev1_201 = __builtin_shufflevector(__s1_201, __s1_201, 3, 2, 1, 0); \
58691		int16x8_t __ret_201; \
58692		__ret_201 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_201), (int16x4_t)(__noswap_vqshrun_n_s32(__rev1_201, __p2_201)))); \
58693		__ret_201 = __builtin_shufflevector(__ret_201, __ret_201, 7, 6, 5, 4, 3, 2, 1, 0); \
58694		__ret_201; \
	61998	#define vqshrun_high_n_s32(__p0_213, __p1_213, __p2_213) __extension__ ({ \
	61999	int16x4_t __s0_213 = __p0_213; \
	62000	int32x4_t __s1_213 = __p1_213; \
	62001	int16x4_t __rev0_213; __rev0_213 = __builtin_shufflevector(__s0_213, __s0_213, 3, 2, 1, 0); \
	62002	int32x4_t __rev1_213; __rev1_213 = __builtin_shufflevector(__s1_213, __s1_213, 3, 2, 1, 0); \
	62003	int16x8_t __ret_213; \
	62004	__ret_213 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_213), (int16x4_t)(__noswap_vqshrun_n_s32(__rev1_213, __p2_213)))); \
	62005	__ret_213 = __builtin_shufflevector(__ret_213, __ret_213, 7, 6, 5, 4, 3, 2, 1, 0); \
	62006	__ret_213; \
58695	62007	})
58696	62008	#endif
58697	62009
58698	62010	#ifdef __LITTLE_ENDIAN__
58699		#define vqshrun_high_n_s64(__p0_202, __p1_202, __p2_202) __extension__ ({ \
58700		int32x2_t __s0_202 = __p0_202; \
58701		int64x2_t __s1_202 = __p1_202; \
58702		int32x4_t __ret_202; \
58703		__ret_202 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_202), (int32x2_t)(vqshrun_n_s64(__s1_202, __p2_202)))); \
58704		__ret_202; \
	62011	#define vqshrun_high_n_s64(__p0_214, __p1_214, __p2_214) __extension__ ({ \
	62012	int32x2_t __s0_214 = __p0_214; \
	62013	int64x2_t __s1_214 = __p1_214; \
	62014	int32x4_t __ret_214; \
	62015	__ret_214 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_214), (int32x2_t)(vqshrun_n_s64(__s1_214, __p2_214)))); \
	62016	__ret_214; \
58705	62017	})
58706	62018	#else
58707		#define vqshrun_high_n_s64(__p0_203, __p1_203, __p2_203) __extension__ ({ \
58708		int32x2_t __s0_203 = __p0_203; \
58709		int64x2_t __s1_203 = __p1_203; \
58710		int32x2_t __rev0_203; __rev0_203 = __builtin_shufflevector(__s0_203, __s0_203, 1, 0); \
58711		int64x2_t __rev1_203; __rev1_203 = __builtin_shufflevector(__s1_203, __s1_203, 1, 0); \
58712		int32x4_t __ret_203; \
58713		__ret_203 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_203), (int32x2_t)(__noswap_vqshrun_n_s64(__rev1_203, __p2_203)))); \
58714		__ret_203 = __builtin_shufflevector(__ret_203, __ret_203, 3, 2, 1, 0); \
58715		__ret_203; \
	62019	#define vqshrun_high_n_s64(__p0_215, __p1_215, __p2_215) __extension__ ({ \
	62020	int32x2_t __s0_215 = __p0_215; \
	62021	int64x2_t __s1_215 = __p1_215; \
	62022	int32x2_t __rev0_215; __rev0_215 = __builtin_shufflevector(__s0_215, __s0_215, 1, 0); \
	62023	int64x2_t __rev1_215; __rev1_215 = __builtin_shufflevector(__s1_215, __s1_215, 1, 0); \
	62024	int32x4_t __ret_215; \
	62025	__ret_215 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_215), (int32x2_t)(__noswap_vqshrun_n_s64(__rev1_215, __p2_215)))); \
	62026	__ret_215 = __builtin_shufflevector(__ret_215, __ret_215, 3, 2, 1, 0); \
	62027	__ret_215; \
58716	62028	})
58717	62029	#endif
58718	62030
58719	62031	#ifdef __LITTLE_ENDIAN__
58720		#define vqshrun_high_n_s16(__p0_204, __p1_204, __p2_204) __extension__ ({ \
58721		int8x8_t __s0_204 = __p0_204; \
58722		int16x8_t __s1_204 = __p1_204; \
58723		int8x16_t __ret_204; \
58724		__ret_204 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_204), (int8x8_t)(vqshrun_n_s16(__s1_204, __p2_204)))); \
58725		__ret_204; \
	62032	#define vqshrun_high_n_s16(__p0_216, __p1_216, __p2_216) __extension__ ({ \
	62033	int8x8_t __s0_216 = __p0_216; \
	62034	int16x8_t __s1_216 = __p1_216; \
	62035	int8x16_t __ret_216; \
	62036	__ret_216 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_216), (int8x8_t)(vqshrun_n_s16(__s1_216, __p2_216)))); \
	62037	__ret_216; \
58726	62038	})
58727	62039	#else
58728		#define vqshrun_high_n_s16(__p0_205, __p1_205, __p2_205) __extension__ ({ \
58729		int8x8_t __s0_205 = __p0_205; \
58730		int16x8_t __s1_205 = __p1_205; \
58731		int8x8_t __rev0_205; __rev0_205 = __builtin_shufflevector(__s0_205, __s0_205, 7, 6, 5, 4, 3, 2, 1, 0); \
58732		int16x8_t __rev1_205; __rev1_205 = __builtin_shufflevector(__s1_205, __s1_205, 7, 6, 5, 4, 3, 2, 1, 0); \
58733		int8x16_t __ret_205; \
58734		__ret_205 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_205), (int8x8_t)(__noswap_vqshrun_n_s16(__rev1_205, __p2_205)))); \
58735		__ret_205 = __builtin_shufflevector(__ret_205, __ret_205, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
58736		__ret_205; \
	62040	#define vqshrun_high_n_s16(__p0_217, __p1_217, __p2_217) __extension__ ({ \
	62041	int8x8_t __s0_217 = __p0_217; \
	62042	int16x8_t __s1_217 = __p1_217; \
	62043	int8x8_t __rev0_217; __rev0_217 = __builtin_shufflevector(__s0_217, __s0_217, 7, 6, 5, 4, 3, 2, 1, 0); \
	62044	int16x8_t __rev1_217; __rev1_217 = __builtin_shufflevector(__s1_217, __s1_217, 7, 6, 5, 4, 3, 2, 1, 0); \
	62045	int8x16_t __ret_217; \
	62046	__ret_217 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_217), (int8x8_t)(__noswap_vqshrun_n_s16(__rev1_217, __p2_217)))); \
	62047	__ret_217 = __builtin_shufflevector(__ret_217, __ret_217, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	62048	__ret_217; \
58737	62049	})
58738	62050	#endif
58739	62051
...	...	@@ -60265,128 +63577,128 @@ __ai int64_t vrshld_s64(int64_t __p0, int64_t __p1) {
60265	63577	#endif
60266	63578
60267	63579	#ifdef __LITTLE_ENDIAN__
60268		#define vrshrn_high_n_u32(__p0_206, __p1_206, __p2_206) __extension__ ({ \
60269		uint16x4_t __s0_206 = __p0_206; \
60270		uint32x4_t __s1_206 = __p1_206; \
60271		uint16x8_t __ret_206; \
60272		__ret_206 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_206), (uint16x4_t)(vrshrn_n_u32(__s1_206, __p2_206)))); \
60273		__ret_206; \
	63580	#define vrshrn_high_n_u32(__p0_218, __p1_218, __p2_218) __extension__ ({ \
	63581	uint16x4_t __s0_218 = __p0_218; \
	63582	uint32x4_t __s1_218 = __p1_218; \
	63583	uint16x8_t __ret_218; \
	63584	__ret_218 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_218), (uint16x4_t)(vrshrn_n_u32(__s1_218, __p2_218)))); \
	63585	__ret_218; \
60274	63586	})
60275	63587	#else
60276		#define vrshrn_high_n_u32(__p0_207, __p1_207, __p2_207) __extension__ ({ \
60277		uint16x4_t __s0_207 = __p0_207; \
60278		uint32x4_t __s1_207 = __p1_207; \
60279		uint16x4_t __rev0_207; __rev0_207 = __builtin_shufflevector(__s0_207, __s0_207, 3, 2, 1, 0); \
60280		uint32x4_t __rev1_207; __rev1_207 = __builtin_shufflevector(__s1_207, __s1_207, 3, 2, 1, 0); \
60281		uint16x8_t __ret_207; \
60282		__ret_207 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_207), (uint16x4_t)(__noswap_vrshrn_n_u32(__rev1_207, __p2_207)))); \
60283		__ret_207 = __builtin_shufflevector(__ret_207, __ret_207, 7, 6, 5, 4, 3, 2, 1, 0); \
60284		__ret_207; \
	63588	#define vrshrn_high_n_u32(__p0_219, __p1_219, __p2_219) __extension__ ({ \
	63589	uint16x4_t __s0_219 = __p0_219; \
	63590	uint32x4_t __s1_219 = __p1_219; \
	63591	uint16x4_t __rev0_219; __rev0_219 = __builtin_shufflevector(__s0_219, __s0_219, 3, 2, 1, 0); \
	63592	uint32x4_t __rev1_219; __rev1_219 = __builtin_shufflevector(__s1_219, __s1_219, 3, 2, 1, 0); \
	63593	uint16x8_t __ret_219; \
	63594	__ret_219 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_219), (uint16x4_t)(__noswap_vrshrn_n_u32(__rev1_219, __p2_219)))); \
	63595	__ret_219 = __builtin_shufflevector(__ret_219, __ret_219, 7, 6, 5, 4, 3, 2, 1, 0); \
	63596	__ret_219; \
60285	63597	})
60286	63598	#endif
60287	63599
60288	63600	#ifdef __LITTLE_ENDIAN__
60289		#define vrshrn_high_n_u64(__p0_208, __p1_208, __p2_208) __extension__ ({ \
60290		uint32x2_t __s0_208 = __p0_208; \
60291		uint64x2_t __s1_208 = __p1_208; \
60292		uint32x4_t __ret_208; \
60293		__ret_208 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_208), (uint32x2_t)(vrshrn_n_u64(__s1_208, __p2_208)))); \
60294		__ret_208; \
	63601	#define vrshrn_high_n_u64(__p0_220, __p1_220, __p2_220) __extension__ ({ \
	63602	uint32x2_t __s0_220 = __p0_220; \
	63603	uint64x2_t __s1_220 = __p1_220; \
	63604	uint32x4_t __ret_220; \
	63605	__ret_220 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_220), (uint32x2_t)(vrshrn_n_u64(__s1_220, __p2_220)))); \
	63606	__ret_220; \
60295	63607	})
60296	63608	#else
60297		#define vrshrn_high_n_u64(__p0_209, __p1_209, __p2_209) __extension__ ({ \
60298		uint32x2_t __s0_209 = __p0_209; \
60299		uint64x2_t __s1_209 = __p1_209; \
60300		uint32x2_t __rev0_209; __rev0_209 = __builtin_shufflevector(__s0_209, __s0_209, 1, 0); \
60301		uint64x2_t __rev1_209; __rev1_209 = __builtin_shufflevector(__s1_209, __s1_209, 1, 0); \
60302		uint32x4_t __ret_209; \
60303		__ret_209 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_209), (uint32x2_t)(__noswap_vrshrn_n_u64(__rev1_209, __p2_209)))); \
60304		__ret_209 = __builtin_shufflevector(__ret_209, __ret_209, 3, 2, 1, 0); \
60305		__ret_209; \
	63609	#define vrshrn_high_n_u64(__p0_221, __p1_221, __p2_221) __extension__ ({ \
	63610	uint32x2_t __s0_221 = __p0_221; \
	63611	uint64x2_t __s1_221 = __p1_221; \
	63612	uint32x2_t __rev0_221; __rev0_221 = __builtin_shufflevector(__s0_221, __s0_221, 1, 0); \
	63613	uint64x2_t __rev1_221; __rev1_221 = __builtin_shufflevector(__s1_221, __s1_221, 1, 0); \
	63614	uint32x4_t __ret_221; \
	63615	__ret_221 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_221), (uint32x2_t)(__noswap_vrshrn_n_u64(__rev1_221, __p2_221)))); \
	63616	__ret_221 = __builtin_shufflevector(__ret_221, __ret_221, 3, 2, 1, 0); \
	63617	__ret_221; \
60306	63618	})
60307	63619	#endif
60308	63620
60309	63621	#ifdef __LITTLE_ENDIAN__
60310		#define vrshrn_high_n_u16(__p0_210, __p1_210, __p2_210) __extension__ ({ \
60311		uint8x8_t __s0_210 = __p0_210; \
60312		uint16x8_t __s1_210 = __p1_210; \
60313		uint8x16_t __ret_210; \
60314		__ret_210 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_210), (uint8x8_t)(vrshrn_n_u16(__s1_210, __p2_210)))); \
60315		__ret_210; \
	63622	#define vrshrn_high_n_u16(__p0_222, __p1_222, __p2_222) __extension__ ({ \
	63623	uint8x8_t __s0_222 = __p0_222; \
	63624	uint16x8_t __s1_222 = __p1_222; \
	63625	uint8x16_t __ret_222; \
	63626	__ret_222 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_222), (uint8x8_t)(vrshrn_n_u16(__s1_222, __p2_222)))); \
	63627	__ret_222; \
60316	63628	})
60317	63629	#else
60318		#define vrshrn_high_n_u16(__p0_211, __p1_211, __p2_211) __extension__ ({ \
60319		uint8x8_t __s0_211 = __p0_211; \
60320		uint16x8_t __s1_211 = __p1_211; \
60321		uint8x8_t __rev0_211; __rev0_211 = __builtin_shufflevector(__s0_211, __s0_211, 7, 6, 5, 4, 3, 2, 1, 0); \
60322		uint16x8_t __rev1_211; __rev1_211 = __builtin_shufflevector(__s1_211, __s1_211, 7, 6, 5, 4, 3, 2, 1, 0); \
60323		uint8x16_t __ret_211; \
60324		__ret_211 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_211), (uint8x8_t)(__noswap_vrshrn_n_u16(__rev1_211, __p2_211)))); \
60325		__ret_211 = __builtin_shufflevector(__ret_211, __ret_211, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
60326		__ret_211; \
	63630	#define vrshrn_high_n_u16(__p0_223, __p1_223, __p2_223) __extension__ ({ \
	63631	uint8x8_t __s0_223 = __p0_223; \
	63632	uint16x8_t __s1_223 = __p1_223; \
	63633	uint8x8_t __rev0_223; __rev0_223 = __builtin_shufflevector(__s0_223, __s0_223, 7, 6, 5, 4, 3, 2, 1, 0); \
	63634	uint16x8_t __rev1_223; __rev1_223 = __builtin_shufflevector(__s1_223, __s1_223, 7, 6, 5, 4, 3, 2, 1, 0); \
	63635	uint8x16_t __ret_223; \
	63636	__ret_223 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_223), (uint8x8_t)(__noswap_vrshrn_n_u16(__rev1_223, __p2_223)))); \
	63637	__ret_223 = __builtin_shufflevector(__ret_223, __ret_223, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	63638	__ret_223; \
60327	63639	})
60328	63640	#endif
60329	63641
60330	63642	#ifdef __LITTLE_ENDIAN__
60331		#define vrshrn_high_n_s32(__p0_212, __p1_212, __p2_212) __extension__ ({ \
60332		int16x4_t __s0_212 = __p0_212; \
60333		int32x4_t __s1_212 = __p1_212; \
60334		int16x8_t __ret_212; \
60335		__ret_212 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_212), (int16x4_t)(vrshrn_n_s32(__s1_212, __p2_212)))); \
60336		__ret_212; \
	63643	#define vrshrn_high_n_s32(__p0_224, __p1_224, __p2_224) __extension__ ({ \
	63644	int16x4_t __s0_224 = __p0_224; \
	63645	int32x4_t __s1_224 = __p1_224; \
	63646	int16x8_t __ret_224; \
	63647	__ret_224 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_224), (int16x4_t)(vrshrn_n_s32(__s1_224, __p2_224)))); \
	63648	__ret_224; \
60337	63649	})
60338	63650	#else
60339		#define vrshrn_high_n_s32(__p0_213, __p1_213, __p2_213) __extension__ ({ \
60340		int16x4_t __s0_213 = __p0_213; \
60341		int32x4_t __s1_213 = __p1_213; \
60342		int16x4_t __rev0_213; __rev0_213 = __builtin_shufflevector(__s0_213, __s0_213, 3, 2, 1, 0); \
60343		int32x4_t __rev1_213; __rev1_213 = __builtin_shufflevector(__s1_213, __s1_213, 3, 2, 1, 0); \
60344		int16x8_t __ret_213; \
60345		__ret_213 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_213), (int16x4_t)(__noswap_vrshrn_n_s32(__rev1_213, __p2_213)))); \
60346		__ret_213 = __builtin_shufflevector(__ret_213, __ret_213, 7, 6, 5, 4, 3, 2, 1, 0); \
60347		__ret_213; \
	63651	#define vrshrn_high_n_s32(__p0_225, __p1_225, __p2_225) __extension__ ({ \
	63652	int16x4_t __s0_225 = __p0_225; \
	63653	int32x4_t __s1_225 = __p1_225; \
	63654	int16x4_t __rev0_225; __rev0_225 = __builtin_shufflevector(__s0_225, __s0_225, 3, 2, 1, 0); \
	63655	int32x4_t __rev1_225; __rev1_225 = __builtin_shufflevector(__s1_225, __s1_225, 3, 2, 1, 0); \
	63656	int16x8_t __ret_225; \
	63657	__ret_225 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_225), (int16x4_t)(__noswap_vrshrn_n_s32(__rev1_225, __p2_225)))); \
	63658	__ret_225 = __builtin_shufflevector(__ret_225, __ret_225, 7, 6, 5, 4, 3, 2, 1, 0); \
	63659	__ret_225; \
60348	63660	})
60349	63661	#endif
60350	63662
60351	63663	#ifdef __LITTLE_ENDIAN__
60352		#define vrshrn_high_n_s64(__p0_214, __p1_214, __p2_214) __extension__ ({ \
60353		int32x2_t __s0_214 = __p0_214; \
60354		int64x2_t __s1_214 = __p1_214; \
60355		int32x4_t __ret_214; \
60356		__ret_214 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_214), (int32x2_t)(vrshrn_n_s64(__s1_214, __p2_214)))); \
60357		__ret_214; \
	63664	#define vrshrn_high_n_s64(__p0_226, __p1_226, __p2_226) __extension__ ({ \
	63665	int32x2_t __s0_226 = __p0_226; \
	63666	int64x2_t __s1_226 = __p1_226; \
	63667	int32x4_t __ret_226; \
	63668	__ret_226 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_226), (int32x2_t)(vrshrn_n_s64(__s1_226, __p2_226)))); \
	63669	__ret_226; \
60358	63670	})
60359	63671	#else
60360		#define vrshrn_high_n_s64(__p0_215, __p1_215, __p2_215) __extension__ ({ \
60361		int32x2_t __s0_215 = __p0_215; \
60362		int64x2_t __s1_215 = __p1_215; \
60363		int32x2_t __rev0_215; __rev0_215 = __builtin_shufflevector(__s0_215, __s0_215, 1, 0); \
60364		int64x2_t __rev1_215; __rev1_215 = __builtin_shufflevector(__s1_215, __s1_215, 1, 0); \
60365		int32x4_t __ret_215; \
60366		__ret_215 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_215), (int32x2_t)(__noswap_vrshrn_n_s64(__rev1_215, __p2_215)))); \
60367		__ret_215 = __builtin_shufflevector(__ret_215, __ret_215, 3, 2, 1, 0); \
60368		__ret_215; \
	63672	#define vrshrn_high_n_s64(__p0_227, __p1_227, __p2_227) __extension__ ({ \
	63673	int32x2_t __s0_227 = __p0_227; \
	63674	int64x2_t __s1_227 = __p1_227; \
	63675	int32x2_t __rev0_227; __rev0_227 = __builtin_shufflevector(__s0_227, __s0_227, 1, 0); \
	63676	int64x2_t __rev1_227; __rev1_227 = __builtin_shufflevector(__s1_227, __s1_227, 1, 0); \
	63677	int32x4_t __ret_227; \
	63678	__ret_227 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_227), (int32x2_t)(__noswap_vrshrn_n_s64(__rev1_227, __p2_227)))); \
	63679	__ret_227 = __builtin_shufflevector(__ret_227, __ret_227, 3, 2, 1, 0); \
	63680	__ret_227; \
60369	63681	})
60370	63682	#endif
60371	63683
60372	63684	#ifdef __LITTLE_ENDIAN__
60373		#define vrshrn_high_n_s16(__p0_216, __p1_216, __p2_216) __extension__ ({ \
60374		int8x8_t __s0_216 = __p0_216; \
60375		int16x8_t __s1_216 = __p1_216; \
60376		int8x16_t __ret_216; \
60377		__ret_216 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_216), (int8x8_t)(vrshrn_n_s16(__s1_216, __p2_216)))); \
60378		__ret_216; \
	63685	#define vrshrn_high_n_s16(__p0_228, __p1_228, __p2_228) __extension__ ({ \
	63686	int8x8_t __s0_228 = __p0_228; \
	63687	int16x8_t __s1_228 = __p1_228; \
	63688	int8x16_t __ret_228; \
	63689	__ret_228 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_228), (int8x8_t)(vrshrn_n_s16(__s1_228, __p2_228)))); \
	63690	__ret_228; \
60379	63691	})
60380	63692	#else
60381		#define vrshrn_high_n_s16(__p0_217, __p1_217, __p2_217) __extension__ ({ \
60382		int8x8_t __s0_217 = __p0_217; \
60383		int16x8_t __s1_217 = __p1_217; \
60384		int8x8_t __rev0_217; __rev0_217 = __builtin_shufflevector(__s0_217, __s0_217, 7, 6, 5, 4, 3, 2, 1, 0); \
60385		int16x8_t __rev1_217; __rev1_217 = __builtin_shufflevector(__s1_217, __s1_217, 7, 6, 5, 4, 3, 2, 1, 0); \
60386		int8x16_t __ret_217; \
60387		__ret_217 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_217), (int8x8_t)(__noswap_vrshrn_n_s16(__rev1_217, __p2_217)))); \
60388		__ret_217 = __builtin_shufflevector(__ret_217, __ret_217, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
60389		__ret_217; \
	63693	#define vrshrn_high_n_s16(__p0_229, __p1_229, __p2_229) __extension__ ({ \
	63694	int8x8_t __s0_229 = __p0_229; \
	63695	int16x8_t __s1_229 = __p1_229; \
	63696	int8x8_t __rev0_229; __rev0_229 = __builtin_shufflevector(__s0_229, __s0_229, 7, 6, 5, 4, 3, 2, 1, 0); \
	63697	int16x8_t __rev1_229; __rev1_229 = __builtin_shufflevector(__s1_229, __s1_229, 7, 6, 5, 4, 3, 2, 1, 0); \
	63698	int8x16_t __ret_229; \
	63699	__ret_229 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_229), (int8x8_t)(__noswap_vrshrn_n_s16(__rev1_229, __p2_229)))); \
	63700	__ret_229 = __builtin_shufflevector(__ret_229, __ret_229, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	63701	__ret_229; \
60390	63702	})
60391	63703	#endif
60392	63704
...	...	@@ -60816,110 +64128,110 @@ __ai int64_t vshld_s64(int64_t __p0, int64_t __p1) {
60816	64128	#endif
60817	64129
60818	64130	#ifdef __LITTLE_ENDIAN__
60819		#define vshll_high_n_u8(__p0_218, __p1_218) __extension__ ({ \
60820		uint8x16_t __s0_218 = __p0_218; \
60821		uint16x8_t __ret_218; \
60822		__ret_218 = (uint16x8_t)(vshll_n_u8(vget_high_u8(__s0_218), __p1_218)); \
60823		__ret_218; \
	64131	#define vshll_high_n_u8(__p0_230, __p1_230) __extension__ ({ \
	64132	uint8x16_t __s0_230 = __p0_230; \
	64133	uint16x8_t __ret_230; \
	64134	__ret_230 = (uint16x8_t)(vshll_n_u8(vget_high_u8(__s0_230), __p1_230)); \
	64135	__ret_230; \
60824	64136	})
60825	64137	#else
60826		#define vshll_high_n_u8(__p0_219, __p1_219) __extension__ ({ \
60827		uint8x16_t __s0_219 = __p0_219; \
60828		uint8x16_t __rev0_219; __rev0_219 = __builtin_shufflevector(__s0_219, __s0_219, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
60829		uint16x8_t __ret_219; \
60830		__ret_219 = (uint16x8_t)(__noswap_vshll_n_u8(__noswap_vget_high_u8(__rev0_219), __p1_219)); \
60831		__ret_219 = __builtin_shufflevector(__ret_219, __ret_219, 7, 6, 5, 4, 3, 2, 1, 0); \
60832		__ret_219; \
	64138	#define vshll_high_n_u8(__p0_231, __p1_231) __extension__ ({ \
	64139	uint8x16_t __s0_231 = __p0_231; \
	64140	uint8x16_t __rev0_231; __rev0_231 = __builtin_shufflevector(__s0_231, __s0_231, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	64141	uint16x8_t __ret_231; \
	64142	__ret_231 = (uint16x8_t)(__noswap_vshll_n_u8(__noswap_vget_high_u8(__rev0_231), __p1_231)); \
	64143	__ret_231 = __builtin_shufflevector(__ret_231, __ret_231, 7, 6, 5, 4, 3, 2, 1, 0); \
	64144	__ret_231; \
60833	64145	})
60834	64146	#endif
60835	64147
60836	64148	#ifdef __LITTLE_ENDIAN__
60837		#define vshll_high_n_u32(__p0_220, __p1_220) __extension__ ({ \
60838		uint32x4_t __s0_220 = __p0_220; \
60839		uint64x2_t __ret_220; \
60840		__ret_220 = (uint64x2_t)(vshll_n_u32(vget_high_u32(__s0_220), __p1_220)); \
60841		__ret_220; \
	64149	#define vshll_high_n_u32(__p0_232, __p1_232) __extension__ ({ \
	64150	uint32x4_t __s0_232 = __p0_232; \
	64151	uint64x2_t __ret_232; \
	64152	__ret_232 = (uint64x2_t)(vshll_n_u32(vget_high_u32(__s0_232), __p1_232)); \
	64153	__ret_232; \
60842	64154	})
60843	64155	#else
60844		#define vshll_high_n_u32(__p0_221, __p1_221) __extension__ ({ \
60845		uint32x4_t __s0_221 = __p0_221; \
60846		uint32x4_t __rev0_221; __rev0_221 = __builtin_shufflevector(__s0_221, __s0_221, 3, 2, 1, 0); \
60847		uint64x2_t __ret_221; \
60848		__ret_221 = (uint64x2_t)(__noswap_vshll_n_u32(__noswap_vget_high_u32(__rev0_221), __p1_221)); \
60849		__ret_221 = __builtin_shufflevector(__ret_221, __ret_221, 1, 0); \
60850		__ret_221; \
	64156	#define vshll_high_n_u32(__p0_233, __p1_233) __extension__ ({ \
	64157	uint32x4_t __s0_233 = __p0_233; \
	64158	uint32x4_t __rev0_233; __rev0_233 = __builtin_shufflevector(__s0_233, __s0_233, 3, 2, 1, 0); \
	64159	uint64x2_t __ret_233; \
	64160	__ret_233 = (uint64x2_t)(__noswap_vshll_n_u32(__noswap_vget_high_u32(__rev0_233), __p1_233)); \
	64161	__ret_233 = __builtin_shufflevector(__ret_233, __ret_233, 1, 0); \
	64162	__ret_233; \
60851	64163	})
60852	64164	#endif
60853	64165
60854	64166	#ifdef __LITTLE_ENDIAN__
60855		#define vshll_high_n_u16(__p0_222, __p1_222) __extension__ ({ \
60856		uint16x8_t __s0_222 = __p0_222; \
60857		uint32x4_t __ret_222; \
60858		__ret_222 = (uint32x4_t)(vshll_n_u16(vget_high_u16(__s0_222), __p1_222)); \
60859		__ret_222; \
	64167	#define vshll_high_n_u16(__p0_234, __p1_234) __extension__ ({ \
	64168	uint16x8_t __s0_234 = __p0_234; \
	64169	uint32x4_t __ret_234; \
	64170	__ret_234 = (uint32x4_t)(vshll_n_u16(vget_high_u16(__s0_234), __p1_234)); \
	64171	__ret_234; \
60860	64172	})
60861	64173	#else
60862		#define vshll_high_n_u16(__p0_223, __p1_223) __extension__ ({ \
60863		uint16x8_t __s0_223 = __p0_223; \
60864		uint16x8_t __rev0_223; __rev0_223 = __builtin_shufflevector(__s0_223, __s0_223, 7, 6, 5, 4, 3, 2, 1, 0); \
60865		uint32x4_t __ret_223; \
60866		__ret_223 = (uint32x4_t)(__noswap_vshll_n_u16(__noswap_vget_high_u16(__rev0_223), __p1_223)); \
60867		__ret_223 = __builtin_shufflevector(__ret_223, __ret_223, 3, 2, 1, 0); \
60868		__ret_223; \
	64174	#define vshll_high_n_u16(__p0_235, __p1_235) __extension__ ({ \
	64175	uint16x8_t __s0_235 = __p0_235; \
	64176	uint16x8_t __rev0_235; __rev0_235 = __builtin_shufflevector(__s0_235, __s0_235, 7, 6, 5, 4, 3, 2, 1, 0); \
	64177	uint32x4_t __ret_235; \
	64178	__ret_235 = (uint32x4_t)(__noswap_vshll_n_u16(__noswap_vget_high_u16(__rev0_235), __p1_235)); \
	64179	__ret_235 = __builtin_shufflevector(__ret_235, __ret_235, 3, 2, 1, 0); \
	64180	__ret_235; \
60869	64181	})
60870	64182	#endif
60871	64183
60872	64184	#ifdef __LITTLE_ENDIAN__
60873		#define vshll_high_n_s8(__p0_224, __p1_224) __extension__ ({ \
60874		int8x16_t __s0_224 = __p0_224; \
60875		int16x8_t __ret_224; \
60876		__ret_224 = (int16x8_t)(vshll_n_s8(vget_high_s8(__s0_224), __p1_224)); \
60877		__ret_224; \
	64185	#define vshll_high_n_s8(__p0_236, __p1_236) __extension__ ({ \
	64186	int8x16_t __s0_236 = __p0_236; \
	64187	int16x8_t __ret_236; \
	64188	__ret_236 = (int16x8_t)(vshll_n_s8(vget_high_s8(__s0_236), __p1_236)); \
	64189	__ret_236; \
60878	64190	})
60879	64191	#else
60880		#define vshll_high_n_s8(__p0_225, __p1_225) __extension__ ({ \
60881		int8x16_t __s0_225 = __p0_225; \
60882		int8x16_t __rev0_225; __rev0_225 = __builtin_shufflevector(__s0_225, __s0_225, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
60883		int16x8_t __ret_225; \
60884		__ret_225 = (int16x8_t)(__noswap_vshll_n_s8(__noswap_vget_high_s8(__rev0_225), __p1_225)); \
60885		__ret_225 = __builtin_shufflevector(__ret_225, __ret_225, 7, 6, 5, 4, 3, 2, 1, 0); \
60886		__ret_225; \
	64192	#define vshll_high_n_s8(__p0_237, __p1_237) __extension__ ({ \
	64193	int8x16_t __s0_237 = __p0_237; \
	64194	int8x16_t __rev0_237; __rev0_237 = __builtin_shufflevector(__s0_237, __s0_237, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	64195	int16x8_t __ret_237; \
	64196	__ret_237 = (int16x8_t)(__noswap_vshll_n_s8(__noswap_vget_high_s8(__rev0_237), __p1_237)); \
	64197	__ret_237 = __builtin_shufflevector(__ret_237, __ret_237, 7, 6, 5, 4, 3, 2, 1, 0); \
	64198	__ret_237; \
60887	64199	})
60888	64200	#endif
60889	64201
60890	64202	#ifdef __LITTLE_ENDIAN__
60891		#define vshll_high_n_s32(__p0_226, __p1_226) __extension__ ({ \
60892		int32x4_t __s0_226 = __p0_226; \
60893		int64x2_t __ret_226; \
60894		__ret_226 = (int64x2_t)(vshll_n_s32(vget_high_s32(__s0_226), __p1_226)); \
60895		__ret_226; \
	64203	#define vshll_high_n_s32(__p0_238, __p1_238) __extension__ ({ \
	64204	int32x4_t __s0_238 = __p0_238; \
	64205	int64x2_t __ret_238; \
	64206	__ret_238 = (int64x2_t)(vshll_n_s32(vget_high_s32(__s0_238), __p1_238)); \
	64207	__ret_238; \
60896	64208	})
60897	64209	#else
60898		#define vshll_high_n_s32(__p0_227, __p1_227) __extension__ ({ \
60899		int32x4_t __s0_227 = __p0_227; \
60900		int32x4_t __rev0_227; __rev0_227 = __builtin_shufflevector(__s0_227, __s0_227, 3, 2, 1, 0); \
60901		int64x2_t __ret_227; \
60902		__ret_227 = (int64x2_t)(__noswap_vshll_n_s32(__noswap_vget_high_s32(__rev0_227), __p1_227)); \
60903		__ret_227 = __builtin_shufflevector(__ret_227, __ret_227, 1, 0); \
60904		__ret_227; \
	64210	#define vshll_high_n_s32(__p0_239, __p1_239) __extension__ ({ \
	64211	int32x4_t __s0_239 = __p0_239; \
	64212	int32x4_t __rev0_239; __rev0_239 = __builtin_shufflevector(__s0_239, __s0_239, 3, 2, 1, 0); \
	64213	int64x2_t __ret_239; \
	64214	__ret_239 = (int64x2_t)(__noswap_vshll_n_s32(__noswap_vget_high_s32(__rev0_239), __p1_239)); \
	64215	__ret_239 = __builtin_shufflevector(__ret_239, __ret_239, 1, 0); \
	64216	__ret_239; \
60905	64217	})
60906	64218	#endif
60907	64219
60908	64220	#ifdef __LITTLE_ENDIAN__
60909		#define vshll_high_n_s16(__p0_228, __p1_228) __extension__ ({ \
60910		int16x8_t __s0_228 = __p0_228; \
60911		int32x4_t __ret_228; \
60912		__ret_228 = (int32x4_t)(vshll_n_s16(vget_high_s16(__s0_228), __p1_228)); \
60913		__ret_228; \
	64221	#define vshll_high_n_s16(__p0_240, __p1_240) __extension__ ({ \
	64222	int16x8_t __s0_240 = __p0_240; \
	64223	int32x4_t __ret_240; \
	64224	__ret_240 = (int32x4_t)(vshll_n_s16(vget_high_s16(__s0_240), __p1_240)); \
	64225	__ret_240; \
60914	64226	})
60915	64227	#else
60916		#define vshll_high_n_s16(__p0_229, __p1_229) __extension__ ({ \
60917		int16x8_t __s0_229 = __p0_229; \
60918		int16x8_t __rev0_229; __rev0_229 = __builtin_shufflevector(__s0_229, __s0_229, 7, 6, 5, 4, 3, 2, 1, 0); \
60919		int32x4_t __ret_229; \
60920		__ret_229 = (int32x4_t)(__noswap_vshll_n_s16(__noswap_vget_high_s16(__rev0_229), __p1_229)); \
60921		__ret_229 = __builtin_shufflevector(__ret_229, __ret_229, 3, 2, 1, 0); \
60922		__ret_229; \
	64228	#define vshll_high_n_s16(__p0_241, __p1_241) __extension__ ({ \
	64229	int16x8_t __s0_241 = __p0_241; \
	64230	int16x8_t __rev0_241; __rev0_241 = __builtin_shufflevector(__s0_241, __s0_241, 7, 6, 5, 4, 3, 2, 1, 0); \
	64231	int32x4_t __ret_241; \
	64232	__ret_241 = (int32x4_t)(__noswap_vshll_n_s16(__noswap_vget_high_s16(__rev0_241), __p1_241)); \
	64233	__ret_241 = __builtin_shufflevector(__ret_241, __ret_241, 3, 2, 1, 0); \
	64234	__ret_241; \
60923	64235	})
60924	64236	#endif
60925	64237
...	...	@@ -60956,128 +64268,128 @@ __ai int64_t vshld_s64(int64_t __p0, int64_t __p1) {
60956	64268	#endif
60957	64269
60958	64270	#ifdef __LITTLE_ENDIAN__
60959		#define vshrn_high_n_u32(__p0_230, __p1_230, __p2_230) __extension__ ({ \
60960		uint16x4_t __s0_230 = __p0_230; \
60961		uint32x4_t __s1_230 = __p1_230; \
60962		uint16x8_t __ret_230; \
60963		__ret_230 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_230), (uint16x4_t)(vshrn_n_u32(__s1_230, __p2_230)))); \
60964		__ret_230; \
	64271	#define vshrn_high_n_u32(__p0_242, __p1_242, __p2_242) __extension__ ({ \
	64272	uint16x4_t __s0_242 = __p0_242; \
	64273	uint32x4_t __s1_242 = __p1_242; \
	64274	uint16x8_t __ret_242; \
	64275	__ret_242 = (uint16x8_t)(vcombine_u16((uint16x4_t)(__s0_242), (uint16x4_t)(vshrn_n_u32(__s1_242, __p2_242)))); \
	64276	__ret_242; \
60965	64277	})
60966	64278	#else
60967		#define vshrn_high_n_u32(__p0_231, __p1_231, __p2_231) __extension__ ({ \
60968		uint16x4_t __s0_231 = __p0_231; \
60969		uint32x4_t __s1_231 = __p1_231; \
60970		uint16x4_t __rev0_231; __rev0_231 = __builtin_shufflevector(__s0_231, __s0_231, 3, 2, 1, 0); \
60971		uint32x4_t __rev1_231; __rev1_231 = __builtin_shufflevector(__s1_231, __s1_231, 3, 2, 1, 0); \
60972		uint16x8_t __ret_231; \
60973		__ret_231 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_231), (uint16x4_t)(__noswap_vshrn_n_u32(__rev1_231, __p2_231)))); \
60974		__ret_231 = __builtin_shufflevector(__ret_231, __ret_231, 7, 6, 5, 4, 3, 2, 1, 0); \
60975		__ret_231; \
	64279	#define vshrn_high_n_u32(__p0_243, __p1_243, __p2_243) __extension__ ({ \
	64280	uint16x4_t __s0_243 = __p0_243; \
	64281	uint32x4_t __s1_243 = __p1_243; \
	64282	uint16x4_t __rev0_243; __rev0_243 = __builtin_shufflevector(__s0_243, __s0_243, 3, 2, 1, 0); \
	64283	uint32x4_t __rev1_243; __rev1_243 = __builtin_shufflevector(__s1_243, __s1_243, 3, 2, 1, 0); \
	64284	uint16x8_t __ret_243; \
	64285	__ret_243 = (uint16x8_t)(__noswap_vcombine_u16((uint16x4_t)(__rev0_243), (uint16x4_t)(__noswap_vshrn_n_u32(__rev1_243, __p2_243)))); \
	64286	__ret_243 = __builtin_shufflevector(__ret_243, __ret_243, 7, 6, 5, 4, 3, 2, 1, 0); \
	64287	__ret_243; \
60976	64288	})
60977	64289	#endif
60978	64290
60979	64291	#ifdef __LITTLE_ENDIAN__
60980		#define vshrn_high_n_u64(__p0_232, __p1_232, __p2_232) __extension__ ({ \
60981		uint32x2_t __s0_232 = __p0_232; \
60982		uint64x2_t __s1_232 = __p1_232; \
60983		uint32x4_t __ret_232; \
60984		__ret_232 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_232), (uint32x2_t)(vshrn_n_u64(__s1_232, __p2_232)))); \
60985		__ret_232; \
	64292	#define vshrn_high_n_u64(__p0_244, __p1_244, __p2_244) __extension__ ({ \
	64293	uint32x2_t __s0_244 = __p0_244; \
	64294	uint64x2_t __s1_244 = __p1_244; \
	64295	uint32x4_t __ret_244; \
	64296	__ret_244 = (uint32x4_t)(vcombine_u32((uint32x2_t)(__s0_244), (uint32x2_t)(vshrn_n_u64(__s1_244, __p2_244)))); \
	64297	__ret_244; \
60986	64298	})
60987	64299	#else
60988		#define vshrn_high_n_u64(__p0_233, __p1_233, __p2_233) __extension__ ({ \
60989		uint32x2_t __s0_233 = __p0_233; \
60990		uint64x2_t __s1_233 = __p1_233; \
60991		uint32x2_t __rev0_233; __rev0_233 = __builtin_shufflevector(__s0_233, __s0_233, 1, 0); \
60992		uint64x2_t __rev1_233; __rev1_233 = __builtin_shufflevector(__s1_233, __s1_233, 1, 0); \
60993		uint32x4_t __ret_233; \
60994		__ret_233 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_233), (uint32x2_t)(__noswap_vshrn_n_u64(__rev1_233, __p2_233)))); \
60995		__ret_233 = __builtin_shufflevector(__ret_233, __ret_233, 3, 2, 1, 0); \
60996		__ret_233; \
	64300	#define vshrn_high_n_u64(__p0_245, __p1_245, __p2_245) __extension__ ({ \
	64301	uint32x2_t __s0_245 = __p0_245; \
	64302	uint64x2_t __s1_245 = __p1_245; \
	64303	uint32x2_t __rev0_245; __rev0_245 = __builtin_shufflevector(__s0_245, __s0_245, 1, 0); \
	64304	uint64x2_t __rev1_245; __rev1_245 = __builtin_shufflevector(__s1_245, __s1_245, 1, 0); \
	64305	uint32x4_t __ret_245; \
	64306	__ret_245 = (uint32x4_t)(__noswap_vcombine_u32((uint32x2_t)(__rev0_245), (uint32x2_t)(__noswap_vshrn_n_u64(__rev1_245, __p2_245)))); \
	64307	__ret_245 = __builtin_shufflevector(__ret_245, __ret_245, 3, 2, 1, 0); \
	64308	__ret_245; \
60997	64309	})
60998	64310	#endif
60999	64311
61000	64312	#ifdef __LITTLE_ENDIAN__
61001		#define vshrn_high_n_u16(__p0_234, __p1_234, __p2_234) __extension__ ({ \
61002		uint8x8_t __s0_234 = __p0_234; \
61003		uint16x8_t __s1_234 = __p1_234; \
61004		uint8x16_t __ret_234; \
61005		__ret_234 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_234), (uint8x8_t)(vshrn_n_u16(__s1_234, __p2_234)))); \
61006		__ret_234; \
	64313	#define vshrn_high_n_u16(__p0_246, __p1_246, __p2_246) __extension__ ({ \
	64314	uint8x8_t __s0_246 = __p0_246; \
	64315	uint16x8_t __s1_246 = __p1_246; \
	64316	uint8x16_t __ret_246; \
	64317	__ret_246 = (uint8x16_t)(vcombine_u8((uint8x8_t)(__s0_246), (uint8x8_t)(vshrn_n_u16(__s1_246, __p2_246)))); \
	64318	__ret_246; \
61007	64319	})
61008	64320	#else
61009		#define vshrn_high_n_u16(__p0_235, __p1_235, __p2_235) __extension__ ({ \
61010		uint8x8_t __s0_235 = __p0_235; \
61011		uint16x8_t __s1_235 = __p1_235; \
61012		uint8x8_t __rev0_235; __rev0_235 = __builtin_shufflevector(__s0_235, __s0_235, 7, 6, 5, 4, 3, 2, 1, 0); \
61013		uint16x8_t __rev1_235; __rev1_235 = __builtin_shufflevector(__s1_235, __s1_235, 7, 6, 5, 4, 3, 2, 1, 0); \
61014		uint8x16_t __ret_235; \
61015		__ret_235 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_235), (uint8x8_t)(__noswap_vshrn_n_u16(__rev1_235, __p2_235)))); \
61016		__ret_235 = __builtin_shufflevector(__ret_235, __ret_235, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
61017		__ret_235; \
	64321	#define vshrn_high_n_u16(__p0_247, __p1_247, __p2_247) __extension__ ({ \
	64322	uint8x8_t __s0_247 = __p0_247; \
	64323	uint16x8_t __s1_247 = __p1_247; \
	64324	uint8x8_t __rev0_247; __rev0_247 = __builtin_shufflevector(__s0_247, __s0_247, 7, 6, 5, 4, 3, 2, 1, 0); \
	64325	uint16x8_t __rev1_247; __rev1_247 = __builtin_shufflevector(__s1_247, __s1_247, 7, 6, 5, 4, 3, 2, 1, 0); \
	64326	uint8x16_t __ret_247; \
	64327	__ret_247 = (uint8x16_t)(__noswap_vcombine_u8((uint8x8_t)(__rev0_247), (uint8x8_t)(__noswap_vshrn_n_u16(__rev1_247, __p2_247)))); \
	64328	__ret_247 = __builtin_shufflevector(__ret_247, __ret_247, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	64329	__ret_247; \
61018	64330	})
61019	64331	#endif
61020	64332
61021	64333	#ifdef __LITTLE_ENDIAN__
61022		#define vshrn_high_n_s32(__p0_236, __p1_236, __p2_236) __extension__ ({ \
61023		int16x4_t __s0_236 = __p0_236; \
61024		int32x4_t __s1_236 = __p1_236; \
61025		int16x8_t __ret_236; \
61026		__ret_236 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_236), (int16x4_t)(vshrn_n_s32(__s1_236, __p2_236)))); \
61027		__ret_236; \
	64334	#define vshrn_high_n_s32(__p0_248, __p1_248, __p2_248) __extension__ ({ \
	64335	int16x4_t __s0_248 = __p0_248; \
	64336	int32x4_t __s1_248 = __p1_248; \
	64337	int16x8_t __ret_248; \
	64338	__ret_248 = (int16x8_t)(vcombine_s16((int16x4_t)(__s0_248), (int16x4_t)(vshrn_n_s32(__s1_248, __p2_248)))); \
	64339	__ret_248; \
61028	64340	})
61029	64341	#else
61030		#define vshrn_high_n_s32(__p0_237, __p1_237, __p2_237) __extension__ ({ \
61031		int16x4_t __s0_237 = __p0_237; \
61032		int32x4_t __s1_237 = __p1_237; \
61033		int16x4_t __rev0_237; __rev0_237 = __builtin_shufflevector(__s0_237, __s0_237, 3, 2, 1, 0); \
61034		int32x4_t __rev1_237; __rev1_237 = __builtin_shufflevector(__s1_237, __s1_237, 3, 2, 1, 0); \
61035		int16x8_t __ret_237; \
61036		__ret_237 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_237), (int16x4_t)(__noswap_vshrn_n_s32(__rev1_237, __p2_237)))); \
61037		__ret_237 = __builtin_shufflevector(__ret_237, __ret_237, 7, 6, 5, 4, 3, 2, 1, 0); \
61038		__ret_237; \
	64342	#define vshrn_high_n_s32(__p0_249, __p1_249, __p2_249) __extension__ ({ \
	64343	int16x4_t __s0_249 = __p0_249; \
	64344	int32x4_t __s1_249 = __p1_249; \
	64345	int16x4_t __rev0_249; __rev0_249 = __builtin_shufflevector(__s0_249, __s0_249, 3, 2, 1, 0); \
	64346	int32x4_t __rev1_249; __rev1_249 = __builtin_shufflevector(__s1_249, __s1_249, 3, 2, 1, 0); \
	64347	int16x8_t __ret_249; \
	64348	__ret_249 = (int16x8_t)(__noswap_vcombine_s16((int16x4_t)(__rev0_249), (int16x4_t)(__noswap_vshrn_n_s32(__rev1_249, __p2_249)))); \
	64349	__ret_249 = __builtin_shufflevector(__ret_249, __ret_249, 7, 6, 5, 4, 3, 2, 1, 0); \
	64350	__ret_249; \
61039	64351	})
61040	64352	#endif
61041	64353
61042	64354	#ifdef __LITTLE_ENDIAN__
61043		#define vshrn_high_n_s64(__p0_238, __p1_238, __p2_238) __extension__ ({ \
61044		int32x2_t __s0_238 = __p0_238; \
61045		int64x2_t __s1_238 = __p1_238; \
61046		int32x4_t __ret_238; \
61047		__ret_238 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_238), (int32x2_t)(vshrn_n_s64(__s1_238, __p2_238)))); \
61048		__ret_238; \
	64355	#define vshrn_high_n_s64(__p0_250, __p1_250, __p2_250) __extension__ ({ \
	64356	int32x2_t __s0_250 = __p0_250; \
	64357	int64x2_t __s1_250 = __p1_250; \
	64358	int32x4_t __ret_250; \
	64359	__ret_250 = (int32x4_t)(vcombine_s32((int32x2_t)(__s0_250), (int32x2_t)(vshrn_n_s64(__s1_250, __p2_250)))); \
	64360	__ret_250; \
61049	64361	})
61050	64362	#else
61051		#define vshrn_high_n_s64(__p0_239, __p1_239, __p2_239) __extension__ ({ \
61052		int32x2_t __s0_239 = __p0_239; \
61053		int64x2_t __s1_239 = __p1_239; \
61054		int32x2_t __rev0_239; __rev0_239 = __builtin_shufflevector(__s0_239, __s0_239, 1, 0); \
61055		int64x2_t __rev1_239; __rev1_239 = __builtin_shufflevector(__s1_239, __s1_239, 1, 0); \
61056		int32x4_t __ret_239; \
61057		__ret_239 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_239), (int32x2_t)(__noswap_vshrn_n_s64(__rev1_239, __p2_239)))); \
61058		__ret_239 = __builtin_shufflevector(__ret_239, __ret_239, 3, 2, 1, 0); \
61059		__ret_239; \
	64363	#define vshrn_high_n_s64(__p0_251, __p1_251, __p2_251) __extension__ ({ \
	64364	int32x2_t __s0_251 = __p0_251; \
	64365	int64x2_t __s1_251 = __p1_251; \
	64366	int32x2_t __rev0_251; __rev0_251 = __builtin_shufflevector(__s0_251, __s0_251, 1, 0); \
	64367	int64x2_t __rev1_251; __rev1_251 = __builtin_shufflevector(__s1_251, __s1_251, 1, 0); \
	64368	int32x4_t __ret_251; \
	64369	__ret_251 = (int32x4_t)(__noswap_vcombine_s32((int32x2_t)(__rev0_251), (int32x2_t)(__noswap_vshrn_n_s64(__rev1_251, __p2_251)))); \
	64370	__ret_251 = __builtin_shufflevector(__ret_251, __ret_251, 3, 2, 1, 0); \
	64371	__ret_251; \
61060	64372	})
61061	64373	#endif
61062	64374
61063	64375	#ifdef __LITTLE_ENDIAN__
61064		#define vshrn_high_n_s16(__p0_240, __p1_240, __p2_240) __extension__ ({ \
61065		int8x8_t __s0_240 = __p0_240; \
61066		int16x8_t __s1_240 = __p1_240; \
61067		int8x16_t __ret_240; \
61068		__ret_240 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_240), (int8x8_t)(vshrn_n_s16(__s1_240, __p2_240)))); \
61069		__ret_240; \
	64376	#define vshrn_high_n_s16(__p0_252, __p1_252, __p2_252) __extension__ ({ \
	64377	int8x8_t __s0_252 = __p0_252; \
	64378	int16x8_t __s1_252 = __p1_252; \
	64379	int8x16_t __ret_252; \
	64380	__ret_252 = (int8x16_t)(vcombine_s8((int8x8_t)(__s0_252), (int8x8_t)(vshrn_n_s16(__s1_252, __p2_252)))); \
	64381	__ret_252; \
61070	64382	})
61071	64383	#else
61072		#define vshrn_high_n_s16(__p0_241, __p1_241, __p2_241) __extension__ ({ \
61073		int8x8_t __s0_241 = __p0_241; \
61074		int16x8_t __s1_241 = __p1_241; \
61075		int8x8_t __rev0_241; __rev0_241 = __builtin_shufflevector(__s0_241, __s0_241, 7, 6, 5, 4, 3, 2, 1, 0); \
61076		int16x8_t __rev1_241; __rev1_241 = __builtin_shufflevector(__s1_241, __s1_241, 7, 6, 5, 4, 3, 2, 1, 0); \
61077		int8x16_t __ret_241; \
61078		__ret_241 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_241), (int8x8_t)(__noswap_vshrn_n_s16(__rev1_241, __p2_241)))); \
61079		__ret_241 = __builtin_shufflevector(__ret_241, __ret_241, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
61080		__ret_241; \
	64384	#define vshrn_high_n_s16(__p0_253, __p1_253, __p2_253) __extension__ ({ \
	64385	int8x8_t __s0_253 = __p0_253; \
	64386	int16x8_t __s1_253 = __p1_253; \
	64387	int8x8_t __rev0_253; __rev0_253 = __builtin_shufflevector(__s0_253, __s0_253, 7, 6, 5, 4, 3, 2, 1, 0); \
	64388	int16x8_t __rev1_253; __rev1_253 = __builtin_shufflevector(__s1_253, __s1_253, 7, 6, 5, 4, 3, 2, 1, 0); \
	64389	int8x16_t __ret_253; \
	64390	__ret_253 = (int8x16_t)(__noswap_vcombine_s8((int8x8_t)(__rev0_253), (int8x8_t)(__noswap_vshrn_n_s16(__rev1_253, __p2_253)))); \
	64391	__ret_253 = __builtin_shufflevector(__ret_253, __ret_253, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); \
	64392	__ret_253; \
61081	64393	})
61082	64394	#endif
61083	64395
...	...	@@ -67149,44 +70461,60 @@ __ai int32x4_t vaddw_s16(int32x4_t __p0, int16x4_t __p1) {
67149	70461	#endif
67150	70462
67151	70463	#ifdef __LITTLE_ENDIAN__
67152		#define vget_lane_f16(__p0_242, __p1_242) __extension__ ({ \
67153		float16x4_t __s0_242 = __p0_242; \
67154		float16_t __ret_242; \
67155		float16x4_t __reint_242 = __s0_242; \
67156		int16_t __reint1_242 = vget_lane_s16((int16x4_t ) &__reint_242, __p1_242); \
67157		__ret_242 = (float16_t ) &__reint1_242; \
67158		__ret_242; \
	70464	#define vget_lane_f16(__p0_254, __p1_254) __extension__ ({ \
	70465	float16x4_t __s0_254 = __p0_254; \
	70466	float16_t __ret_254; \
	70467	float16x4_t __reint_254 = __s0_254; \
	70468	int16_t __reint1_254 = vget_lane_s16((int16x4_t ) &__reint_254, __p1_254); \
	70469	__ret_254 = (float16_t ) &__reint1_254; \
	70470	__ret_254; \
67159	70471	})
67160	70472	#else
67161		#define vget_lane_f16(__p0_243, __p1_243) __extension__ ({ \
67162		float16x4_t __s0_243 = __p0_243; \
67163		float16x4_t __rev0_243; __rev0_243 = __builtin_shufflevector(__s0_243, __s0_243, 3, 2, 1, 0); \
67164		float16_t __ret_243; \
67165		float16x4_t __reint_243 = __rev0_243; \
67166		int16_t __reint1_243 = __noswap_vget_lane_s16((int16x4_t ) &__reint_243, __p1_243); \
67167		__ret_243 = (float16_t ) &__reint1_243; \
67168		__ret_243; \
	70473	#define vget_lane_f16(__p0_255, __p1_255) __extension__ ({ \
	70474	float16x4_t __s0_255 = __p0_255; \
	70475	float16x4_t __rev0_255; __rev0_255 = __builtin_shufflevector(__s0_255, __s0_255, 3, 2, 1, 0); \
	70476	float16_t __ret_255; \
	70477	float16x4_t __reint_255 = __rev0_255; \
	70478	int16_t __reint1_255 = __noswap_vget_lane_s16((int16x4_t ) &__reint_255, __p1_255); \
	70479	__ret_255 = (float16_t ) &__reint1_255; \
	70480	__ret_255; \
	70481	})
	70482	#define __noswap_vget_lane_f16(__p0_256, __p1_256) __extension__ ({ \
	70483	float16x4_t __s0_256 = __p0_256; \
	70484	float16_t __ret_256; \
	70485	float16x4_t __reint_256 = __s0_256; \
	70486	int16_t __reint1_256 = __noswap_vget_lane_s16((int16x4_t ) &__reint_256, __p1_256); \
	70487	__ret_256 = (float16_t ) &__reint1_256; \
	70488	__ret_256; \
67169	70489	})
67170	70490	#endif
67171	70491
67172	70492	#ifdef __LITTLE_ENDIAN__
67173		#define vgetq_lane_f16(__p0_244, __p1_244) __extension__ ({ \
67174		float16x8_t __s0_244 = __p0_244; \
67175		float16_t __ret_244; \
67176		float16x8_t __reint_244 = __s0_244; \
67177		int16_t __reint1_244 = vgetq_lane_s16((int16x8_t ) &__reint_244, __p1_244); \
67178		__ret_244 = (float16_t ) &__reint1_244; \
67179		__ret_244; \
	70493	#define vgetq_lane_f16(__p0_257, __p1_257) __extension__ ({ \
	70494	float16x8_t __s0_257 = __p0_257; \
	70495	float16_t __ret_257; \
	70496	float16x8_t __reint_257 = __s0_257; \
	70497	int16_t __reint1_257 = vgetq_lane_s16((int16x8_t ) &__reint_257, __p1_257); \
	70498	__ret_257 = (float16_t ) &__reint1_257; \
	70499	__ret_257; \
67180	70500	})
67181	70501	#else
67182		#define vgetq_lane_f16(__p0_245, __p1_245) __extension__ ({ \
67183		float16x8_t __s0_245 = __p0_245; \
67184		float16x8_t __rev0_245; __rev0_245 = __builtin_shufflevector(__s0_245, __s0_245, 7, 6, 5, 4, 3, 2, 1, 0); \
67185		float16_t __ret_245; \
67186		float16x8_t __reint_245 = __rev0_245; \
67187		int16_t __reint1_245 = __noswap_vgetq_lane_s16((int16x8_t ) &__reint_245, __p1_245); \
67188		__ret_245 = (float16_t ) &__reint1_245; \
67189		__ret_245; \
	70502	#define vgetq_lane_f16(__p0_258, __p1_258) __extension__ ({ \
	70503	float16x8_t __s0_258 = __p0_258; \
	70504	float16x8_t __rev0_258; __rev0_258 = __builtin_shufflevector(__s0_258, __s0_258, 7, 6, 5, 4, 3, 2, 1, 0); \
	70505	float16_t __ret_258; \
	70506	float16x8_t __reint_258 = __rev0_258; \
	70507	int16_t __reint1_258 = __noswap_vgetq_lane_s16((int16x8_t ) &__reint_258, __p1_258); \
	70508	__ret_258 = (float16_t ) &__reint1_258; \
	70509	__ret_258; \
	70510	})
	70511	#define __noswap_vgetq_lane_f16(__p0_259, __p1_259) __extension__ ({ \
	70512	float16x8_t __s0_259 = __p0_259; \
	70513	float16_t __ret_259; \
	70514	float16x8_t __reint_259 = __s0_259; \
	70515	int16_t __reint1_259 = __noswap_vgetq_lane_s16((int16x8_t ) &__reint_259, __p1_259); \
	70516	__ret_259 = (float16_t ) &__reint1_259; \
	70517	__ret_259; \
67190	70518	})
67191	70519	#endif
67192	70520
...	...	@@ -67835,57 +71163,97 @@ __ai int32x4_t __noswap_vmlsl_n_s16(int32x4_t __p0, int16x4_t __p1, int16_t __p2
67835	71163	#endif
67836	71164
67837	71165	#ifdef __LITTLE_ENDIAN__
67838		#define vset_lane_f16(__p0_246, __p1_246, __p2_246) __extension__ ({ \
67839		float16_t __s0_246 = __p0_246; \
67840		float16x4_t __s1_246 = __p1_246; \
67841		float16x4_t __ret_246; \
67842		float16_t __reint_246 = __s0_246; \
67843		float16x4_t __reint1_246 = __s1_246; \
67844		int16x4_t __reint2_246 = vset_lane_s16((int16_t ) &__reint_246, (int16x4_t ) &__reint1_246, __p2_246); \
67845		__ret_246 = (float16x4_t ) &__reint2_246; \
67846		__ret_246; \
	71166	#define vset_lane_f16(__p0_260, __p1_260, __p2_260) __extension__ ({ \
	71167	float16_t __s0_260 = __p0_260; \
	71168	float16x4_t __s1_260 = __p1_260; \
	71169	float16x4_t __ret_260; \
	71170	float16_t __reint_260 = __s0_260; \
	71171	float16x4_t __reint1_260 = __s1_260; \
	71172	int16x4_t __reint2_260 = vset_lane_s16((int16_t ) &__reint_260, (int16x4_t ) &__reint1_260, __p2_260); \
	71173	__ret_260 = (float16x4_t ) &__reint2_260; \
	71174	__ret_260; \
67847	71175	})
67848	71176	#else
67849		#define vset_lane_f16(__p0_247, __p1_247, __p2_247) __extension__ ({ \
67850		float16_t __s0_247 = __p0_247; \
67851		float16x4_t __s1_247 = __p1_247; \
67852		float16x4_t __rev1_247; __rev1_247 = __builtin_shufflevector(__s1_247, __s1_247, 3, 2, 1, 0); \
67853		float16x4_t __ret_247; \
67854		float16_t __reint_247 = __s0_247; \
67855		float16x4_t __reint1_247 = __rev1_247; \
67856		int16x4_t __reint2_247 = __noswap_vset_lane_s16((int16_t ) &__reint_247, (int16x4_t ) &__reint1_247, __p2_247); \
67857		__ret_247 = (float16x4_t ) &__reint2_247; \
67858		__ret_247 = __builtin_shufflevector(__ret_247, __ret_247, 3, 2, 1, 0); \
67859		__ret_247; \
	71177	#define vset_lane_f16(__p0_261, __p1_261, __p2_261) __extension__ ({ \
	71178	float16_t __s0_261 = __p0_261; \
	71179	float16x4_t __s1_261 = __p1_261; \
	71180	float16x4_t __rev1_261; __rev1_261 = __builtin_shufflevector(__s1_261, __s1_261, 3, 2, 1, 0); \
	71181	float16x4_t __ret_261; \
	71182	float16_t __reint_261 = __s0_261; \
	71183	float16x4_t __reint1_261 = __rev1_261; \
	71184	int16x4_t __reint2_261 = __noswap_vset_lane_s16((int16_t ) &__reint_261, (int16x4_t ) &__reint1_261, __p2_261); \
	71185	__ret_261 = (float16x4_t ) &__reint2_261; \
	71186	__ret_261 = __builtin_shufflevector(__ret_261, __ret_261, 3, 2, 1, 0); \
	71187	__ret_261; \
67860	71188	})
67861	71189	#endif
67862	71190
67863	71191	#ifdef __LITTLE_ENDIAN__
67864		#define vsetq_lane_f16(__p0_248, __p1_248, __p2_248) __extension__ ({ \
67865		float16_t __s0_248 = __p0_248; \
67866		float16x8_t __s1_248 = __p1_248; \
67867		float16x8_t __ret_248; \
67868		float16_t __reint_248 = __s0_248; \
67869		float16x8_t __reint1_248 = __s1_248; \
67870		int16x8_t __reint2_248 = vsetq_lane_s16((int16_t ) &__reint_248, (int16x8_t ) &__reint1_248, __p2_248); \
67871		__ret_248 = (float16x8_t ) &__reint2_248; \
67872		__ret_248; \
	71192	#define vsetq_lane_f16(__p0_262, __p1_262, __p2_262) __extension__ ({ \
	71193	float16_t __s0_262 = __p0_262; \
	71194	float16x8_t __s1_262 = __p1_262; \
	71195	float16x8_t __ret_262; \
	71196	float16_t __reint_262 = __s0_262; \
	71197	float16x8_t __reint1_262 = __s1_262; \
	71198	int16x8_t __reint2_262 = vsetq_lane_s16((int16_t ) &__reint_262, (int16x8_t ) &__reint1_262, __p2_262); \
	71199	__ret_262 = (float16x8_t ) &__reint2_262; \
	71200	__ret_262; \
67873	71201	})
67874	71202	#else
67875		#define vsetq_lane_f16(__p0_249, __p1_249, __p2_249) __extension__ ({ \
67876		float16_t __s0_249 = __p0_249; \
67877		float16x8_t __s1_249 = __p1_249; \
67878		float16x8_t __rev1_249; __rev1_249 = __builtin_shufflevector(__s1_249, __s1_249, 7, 6, 5, 4, 3, 2, 1, 0); \
67879		float16x8_t __ret_249; \
67880		float16_t __reint_249 = __s0_249; \
67881		float16x8_t __reint1_249 = __rev1_249; \
67882		int16x8_t __reint2_249 = __noswap_vsetq_lane_s16((int16_t ) &__reint_249, (int16x8_t ) &__reint1_249, __p2_249); \
67883		__ret_249 = (float16x8_t ) &__reint2_249; \
67884		__ret_249 = __builtin_shufflevector(__ret_249, __ret_249, 7, 6, 5, 4, 3, 2, 1, 0); \
67885		__ret_249; \
	71203	#define vsetq_lane_f16(__p0_263, __p1_263, __p2_263) __extension__ ({ \
	71204	float16_t __s0_263 = __p0_263; \
	71205	float16x8_t __s1_263 = __p1_263; \
	71206	float16x8_t __rev1_263; __rev1_263 = __builtin_shufflevector(__s1_263, __s1_263, 7, 6, 5, 4, 3, 2, 1, 0); \
	71207	float16x8_t __ret_263; \
	71208	float16_t __reint_263 = __s0_263; \
	71209	float16x8_t __reint1_263 = __rev1_263; \
	71210	int16x8_t __reint2_263 = __noswap_vsetq_lane_s16((int16_t ) &__reint_263, (int16x8_t ) &__reint1_263, __p2_263); \
	71211	__ret_263 = (float16x8_t ) &__reint2_263; \
	71212	__ret_263 = __builtin_shufflevector(__ret_263, __ret_263, 7, 6, 5, 4, 3, 2, 1, 0); \
	71213	__ret_263; \
	71214	})
	71215	#endif
	71216
	71217	#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)
	71218	#ifdef __LITTLE_ENDIAN__
	71219	#define vmulh_lane_f16(__p0_264, __p1_264, __p2_264) __extension__ ({ \
	71220	float16_t __s0_264 = __p0_264; \
	71221	float16x4_t __s1_264 = __p1_264; \
	71222	float16_t __ret_264; \
	71223	__ret_264 = __s0_264 * vget_lane_f16(__s1_264, __p2_264); \
	71224	__ret_264; \
	71225	})
	71226	#else
	71227	#define vmulh_lane_f16(__p0_265, __p1_265, __p2_265) __extension__ ({ \
	71228	float16_t __s0_265 = __p0_265; \
	71229	float16x4_t __s1_265 = __p1_265; \
	71230	float16x4_t __rev1_265; __rev1_265 = __builtin_shufflevector(__s1_265, __s1_265, 3, 2, 1, 0); \
	71231	float16_t __ret_265; \
	71232	__ret_265 = __s0_265 * __noswap_vget_lane_f16(__rev1_265, __p2_265); \
	71233	__ret_265; \
	71234	})
	71235	#endif
	71236
	71237	#ifdef __LITTLE_ENDIAN__
	71238	#define vmulh_laneq_f16(__p0_266, __p1_266, __p2_266) __extension__ ({ \
	71239	float16_t __s0_266 = __p0_266; \
	71240	float16x8_t __s1_266 = __p1_266; \
	71241	float16_t __ret_266; \
	71242	__ret_266 = __s0_266 * vgetq_lane_f16(__s1_266, __p2_266); \
	71243	__ret_266; \
	71244	})
	71245	#else
	71246	#define vmulh_laneq_f16(__p0_267, __p1_267, __p2_267) __extension__ ({ \
	71247	float16_t __s0_267 = __p0_267; \
	71248	float16x8_t __s1_267 = __p1_267; \
	71249	float16x8_t __rev1_267; __rev1_267 = __builtin_shufflevector(__s1_267, __s1_267, 7, 6, 5, 4, 3, 2, 1, 0); \
	71250	float16_t __ret_267; \
	71251	__ret_267 = __s0_267 * __noswap_vgetq_lane_f16(__rev1_267, __p2_267); \
	71252	__ret_267; \
67886	71253	})
67887	71254	#endif
67888	71255
	71256	#endif
67889	71257	#if defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)
67890	71258	#ifdef __LITTLE_ENDIAN__
67891	71259	__ai int32_t vqrdmlahs_s32(int32_t __p0, int32_t __p1, int32_t __p2) {
...	...	@@ -67916,86 +71284,86 @@ __ai int16_t vqrdmlahh_s16(int16_t __p0, int16_t __p1, int16_t __p2) {
67916	71284	#endif
67917	71285
67918	71286	#ifdef __LITTLE_ENDIAN__
67919		#define vqrdmlahs_lane_s32(__p0_250, __p1_250, __p2_250, __p3_250) __extension__ ({ \
67920		int32_t __s0_250 = __p0_250; \
67921		int32_t __s1_250 = __p1_250; \
67922		int32x2_t __s2_250 = __p2_250; \
67923		int32_t __ret_250; \
67924		__ret_250 = vqadds_s32(__s0_250, vqrdmulhs_s32(__s1_250, vget_lane_s32(__s2_250, __p3_250))); \
67925		__ret_250; \
	71287	#define vqrdmlahs_lane_s32(__p0_268, __p1_268, __p2_268, __p3_268) __extension__ ({ \
	71288	int32_t __s0_268 = __p0_268; \
	71289	int32_t __s1_268 = __p1_268; \
	71290	int32x2_t __s2_268 = __p2_268; \
	71291	int32_t __ret_268; \
	71292	__ret_268 = vqadds_s32(__s0_268, vqrdmulhs_s32(__s1_268, vget_lane_s32(__s2_268, __p3_268))); \
	71293	__ret_268; \
67926	71294	})
67927	71295	#else
67928		#define vqrdmlahs_lane_s32(__p0_251, __p1_251, __p2_251, __p3_251) __extension__ ({ \
67929		int32_t __s0_251 = __p0_251; \
67930		int32_t __s1_251 = __p1_251; \
67931		int32x2_t __s2_251 = __p2_251; \
67932		int32x2_t __rev2_251; __rev2_251 = __builtin_shufflevector(__s2_251, __s2_251, 1, 0); \
67933		int32_t __ret_251; \
67934		__ret_251 = __noswap_vqadds_s32(__s0_251, __noswap_vqrdmulhs_s32(__s1_251, __noswap_vget_lane_s32(__rev2_251, __p3_251))); \
67935		__ret_251; \
	71296	#define vqrdmlahs_lane_s32(__p0_269, __p1_269, __p2_269, __p3_269) __extension__ ({ \
	71297	int32_t __s0_269 = __p0_269; \
	71298	int32_t __s1_269 = __p1_269; \
	71299	int32x2_t __s2_269 = __p2_269; \
	71300	int32x2_t __rev2_269; __rev2_269 = __builtin_shufflevector(__s2_269, __s2_269, 1, 0); \
	71301	int32_t __ret_269; \
	71302	__ret_269 = __noswap_vqadds_s32(__s0_269, __noswap_vqrdmulhs_s32(__s1_269, __noswap_vget_lane_s32(__rev2_269, __p3_269))); \
	71303	__ret_269; \
67936	71304	})
67937	71305	#endif
67938	71306
67939	71307	#ifdef __LITTLE_ENDIAN__
67940		#define vqrdmlahh_lane_s16(__p0_252, __p1_252, __p2_252, __p3_252) __extension__ ({ \
67941		int16_t __s0_252 = __p0_252; \
67942		int16_t __s1_252 = __p1_252; \
67943		int16x4_t __s2_252 = __p2_252; \
67944		int16_t __ret_252; \
67945		__ret_252 = vqaddh_s16(__s0_252, vqrdmulhh_s16(__s1_252, vget_lane_s16(__s2_252, __p3_252))); \
67946		__ret_252; \
	71308	#define vqrdmlahh_lane_s16(__p0_270, __p1_270, __p2_270, __p3_270) __extension__ ({ \
	71309	int16_t __s0_270 = __p0_270; \
	71310	int16_t __s1_270 = __p1_270; \
	71311	int16x4_t __s2_270 = __p2_270; \
	71312	int16_t __ret_270; \
	71313	__ret_270 = vqaddh_s16(__s0_270, vqrdmulhh_s16(__s1_270, vget_lane_s16(__s2_270, __p3_270))); \
	71314	__ret_270; \
67947	71315	})
67948	71316	#else
67949		#define vqrdmlahh_lane_s16(__p0_253, __p1_253, __p2_253, __p3_253) __extension__ ({ \
67950		int16_t __s0_253 = __p0_253; \
67951		int16_t __s1_253 = __p1_253; \
67952		int16x4_t __s2_253 = __p2_253; \
67953		int16x4_t __rev2_253; __rev2_253 = __builtin_shufflevector(__s2_253, __s2_253, 3, 2, 1, 0); \
67954		int16_t __ret_253; \
67955		__ret_253 = __noswap_vqaddh_s16(__s0_253, __noswap_vqrdmulhh_s16(__s1_253, __noswap_vget_lane_s16(__rev2_253, __p3_253))); \
67956		__ret_253; \
	71317	#define vqrdmlahh_lane_s16(__p0_271, __p1_271, __p2_271, __p3_271) __extension__ ({ \
	71318	int16_t __s0_271 = __p0_271; \
	71319	int16_t __s1_271 = __p1_271; \
	71320	int16x4_t __s2_271 = __p2_271; \
	71321	int16x4_t __rev2_271; __rev2_271 = __builtin_shufflevector(__s2_271, __s2_271, 3, 2, 1, 0); \
	71322	int16_t __ret_271; \
	71323	__ret_271 = __noswap_vqaddh_s16(__s0_271, __noswap_vqrdmulhh_s16(__s1_271, __noswap_vget_lane_s16(__rev2_271, __p3_271))); \
	71324	__ret_271; \
67957	71325	})
67958	71326	#endif
67959	71327
67960	71328	#ifdef __LITTLE_ENDIAN__
67961		#define vqrdmlahs_laneq_s32(__p0_254, __p1_254, __p2_254, __p3_254) __extension__ ({ \
67962		int32_t __s0_254 = __p0_254; \
67963		int32_t __s1_254 = __p1_254; \
67964		int32x4_t __s2_254 = __p2_254; \
67965		int32_t __ret_254; \
67966		__ret_254 = vqadds_s32(__s0_254, vqrdmulhs_s32(__s1_254, vgetq_lane_s32(__s2_254, __p3_254))); \
67967		__ret_254; \
	71329	#define vqrdmlahs_laneq_s32(__p0_272, __p1_272, __p2_272, __p3_272) __extension__ ({ \
	71330	int32_t __s0_272 = __p0_272; \
	71331	int32_t __s1_272 = __p1_272; \
	71332	int32x4_t __s2_272 = __p2_272; \
	71333	int32_t __ret_272; \
	71334	__ret_272 = vqadds_s32(__s0_272, vqrdmulhs_s32(__s1_272, vgetq_lane_s32(__s2_272, __p3_272))); \
	71335	__ret_272; \
67968	71336	})
67969	71337	#else
67970		#define vqrdmlahs_laneq_s32(__p0_255, __p1_255, __p2_255, __p3_255) __extension__ ({ \
67971		int32_t __s0_255 = __p0_255; \
67972		int32_t __s1_255 = __p1_255; \
67973		int32x4_t __s2_255 = __p2_255; \
67974		int32x4_t __rev2_255; __rev2_255 = __builtin_shufflevector(__s2_255, __s2_255, 3, 2, 1, 0); \
67975		int32_t __ret_255; \
67976		__ret_255 = __noswap_vqadds_s32(__s0_255, __noswap_vqrdmulhs_s32(__s1_255, __noswap_vgetq_lane_s32(__rev2_255, __p3_255))); \
67977		__ret_255; \
	71338	#define vqrdmlahs_laneq_s32(__p0_273, __p1_273, __p2_273, __p3_273) __extension__ ({ \
	71339	int32_t __s0_273 = __p0_273; \
	71340	int32_t __s1_273 = __p1_273; \
	71341	int32x4_t __s2_273 = __p2_273; \
	71342	int32x4_t __rev2_273; __rev2_273 = __builtin_shufflevector(__s2_273, __s2_273, 3, 2, 1, 0); \
	71343	int32_t __ret_273; \
	71344	__ret_273 = __noswap_vqadds_s32(__s0_273, __noswap_vqrdmulhs_s32(__s1_273, __noswap_vgetq_lane_s32(__rev2_273, __p3_273))); \
	71345	__ret_273; \
67978	71346	})
67979	71347	#endif
67980	71348
67981	71349	#ifdef __LITTLE_ENDIAN__
67982		#define vqrdmlahh_laneq_s16(__p0_256, __p1_256, __p2_256, __p3_256) __extension__ ({ \
67983		int16_t __s0_256 = __p0_256; \
67984		int16_t __s1_256 = __p1_256; \
67985		int16x8_t __s2_256 = __p2_256; \
67986		int16_t __ret_256; \
67987		__ret_256 = vqaddh_s16(__s0_256, vqrdmulhh_s16(__s1_256, vgetq_lane_s16(__s2_256, __p3_256))); \
67988		__ret_256; \
	71350	#define vqrdmlahh_laneq_s16(__p0_274, __p1_274, __p2_274, __p3_274) __extension__ ({ \
	71351	int16_t __s0_274 = __p0_274; \
	71352	int16_t __s1_274 = __p1_274; \
	71353	int16x8_t __s2_274 = __p2_274; \
	71354	int16_t __ret_274; \
	71355	__ret_274 = vqaddh_s16(__s0_274, vqrdmulhh_s16(__s1_274, vgetq_lane_s16(__s2_274, __p3_274))); \
	71356	__ret_274; \
67989	71357	})
67990	71358	#else
67991		#define vqrdmlahh_laneq_s16(__p0_257, __p1_257, __p2_257, __p3_257) __extension__ ({ \
67992		int16_t __s0_257 = __p0_257; \
67993		int16_t __s1_257 = __p1_257; \
67994		int16x8_t __s2_257 = __p2_257; \
67995		int16x8_t __rev2_257; __rev2_257 = __builtin_shufflevector(__s2_257, __s2_257, 7, 6, 5, 4, 3, 2, 1, 0); \
67996		int16_t __ret_257; \
67997		__ret_257 = __noswap_vqaddh_s16(__s0_257, __noswap_vqrdmulhh_s16(__s1_257, __noswap_vgetq_lane_s16(__rev2_257, __p3_257))); \
67998		__ret_257; \
	71359	#define vqrdmlahh_laneq_s16(__p0_275, __p1_275, __p2_275, __p3_275) __extension__ ({ \
	71360	int16_t __s0_275 = __p0_275; \
	71361	int16_t __s1_275 = __p1_275; \
	71362	int16x8_t __s2_275 = __p2_275; \
	71363	int16x8_t __rev2_275; __rev2_275 = __builtin_shufflevector(__s2_275, __s2_275, 7, 6, 5, 4, 3, 2, 1, 0); \
	71364	int16_t __ret_275; \
	71365	__ret_275 = __noswap_vqaddh_s16(__s0_275, __noswap_vqrdmulhh_s16(__s1_275, __noswap_vgetq_lane_s16(__rev2_275, __p3_275))); \
	71366	__ret_275; \
67999	71367	})
68000	71368	#endif
68001	71369
...	...	@@ -68028,86 +71396,86 @@ __ai int16_t vqrdmlshh_s16(int16_t __p0, int16_t __p1, int16_t __p2) {
68028	71396	#endif
68029	71397
68030	71398	#ifdef __LITTLE_ENDIAN__
68031		#define vqrdmlshs_lane_s32(__p0_258, __p1_258, __p2_258, __p3_258) __extension__ ({ \
68032		int32_t __s0_258 = __p0_258; \
68033		int32_t __s1_258 = __p1_258; \
68034		int32x2_t __s2_258 = __p2_258; \
68035		int32_t __ret_258; \
68036		__ret_258 = vqsubs_s32(__s0_258, vqrdmulhs_s32(__s1_258, vget_lane_s32(__s2_258, __p3_258))); \
68037		__ret_258; \
	71399	#define vqrdmlshs_lane_s32(__p0_276, __p1_276, __p2_276, __p3_276) __extension__ ({ \
	71400	int32_t __s0_276 = __p0_276; \
	71401	int32_t __s1_276 = __p1_276; \
	71402	int32x2_t __s2_276 = __p2_276; \
	71403	int32_t __ret_276; \
	71404	__ret_276 = vqsubs_s32(__s0_276, vqrdmulhs_s32(__s1_276, vget_lane_s32(__s2_276, __p3_276))); \
	71405	__ret_276; \
68038	71406	})
68039	71407	#else
68040		#define vqrdmlshs_lane_s32(__p0_259, __p1_259, __p2_259, __p3_259) __extension__ ({ \
68041		int32_t __s0_259 = __p0_259; \
68042		int32_t __s1_259 = __p1_259; \
68043		int32x2_t __s2_259 = __p2_259; \
68044		int32x2_t __rev2_259; __rev2_259 = __builtin_shufflevector(__s2_259, __s2_259, 1, 0); \
68045		int32_t __ret_259; \
68046		__ret_259 = __noswap_vqsubs_s32(__s0_259, __noswap_vqrdmulhs_s32(__s1_259, __noswap_vget_lane_s32(__rev2_259, __p3_259))); \
68047		__ret_259; \
	71408	#define vqrdmlshs_lane_s32(__p0_277, __p1_277, __p2_277, __p3_277) __extension__ ({ \
	71409	int32_t __s0_277 = __p0_277; \
	71410	int32_t __s1_277 = __p1_277; \
	71411	int32x2_t __s2_277 = __p2_277; \
	71412	int32x2_t __rev2_277; __rev2_277 = __builtin_shufflevector(__s2_277, __s2_277, 1, 0); \
	71413	int32_t __ret_277; \
	71414	__ret_277 = __noswap_vqsubs_s32(__s0_277, __noswap_vqrdmulhs_s32(__s1_277, __noswap_vget_lane_s32(__rev2_277, __p3_277))); \
	71415	__ret_277; \
68048	71416	})
68049	71417	#endif
68050	71418
68051	71419	#ifdef __LITTLE_ENDIAN__
68052		#define vqrdmlshh_lane_s16(__p0_260, __p1_260, __p2_260, __p3_260) __extension__ ({ \
68053		int16_t __s0_260 = __p0_260; \
68054		int16_t __s1_260 = __p1_260; \
68055		int16x4_t __s2_260 = __p2_260; \
68056		int16_t __ret_260; \
68057		__ret_260 = vqsubh_s16(__s0_260, vqrdmulhh_s16(__s1_260, vget_lane_s16(__s2_260, __p3_260))); \
68058		__ret_260; \
	71420	#define vqrdmlshh_lane_s16(__p0_278, __p1_278, __p2_278, __p3_278) __extension__ ({ \
	71421	int16_t __s0_278 = __p0_278; \
	71422	int16_t __s1_278 = __p1_278; \
	71423	int16x4_t __s2_278 = __p2_278; \
	71424	int16_t __ret_278; \
	71425	__ret_278 = vqsubh_s16(__s0_278, vqrdmulhh_s16(__s1_278, vget_lane_s16(__s2_278, __p3_278))); \
	71426	__ret_278; \
68059	71427	})
68060	71428	#else
68061		#define vqrdmlshh_lane_s16(__p0_261, __p1_261, __p2_261, __p3_261) __extension__ ({ \
68062		int16_t __s0_261 = __p0_261; \
68063		int16_t __s1_261 = __p1_261; \
68064		int16x4_t __s2_261 = __p2_261; \
68065		int16x4_t __rev2_261; __rev2_261 = __builtin_shufflevector(__s2_261, __s2_261, 3, 2, 1, 0); \
68066		int16_t __ret_261; \
68067		__ret_261 = __noswap_vqsubh_s16(__s0_261, __noswap_vqrdmulhh_s16(__s1_261, __noswap_vget_lane_s16(__rev2_261, __p3_261))); \
68068		__ret_261; \
	71429	#define vqrdmlshh_lane_s16(__p0_279, __p1_279, __p2_279, __p3_279) __extension__ ({ \
	71430	int16_t __s0_279 = __p0_279; \
	71431	int16_t __s1_279 = __p1_279; \
	71432	int16x4_t __s2_279 = __p2_279; \
	71433	int16x4_t __rev2_279; __rev2_279 = __builtin_shufflevector(__s2_279, __s2_279, 3, 2, 1, 0); \
	71434	int16_t __ret_279; \
	71435	__ret_279 = __noswap_vqsubh_s16(__s0_279, __noswap_vqrdmulhh_s16(__s1_279, __noswap_vget_lane_s16(__rev2_279, __p3_279))); \
	71436	__ret_279; \
68069	71437	})
68070	71438	#endif
68071	71439
68072	71440	#ifdef __LITTLE_ENDIAN__
68073		#define vqrdmlshs_laneq_s32(__p0_262, __p1_262, __p2_262, __p3_262) __extension__ ({ \
68074		int32_t __s0_262 = __p0_262; \
68075		int32_t __s1_262 = __p1_262; \
68076		int32x4_t __s2_262 = __p2_262; \
68077		int32_t __ret_262; \
68078		__ret_262 = vqsubs_s32(__s0_262, vqrdmulhs_s32(__s1_262, vgetq_lane_s32(__s2_262, __p3_262))); \
68079		__ret_262; \
	71441	#define vqrdmlshs_laneq_s32(__p0_280, __p1_280, __p2_280, __p3_280) __extension__ ({ \
	71442	int32_t __s0_280 = __p0_280; \
	71443	int32_t __s1_280 = __p1_280; \
	71444	int32x4_t __s2_280 = __p2_280; \
	71445	int32_t __ret_280; \
	71446	__ret_280 = vqsubs_s32(__s0_280, vqrdmulhs_s32(__s1_280, vgetq_lane_s32(__s2_280, __p3_280))); \
	71447	__ret_280; \
68080	71448	})
68081	71449	#else
68082		#define vqrdmlshs_laneq_s32(__p0_263, __p1_263, __p2_263, __p3_263) __extension__ ({ \
68083		int32_t __s0_263 = __p0_263; \
68084		int32_t __s1_263 = __p1_263; \
68085		int32x4_t __s2_263 = __p2_263; \
68086		int32x4_t __rev2_263; __rev2_263 = __builtin_shufflevector(__s2_263, __s2_263, 3, 2, 1, 0); \
68087		int32_t __ret_263; \
68088		__ret_263 = __noswap_vqsubs_s32(__s0_263, __noswap_vqrdmulhs_s32(__s1_263, __noswap_vgetq_lane_s32(__rev2_263, __p3_263))); \
68089		__ret_263; \
	71450	#define vqrdmlshs_laneq_s32(__p0_281, __p1_281, __p2_281, __p3_281) __extension__ ({ \
	71451	int32_t __s0_281 = __p0_281; \
	71452	int32_t __s1_281 = __p1_281; \
	71453	int32x4_t __s2_281 = __p2_281; \
	71454	int32x4_t __rev2_281; __rev2_281 = __builtin_shufflevector(__s2_281, __s2_281, 3, 2, 1, 0); \
	71455	int32_t __ret_281; \
	71456	__ret_281 = __noswap_vqsubs_s32(__s0_281, __noswap_vqrdmulhs_s32(__s1_281, __noswap_vgetq_lane_s32(__rev2_281, __p3_281))); \
	71457	__ret_281; \
68090	71458	})
68091	71459	#endif
68092	71460
68093	71461	#ifdef __LITTLE_ENDIAN__
68094		#define vqrdmlshh_laneq_s16(__p0_264, __p1_264, __p2_264, __p3_264) __extension__ ({ \
68095		int16_t __s0_264 = __p0_264; \
68096		int16_t __s1_264 = __p1_264; \
68097		int16x8_t __s2_264 = __p2_264; \
68098		int16_t __ret_264; \
68099		__ret_264 = vqsubh_s16(__s0_264, vqrdmulhh_s16(__s1_264, vgetq_lane_s16(__s2_264, __p3_264))); \
68100		__ret_264; \
	71462	#define vqrdmlshh_laneq_s16(__p0_282, __p1_282, __p2_282, __p3_282) __extension__ ({ \
	71463	int16_t __s0_282 = __p0_282; \
	71464	int16_t __s1_282 = __p1_282; \
	71465	int16x8_t __s2_282 = __p2_282; \
	71466	int16_t __ret_282; \
	71467	__ret_282 = vqsubh_s16(__s0_282, vqrdmulhh_s16(__s1_282, vgetq_lane_s16(__s2_282, __p3_282))); \
	71468	__ret_282; \
68101	71469	})
68102	71470	#else
68103		#define vqrdmlshh_laneq_s16(__p0_265, __p1_265, __p2_265, __p3_265) __extension__ ({ \
68104		int16_t __s0_265 = __p0_265; \
68105		int16_t __s1_265 = __p1_265; \
68106		int16x8_t __s2_265 = __p2_265; \
68107		int16x8_t __rev2_265; __rev2_265 = __builtin_shufflevector(__s2_265, __s2_265, 7, 6, 5, 4, 3, 2, 1, 0); \
68108		int16_t __ret_265; \
68109		__ret_265 = __noswap_vqsubh_s16(__s0_265, __noswap_vqrdmulhh_s16(__s1_265, __noswap_vgetq_lane_s16(__rev2_265, __p3_265))); \
68110		__ret_265; \
	71471	#define vqrdmlshh_laneq_s16(__p0_283, __p1_283, __p2_283, __p3_283) __extension__ ({ \
	71472	int16_t __s0_283 = __p0_283; \
	71473	int16_t __s1_283 = __p1_283; \
	71474	int16x8_t __s2_283 = __p2_283; \
	71475	int16x8_t __rev2_283; __rev2_283 = __builtin_shufflevector(__s2_283, __s2_283, 7, 6, 5, 4, 3, 2, 1, 0); \
	71476	int16_t __ret_283; \
	71477	__ret_283 = __noswap_vqsubh_s16(__s0_283, __noswap_vqrdmulhh_s16(__s1_283, __noswap_vgetq_lane_s16(__rev2_283, __p3_283))); \
	71478	__ret_283; \
68111	71479	})
68112	71480	#endif
68113	71481
...	...	@@ -68420,158 +71788,158 @@ __ai int32x4_t vaddw_high_s16(int32x4_t __p0, int16x8_t __p1) {
68420	71788	#endif
68421	71789
68422	71790	#ifdef __LITTLE_ENDIAN__
68423		#define vcopyq_lane_p64(__p0_266, __p1_266, __p2_266, __p3_266) __extension__ ({ \
68424		poly64x2_t __s0_266 = __p0_266; \
68425		poly64x1_t __s2_266 = __p2_266; \
68426		poly64x2_t __ret_266; \
68427		__ret_266 = vsetq_lane_p64(vget_lane_p64(__s2_266, __p3_266), __s0_266, __p1_266); \
68428		__ret_266; \
	71791	#define vcopyq_lane_p64(__p0_284, __p1_284, __p2_284, __p3_284) __extension__ ({ \
	71792	poly64x2_t __s0_284 = __p0_284; \
	71793	poly64x1_t __s2_284 = __p2_284; \
	71794	poly64x2_t __ret_284; \
	71795	__ret_284 = vsetq_lane_p64(vget_lane_p64(__s2_284, __p3_284), __s0_284, __p1_284); \
	71796	__ret_284; \
68429	71797	})
68430	71798	#else
68431		#define vcopyq_lane_p64(__p0_267, __p1_267, __p2_267, __p3_267) __extension__ ({ \
68432		poly64x2_t __s0_267 = __p0_267; \
68433		poly64x1_t __s2_267 = __p2_267; \
68434		poly64x2_t __rev0_267; __rev0_267 = __builtin_shufflevector(__s0_267, __s0_267, 1, 0); \
68435		poly64x2_t __ret_267; \
68436		__ret_267 = __noswap_vsetq_lane_p64(__noswap_vget_lane_p64(__s2_267, __p3_267), __rev0_267, __p1_267); \
68437		__ret_267 = __builtin_shufflevector(__ret_267, __ret_267, 1, 0); \
68438		__ret_267; \
	71799	#define vcopyq_lane_p64(__p0_285, __p1_285, __p2_285, __p3_285) __extension__ ({ \
	71800	poly64x2_t __s0_285 = __p0_285; \
	71801	poly64x1_t __s2_285 = __p2_285; \
	71802	poly64x2_t __rev0_285; __rev0_285 = __builtin_shufflevector(__s0_285, __s0_285, 1, 0); \
	71803	poly64x2_t __ret_285; \
	71804	__ret_285 = __noswap_vsetq_lane_p64(__noswap_vget_lane_p64(__s2_285, __p3_285), __rev0_285, __p1_285); \
	71805	__ret_285 = __builtin_shufflevector(__ret_285, __ret_285, 1, 0); \
	71806	__ret_285; \
68439	71807	})
68440	71808	#endif
68441	71809
68442	71810	#ifdef __LITTLE_ENDIAN__
68443		#define vcopyq_lane_f64(__p0_268, __p1_268, __p2_268, __p3_268) __extension__ ({ \
68444		float64x2_t __s0_268 = __p0_268; \
68445		float64x1_t __s2_268 = __p2_268; \
68446		float64x2_t __ret_268; \
68447		__ret_268 = vsetq_lane_f64(vget_lane_f64(__s2_268, __p3_268), __s0_268, __p1_268); \
68448		__ret_268; \
	71811	#define vcopyq_lane_f64(__p0_286, __p1_286, __p2_286, __p3_286) __extension__ ({ \
	71812	float64x2_t __s0_286 = __p0_286; \
	71813	float64x1_t __s2_286 = __p2_286; \
	71814	float64x2_t __ret_286; \
	71815	__ret_286 = vsetq_lane_f64(vget_lane_f64(__s2_286, __p3_286), __s0_286, __p1_286); \
	71816	__ret_286; \
68449	71817	})
68450	71818	#else
68451		#define vcopyq_lane_f64(__p0_269, __p1_269, __p2_269, __p3_269) __extension__ ({ \
68452		float64x2_t __s0_269 = __p0_269; \
68453		float64x1_t __s2_269 = __p2_269; \
68454		float64x2_t __rev0_269; __rev0_269 = __builtin_shufflevector(__s0_269, __s0_269, 1, 0); \
68455		float64x2_t __ret_269; \
68456		__ret_269 = __noswap_vsetq_lane_f64(__noswap_vget_lane_f64(__s2_269, __p3_269), __rev0_269, __p1_269); \
68457		__ret_269 = __builtin_shufflevector(__ret_269, __ret_269, 1, 0); \
68458		__ret_269; \
	71819	#define vcopyq_lane_f64(__p0_287, __p1_287, __p2_287, __p3_287) __extension__ ({ \
	71820	float64x2_t __s0_287 = __p0_287; \
	71821	float64x1_t __s2_287 = __p2_287; \
	71822	float64x2_t __rev0_287; __rev0_287 = __builtin_shufflevector(__s0_287, __s0_287, 1, 0); \
	71823	float64x2_t __ret_287; \
	71824	__ret_287 = __noswap_vsetq_lane_f64(__noswap_vget_lane_f64(__s2_287, __p3_287), __rev0_287, __p1_287); \
	71825	__ret_287 = __builtin_shufflevector(__ret_287, __ret_287, 1, 0); \
	71826	__ret_287; \
68459	71827	})
68460	71828	#endif
68461	71829
68462	71830	#ifdef __LITTLE_ENDIAN__
68463		#define vcopy_lane_p64(__p0_270, __p1_270, __p2_270, __p3_270) __extension__ ({ \
68464		poly64x1_t __s0_270 = __p0_270; \
68465		poly64x1_t __s2_270 = __p2_270; \
68466		poly64x1_t __ret_270; \
68467		__ret_270 = vset_lane_p64(vget_lane_p64(__s2_270, __p3_270), __s0_270, __p1_270); \
68468		__ret_270; \
	71831	#define vcopy_lane_p64(__p0_288, __p1_288, __p2_288, __p3_288) __extension__ ({ \
	71832	poly64x1_t __s0_288 = __p0_288; \
	71833	poly64x1_t __s2_288 = __p2_288; \
	71834	poly64x1_t __ret_288; \
	71835	__ret_288 = vset_lane_p64(vget_lane_p64(__s2_288, __p3_288), __s0_288, __p1_288); \
	71836	__ret_288; \
68469	71837	})
68470	71838	#else
68471		#define vcopy_lane_p64(__p0_271, __p1_271, __p2_271, __p3_271) __extension__ ({ \
68472		poly64x1_t __s0_271 = __p0_271; \
68473		poly64x1_t __s2_271 = __p2_271; \
68474		poly64x1_t __ret_271; \
68475		__ret_271 = __noswap_vset_lane_p64(__noswap_vget_lane_p64(__s2_271, __p3_271), __s0_271, __p1_271); \
68476		__ret_271; \
	71839	#define vcopy_lane_p64(__p0_289, __p1_289, __p2_289, __p3_289) __extension__ ({ \
	71840	poly64x1_t __s0_289 = __p0_289; \
	71841	poly64x1_t __s2_289 = __p2_289; \
	71842	poly64x1_t __ret_289; \
	71843	__ret_289 = __noswap_vset_lane_p64(__noswap_vget_lane_p64(__s2_289, __p3_289), __s0_289, __p1_289); \
	71844	__ret_289; \
68477	71845	})
68478	71846	#endif
68479	71847
68480	71848	#ifdef __LITTLE_ENDIAN__
68481		#define vcopy_lane_f64(__p0_272, __p1_272, __p2_272, __p3_272) __extension__ ({ \
68482		float64x1_t __s0_272 = __p0_272; \
68483		float64x1_t __s2_272 = __p2_272; \
68484		float64x1_t __ret_272; \
68485		__ret_272 = vset_lane_f64(vget_lane_f64(__s2_272, __p3_272), __s0_272, __p1_272); \
68486		__ret_272; \
	71849	#define vcopy_lane_f64(__p0_290, __p1_290, __p2_290, __p3_290) __extension__ ({ \
	71850	float64x1_t __s0_290 = __p0_290; \
	71851	float64x1_t __s2_290 = __p2_290; \
	71852	float64x1_t __ret_290; \
	71853	__ret_290 = vset_lane_f64(vget_lane_f64(__s2_290, __p3_290), __s0_290, __p1_290); \
	71854	__ret_290; \
68487	71855	})
68488	71856	#else
68489		#define vcopy_lane_f64(__p0_273, __p1_273, __p2_273, __p3_273) __extension__ ({ \
68490		float64x1_t __s0_273 = __p0_273; \
68491		float64x1_t __s2_273 = __p2_273; \
68492		float64x1_t __ret_273; \
68493		__ret_273 = __noswap_vset_lane_f64(__noswap_vget_lane_f64(__s2_273, __p3_273), __s0_273, __p1_273); \
68494		__ret_273; \
	71857	#define vcopy_lane_f64(__p0_291, __p1_291, __p2_291, __p3_291) __extension__ ({ \
	71858	float64x1_t __s0_291 = __p0_291; \
	71859	float64x1_t __s2_291 = __p2_291; \
	71860	float64x1_t __ret_291; \
	71861	__ret_291 = __noswap_vset_lane_f64(__noswap_vget_lane_f64(__s2_291, __p3_291), __s0_291, __p1_291); \
	71862	__ret_291; \
68495	71863	})
68496	71864	#endif
68497	71865
68498	71866	#ifdef __LITTLE_ENDIAN__
68499		#define vcopyq_laneq_p64(__p0_274, __p1_274, __p2_274, __p3_274) __extension__ ({ \
68500		poly64x2_t __s0_274 = __p0_274; \
68501		poly64x2_t __s2_274 = __p2_274; \
68502		poly64x2_t __ret_274; \
68503		__ret_274 = vsetq_lane_p64(vgetq_lane_p64(__s2_274, __p3_274), __s0_274, __p1_274); \
68504		__ret_274; \
	71867	#define vcopyq_laneq_p64(__p0_292, __p1_292, __p2_292, __p3_292) __extension__ ({ \
	71868	poly64x2_t __s0_292 = __p0_292; \
	71869	poly64x2_t __s2_292 = __p2_292; \
	71870	poly64x2_t __ret_292; \
	71871	__ret_292 = vsetq_lane_p64(vgetq_lane_p64(__s2_292, __p3_292), __s0_292, __p1_292); \
	71872	__ret_292; \
68505	71873	})
68506	71874	#else
68507		#define vcopyq_laneq_p64(__p0_275, __p1_275, __p2_275, __p3_275) __extension__ ({ \
68508		poly64x2_t __s0_275 = __p0_275; \
68509		poly64x2_t __s2_275 = __p2_275; \
68510		poly64x2_t __rev0_275; __rev0_275 = __builtin_shufflevector(__s0_275, __s0_275, 1, 0); \
68511		poly64x2_t __rev2_275; __rev2_275 = __builtin_shufflevector(__s2_275, __s2_275, 1, 0); \
68512		poly64x2_t __ret_275; \
68513		__ret_275 = __noswap_vsetq_lane_p64(__noswap_vgetq_lane_p64(__rev2_275, __p3_275), __rev0_275, __p1_275); \
68514		__ret_275 = __builtin_shufflevector(__ret_275, __ret_275, 1, 0); \
68515		__ret_275; \
	71875	#define vcopyq_laneq_p64(__p0_293, __p1_293, __p2_293, __p3_293) __extension__ ({ \
	71876	poly64x2_t __s0_293 = __p0_293; \
	71877	poly64x2_t __s2_293 = __p2_293; \
	71878	poly64x2_t __rev0_293; __rev0_293 = __builtin_shufflevector(__s0_293, __s0_293, 1, 0); \
	71879	poly64x2_t __rev2_293; __rev2_293 = __builtin_shufflevector(__s2_293, __s2_293, 1, 0); \
	71880	poly64x2_t __ret_293; \
	71881	__ret_293 = __noswap_vsetq_lane_p64(__noswap_vgetq_lane_p64(__rev2_293, __p3_293), __rev0_293, __p1_293); \
	71882	__ret_293 = __builtin_shufflevector(__ret_293, __ret_293, 1, 0); \
	71883	__ret_293; \
68516	71884	})
68517	71885	#endif
68518	71886
68519	71887	#ifdef __LITTLE_ENDIAN__
68520		#define vcopyq_laneq_f64(__p0_276, __p1_276, __p2_276, __p3_276) __extension__ ({ \
68521		float64x2_t __s0_276 = __p0_276; \
68522		float64x2_t __s2_276 = __p2_276; \
68523		float64x2_t __ret_276; \
68524		__ret_276 = vsetq_lane_f64(vgetq_lane_f64(__s2_276, __p3_276), __s0_276, __p1_276); \
68525		__ret_276; \
	71888	#define vcopyq_laneq_f64(__p0_294, __p1_294, __p2_294, __p3_294) __extension__ ({ \
	71889	float64x2_t __s0_294 = __p0_294; \
	71890	float64x2_t __s2_294 = __p2_294; \
	71891	float64x2_t __ret_294; \
	71892	__ret_294 = vsetq_lane_f64(vgetq_lane_f64(__s2_294, __p3_294), __s0_294, __p1_294); \
	71893	__ret_294; \
68526	71894	})
68527	71895	#else
68528		#define vcopyq_laneq_f64(__p0_277, __p1_277, __p2_277, __p3_277) __extension__ ({ \
68529		float64x2_t __s0_277 = __p0_277; \
68530		float64x2_t __s2_277 = __p2_277; \
68531		float64x2_t __rev0_277; __rev0_277 = __builtin_shufflevector(__s0_277, __s0_277, 1, 0); \
68532		float64x2_t __rev2_277; __rev2_277 = __builtin_shufflevector(__s2_277, __s2_277, 1, 0); \
68533		float64x2_t __ret_277; \
68534		__ret_277 = __noswap_vsetq_lane_f64(__noswap_vgetq_lane_f64(__rev2_277, __p3_277), __rev0_277, __p1_277); \
68535		__ret_277 = __builtin_shufflevector(__ret_277, __ret_277, 1, 0); \
68536		__ret_277; \
	71896	#define vcopyq_laneq_f64(__p0_295, __p1_295, __p2_295, __p3_295) __extension__ ({ \
	71897	float64x2_t __s0_295 = __p0_295; \
	71898	float64x2_t __s2_295 = __p2_295; \
	71899	float64x2_t __rev0_295; __rev0_295 = __builtin_shufflevector(__s0_295, __s0_295, 1, 0); \
	71900	float64x2_t __rev2_295; __rev2_295 = __builtin_shufflevector(__s2_295, __s2_295, 1, 0); \
	71901	float64x2_t __ret_295; \
	71902	__ret_295 = __noswap_vsetq_lane_f64(__noswap_vgetq_lane_f64(__rev2_295, __p3_295), __rev0_295, __p1_295); \
	71903	__ret_295 = __builtin_shufflevector(__ret_295, __ret_295, 1, 0); \
	71904	__ret_295; \
68537	71905	})
68538	71906	#endif
68539	71907
68540	71908	#ifdef __LITTLE_ENDIAN__
68541		#define vcopy_laneq_p64(__p0_278, __p1_278, __p2_278, __p3_278) __extension__ ({ \
68542		poly64x1_t __s0_278 = __p0_278; \
68543		poly64x2_t __s2_278 = __p2_278; \
68544		poly64x1_t __ret_278; \
68545		__ret_278 = vset_lane_p64(vgetq_lane_p64(__s2_278, __p3_278), __s0_278, __p1_278); \
68546		__ret_278; \
	71909	#define vcopy_laneq_p64(__p0_296, __p1_296, __p2_296, __p3_296) __extension__ ({ \
	71910	poly64x1_t __s0_296 = __p0_296; \
	71911	poly64x2_t __s2_296 = __p2_296; \
	71912	poly64x1_t __ret_296; \
	71913	__ret_296 = vset_lane_p64(vgetq_lane_p64(__s2_296, __p3_296), __s0_296, __p1_296); \
	71914	__ret_296; \
68547	71915	})
68548	71916	#else
68549		#define vcopy_laneq_p64(__p0_279, __p1_279, __p2_279, __p3_279) __extension__ ({ \
68550		poly64x1_t __s0_279 = __p0_279; \
68551		poly64x2_t __s2_279 = __p2_279; \
68552		poly64x2_t __rev2_279; __rev2_279 = __builtin_shufflevector(__s2_279, __s2_279, 1, 0); \
68553		poly64x1_t __ret_279; \
68554		__ret_279 = __noswap_vset_lane_p64(__noswap_vgetq_lane_p64(__rev2_279, __p3_279), __s0_279, __p1_279); \
68555		__ret_279; \
	71917	#define vcopy_laneq_p64(__p0_297, __p1_297, __p2_297, __p3_297) __extension__ ({ \
	71918	poly64x1_t __s0_297 = __p0_297; \
	71919	poly64x2_t __s2_297 = __p2_297; \
	71920	poly64x2_t __rev2_297; __rev2_297 = __builtin_shufflevector(__s2_297, __s2_297, 1, 0); \
	71921	poly64x1_t __ret_297; \
	71922	__ret_297 = __noswap_vset_lane_p64(__noswap_vgetq_lane_p64(__rev2_297, __p3_297), __s0_297, __p1_297); \
	71923	__ret_297; \
68556	71924	})
68557	71925	#endif
68558	71926
68559	71927	#ifdef __LITTLE_ENDIAN__
68560		#define vcopy_laneq_f64(__p0_280, __p1_280, __p2_280, __p3_280) __extension__ ({ \
68561		float64x1_t __s0_280 = __p0_280; \
68562		float64x2_t __s2_280 = __p2_280; \
68563		float64x1_t __ret_280; \
68564		__ret_280 = vset_lane_f64(vgetq_lane_f64(__s2_280, __p3_280), __s0_280, __p1_280); \
68565		__ret_280; \
	71928	#define vcopy_laneq_f64(__p0_298, __p1_298, __p2_298, __p3_298) __extension__ ({ \
	71929	float64x1_t __s0_298 = __p0_298; \
	71930	float64x2_t __s2_298 = __p2_298; \
	71931	float64x1_t __ret_298; \
	71932	__ret_298 = vset_lane_f64(vgetq_lane_f64(__s2_298, __p3_298), __s0_298, __p1_298); \
	71933	__ret_298; \
68566	71934	})
68567	71935	#else
68568		#define vcopy_laneq_f64(__p0_281, __p1_281, __p2_281, __p3_281) __extension__ ({ \
68569		float64x1_t __s0_281 = __p0_281; \
68570		float64x2_t __s2_281 = __p2_281; \
68571		float64x2_t __rev2_281; __rev2_281 = __builtin_shufflevector(__s2_281, __s2_281, 1, 0); \
68572		float64x1_t __ret_281; \
68573		__ret_281 = __noswap_vset_lane_f64(__noswap_vgetq_lane_f64(__rev2_281, __p3_281), __s0_281, __p1_281); \
68574		__ret_281; \
	71936	#define vcopy_laneq_f64(__p0_299, __p1_299, __p2_299, __p3_299) __extension__ ({ \
	71937	float64x1_t __s0_299 = __p0_299; \
	71938	float64x2_t __s2_299 = __p2_299; \
	71939	float64x2_t __rev2_299; __rev2_299 = __builtin_shufflevector(__s2_299, __s2_299, 1, 0); \
	71940	float64x1_t __ret_299; \
	71941	__ret_299 = __noswap_vset_lane_f64(__noswap_vgetq_lane_f64(__rev2_299, __p3_299), __s0_299, __p1_299); \
	71942	__ret_299; \
68575	71943	})
68576	71944	#endif
68577	71945
...	...	@@ -68928,51 +72296,51 @@ __ai int32x4_t vmlsl_high_n_s16(int32x4_t __p0, int16x8_t __p1, int16_t __p2) {
68928	72296	#endif
68929	72297
68930	72298	#ifdef __LITTLE_ENDIAN__
68931		#define vmulx_lane_f64(__p0_282, __p1_282, __p2_282) __extension__ ({ \
68932		float64x1_t __s0_282 = __p0_282; \
68933		float64x1_t __s1_282 = __p1_282; \
68934		float64x1_t __ret_282; \
68935		float64_t __x_282 = vget_lane_f64(__s0_282, 0); \
68936		float64_t __y_282 = vget_lane_f64(__s1_282, __p2_282); \
68937		float64_t __z_282 = vmulxd_f64(__x_282, __y_282); \
68938		__ret_282 = vset_lane_f64(__z_282, __s0_282, __p2_282); \
68939		__ret_282; \
	72299	#define vmulx_lane_f64(__p0_300, __p1_300, __p2_300) __extension__ ({ \
	72300	float64x1_t __s0_300 = __p0_300; \
	72301	float64x1_t __s1_300 = __p1_300; \
	72302	float64x1_t __ret_300; \
	72303	float64_t __x_300 = vget_lane_f64(__s0_300, 0); \
	72304	float64_t __y_300 = vget_lane_f64(__s1_300, __p2_300); \
	72305	float64_t __z_300 = vmulxd_f64(__x_300, __y_300); \
	72306	__ret_300 = vset_lane_f64(__z_300, __s0_300, __p2_300); \
	72307	__ret_300; \
68940	72308	})
68941	72309	#else
68942		#define vmulx_lane_f64(__p0_283, __p1_283, __p2_283) __extension__ ({ \
68943		float64x1_t __s0_283 = __p0_283; \
68944		float64x1_t __s1_283 = __p1_283; \
68945		float64x1_t __ret_283; \
68946		float64_t __x_283 = __noswap_vget_lane_f64(__s0_283, 0); \
68947		float64_t __y_283 = __noswap_vget_lane_f64(__s1_283, __p2_283); \
68948		float64_t __z_283 = __noswap_vmulxd_f64(__x_283, __y_283); \
68949		__ret_283 = __noswap_vset_lane_f64(__z_283, __s0_283, __p2_283); \
68950		__ret_283; \
	72310	#define vmulx_lane_f64(__p0_301, __p1_301, __p2_301) __extension__ ({ \
	72311	float64x1_t __s0_301 = __p0_301; \
	72312	float64x1_t __s1_301 = __p1_301; \
	72313	float64x1_t __ret_301; \
	72314	float64_t __x_301 = __noswap_vget_lane_f64(__s0_301, 0); \
	72315	float64_t __y_301 = __noswap_vget_lane_f64(__s1_301, __p2_301); \
	72316	float64_t __z_301 = __noswap_vmulxd_f64(__x_301, __y_301); \
	72317	__ret_301 = __noswap_vset_lane_f64(__z_301, __s0_301, __p2_301); \
	72318	__ret_301; \
68951	72319	})
68952	72320	#endif
68953	72321
68954	72322	#ifdef __LITTLE_ENDIAN__
68955		#define vmulx_laneq_f64(__p0_284, __p1_284, __p2_284) __extension__ ({ \
68956		float64x1_t __s0_284 = __p0_284; \
68957		float64x2_t __s1_284 = __p1_284; \
68958		float64x1_t __ret_284; \
68959		float64_t __x_284 = vget_lane_f64(__s0_284, 0); \
68960		float64_t __y_284 = vgetq_lane_f64(__s1_284, __p2_284); \
68961		float64_t __z_284 = vmulxd_f64(__x_284, __y_284); \
68962		__ret_284 = vset_lane_f64(__z_284, __s0_284, 0); \
68963		__ret_284; \
	72323	#define vmulx_laneq_f64(__p0_302, __p1_302, __p2_302) __extension__ ({ \
	72324	float64x1_t __s0_302 = __p0_302; \
	72325	float64x2_t __s1_302 = __p1_302; \
	72326	float64x1_t __ret_302; \
	72327	float64_t __x_302 = vget_lane_f64(__s0_302, 0); \
	72328	float64_t __y_302 = vgetq_lane_f64(__s1_302, __p2_302); \
	72329	float64_t __z_302 = vmulxd_f64(__x_302, __y_302); \
	72330	__ret_302 = vset_lane_f64(__z_302, __s0_302, 0); \
	72331	__ret_302; \
68964	72332	})
68965	72333	#else
68966		#define vmulx_laneq_f64(__p0_285, __p1_285, __p2_285) __extension__ ({ \
68967		float64x1_t __s0_285 = __p0_285; \
68968		float64x2_t __s1_285 = __p1_285; \
68969		float64x2_t __rev1_285; __rev1_285 = __builtin_shufflevector(__s1_285, __s1_285, 1, 0); \
68970		float64x1_t __ret_285; \
68971		float64_t __x_285 = __noswap_vget_lane_f64(__s0_285, 0); \
68972		float64_t __y_285 = __noswap_vgetq_lane_f64(__rev1_285, __p2_285); \
68973		float64_t __z_285 = __noswap_vmulxd_f64(__x_285, __y_285); \
68974		__ret_285 = __noswap_vset_lane_f64(__z_285, __s0_285, 0); \
68975		__ret_285; \
	72334	#define vmulx_laneq_f64(__p0_303, __p1_303, __p2_303) __extension__ ({ \
	72335	float64x1_t __s0_303 = __p0_303; \
	72336	float64x2_t __s1_303 = __p1_303; \
	72337	float64x2_t __rev1_303; __rev1_303 = __builtin_shufflevector(__s1_303, __s1_303, 1, 0); \
	72338	float64x1_t __ret_303; \
	72339	float64_t __x_303 = __noswap_vget_lane_f64(__s0_303, 0); \
	72340	float64_t __y_303 = __noswap_vgetq_lane_f64(__rev1_303, __p2_303); \
	72341	float64_t __z_303 = __noswap_vmulxd_f64(__x_303, __y_303); \
	72342	__ret_303 = __noswap_vset_lane_f64(__z_303, __s0_303, 0); \
	72343	__ret_303; \
68976	72344	})
68977	72345	#endif
68978	72346

c_headers/avx512bitalgintrin.h created+97

...	...	@@ -0,0 +1,97 @@
	1	/*===------------- avx512bitalgintrin.h - BITALG intrinsics ------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <avx512bitalgintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __AVX512BITALGINTRIN_H
	29	#define __AVX512BITALGINTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512bitalg")))
	33
	34	static __inline__ __m512i __DEFAULT_FN_ATTRS
	35	_mm512_popcnt_epi16(__m512i __A)
	36	{
	37	return (__m512i) __builtin_ia32_vpopcntw_512((__v32hi) __A);
	38	}
	39
	40	static __inline__ __m512i __DEFAULT_FN_ATTRS
	41	_mm512_mask_popcnt_epi16(__m512i __A, __mmask32 __U, __m512i __B)
	42	{
	43	return (__m512i) __builtin_ia32_selectw_512((__mmask32) __U,
	44	(__v32hi) _mm512_popcnt_epi16(__B),
	45	(__v32hi) __A);
	46	}
	47
	48	static __inline__ __m512i __DEFAULT_FN_ATTRS
	49	_mm512_maskz_popcnt_epi16(__mmask32 __U, __m512i __B)
	50	{
	51	return _mm512_mask_popcnt_epi16((__m512i) _mm512_setzero_hi(),
	52	__U,
	53	__B);
	54	}
	55
	56	static __inline__ __m512i __DEFAULT_FN_ATTRS
	57	_mm512_popcnt_epi8(__m512i __A)
	58	{
	59	return (__m512i) __builtin_ia32_vpopcntb_512((__v64qi) __A);
	60	}
	61
	62	static __inline__ __m512i __DEFAULT_FN_ATTRS
	63	_mm512_mask_popcnt_epi8(__m512i __A, __mmask64 __U, __m512i __B)
	64	{
	65	return (__m512i) __builtin_ia32_selectb_512((__mmask64) __U,
	66	(__v64qi) _mm512_popcnt_epi8(__B),
	67	(__v64qi) __A);
	68	}
	69
	70	static __inline__ __m512i __DEFAULT_FN_ATTRS
	71	_mm512_maskz_popcnt_epi8(__mmask64 __U, __m512i __B)
	72	{
	73	return _mm512_mask_popcnt_epi8((__m512i) _mm512_setzero_qi(),
	74	__U,
	75	__B);
	76	}
	77
	78	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
	79	_mm512_mask_bitshuffle_epi64_mask(__mmask64 __U, __m512i __A, __m512i __B)
	80	{
	81	return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask((__v64qi) __A,
	82	(__v64qi) __B,
	83	__U);
	84	}
	85
	86	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
	87	_mm512_bitshuffle_epi64_mask(__m512i __A, __m512i __B)
	88	{
	89	return _mm512_mask_bitshuffle_epi64_mask((__mmask64) -1,
	90	__A,
	91	__B);
	92	}
	93
	94
	95	#undef __DEFAULT_FN_ATTRS
	96
	97	#endif

c_headers/avx512bwintrin.h+148-343

...	...	@@ -56,293 +56,145 @@ _mm512_setzero_hi(void) {
56	56
57	57	/* Integer compare */
58	58
59		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
60		_mm512_cmpeq_epi8_mask(__m512i __a, __m512i __b) {
61		return (__mmask64)__builtin_ia32_pcmpeqb512_mask((__v64qi)__a, (__v64qi)__b,
62		(__mmask64)-1);
63		}
64
65		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
66		_mm512_mask_cmpeq_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
67		return (__mmask64)__builtin_ia32_pcmpeqb512_mask((__v64qi)__a, (__v64qi)__b,
68		__u);
69		}
70
71		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
72		_mm512_cmpeq_epu8_mask(__m512i __a, __m512i __b) {
73		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 0,
74		(__mmask64)-1);
75		}
76
77		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
78		_mm512_mask_cmpeq_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
79		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 0,
80		__u);
81		}
82
83		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
84		_mm512_cmpeq_epi16_mask(__m512i __a, __m512i __b) {
85		return (__mmask32)__builtin_ia32_pcmpeqw512_mask((__v32hi)__a, (__v32hi)__b,
86		(__mmask32)-1);
87		}
88
89		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
90		_mm512_mask_cmpeq_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
91		return (__mmask32)__builtin_ia32_pcmpeqw512_mask((__v32hi)__a, (__v32hi)__b,
92		__u);
93		}
94
95		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
96		_mm512_cmpeq_epu16_mask(__m512i __a, __m512i __b) {
97		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 0,
98		(__mmask32)-1);
99		}
100
101		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
102		_mm512_mask_cmpeq_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
103		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 0,
104		__u);
105		}
106
107		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
108		_mm512_cmpge_epi8_mask(__m512i __a, __m512i __b) {
109		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
110		(__mmask64)-1);
111		}
112
113		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
114		_mm512_mask_cmpge_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
115		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
116		__u);
117		}
118
119		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
120		_mm512_cmpge_epu8_mask(__m512i __a, __m512i __b) {
121		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
122		(__mmask64)-1);
123		}
124
125		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
126		_mm512_mask_cmpge_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
127		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 5,
128		__u);
129		}
130
131		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
132		_mm512_cmpge_epi16_mask(__m512i __a, __m512i __b) {
133		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
134		(__mmask32)-1);
135		}
136
137		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
138		_mm512_mask_cmpge_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
139		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
140		__u);
141		}
142
143		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
144		_mm512_cmpge_epu16_mask(__m512i __a, __m512i __b) {
145		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
146		(__mmask32)-1);
147		}
148
149		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
150		_mm512_mask_cmpge_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
151		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 5,
152		__u);
153		}
154
155		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
156		_mm512_cmpgt_epi8_mask(__m512i __a, __m512i __b) {
157		return (__mmask64)__builtin_ia32_pcmpgtb512_mask((__v64qi)__a, (__v64qi)__b,
158		(__mmask64)-1);
159		}
160
161		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
162		_mm512_mask_cmpgt_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
163		return (__mmask64)__builtin_ia32_pcmpgtb512_mask((__v64qi)__a, (__v64qi)__b,
164		__u);
165		}
166
167		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
168		_mm512_cmpgt_epu8_mask(__m512i __a, __m512i __b) {
169		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 6,
170		(__mmask64)-1);
171		}
172
173		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
174		_mm512_mask_cmpgt_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
175		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 6,
176		__u);
177		}
178
179		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
180		_mm512_cmpgt_epi16_mask(__m512i __a, __m512i __b) {
181		return (__mmask32)__builtin_ia32_pcmpgtw512_mask((__v32hi)__a, (__v32hi)__b,
182		(__mmask32)-1);
183		}
184
185		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
186		_mm512_mask_cmpgt_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
187		return (__mmask32)__builtin_ia32_pcmpgtw512_mask((__v32hi)__a, (__v32hi)__b,
188		__u);
189		}
190
191		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
192		_mm512_cmpgt_epu16_mask(__m512i __a, __m512i __b) {
193		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 6,
194		(__mmask32)-1);
195		}
196
197		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
198		_mm512_mask_cmpgt_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
199		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 6,
200		__u);
201		}
202
203		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
204		_mm512_cmple_epi8_mask(__m512i __a, __m512i __b) {
205		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
206		(__mmask64)-1);
207		}
208
209		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
210		_mm512_mask_cmple_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
211		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
212		__u);
213		}
214
215		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
216		_mm512_cmple_epu8_mask(__m512i __a, __m512i __b) {
217		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
218		(__mmask64)-1);
219		}
220
221		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
222		_mm512_mask_cmple_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
223		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 2,
224		__u);
225		}
226
227		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
228		_mm512_cmple_epi16_mask(__m512i __a, __m512i __b) {
229		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
230		(__mmask32)-1);
231		}
232
233		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
234		_mm512_mask_cmple_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
235		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
236		__u);
237		}
238
239		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
240		_mm512_cmple_epu16_mask(__m512i __a, __m512i __b) {
241		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
242		(__mmask32)-1);
243		}
244
245		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
246		_mm512_mask_cmple_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
247		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 2,
248		__u);
249		}
250
251		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
252		_mm512_cmplt_epi8_mask(__m512i __a, __m512i __b) {
253		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
254		(__mmask64)-1);
255		}
256
257		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
258		_mm512_mask_cmplt_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
259		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
260		__u);
261		}
262
263		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
264		_mm512_cmplt_epu8_mask(__m512i __a, __m512i __b) {
265		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
266		(__mmask64)-1);
267		}
268
269		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
270		_mm512_mask_cmplt_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
271		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 1,
272		__u);
273		}
274
275		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
276		_mm512_cmplt_epi16_mask(__m512i __a, __m512i __b) {
277		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
278		(__mmask32)-1);
279		}
280
281		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
282		_mm512_mask_cmplt_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
283		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
284		__u);
285		}
286
287		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
288		_mm512_cmplt_epu16_mask(__m512i __a, __m512i __b) {
289		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
290		(__mmask32)-1);
291		}
292
293		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
294		_mm512_mask_cmplt_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
295		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 1,
296		__u);
297		}
	59	#define _mm512_cmp_epi8_mask(a, b, p) __extension__ ({ \
	60	(__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)(__m512i)(a), \
	61	(__v64qi)(__m512i)(b), (int)(p), \
	62	(__mmask64)-1); })
298	63
299		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
300		_mm512_cmpneq_epi8_mask(__m512i __a, __m512i __b) {
301		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
302		(__mmask64)-1);
303		}
	64	#define _mm512_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
	65	(__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)(__m512i)(a), \
	66	(__v64qi)(__m512i)(b), (int)(p), \
	67	(__mmask64)(m)); })
304	68
305		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
306		_mm512_mask_cmpneq_epi8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
307		return (__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
308		__u);
309		}
	69	#define _mm512_cmp_epu8_mask(a, b, p) __extension__ ({ \
	70	(__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)(__m512i)(a), \
	71	(__v64qi)(__m512i)(b), (int)(p), \
	72	(__mmask64)-1); })
310	73
311		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
312		_mm512_cmpneq_epu8_mask(__m512i __a, __m512i __b) {
313		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
314		(__mmask64)-1);
315		}
	74	#define _mm512_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
	75	(__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)(__m512i)(a), \
	76	(__v64qi)(__m512i)(b), (int)(p), \
	77	(__mmask64)(m)); })
316	78
317		static __inline__ __mmask64 __DEFAULT_FN_ATTRS
318		_mm512_mask_cmpneq_epu8_mask(__mmask64 __u, __m512i __a, __m512i __b) {
319		return (__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)__a, (__v64qi)__b, 4,
320		__u);
321		}
	79	#define _mm512_cmp_epi16_mask(a, b, p) __extension__ ({ \
	80	(__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)(__m512i)(a), \
	81	(__v32hi)(__m512i)(b), (int)(p), \
	82	(__mmask32)-1); })
322	83
323		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
324		_mm512_cmpneq_epi16_mask(__m512i __a, __m512i __b) {
325		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
326		(__mmask32)-1);
327		}
	84	#define _mm512_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
	85	(__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)(__m512i)(a), \
	86	(__v32hi)(__m512i)(b), (int)(p), \
	87	(__mmask32)(m)); })
328	88
329		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
330		_mm512_mask_cmpneq_epi16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
331		return (__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
332		__u);
333		}
	89	#define _mm512_cmp_epu16_mask(a, b, p) __extension__ ({ \
	90	(__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)(__m512i)(a), \
	91	(__v32hi)(__m512i)(b), (int)(p), \
	92	(__mmask32)-1); })
334	93
335		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
336		_mm512_cmpneq_epu16_mask(__m512i __a, __m512i __b) {
337		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
338		(__mmask32)-1);
339		}
	94	#define _mm512_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
	95	(__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)(__m512i)(a), \
	96	(__v32hi)(__m512i)(b), (int)(p), \
	97	(__mmask32)(m)); })
340	98
341		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
342		_mm512_mask_cmpneq_epu16_mask(__mmask32 __u, __m512i __a, __m512i __b) {
343		return (__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)__a, (__v32hi)__b, 4,
344		__u);
345		}
	99	#define _mm512_cmpeq_epi8_mask(A, B) \
	100	_mm512_cmp_epi8_mask((A), (B), _MM_CMPINT_EQ)
	101	#define _mm512_mask_cmpeq_epi8_mask(k, A, B) \
	102	_mm512_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_EQ)
	103	#define _mm512_cmpge_epi8_mask(A, B) \
	104	_mm512_cmp_epi8_mask((A), (B), _MM_CMPINT_GE)
	105	#define _mm512_mask_cmpge_epi8_mask(k, A, B) \
	106	_mm512_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_GE)
	107	#define _mm512_cmpgt_epi8_mask(A, B) \
	108	_mm512_cmp_epi8_mask((A), (B), _MM_CMPINT_GT)
	109	#define _mm512_mask_cmpgt_epi8_mask(k, A, B) \
	110	_mm512_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_GT)
	111	#define _mm512_cmple_epi8_mask(A, B) \
	112	_mm512_cmp_epi8_mask((A), (B), _MM_CMPINT_LE)
	113	#define _mm512_mask_cmple_epi8_mask(k, A, B) \
	114	_mm512_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_LE)
	115	#define _mm512_cmplt_epi8_mask(A, B) \
	116	_mm512_cmp_epi8_mask((A), (B), _MM_CMPINT_LT)
	117	#define _mm512_mask_cmplt_epi8_mask(k, A, B) \
	118	_mm512_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_LT)
	119	#define _mm512_cmpneq_epi8_mask(A, B) \
	120	_mm512_cmp_epi8_mask((A), (B), _MM_CMPINT_NE)
	121	#define _mm512_mask_cmpneq_epi8_mask(k, A, B) \
	122	_mm512_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_NE)
	123
	124	#define _mm512_cmpeq_epu8_mask(A, B) \
	125	_mm512_cmp_epu8_mask((A), (B), _MM_CMPINT_EQ)
	126	#define _mm512_mask_cmpeq_epu8_mask(k, A, B) \
	127	_mm512_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_EQ)
	128	#define _mm512_cmpge_epu8_mask(A, B) \
	129	_mm512_cmp_epu8_mask((A), (B), _MM_CMPINT_GE)
	130	#define _mm512_mask_cmpge_epu8_mask(k, A, B) \
	131	_mm512_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_GE)
	132	#define _mm512_cmpgt_epu8_mask(A, B) \
	133	_mm512_cmp_epu8_mask((A), (B), _MM_CMPINT_GT)
	134	#define _mm512_mask_cmpgt_epu8_mask(k, A, B) \
	135	_mm512_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_GT)
	136	#define _mm512_cmple_epu8_mask(A, B) \
	137	_mm512_cmp_epu8_mask((A), (B), _MM_CMPINT_LE)
	138	#define _mm512_mask_cmple_epu8_mask(k, A, B) \
	139	_mm512_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_LE)
	140	#define _mm512_cmplt_epu8_mask(A, B) \
	141	_mm512_cmp_epu8_mask((A), (B), _MM_CMPINT_LT)
	142	#define _mm512_mask_cmplt_epu8_mask(k, A, B) \
	143	_mm512_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_LT)
	144	#define _mm512_cmpneq_epu8_mask(A, B) \
	145	_mm512_cmp_epu8_mask((A), (B), _MM_CMPINT_NE)
	146	#define _mm512_mask_cmpneq_epu8_mask(k, A, B) \
	147	_mm512_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_NE)
	148
	149	#define _mm512_cmpeq_epi16_mask(A, B) \
	150	_mm512_cmp_epi16_mask((A), (B), _MM_CMPINT_EQ)
	151	#define _mm512_mask_cmpeq_epi16_mask(k, A, B) \
	152	_mm512_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_EQ)
	153	#define _mm512_cmpge_epi16_mask(A, B) \
	154	_mm512_cmp_epi16_mask((A), (B), _MM_CMPINT_GE)
	155	#define _mm512_mask_cmpge_epi16_mask(k, A, B) \
	156	_mm512_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_GE)
	157	#define _mm512_cmpgt_epi16_mask(A, B) \
	158	_mm512_cmp_epi16_mask((A), (B), _MM_CMPINT_GT)
	159	#define _mm512_mask_cmpgt_epi16_mask(k, A, B) \
	160	_mm512_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_GT)
	161	#define _mm512_cmple_epi16_mask(A, B) \
	162	_mm512_cmp_epi16_mask((A), (B), _MM_CMPINT_LE)
	163	#define _mm512_mask_cmple_epi16_mask(k, A, B) \
	164	_mm512_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_LE)
	165	#define _mm512_cmplt_epi16_mask(A, B) \
	166	_mm512_cmp_epi16_mask((A), (B), _MM_CMPINT_LT)
	167	#define _mm512_mask_cmplt_epi16_mask(k, A, B) \
	168	_mm512_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_LT)
	169	#define _mm512_cmpneq_epi16_mask(A, B) \
	170	_mm512_cmp_epi16_mask((A), (B), _MM_CMPINT_NE)
	171	#define _mm512_mask_cmpneq_epi16_mask(k, A, B) \
	172	_mm512_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_NE)
	173
	174	#define _mm512_cmpeq_epu16_mask(A, B) \
	175	_mm512_cmp_epu16_mask((A), (B), _MM_CMPINT_EQ)
	176	#define _mm512_mask_cmpeq_epu16_mask(k, A, B) \
	177	_mm512_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_EQ)
	178	#define _mm512_cmpge_epu16_mask(A, B) \
	179	_mm512_cmp_epu16_mask((A), (B), _MM_CMPINT_GE)
	180	#define _mm512_mask_cmpge_epu16_mask(k, A, B) \
	181	_mm512_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_GE)
	182	#define _mm512_cmpgt_epu16_mask(A, B) \
	183	_mm512_cmp_epu16_mask((A), (B), _MM_CMPINT_GT)
	184	#define _mm512_mask_cmpgt_epu16_mask(k, A, B) \
	185	_mm512_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_GT)
	186	#define _mm512_cmple_epu16_mask(A, B) \
	187	_mm512_cmp_epu16_mask((A), (B), _MM_CMPINT_LE)
	188	#define _mm512_mask_cmple_epu16_mask(k, A, B) \
	189	_mm512_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_LE)
	190	#define _mm512_cmplt_epu16_mask(A, B) \
	191	_mm512_cmp_epu16_mask((A), (B), _MM_CMPINT_LT)
	192	#define _mm512_mask_cmplt_epu16_mask(k, A, B) \
	193	_mm512_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_LT)
	194	#define _mm512_cmpneq_epu16_mask(A, B) \
	195	_mm512_cmp_epu16_mask((A), (B), _MM_CMPINT_NE)
	196	#define _mm512_mask_cmpneq_epu16_mask(k, A, B) \
	197	_mm512_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_NE)
346	198
347	199	static __inline__ __m512i __DEFAULT_FN_ATTRS
348	200	_mm512_add_epi8 (__m512i __A, __m512i __B) {
...	...	@@ -1541,46 +1393,6 @@ _mm512_maskz_cvtepu8_epi16(__mmask32 __U, __m256i __A)
1541	1393	}
1542	1394
1543	1395
1544		#define _mm512_cmp_epi8_mask(a, b, p) __extension__ ({ \
1545		(__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)(__m512i)(a), \
1546		(__v64qi)(__m512i)(b), (int)(p), \
1547		(__mmask64)-1); })
1548
1549		#define _mm512_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
1550		(__mmask64)__builtin_ia32_cmpb512_mask((__v64qi)(__m512i)(a), \
1551		(__v64qi)(__m512i)(b), (int)(p), \
1552		(__mmask64)(m)); })
1553
1554		#define _mm512_cmp_epu8_mask(a, b, p) __extension__ ({ \
1555		(__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)(__m512i)(a), \
1556		(__v64qi)(__m512i)(b), (int)(p), \
1557		(__mmask64)-1); })
1558
1559		#define _mm512_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
1560		(__mmask64)__builtin_ia32_ucmpb512_mask((__v64qi)(__m512i)(a), \
1561		(__v64qi)(__m512i)(b), (int)(p), \
1562		(__mmask64)(m)); })
1563
1564		#define _mm512_cmp_epi16_mask(a, b, p) __extension__ ({ \
1565		(__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)(__m512i)(a), \
1566		(__v32hi)(__m512i)(b), (int)(p), \
1567		(__mmask32)-1); })
1568
1569		#define _mm512_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
1570		(__mmask32)__builtin_ia32_cmpw512_mask((__v32hi)(__m512i)(a), \
1571		(__v32hi)(__m512i)(b), (int)(p), \
1572		(__mmask32)(m)); })
1573
1574		#define _mm512_cmp_epu16_mask(a, b, p) __extension__ ({ \
1575		(__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)(__m512i)(a), \
1576		(__v32hi)(__m512i)(b), (int)(p), \
1577		(__mmask32)-1); })
1578
1579		#define _mm512_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
1580		(__mmask32)__builtin_ia32_ucmpw512_mask((__v32hi)(__m512i)(a), \
1581		(__v32hi)(__m512i)(b), (int)(p), \
1582		(__mmask32)(m)); })
1583
1584	1396	#define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \
1585	1397	(__m512i)__builtin_shufflevector((__v32hi)(__m512i)(A), \
1586	1398	(__v32hi)_mm512_undefined_epi32(), \
...	...	@@ -2042,15 +1854,13 @@ _mm512_maskz_set1_epi8 (__mmask64 __M, char __A)
2042	1854	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2043	1855	_mm512_kunpackd (__mmask64 __A, __mmask64 __B)
2044	1856	{
2045		return (__mmask64) __builtin_ia32_kunpckdi ((__mmask64) __A,
2046		(__mmask64) __B);
	1857	return (__mmask64) (( __A & 0xFFFFFFFF) \| ( __B << 32));
2047	1858	}
2048	1859
2049	1860	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2050	1861	_mm512_kunpackw (__mmask32 __A, __mmask32 __B)
2051	1862	{
2052		return (__mmask32) __builtin_ia32_kunpcksi ((__mmask32) __A,
2053		(__mmask32) __B);
	1863	return (__mmask32) (( __A & 0xFFFF) \| ( __B << 16));
2054	1864	}
2055	1865
2056	1866	static __inline__ __m512i __DEFAULT_FN_ATTRS
...	...	@@ -2105,61 +1915,56 @@ _mm512_mask_storeu_epi8 (void *__P, __mmask64 __U, __m512i __A)
2105	1915	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2106	1916	_mm512_test_epi8_mask (__m512i __A, __m512i __B)
2107	1917	{
2108		return (__mmask64) __builtin_ia32_ptestmb512 ((__v64qi) __A,
2109		(__v64qi) __B,
2110		(__mmask64) -1);
	1918	return _mm512_cmpneq_epi8_mask (_mm512_and_epi32 (__A, __B),
	1919	_mm512_setzero_qi());
2111	1920	}
2112	1921
2113	1922	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2114	1923	_mm512_mask_test_epi8_mask (__mmask64 __U, __m512i __A, __m512i __B)
2115	1924	{
2116		return (__mmask64) __builtin_ia32_ptestmb512 ((__v64qi) __A,
2117		(__v64qi) __B, __U);
	1925	return _mm512_mask_cmpneq_epi8_mask (__U, _mm512_and_epi32 (__A, __B),
	1926	_mm512_setzero_qi());
2118	1927	}
2119	1928
2120	1929	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2121	1930	_mm512_test_epi16_mask (__m512i __A, __m512i __B)
2122	1931	{
2123		return (__mmask32) __builtin_ia32_ptestmw512 ((__v32hi) __A,
2124		(__v32hi) __B,
2125		(__mmask32) -1);
	1932	return _mm512_cmpneq_epi16_mask (_mm512_and_epi32 (__A, __B),
	1933	_mm512_setzero_qi());
2126	1934	}
2127	1935
2128	1936	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2129	1937	_mm512_mask_test_epi16_mask (__mmask32 __U, __m512i __A, __m512i __B)
2130	1938	{
2131		return (__mmask32) __builtin_ia32_ptestmw512 ((__v32hi) __A,
2132		(__v32hi) __B, __U);
	1939	return _mm512_mask_cmpneq_epi16_mask (__U, _mm512_and_epi32 (__A, __B),
	1940	_mm512_setzero_qi());
2133	1941	}
2134	1942
2135	1943	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2136	1944	_mm512_testn_epi8_mask (__m512i __A, __m512i __B)
2137	1945	{
2138		return (__mmask64) __builtin_ia32_ptestnmb512 ((__v64qi) __A,
2139		(__v64qi) __B,
2140		(__mmask64) -1);
	1946	return _mm512_cmpeq_epi8_mask (_mm512_and_epi32 (__A, __B), _mm512_setzero_qi());
2141	1947	}
2142	1948
2143	1949	static __inline__ __mmask64 __DEFAULT_FN_ATTRS
2144	1950	_mm512_mask_testn_epi8_mask (__mmask64 __U, __m512i __A, __m512i __B)
2145	1951	{
2146		return (__mmask64) __builtin_ia32_ptestnmb512 ((__v64qi) __A,
2147		(__v64qi) __B, __U);
	1952	return _mm512_mask_cmpeq_epi8_mask (__U, _mm512_and_epi32 (__A, __B),
	1953	_mm512_setzero_qi());
2148	1954	}
2149	1955
2150	1956	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2151	1957	_mm512_testn_epi16_mask (__m512i __A, __m512i __B)
2152	1958	{
2153		return (__mmask32) __builtin_ia32_ptestnmw512 ((__v32hi) __A,
2154		(__v32hi) __B,
2155		(__mmask32) -1);
	1959	return _mm512_cmpeq_epi16_mask (_mm512_and_epi32 (__A, __B),
	1960	_mm512_setzero_qi());
2156	1961	}
2157	1962
2158	1963	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2159	1964	_mm512_mask_testn_epi16_mask (__mmask32 __U, __m512i __A, __m512i __B)
2160	1965	{
2161		return (__mmask32) __builtin_ia32_ptestnmw512 ((__v32hi) __A,
2162		(__v32hi) __B, __U);
	1966	return _mm512_mask_cmpeq_epi16_mask (__U, _mm512_and_epi32 (__A, __B),
	1967	_mm512_setzero_qi());
2163	1968	}
2164	1969
2165	1970	static __inline__ __mmask64 __DEFAULT_FN_ATTRS

c_headers/avx512cdintrin.h+3-2

...	...	@@ -130,13 +130,14 @@ _mm512_maskz_lzcnt_epi64 (__mmask8 __U, __m512i __A)
130	130	static __inline__ __m512i __DEFAULT_FN_ATTRS
131	131	_mm512_broadcastmb_epi64 (__mmask8 __A)
132	132	{
133		return (__m512i) __builtin_ia32_broadcastmb512 (__A);
	133	return (__m512i) _mm512_set1_epi64((long long) __A);
134	134	}
135	135
136	136	static __inline__ __m512i __DEFAULT_FN_ATTRS
137	137	_mm512_broadcastmw_epi32 (__mmask16 __A)
138	138	{
139		return (__m512i) __builtin_ia32_broadcastmw512 (__A);
	139	return (__m512i) _mm512_set1_epi32((int) __A);
	140
140	141	}
141	142
142	143	#undef __DEFAULT_FN_ATTRS

c_headers/avx512fintrin.h+1-1

...	...	@@ -8787,7 +8787,7 @@ _mm512_kortestz (__mmask16 __A, __mmask16 __B)
8787	8787	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
8788	8788	_mm512_kunpackb (__mmask16 __A, __mmask16 __B)
8789	8789	{
8790		return (__mmask16) __builtin_ia32_kunpckhi ((__mmask16) __A, (__mmask16) __B);
	8790	return (__mmask16) (( __A & 0xFF) \| ( __B << 8));
8791	8791	}
8792	8792
8793	8793	static __inline__ __mmask16 __DEFAULT_FN_ATTRS

c_headers/avx512vbmi2intrin.h created+391

...	...	@@ -0,0 +1,391 @@
	1	/*===------------- avx512vbmi2intrin.h - VBMI2 intrinsics ------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <avx512vbmi2intrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __AVX512VBMI2INTRIN_H
	29	#define __AVX512VBMI2INTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi2")))
	33
	34
	35	static __inline__ __m512i __DEFAULT_FN_ATTRS
	36	_mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D)
	37	{
	38	return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
	39	(__v32hi) __S,
	40	__U);
	41	}
	42
	43	static __inline__ __m512i __DEFAULT_FN_ATTRS
	44	_mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D)
	45	{
	46	return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
	47	(__v32hi) _mm512_setzero_hi(),
	48	__U);
	49	}
	50
	51	static __inline__ __m512i __DEFAULT_FN_ATTRS
	52	_mm512_mask_compress_epi8(__m512i __S, __mmask64 __U, __m512i __D)
	53	{
	54	return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
	55	(__v64qi) __S,
	56	__U);
	57	}
	58
	59	static __inline__ __m512i __DEFAULT_FN_ATTRS
	60	_mm512_maskz_compress_epi8(__mmask64 __U, __m512i __D)
	61	{
	62	return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
	63	(__v64qi) _mm512_setzero_qi(),
	64	__U);
	65	}
	66
	67	static __inline__ void __DEFAULT_FN_ATTRS
	68	_mm512_mask_compressstoreu_epi16(void *__P, __mmask32 __U, __m512i __D)
	69	{
	70	__builtin_ia32_compressstorehi512_mask ((__v32hi *) __P, (__v32hi) __D,
	71	__U);
	72	}
	73
	74	static __inline__ void __DEFAULT_FN_ATTRS
	75	_mm512_mask_compressstoreu_epi8(void *__P, __mmask64 __U, __m512i __D)
	76	{
	77	__builtin_ia32_compressstoreqi512_mask ((__v64qi *) __P, (__v64qi) __D,
	78	__U);
	79	}
	80
	81	static __inline__ __m512i __DEFAULT_FN_ATTRS
	82	_mm512_mask_expand_epi16(__m512i __S, __mmask32 __U, __m512i __D)
	83	{
	84	return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
	85	(__v32hi) __S,
	86	__U);
	87	}
	88
	89	static __inline__ __m512i __DEFAULT_FN_ATTRS
	90	_mm512_maskz_expand_epi16(__mmask32 __U, __m512i __D)
	91	{
	92	return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
	93	(__v32hi) _mm512_setzero_hi(),
	94	__U);
	95	}
	96
	97	static __inline__ __m512i __DEFAULT_FN_ATTRS
	98	_mm512_mask_expand_epi8(__m512i __S, __mmask64 __U, __m512i __D)
	99	{
	100	return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
	101	(__v64qi) __S,
	102	__U);
	103	}
	104
	105	static __inline__ __m512i __DEFAULT_FN_ATTRS
	106	_mm512_maskz_expand_epi8(__mmask64 __U, __m512i __D)
	107	{
	108	return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
	109	(__v64qi) _mm512_setzero_qi(),
	110	__U);
	111	}
	112
	113	static __inline__ __m512i __DEFAULT_FN_ATTRS
	114	_mm512_mask_expandloadu_epi16(__m512i __S, __mmask32 __U, void const *__P)
	115	{
	116	return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *)__P,
	117	(__v32hi) __S,
	118	__U);
	119	}
	120
	121	static __inline__ __m512i __DEFAULT_FN_ATTRS
	122	_mm512_maskz_expandloadu_epi16(__mmask32 __U, void const *__P)
	123	{
	124	return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *)__P,
	125	(__v32hi) _mm512_setzero_hi(),
	126	__U);
	127	}
	128
	129	static __inline__ __m512i __DEFAULT_FN_ATTRS
	130	_mm512_mask_expandloadu_epi8(__m512i __S, __mmask64 __U, void const *__P)
	131	{
	132	return (__m512i) __builtin_ia32_expandloadqi512_mask ((const __v64qi *)__P,
	133	(__v64qi) __S,
	134	__U);
	135	}
	136
	137	static __inline__ __m512i __DEFAULT_FN_ATTRS
	138	_mm512_maskz_expandloadu_epi8(__mmask64 __U, void const *__P)
	139	{
	140	return (__m512i) __builtin_ia32_expandloadqi512_mask ((const __v64qi *)__P,
	141	(__v64qi) _mm512_setzero_qi(),
	142	__U);
	143	}
	144
	145	#define _mm512_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \
	146	(__m512i)__builtin_ia32_vpshldq512_mask((__v8di)(A), \
	147	(__v8di)(B), \
	148	(int)(I), \
	149	(__v8di)(S), \
	150	(__mmask8)(U)); })
	151
	152	#define _mm512_maskz_shldi_epi64(U, A, B, I) \
	153	_mm512_mask_shldi_epi64(_mm512_setzero_hi(), (U), (A), (B), (I))
	154
	155	#define _mm512_shldi_epi64(A, B, I) \
	156	_mm512_mask_shldi_epi64(_mm512_undefined(), (__mmask8)(-1), (A), (B), (I))
	157
	158	#define _mm512_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \
	159	(__m512i)__builtin_ia32_vpshldd512_mask((__v16si)(A), \
	160	(__v16si)(B), \
	161	(int)(I), \
	162	(__v16si)(S), \
	163	(__mmask16)(U)); })
	164
	165	#define _mm512_maskz_shldi_epi32(U, A, B, I) \
	166	_mm512_mask_shldi_epi32(_mm512_setzero_hi(), (U), (A), (B), (I))
	167
	168	#define _mm512_shldi_epi32(A, B, I) \
	169	_mm512_mask_shldi_epi32(_mm512_undefined(), (__mmask16)(-1), (A), (B), (I))
	170
	171	#define _mm512_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \
	172	(__m512i)__builtin_ia32_vpshldw512_mask((__v32hi)(A), \
	173	(__v32hi)(B), \
	174	(int)(I), \
	175	(__v32hi)(S), \
	176	(__mmask32)(U)); })
	177
	178	#define _mm512_maskz_shldi_epi16(U, A, B, I) \
	179	_mm512_mask_shldi_epi16(_mm512_setzero_hi(), (U), (A), (B), (I))
	180
	181	#define _mm512_shldi_epi16(A, B, I) \
	182	_mm512_mask_shldi_epi16(_mm512_undefined(), (__mmask32)(-1), (A), (B), (I))
	183
	184	#define _mm512_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \
	185	(__m512i)__builtin_ia32_vpshrdq512_mask((__v8di)(A), \
	186	(__v8di)(B), \
	187	(int)(I), \
	188	(__v8di)(S), \
	189	(__mmask8)(U)); })
	190
	191	#define _mm512_maskz_shrdi_epi64(U, A, B, I) \
	192	_mm512_mask_shrdi_epi64(_mm512_setzero_hi(), (U), (A), (B), (I))
	193
	194	#define _mm512_shrdi_epi64(A, B, I) \
	195	_mm512_mask_shrdi_epi64(_mm512_undefined(), (__mmask8)(-1), (A), (B), (I))
	196
	197	#define _mm512_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \
	198	(__m512i)__builtin_ia32_vpshrdd512_mask((__v16si)(A), \
	199	(__v16si)(B), \
	200	(int)(I), \
	201	(__v16si)(S), \
	202	(__mmask16)(U)); })
	203
	204	#define _mm512_maskz_shrdi_epi32(U, A, B, I) \
	205	_mm512_mask_shrdi_epi32(_mm512_setzero_hi(), (U), (A), (B), (I))
	206
	207	#define _mm512_shrdi_epi32(A, B, I) \
	208	_mm512_mask_shrdi_epi32(_mm512_undefined(), (__mmask16)(-1), (A), (B), (I))
	209
	210	#define _mm512_mask_shrdi_epi16(S, U, A, B, I) __extension__ ({ \
	211	(__m512i)__builtin_ia32_vpshrdw512_mask((__v32hi)(A), \
	212	(__v32hi)(B), \
	213	(int)(I), \
	214	(__v32hi)(S), \
	215	(__mmask32)(U)); })
	216
	217	#define _mm512_maskz_shrdi_epi16(U, A, B, I) \
	218	_mm512_mask_shrdi_epi16(_mm512_setzero_hi(), (U), (A), (B), (I))
	219
	220	#define _mm512_shrdi_epi16(A, B, I) \
	221	_mm512_mask_shrdi_epi16(_mm512_undefined(), (__mmask32)(-1), (A), (B), (I))
	222
	223	static __inline__ __m512i __DEFAULT_FN_ATTRS
	224	_mm512_mask_shldv_epi64(__m512i __S, __mmask8 __U, __m512i __A, __m512i __B)
	225	{
	226	return (__m512i) __builtin_ia32_vpshldvq512_mask ((__v8di) __S,
	227	(__v8di) __A,
	228	(__v8di) __B,
	229	__U);
	230	}
	231
	232	static __inline__ __m512i __DEFAULT_FN_ATTRS
	233	_mm512_maskz_shldv_epi64(__mmask8 __U, __m512i __S, __m512i __A, __m512i __B)
	234	{
	235	return (__m512i) __builtin_ia32_vpshldvq512_maskz ((__v8di) __S,
	236	(__v8di) __A,
	237	(__v8di) __B,
	238	__U);
	239	}
	240
	241	static __inline__ __m512i __DEFAULT_FN_ATTRS
	242	_mm512_shldv_epi64(__m512i __S, __m512i __A, __m512i __B)
	243	{
	244	return (__m512i) __builtin_ia32_vpshldvq512_mask ((__v8di) __S,
	245	(__v8di) __A,
	246	(__v8di) __B,
	247	(__mmask8) -1);
	248	}
	249
	250	static __inline__ __m512i __DEFAULT_FN_ATTRS
	251	_mm512_mask_shldv_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
	252	{
	253	return (__m512i) __builtin_ia32_vpshldvd512_mask ((__v16si) __S,
	254	(__v16si) __A,
	255	(__v16si) __B,
	256	__U);
	257	}
	258
	259	static __inline__ __m512i __DEFAULT_FN_ATTRS
	260	_mm512_maskz_shldv_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
	261	{
	262	return (__m512i) __builtin_ia32_vpshldvd512_maskz ((__v16si) __S,
	263	(__v16si) __A,
	264	(__v16si) __B,
	265	__U);
	266	}
	267
	268	static __inline__ __m512i __DEFAULT_FN_ATTRS
	269	_mm512_shldv_epi32(__m512i __S, __m512i __A, __m512i __B)
	270	{
	271	return (__m512i) __builtin_ia32_vpshldvd512_mask ((__v16si) __S,
	272	(__v16si) __A,
	273	(__v16si) __B,
	274	(__mmask16) -1);
	275	}
	276
	277
	278	static __inline__ __m512i __DEFAULT_FN_ATTRS
	279	_mm512_mask_shldv_epi16(__m512i __S, __mmask32 __U, __m512i __A, __m512i __B)
	280	{
	281	return (__m512i) __builtin_ia32_vpshldvw512_mask ((__v32hi) __S,
	282	(__v32hi) __A,
	283	(__v32hi) __B,
	284	__U);
	285	}
	286
	287	static __inline__ __m512i __DEFAULT_FN_ATTRS
	288	_mm512_maskz_shldv_epi16(__mmask32 __U, __m512i __S, __m512i __A, __m512i __B)
	289	{
	290	return (__m512i) __builtin_ia32_vpshldvw512_maskz ((__v32hi) __S,
	291	(__v32hi) __A,
	292	(__v32hi) __B,
	293	__U);
	294	}
	295
	296	static __inline__ __m512i __DEFAULT_FN_ATTRS
	297	_mm512_shldv_epi16(__m512i __S, __m512i __A, __m512i __B)
	298	{
	299	return (__m512i) __builtin_ia32_vpshldvw512_mask ((__v32hi) __S,
	300	(__v32hi) __A,
	301	(__v32hi) __B,
	302	(__mmask32) -1);
	303	}
	304
	305	static __inline__ __m512i __DEFAULT_FN_ATTRS
	306	_mm512_mask_shrdv_epi64(__m512i __S, __mmask8 __U, __m512i __A, __m512i __B)
	307	{
	308	return (__m512i) __builtin_ia32_vpshrdvq512_mask ((__v8di) __S,
	309	(__v8di) __A,
	310	(__v8di) __B,
	311	__U);
	312	}
	313
	314	static __inline__ __m512i __DEFAULT_FN_ATTRS
	315	_mm512_maskz_shrdv_epi64(__mmask8 __U, __m512i __S, __m512i __A, __m512i __B)
	316	{
	317	return (__m512i) __builtin_ia32_vpshrdvq512_maskz ((__v8di) __S,
	318	(__v8di) __A,
	319	(__v8di) __B,
	320	__U);
	321	}
	322
	323	static __inline__ __m512i __DEFAULT_FN_ATTRS
	324	_mm512_shrdv_epi64(__m512i __S, __m512i __A, __m512i __B)
	325	{
	326	return (__m512i) __builtin_ia32_vpshrdvq512_mask ((__v8di) __S,
	327	(__v8di) __A,
	328	(__v8di) __B,
	329	(__mmask8) -1);
	330	}
	331
	332	static __inline__ __m512i __DEFAULT_FN_ATTRS
	333	_mm512_mask_shrdv_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
	334	{
	335	return (__m512i) __builtin_ia32_vpshrdvd512_mask ((__v16si) __S,
	336	(__v16si) __A,
	337	(__v16si) __B,
	338	__U);
	339	}
	340
	341	static __inline__ __m512i __DEFAULT_FN_ATTRS
	342	_mm512_maskz_shrdv_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
	343	{
	344	return (__m512i) __builtin_ia32_vpshrdvd512_maskz ((__v16si) __S,
	345	(__v16si) __A,
	346	(__v16si) __B,
	347	__U);
	348	}
	349
	350	static __inline__ __m512i __DEFAULT_FN_ATTRS
	351	_mm512_shrdv_epi32(__m512i __S, __m512i __A, __m512i __B)
	352	{
	353	return (__m512i) __builtin_ia32_vpshrdvd512_mask ((__v16si) __S,
	354	(__v16si) __A,
	355	(__v16si) __B,
	356	(__mmask16) -1);
	357	}
	358
	359
	360	static __inline__ __m512i __DEFAULT_FN_ATTRS
	361	_mm512_mask_shrdv_epi16(__m512i __S, __mmask32 __U, __m512i __A, __m512i __B)
	362	{
	363	return (__m512i) __builtin_ia32_vpshrdvw512_mask ((__v32hi) __S,
	364	(__v32hi) __A,
	365	(__v32hi) __B,
	366	__U);
	367	}
	368
	369	static __inline__ __m512i __DEFAULT_FN_ATTRS
	370	_mm512_maskz_shrdv_epi16(__mmask32 __U, __m512i __S, __m512i __A, __m512i __B)
	371	{
	372	return (__m512i) __builtin_ia32_vpshrdvw512_maskz ((__v32hi) __S,
	373	(__v32hi) __A,
	374	(__v32hi) __B,
	375	__U);
	376	}
	377
	378	static __inline__ __m512i __DEFAULT_FN_ATTRS
	379	_mm512_shrdv_epi16(__m512i __S, __m512i __A, __m512i __B)
	380	{
	381	return (__m512i) __builtin_ia32_vpshrdvw512_mask ((__v32hi) __S,
	382	(__v32hi) __A,
	383	(__v32hi) __B,
	384	(__mmask32) -1);
	385	}
	386
	387
	388	#undef __DEFAULT_FN_ATTRS
	389
	390	#endif
	391

c_headers/avx512vlbitalgintrin.h created+157

...	...	@@ -0,0 +1,157 @@
	1	/*===------------- avx512vlbitalgintrin.h - BITALG intrinsics ------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <avx512vlbitalgintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __AVX512VLBITALGINTRIN_H
	29	#define __AVX512VLBITALGINTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512bitalg")))
	33
	34	static __inline__ __m256i __DEFAULT_FN_ATTRS
	35	_mm256_popcnt_epi16(__m256i __A)
	36	{
	37	return (__m256i) __builtin_ia32_vpopcntw_256((__v16hi) __A);
	38	}
	39
	40	static __inline__ __m256i __DEFAULT_FN_ATTRS
	41	_mm256_mask_popcnt_epi16(__m256i __A, __mmask16 __U, __m256i __B)
	42	{
	43	return (__m256i) __builtin_ia32_selectw_256((__mmask16) __U,
	44	(__v16hi) _mm256_popcnt_epi16(__B),
	45	(__v16hi) __A);
	46	}
	47
	48	static __inline__ __m256i __DEFAULT_FN_ATTRS
	49	_mm256_maskz_popcnt_epi16(__mmask16 __U, __m256i __B)
	50	{
	51	return _mm256_mask_popcnt_epi16((__m256i) _mm256_setzero_si256(),
	52	__U,
	53	__B);
	54	}
	55
	56	static __inline__ __m128i __DEFAULT_FN_ATTRS
	57	_mm128_popcnt_epi16(__m128i __A)
	58	{
	59	return (__m128i) __builtin_ia32_vpopcntw_128((__v8hi) __A);
	60	}
	61
	62	static __inline__ __m128i __DEFAULT_FN_ATTRS
	63	_mm128_mask_popcnt_epi16(__m128i __A, __mmask8 __U, __m128i __B)
	64	{
	65	return (__m128i) __builtin_ia32_selectw_128((__mmask8) __U,
	66	(__v8hi) _mm128_popcnt_epi16(__B),
	67	(__v8hi) __A);
	68	}
	69
	70	static __inline__ __m128i __DEFAULT_FN_ATTRS
	71	_mm128_maskz_popcnt_epi16(__mmask8 __U, __m128i __B)
	72	{
	73	return _mm128_mask_popcnt_epi16((__m128i) _mm_setzero_si128(),
	74	__U,
	75	__B);
	76	}
	77
	78	static __inline__ __m256i __DEFAULT_FN_ATTRS
	79	_mm256_popcnt_epi8(__m256i __A)
	80	{
	81	return (__m256i) __builtin_ia32_vpopcntb_256((__v32qi) __A);
	82	}
	83
	84	static __inline__ __m256i __DEFAULT_FN_ATTRS
	85	_mm256_mask_popcnt_epi8(__m256i __A, __mmask32 __U, __m256i __B)
	86	{
	87	return (__m256i) __builtin_ia32_selectb_256((__mmask32) __U,
	88	(__v32qi) _mm256_popcnt_epi8(__B),
	89	(__v32qi) __A);
	90	}
	91
	92	static __inline__ __m256i __DEFAULT_FN_ATTRS
	93	_mm256_maskz_popcnt_epi8(__mmask32 __U, __m256i __B)
	94	{
	95	return _mm256_mask_popcnt_epi8((__m256i) _mm256_setzero_si256(),
	96	__U,
	97	__B);
	98	}
	99
	100	static __inline__ __m128i __DEFAULT_FN_ATTRS
	101	_mm128_popcnt_epi8(__m128i __A)
	102	{
	103	return (__m128i) __builtin_ia32_vpopcntb_128((__v16qi) __A);
	104	}
	105
	106	static __inline__ __m128i __DEFAULT_FN_ATTRS
	107	_mm128_mask_popcnt_epi8(__m128i __A, __mmask16 __U, __m128i __B)
	108	{
	109	return (__m128i) __builtin_ia32_selectb_128((__mmask16) __U,
	110	(__v16qi) _mm128_popcnt_epi8(__B),
	111	(__v16qi) __A);
	112	}
	113
	114	static __inline__ __m128i __DEFAULT_FN_ATTRS
	115	_mm128_maskz_popcnt_epi8(__mmask16 __U, __m128i __B)
	116	{
	117	return _mm128_mask_popcnt_epi8((__m128i) _mm_setzero_si128(),
	118	__U,
	119	__B);
	120	}
	121
	122	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
	123	_mm256_mask_bitshuffle_epi32_mask(__mmask32 __U, __m256i __A, __m256i __B)
	124	{
	125	return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask((__v32qi) __A,
	126	(__v32qi) __B,
	127	__U);
	128	}
	129
	130	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
	131	_mm256_bitshuffle_epi32_mask(__m256i __A, __m256i __B)
	132	{
	133	return _mm256_mask_bitshuffle_epi32_mask((__mmask32) -1,
	134	__A,
	135	__B);
	136	}
	137
	138	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
	139	_mm128_mask_bitshuffle_epi16_mask(__mmask16 __U, __m128i __A, __m128i __B)
	140	{
	141	return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask((__v16qi) __A,
	142	(__v16qi) __B,
	143	__U);
	144	}
	145
	146	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
	147	_mm128_bitshuffle_epi16_mask(__m128i __A, __m128i __B)
	148	{
	149	return _mm128_mask_bitshuffle_epi16_mask((__mmask16) -1,
	150	__A,
	151	__B);
	152	}
	153
	154
	155	#undef __DEFAULT_FN_ATTRS
	156
	157	#endif

c_headers/avx512vlbwintrin.h+290-679

...	...	@@ -38,581 +38,285 @@ _mm_setzero_hi(void){
38	38
39	39	/* Integer compare */
40	40
41		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
42		_mm_cmpeq_epi8_mask(__m128i __a, __m128i __b) {
43		return (__mmask16)__builtin_ia32_pcmpeqb128_mask((__v16qi)__a, (__v16qi)__b,
44		(__mmask16)-1);
45		}
46
47		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
48		_mm_mask_cmpeq_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
49		return (__mmask16)__builtin_ia32_pcmpeqb128_mask((__v16qi)__a, (__v16qi)__b,
50		__u);
51		}
52
53		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
54		_mm_cmpeq_epu8_mask(__m128i __a, __m128i __b) {
55		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 0,
56		(__mmask16)-1);
57		}
58
59		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
60		_mm_mask_cmpeq_epu8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
61		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 0,
62		__u);
63		}
64
65		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
66		_mm256_cmpeq_epi8_mask(__m256i __a, __m256i __b) {
67		return (__mmask32)__builtin_ia32_pcmpeqb256_mask((__v32qi)__a, (__v32qi)__b,
68		(__mmask32)-1);
69		}
70
71		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
72		_mm256_mask_cmpeq_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
73		return (__mmask32)__builtin_ia32_pcmpeqb256_mask((__v32qi)__a, (__v32qi)__b,
74		__u);
75		}
76
77		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
78		_mm256_cmpeq_epu8_mask(__m256i __a, __m256i __b) {
79		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 0,
80		(__mmask32)-1);
81		}
82
83		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
84		_mm256_mask_cmpeq_epu8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
85		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 0,
86		__u);
87		}
88
89		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
90		_mm_cmpeq_epi16_mask(__m128i __a, __m128i __b) {
91		return (__mmask8)__builtin_ia32_pcmpeqw128_mask((__v8hi)__a, (__v8hi)__b,
92		(__mmask8)-1);
93		}
94
95		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
96		_mm_mask_cmpeq_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
97		return (__mmask8)__builtin_ia32_pcmpeqw128_mask((__v8hi)__a, (__v8hi)__b,
98		__u);
99		}
100
101		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
102		_mm_cmpeq_epu16_mask(__m128i __a, __m128i __b) {
103		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 0,
104		(__mmask8)-1);
105		}
106
107		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
108		_mm_mask_cmpeq_epu16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
109		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 0,
110		__u);
111		}
112
113		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
114		_mm256_cmpeq_epi16_mask(__m256i __a, __m256i __b) {
115		return (__mmask16)__builtin_ia32_pcmpeqw256_mask((__v16hi)__a, (__v16hi)__b,
116		(__mmask16)-1);
117		}
118
119		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
120		_mm256_mask_cmpeq_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
121		return (__mmask16)__builtin_ia32_pcmpeqw256_mask((__v16hi)__a, (__v16hi)__b,
122		__u);
123		}
124
125		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
126		_mm256_cmpeq_epu16_mask(__m256i __a, __m256i __b) {
127		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 0,
128		(__mmask16)-1);
129		}
130
131		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
132		_mm256_mask_cmpeq_epu16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
133		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 0,
134		__u);
135		}
136
137		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
138		_mm_cmpge_epi8_mask(__m128i __a, __m128i __b) {
139		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 5,
140		(__mmask16)-1);
141		}
142
143		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
144		_mm_mask_cmpge_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
145		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 5,
146		__u);
147		}
148
149		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
150		_mm_cmpge_epu8_mask(__m128i __a, __m128i __b) {
151		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 5,
152		(__mmask16)-1);
153		}
154
155		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
156		_mm_mask_cmpge_epu8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
157		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 5,
158		__u);
159		}
160
161		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
162		_mm256_cmpge_epi8_mask(__m256i __a, __m256i __b) {
163		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 5,
164		(__mmask32)-1);
165		}
166
167		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
168		_mm256_mask_cmpge_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
169		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 5,
170		__u);
171		}
172
173		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
174		_mm256_cmpge_epu8_mask(__m256i __a, __m256i __b) {
175		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 5,
176		(__mmask32)-1);
177		}
178
179		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
180		_mm256_mask_cmpge_epu8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
181		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 5,
182		__u);
183		}
184
185		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
186		_mm_cmpge_epi16_mask(__m128i __a, __m128i __b) {
187		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 5,
188		(__mmask8)-1);
189		}
190
191		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
192		_mm_mask_cmpge_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
193		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 5,
194		__u);
195		}
196
197		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
198		_mm_cmpge_epu16_mask(__m128i __a, __m128i __b) {
199		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 5,
200		(__mmask8)-1);
201		}
202
203		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
204		_mm_mask_cmpge_epu16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
205		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 5,
206		__u);
207		}
208
209		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
210		_mm256_cmpge_epi16_mask(__m256i __a, __m256i __b) {
211		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 5,
212		(__mmask16)-1);
213		}
214
215		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
216		_mm256_mask_cmpge_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
217		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 5,
218		__u);
219		}
220
221		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
222		_mm256_cmpge_epu16_mask(__m256i __a, __m256i __b) {
223		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 5,
224		(__mmask16)-1);
225		}
226
227		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
228		_mm256_mask_cmpge_epu16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
229		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 5,
230		__u);
231		}
232
233		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
234		_mm_cmpgt_epi8_mask(__m128i __a, __m128i __b) {
235		return (__mmask16)__builtin_ia32_pcmpgtb128_mask((__v16qi)__a, (__v16qi)__b,
236		(__mmask16)-1);
237		}
238
239		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
240		_mm_mask_cmpgt_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
241		return (__mmask16)__builtin_ia32_pcmpgtb128_mask((__v16qi)__a, (__v16qi)__b,
242		__u);
243		}
244
245		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
246		_mm_cmpgt_epu8_mask(__m128i __a, __m128i __b) {
247		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 6,
248		(__mmask16)-1);
249		}
250
251		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
252		_mm_mask_cmpgt_epu8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
253		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 6,
254		__u);
255		}
256
257		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
258		_mm256_cmpgt_epi8_mask(__m256i __a, __m256i __b) {
259		return (__mmask32)__builtin_ia32_pcmpgtb256_mask((__v32qi)__a, (__v32qi)__b,
260		(__mmask32)-1);
261		}
262
263		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
264		_mm256_mask_cmpgt_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
265		return (__mmask32)__builtin_ia32_pcmpgtb256_mask((__v32qi)__a, (__v32qi)__b,
266		__u);
267		}
268
269		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
270		_mm256_cmpgt_epu8_mask(__m256i __a, __m256i __b) {
271		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 6,
272		(__mmask32)-1);
273		}
274
275		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
276		_mm256_mask_cmpgt_epu8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
277		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 6,
278		__u);
279		}
280
281		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
282		_mm_cmpgt_epi16_mask(__m128i __a, __m128i __b) {
283		return (__mmask8)__builtin_ia32_pcmpgtw128_mask((__v8hi)__a, (__v8hi)__b,
284		(__mmask8)-1);
285		}
286
287		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
288		_mm_mask_cmpgt_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
289		return (__mmask8)__builtin_ia32_pcmpgtw128_mask((__v8hi)__a, (__v8hi)__b,
290		__u);
291		}
292
293		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
294		_mm_cmpgt_epu16_mask(__m128i __a, __m128i __b) {
295		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 6,
296		(__mmask8)-1);
297		}
298
299		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
300		_mm_mask_cmpgt_epu16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
301		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 6,
302		__u);
303		}
304
305		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
306		_mm256_cmpgt_epi16_mask(__m256i __a, __m256i __b) {
307		return (__mmask16)__builtin_ia32_pcmpgtw256_mask((__v16hi)__a, (__v16hi)__b,
308		(__mmask16)-1);
309		}
310
311		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
312		_mm256_mask_cmpgt_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
313		return (__mmask16)__builtin_ia32_pcmpgtw256_mask((__v16hi)__a, (__v16hi)__b,
314		__u);
315		}
316
317		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
318		_mm256_cmpgt_epu16_mask(__m256i __a, __m256i __b) {
319		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 6,
320		(__mmask16)-1);
321		}
322
323		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
324		_mm256_mask_cmpgt_epu16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
325		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 6,
326		__u);
327		}
328
329		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
330		_mm_cmple_epi8_mask(__m128i __a, __m128i __b) {
331		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 2,
332		(__mmask16)-1);
333		}
334
335		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
336		_mm_mask_cmple_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
337		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 2,
338		__u);
339		}
340
341		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
342		_mm_cmple_epu8_mask(__m128i __a, __m128i __b) {
343		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 2,
344		(__mmask16)-1);
345		}
346
347		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
348		_mm_mask_cmple_epu8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
349		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 2,
350		__u);
351		}
352
353		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
354		_mm256_cmple_epi8_mask(__m256i __a, __m256i __b) {
355		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 2,
356		(__mmask32)-1);
357		}
358
359		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
360		_mm256_mask_cmple_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
361		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 2,
362		__u);
363		}
364
365		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
366		_mm256_cmple_epu8_mask(__m256i __a, __m256i __b) {
367		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 2,
368		(__mmask32)-1);
369		}
370
371		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
372		_mm256_mask_cmple_epu8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
373		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 2,
374		__u);
375		}
376
377		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
378		_mm_cmple_epi16_mask(__m128i __a, __m128i __b) {
379		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 2,
380		(__mmask8)-1);
381		}
382
383		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
384		_mm_mask_cmple_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
385		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 2,
386		__u);
387		}
388
389		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
390		_mm_cmple_epu16_mask(__m128i __a, __m128i __b) {
391		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 2,
392		(__mmask8)-1);
393		}
394
395		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
396		_mm_mask_cmple_epu16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
397		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 2,
398		__u);
399		}
400
401		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
402		_mm256_cmple_epi16_mask(__m256i __a, __m256i __b) {
403		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 2,
404		(__mmask16)-1);
405		}
406
407		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
408		_mm256_mask_cmple_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
409		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 2,
410		__u);
411		}
412
413		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
414		_mm256_cmple_epu16_mask(__m256i __a, __m256i __b) {
415		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 2,
416		(__mmask16)-1);
417		}
418
419		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
420		_mm256_mask_cmple_epu16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
421		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 2,
422		__u);
423		}
424
425		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
426		_mm_cmplt_epi8_mask(__m128i __a, __m128i __b) {
427		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 1,
428		(__mmask16)-1);
429		}
430
431		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
432		_mm_mask_cmplt_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
433		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 1,
434		__u);
435		}
436
437		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
438		_mm_cmplt_epu8_mask(__m128i __a, __m128i __b) {
439		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 1,
440		(__mmask16)-1);
441		}
442
443		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
444		_mm_mask_cmplt_epu8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
445		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 1,
446		__u);
447		}
448
449		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
450		_mm256_cmplt_epi8_mask(__m256i __a, __m256i __b) {
451		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 1,
452		(__mmask32)-1);
453		}
454
455		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
456		_mm256_mask_cmplt_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
457		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 1,
458		__u);
459		}
460
461		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
462		_mm256_cmplt_epu8_mask(__m256i __a, __m256i __b) {
463		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 1,
464		(__mmask32)-1);
465		}
466
467		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
468		_mm256_mask_cmplt_epu8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
469		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 1,
470		__u);
471		}
472
473		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
474		_mm_cmplt_epi16_mask(__m128i __a, __m128i __b) {
475		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 1,
476		(__mmask8)-1);
477		}
478
479		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
480		_mm_mask_cmplt_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
481		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 1,
482		__u);
483		}
484
485		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
486		_mm_cmplt_epu16_mask(__m128i __a, __m128i __b) {
487		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 1,
488		(__mmask8)-1);
489		}
490
491		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
492		_mm_mask_cmplt_epu16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
493		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 1,
494		__u);
495		}
496
497		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
498		_mm256_cmplt_epi16_mask(__m256i __a, __m256i __b) {
499		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 1,
500		(__mmask16)-1);
501		}
502
503		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
504		_mm256_mask_cmplt_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
505		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 1,
506		__u);
507		}
508
509		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
510		_mm256_cmplt_epu16_mask(__m256i __a, __m256i __b) {
511		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 1,
512		(__mmask16)-1);
513		}
514
515		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
516		_mm256_mask_cmplt_epu16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
517		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 1,
518		__u);
519		}
	41	#define _mm_cmp_epi8_mask(a, b, p) __extension__ ({ \
	42	(__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)(__m128i)(a), \
	43	(__v16qi)(__m128i)(b), (int)(p), \
	44	(__mmask16)-1); })
520	45
521		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
522		_mm_cmpneq_epi8_mask(__m128i __a, __m128i __b) {
523		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 4,
524		(__mmask16)-1);
525		}
	46	#define _mm_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
	47	(__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)(__m128i)(a), \
	48	(__v16qi)(__m128i)(b), (int)(p), \
	49	(__mmask16)(m)); })
526	50
527		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
528		_mm_mask_cmpneq_epi8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
529		return (__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)__a, (__v16qi)__b, 4,
530		__u);
531		}
	51	#define _mm_cmp_epu8_mask(a, b, p) __extension__ ({ \
	52	(__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)(__m128i)(a), \
	53	(__v16qi)(__m128i)(b), (int)(p), \
	54	(__mmask16)-1); })
532	55
533		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
534		_mm_cmpneq_epu8_mask(__m128i __a, __m128i __b) {
535		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 4,
536		(__mmask16)-1);
537		}
	56	#define _mm_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
	57	(__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)(__m128i)(a), \
	58	(__v16qi)(__m128i)(b), (int)(p), \
	59	(__mmask16)(m)); })
538	60
539		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
540		_mm_mask_cmpneq_epu8_mask(__mmask16 __u, __m128i __a, __m128i __b) {
541		return (__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)__a, (__v16qi)__b, 4,
542		__u);
543		}
	61	#define _mm256_cmp_epi8_mask(a, b, p) __extension__ ({ \
	62	(__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)(__m256i)(a), \
	63	(__v32qi)(__m256i)(b), (int)(p), \
	64	(__mmask32)-1); })
544	65
545		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
546		_mm256_cmpneq_epi8_mask(__m256i __a, __m256i __b) {
547		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 4,
548		(__mmask32)-1);
549		}
	66	#define _mm256_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
	67	(__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)(__m256i)(a), \
	68	(__v32qi)(__m256i)(b), (int)(p), \
	69	(__mmask32)(m)); })
550	70
551		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
552		_mm256_mask_cmpneq_epi8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
553		return (__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)__a, (__v32qi)__b, 4,
554		__u);
555		}
	71	#define _mm256_cmp_epu8_mask(a, b, p) __extension__ ({ \
	72	(__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)(__m256i)(a), \
	73	(__v32qi)(__m256i)(b), (int)(p), \
	74	(__mmask32)-1); })
556	75
557		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
558		_mm256_cmpneq_epu8_mask(__m256i __a, __m256i __b) {
559		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 4,
560		(__mmask32)-1);
561		}
	76	#define _mm256_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
	77	(__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)(__m256i)(a), \
	78	(__v32qi)(__m256i)(b), (int)(p), \
	79	(__mmask32)(m)); })
562	80
563		static __inline__ __mmask32 __DEFAULT_FN_ATTRS
564		_mm256_mask_cmpneq_epu8_mask(__mmask32 __u, __m256i __a, __m256i __b) {
565		return (__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)__a, (__v32qi)__b, 4,
566		__u);
567		}
	81	#define _mm_cmp_epi16_mask(a, b, p) __extension__ ({ \
	82	(__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)(__m128i)(a), \
	83	(__v8hi)(__m128i)(b), (int)(p), \
	84	(__mmask8)-1); })
568	85
569		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
570		_mm_cmpneq_epi16_mask(__m128i __a, __m128i __b) {
571		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 4,
572		(__mmask8)-1);
573		}
	86	#define _mm_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
	87	(__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)(__m128i)(a), \
	88	(__v8hi)(__m128i)(b), (int)(p), \
	89	(__mmask8)(m)); })
574	90
575		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
576		_mm_mask_cmpneq_epi16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
577		return (__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)__a, (__v8hi)__b, 4,
578		__u);
579		}
	91	#define _mm_cmp_epu16_mask(a, b, p) __extension__ ({ \
	92	(__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)(__m128i)(a), \
	93	(__v8hi)(__m128i)(b), (int)(p), \
	94	(__mmask8)-1); })
580	95
581		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
582		_mm_cmpneq_epu16_mask(__m128i __a, __m128i __b) {
583		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 4,
584		(__mmask8)-1);
585		}
	96	#define _mm_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
	97	(__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)(__m128i)(a), \
	98	(__v8hi)(__m128i)(b), (int)(p), \
	99	(__mmask8)(m)); })
586	100
587		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
588		_mm_mask_cmpneq_epu16_mask(__mmask8 __u, __m128i __a, __m128i __b) {
589		return (__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)__a, (__v8hi)__b, 4,
590		__u);
591		}
	101	#define _mm256_cmp_epi16_mask(a, b, p) __extension__ ({ \
	102	(__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)(__m256i)(a), \
	103	(__v16hi)(__m256i)(b), (int)(p), \
	104	(__mmask16)-1); })
592	105
593		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
594		_mm256_cmpneq_epi16_mask(__m256i __a, __m256i __b) {
595		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 4,
596		(__mmask16)-1);
597		}
	106	#define _mm256_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
	107	(__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)(__m256i)(a), \
	108	(__v16hi)(__m256i)(b), (int)(p), \
	109	(__mmask16)(m)); })
598	110
599		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
600		_mm256_mask_cmpneq_epi16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
601		return (__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)__a, (__v16hi)__b, 4,
602		__u);
603		}
	111	#define _mm256_cmp_epu16_mask(a, b, p) __extension__ ({ \
	112	(__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)(__m256i)(a), \
	113	(__v16hi)(__m256i)(b), (int)(p), \
	114	(__mmask16)-1); })
604	115
605		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
606		_mm256_cmpneq_epu16_mask(__m256i __a, __m256i __b) {
607		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 4,
608		(__mmask16)-1);
609		}
	116	#define _mm256_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
	117	(__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)(__m256i)(a), \
	118	(__v16hi)(__m256i)(b), (int)(p), \
	119	(__mmask16)(m)); })
610	120
611		static __inline__ __mmask16 __DEFAULT_FN_ATTRS
612		_mm256_mask_cmpneq_epu16_mask(__mmask16 __u, __m256i __a, __m256i __b) {
613		return (__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)__a, (__v16hi)__b, 4,
614		__u);
615		}
	121	#define _mm_cmpeq_epi8_mask(A, B) \
	122	_mm_cmp_epi8_mask((A), (B), _MM_CMPINT_EQ)
	123	#define _mm_mask_cmpeq_epi8_mask(k, A, B) \
	124	_mm_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_EQ)
	125	#define _mm_cmpge_epi8_mask(A, B) \
	126	_mm_cmp_epi8_mask((A), (B), _MM_CMPINT_GE)
	127	#define _mm_mask_cmpge_epi8_mask(k, A, B) \
	128	_mm_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_GE)
	129	#define _mm_cmpgt_epi8_mask(A, B) \
	130	_mm_cmp_epi8_mask((A), (B), _MM_CMPINT_GT)
	131	#define _mm_mask_cmpgt_epi8_mask(k, A, B) \
	132	_mm_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_GT)
	133	#define _mm_cmple_epi8_mask(A, B) \
	134	_mm_cmp_epi8_mask((A), (B), _MM_CMPINT_LE)
	135	#define _mm_mask_cmple_epi8_mask(k, A, B) \
	136	_mm_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_LE)
	137	#define _mm_cmplt_epi8_mask(A, B) \
	138	_mm_cmp_epi8_mask((A), (B), _MM_CMPINT_LT)
	139	#define _mm_mask_cmplt_epi8_mask(k, A, B) \
	140	_mm_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_LT)
	141	#define _mm_cmpneq_epi8_mask(A, B) \
	142	_mm_cmp_epi8_mask((A), (B), _MM_CMPINT_NE)
	143	#define _mm_mask_cmpneq_epi8_mask(k, A, B) \
	144	_mm_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_NE)
	145
	146	#define _mm256_cmpeq_epi8_mask(A, B) \
	147	_mm256_cmp_epi8_mask((A), (B), _MM_CMPINT_EQ)
	148	#define _mm256_mask_cmpeq_epi8_mask(k, A, B) \
	149	_mm256_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_EQ)
	150	#define _mm256_cmpge_epi8_mask(A, B) \
	151	_mm256_cmp_epi8_mask((A), (B), _MM_CMPINT_GE)
	152	#define _mm256_mask_cmpge_epi8_mask(k, A, B) \
	153	_mm256_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_GE)
	154	#define _mm256_cmpgt_epi8_mask(A, B) \
	155	_mm256_cmp_epi8_mask((A), (B), _MM_CMPINT_GT)
	156	#define _mm256_mask_cmpgt_epi8_mask(k, A, B) \
	157	_mm256_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_GT)
	158	#define _mm256_cmple_epi8_mask(A, B) \
	159	_mm256_cmp_epi8_mask((A), (B), _MM_CMPINT_LE)
	160	#define _mm256_mask_cmple_epi8_mask(k, A, B) \
	161	_mm256_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_LE)
	162	#define _mm256_cmplt_epi8_mask(A, B) \
	163	_mm256_cmp_epi8_mask((A), (B), _MM_CMPINT_LT)
	164	#define _mm256_mask_cmplt_epi8_mask(k, A, B) \
	165	_mm256_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_LT)
	166	#define _mm256_cmpneq_epi8_mask(A, B) \
	167	_mm256_cmp_epi8_mask((A), (B), _MM_CMPINT_NE)
	168	#define _mm256_mask_cmpneq_epi8_mask(k, A, B) \
	169	_mm256_mask_cmp_epi8_mask((k), (A), (B), _MM_CMPINT_NE)
	170
	171	#define _mm_cmpeq_epu8_mask(A, B) \
	172	_mm_cmp_epu8_mask((A), (B), _MM_CMPINT_EQ)
	173	#define _mm_mask_cmpeq_epu8_mask(k, A, B) \
	174	_mm_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_EQ)
	175	#define _mm_cmpge_epu8_mask(A, B) \
	176	_mm_cmp_epu8_mask((A), (B), _MM_CMPINT_GE)
	177	#define _mm_mask_cmpge_epu8_mask(k, A, B) \
	178	_mm_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_GE)
	179	#define _mm_cmpgt_epu8_mask(A, B) \
	180	_mm_cmp_epu8_mask((A), (B), _MM_CMPINT_GT)
	181	#define _mm_mask_cmpgt_epu8_mask(k, A, B) \
	182	_mm_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_GT)
	183	#define _mm_cmple_epu8_mask(A, B) \
	184	_mm_cmp_epu8_mask((A), (B), _MM_CMPINT_LE)
	185	#define _mm_mask_cmple_epu8_mask(k, A, B) \
	186	_mm_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_LE)
	187	#define _mm_cmplt_epu8_mask(A, B) \
	188	_mm_cmp_epu8_mask((A), (B), _MM_CMPINT_LT)
	189	#define _mm_mask_cmplt_epu8_mask(k, A, B) \
	190	_mm_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_LT)
	191	#define _mm_cmpneq_epu8_mask(A, B) \
	192	_mm_cmp_epu8_mask((A), (B), _MM_CMPINT_NE)
	193	#define _mm_mask_cmpneq_epu8_mask(k, A, B) \
	194	_mm_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_NE)
	195
	196	#define _mm256_cmpeq_epu8_mask(A, B) \
	197	_mm256_cmp_epu8_mask((A), (B), _MM_CMPINT_EQ)
	198	#define _mm256_mask_cmpeq_epu8_mask(k, A, B) \
	199	_mm256_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_EQ)
	200	#define _mm256_cmpge_epu8_mask(A, B) \
	201	_mm256_cmp_epu8_mask((A), (B), _MM_CMPINT_GE)
	202	#define _mm256_mask_cmpge_epu8_mask(k, A, B) \
	203	_mm256_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_GE)
	204	#define _mm256_cmpgt_epu8_mask(A, B) \
	205	_mm256_cmp_epu8_mask((A), (B), _MM_CMPINT_GT)
	206	#define _mm256_mask_cmpgt_epu8_mask(k, A, B) \
	207	_mm256_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_GT)
	208	#define _mm256_cmple_epu8_mask(A, B) \
	209	_mm256_cmp_epu8_mask((A), (B), _MM_CMPINT_LE)
	210	#define _mm256_mask_cmple_epu8_mask(k, A, B) \
	211	_mm256_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_LE)
	212	#define _mm256_cmplt_epu8_mask(A, B) \
	213	_mm256_cmp_epu8_mask((A), (B), _MM_CMPINT_LT)
	214	#define _mm256_mask_cmplt_epu8_mask(k, A, B) \
	215	_mm256_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_LT)
	216	#define _mm256_cmpneq_epu8_mask(A, B) \
	217	_mm256_cmp_epu8_mask((A), (B), _MM_CMPINT_NE)
	218	#define _mm256_mask_cmpneq_epu8_mask(k, A, B) \
	219	_mm256_mask_cmp_epu8_mask((k), (A), (B), _MM_CMPINT_NE)
	220
	221	#define _mm_cmpeq_epi16_mask(A, B) \
	222	_mm_cmp_epi16_mask((A), (B), _MM_CMPINT_EQ)
	223	#define _mm_mask_cmpeq_epi16_mask(k, A, B) \
	224	_mm_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_EQ)
	225	#define _mm_cmpge_epi16_mask(A, B) \
	226	_mm_cmp_epi16_mask((A), (B), _MM_CMPINT_GE)
	227	#define _mm_mask_cmpge_epi16_mask(k, A, B) \
	228	_mm_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_GE)
	229	#define _mm_cmpgt_epi16_mask(A, B) \
	230	_mm_cmp_epi16_mask((A), (B), _MM_CMPINT_GT)
	231	#define _mm_mask_cmpgt_epi16_mask(k, A, B) \
	232	_mm_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_GT)
	233	#define _mm_cmple_epi16_mask(A, B) \
	234	_mm_cmp_epi16_mask((A), (B), _MM_CMPINT_LE)
	235	#define _mm_mask_cmple_epi16_mask(k, A, B) \
	236	_mm_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_LE)
	237	#define _mm_cmplt_epi16_mask(A, B) \
	238	_mm_cmp_epi16_mask((A), (B), _MM_CMPINT_LT)
	239	#define _mm_mask_cmplt_epi16_mask(k, A, B) \
	240	_mm_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_LT)
	241	#define _mm_cmpneq_epi16_mask(A, B) \
	242	_mm_cmp_epi16_mask((A), (B), _MM_CMPINT_NE)
	243	#define _mm_mask_cmpneq_epi16_mask(k, A, B) \
	244	_mm_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_NE)
	245
	246	#define _mm256_cmpeq_epi16_mask(A, B) \
	247	_mm256_cmp_epi16_mask((A), (B), _MM_CMPINT_EQ)
	248	#define _mm256_mask_cmpeq_epi16_mask(k, A, B) \
	249	_mm256_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_EQ)
	250	#define _mm256_cmpge_epi16_mask(A, B) \
	251	_mm256_cmp_epi16_mask((A), (B), _MM_CMPINT_GE)
	252	#define _mm256_mask_cmpge_epi16_mask(k, A, B) \
	253	_mm256_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_GE)
	254	#define _mm256_cmpgt_epi16_mask(A, B) \
	255	_mm256_cmp_epi16_mask((A), (B), _MM_CMPINT_GT)
	256	#define _mm256_mask_cmpgt_epi16_mask(k, A, B) \
	257	_mm256_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_GT)
	258	#define _mm256_cmple_epi16_mask(A, B) \
	259	_mm256_cmp_epi16_mask((A), (B), _MM_CMPINT_LE)
	260	#define _mm256_mask_cmple_epi16_mask(k, A, B) \
	261	_mm256_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_LE)
	262	#define _mm256_cmplt_epi16_mask(A, B) \
	263	_mm256_cmp_epi16_mask((A), (B), _MM_CMPINT_LT)
	264	#define _mm256_mask_cmplt_epi16_mask(k, A, B) \
	265	_mm256_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_LT)
	266	#define _mm256_cmpneq_epi16_mask(A, B) \
	267	_mm256_cmp_epi16_mask((A), (B), _MM_CMPINT_NE)
	268	#define _mm256_mask_cmpneq_epi16_mask(k, A, B) \
	269	_mm256_mask_cmp_epi16_mask((k), (A), (B), _MM_CMPINT_NE)
	270
	271	#define _mm_cmpeq_epu16_mask(A, B) \
	272	_mm_cmp_epu16_mask((A), (B), _MM_CMPINT_EQ)
	273	#define _mm_mask_cmpeq_epu16_mask(k, A, B) \
	274	_mm_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_EQ)
	275	#define _mm_cmpge_epu16_mask(A, B) \
	276	_mm_cmp_epu16_mask((A), (B), _MM_CMPINT_GE)
	277	#define _mm_mask_cmpge_epu16_mask(k, A, B) \
	278	_mm_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_GE)
	279	#define _mm_cmpgt_epu16_mask(A, B) \
	280	_mm_cmp_epu16_mask((A), (B), _MM_CMPINT_GT)
	281	#define _mm_mask_cmpgt_epu16_mask(k, A, B) \
	282	_mm_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_GT)
	283	#define _mm_cmple_epu16_mask(A, B) \
	284	_mm_cmp_epu16_mask((A), (B), _MM_CMPINT_LE)
	285	#define _mm_mask_cmple_epu16_mask(k, A, B) \
	286	_mm_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_LE)
	287	#define _mm_cmplt_epu16_mask(A, B) \
	288	_mm_cmp_epu16_mask((A), (B), _MM_CMPINT_LT)
	289	#define _mm_mask_cmplt_epu16_mask(k, A, B) \
	290	_mm_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_LT)
	291	#define _mm_cmpneq_epu16_mask(A, B) \
	292	_mm_cmp_epu16_mask((A), (B), _MM_CMPINT_NE)
	293	#define _mm_mask_cmpneq_epu16_mask(k, A, B) \
	294	_mm_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_NE)
	295
	296	#define _mm256_cmpeq_epu16_mask(A, B) \
	297	_mm256_cmp_epu16_mask((A), (B), _MM_CMPINT_EQ)
	298	#define _mm256_mask_cmpeq_epu16_mask(k, A, B) \
	299	_mm256_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_EQ)
	300	#define _mm256_cmpge_epu16_mask(A, B) \
	301	_mm256_cmp_epu16_mask((A), (B), _MM_CMPINT_GE)
	302	#define _mm256_mask_cmpge_epu16_mask(k, A, B) \
	303	_mm256_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_GE)
	304	#define _mm256_cmpgt_epu16_mask(A, B) \
	305	_mm256_cmp_epu16_mask((A), (B), _MM_CMPINT_GT)
	306	#define _mm256_mask_cmpgt_epu16_mask(k, A, B) \
	307	_mm256_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_GT)
	308	#define _mm256_cmple_epu16_mask(A, B) \
	309	_mm256_cmp_epu16_mask((A), (B), _MM_CMPINT_LE)
	310	#define _mm256_mask_cmple_epu16_mask(k, A, B) \
	311	_mm256_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_LE)
	312	#define _mm256_cmplt_epu16_mask(A, B) \
	313	_mm256_cmp_epu16_mask((A), (B), _MM_CMPINT_LT)
	314	#define _mm256_mask_cmplt_epu16_mask(k, A, B) \
	315	_mm256_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_LT)
	316	#define _mm256_cmpneq_epu16_mask(A, B) \
	317	_mm256_cmp_epu16_mask((A), (B), _MM_CMPINT_NE)
	318	#define _mm256_mask_cmpneq_epu16_mask(k, A, B) \
	319	_mm256_mask_cmp_epu16_mask((k), (A), (B), _MM_CMPINT_NE)
616	320
617	321	static __inline__ __m256i __DEFAULT_FN_ATTRS
618	322	_mm256_mask_add_epi8(__m256i __W, __mmask32 __U, __m256i __A, __m256i __B){
...	...	@@ -2146,86 +1850,6 @@ _mm256_maskz_cvtepu8_epi16 (__mmask16 __U, __m128i __A)
2146	1850	}
2147	1851
2148	1852
2149		#define _mm_cmp_epi8_mask(a, b, p) __extension__ ({ \
2150		(__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)(__m128i)(a), \
2151		(__v16qi)(__m128i)(b), (int)(p), \
2152		(__mmask16)-1); })
2153
2154		#define _mm_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
2155		(__mmask16)__builtin_ia32_cmpb128_mask((__v16qi)(__m128i)(a), \
2156		(__v16qi)(__m128i)(b), (int)(p), \
2157		(__mmask16)(m)); })
2158
2159		#define _mm_cmp_epu8_mask(a, b, p) __extension__ ({ \
2160		(__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)(__m128i)(a), \
2161		(__v16qi)(__m128i)(b), (int)(p), \
2162		(__mmask16)-1); })
2163
2164		#define _mm_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
2165		(__mmask16)__builtin_ia32_ucmpb128_mask((__v16qi)(__m128i)(a), \
2166		(__v16qi)(__m128i)(b), (int)(p), \
2167		(__mmask16)(m)); })
2168
2169		#define _mm256_cmp_epi8_mask(a, b, p) __extension__ ({ \
2170		(__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)(__m256i)(a), \
2171		(__v32qi)(__m256i)(b), (int)(p), \
2172		(__mmask32)-1); })
2173
2174		#define _mm256_mask_cmp_epi8_mask(m, a, b, p) __extension__ ({ \
2175		(__mmask32)__builtin_ia32_cmpb256_mask((__v32qi)(__m256i)(a), \
2176		(__v32qi)(__m256i)(b), (int)(p), \
2177		(__mmask32)(m)); })
2178
2179		#define _mm256_cmp_epu8_mask(a, b, p) __extension__ ({ \
2180		(__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)(__m256i)(a), \
2181		(__v32qi)(__m256i)(b), (int)(p), \
2182		(__mmask32)-1); })
2183
2184		#define _mm256_mask_cmp_epu8_mask(m, a, b, p) __extension__ ({ \
2185		(__mmask32)__builtin_ia32_ucmpb256_mask((__v32qi)(__m256i)(a), \
2186		(__v32qi)(__m256i)(b), (int)(p), \
2187		(__mmask32)(m)); })
2188
2189		#define _mm_cmp_epi16_mask(a, b, p) __extension__ ({ \
2190		(__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)(__m128i)(a), \
2191		(__v8hi)(__m128i)(b), (int)(p), \
2192		(__mmask8)-1); })
2193
2194		#define _mm_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
2195		(__mmask8)__builtin_ia32_cmpw128_mask((__v8hi)(__m128i)(a), \
2196		(__v8hi)(__m128i)(b), (int)(p), \
2197		(__mmask8)(m)); })
2198
2199		#define _mm_cmp_epu16_mask(a, b, p) __extension__ ({ \
2200		(__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)(__m128i)(a), \
2201		(__v8hi)(__m128i)(b), (int)(p), \
2202		(__mmask8)-1); })
2203
2204		#define _mm_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
2205		(__mmask8)__builtin_ia32_ucmpw128_mask((__v8hi)(__m128i)(a), \
2206		(__v8hi)(__m128i)(b), (int)(p), \
2207		(__mmask8)(m)); })
2208
2209		#define _mm256_cmp_epi16_mask(a, b, p) __extension__ ({ \
2210		(__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)(__m256i)(a), \
2211		(__v16hi)(__m256i)(b), (int)(p), \
2212		(__mmask16)-1); })
2213
2214		#define _mm256_mask_cmp_epi16_mask(m, a, b, p) __extension__ ({ \
2215		(__mmask16)__builtin_ia32_cmpw256_mask((__v16hi)(__m256i)(a), \
2216		(__v16hi)(__m256i)(b), (int)(p), \
2217		(__mmask16)(m)); })
2218
2219		#define _mm256_cmp_epu16_mask(a, b, p) __extension__ ({ \
2220		(__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)(__m256i)(a), \
2221		(__v16hi)(__m256i)(b), (int)(p), \
2222		(__mmask16)-1); })
2223
2224		#define _mm256_mask_cmp_epu16_mask(m, a, b, p) __extension__ ({ \
2225		(__mmask16)__builtin_ia32_ucmpw256_mask((__v16hi)(__m256i)(a), \
2226		(__v16hi)(__m256i)(b), (int)(p), \
2227		(__mmask16)(m)); })
2228
2229	1853	#define _mm_mask_shufflehi_epi16(W, U, A, imm) __extension__ ({ \
2230	1854	(__m128i)__builtin_ia32_selectw_128((__mmask8)(U), \
2231	1855	(__v8hi)_mm_shufflehi_epi16((A), (imm)), \
...	...	@@ -2791,121 +2415,108 @@ _mm256_mask_storeu_epi8 (void *__P, __mmask32 __U, __m256i __A)
2791	2415	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2792	2416	_mm_test_epi8_mask (__m128i __A, __m128i __B)
2793	2417	{
2794		return (__mmask16) __builtin_ia32_ptestmb128 ((__v16qi) __A,
2795		(__v16qi) __B,
2796		(__mmask16) -1);
	2418	return _mm_cmpneq_epi8_mask (_mm_and_si128(__A, __B), _mm_setzero_hi());
2797	2419	}
2798	2420
2799	2421	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2800	2422	_mm_mask_test_epi8_mask (__mmask16 __U, __m128i __A, __m128i __B)
2801	2423	{
2802		return (__mmask16) __builtin_ia32_ptestmb128 ((__v16qi) __A,
2803		(__v16qi) __B, __U);
	2424	return _mm_mask_cmpneq_epi8_mask (__U, _mm_and_si128 (__A, __B),
	2425	_mm_setzero_hi());
2804	2426	}
2805	2427
2806	2428	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2807	2429	_mm256_test_epi8_mask (__m256i __A, __m256i __B)
2808	2430	{
2809		return (__mmask32) __builtin_ia32_ptestmb256 ((__v32qi) __A,
2810		(__v32qi) __B,
2811		(__mmask32) -1);
	2431	return _mm256_cmpneq_epi8_mask (_mm256_and_si256(__A, __B),
	2432	_mm256_setzero_si256());
2812	2433	}
2813	2434
2814	2435	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2815	2436	_mm256_mask_test_epi8_mask (__mmask32 __U, __m256i __A, __m256i __B)
2816	2437	{
2817		return (__mmask32) __builtin_ia32_ptestmb256 ((__v32qi) __A,
2818		(__v32qi) __B, __U);
	2438	return _mm256_mask_cmpneq_epi8_mask (__U, _mm256_and_si256(__A, __B),
	2439	_mm256_setzero_si256());
2819	2440	}
2820	2441
2821	2442	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
2822	2443	_mm_test_epi16_mask (__m128i __A, __m128i __B)
2823	2444	{
2824		return (__mmask8) __builtin_ia32_ptestmw128 ((__v8hi) __A,
2825		(__v8hi) __B,
2826		(__mmask8) -1);
	2445	return _mm_cmpneq_epi16_mask (_mm_and_si128 (__A, __B), _mm_setzero_hi());
2827	2446	}
2828	2447
2829	2448	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
2830	2449	_mm_mask_test_epi16_mask (__mmask8 __U, __m128i __A, __m128i __B)
2831	2450	{
2832		return (__mmask8) __builtin_ia32_ptestmw128 ((__v8hi) __A,
2833		(__v8hi) __B, __U);
	2451	return _mm_mask_cmpneq_epi16_mask (__U, _mm_and_si128 (__A, __B),
	2452	_mm_setzero_hi());
2834	2453	}
2835	2454
2836	2455	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2837	2456	_mm256_test_epi16_mask (__m256i __A, __m256i __B)
2838	2457	{
2839		return (__mmask16) __builtin_ia32_ptestmw256 ((__v16hi) __A,
2840		(__v16hi) __B,
2841		(__mmask16) -1);
	2458	return _mm256_cmpneq_epi16_mask (_mm256_and_si256 (__A, __B),
	2459	_mm256_setzero_si256 ());
2842	2460	}
2843	2461
2844	2462	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2845	2463	_mm256_mask_test_epi16_mask (__mmask16 __U, __m256i __A, __m256i __B)
2846	2464	{
2847		return (__mmask16) __builtin_ia32_ptestmw256 ((__v16hi) __A,
2848		(__v16hi) __B, __U);
	2465	return _mm256_mask_cmpneq_epi16_mask (__U, _mm256_and_si256(__A, __B),
	2466	_mm256_setzero_si256());
2849	2467	}
2850	2468
2851	2469	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2852	2470	_mm_testn_epi8_mask (__m128i __A, __m128i __B)
2853	2471	{
2854		return (__mmask16) __builtin_ia32_ptestnmb128 ((__v16qi) __A,
2855		(__v16qi) __B,
2856		(__mmask16) -1);
	2472	return _mm_cmpeq_epi8_mask (_mm_and_si128 (__A, __B), _mm_setzero_hi());
2857	2473	}
2858	2474
2859	2475	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2860	2476	_mm_mask_testn_epi8_mask (__mmask16 __U, __m128i __A, __m128i __B)
2861	2477	{
2862		return (__mmask16) __builtin_ia32_ptestnmb128 ((__v16qi) __A,
2863		(__v16qi) __B, __U);
	2478	return _mm_mask_cmpeq_epi8_mask (__U, _mm_and_si128 (__A, __B),
	2479	_mm_setzero_hi());
2864	2480	}
2865	2481
2866	2482	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2867	2483	_mm256_testn_epi8_mask (__m256i __A, __m256i __B)
2868	2484	{
2869		return (__mmask32) __builtin_ia32_ptestnmb256 ((__v32qi) __A,
2870		(__v32qi) __B,
2871		(__mmask32) -1);
	2485	return _mm256_cmpeq_epi8_mask (_mm256_and_si256 (__A, __B),
	2486	_mm256_setzero_si256());
2872	2487	}
2873	2488
2874	2489	static __inline__ __mmask32 __DEFAULT_FN_ATTRS
2875	2490	_mm256_mask_testn_epi8_mask (__mmask32 __U, __m256i __A, __m256i __B)
2876	2491	{
2877		return (__mmask32) __builtin_ia32_ptestnmb256 ((__v32qi) __A,
2878		(__v32qi) __B, __U);
	2492	return _mm256_mask_cmpeq_epi8_mask (__U, _mm256_and_si256 (__A, __B),
	2493	_mm256_setzero_si256());
2879	2494	}
2880	2495
2881	2496	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
2882	2497	_mm_testn_epi16_mask (__m128i __A, __m128i __B)
2883	2498	{
2884		return (__mmask8) __builtin_ia32_ptestnmw128 ((__v8hi) __A,
2885		(__v8hi) __B,
2886		(__mmask8) -1);
	2499	return _mm_cmpeq_epi16_mask (_mm_and_si128 (__A, __B), _mm_setzero_hi());
2887	2500	}
2888	2501
2889	2502	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
2890	2503	_mm_mask_testn_epi16_mask (__mmask8 __U, __m128i __A, __m128i __B)
2891	2504	{
2892		return (__mmask8) __builtin_ia32_ptestnmw128 ((__v8hi) __A,
2893		(__v8hi) __B, __U);
	2505	return _mm_mask_cmpeq_epi16_mask (__U, _mm_and_si128(__A, __B), _mm_setzero_hi());
2894	2506	}
2895	2507
2896	2508	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2897	2509	_mm256_testn_epi16_mask (__m256i __A, __m256i __B)
2898	2510	{
2899		return (__mmask16) __builtin_ia32_ptestnmw256 ((__v16hi) __A,
2900		(__v16hi) __B,
2901		(__mmask16) -1);
	2511	return _mm256_cmpeq_epi16_mask (_mm256_and_si256(__A, __B),
	2512	_mm256_setzero_si256());
2902	2513	}
2903	2514
2904	2515	static __inline__ __mmask16 __DEFAULT_FN_ATTRS
2905	2516	_mm256_mask_testn_epi16_mask (__mmask16 __U, __m256i __A, __m256i __B)
2906	2517	{
2907		return (__mmask16) __builtin_ia32_ptestnmw256 ((__v16hi) __A,
2908		(__v16hi) __B, __U);
	2518	return _mm256_mask_cmpeq_epi16_mask (__U, _mm256_and_si256 (__A, __B),
	2519	_mm256_setzero_si256());
2909	2520	}
2910	2521
2911	2522	static __inline__ __mmask16 __DEFAULT_FN_ATTRS

c_headers/avx512vlcdintrin.h+5-5

...	...	@@ -33,26 +33,26 @@
33	33
34	34	static __inline__ __m128i __DEFAULT_FN_ATTRS
35	35	_mm_broadcastmb_epi64 (__mmask8 __A)
36		{
37		return (__m128i) __builtin_ia32_broadcastmb128 (__A);
	36	{
	37	return (__m128i) _mm_set1_epi64x((long long) __A);
38	38	}
39	39
40	40	static __inline__ __m256i __DEFAULT_FN_ATTRS
41	41	_mm256_broadcastmb_epi64 (__mmask8 __A)
42	42	{
43		return (__m256i) __builtin_ia32_broadcastmb256 (__A);
	43	return (__m256i) _mm256_set1_epi64x((long long)__A);
44	44	}
45	45
46	46	static __inline__ __m128i __DEFAULT_FN_ATTRS
47	47	_mm_broadcastmw_epi32 (__mmask16 __A)
48	48	{
49		return (__m128i) __builtin_ia32_broadcastmw128 (__A);
	49	return (__m128i) _mm_set1_epi32((int)__A);
50	50	}
51	51
52	52	static __inline__ __m256i __DEFAULT_FN_ATTRS
53	53	_mm256_broadcastmw_epi32 (__mmask16 __A)
54	54	{
55		return (__m256i) __builtin_ia32_broadcastmw256 (__A);
	55	return (__m256i) _mm256_set1_epi32((int)__A);
56	56	}
57	57
58	58

c_headers/avx512vlintrin.h+280-675

...	...	@@ -38,582 +38,205 @@ _mm_setzero_di(void) {
38	38
39	39	/* Integer compare */
40	40
41		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
42		_mm_cmpeq_epi32_mask(__m128i __a, __m128i __b) {
43		return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
44		(__mmask8)-1);
45		}
46
47		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
48		_mm_mask_cmpeq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
49		return (__mmask8)__builtin_ia32_pcmpeqd128_mask((__v4si)__a, (__v4si)__b,
50		__u);
51		}
52
53		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
54		_mm_cmpeq_epu32_mask(__m128i __a, __m128i __b) {
55		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 0,
56		(__mmask8)-1);
57		}
58
59		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
60		_mm_mask_cmpeq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
61		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 0,
62		__u);
63		}
64
65		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
66		_mm256_cmpeq_epi32_mask(__m256i __a, __m256i __b) {
67		return (__mmask8)__builtin_ia32_pcmpeqd256_mask((__v8si)__a, (__v8si)__b,
68		(__mmask8)-1);
69		}
70
71		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
72		_mm256_mask_cmpeq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
73		return (__mmask8)__builtin_ia32_pcmpeqd256_mask((__v8si)__a, (__v8si)__b,
74		__u);
75		}
76
77		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
78		_mm256_cmpeq_epu32_mask(__m256i __a, __m256i __b) {
79		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 0,
80		(__mmask8)-1);
81		}
82
83		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
84		_mm256_mask_cmpeq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
85		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 0,
86		__u);
87		}
88
89		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
90		_mm_cmpeq_epi64_mask(__m128i __a, __m128i __b) {
91		return (__mmask8)__builtin_ia32_pcmpeqq128_mask((__v2di)__a, (__v2di)__b,
92		(__mmask8)-1);
93		}
94
95		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
96		_mm_mask_cmpeq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
97		return (__mmask8)__builtin_ia32_pcmpeqq128_mask((__v2di)__a, (__v2di)__b,
98		__u);
99		}
100
101		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
102		_mm_cmpeq_epu64_mask(__m128i __a, __m128i __b) {
103		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 0,
104		(__mmask8)-1);
105		}
106
107		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
108		_mm_mask_cmpeq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
109		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 0,
110		__u);
111		}
112
113		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
114		_mm256_cmpeq_epi64_mask(__m256i __a, __m256i __b) {
115		return (__mmask8)__builtin_ia32_pcmpeqq256_mask((__v4di)__a, (__v4di)__b,
116		(__mmask8)-1);
117		}
118
119		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
120		_mm256_mask_cmpeq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
121		return (__mmask8)__builtin_ia32_pcmpeqq256_mask((__v4di)__a, (__v4di)__b,
122		__u);
123		}
124
125		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
126		_mm256_cmpeq_epu64_mask(__m256i __a, __m256i __b) {
127		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 0,
128		(__mmask8)-1);
129		}
130
131		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
132		_mm256_mask_cmpeq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
133		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 0,
134		__u);
135		}
136
137
138		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
139		_mm_cmpge_epi32_mask(__m128i __a, __m128i __b) {
140		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 5,
141		(__mmask8)-1);
142		}
143
144		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
145		_mm_mask_cmpge_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
146		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 5,
147		__u);
148		}
149
150		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
151		_mm_cmpge_epu32_mask(__m128i __a, __m128i __b) {
152		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 5,
153		(__mmask8)-1);
154		}
155
156		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
157		_mm_mask_cmpge_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
158		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 5,
159		__u);
160		}
161
162		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
163		_mm256_cmpge_epi32_mask(__m256i __a, __m256i __b) {
164		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 5,
165		(__mmask8)-1);
166		}
167
168		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
169		_mm256_mask_cmpge_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
170		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 5,
171		__u);
172		}
173
174		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
175		_mm256_cmpge_epu32_mask(__m256i __a, __m256i __b) {
176		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 5,
177		(__mmask8)-1);
178		}
179
180		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
181		_mm256_mask_cmpge_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
182		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 5,
183		__u);
184		}
185
186		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
187		_mm_cmpge_epi64_mask(__m128i __a, __m128i __b) {
188		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 5,
189		(__mmask8)-1);
190		}
191
192		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
193		_mm_mask_cmpge_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
194		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 5,
195		__u);
196		}
197
198		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
199		_mm_cmpge_epu64_mask(__m128i __a, __m128i __b) {
200		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 5,
201		(__mmask8)-1);
202		}
203
204		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
205		_mm_mask_cmpge_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
206		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 5,
207		__u);
208		}
209
210		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
211		_mm256_cmpge_epi64_mask(__m256i __a, __m256i __b) {
212		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 5,
213		(__mmask8)-1);
214		}
215
216		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
217		_mm256_mask_cmpge_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
218		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 5,
219		__u);
220		}
221
222		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
223		_mm256_cmpge_epu64_mask(__m256i __a, __m256i __b) {
224		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 5,
225		(__mmask8)-1);
226		}
227
228		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
229		_mm256_mask_cmpge_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
230		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 5,
231		__u);
232		}
233
234		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
235		_mm_cmpgt_epi32_mask(__m128i __a, __m128i __b) {
236		return (__mmask8)__builtin_ia32_pcmpgtd128_mask((__v4si)__a, (__v4si)__b,
237		(__mmask8)-1);
238		}
239
240		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
241		_mm_mask_cmpgt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
242		return (__mmask8)__builtin_ia32_pcmpgtd128_mask((__v4si)__a, (__v4si)__b,
243		__u);
244		}
245
246		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
247		_mm_cmpgt_epu32_mask(__m128i __a, __m128i __b) {
248		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 6,
249		(__mmask8)-1);
250		}
251
252		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
253		_mm_mask_cmpgt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
254		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 6,
255		__u);
256		}
257
258		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
259		_mm256_cmpgt_epi32_mask(__m256i __a, __m256i __b) {
260		return (__mmask8)__builtin_ia32_pcmpgtd256_mask((__v8si)__a, (__v8si)__b,
261		(__mmask8)-1);
262		}
263
264		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
265		_mm256_mask_cmpgt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
266		return (__mmask8)__builtin_ia32_pcmpgtd256_mask((__v8si)__a, (__v8si)__b,
267		__u);
268		}
269
270		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
271		_mm256_cmpgt_epu32_mask(__m256i __a, __m256i __b) {
272		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 6,
273		(__mmask8)-1);
274		}
275
276		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
277		_mm256_mask_cmpgt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
278		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 6,
279		__u);
280		}
281
282		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
283		_mm_cmpgt_epi64_mask(__m128i __a, __m128i __b) {
284		return (__mmask8)__builtin_ia32_pcmpgtq128_mask((__v2di)__a, (__v2di)__b,
285		(__mmask8)-1);
286		}
287
288		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
289		_mm_mask_cmpgt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
290		return (__mmask8)__builtin_ia32_pcmpgtq128_mask((__v2di)__a, (__v2di)__b,
291		__u);
292		}
293
294		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
295		_mm_cmpgt_epu64_mask(__m128i __a, __m128i __b) {
296		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 6,
297		(__mmask8)-1);
298		}
299
300		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
301		_mm_mask_cmpgt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
302		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 6,
303		__u);
304		}
305
306		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
307		_mm256_cmpgt_epi64_mask(__m256i __a, __m256i __b) {
308		return (__mmask8)__builtin_ia32_pcmpgtq256_mask((__v4di)__a, (__v4di)__b,
309		(__mmask8)-1);
310		}
311
312		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
313		_mm256_mask_cmpgt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
314		return (__mmask8)__builtin_ia32_pcmpgtq256_mask((__v4di)__a, (__v4di)__b,
315		__u);
316		}
317
318		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
319		_mm256_cmpgt_epu64_mask(__m256i __a, __m256i __b) {
320		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 6,
321		(__mmask8)-1);
322		}
323
324		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
325		_mm256_mask_cmpgt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
326		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 6,
327		__u);
328		}
329
330		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
331		_mm_cmple_epi32_mask(__m128i __a, __m128i __b) {
332		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 2,
333		(__mmask8)-1);
334		}
335
336		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
337		_mm_mask_cmple_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
338		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 2,
339		__u);
340		}
341
342		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
343		_mm_cmple_epu32_mask(__m128i __a, __m128i __b) {
344		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 2,
345		(__mmask8)-1);
346		}
347
348		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
349		_mm_mask_cmple_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
350		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 2,
351		__u);
352		}
353
354		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
355		_mm256_cmple_epi32_mask(__m256i __a, __m256i __b) {
356		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 2,
357		(__mmask8)-1);
358		}
359
360		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
361		_mm256_mask_cmple_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
362		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 2,
363		__u);
364		}
365
366		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
367		_mm256_cmple_epu32_mask(__m256i __a, __m256i __b) {
368		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 2,
369		(__mmask8)-1);
370		}
371
372		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
373		_mm256_mask_cmple_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
374		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 2,
375		__u);
376		}
377
378		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
379		_mm_cmple_epi64_mask(__m128i __a, __m128i __b) {
380		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 2,
381		(__mmask8)-1);
382		}
383
384		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
385		_mm_mask_cmple_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
386		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 2,
387		__u);
388		}
389
390		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
391		_mm_cmple_epu64_mask(__m128i __a, __m128i __b) {
392		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 2,
393		(__mmask8)-1);
394		}
395
396		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
397		_mm_mask_cmple_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
398		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 2,
399		__u);
400		}
401
402		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
403		_mm256_cmple_epi64_mask(__m256i __a, __m256i __b) {
404		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 2,
405		(__mmask8)-1);
406		}
407
408		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
409		_mm256_mask_cmple_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
410		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 2,
411		__u);
412		}
413
414		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
415		_mm256_cmple_epu64_mask(__m256i __a, __m256i __b) {
416		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 2,
417		(__mmask8)-1);
418		}
419
420		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
421		_mm256_mask_cmple_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
422		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 2,
423		__u);
424		}
425
426		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
427		_mm_cmplt_epi32_mask(__m128i __a, __m128i __b) {
428		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 1,
429		(__mmask8)-1);
430		}
431
432		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
433		_mm_mask_cmplt_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
434		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 1,
435		__u);
436		}
437
438		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
439		_mm_cmplt_epu32_mask(__m128i __a, __m128i __b) {
440		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 1,
441		(__mmask8)-1);
442		}
443
444		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
445		_mm_mask_cmplt_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
446		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 1,
447		__u);
448		}
449
450		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
451		_mm256_cmplt_epi32_mask(__m256i __a, __m256i __b) {
452		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 1,
453		(__mmask8)-1);
454		}
455
456		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
457		_mm256_mask_cmplt_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
458		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 1,
459		__u);
460		}
461
462		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
463		_mm256_cmplt_epu32_mask(__m256i __a, __m256i __b) {
464		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 1,
465		(__mmask8)-1);
466		}
467
468		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
469		_mm256_mask_cmplt_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
470		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 1,
471		__u);
472		}
473
474		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
475		_mm_cmplt_epi64_mask(__m128i __a, __m128i __b) {
476		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 1,
477		(__mmask8)-1);
478		}
479
480		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
481		_mm_mask_cmplt_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
482		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 1,
483		__u);
484		}
485
486		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
487		_mm_cmplt_epu64_mask(__m128i __a, __m128i __b) {
488		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 1,
489		(__mmask8)-1);
490		}
491
492		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
493		_mm_mask_cmplt_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
494		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 1,
495		__u);
496		}
497
498		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
499		_mm256_cmplt_epi64_mask(__m256i __a, __m256i __b) {
500		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 1,
501		(__mmask8)-1);
502		}
503
504		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
505		_mm256_mask_cmplt_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
506		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 1,
507		__u);
508		}
509
510		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
511		_mm256_cmplt_epu64_mask(__m256i __a, __m256i __b) {
512		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 1,
513		(__mmask8)-1);
514		}
515
516		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
517		_mm256_mask_cmplt_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
518		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 1,
519		__u);
520		}
521
522		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
523		_mm_cmpneq_epi32_mask(__m128i __a, __m128i __b) {
524		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 4,
525		(__mmask8)-1);
526		}
527
528		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
529		_mm_mask_cmpneq_epi32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
530		return (__mmask8)__builtin_ia32_cmpd128_mask((__v4si)__a, (__v4si)__b, 4,
531		__u);
532		}
533
534		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
535		_mm_cmpneq_epu32_mask(__m128i __a, __m128i __b) {
536		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 4,
537		(__mmask8)-1);
538		}
539
540		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
541		_mm_mask_cmpneq_epu32_mask(__mmask8 __u, __m128i __a, __m128i __b) {
542		return (__mmask8)__builtin_ia32_ucmpd128_mask((__v4si)__a, (__v4si)__b, 4,
543		__u);
544		}
545
546		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
547		_mm256_cmpneq_epi32_mask(__m256i __a, __m256i __b) {
548		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 4,
549		(__mmask8)-1);
550		}
551
552		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
553		_mm256_mask_cmpneq_epi32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
554		return (__mmask8)__builtin_ia32_cmpd256_mask((__v8si)__a, (__v8si)__b, 4,
555		__u);
556		}
557
558		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
559		_mm256_cmpneq_epu32_mask(__m256i __a, __m256i __b) {
560		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 4,
561		(__mmask8)-1);
562		}
563
564		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
565		_mm256_mask_cmpneq_epu32_mask(__mmask8 __u, __m256i __a, __m256i __b) {
566		return (__mmask8)__builtin_ia32_ucmpd256_mask((__v8si)__a, (__v8si)__b, 4,
567		__u);
568		}
569
570		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
571		_mm_cmpneq_epi64_mask(__m128i __a, __m128i __b) {
572		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 4,
573		(__mmask8)-1);
574		}
575
576		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
577		_mm_mask_cmpneq_epi64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
578		return (__mmask8)__builtin_ia32_cmpq128_mask((__v2di)__a, (__v2di)__b, 4,
579		__u);
580		}
581
582		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
583		_mm_cmpneq_epu64_mask(__m128i __a, __m128i __b) {
584		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 4,
585		(__mmask8)-1);
586		}
587
588		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
589		_mm_mask_cmpneq_epu64_mask(__mmask8 __u, __m128i __a, __m128i __b) {
590		return (__mmask8)__builtin_ia32_ucmpq128_mask((__v2di)__a, (__v2di)__b, 4,
591		__u);
592		}
593
594		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
595		_mm256_cmpneq_epi64_mask(__m256i __a, __m256i __b) {
596		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 4,
597		(__mmask8)-1);
598		}
599
600		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
601		_mm256_mask_cmpneq_epi64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
602		return (__mmask8)__builtin_ia32_cmpq256_mask((__v4di)__a, (__v4di)__b, 4,
603		__u);
604		}
605
606		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
607		_mm256_cmpneq_epu64_mask(__m256i __a, __m256i __b) {
608		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 4,
609		(__mmask8)-1);
610		}
611
612		static __inline__ __mmask8 __DEFAULT_FN_ATTRS
613		_mm256_mask_cmpneq_epu64_mask(__mmask8 __u, __m256i __a, __m256i __b) {
614		return (__mmask8)__builtin_ia32_ucmpq256_mask((__v4di)__a, (__v4di)__b, 4,
615		__u);
616		}
	41	#define _mm_cmpeq_epi32_mask(A, B) \
	42	_mm_cmp_epi32_mask((A), (B), _MM_CMPINT_EQ)
	43	#define _mm_mask_cmpeq_epi32_mask(k, A, B) \
	44	_mm_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_EQ)
	45	#define _mm_cmpge_epi32_mask(A, B) \
	46	_mm_cmp_epi32_mask((A), (B), _MM_CMPINT_GE)
	47	#define _mm_mask_cmpge_epi32_mask(k, A, B) \
	48	_mm_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_GE)
	49	#define _mm_cmpgt_epi32_mask(A, B) \
	50	_mm_cmp_epi32_mask((A), (B), _MM_CMPINT_GT)
	51	#define _mm_mask_cmpgt_epi32_mask(k, A, B) \
	52	_mm_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_GT)
	53	#define _mm_cmple_epi32_mask(A, B) \
	54	_mm_cmp_epi32_mask((A), (B), _MM_CMPINT_LE)
	55	#define _mm_mask_cmple_epi32_mask(k, A, B) \
	56	_mm_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_LE)
	57	#define _mm_cmplt_epi32_mask(A, B) \
	58	_mm_cmp_epi32_mask((A), (B), _MM_CMPINT_LT)
	59	#define _mm_mask_cmplt_epi32_mask(k, A, B) \
	60	_mm_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_LT)
	61	#define _mm_cmpneq_epi32_mask(A, B) \
	62	_mm_cmp_epi32_mask((A), (B), _MM_CMPINT_NE)
	63	#define _mm_mask_cmpneq_epi32_mask(k, A, B) \
	64	_mm_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_NE)
	65
	66	#define _mm256_cmpeq_epi32_mask(A, B) \
	67	_mm256_cmp_epi32_mask((A), (B), _MM_CMPINT_EQ)
	68	#define _mm256_mask_cmpeq_epi32_mask(k, A, B) \
	69	_mm256_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_EQ)
	70	#define _mm256_cmpge_epi32_mask(A, B) \
	71	_mm256_cmp_epi32_mask((A), (B), _MM_CMPINT_GE)
	72	#define _mm256_mask_cmpge_epi32_mask(k, A, B) \
	73	_mm256_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_GE)
	74	#define _mm256_cmpgt_epi32_mask(A, B) \
	75	_mm256_cmp_epi32_mask((A), (B), _MM_CMPINT_GT)
	76	#define _mm256_mask_cmpgt_epi32_mask(k, A, B) \
	77	_mm256_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_GT)
	78	#define _mm256_cmple_epi32_mask(A, B) \
	79	_mm256_cmp_epi32_mask((A), (B), _MM_CMPINT_LE)
	80	#define _mm256_mask_cmple_epi32_mask(k, A, B) \
	81	_mm256_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_LE)
	82	#define _mm256_cmplt_epi32_mask(A, B) \
	83	_mm256_cmp_epi32_mask((A), (B), _MM_CMPINT_LT)
	84	#define _mm256_mask_cmplt_epi32_mask(k, A, B) \
	85	_mm256_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_LT)
	86	#define _mm256_cmpneq_epi32_mask(A, B) \
	87	_mm256_cmp_epi32_mask((A), (B), _MM_CMPINT_NE)
	88	#define _mm256_mask_cmpneq_epi32_mask(k, A, B) \
	89	_mm256_mask_cmp_epi32_mask((k), (A), (B), _MM_CMPINT_NE)
	90
	91	#define _mm_cmpeq_epu32_mask(A, B) \
	92	_mm_cmp_epu32_mask((A), (B), _MM_CMPINT_EQ)
	93	#define _mm_mask_cmpeq_epu32_mask(k, A, B) \
	94	_mm_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_EQ)
	95	#define _mm_cmpge_epu32_mask(A, B) \
	96	_mm_cmp_epu32_mask((A), (B), _MM_CMPINT_GE)
	97	#define _mm_mask_cmpge_epu32_mask(k, A, B) \
	98	_mm_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_GE)
	99	#define _mm_cmpgt_epu32_mask(A, B) \
	100	_mm_cmp_epu32_mask((A), (B), _MM_CMPINT_GT)
	101	#define _mm_mask_cmpgt_epu32_mask(k, A, B) \
	102	_mm_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_GT)
	103	#define _mm_cmple_epu32_mask(A, B) \
	104	_mm_cmp_epu32_mask((A), (B), _MM_CMPINT_LE)
	105	#define _mm_mask_cmple_epu32_mask(k, A, B) \
	106	_mm_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_LE)
	107	#define _mm_cmplt_epu32_mask(A, B) \
	108	_mm_cmp_epu32_mask((A), (B), _MM_CMPINT_LT)
	109	#define _mm_mask_cmplt_epu32_mask(k, A, B) \
	110	_mm_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_LT)
	111	#define _mm_cmpneq_epu32_mask(A, B) \
	112	_mm_cmp_epu32_mask((A), (B), _MM_CMPINT_NE)
	113	#define _mm_mask_cmpneq_epu32_mask(k, A, B) \
	114	_mm_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_NE)
	115
	116	#define _mm256_cmpeq_epu32_mask(A, B) \
	117	_mm256_cmp_epu32_mask((A), (B), _MM_CMPINT_EQ)
	118	#define _mm256_mask_cmpeq_epu32_mask(k, A, B) \
	119	_mm256_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_EQ)
	120	#define _mm256_cmpge_epu32_mask(A, B) \
	121	_mm256_cmp_epu32_mask((A), (B), _MM_CMPINT_GE)
	122	#define _mm256_mask_cmpge_epu32_mask(k, A, B) \
	123	_mm256_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_GE)
	124	#define _mm256_cmpgt_epu32_mask(A, B) \
	125	_mm256_cmp_epu32_mask((A), (B), _MM_CMPINT_GT)
	126	#define _mm256_mask_cmpgt_epu32_mask(k, A, B) \
	127	_mm256_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_GT)
	128	#define _mm256_cmple_epu32_mask(A, B) \
	129	_mm256_cmp_epu32_mask((A), (B), _MM_CMPINT_LE)
	130	#define _mm256_mask_cmple_epu32_mask(k, A, B) \
	131	_mm256_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_LE)
	132	#define _mm256_cmplt_epu32_mask(A, B) \
	133	_mm256_cmp_epu32_mask((A), (B), _MM_CMPINT_LT)
	134	#define _mm256_mask_cmplt_epu32_mask(k, A, B) \
	135	_mm256_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_LT)
	136	#define _mm256_cmpneq_epu32_mask(A, B) \
	137	_mm256_cmp_epu32_mask((A), (B), _MM_CMPINT_NE)
	138	#define _mm256_mask_cmpneq_epu32_mask(k, A, B) \
	139	_mm256_mask_cmp_epu32_mask((k), (A), (B), _MM_CMPINT_NE)
	140
	141	#define _mm_cmpeq_epi64_mask(A, B) \
	142	_mm_cmp_epi64_mask((A), (B), _MM_CMPINT_EQ)
	143	#define _mm_mask_cmpeq_epi64_mask(k, A, B) \
	144	_mm_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_EQ)
	145	#define _mm_cmpge_epi64_mask(A, B) \
	146	_mm_cmp_epi64_mask((A), (B), _MM_CMPINT_GE)
	147	#define _mm_mask_cmpge_epi64_mask(k, A, B) \
	148	_mm_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_GE)
	149	#define _mm_cmpgt_epi64_mask(A, B) \
	150	_mm_cmp_epi64_mask((A), (B), _MM_CMPINT_GT)
	151	#define _mm_mask_cmpgt_epi64_mask(k, A, B) \
	152	_mm_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_GT)
	153	#define _mm_cmple_epi64_mask(A, B) \
	154	_mm_cmp_epi64_mask((A), (B), _MM_CMPINT_LE)
	155	#define _mm_mask_cmple_epi64_mask(k, A, B) \
	156	_mm_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_LE)
	157	#define _mm_cmplt_epi64_mask(A, B) \
	158	_mm_cmp_epi64_mask((A), (B), _MM_CMPINT_LT)
	159	#define _mm_mask_cmplt_epi64_mask(k, A, B) \
	160	_mm_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_LT)
	161	#define _mm_cmpneq_epi64_mask(A, B) \
	162	_mm_cmp_epi64_mask((A), (B), _MM_CMPINT_NE)
	163	#define _mm_mask_cmpneq_epi64_mask(k, A, B) \
	164	_mm_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_NE)
	165
	166	#define _mm256_cmpeq_epi64_mask(A, B) \
	167	_mm256_cmp_epi64_mask((A), (B), _MM_CMPINT_EQ)
	168	#define _mm256_mask_cmpeq_epi64_mask(k, A, B) \
	169	_mm256_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_EQ)
	170	#define _mm256_cmpge_epi64_mask(A, B) \
	171	_mm256_cmp_epi64_mask((A), (B), _MM_CMPINT_GE)
	172	#define _mm256_mask_cmpge_epi64_mask(k, A, B) \
	173	_mm256_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_GE)
	174	#define _mm256_cmpgt_epi64_mask(A, B) \
	175	_mm256_cmp_epi64_mask((A), (B), _MM_CMPINT_GT)
	176	#define _mm256_mask_cmpgt_epi64_mask(k, A, B) \
	177	_mm256_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_GT)
	178	#define _mm256_cmple_epi64_mask(A, B) \
	179	_mm256_cmp_epi64_mask((A), (B), _MM_CMPINT_LE)
	180	#define _mm256_mask_cmple_epi64_mask(k, A, B) \
	181	_mm256_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_LE)
	182	#define _mm256_cmplt_epi64_mask(A, B) \
	183	_mm256_cmp_epi64_mask((A), (B), _MM_CMPINT_LT)
	184	#define _mm256_mask_cmplt_epi64_mask(k, A, B) \
	185	_mm256_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_LT)
	186	#define _mm256_cmpneq_epi64_mask(A, B) \
	187	_mm256_cmp_epi64_mask((A), (B), _MM_CMPINT_NE)
	188	#define _mm256_mask_cmpneq_epi64_mask(k, A, B) \
	189	_mm256_mask_cmp_epi64_mask((k), (A), (B), _MM_CMPINT_NE)
	190
	191	#define _mm_cmpeq_epu64_mask(A, B) \
	192	_mm_cmp_epu64_mask((A), (B), _MM_CMPINT_EQ)
	193	#define _mm_mask_cmpeq_epu64_mask(k, A, B) \
	194	_mm_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_EQ)
	195	#define _mm_cmpge_epu64_mask(A, B) \
	196	_mm_cmp_epu64_mask((A), (B), _MM_CMPINT_GE)
	197	#define _mm_mask_cmpge_epu64_mask(k, A, B) \
	198	_mm_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_GE)
	199	#define _mm_cmpgt_epu64_mask(A, B) \
	200	_mm_cmp_epu64_mask((A), (B), _MM_CMPINT_GT)
	201	#define _mm_mask_cmpgt_epu64_mask(k, A, B) \
	202	_mm_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_GT)
	203	#define _mm_cmple_epu64_mask(A, B) \
	204	_mm_cmp_epu64_mask((A), (B), _MM_CMPINT_LE)
	205	#define _mm_mask_cmple_epu64_mask(k, A, B) \
	206	_mm_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_LE)
	207	#define _mm_cmplt_epu64_mask(A, B) \
	208	_mm_cmp_epu64_mask((A), (B), _MM_CMPINT_LT)
	209	#define _mm_mask_cmplt_epu64_mask(k, A, B) \
	210	_mm_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_LT)
	211	#define _mm_cmpneq_epu64_mask(A, B) \
	212	_mm_cmp_epu64_mask((A), (B), _MM_CMPINT_NE)
	213	#define _mm_mask_cmpneq_epu64_mask(k, A, B) \
	214	_mm_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_NE)
	215
	216	#define _mm256_cmpeq_epu64_mask(A, B) \
	217	_mm256_cmp_epu64_mask((A), (B), _MM_CMPINT_EQ)
	218	#define _mm256_mask_cmpeq_epu64_mask(k, A, B) \
	219	_mm256_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_EQ)
	220	#define _mm256_cmpge_epu64_mask(A, B) \
	221	_mm256_cmp_epu64_mask((A), (B), _MM_CMPINT_GE)
	222	#define _mm256_mask_cmpge_epu64_mask(k, A, B) \
	223	_mm256_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_GE)
	224	#define _mm256_cmpgt_epu64_mask(A, B) \
	225	_mm256_cmp_epu64_mask((A), (B), _MM_CMPINT_GT)
	226	#define _mm256_mask_cmpgt_epu64_mask(k, A, B) \
	227	_mm256_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_GT)
	228	#define _mm256_cmple_epu64_mask(A, B) \
	229	_mm256_cmp_epu64_mask((A), (B), _MM_CMPINT_LE)
	230	#define _mm256_mask_cmple_epu64_mask(k, A, B) \
	231	_mm256_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_LE)
	232	#define _mm256_cmplt_epu64_mask(A, B) \
	233	_mm256_cmp_epu64_mask((A), (B), _MM_CMPINT_LT)
	234	#define _mm256_mask_cmplt_epu64_mask(k, A, B) \
	235	_mm256_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_LT)
	236	#define _mm256_cmpneq_epu64_mask(A, B) \
	237	_mm256_cmp_epu64_mask((A), (B), _MM_CMPINT_NE)
	238	#define _mm256_mask_cmpneq_epu64_mask(k, A, B) \
	239	_mm256_mask_cmp_epu64_mask((k), (A), (B), _MM_CMPINT_NE)
617	240
618	241	static __inline__ __m256i __DEFAULT_FN_ATTRS
619	242	_mm256_mask_add_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)
...	...	@@ -6503,125 +6126,111 @@ _mm256_maskz_permutevar_ps(__mmask8 __U, __m256 __A, __m256i __C)
6503	6126	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6504	6127	_mm_test_epi32_mask (__m128i __A, __m128i __B)
6505	6128	{
6506		return (__mmask8) __builtin_ia32_ptestmd128 ((__v4si) __A,
6507		(__v4si) __B,
6508		(__mmask8) -1);
	6129	return _mm_cmpneq_epi32_mask (_mm_and_si128 (__A, __B), _mm_setzero_di());
6509	6130	}
6510	6131
6511	6132	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6512	6133	_mm_mask_test_epi32_mask (__mmask8 __U, __m128i __A, __m128i __B)
6513	6134	{
6514		return (__mmask8) __builtin_ia32_ptestmd128 ((__v4si) __A,
6515		(__v4si) __B, __U);
	6135	return _mm_mask_cmpneq_epi32_mask (__U, _mm_and_si128 (__A, __B),
	6136	_mm_setzero_di());
6516	6137	}
6517	6138
6518	6139	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6519	6140	_mm256_test_epi32_mask (__m256i __A, __m256i __B)
6520	6141	{
6521		return (__mmask8) __builtin_ia32_ptestmd256 ((__v8si) __A,
6522		(__v8si) __B,
6523		(__mmask8) -1);
	6142	return _mm256_cmpneq_epi32_mask (_mm256_and_si256 (__A, __B),
	6143	_mm256_setzero_si256());
6524	6144	}
6525	6145
6526	6146	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6527	6147	_mm256_mask_test_epi32_mask (__mmask8 __U, __m256i __A, __m256i __B)
6528	6148	{
6529		return (__mmask8) __builtin_ia32_ptestmd256 ((__v8si) __A,
6530		(__v8si) __B, __U);
	6149	return _mm256_mask_cmpneq_epi32_mask (__U, _mm256_and_si256 (__A, __B),
	6150	_mm256_setzero_si256());
6531	6151	}
6532	6152
6533	6153	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6534	6154	_mm_test_epi64_mask (__m128i __A, __m128i __B)
6535	6155	{
6536		return (__mmask8) __builtin_ia32_ptestmq128 ((__v2di) __A,
6537		(__v2di) __B,
6538		(__mmask8) -1);
	6156	return _mm_cmpneq_epi64_mask (_mm_and_si128 (__A, __B), _mm_setzero_di());
6539	6157	}
6540	6158
6541	6159	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6542	6160	_mm_mask_test_epi64_mask (__mmask8 __U, __m128i __A, __m128i __B)
6543	6161	{
6544		return (__mmask8) __builtin_ia32_ptestmq128 ((__v2di) __A,
6545		(__v2di) __B, __U);
	6162	return _mm_mask_cmpneq_epi64_mask (__U, _mm_and_si128 (__A, __B),
	6163	_mm_setzero_di());
6546	6164	}
6547	6165
6548	6166	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6549	6167	_mm256_test_epi64_mask (__m256i __A, __m256i __B)
6550	6168	{
6551		return (__mmask8) __builtin_ia32_ptestmq256 ((__v4di) __A,
6552		(__v4di) __B,
6553		(__mmask8) -1);
	6169	return _mm256_cmpneq_epi64_mask (_mm256_and_si256 (__A, __B),
	6170	_mm256_setzero_si256());
6554	6171	}
6555	6172
6556	6173	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6557	6174	_mm256_mask_test_epi64_mask (__mmask8 __U, __m256i __A, __m256i __B)
6558	6175	{
6559		return (__mmask8) __builtin_ia32_ptestmq256 ((__v4di) __A,
6560		(__v4di) __B, __U);
	6176	return _mm256_mask_cmpneq_epi64_mask (__U, _mm256_and_si256 (__A, __B),
	6177	_mm256_setzero_si256());
6561	6178	}
6562	6179
6563	6180	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6564	6181	_mm_testn_epi32_mask (__m128i __A, __m128i __B)
6565	6182	{
6566		return (__mmask8) __builtin_ia32_ptestnmd128 ((__v4si) __A,
6567		(__v4si) __B,
6568		(__mmask8) -1);
	6183	return _mm_cmpeq_epi32_mask (_mm_and_si128 (__A, __B), _mm_setzero_di());
6569	6184	}
6570	6185
6571	6186	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6572	6187	_mm_mask_testn_epi32_mask (__mmask8 __U, __m128i __A, __m128i __B)
6573	6188	{
6574		return (__mmask8) __builtin_ia32_ptestnmd128 ((__v4si) __A,
6575		(__v4si) __B, __U);
	6189	return _mm_mask_cmpeq_epi32_mask (__U, _mm_and_si128 (__A, __B),
	6190	_mm_setzero_di());
6576	6191	}
6577	6192
6578	6193	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6579	6194	_mm256_testn_epi32_mask (__m256i __A, __m256i __B)
6580	6195	{
6581		return (__mmask8) __builtin_ia32_ptestnmd256 ((__v8si) __A,
6582		(__v8si) __B,
6583		(__mmask8) -1);
	6196	return _mm256_cmpeq_epi32_mask (_mm256_and_si256 (__A, __B),
	6197	_mm256_setzero_si256());
6584	6198	}
6585	6199
6586	6200	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6587	6201	_mm256_mask_testn_epi32_mask (__mmask8 __U, __m256i __A, __m256i __B)
6588	6202	{
6589		return (__mmask8) __builtin_ia32_ptestnmd256 ((__v8si) __A,
6590		(__v8si) __B, __U);
	6203	return _mm256_mask_cmpeq_epi32_mask (__U, _mm256_and_si256 (__A, __B),
	6204	_mm256_setzero_si256());
6591	6205	}
6592	6206
6593	6207	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6594	6208	_mm_testn_epi64_mask (__m128i __A, __m128i __B)
6595	6209	{
6596		return (__mmask8) __builtin_ia32_ptestnmq128 ((__v2di) __A,
6597		(__v2di) __B,
6598		(__mmask8) -1);
	6210	return _mm_cmpeq_epi64_mask (_mm_and_si128 (__A, __B), _mm_setzero_di());
6599	6211	}
6600	6212
6601	6213	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6602	6214	_mm_mask_testn_epi64_mask (__mmask8 __U, __m128i __A, __m128i __B)
6603	6215	{
6604		return (__mmask8) __builtin_ia32_ptestnmq128 ((__v2di) __A,
6605		(__v2di) __B, __U);
	6216	return _mm_mask_cmpeq_epi64_mask (__U, _mm_and_si128 (__A, __B),
	6217	_mm_setzero_di());
6606	6218	}
6607	6219
6608	6220	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6609	6221	_mm256_testn_epi64_mask (__m256i __A, __m256i __B)
6610	6222	{
6611		return (__mmask8) __builtin_ia32_ptestnmq256 ((__v4di) __A,
6612		(__v4di) __B,
6613		(__mmask8) -1);
	6223	return _mm256_cmpeq_epi64_mask (_mm256_and_si256 (__A, __B),
	6224	_mm256_setzero_si256());
6614	6225	}
6615	6226
6616	6227	static __inline__ __mmask8 __DEFAULT_FN_ATTRS
6617	6228	_mm256_mask_testn_epi64_mask (__mmask8 __U, __m256i __A, __m256i __B)
6618	6229	{
6619		return (__mmask8) __builtin_ia32_ptestnmq256 ((__v4di) __A,
6620		(__v4di) __B, __U);
	6230	return _mm256_mask_cmpeq_epi64_mask (__U, _mm256_and_si256 (__A, __B),
	6231	_mm256_setzero_si256());
6621	6232	}
6622	6233
6623
6624
6625	6234	static __inline__ __m128i __DEFAULT_FN_ATTRS
6626	6235	_mm_mask_unpackhi_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)
6627	6236	{
...	...	@@ -6977,85 +6586,81 @@ _mm256_maskz_srai_epi64(__mmask8 __U, __m256i __A, int __imm)
6977	6586
6978	6587
6979	6588	#define _mm256_shuffle_f32x4(A, B, imm) __extension__ ({ \
6980		(__m256)__builtin_ia32_shuf_f32x4_256_mask((__v8sf)(__m256)(A), \
6981		(__v8sf)(__m256)(B), (int)(imm), \
6982		(__v8sf)_mm256_setzero_ps(), \
6983		(__mmask8)-1); })
	6589	(__m256)__builtin_shufflevector((__v8sf)(__m256)(A), \
	6590	(__v8sf)(__m256)(B), \
	6591	0 + ((((imm) >> 0) & 0x1) * 4), \
	6592	1 + ((((imm) >> 0) & 0x1) * 4), \
	6593	2 + ((((imm) >> 0) & 0x1) * 4), \
	6594	3 + ((((imm) >> 0) & 0x1) * 4), \
	6595	8 + ((((imm) >> 1) & 0x1) * 4), \
	6596	9 + ((((imm) >> 1) & 0x1) * 4), \
	6597	10 + ((((imm) >> 1) & 0x1) * 4), \
	6598	11 + ((((imm) >> 1) & 0x1) * 4)); })
6984	6599
6985	6600	#define _mm256_mask_shuffle_f32x4(W, U, A, B, imm) __extension__ ({ \
6986		(__m256)__builtin_ia32_shuf_f32x4_256_mask((__v8sf)(__m256)(A), \
6987		(__v8sf)(__m256)(B), (int)(imm), \
6988		(__v8sf)(__m256)(W), \
6989		(__mmask8)(U)); })
	6601	(__m256)__builtin_ia32_selectps_256((__mmask8)(U), \
	6602	(__v8sf)_mm256_shuffle_f32x4((A), (B), (imm)), \
	6603	(__v8sf)(__m256)(W)); })
6990	6604
6991	6605	#define _mm256_maskz_shuffle_f32x4(U, A, B, imm) __extension__ ({ \
6992		(__m256)__builtin_ia32_shuf_f32x4_256_mask((__v8sf)(__m256)(A), \
6993		(__v8sf)(__m256)(B), (int)(imm), \
6994		(__v8sf)_mm256_setzero_ps(), \
6995		(__mmask8)(U)); })
	6606	(__m256)__builtin_ia32_selectps_256((__mmask8)(U), \
	6607	(__v8sf)_mm256_shuffle_f32x4((A), (B), (imm)), \
	6608	(__v8sf)_mm256_setzero_ps()); })
6996	6609
6997	6610	#define _mm256_shuffle_f64x2(A, B, imm) __extension__ ({ \
6998		(__m256d)__builtin_ia32_shuf_f64x2_256_mask((__v4df)(__m256d)(A), \
6999		(__v4df)(__m256d)(B), \
7000		(int)(imm), \
7001		(__v4df)_mm256_setzero_pd(), \
7002		(__mmask8)-1); })
	6611	(__m256d)__builtin_shufflevector((__v4df)(__m256d)(A), \
	6612	(__v4df)(__m256d)(B), \
	6613	0 + ((((imm) >> 0) & 0x1) * 2), \
	6614	1 + ((((imm) >> 0) & 0x1) * 2), \
	6615	4 + ((((imm) >> 1) & 0x1) * 2), \
	6616	5 + ((((imm) >> 1) & 0x1) * 2)); })
7003	6617
7004	6618	#define _mm256_mask_shuffle_f64x2(W, U, A, B, imm) __extension__ ({ \
7005		(__m256d)__builtin_ia32_shuf_f64x2_256_mask((__v4df)(__m256d)(A), \
7006		(__v4df)(__m256d)(B), \
7007		(int)(imm), \
7008		(__v4df)(__m256d)(W), \
7009		(__mmask8)(U)); })
	6619	(__m256d)__builtin_ia32_selectpd_256((__mmask8)(U), \
	6620	(__v4df)_mm256_shuffle_f64x2((A), (B), (imm)), \
	6621	(__v4df)(__m256)(W)); })
7010	6622
7011	6623	#define _mm256_maskz_shuffle_f64x2(U, A, B, imm) __extension__ ({ \
7012		(__m256d)__builtin_ia32_shuf_f64x2_256_mask((__v4df)(__m256d)(A), \
7013		(__v4df)(__m256d)(B), \
7014		(int)(imm), \
7015		(__v4df)_mm256_setzero_pd(), \
7016		(__mmask8)(U)); })
	6624	(__m256d)__builtin_ia32_selectpd_256((__mmask8)(U), \
	6625	(__v4df)_mm256_shuffle_f64x2((A), (B), (imm)), \
	6626	(__v4df)_mm256_setzero_pd()); })
7017	6627
7018	6628	#define _mm256_shuffle_i32x4(A, B, imm) __extension__ ({ \
7019		(__m256i)__builtin_ia32_shuf_i32x4_256_mask((__v8si)(__m256i)(A), \
7020		(__v8si)(__m256i)(B), \
7021		(int)(imm), \
7022		(__v8si)_mm256_setzero_si256(), \
7023		(__mmask8)-1); })
	6629	(__m256i)__builtin_shufflevector((__v4di)(__m256i)(A), \
	6630	(__v4di)(__m256i)(B), \
	6631	0 + ((((imm) >> 0) & 0x1) * 2), \
	6632	1 + ((((imm) >> 0) & 0x1) * 2), \
	6633	4 + ((((imm) >> 1) & 0x1) * 2), \
	6634	5 + ((((imm) >> 1) & 0x1) * 2)); })
7024	6635
7025	6636	#define _mm256_mask_shuffle_i32x4(W, U, A, B, imm) __extension__ ({ \
7026		(__m256i)__builtin_ia32_shuf_i32x4_256_mask((__v8si)(__m256i)(A), \
7027		(__v8si)(__m256i)(B), \
7028		(int)(imm), \
7029		(__v8si)(__m256i)(W), \
7030		(__mmask8)(U)); })
	6637	(__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \
	6638	(__v8si)_mm256_shuffle_i32x4((A), (B), (imm)), \
	6639	(__v8si)(__m256)(W)); })
7031	6640
7032	6641	#define _mm256_maskz_shuffle_i32x4(U, A, B, imm) __extension__ ({ \
7033		(__m256i)__builtin_ia32_shuf_i32x4_256_mask((__v8si)(__m256i)(A), \
7034		(__v8si)(__m256i)(B), \
7035		(int)(imm), \
7036		(__v8si)_mm256_setzero_si256(), \
7037		(__mmask8)(U)); })
	6642	(__m256i)__builtin_ia32_selectd_256((__mmask8)(U), \
	6643	(__v8si)_mm256_shuffle_i32x4((A), (B), (imm)), \
	6644	(__v8si)_mm256_setzero_si256()); })
7038	6645
7039	6646	#define _mm256_shuffle_i64x2(A, B, imm) __extension__ ({ \
7040		(__m256i)__builtin_ia32_shuf_i64x2_256_mask((__v4di)(__m256i)(A), \
7041		(__v4di)(__m256i)(B), \
7042		(int)(imm), \
7043		(__v4di)_mm256_setzero_si256(), \
7044		(__mmask8)-1); })
	6647	(__m256i)__builtin_shufflevector((__v4di)(__m256i)(A), \
	6648	(__v4di)(__m256i)(B), \
	6649	0 + ((((imm) >> 0) & 0x1) * 2), \
	6650	1 + ((((imm) >> 0) & 0x1) * 2), \
	6651	4 + ((((imm) >> 1) & 0x1) * 2), \
	6652	5 + ((((imm) >> 1) & 0x1) * 2)); })
7045	6653
7046	6654	#define _mm256_mask_shuffle_i64x2(W, U, A, B, imm) __extension__ ({ \
7047		(__m256i)__builtin_ia32_shuf_i64x2_256_mask((__v4di)(__m256i)(A), \
7048		(__v4di)(__m256i)(B), \
7049		(int)(imm), \
7050		(__v4di)(__m256i)(W), \
7051		(__mmask8)(U)); })
	6655	(__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
	6656	(__v4di)_mm256_shuffle_i64x2((A), (B), (imm)), \
	6657	(__v4di)(__m256)(W)); })
	6658
7052	6659
7053	6660	#define _mm256_maskz_shuffle_i64x2(U, A, B, imm) __extension__ ({ \
7054		(__m256i)__builtin_ia32_shuf_i64x2_256_mask((__v4di)(__m256i)(A), \
7055		(__v4di)(__m256i)(B), \
7056		(int)(imm), \
7057		(__v4di)_mm256_setzero_si256(), \
7058		(__mmask8)(U)); })
	6661	(__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
	6662	(__v4di)_mm256_shuffle_i64x2((A), (B), (imm)), \
	6663	(__v4di)_mm256_setzero_si256()); })
7059	6664
7060	6665	#define _mm_mask_shuffle_pd(W, U, A, B, M) __extension__ ({ \
7061	6666	(__m128d)__builtin_ia32_selectpd_128((__mmask8)(U), \

c_headers/avx512vlvbmi2intrin.h created+748

...	...	@@ -0,0 +1,748 @@
	1	/*===------------- avx512vlvbmi2intrin.h - VBMI2 intrinsics -----------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <avx512vlvbmi2intrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __AVX512VLVBMI2INTRIN_H
	29	#define __AVX512VLVBMI2INTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vbmi2")))
	33
	34	static __inline __m128i __DEFAULT_FN_ATTRS
	35	_mm128_setzero_hi(void) {
	36	return (__m128i)(__v8hi){ 0, 0, 0, 0, 0, 0, 0, 0 };
	37	}
	38
	39	static __inline__ __m128i __DEFAULT_FN_ATTRS
	40	_mm128_mask_compress_epi16(__m128i __S, __mmask8 __U, __m128i __D)
	41	{
	42	return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
	43	(__v8hi) __S,
	44	__U);
	45	}
	46
	47	static __inline__ __m128i __DEFAULT_FN_ATTRS
	48	_mm128_maskz_compress_epi16(__mmask8 __U, __m128i __D)
	49	{
	50	return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __D,
	51	(__v8hi) _mm128_setzero_hi(),
	52	__U);
	53	}
	54
	55	static __inline__ __m128i __DEFAULT_FN_ATTRS
	56	_mm128_mask_compress_epi8(__m128i __S, __mmask16 __U, __m128i __D)
	57	{
	58	return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
	59	(__v16qi) __S,
	60	__U);
	61	}
	62
	63	static __inline__ __m128i __DEFAULT_FN_ATTRS
	64	_mm128_maskz_compress_epi8(__mmask16 __U, __m128i __D)
	65	{
	66	return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __D,
	67	(__v16qi) _mm128_setzero_hi(),
	68	__U);
	69	}
	70
	71	static __inline__ void __DEFAULT_FN_ATTRS
	72	_mm128_mask_compressstoreu_epi16(void *__P, __mmask8 __U, __m128i __D)
	73	{
	74	__builtin_ia32_compressstorehi128_mask ((__v8hi *) __P, (__v8hi) __D,
	75	__U);
	76	}
	77
	78	static __inline__ void __DEFAULT_FN_ATTRS
	79	_mm128_mask_compressstoreu_epi8(void *__P, __mmask16 __U, __m128i __D)
	80	{
	81	__builtin_ia32_compressstoreqi128_mask ((__v16qi *) __P, (__v16qi) __D,
	82	__U);
	83	}
	84
	85	static __inline__ __m128i __DEFAULT_FN_ATTRS
	86	_mm128_mask_expand_epi16(__m128i __S, __mmask8 __U, __m128i __D)
	87	{
	88	return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
	89	(__v8hi) __S,
	90	__U);
	91	}
	92
	93	static __inline__ __m128i __DEFAULT_FN_ATTRS
	94	_mm128_maskz_expand_epi16(__mmask8 __U, __m128i __D)
	95	{
	96	return (__m128i) __builtin_ia32_expandhi128_mask ((__v8hi) __D,
	97	(__v8hi) _mm128_setzero_hi(),
	98	__U);
	99	}
	100
	101	static __inline__ __m128i __DEFAULT_FN_ATTRS
	102	_mm128_mask_expand_epi8(__m128i __S, __mmask16 __U, __m128i __D)
	103	{
	104	return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
	105	(__v16qi) __S,
	106	__U);
	107	}
	108
	109	static __inline__ __m128i __DEFAULT_FN_ATTRS
	110	_mm128_maskz_expand_epi8(__mmask16 __U, __m128i __D)
	111	{
	112	return (__m128i) __builtin_ia32_expandqi128_mask ((__v16qi) __D,
	113	(__v16qi) _mm128_setzero_hi(),
	114	__U);
	115	}
	116
	117	static __inline__ __m128i __DEFAULT_FN_ATTRS
	118	_mm128_mask_expandloadu_epi16(__m128i __S, __mmask8 __U, void const *__P)
	119	{
	120	return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P,
	121	(__v8hi) __S,
	122	__U);
	123	}
	124
	125	static __inline__ __m128i __DEFAULT_FN_ATTRS
	126	_mm128_maskz_expandloadu_epi16(__mmask8 __U, void const *__P)
	127	{
	128	return (__m128i) __builtin_ia32_expandloadhi128_mask ((const __v8hi *)__P,
	129	(__v8hi) _mm128_setzero_hi(),
	130	__U);
	131	}
	132
	133	static __inline__ __m128i __DEFAULT_FN_ATTRS
	134	_mm128_mask_expandloadu_epi8(__m128i __S, __mmask16 __U, void const *__P)
	135	{
	136	return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P,
	137	(__v16qi) __S,
	138	__U);
	139	}
	140
	141	static __inline__ __m128i __DEFAULT_FN_ATTRS
	142	_mm128_maskz_expandloadu_epi8(__mmask16 __U, void const *__P)
	143	{
	144	return (__m128i) __builtin_ia32_expandloadqi128_mask ((const __v16qi *)__P,
	145	(__v16qi) _mm128_setzero_hi(),
	146	__U);
	147	}
	148
	149	static __inline __m256i __DEFAULT_FN_ATTRS
	150	_mm256_setzero_hi(void) {
	151	return (__m256i)(__v16hi){ 0, 0, 0, 0, 0, 0, 0, 0,
	152	0, 0, 0, 0, 0, 0, 0, 0 };
	153	}
	154
	155	static __inline__ __m256i __DEFAULT_FN_ATTRS
	156	_mm256_mask_compress_epi16(__m256i __S, __mmask16 __U, __m256i __D)
	157	{
	158	return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
	159	(__v16hi) __S,
	160	__U);
	161	}
	162
	163	static __inline__ __m256i __DEFAULT_FN_ATTRS
	164	_mm256_maskz_compress_epi16(__mmask16 __U, __m256i __D)
	165	{
	166	return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __D,
	167	(__v16hi) _mm256_setzero_hi(),
	168	__U);
	169	}
	170
	171	static __inline__ __m256i __DEFAULT_FN_ATTRS
	172	_mm256_mask_compress_epi8(__m256i __S, __mmask32 __U, __m256i __D)
	173	{
	174	return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
	175	(__v32qi) __S,
	176	__U);
	177	}
	178
	179	static __inline__ __m256i __DEFAULT_FN_ATTRS
	180	_mm256_maskz_compress_epi8(__mmask32 __U, __m256i __D)
	181	{
	182	return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __D,
	183	(__v32qi) _mm256_setzero_hi(),
	184	__U);
	185	}
	186
	187	static __inline__ void __DEFAULT_FN_ATTRS
	188	_mm256_mask_compressstoreu_epi16(void *__P, __mmask16 __U, __m256i __D)
	189	{
	190	__builtin_ia32_compressstorehi256_mask ((__v16hi *) __P, (__v16hi) __D,
	191	__U);
	192	}
	193
	194	static __inline__ void __DEFAULT_FN_ATTRS
	195	_mm256_mask_compressstoreu_epi8(void *__P, __mmask32 __U, __m256i __D)
	196	{
	197	__builtin_ia32_compressstoreqi256_mask ((__v32qi *) __P, (__v32qi) __D,
	198	__U);
	199	}
	200
	201	static __inline__ __m256i __DEFAULT_FN_ATTRS
	202	_mm256_mask_expand_epi16(__m256i __S, __mmask16 __U, __m256i __D)
	203	{
	204	return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
	205	(__v16hi) __S,
	206	__U);
	207	}
	208
	209	static __inline__ __m256i __DEFAULT_FN_ATTRS
	210	_mm256_maskz_expand_epi16(__mmask16 __U, __m256i __D)
	211	{
	212	return (__m256i) __builtin_ia32_expandhi256_mask ((__v16hi) __D,
	213	(__v16hi) _mm256_setzero_hi(),
	214	__U);
	215	}
	216
	217	static __inline__ __m256i __DEFAULT_FN_ATTRS
	218	_mm256_mask_expand_epi8(__m256i __S, __mmask32 __U, __m256i __D)
	219	{
	220	return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
	221	(__v32qi) __S,
	222	__U);
	223	}
	224
	225	static __inline__ __m256i __DEFAULT_FN_ATTRS
	226	_mm256_maskz_expand_epi8(__mmask32 __U, __m256i __D)
	227	{
	228	return (__m256i) __builtin_ia32_expandqi256_mask ((__v32qi) __D,
	229	(__v32qi) _mm256_setzero_hi(),
	230	__U);
	231	}
	232
	233	static __inline__ __m256i __DEFAULT_FN_ATTRS
	234	_mm256_mask_expandloadu_epi16(__m256i __S, __mmask16 __U, void const *__P)
	235	{
	236	return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P,
	237	(__v16hi) __S,
	238	__U);
	239	}
	240
	241	static __inline__ __m256i __DEFAULT_FN_ATTRS
	242	_mm256_maskz_expandloadu_epi16(__mmask16 __U, void const *__P)
	243	{
	244	return (__m256i) __builtin_ia32_expandloadhi256_mask ((const __v16hi *)__P,
	245	(__v16hi) _mm256_setzero_hi(),
	246	__U);
	247	}
	248
	249	static __inline__ __m256i __DEFAULT_FN_ATTRS
	250	_mm256_mask_expandloadu_epi8(__m256i __S, __mmask32 __U, void const *__P)
	251	{
	252	return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P,
	253	(__v32qi) __S,
	254	__U);
	255	}
	256
	257	static __inline__ __m256i __DEFAULT_FN_ATTRS
	258	_mm256_maskz_expandloadu_epi8(__mmask32 __U, void const *__P)
	259	{
	260	return (__m256i) __builtin_ia32_expandloadqi256_mask ((const __v32qi *)__P,
	261	(__v32qi) _mm256_setzero_hi(),
	262	__U);
	263	}
	264
	265	#define _mm256_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \
	266	(__m256i)__builtin_ia32_vpshldq256_mask((__v4di)(A), \
	267	(__v4di)(B), \
	268	(int)(I), \
	269	(__v4di)(S), \
	270	(__mmask8)(U)); })
	271
	272	#define _mm256_maskz_shldi_epi64(U, A, B, I) \
	273	_mm256_mask_shldi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I))
	274
	275	#define _mm256_shldi_epi64(A, B, I) \
	276	_mm256_mask_shldi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
	277
	278	#define _mm128_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \
	279	(__m128i)__builtin_ia32_vpshldq128_mask((__v2di)(A), \
	280	(__v2di)(B), \
	281	(int)(I), \
	282	(__v2di)(S), \
	283	(__mmask8)(U)); })
	284
	285	#define _mm128_maskz_shldi_epi64(U, A, B, I) \
	286	_mm128_mask_shldi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I))
	287
	288	#define _mm128_shldi_epi64(A, B, I) \
	289	_mm128_mask_shldi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
	290
	291	#define _mm256_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \
	292	(__m256i)__builtin_ia32_vpshldd256_mask((__v8si)(A), \
	293	(__v8si)(B), \
	294	(int)(I), \
	295	(__v8si)(S), \
	296	(__mmask8)(U)); })
	297
	298	#define _mm256_maskz_shldi_epi32(U, A, B, I) \
	299	_mm256_mask_shldi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I))
	300
	301	#define _mm256_shldi_epi32(A, B, I) \
	302	_mm256_mask_shldi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
	303
	304	#define _mm128_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \
	305	(__m128i)__builtin_ia32_vpshldd128_mask((__v4si)(A), \
	306	(__v4si)(B), \
	307	(int)(I), \
	308	(__v4si)(S), \
	309	(__mmask8)(U)); })
	310
	311	#define _mm128_maskz_shldi_epi32(U, A, B, I) \
	312	_mm128_mask_shldi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I))
	313
	314	#define _mm128_shldi_epi32(A, B, I) \
	315	_mm128_mask_shldi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
	316
	317	#define _mm256_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \
	318	(__m256i)__builtin_ia32_vpshldw256_mask((__v16hi)(A), \
	319	(__v16hi)(B), \
	320	(int)(I), \
	321	(__v16hi)(S), \
	322	(__mmask16)(U)); })
	323
	324	#define _mm256_maskz_shldi_epi16(U, A, B, I) \
	325	_mm256_mask_shldi_epi16(_mm256_setzero_hi(), (U), (A), (B), (I))
	326
	327	#define _mm256_shldi_epi16(A, B, I) \
	328	_mm256_mask_shldi_epi16(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
	329
	330	#define _mm128_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \
	331	(__m128i)__builtin_ia32_vpshldw128_mask((__v8hi)(A), \
	332	(__v8hi)(B), \
	333	(int)(I), \
	334	(__v8hi)(S), \
	335	(__mmask8)(U)); })
	336
	337	#define _mm128_maskz_shldi_epi16(U, A, B, I) \
	338	_mm128_mask_shldi_epi16(_mm128_setzero_hi(), (U), (A), (B), (I))
	339
	340	#define _mm128_shldi_epi16(A, B, I) \
	341	_mm128_mask_shldi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
	342
	343	#define _mm256_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \
	344	(__m256i)__builtin_ia32_vpshrdq256_mask((__v4di)(A), \
	345	(__v4di)(B), \
	346	(int)(I), \
	347	(__v4di)(S), \
	348	(__mmask8)(U)); })
	349
	350	#define _mm256_maskz_shrdi_epi64(U, A, B, I) \
	351	_mm256_mask_shrdi_epi64(_mm256_setzero_hi(), (U), (A), (B), (I))
	352
	353	#define _mm256_shrdi_epi64(A, B, I) \
	354	_mm256_mask_shrdi_epi64(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
	355
	356	#define _mm128_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \
	357	(__m128i)__builtin_ia32_vpshrdq128_mask((__v2di)(A), \
	358	(__v2di)(B), \
	359	(int)(I), \
	360	(__v2di)(S), \
	361	(__mmask8)(U)); })
	362
	363	#define _mm128_maskz_shrdi_epi64(U, A, B, I) \
	364	_mm128_mask_shrdi_epi64(_mm128_setzero_hi(), (U), (A), (B), (I))
	365
	366	#define _mm128_shrdi_epi64(A, B, I) \
	367	_mm128_mask_shrdi_epi64(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
	368
	369	#define _mm256_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \
	370	(__m256i)__builtin_ia32_vpshrdd256_mask((__v8si)(A), \
	371	(__v8si)(B), \
	372	(int)(I), \
	373	(__v8si)(S), \
	374	(__mmask8)(U)); })
	375
	376	#define _mm256_maskz_shrdi_epi32(U, A, B, I) \
	377	_mm256_mask_shrdi_epi32(_mm256_setzero_hi(), (U), (A), (B), (I))
	378
	379	#define _mm256_shrdi_epi32(A, B, I) \
	380	_mm256_mask_shrdi_epi32(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
	381
	382	#define _mm128_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \
	383	(__m128i)__builtin_ia32_vpshrdd128_mask((__v4si)(A), \
	384	(__v4si)(B), \
	385	(int)(I), \
	386	(__v4si)(S), \
	387	(__mmask8)(U)); })
	388
	389	#define _mm128_maskz_shrdi_epi32(U, A, B, I) \
	390	_mm128_mask_shrdi_epi32(_mm128_setzero_hi(), (U), (A), (B), (I))
	391
	392	#define _mm128_shrdi_epi32(A, B, I) \
	393	_mm128_mask_shrdi_epi32(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
	394
	395	#define _mm256_mask_shrdi_epi16(S, U, A, B, I) __extension__ ({ \
	396	(__m256i)__builtin_ia32_vpshrdw256_mask((__v16hi)(A), \
	397	(__v16hi)(B), \
	398	(int)(I), \
	399	(__v16hi)(S), \
	400	(__mmask16)(U)); })
	401
	402	#define _mm256_maskz_shrdi_epi16(U, A, B, I) \
	403	_mm256_mask_shrdi_epi16(_mm256_setzero_hi(), (U), (A), (B), (I))
	404
	405	#define _mm256_shrdi_epi16(A, B, I) \
	406	_mm256_mask_shrdi_epi16(_mm256_undefined_si256(), (__mmask8)(-1), (A), (B), (I))
	407
	408	#define _mm128_mask_shrdi_epi16(S, U, A, B, I) __extension__ ({ \
	409	(__m128i)__builtin_ia32_vpshrdw128_mask((__v8hi)(A), \
	410	(__v8hi)(B), \
	411	(int)(I), \
	412	(__v8hi)(S), \
	413	(__mmask8)(U)); })
	414
	415	#define _mm128_maskz_shrdi_epi16(U, A, B, I) \
	416	_mm128_mask_shrdi_epi16(_mm128_setzero_hi(), (U), (A), (B), (I))
	417
	418	#define _mm128_shrdi_epi16(A, B, I) \
	419	_mm128_mask_shrdi_epi16(_mm_undefined_si128(), (__mmask8)(-1), (A), (B), (I))
	420
	421	static __inline__ __m256i __DEFAULT_FN_ATTRS
	422	_mm256_mask_shldv_epi64(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	423	{
	424	return (__m256i) __builtin_ia32_vpshldvq256_mask ((__v4di) __S,
	425	(__v4di) __A,
	426	(__v4di) __B,
	427	__U);
	428	}
	429
	430	static __inline__ __m256i __DEFAULT_FN_ATTRS
	431	_mm256_maskz_shldv_epi64(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	432	{
	433	return (__m256i) __builtin_ia32_vpshldvq256_maskz ((__v4di) __S,
	434	(__v4di) __A,
	435	(__v4di) __B,
	436	__U);
	437	}
	438
	439	static __inline__ __m256i __DEFAULT_FN_ATTRS
	440	_mm256_shldv_epi64(__m256i __S, __m256i __A, __m256i __B)
	441	{
	442	return (__m256i) __builtin_ia32_vpshldvq256_mask ((__v4di) __S,
	443	(__v4di) __A,
	444	(__v4di) __B,
	445	(__mmask8) -1);
	446	}
	447
	448	static __inline__ __m128i __DEFAULT_FN_ATTRS
	449	_mm128_mask_shldv_epi64(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	450	{
	451	return (__m128i) __builtin_ia32_vpshldvq128_mask ((__v2di) __S,
	452	(__v2di) __A,
	453	(__v2di) __B,
	454	__U);
	455	}
	456
	457	static __inline__ __m128i __DEFAULT_FN_ATTRS
	458	_mm128_maskz_shldv_epi64(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	459	{
	460	return (__m128i) __builtin_ia32_vpshldvq128_maskz ((__v2di) __S,
	461	(__v2di) __A,
	462	(__v2di) __B,
	463	__U);
	464	}
	465
	466	static __inline__ __m128i __DEFAULT_FN_ATTRS
	467	_mm128_shldv_epi64(__m128i __S, __m128i __A, __m128i __B)
	468	{
	469	return (__m128i) __builtin_ia32_vpshldvq128_mask ((__v2di) __S,
	470	(__v2di) __A,
	471	(__v2di) __B,
	472	(__mmask8) -1);
	473	}
	474
	475	static __inline__ __m256i __DEFAULT_FN_ATTRS
	476	_mm256_mask_shldv_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	477	{
	478	return (__m256i) __builtin_ia32_vpshldvd256_mask ((__v8si) __S,
	479	(__v8si) __A,
	480	(__v8si) __B,
	481	__U);
	482	}
	483
	484	static __inline__ __m256i __DEFAULT_FN_ATTRS
	485	_mm256_maskz_shldv_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	486	{
	487	return (__m256i) __builtin_ia32_vpshldvd256_maskz ((__v8si) __S,
	488	(__v8si) __A,
	489	(__v8si) __B,
	490	__U);
	491	}
	492
	493	static __inline__ __m256i __DEFAULT_FN_ATTRS
	494	_mm256_shldv_epi32(__m256i __S, __m256i __A, __m256i __B)
	495	{
	496	return (__m256i) __builtin_ia32_vpshldvd256_mask ((__v8si) __S,
	497	(__v8si) __A,
	498	(__v8si) __B,
	499	(__mmask8) -1);
	500	}
	501
	502	static __inline__ __m128i __DEFAULT_FN_ATTRS
	503	_mm128_mask_shldv_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	504	{
	505	return (__m128i) __builtin_ia32_vpshldvd128_mask ((__v4si) __S,
	506	(__v4si) __A,
	507	(__v4si) __B,
	508	__U);
	509	}
	510
	511	static __inline__ __m128i __DEFAULT_FN_ATTRS
	512	_mm128_maskz_shldv_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	513	{
	514	return (__m128i) __builtin_ia32_vpshldvd128_maskz ((__v4si) __S,
	515	(__v4si) __A,
	516	(__v4si) __B,
	517	__U);
	518	}
	519
	520	static __inline__ __m128i __DEFAULT_FN_ATTRS
	521	_mm128_shldv_epi32(__m128i __S, __m128i __A, __m128i __B)
	522	{
	523	return (__m128i) __builtin_ia32_vpshldvd128_mask ((__v4si) __S,
	524	(__v4si) __A,
	525	(__v4si) __B,
	526	(__mmask8) -1);
	527	}
	528
	529	static __inline__ __m256i __DEFAULT_FN_ATTRS
	530	_mm256_mask_shldv_epi16(__m256i __S, __mmask16 __U, __m256i __A, __m256i __B)
	531	{
	532	return (__m256i) __builtin_ia32_vpshldvw256_mask ((__v16hi) __S,
	533	(__v16hi) __A,
	534	(__v16hi) __B,
	535	__U);
	536	}
	537
	538	static __inline__ __m256i __DEFAULT_FN_ATTRS
	539	_mm256_maskz_shldv_epi16(__mmask16 __U, __m256i __S, __m256i __A, __m256i __B)
	540	{
	541	return (__m256i) __builtin_ia32_vpshldvw256_maskz ((__v16hi) __S,
	542	(__v16hi) __A,
	543	(__v16hi) __B,
	544	__U);
	545	}
	546
	547	static __inline__ __m256i __DEFAULT_FN_ATTRS
	548	_mm256_shldv_epi16(__m256i __S, __m256i __A, __m256i __B)
	549	{
	550	return (__m256i) __builtin_ia32_vpshldvw256_mask ((__v16hi) __S,
	551	(__v16hi) __A,
	552	(__v16hi) __B,
	553	(__mmask16) -1);
	554	}
	555
	556	static __inline__ __m128i __DEFAULT_FN_ATTRS
	557	_mm128_mask_shldv_epi16(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	558	{
	559	return (__m128i) __builtin_ia32_vpshldvw128_mask ((__v8hi) __S,
	560	(__v8hi) __A,
	561	(__v8hi) __B,
	562	__U);
	563	}
	564
	565	static __inline__ __m128i __DEFAULT_FN_ATTRS
	566	_mm128_maskz_shldv_epi16(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	567	{
	568	return (__m128i) __builtin_ia32_vpshldvw128_maskz ((__v8hi) __S,
	569	(__v8hi) __A,
	570	(__v8hi) __B,
	571	__U);
	572	}
	573
	574	static __inline__ __m128i __DEFAULT_FN_ATTRS
	575	_mm128_shldv_epi16(__m128i __S, __m128i __A, __m128i __B)
	576	{
	577	return (__m128i) __builtin_ia32_vpshldvw128_mask ((__v8hi) __S,
	578	(__v8hi) __A,
	579	(__v8hi) __B,
	580	(__mmask8) -1);
	581	}
	582
	583	static __inline__ __m256i __DEFAULT_FN_ATTRS
	584	_mm256_mask_shrdv_epi64(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	585	{
	586	return (__m256i) __builtin_ia32_vpshrdvq256_mask ((__v4di) __S,
	587	(__v4di) __A,
	588	(__v4di) __B,
	589	__U);
	590	}
	591
	592	static __inline__ __m256i __DEFAULT_FN_ATTRS
	593	_mm256_maskz_shrdv_epi64(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	594	{
	595	return (__m256i) __builtin_ia32_vpshrdvq256_maskz ((__v4di) __S,
	596	(__v4di) __A,
	597	(__v4di) __B,
	598	__U);
	599	}
	600
	601	static __inline__ __m256i __DEFAULT_FN_ATTRS
	602	_mm256_shrdv_epi64(__m256i __S, __m256i __A, __m256i __B)
	603	{
	604	return (__m256i) __builtin_ia32_vpshrdvq256_mask ((__v4di) __S,
	605	(__v4di) __A,
	606	(__v4di) __B,
	607	(__mmask8) -1);
	608	}
	609
	610	static __inline__ __m128i __DEFAULT_FN_ATTRS
	611	_mm128_mask_shrdv_epi64(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	612	{
	613	return (__m128i) __builtin_ia32_vpshrdvq128_mask ((__v2di) __S,
	614	(__v2di) __A,
	615	(__v2di) __B,
	616	__U);
	617	}
	618
	619	static __inline__ __m128i __DEFAULT_FN_ATTRS
	620	_mm128_maskz_shrdv_epi64(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	621	{
	622	return (__m128i) __builtin_ia32_vpshrdvq128_maskz ((__v2di) __S,
	623	(__v2di) __A,
	624	(__v2di) __B,
	625	__U);
	626	}
	627
	628	static __inline__ __m128i __DEFAULT_FN_ATTRS
	629	_mm128_shrdv_epi64(__m128i __S, __m128i __A, __m128i __B)
	630	{
	631	return (__m128i) __builtin_ia32_vpshrdvq128_mask ((__v2di) __S,
	632	(__v2di) __A,
	633	(__v2di) __B,
	634	(__mmask8) -1);
	635	}
	636
	637	static __inline__ __m256i __DEFAULT_FN_ATTRS
	638	_mm256_mask_shrdv_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	639	{
	640	return (__m256i) __builtin_ia32_vpshrdvd256_mask ((__v8si) __S,
	641	(__v8si) __A,
	642	(__v8si) __B,
	643	__U);
	644	}
	645
	646	static __inline__ __m256i __DEFAULT_FN_ATTRS
	647	_mm256_maskz_shrdv_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	648	{
	649	return (__m256i) __builtin_ia32_vpshrdvd256_maskz ((__v8si) __S,
	650	(__v8si) __A,
	651	(__v8si) __B,
	652	__U);
	653	}
	654
	655	static __inline__ __m256i __DEFAULT_FN_ATTRS
	656	_mm256_shrdv_epi32(__m256i __S, __m256i __A, __m256i __B)
	657	{
	658	return (__m256i) __builtin_ia32_vpshrdvd256_mask ((__v8si) __S,
	659	(__v8si) __A,
	660	(__v8si) __B,
	661	(__mmask8) -1);
	662	}
	663
	664	static __inline__ __m128i __DEFAULT_FN_ATTRS
	665	_mm128_mask_shrdv_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	666	{
	667	return (__m128i) __builtin_ia32_vpshrdvd128_mask ((__v4si) __S,
	668	(__v4si) __A,
	669	(__v4si) __B,
	670	__U);
	671	}
	672
	673	static __inline__ __m128i __DEFAULT_FN_ATTRS
	674	_mm128_maskz_shrdv_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	675	{
	676	return (__m128i) __builtin_ia32_vpshrdvd128_maskz ((__v4si) __S,
	677	(__v4si) __A,
	678	(__v4si) __B,
	679	__U);
	680	}
	681
	682	static __inline__ __m128i __DEFAULT_FN_ATTRS
	683	_mm128_shrdv_epi32(__m128i __S, __m128i __A, __m128i __B)
	684	{
	685	return (__m128i) __builtin_ia32_vpshrdvd128_mask ((__v4si) __S,
	686	(__v4si) __A,
	687	(__v4si) __B,
	688	(__mmask8) -1);
	689	}
	690
	691	static __inline__ __m256i __DEFAULT_FN_ATTRS
	692	_mm256_mask_shrdv_epi16(__m256i __S, __mmask16 __U, __m256i __A, __m256i __B)
	693	{
	694	return (__m256i) __builtin_ia32_vpshrdvw256_mask ((__v16hi) __S,
	695	(__v16hi) __A,
	696	(__v16hi) __B,
	697	__U);
	698	}
	699
	700	static __inline__ __m256i __DEFAULT_FN_ATTRS
	701	_mm256_maskz_shrdv_epi16(__mmask16 __U, __m256i __S, __m256i __A, __m256i __B)
	702	{
	703	return (__m256i) __builtin_ia32_vpshrdvw256_maskz ((__v16hi) __S,
	704	(__v16hi) __A,
	705	(__v16hi) __B,
	706	__U);
	707	}
	708
	709	static __inline__ __m256i __DEFAULT_FN_ATTRS
	710	_mm256_shrdv_epi16(__m256i __S, __m256i __A, __m256i __B)
	711	{
	712	return (__m256i) __builtin_ia32_vpshrdvw256_mask ((__v16hi) __S,
	713	(__v16hi) __A,
	714	(__v16hi) __B,
	715	(__mmask16) -1);
	716	}
	717
	718	static __inline__ __m128i __DEFAULT_FN_ATTRS
	719	_mm128_mask_shrdv_epi16(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	720	{
	721	return (__m128i) __builtin_ia32_vpshrdvw128_mask ((__v8hi) __S,
	722	(__v8hi) __A,
	723	(__v8hi) __B,
	724	__U);
	725	}
	726
	727	static __inline__ __m128i __DEFAULT_FN_ATTRS
	728	_mm128_maskz_shrdv_epi16(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	729	{
	730	return (__m128i) __builtin_ia32_vpshrdvw128_maskz ((__v8hi) __S,
	731	(__v8hi) __A,
	732	(__v8hi) __B,
	733	__U);
	734	}
	735
	736	static __inline__ __m128i __DEFAULT_FN_ATTRS
	737	_mm128_shrdv_epi16(__m128i __S, __m128i __A, __m128i __B)
	738	{
	739	return (__m128i) __builtin_ia32_vpshrdvw128_mask ((__v8hi) __S,
	740	(__v8hi) __A,
	741	(__v8hi) __B,
	742	(__mmask8) -1);
	743	}
	744
	745
	746	#undef __DEFAULT_FN_ATTRS
	747
	748	#endif

c_headers/avx512vlvnniintrin.h created+254

...	...	@@ -0,0 +1,254 @@
	1	/*===------------- avx512vlvnniintrin.h - VNNI intrinsics ------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <avx512vlvnniintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __AVX512VLVNNIINTRIN_H
	29	#define __AVX512VLVNNIINTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vnni")))
	33
	34
	35	static __inline__ __m256i __DEFAULT_FN_ATTRS
	36	_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	37	{
	38	return (__m256i) __builtin_ia32_vpdpbusd256_mask ((__v8si) __S,
	39	(__v8si) __A,
	40	(__v8si) __B,
	41	(__mmask8) __U);
	42	}
	43
	44	static __inline__ __m256i __DEFAULT_FN_ATTRS
	45	_mm256_maskz_dpbusd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	46	{
	47	return (__m256i) __builtin_ia32_vpdpbusd256_maskz ((__v8si) __S,
	48	(__v8si) __A,
	49	(__v8si) __B,
	50	(__mmask8) __U);
	51	}
	52
	53	static __inline__ __m256i __DEFAULT_FN_ATTRS
	54	_mm256_dpbusd_epi32(__m256i __S, __m256i __A, __m256i __B)
	55	{
	56	return (__m256i) __builtin_ia32_vpdpbusd256_mask ((__v8si) __S,
	57	(__v8si) __A,
	58	(__v8si) __B,
	59	(__mmask8) -1);
	60	}
	61
	62	static __inline__ __m256i __DEFAULT_FN_ATTRS
	63	_mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	64	{
	65	return (__m256i) __builtin_ia32_vpdpbusds256_mask ((__v8si) __S,
	66	(__v8si) __A,
	67	(__v8si) __B,
	68	(__mmask8) __U);
	69	}
	70
	71	static __inline__ __m256i __DEFAULT_FN_ATTRS
	72	_mm256_maskz_dpbusds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	73	{
	74	return (__m256i) __builtin_ia32_vpdpbusds256_maskz ((__v8si) __S,
	75	(__v8si) __A,
	76	(__v8si) __B,
	77	(__mmask8) __U);
	78	}
	79
	80	static __inline__ __m256i __DEFAULT_FN_ATTRS
	81	_mm256_dpbusds_epi32(__m256i __S, __m256i __A, __m256i __B)
	82	{
	83	return (__m256i) __builtin_ia32_vpdpbusds256_mask ((__v8si) __S,
	84	(__v8si) __A,
	85	(__v8si) __B,
	86	(__mmask8) -1);
	87	}
	88
	89	static __inline__ __m256i __DEFAULT_FN_ATTRS
	90	_mm256_mask_dpwssd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	91	{
	92	return (__m256i) __builtin_ia32_vpdpwssd256_mask ((__v8si) __S,
	93	(__v8si) __A,
	94	(__v8si) __B,
	95	(__mmask8) __U);
	96	}
	97
	98	static __inline__ __m256i __DEFAULT_FN_ATTRS
	99	_mm256_maskz_dpwssd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	100	{
	101	return (__m256i) __builtin_ia32_vpdpwssd256_maskz ((__v8si) __S,
	102	(__v8si) __A,
	103	(__v8si) __B,
	104	(__mmask8) __U);
	105	}
	106
	107	static __inline__ __m256i __DEFAULT_FN_ATTRS
	108	_mm256_dpwssd_epi32(__m256i __S, __m256i __A, __m256i __B)
	109	{
	110	return (__m256i) __builtin_ia32_vpdpwssd256_mask ((__v8si) __S,
	111	(__v8si) __A,
	112	(__v8si) __B,
	113	(__mmask8) -1);
	114	}
	115
	116	static __inline__ __m256i __DEFAULT_FN_ATTRS
	117	_mm256_mask_dpwssds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
	118	{
	119	return (__m256i) __builtin_ia32_vpdpwssds256_mask ((__v8si) __S,
	120	(__v8si) __A,
	121	(__v8si) __B,
	122	(__mmask8) __U);
	123	}
	124
	125	static __inline__ __m256i __DEFAULT_FN_ATTRS
	126	_mm256_maskz_dpwssds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
	127	{
	128	return (__m256i) __builtin_ia32_vpdpwssds256_maskz ((__v8si) __S,
	129	(__v8si) __A,
	130	(__v8si) __B,
	131	(__mmask8) __U);
	132	}
	133
	134	static __inline__ __m256i __DEFAULT_FN_ATTRS
	135	_mm256_dpwssds_epi32(__m256i __S, __m256i __A, __m256i __B)
	136	{
	137	return (__m256i) __builtin_ia32_vpdpwssds256_mask ((__v8si) __S,
	138	(__v8si) __A,
	139	(__v8si) __B,
	140	(__mmask8) -1);
	141	}
	142
	143	static __inline__ __m128i __DEFAULT_FN_ATTRS
	144	_mm128_mask_dpbusd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	145	{
	146	return (__m128i) __builtin_ia32_vpdpbusd128_mask ((__v4si) __S,
	147	(__v4si) __A,
	148	(__v4si) __B,
	149	(__mmask8) __U);
	150	}
	151
	152	static __inline__ __m128i __DEFAULT_FN_ATTRS
	153	_mm128_maskz_dpbusd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	154	{
	155	return (__m128i) __builtin_ia32_vpdpbusd128_maskz ((__v4si) __S,
	156	(__v4si) __A,
	157	(__v4si) __B,
	158	(__mmask8) __U);
	159	}
	160
	161	static __inline__ __m128i __DEFAULT_FN_ATTRS
	162	_mm128_dpbusd_epi32(__m128i __S, __m128i __A, __m128i __B)
	163	{
	164	return (__m128i) __builtin_ia32_vpdpbusd128_mask ((__v4si) __S,
	165	(__v4si) __A,
	166	(__v4si) __B,
	167	(__mmask8) -1);
	168	}
	169
	170	static __inline__ __m128i __DEFAULT_FN_ATTRS
	171	_mm128_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	172	{
	173	return (__m128i) __builtin_ia32_vpdpbusds128_mask ((__v4si) __S,
	174	(__v4si) __A,
	175	(__v4si) __B,
	176	(__mmask8) __U);
	177	}
	178
	179	static __inline__ __m128i __DEFAULT_FN_ATTRS
	180	_mm128_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	181	{
	182	return (__m128i) __builtin_ia32_vpdpbusds128_maskz ((__v4si) __S,
	183	(__v4si) __A,
	184	(__v4si) __B,
	185	(__mmask8) __U);
	186	}
	187
	188	static __inline__ __m128i __DEFAULT_FN_ATTRS
	189	_mm128_dpbusds_epi32(__m128i __S, __m128i __A, __m128i __B)
	190	{
	191	return (__m128i) __builtin_ia32_vpdpbusds128_mask ((__v4si) __S,
	192	(__v4si) __A,
	193	(__v4si) __B,
	194	(__mmask8) -1);
	195	}
	196
	197	static __inline__ __m128i __DEFAULT_FN_ATTRS
	198	_mm128_mask_dpwssd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	199	{
	200	return (__m128i) __builtin_ia32_vpdpwssd128_mask ((__v4si) __S,
	201	(__v4si) __A,
	202	(__v4si) __B,
	203	(__mmask8) __U);
	204	}
	205
	206	static __inline__ __m128i __DEFAULT_FN_ATTRS
	207	_mm128_maskz_dpwssd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	208	{
	209	return (__m128i) __builtin_ia32_vpdpwssd128_maskz ((__v4si) __S,
	210	(__v4si) __A,
	211	(__v4si) __B,
	212	(__mmask8) __U);
	213	}
	214
	215	static __inline__ __m128i __DEFAULT_FN_ATTRS
	216	_mm128_dpwssd_epi32(__m128i __S, __m128i __A, __m128i __B)
	217	{
	218	return (__m128i) __builtin_ia32_vpdpwssd128_mask ((__v4si) __S,
	219	(__v4si) __A,
	220	(__v4si) __B,
	221	(__mmask8) -1);
	222	}
	223
	224	static __inline__ __m128i __DEFAULT_FN_ATTRS
	225	_mm128_mask_dpwssds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
	226	{
	227	return (__m128i) __builtin_ia32_vpdpwssds128_mask ((__v4si) __S,
	228	(__v4si) __A,
	229	(__v4si) __B,
	230	(__mmask8) __U);
	231	}
	232
	233	static __inline__ __m128i __DEFAULT_FN_ATTRS
	234	_mm128_maskz_dpwssds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
	235	{
	236	return (__m128i) __builtin_ia32_vpdpwssds128_maskz ((__v4si) __S,
	237	(__v4si) __A,
	238	(__v4si) __B,
	239	(__mmask8) __U);
	240	}
	241
	242	static __inline__ __m128i __DEFAULT_FN_ATTRS
	243	_mm128_dpwssds_epi32(__m128i __S, __m128i __A, __m128i __B)
	244	{
	245	return (__m128i) __builtin_ia32_vpdpwssds128_mask ((__v4si) __S,
	246	(__v4si) __A,
	247	(__v4si) __B,
	248	(__mmask8) -1);
	249	}
	250
	251
	252	#undef __DEFAULT_FN_ATTRS
	253
	254	#endif

c_headers/avx512vnniintrin.h created+146

...	...	@@ -0,0 +1,146 @@
	1	/*===------------- avx512vnniintrin.h - VNNI intrinsics ------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <avx512vnniintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __AVX512VNNIINTRIN_H
	29	#define __AVX512VNNIINTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vnni")))
	33
	34
	35	static __inline__ __m512i __DEFAULT_FN_ATTRS
	36	_mm512_mask_dpbusd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
	37	{
	38	return (__m512i) __builtin_ia32_vpdpbusd512_mask ((__v16si) __S,
	39	(__v16si) __A,
	40	(__v16si) __B,
	41	(__mmask16) __U);
	42	}
	43
	44	static __inline__ __m512i __DEFAULT_FN_ATTRS
	45	_mm512_maskz_dpbusd_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
	46	{
	47	return (__m512i) __builtin_ia32_vpdpbusd512_maskz ((__v16si) __S,
	48	(__v16si) __A,
	49	(__v16si) __B,
	50	(__mmask16) __U);
	51	}
	52
	53	static __inline__ __m512i __DEFAULT_FN_ATTRS
	54	_mm512_dpbusd_epi32(__m512i __S, __m512i __A, __m512i __B)
	55	{
	56	return (__m512i) __builtin_ia32_vpdpbusd512_mask ((__v16si) __S,
	57	(__v16si) __A,
	58	(__v16si) __B,
	59	(__mmask16) -1);
	60	}
	61
	62	static __inline__ __m512i __DEFAULT_FN_ATTRS
	63	_mm512_mask_dpbusds_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
	64	{
	65	return (__m512i) __builtin_ia32_vpdpbusds512_mask ((__v16si) __S,
	66	(__v16si) __A,
	67	(__v16si) __B,
	68	(__mmask16) __U);
	69	}
	70
	71	static __inline__ __m512i __DEFAULT_FN_ATTRS
	72	_mm512_maskz_dpbusds_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
	73	{
	74	return (__m512i) __builtin_ia32_vpdpbusds512_maskz ((__v16si) __S,
	75	(__v16si) __A,
	76	(__v16si) __B,
	77	(__mmask16) __U);
	78	}
	79
	80	static __inline__ __m512i __DEFAULT_FN_ATTRS
	81	_mm512_dpbusds_epi32(__m512i __S, __m512i __A, __m512i __B)
	82	{
	83	return (__m512i) __builtin_ia32_vpdpbusds512_mask ((__v16si) __S,
	84	(__v16si) __A,
	85	(__v16si) __B,
	86	(__mmask16) -1);
	87	}
	88
	89	static __inline__ __m512i __DEFAULT_FN_ATTRS
	90	_mm512_mask_dpwssd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
	91	{
	92	return (__m512i) __builtin_ia32_vpdpwssd512_mask ((__v16si) __S,
	93	(__v16si) __A,
	94	(__v16si) __B,
	95	(__mmask16) __U);
	96	}
	97
	98	static __inline__ __m512i __DEFAULT_FN_ATTRS
	99	_mm512_maskz_dpwssd_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
	100	{
	101	return (__m512i) __builtin_ia32_vpdpwssd512_maskz ((__v16si) __S,
	102	(__v16si) __A,
	103	(__v16si) __B,
	104	(__mmask16) __U);
	105	}
	106
	107	static __inline__ __m512i __DEFAULT_FN_ATTRS
	108	_mm512_dpwssd_epi32(__m512i __S, __m512i __A, __m512i __B)
	109	{
	110	return (__m512i) __builtin_ia32_vpdpwssd512_mask ((__v16si) __S,
	111	(__v16si) __A,
	112	(__v16si) __B,
	113	(__mmask16) -1);
	114	}
	115
	116	static __inline__ __m512i __DEFAULT_FN_ATTRS
	117	_mm512_mask_dpwssds_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
	118	{
	119	return (__m512i) __builtin_ia32_vpdpwssds512_mask ((__v16si) __S,
	120	(__v16si) __A,
	121	(__v16si) __B,
	122	(__mmask16) __U);
	123	}
	124
	125	static __inline__ __m512i __DEFAULT_FN_ATTRS
	126	_mm512_maskz_dpwssds_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
	127	{
	128	return (__m512i) __builtin_ia32_vpdpwssds512_maskz ((__v16si) __S,
	129	(__v16si) __A,
	130	(__v16si) __B,
	131	(__mmask16) __U);
	132	}
	133
	134	static __inline__ __m512i __DEFAULT_FN_ATTRS
	135	_mm512_dpwssds_epi32(__m512i __S, __m512i __A, __m512i __B)
	136	{
	137	return (__m512i) __builtin_ia32_vpdpwssds512_mask ((__v16si) __S,
	138	(__v16si) __A,
	139	(__v16si) __B,
	140	(__mmask16) -1);
	141	}
	142
	143
	144	#undef __DEFAULT_FN_ATTRS
	145
	146	#endif

c_headers/avx512vpopcntdqvlintrin.h created+99

...	...	@@ -0,0 +1,99 @@
	1	/*===------------- avx512vpopcntdqintrin.h - AVX512VPOPCNTDQ intrinsics
	2	*------------------===
	3	*
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a copy
	6	* of this software and associated documentation files (the "Software"), to deal
	7	* in the Software without restriction, including without limitation the rights
	8	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	9	* copies of the Software, and to permit persons to whom the Software is
	10	* furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice shall be included in
	13	* all copies or substantial portions of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	18	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	21	* THE SOFTWARE.
	22	*
	23	*===-----------------------------------------------------------------------===
	24	*/
	25	#ifndef __IMMINTRIN_H
	26	#error \
	27	"Never use <avx512vpopcntdqvlintrin.h> directly; include <immintrin.h> instead."
	28	#endif
	29
	30	#ifndef __AVX512VPOPCNTDQVLINTRIN_H
	31	#define __AVX512VPOPCNTDQVLINTRIN_H
	32
	33	/* Define the default attributes for the functions in this file. */
	34	#define __DEFAULT_FN_ATTRS \
	35	__attribute__((__always_inline__, __nodebug__, __target__("avx512vpopcntdq,avx512vl")))
	36
	37	static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_popcnt_epi64(__m128i __A) {
	38	return (__m128i)__builtin_ia32_vpopcntq_128((__v2di)__A);
	39	}
	40
	41	static __inline__ __m128i __DEFAULT_FN_ATTRS
	42	_mm_mask_popcnt_epi64(__m128i __W, __mmask8 __U, __m128i __A) {
	43	return (__m128i)__builtin_ia32_selectq_128(
	44	(__mmask8)__U, (__v2di)_mm_popcnt_epi64(__A), (__v2di)__W);
	45	}
	46
	47	static __inline__ __m128i __DEFAULT_FN_ATTRS
	48	_mm_maskz_popcnt_epi64(__mmask8 __U, __m128i __A) {
	49	return _mm_mask_popcnt_epi64((__m128i)_mm_setzero_si128(), __U, __A);
	50	}
	51
	52	static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_popcnt_epi32(__m128i __A) {
	53	return (__m128i)__builtin_ia32_vpopcntd_128((__v4si)__A);
	54	}
	55
	56	static __inline__ __m128i __DEFAULT_FN_ATTRS
	57	_mm_mask_popcnt_epi32(__m128i __W, __mmask8 __U, __m128i __A) {
	58	return (__m128i)__builtin_ia32_selectd_128(
	59	(__mmask8)__U, (__v4si)_mm_popcnt_epi32(__A), (__v4si)__W);
	60	}
	61
	62	static __inline__ __m128i __DEFAULT_FN_ATTRS
	63	_mm_maskz_popcnt_epi32(__mmask8 __U, __m128i __A) {
	64	return _mm_mask_popcnt_epi32((__m128i)_mm_setzero_si128(), __U, __A);
	65	}
	66
	67	static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_popcnt_epi64(__m256i __A) {
	68	return (__m256i)__builtin_ia32_vpopcntq_256((__v4di)__A);
	69	}
	70
	71	static __inline__ __m256i __DEFAULT_FN_ATTRS
	72	_mm256_mask_popcnt_epi64(__m256i __W, __mmask8 __U, __m256i __A) {
	73	return (__m256i)__builtin_ia32_selectq_256(
	74	(__mmask8)__U, (__v4di)_mm256_popcnt_epi64(__A), (__v4di)__W);
	75	}
	76
	77	static __inline__ __m256i __DEFAULT_FN_ATTRS
	78	_mm256_maskz_popcnt_epi64(__mmask8 __U, __m256i __A) {
	79	return _mm256_mask_popcnt_epi64((__m256i)_mm256_setzero_si256(), __U, __A);
	80	}
	81
	82	static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_popcnt_epi32(__m256i __A) {
	83	return (__m256i)__builtin_ia32_vpopcntd_256((__v8si)__A);
	84	}
	85
	86	static __inline__ __m256i __DEFAULT_FN_ATTRS
	87	_mm256_mask_popcnt_epi32(__m256i __W, __mmask8 __U, __m256i __A) {
	88	return (__m256i)__builtin_ia32_selectd_256(
	89	(__mmask8)__U, (__v8si)_mm256_popcnt_epi32(__A), (__v8si)__W);
	90	}
	91
	92	static __inline__ __m256i __DEFAULT_FN_ATTRS
	93	_mm256_maskz_popcnt_epi32(__mmask8 __U, __m256i __A) {
	94	return _mm256_mask_popcnt_epi32((__m256i)_mm256_setzero_si256(), __U, __A);
	95	}
	96
	97	#undef __DEFAULT_FN_ATTRS
	98
	99	#endif

c_headers/cetintrin.h created+93

...	...	@@ -0,0 +1,93 @@
	1	/*===---- cetintrin.h - CET intrinsic ------------------------------------===
	2	*
	3	* Permission is hereby granted, free of charge, to any person obtaining a copy
	4	* of this software and associated documentation files (the "Software"), to deal
	5	* in the Software without restriction, including without limitation the rights
	6	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	7	* copies of the Software, and to permit persons to whom the Software is
	8	* furnished to do so, subject to the following conditions:
	9	*
	10	* The above copyright notice and this permission notice shall be included in
	11	* all copies or substantial portions of the Software.
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	16	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	17	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	18	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	19	* THE SOFTWARE.
	20	*
	21	*===-----------------------------------------------------------------------===
	22	*/
	23
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <cetintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __CETINTRIN_H
	29	#define __CETINTRIN_H
	30
	31	/* Define the default attributes for the functions in this file. */
	32	#define __DEFAULT_FN_ATTRS \
	33	__attribute__((__always_inline__, __nodebug__, __target__("shstk")))
	34
	35	static __inline__ void __DEFAULT_FN_ATTRS _incsspd(int __a) {
	36	__builtin_ia32_incsspd(__a);
	37	}
	38
	39	#ifdef __x86_64__
	40	static __inline__ void __DEFAULT_FN_ATTRS _incsspq(unsigned long long __a) {
	41	__builtin_ia32_incsspq(__a);
	42	}
	43	#endif /* __x86_64__ */
	44
	45	static __inline__ unsigned int __DEFAULT_FN_ATTRS _rdsspd(unsigned int __a) {
	46	return __builtin_ia32_rdsspd(__a);
	47	}
	48
	49	#ifdef __x86_64__
	50	static __inline__ unsigned long long __DEFAULT_FN_ATTRS _rdsspq(unsigned long long __a) {
	51	return __builtin_ia32_rdsspq(__a);
	52	}
	53	#endif /* __x86_64__ */
	54
	55	static __inline__ void __DEFAULT_FN_ATTRS _saveprevssp() {
	56	__builtin_ia32_saveprevssp();
	57	}
	58
	59	static __inline__ void __DEFAULT_FN_ATTRS _rstorssp(void * __p) {
	60	__builtin_ia32_rstorssp(__p);
	61	}
	62
	63	static __inline__ void __DEFAULT_FN_ATTRS _wrssd(unsigned int __a, void * __p) {
	64	__builtin_ia32_wrssd(__a, __p);
	65	}
	66
	67	#ifdef __x86_64__
	68	static __inline__ void __DEFAULT_FN_ATTRS _wrssq(unsigned long long __a, void * __p) {
	69	__builtin_ia32_wrssq(__a, __p);
	70	}
	71	#endif /* __x86_64__ */
	72
	73	static __inline__ void __DEFAULT_FN_ATTRS _wrussd(unsigned int __a, void * __p) {
	74	__builtin_ia32_wrussd(__a, __p);
	75	}
	76
	77	#ifdef __x86_64__
	78	static __inline__ void __DEFAULT_FN_ATTRS _wrussq(unsigned long long __a, void * __p) {
	79	__builtin_ia32_wrussq(__a, __p);
	80	}
	81	#endif /* __x86_64__ */
	82
	83	static __inline__ void __DEFAULT_FN_ATTRS _setssbsy() {
	84	__builtin_ia32_setssbsy();
	85	}
	86
	87	static __inline__ void __DEFAULT_FN_ATTRS _clrssbsy(void * __p) {
	88	__builtin_ia32_clrssbsy(__p);
	89	}
	90
	91	#undef __DEFAULT_FN_ATTRS
	92
	93	#endif /* __CETINTRIN_H */

c_headers/cpuid.h+14-5

...	...	@@ -173,16 +173,24 @@
173	173	#define bit_AVX512VL 0x80000000
174	174
175	175	/* Features in %ecx for leaf 7 sub-leaf 0 */
176		#define bit_PREFTCHWT1 0x00000001
177		#define bit_AVX512VBMI 0x00000002
178		#define bit_PKU 0x00000004
179		#define bit_OSPKE 0x00000010
	176	#define bit_PREFTCHWT1 0x00000001
	177	#define bit_AVX512VBMI 0x00000002
	178	#define bit_PKU 0x00000004
	179	#define bit_OSPKE 0x00000010
	180	#define bit_AVX512VBMI2 0x00000040
	181	#define bit_SHSTK 0x00000080
	182	#define bit_GFNI 0x00000100
	183	#define bit_VAES 0x00000200
	184	#define bit_VPCLMULQDQ 0x00000400
	185	#define bit_AVX512VNNI 0x00000800
	186	#define bit_AVX512BITALG 0x00001000
180	187	#define bit_AVX512VPOPCNTDQ 0x00004000
181		#define bit_RDPID 0x00400000
	188	#define bit_RDPID 0x00400000
182	189
183	190	/* Features in %edx for leaf 7 sub-leaf 0 */
184	191	#define bit_AVX5124VNNIW 0x00000004
185	192	#define bit_AVX5124FMAPS 0x00000008
	193	#define bit_IBT 0x00100000
186	194
187	195	/* Features in %eax for leaf 13 sub-leaf 1 */
188	196	#define bit_XSAVEOPT 0x00000001
...	...	@@ -192,6 +200,7 @@
192	200	/* Features in %ecx for leaf 0x80000001 */
193	201	#define bit_LAHF_LM 0x00000001
194	202	#define bit_ABM 0x00000020
	203	#define bit_LZCNT bit_ABM /* for gcc compat */
195	204	#define bit_SSE4a 0x00000040
196	205	#define bit_PRFCHW 0x00000100
197	206	#define bit_XOP 0x00000800

c_headers/cuda_wrappers/algorithm+1-1

...	...	@@ -80,7 +80,7 @@ min(const __T &__a, const __T &__b, __Cmp __cmp) {
80	80	template <class __T>
81	81	inline __device__ const __T &
82	82	min(const __T &__a, const __T &__b) {
83		return __a < __b ? __b : __a;
	83	return __a < __b ? __a : __b;
84	84	}
85	85
86	86	#ifdef _LIBCPP_END_NAMESPACE_STD

c_headers/emmintrin.h+63-48

...	...	@@ -217,8 +217,8 @@ _mm_div_pd(__m128d __a, __m128d __b)
217	217
218	218	/// \brief Calculates the square root of the lower double-precision value of
219	219	/// the second operand and returns it in the lower 64 bits of the result.
220		/// The upper 64 bits of the result are copied from the upper double-
221		/// precision value of the first operand.
	220	/// The upper 64 bits of the result are copied from the upper
	221	/// double-precision value of the first operand.
222	222	///
223	223	/// \headerfile <x86intrin.h>
224	224	///
...	...	@@ -260,8 +260,8 @@ _mm_sqrt_pd(__m128d __a)
260	260
261	261	/// \brief Compares lower 64-bit double-precision values of both operands, and
262	262	/// returns the lesser of the pair of values in the lower 64-bits of the
263		/// result. The upper 64 bits of the result are copied from the upper double-
264		/// precision value of the first operand.
	263	/// result. The upper 64 bits of the result are copied from the upper
	264	/// double-precision value of the first operand.
265	265	///
266	266	/// \headerfile <x86intrin.h>
267	267	///
...	...	@@ -304,8 +304,8 @@ _mm_min_pd(__m128d __a, __m128d __b)
304	304
305	305	/// \brief Compares lower 64-bit double-precision values of both operands, and
306	306	/// returns the greater of the pair of values in the lower 64-bits of the
307		/// result. The upper 64 bits of the result are copied from the upper double-
308		/// precision value of the first operand.
	307	/// result. The upper 64 bits of the result are copied from the upper
	308	/// double-precision value of the first operand.
309	309	///
310	310	/// \headerfile <x86intrin.h>
311	311	///
...	...	@@ -983,8 +983,10 @@ _mm_cmpnge_sd(__m128d __a, __m128d __b)
983	983	}
984	984
985	985	/// \brief Compares the lower double-precision floating-point values in each of
986		/// the two 128-bit floating-point vectors of [2 x double] for equality. The
987		/// comparison yields 0 for false, 1 for true.
	986	/// the two 128-bit floating-point vectors of [2 x double] for equality.
	987	///
	988	/// The comparison yields 0 for false, 1 for true. If either of the two
	989	/// lower double-precision values is NaN, 0 is returned.
988	990	///
989	991	/// \headerfile <x86intrin.h>
990	992	///
...	...	@@ -996,7 +998,8 @@ _mm_cmpnge_sd(__m128d __a, __m128d __b)
996	998	/// \param __b
997	999	/// A 128-bit vector of [2 x double]. The lower double-precision value is
998	1000	/// compared to the lower double-precision value of \a __a.
999		/// \returns An integer containing the comparison results.
	1001	/// \returns An integer containing the comparison results. If either of the two
	1002	/// lower double-precision values is NaN, 0 is returned.
1000	1003	static __inline__ int __DEFAULT_FN_ATTRS
1001	1004	_mm_comieq_sd(__m128d __a, __m128d __b)
1002	1005	{
...	...	@@ -1008,7 +1011,8 @@ _mm_comieq_sd(__m128d __a, __m128d __b)
1008	1011	/// the value in the first parameter is less than the corresponding value in
1009	1012	/// the second parameter.
1010	1013	///
1011		/// The comparison yields 0 for false, 1 for true.
	1014	/// The comparison yields 0 for false, 1 for true. If either of the two
	1015	/// lower double-precision values is NaN, 0 is returned.
1012	1016	///
1013	1017	/// \headerfile <x86intrin.h>
1014	1018	///
...	...	@@ -1020,7 +1024,8 @@ _mm_comieq_sd(__m128d __a, __m128d __b)
1020	1024	/// \param __b
1021	1025	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1022	1026	/// compared to the lower double-precision value of \a __a.
1023		/// \returns An integer containing the comparison results.
	1027	/// \returns An integer containing the comparison results. If either of the two
	1028	/// lower double-precision values is NaN, 0 is returned.
1024	1029	static __inline__ int __DEFAULT_FN_ATTRS
1025	1030	_mm_comilt_sd(__m128d __a, __m128d __b)
1026	1031	{
...	...	@@ -1032,7 +1037,8 @@ _mm_comilt_sd(__m128d __a, __m128d __b)
1032	1037	/// the value in the first parameter is less than or equal to the
1033	1038	/// corresponding value in the second parameter.
1034	1039	///
1035		/// The comparison yields 0 for false, 1 for true.
	1040	/// The comparison yields 0 for false, 1 for true. If either of the two
	1041	/// lower double-precision values is NaN, 0 is returned.
1036	1042	///
1037	1043	/// \headerfile <x86intrin.h>
1038	1044	///
...	...	@@ -1044,7 +1050,8 @@ _mm_comilt_sd(__m128d __a, __m128d __b)
1044	1050	/// \param __b
1045	1051	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1046	1052	/// compared to the lower double-precision value of \a __a.
1047		/// \returns An integer containing the comparison results.
	1053	/// \returns An integer containing the comparison results. If either of the two
	1054	/// lower double-precision values is NaN, 0 is returned.
1048	1055	static __inline__ int __DEFAULT_FN_ATTRS
1049	1056	_mm_comile_sd(__m128d __a, __m128d __b)
1050	1057	{
...	...	@@ -1056,7 +1063,8 @@ _mm_comile_sd(__m128d __a, __m128d __b)
1056	1063	/// the value in the first parameter is greater than the corresponding value
1057	1064	/// in the second parameter.
1058	1065	///
1059		/// The comparison yields 0 for false, 1 for true.
	1066	/// The comparison yields 0 for false, 1 for true. If either of the two
	1067	/// lower double-precision values is NaN, 0 is returned.
1060	1068	///
1061	1069	/// \headerfile <x86intrin.h>
1062	1070	///
...	...	@@ -1068,7 +1076,8 @@ _mm_comile_sd(__m128d __a, __m128d __b)
1068	1076	/// \param __b
1069	1077	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1070	1078	/// compared to the lower double-precision value of \a __a.
1071		/// \returns An integer containing the comparison results.
	1079	/// \returns An integer containing the comparison results. If either of the two
	1080	/// lower double-precision values is NaN, 0 is returned.
1072	1081	static __inline__ int __DEFAULT_FN_ATTRS
1073	1082	_mm_comigt_sd(__m128d __a, __m128d __b)
1074	1083	{
...	...	@@ -1080,7 +1089,8 @@ _mm_comigt_sd(__m128d __a, __m128d __b)
1080	1089	/// the value in the first parameter is greater than or equal to the
1081	1090	/// corresponding value in the second parameter.
1082	1091	///
1083		/// The comparison yields 0 for false, 1 for true.
	1092	/// The comparison yields 0 for false, 1 for true. If either of the two
	1093	/// lower double-precision values is NaN, 0 is returned.
1084	1094	///
1085	1095	/// \headerfile <x86intrin.h>
1086	1096	///
...	...	@@ -1092,7 +1102,8 @@ _mm_comigt_sd(__m128d __a, __m128d __b)
1092	1102	/// \param __b
1093	1103	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1094	1104	/// compared to the lower double-precision value of \a __a.
1095		/// \returns An integer containing the comparison results.
	1105	/// \returns An integer containing the comparison results. If either of the two
	1106	/// lower double-precision values is NaN, 0 is returned.
1096	1107	static __inline__ int __DEFAULT_FN_ATTRS
1097	1108	_mm_comige_sd(__m128d __a, __m128d __b)
1098	1109	{
...	...	@@ -1104,7 +1115,8 @@ _mm_comige_sd(__m128d __a, __m128d __b)
1104	1115	/// the value in the first parameter is unequal to the corresponding value in
1105	1116	/// the second parameter.
1106	1117	///
1107		/// The comparison yields 0 for false, 1 for true.
	1118	/// The comparison yields 0 for false, 1 for true. If either of the two
	1119	/// lower double-precision values is NaN, 1 is returned.
1108	1120	///
1109	1121	/// \headerfile <x86intrin.h>
1110	1122	///
...	...	@@ -1116,7 +1128,8 @@ _mm_comige_sd(__m128d __a, __m128d __b)
1116	1128	/// \param __b
1117	1129	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1118	1130	/// compared to the lower double-precision value of \a __a.
1119		/// \returns An integer containing the comparison results.
	1131	/// \returns An integer containing the comparison results. If either of the two
	1132	/// lower double-precision values is NaN, 1 is returned.
1120	1133	static __inline__ int __DEFAULT_FN_ATTRS
1121	1134	_mm_comineq_sd(__m128d __a, __m128d __b)
1122	1135	{
...	...	@@ -1127,7 +1140,7 @@ _mm_comineq_sd(__m128d __a, __m128d __b)
1127	1140	/// the two 128-bit floating-point vectors of [2 x double] for equality. The
1128	1141	/// comparison yields 0 for false, 1 for true.
1129	1142	///
1130		/// If either of the two lower double-precision values is NaN, 1 is returned.
	1143	/// If either of the two lower double-precision values is NaN, 0 is returned.
1131	1144	///
1132	1145	/// \headerfile <x86intrin.h>
1133	1146	///
...	...	@@ -1140,7 +1153,7 @@ _mm_comineq_sd(__m128d __a, __m128d __b)
1140	1153	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1141	1154	/// compared to the lower double-precision value of \a __a.
1142	1155	/// \returns An integer containing the comparison results. If either of the two
1143		/// lower double-precision values is NaN, 1 is returned.
	1156	/// lower double-precision values is NaN, 0 is returned.
1144	1157	static __inline__ int __DEFAULT_FN_ATTRS
1145	1158	_mm_ucomieq_sd(__m128d __a, __m128d __b)
1146	1159	{
...	...	@@ -1153,7 +1166,7 @@ _mm_ucomieq_sd(__m128d __a, __m128d __b)
1153	1166	/// the second parameter.
1154	1167	///
1155	1168	/// The comparison yields 0 for false, 1 for true. If either of the two lower
1156		/// double-precision values is NaN, 1 is returned.
	1169	/// double-precision values is NaN, 0 is returned.
1157	1170	///
1158	1171	/// \headerfile <x86intrin.h>
1159	1172	///
...	...	@@ -1166,7 +1179,7 @@ _mm_ucomieq_sd(__m128d __a, __m128d __b)
1166	1179	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1167	1180	/// compared to the lower double-precision value of \a __a.
1168	1181	/// \returns An integer containing the comparison results. If either of the two
1169		/// lower double-precision values is NaN, 1 is returned.
	1182	/// lower double-precision values is NaN, 0 is returned.
1170	1183	static __inline__ int __DEFAULT_FN_ATTRS
1171	1184	_mm_ucomilt_sd(__m128d __a, __m128d __b)
1172	1185	{
...	...	@@ -1179,7 +1192,7 @@ _mm_ucomilt_sd(__m128d __a, __m128d __b)
1179	1192	/// corresponding value in the second parameter.
1180	1193	///
1181	1194	/// The comparison yields 0 for false, 1 for true. If either of the two lower
1182		/// double-precision values is NaN, 1 is returned.
	1195	/// double-precision values is NaN, 0 is returned.
1183	1196	///
1184	1197	/// \headerfile <x86intrin.h>
1185	1198	///
...	...	@@ -1192,7 +1205,7 @@ _mm_ucomilt_sd(__m128d __a, __m128d __b)
1192	1205	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1193	1206	/// compared to the lower double-precision value of \a __a.
1194	1207	/// \returns An integer containing the comparison results. If either of the two
1195		/// lower double-precision values is NaN, 1 is returned.
	1208	/// lower double-precision values is NaN, 0 is returned.
1196	1209	static __inline__ int __DEFAULT_FN_ATTRS
1197	1210	_mm_ucomile_sd(__m128d __a, __m128d __b)
1198	1211	{
...	...	@@ -1257,7 +1270,7 @@ _mm_ucomige_sd(__m128d __a, __m128d __b)
1257	1270	/// the second parameter.
1258	1271	///
1259	1272	/// The comparison yields 0 for false, 1 for true. If either of the two lower
1260		/// double-precision values is NaN, 0 is returned.
	1273	/// double-precision values is NaN, 1 is returned.
1261	1274	///
1262	1275	/// \headerfile <x86intrin.h>
1263	1276	///
...	...	@@ -1270,7 +1283,7 @@ _mm_ucomige_sd(__m128d __a, __m128d __b)
1270	1283	/// A 128-bit vector of [2 x double]. The lower double-precision value is
1271	1284	/// compared to the lower double-precision value of \a __a.
1272	1285	/// \returns An integer containing the comparison result. If either of the two
1273		/// lower double-precision values is NaN, 0 is returned.
	1286	/// lower double-precision values is NaN, 1 is returned.
1274	1287	static __inline__ int __DEFAULT_FN_ATTRS
1275	1288	_mm_ucomineq_sd(__m128d __a, __m128d __b)
1276	1289	{
...	...	@@ -1935,14 +1948,15 @@ _mm_store_pd(double *__dp, __m128d __a)
1935	1948	///
1936	1949	/// \headerfile <x86intrin.h>
1937	1950	///
1938		/// This intrinsic corresponds to the <c>VMOVDDUP + VMOVAPD / MOVLHPS + MOVAPS </c> instruction.
	1951	/// This intrinsic corresponds to the
	1952	/// <c> VMOVDDUP + VMOVAPD / MOVLHPS + MOVAPS </c> instruction.
1939	1953	///
1940	1954	/// \param __dp
1941	1955	/// A pointer to a memory location that can store two double-precision
1942	1956	/// values.
1943	1957	/// \param __a
1944	1958	/// A 128-bit vector of [2 x double] whose lower 64 bits are copied to each
1945		/// of the values in \a dp.
	1959	/// of the values in \a __dp.
1946	1960	static __inline__ void __DEFAULT_FN_ATTRS
1947	1961	_mm_store1_pd(double *__dp, __m128d __a)
1948	1962	{
...	...	@@ -1950,18 +1964,20 @@ _mm_store1_pd(double *__dp, __m128d __a)
1950	1964	_mm_store_pd(__dp, __a);
1951	1965	}
1952	1966
1953		/// \brief Stores a 128-bit vector of [2 x double] into an aligned memory
1954		/// location.
	1967	/// \brief Moves the lower 64 bits of a 128-bit vector of [2 x double] twice to
	1968	/// the upper and lower 64 bits of a memory location.
1955	1969	///
1956	1970	/// \headerfile <x86intrin.h>
1957	1971	///
1958		/// This intrinsic corresponds to the <c> VMOVAPD / MOVAPD </c> instruction.
	1972	/// This intrinsic corresponds to the
	1973	/// <c> VMOVDDUP + VMOVAPD / MOVLHPS + MOVAPS </c> instruction.
1959	1974	///
1960	1975	/// \param __dp
1961		/// A pointer to a 128-bit memory location. The address of the memory
1962		/// location has to be 16-byte aligned.
	1976	/// A pointer to a memory location that can store two double-precision
	1977	/// values.
1963	1978	/// \param __a
1964		/// A 128-bit vector of [2 x double] containing the values to be stored.
	1979	/// A 128-bit vector of [2 x double] whose lower 64 bits are copied to each
	1980	/// of the values in \a __dp.
1965	1981	static __inline__ void __DEFAULT_FN_ATTRS
1966	1982	_mm_store_pd1(double *__dp, __m128d __a)
1967	1983	{
...	...	@@ -3846,8 +3862,7 @@ _mm_set1_epi8(char __b)
3846	3862	///
3847	3863	/// \headerfile <x86intrin.h>
3848	3864	///
3849		/// This intrinsic corresponds to the <c> VPUNPCKLQDQ / PUNPCKLQDQ </c>
3850		/// instruction.
	3865	/// This intrinsic does not correspond to a specific instruction.
3851	3866	///
3852	3867	/// \param __q0
3853	3868	/// A 64-bit integral value used to initialize the lower 64 bits of the
...	...	@@ -4018,7 +4033,7 @@ _mm_storeu_si128(__m128i *__p, __m128i __b)
4018	4033	/// specified unaligned memory location. When a mask bit is 1, the
4019	4034	/// corresponding byte is written, otherwise it is not written.
4020	4035	///
4021		/// To minimize caching, the date is flagged as non-temporal (unlikely to be
	4036	/// To minimize caching, the data is flagged as non-temporal (unlikely to be
4022	4037	/// used again soon). Exception and trap behavior for elements not selected
4023	4038	/// for storage to memory are implementation dependent.
4024	4039	///
...	...	@@ -4532,8 +4547,8 @@ _mm_unpackhi_epi32(__m128i __a, __m128i __b)
4532	4547	return (__m128i)__builtin_shufflevector((__v4si)__a, (__v4si)__b, 2, 4+2, 3, 4+3);
4533	4548	}
4534	4549
4535		/// \brief Unpacks the high-order (odd-indexed) values from two 128-bit vectors
4536		/// of [2 x i64] and interleaves them into a 128-bit vector of [2 x i64].
	4550	/// \brief Unpacks the high-order 64-bit elements from two 128-bit vectors of
	4551	/// [2 x i64] and interleaves them into a 128-bit vector of [2 x i64].
4537	4552	///
4538	4553	/// \headerfile <x86intrin.h>
4539	4554	///
...	...	@@ -4665,7 +4680,7 @@ _mm_unpacklo_epi64(__m128i __a, __m128i __b)
4665	4680	///
4666	4681	/// \headerfile <x86intrin.h>
4667	4682	///
4668		/// This intrinsic has no corresponding instruction.
	4683	/// This intrinsic corresponds to the <c> MOVDQ2Q </c> instruction.
4669	4684	///
4670	4685	/// \param __a
4671	4686	/// A 128-bit integer vector operand. The lower 64 bits are moved to the
...	...	@@ -4682,7 +4697,7 @@ _mm_movepi64_pi64(__m128i __a)
4682	4697	///
4683	4698	/// \headerfile <x86intrin.h>
4684	4699	///
4685		/// This intrinsic corresponds to the <c> VMOVQ / MOVQ / MOVD </c> instruction.
	4700	/// This intrinsic corresponds to the <c> MOVD+VMOVQ </c> instruction.
4686	4701	///
4687	4702	/// \param __a
4688	4703	/// A 64-bit value.
...	...	@@ -4712,8 +4727,8 @@ _mm_move_epi64(__m128i __a)
4712	4727	return __builtin_shufflevector((__v2di)__a, (__m128i){ 0 }, 0, 2);
4713	4728	}
4714	4729
4715		/// \brief Unpacks the high-order (odd-indexed) values from two 128-bit vectors
4716		/// of [2 x double] and interleaves them into a 128-bit vector of [2 x
	4730	/// \brief Unpacks the high-order 64-bit elements from two 128-bit vectors of
	4731	/// [2 x double] and interleaves them into a 128-bit vector of [2 x
4717	4732	/// double].
4718	4733	///
4719	4734	/// \headerfile <x86intrin.h>
...	...	@@ -4733,7 +4748,7 @@ _mm_unpackhi_pd(__m128d __a, __m128d __b)
4733	4748	return __builtin_shufflevector((__v2df)__a, (__v2df)__b, 1, 2+1);
4734	4749	}
4735	4750
4736		/// \brief Unpacks the low-order (even-indexed) values from two 128-bit vectors
	4751	/// \brief Unpacks the low-order 64-bit elements from two 128-bit vectors
4737	4752	/// of [2 x double] and interleaves them into a 128-bit vector of [2 x
4738	4753	/// double].
4739	4754	///
...	...	@@ -4792,9 +4807,9 @@ _mm_movemask_pd(__m128d __a)
4792	4807	/// A 128-bit vector of [2 x double].
4793	4808	/// \param i
4794	4809	/// An 8-bit immediate value. The least significant two bits specify which
4795		/// elements to copy from a and b: \n
4796		/// Bit[0] = 0: lower element of a copied to lower element of result. \n
4797		/// Bit[0] = 1: upper element of a copied to lower element of result. \n
	4810	/// elements to copy from \a a and \a b: \n
	4811	/// Bit[0] = 0: lower element of \a a copied to lower element of result. \n
	4812	/// Bit[0] = 1: upper element of \a a copied to lower element of result. \n
4798	4813	/// Bit[1] = 0: lower element of \a b copied to upper element of result. \n
4799	4814	/// Bit[1] = 1: upper element of \a b copied to upper element of result. \n
4800	4815	/// \returns A 128-bit vector of [2 x double] containing the shuffled values.

c_headers/fma4intrin.h+22-22

...	...	@@ -60,73 +60,73 @@ _mm_macc_sd(__m128d __A, __m128d __B, __m128d __C)
60	60	static __inline__ __m128 __DEFAULT_FN_ATTRS
61	61	_mm_msub_ps(__m128 __A, __m128 __B, __m128 __C)
62	62	{
63		return (__m128)__builtin_ia32_vfmsubps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	63	return (__m128)__builtin_ia32_vfmaddps((__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
64	64	}
65	65
66	66	static __inline__ __m128d __DEFAULT_FN_ATTRS
67	67	_mm_msub_pd(__m128d __A, __m128d __B, __m128d __C)
68	68	{
69		return (__m128d)__builtin_ia32_vfmsubpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	69	return (__m128d)__builtin_ia32_vfmaddpd((__v2df)__A, (__v2df)__B, -(__v2df)__C);
70	70	}
71	71
72	72	static __inline__ __m128 __DEFAULT_FN_ATTRS
73	73	_mm_msub_ss(__m128 __A, __m128 __B, __m128 __C)
74	74	{
75		return (__m128)__builtin_ia32_vfmsubss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	75	return (__m128)__builtin_ia32_vfmaddss((__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
76	76	}
77	77
78	78	static __inline__ __m128d __DEFAULT_FN_ATTRS
79	79	_mm_msub_sd(__m128d __A, __m128d __B, __m128d __C)
80	80	{
81		return (__m128d)__builtin_ia32_vfmsubsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	81	return (__m128d)__builtin_ia32_vfmaddsd((__v2df)__A, (__v2df)__B, -(__v2df)__C);
82	82	}
83	83
84	84	static __inline__ __m128 __DEFAULT_FN_ATTRS
85	85	_mm_nmacc_ps(__m128 __A, __m128 __B, __m128 __C)
86	86	{
87		return (__m128)__builtin_ia32_vfnmaddps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	87	return (__m128)__builtin_ia32_vfmaddps(-(__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
88	88	}
89	89
90	90	static __inline__ __m128d __DEFAULT_FN_ATTRS
91	91	_mm_nmacc_pd(__m128d __A, __m128d __B, __m128d __C)
92	92	{
93		return (__m128d)__builtin_ia32_vfnmaddpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	93	return (__m128d)__builtin_ia32_vfmaddpd(-(__v2df)__A, (__v2df)__B, (__v2df)__C);
94	94	}
95	95
96	96	static __inline__ __m128 __DEFAULT_FN_ATTRS
97	97	_mm_nmacc_ss(__m128 __A, __m128 __B, __m128 __C)
98	98	{
99		return (__m128)__builtin_ia32_vfnmaddss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	99	return (__m128)__builtin_ia32_vfmaddss(-(__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
100	100	}
101	101
102	102	static __inline__ __m128d __DEFAULT_FN_ATTRS
103	103	_mm_nmacc_sd(__m128d __A, __m128d __B, __m128d __C)
104	104	{
105		return (__m128d)__builtin_ia32_vfnmaddsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	105	return (__m128d)__builtin_ia32_vfmaddsd(-(__v2df)__A, (__v2df)__B, (__v2df)__C);
106	106	}
107	107
108	108	static __inline__ __m128 __DEFAULT_FN_ATTRS
109	109	_mm_nmsub_ps(__m128 __A, __m128 __B, __m128 __C)
110	110	{
111		return (__m128)__builtin_ia32_vfnmsubps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	111	return (__m128)__builtin_ia32_vfmaddps(-(__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
112	112	}
113	113
114	114	static __inline__ __m128d __DEFAULT_FN_ATTRS
115	115	_mm_nmsub_pd(__m128d __A, __m128d __B, __m128d __C)
116	116	{
117		return (__m128d)__builtin_ia32_vfnmsubpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	117	return (__m128d)__builtin_ia32_vfmaddpd(-(__v2df)__A, (__v2df)__B, -(__v2df)__C);
118	118	}
119	119
120	120	static __inline__ __m128 __DEFAULT_FN_ATTRS
121	121	_mm_nmsub_ss(__m128 __A, __m128 __B, __m128 __C)
122	122	{
123		return (__m128)__builtin_ia32_vfnmsubss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	123	return (__m128)__builtin_ia32_vfmaddss(-(__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
124	124	}
125	125
126	126	static __inline__ __m128d __DEFAULT_FN_ATTRS
127	127	_mm_nmsub_sd(__m128d __A, __m128d __B, __m128d __C)
128	128	{
129		return (__m128d)__builtin_ia32_vfnmsubsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	129	return (__m128d)__builtin_ia32_vfmaddsd(-(__v2df)__A, (__v2df)__B, -(__v2df)__C);
130	130	}
131	131
132	132	static __inline__ __m128 __DEFAULT_FN_ATTRS
...	...	@@ -144,13 +144,13 @@ _mm_maddsub_pd(__m128d __A, __m128d __B, __m128d __C)
144	144	static __inline__ __m128 __DEFAULT_FN_ATTRS
145	145	_mm_msubadd_ps(__m128 __A, __m128 __B, __m128 __C)
146	146	{
147		return (__m128)__builtin_ia32_vfmsubaddps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	147	return (__m128)__builtin_ia32_vfmaddsubps((__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
148	148	}
149	149
150	150	static __inline__ __m128d __DEFAULT_FN_ATTRS
151	151	_mm_msubadd_pd(__m128d __A, __m128d __B, __m128d __C)
152	152	{
153		return (__m128d)__builtin_ia32_vfmsubaddpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	153	return (__m128d)__builtin_ia32_vfmaddsubpd((__v2df)__A, (__v2df)__B, -(__v2df)__C);
154	154	}
155	155
156	156	static __inline__ __m256 __DEFAULT_FN_ATTRS
...	...	@@ -168,37 +168,37 @@ _mm256_macc_pd(__m256d __A, __m256d __B, __m256d __C)
168	168	static __inline__ __m256 __DEFAULT_FN_ATTRS
169	169	_mm256_msub_ps(__m256 __A, __m256 __B, __m256 __C)
170	170	{
171		return (__m256)__builtin_ia32_vfmsubps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	171	return (__m256)__builtin_ia32_vfmaddps256((__v8sf)__A, (__v8sf)__B, -(__v8sf)__C);
172	172	}
173	173
174	174	static __inline__ __m256d __DEFAULT_FN_ATTRS
175	175	_mm256_msub_pd(__m256d __A, __m256d __B, __m256d __C)
176	176	{
177		return (__m256d)__builtin_ia32_vfmsubpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	177	return (__m256d)__builtin_ia32_vfmaddpd256((__v4df)__A, (__v4df)__B, -(__v4df)__C);
178	178	}
179	179
180	180	static __inline__ __m256 __DEFAULT_FN_ATTRS
181	181	_mm256_nmacc_ps(__m256 __A, __m256 __B, __m256 __C)
182	182	{
183		return (__m256)__builtin_ia32_vfnmaddps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	183	return (__m256)__builtin_ia32_vfmaddps256(-(__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
184	184	}
185	185
186	186	static __inline__ __m256d __DEFAULT_FN_ATTRS
187	187	_mm256_nmacc_pd(__m256d __A, __m256d __B, __m256d __C)
188	188	{
189		return (__m256d)__builtin_ia32_vfnmaddpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	189	return (__m256d)__builtin_ia32_vfmaddpd256(-(__v4df)__A, (__v4df)__B, (__v4df)__C);
190	190	}
191	191
192	192	static __inline__ __m256 __DEFAULT_FN_ATTRS
193	193	_mm256_nmsub_ps(__m256 __A, __m256 __B, __m256 __C)
194	194	{
195		return (__m256)__builtin_ia32_vfnmsubps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	195	return (__m256)__builtin_ia32_vfmaddps256(-(__v8sf)__A, (__v8sf)__B, -(__v8sf)__C);
196	196	}
197	197
198	198	static __inline__ __m256d __DEFAULT_FN_ATTRS
199	199	_mm256_nmsub_pd(__m256d __A, __m256d __B, __m256d __C)
200	200	{
201		return (__m256d)__builtin_ia32_vfnmsubpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	201	return (__m256d)__builtin_ia32_vfmaddpd256(-(__v4df)__A, (__v4df)__B, -(__v4df)__C);
202	202	}
203	203
204	204	static __inline__ __m256 __DEFAULT_FN_ATTRS
...	...	@@ -216,13 +216,13 @@ _mm256_maddsub_pd(__m256d __A, __m256d __B, __m256d __C)
216	216	static __inline__ __m256 __DEFAULT_FN_ATTRS
217	217	_mm256_msubadd_ps(__m256 __A, __m256 __B, __m256 __C)
218	218	{
219		return (__m256)__builtin_ia32_vfmsubaddps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	219	return (__m256)__builtin_ia32_vfmaddsubps256((__v8sf)__A, (__v8sf)__B, -(__v8sf)__C);
220	220	}
221	221
222	222	static __inline__ __m256d __DEFAULT_FN_ATTRS
223	223	_mm256_msubadd_pd(__m256d __A, __m256d __B, __m256d __C)
224	224	{
225		return (__m256d)__builtin_ia32_vfmsubaddpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	225	return (__m256d)__builtin_ia32_vfmaddsubpd256((__v4df)__A, (__v4df)__B, -(__v4df)__C);
226	226	}
227	227
228	228	#undef __DEFAULT_FN_ATTRS

c_headers/fmaintrin.h+24-24

...	...	@@ -46,85 +46,85 @@ _mm_fmadd_pd(__m128d __A, __m128d __B, __m128d __C)
46	46	static __inline__ __m128 __DEFAULT_FN_ATTRS
47	47	_mm_fmadd_ss(__m128 __A, __m128 __B, __m128 __C)
48	48	{
49		return (__m128)__builtin_ia32_vfmaddss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	49	return (__m128)__builtin_ia32_vfmaddss3((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
50	50	}
51	51
52	52	static __inline__ __m128d __DEFAULT_FN_ATTRS
53	53	_mm_fmadd_sd(__m128d __A, __m128d __B, __m128d __C)
54	54	{
55		return (__m128d)__builtin_ia32_vfmaddsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	55	return (__m128d)__builtin_ia32_vfmaddsd3((__v2df)__A, (__v2df)__B, (__v2df)__C);
56	56	}
57	57
58	58	static __inline__ __m128 __DEFAULT_FN_ATTRS
59	59	_mm_fmsub_ps(__m128 __A, __m128 __B, __m128 __C)
60	60	{
61		return (__m128)__builtin_ia32_vfmsubps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	61	return (__m128)__builtin_ia32_vfmaddps((__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
62	62	}
63	63
64	64	static __inline__ __m128d __DEFAULT_FN_ATTRS
65	65	_mm_fmsub_pd(__m128d __A, __m128d __B, __m128d __C)
66	66	{
67		return (__m128d)__builtin_ia32_vfmsubpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	67	return (__m128d)__builtin_ia32_vfmaddpd((__v2df)__A, (__v2df)__B, -(__v2df)__C);
68	68	}
69	69
70	70	static __inline__ __m128 __DEFAULT_FN_ATTRS
71	71	_mm_fmsub_ss(__m128 __A, __m128 __B, __m128 __C)
72	72	{
73		return (__m128)__builtin_ia32_vfmsubss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	73	return (__m128)__builtin_ia32_vfmaddss3((__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
74	74	}
75	75
76	76	static __inline__ __m128d __DEFAULT_FN_ATTRS
77	77	_mm_fmsub_sd(__m128d __A, __m128d __B, __m128d __C)
78	78	{
79		return (__m128d)__builtin_ia32_vfmsubsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	79	return (__m128d)__builtin_ia32_vfmaddsd3((__v2df)__A, (__v2df)__B, -(__v2df)__C);
80	80	}
81	81
82	82	static __inline__ __m128 __DEFAULT_FN_ATTRS
83	83	_mm_fnmadd_ps(__m128 __A, __m128 __B, __m128 __C)
84	84	{
85		return (__m128)__builtin_ia32_vfnmaddps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	85	return (__m128)__builtin_ia32_vfmaddps(-(__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
86	86	}
87	87
88	88	static __inline__ __m128d __DEFAULT_FN_ATTRS
89	89	_mm_fnmadd_pd(__m128d __A, __m128d __B, __m128d __C)
90	90	{
91		return (__m128d)__builtin_ia32_vfnmaddpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	91	return (__m128d)__builtin_ia32_vfmaddpd(-(__v2df)__A, (__v2df)__B, (__v2df)__C);
92	92	}
93	93
94	94	static __inline__ __m128 __DEFAULT_FN_ATTRS
95	95	_mm_fnmadd_ss(__m128 __A, __m128 __B, __m128 __C)
96	96	{
97		return (__m128)__builtin_ia32_vfnmaddss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	97	return (__m128)__builtin_ia32_vfmaddss3((__v4sf)__A, -(__v4sf)__B, (__v4sf)__C);
98	98	}
99	99
100	100	static __inline__ __m128d __DEFAULT_FN_ATTRS
101	101	_mm_fnmadd_sd(__m128d __A, __m128d __B, __m128d __C)
102	102	{
103		return (__m128d)__builtin_ia32_vfnmaddsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	103	return (__m128d)__builtin_ia32_vfmaddsd3((__v2df)__A, -(__v2df)__B, (__v2df)__C);
104	104	}
105	105
106	106	static __inline__ __m128 __DEFAULT_FN_ATTRS
107	107	_mm_fnmsub_ps(__m128 __A, __m128 __B, __m128 __C)
108	108	{
109		return (__m128)__builtin_ia32_vfnmsubps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	109	return (__m128)__builtin_ia32_vfmaddps(-(__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
110	110	}
111	111
112	112	static __inline__ __m128d __DEFAULT_FN_ATTRS
113	113	_mm_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C)
114	114	{
115		return (__m128d)__builtin_ia32_vfnmsubpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	115	return (__m128d)__builtin_ia32_vfmaddpd(-(__v2df)__A, (__v2df)__B, -(__v2df)__C);
116	116	}
117	117
118	118	static __inline__ __m128 __DEFAULT_FN_ATTRS
119	119	_mm_fnmsub_ss(__m128 __A, __m128 __B, __m128 __C)
120	120	{
121		return (__m128)__builtin_ia32_vfnmsubss((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	121	return (__m128)__builtin_ia32_vfmaddss3((__v4sf)__A, -(__v4sf)__B, -(__v4sf)__C);
122	122	}
123	123
124	124	static __inline__ __m128d __DEFAULT_FN_ATTRS
125	125	_mm_fnmsub_sd(__m128d __A, __m128d __B, __m128d __C)
126	126	{
127		return (__m128d)__builtin_ia32_vfnmsubsd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	127	return (__m128d)__builtin_ia32_vfmaddsd3((__v2df)__A, -(__v2df)__B, -(__v2df)__C);
128	128	}
129	129
130	130	static __inline__ __m128 __DEFAULT_FN_ATTRS
...	...	@@ -142,13 +142,13 @@ _mm_fmaddsub_pd(__m128d __A, __m128d __B, __m128d __C)
142	142	static __inline__ __m128 __DEFAULT_FN_ATTRS
143	143	_mm_fmsubadd_ps(__m128 __A, __m128 __B, __m128 __C)
144	144	{
145		return (__m128)__builtin_ia32_vfmsubaddps((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
	145	return (__m128)__builtin_ia32_vfmaddsubps((__v4sf)__A, (__v4sf)__B, -(__v4sf)__C);
146	146	}
147	147
148	148	static __inline__ __m128d __DEFAULT_FN_ATTRS
149	149	_mm_fmsubadd_pd(__m128d __A, __m128d __B, __m128d __C)
150	150	{
151		return (__m128d)__builtin_ia32_vfmsubaddpd((__v2df)__A, (__v2df)__B, (__v2df)__C);
	151	return (__m128d)__builtin_ia32_vfmaddsubpd((__v2df)__A, (__v2df)__B, -(__v2df)__C);
152	152	}
153	153
154	154	static __inline__ __m256 __DEFAULT_FN_ATTRS
...	...	@@ -166,37 +166,37 @@ _mm256_fmadd_pd(__m256d __A, __m256d __B, __m256d __C)
166	166	static __inline__ __m256 __DEFAULT_FN_ATTRS
167	167	_mm256_fmsub_ps(__m256 __A, __m256 __B, __m256 __C)
168	168	{
169		return (__m256)__builtin_ia32_vfmsubps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	169	return (__m256)__builtin_ia32_vfmaddps256((__v8sf)__A, (__v8sf)__B, -(__v8sf)__C);
170	170	}
171	171
172	172	static __inline__ __m256d __DEFAULT_FN_ATTRS
173	173	_mm256_fmsub_pd(__m256d __A, __m256d __B, __m256d __C)
174	174	{
175		return (__m256d)__builtin_ia32_vfmsubpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	175	return (__m256d)__builtin_ia32_vfmaddpd256((__v4df)__A, (__v4df)__B, -(__v4df)__C);
176	176	}
177	177
178	178	static __inline__ __m256 __DEFAULT_FN_ATTRS
179	179	_mm256_fnmadd_ps(__m256 __A, __m256 __B, __m256 __C)
180	180	{
181		return (__m256)__builtin_ia32_vfnmaddps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	181	return (__m256)__builtin_ia32_vfmaddps256(-(__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
182	182	}
183	183
184	184	static __inline__ __m256d __DEFAULT_FN_ATTRS
185	185	_mm256_fnmadd_pd(__m256d __A, __m256d __B, __m256d __C)
186	186	{
187		return (__m256d)__builtin_ia32_vfnmaddpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	187	return (__m256d)__builtin_ia32_vfmaddpd256(-(__v4df)__A, (__v4df)__B, (__v4df)__C);
188	188	}
189	189
190	190	static __inline__ __m256 __DEFAULT_FN_ATTRS
191	191	_mm256_fnmsub_ps(__m256 __A, __m256 __B, __m256 __C)
192	192	{
193		return (__m256)__builtin_ia32_vfnmsubps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	193	return (__m256)__builtin_ia32_vfmaddps256(-(__v8sf)__A, (__v8sf)__B, -(__v8sf)__C);
194	194	}
195	195
196	196	static __inline__ __m256d __DEFAULT_FN_ATTRS
197	197	_mm256_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C)
198	198	{
199		return (__m256d)__builtin_ia32_vfnmsubpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	199	return (__m256d)__builtin_ia32_vfmaddpd256(-(__v4df)__A, (__v4df)__B, -(__v4df)__C);
200	200	}
201	201
202	202	static __inline__ __m256 __DEFAULT_FN_ATTRS
...	...	@@ -214,13 +214,13 @@ _mm256_fmaddsub_pd(__m256d __A, __m256d __B, __m256d __C)
214	214	static __inline__ __m256 __DEFAULT_FN_ATTRS
215	215	_mm256_fmsubadd_ps(__m256 __A, __m256 __B, __m256 __C)
216	216	{
217		return (__m256)__builtin_ia32_vfmsubaddps256((__v8sf)__A, (__v8sf)__B, (__v8sf)__C);
	217	return (__m256)__builtin_ia32_vfmaddsubps256((__v8sf)__A, (__v8sf)__B, -(__v8sf)__C);
218	218	}
219	219
220	220	static __inline__ __m256d __DEFAULT_FN_ATTRS
221	221	_mm256_fmsubadd_pd(__m256d __A, __m256d __B, __m256d __C)
222	222	{
223		return (__m256d)__builtin_ia32_vfmsubaddpd256((__v4df)__A, (__v4df)__B, (__v4df)__C);
	223	return (__m256d)__builtin_ia32_vfmaddsubpd256((__v4df)__A, (__v4df)__B, -(__v4df)__C);
224	224	}
225	225
226	226	#undef __DEFAULT_FN_ATTRS

c_headers/gfniintrin.h created+202

...	...	@@ -0,0 +1,202 @@
	1	/*===----------------- gfniintrin.h - GFNI intrinsics ----------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <gfniintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __GFNIINTRIN_H
	29	#define __GFNIINTRIN_H
	30
	31
	32	#define _mm_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({ \
	33	(__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \
	34	(__v16qi)(__m128i)(B), \
	35	(char)(I)); })
	36
	37	#define _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
	38	(__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
	39	(__v16qi)_mm_gf2p8affineinv_epi64_epi8(A, B, I), \
	40	(__v16qi)(__m128i)(S)); })
	41
	42
	43	#define _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({ \
	44	(__m128i)_mm_mask_gf2p8affineinv_epi64_epi8((__m128i)_mm_setzero_si128(), \
	45	U, A, B, I); })
	46
	47
	48	#define _mm256_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({ \
	49	(__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \
	50	(__v32qi)(__m256i)(B), \
	51	(char)(I)); })
	52
	53	#define _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
	54	(__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
	55	(__v32qi)_mm256_gf2p8affineinv_epi64_epi8(A, B, I), \
	56	(__v32qi)(__m256i)(S)); })
	57
	58	#define _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({ \
	59	(__m256i)_mm256_mask_gf2p8affineinv_epi64_epi8((__m256i)_mm256_setzero_si256(), \
	60	U, A, B, I); })
	61
	62
	63	#define _mm512_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({ \
	64	(__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)(__m512i)(A), \
	65	(__v64qi)(__m512i)(B), \
	66	(char)(I)); })
	67
	68	#define _mm512_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
	69	(__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \
	70	(__v64qi)_mm512_gf2p8affineinv_epi64_epi8(A, B, I), \
	71	(__v64qi)(__m512i)(S)); })
	72
	73	#define _mm512_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({ \
	74	(__m512i)_mm512_mask_gf2p8affineinv_epi64_epi8((__m512i)_mm512_setzero_qi(), \
	75	U, A, B, I); })
	76
	77	#define _mm_gf2p8affine_epi64_epi8(A, B, I) __extension__ ({ \
	78	(__m128i)__builtin_ia32_vgf2p8affineqb_v16qi((__v16qi)(__m128i)(A), \
	79	(__v16qi)(__m128i)(B), \
	80	(char)(I)); })
	81
	82	#define _mm_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) __extension__ ({ \
	83	(__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
	84	(__v16qi)_mm_gf2p8affine_epi64_epi8(A, B, I), \
	85	(__v16qi)(__m128i)(S)); })
	86
	87
	88	#define _mm_maskz_gf2p8affine_epi64_epi8(U, A, B, I) __extension__ ({ \
	89	(__m128i)_mm_mask_gf2p8affine_epi64_epi8((__m128i)_mm_setzero_si128(), \
	90	U, A, B, I); })
	91
	92
	93	#define _mm256_gf2p8affine_epi64_epi8(A, B, I) __extension__ ({ \
	94	(__m256i)__builtin_ia32_vgf2p8affineqb_v32qi((__v32qi)(__m256i)(A), \
	95	(__v32qi)(__m256i)(B), \
	96	(char)(I)); })
	97
	98	#define _mm256_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) __extension__ ({ \
	99	(__m256i)__builtin_ia32_selectb_256((__mmask32)(U), \
	100	(__v32qi)_mm256_gf2p8affine_epi64_epi8(A, B, I), \
	101	(__v32qi)(__m256i)(S)); })
	102
	103	#define _mm256_maskz_gf2p8affine_epi64_epi8(U, A, B, I) __extension__ ({ \
	104	(__m256i)_mm256_mask_gf2p8affine_epi64_epi8((__m256i)_mm256_setzero_si256(), \
	105	U, A, B, I); })
	106
	107
	108	#define _mm512_gf2p8affine_epi64_epi8(A, B, I) __extension__ ({ \
	109	(__m512i)__builtin_ia32_vgf2p8affineqb_v64qi((__v64qi)(__m512i)(A), \
	110	(__v64qi)(__m512i)(B), \
	111	(char)(I)); })
	112
	113	#define _mm512_mask_gf2p8affine_epi64_epi8(S, U, A, B, I) __extension__ ({ \
	114	(__m512i)__builtin_ia32_selectb_512((__mmask64)(U), \
	115	(__v64qi)_mm512_gf2p8affine_epi64_epi8(A, B, I), \
	116	(__v64qi)(__m512i)(S)); })
	117
	118	#define _mm512_maskz_gf2p8affine_epi64_epi8(U, A, B, I) __extension__ ({ \
	119	(__m512i)_mm512_mask_gf2p8affine_epi64_epi8((__m512i)_mm512_setzero_qi(), \
	120	U, A, B, I); })
	121
	122	/* Default attributes for simple form (no masking). */
	123	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("gfni")))
	124
	125	/* Default attributes for ZMM forms. */
	126	#define __DEFAULT_FN_ATTRS_F __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,gfni")))
	127
	128	/* Default attributes for VLX forms. */
	129	#define __DEFAULT_FN_ATTRS_VL __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,avx512vl,gfni")))
	130
	131	static __inline__ __m128i __DEFAULT_FN_ATTRS
	132	_mm_gf2p8mul_epi8(__m128i __A, __m128i __B)
	133	{
	134	return (__m128i) __builtin_ia32_vgf2p8mulb_v16qi((__v16qi) __A,
	135	(__v16qi) __B);
	136	}
	137
	138	static __inline__ __m128i __DEFAULT_FN_ATTRS_VL
	139	_mm_mask_gf2p8mul_epi8(__m128i __S, __mmask16 __U, __m128i __A, __m128i __B)
	140	{
	141	return (__m128i) __builtin_ia32_selectb_128(__U,
	142	(__v16qi) _mm_gf2p8mul_epi8(__A, __B),
	143	(__v16qi) __S);
	144	}
	145
	146	static __inline__ __m128i __DEFAULT_FN_ATTRS_VL
	147	_mm_maskz_gf2p8mul_epi8(__mmask16 __U, __m128i __A, __m128i __B)
	148	{
	149	return _mm_mask_gf2p8mul_epi8((__m128i)_mm_setzero_si128(),
	150	__U, __A, __B);
	151	}
	152
	153	static __inline__ __m256i __DEFAULT_FN_ATTRS
	154	_mm256_gf2p8mul_epi8(__m256i __A, __m256i __B)
	155	{
	156	return (__m256i) __builtin_ia32_vgf2p8mulb_v32qi((__v32qi) __A,
	157	(__v32qi) __B);
	158	}
	159
	160	static __inline__ __m256i __DEFAULT_FN_ATTRS_VL
	161	_mm256_mask_gf2p8mul_epi8(__m256i __S, __mmask32 __U, __m256i __A, __m256i __B)
	162	{
	163	return (__m256i) __builtin_ia32_selectb_256(__U,
	164	(__v32qi) _mm256_gf2p8mul_epi8(__A, __B),
	165	(__v32qi) __S);
	166	}
	167
	168	static __inline__ __m256i __DEFAULT_FN_ATTRS_VL
	169	_mm256_maskz_gf2p8mul_epi8(__mmask32 __U, __m256i __A, __m256i __B)
	170	{
	171	return _mm256_mask_gf2p8mul_epi8((__m256i)_mm256_setzero_si256(),
	172	__U, __A, __B);
	173	}
	174
	175	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	176	_mm512_gf2p8mul_epi8(__m512i __A, __m512i __B)
	177	{
	178	return (__m512i) __builtin_ia32_vgf2p8mulb_v64qi((__v64qi) __A,
	179	(__v64qi) __B);
	180	}
	181
	182	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	183	_mm512_mask_gf2p8mul_epi8(__m512i __S, __mmask64 __U, __m512i __A, __m512i __B)
	184	{
	185	return (__m512i) __builtin_ia32_selectb_512(__U,
	186	(__v64qi) _mm512_gf2p8mul_epi8(__A, __B),
	187	(__v64qi) __S);
	188	}
	189
	190	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	191	_mm512_maskz_gf2p8mul_epi8(__mmask64 __U, __m512i __A, __m512i __B)
	192	{
	193	return _mm512_mask_gf2p8mul_epi8((__m512i)_mm512_setzero_qi(),
	194	__U, __A, __B);
	195	}
	196
	197	#undef __DEFAULT_FN_ATTRS
	198	#undef __DEFAULT_FN_ATTRS_F
	199	#undef __DEFAULT_FN_ATTRS_VL
	200
	201	#endif // __GFNIINTRIN_H
	202

c_headers/immintrin.h+48

...	...	@@ -118,6 +118,10 @@ _mm256_cvtph_ps(__m128i __a)
118	118	}
119	119	#endif /* __AVX2__ */
120	120
	121	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__VPCLMULQDQ__)
	122	#include <vpclmulqdqintrin.h>
	123	#endif
	124
121	125	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__BMI__)
122	126	#include <bmiintrin.h>
123	127	#endif
...	...	@@ -146,6 +150,10 @@ _mm256_cvtph_ps(__m128i __a)
146	150	#include <avx512bwintrin.h>
147	151	#endif
148	152
	153	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__AVX512BITALG__)
	154	#include <avx512bitalgintrin.h>
	155	#endif
	156
149	157	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__AVX512CD__)
150	158	#include <avx512cdintrin.h>
151	159	#endif
...	...	@@ -154,10 +162,29 @@ _mm256_cvtph_ps(__m128i __a)
154	162	#include <avx512vpopcntdqintrin.h>
155	163	#endif
156	164
	165	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| \
	166	(defined(__AVX512VL__) && defined(__AVX512VPOPCNTDQ__))
	167	#include <avx512vpopcntdqvlintrin.h>
	168	#endif
	169
	170	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__AVX512VNNI__)
	171	#include <avx512vnniintrin.h>
	172	#endif
	173
	174	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| \
	175	(defined(__AVX512VL__) && defined(__AVX512VNNI__))
	176	#include <avx512vlvnniintrin.h>
	177	#endif
	178
157	179	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__AVX512DQ__)
158	180	#include <avx512dqintrin.h>
159	181	#endif
160	182
	183	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| \
	184	(defined(__AVX512VL__) && defined(__AVX512BITALG__))
	185	#include <avx512vlbitalgintrin.h>
	186	#endif
	187
161	188	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| \
162	189	(defined(__AVX512VL__) && defined(__AVX512BW__))
163	190	#include <avx512vlbwintrin.h>
...	...	@@ -195,6 +222,15 @@ _mm256_cvtph_ps(__m128i __a)
195	222	#include <avx512vbmivlintrin.h>
196	223	#endif
197	224
	225	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__AVX512VBMI2__)
	226	#include <avx512vbmi2intrin.h>
	227	#endif
	228
	229	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| \
	230	(defined(__AVX512VBMI2__) && defined(__AVX512VL__))
	231	#include <avx512vlvbmi2intrin.h>
	232	#endif
	233
198	234	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__AVX512PF__)
199	235	#include <avx512pfintrin.h>
200	236	#endif
...	...	@@ -203,6 +239,14 @@ _mm256_cvtph_ps(__m128i __a)
203	239	#include <pkuintrin.h>
204	240	#endif
205	241
	242	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__VAES__)
	243	#include <vaesintrin.h>
	244	#endif
	245
	246	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__GFNI__)
	247	#include <gfniintrin.h>
	248	#endif
	249
206	250	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__RDRND__)
207	251	static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
208	252	_rdrand16_step(unsigned short *__p)
...	...	@@ -319,6 +363,10 @@ _writegsbase_u64(unsigned long long __V)
319	363	#include <xsavesintrin.h>
320	364	#endif
321	365
	366	#if !defined(_MSC_VER) \|\| __has_feature(modules) \|\| defined(__SHSTK__)
	367	#include <cetintrin.h>
	368	#endif
	369
322	370	/* Some intrinsics inside adxintrin.h are available only on processors with ADX,
323	371	* whereas others are also available at all times. */
324	372	#include <adxintrin.h>

c_headers/opencl-c.h+307

...	...	@@ -15886,6 +15886,313 @@ double __ovld __conv sub_group_scan_inclusive_max(double x);
15886	15886
15887	15887	#endif //cl_khr_subgroups cl_intel_subgroups
15888	15888
	15889	#if defined(cl_intel_subgroups)
	15890	// Intel-Specific Sub Group Functions
	15891	float __ovld __conv intel_sub_group_shuffle( float x, uint c );
	15892	float2 __ovld __conv intel_sub_group_shuffle( float2 x, uint c );
	15893	float3 __ovld __conv intel_sub_group_shuffle( float3 x, uint c );
	15894	float4 __ovld __conv intel_sub_group_shuffle( float4 x, uint c );
	15895	float8 __ovld __conv intel_sub_group_shuffle( float8 x, uint c );
	15896	float16 __ovld __conv intel_sub_group_shuffle( float16 x, uint c );
	15897
	15898	int __ovld __conv intel_sub_group_shuffle( int x, uint c );
	15899	int2 __ovld __conv intel_sub_group_shuffle( int2 x, uint c );
	15900	int3 __ovld __conv intel_sub_group_shuffle( int3 x, uint c );
	15901	int4 __ovld __conv intel_sub_group_shuffle( int4 x, uint c );
	15902	int8 __ovld __conv intel_sub_group_shuffle( int8 x, uint c );
	15903	int16 __ovld __conv intel_sub_group_shuffle( int16 x, uint c );
	15904
	15905	uint __ovld __conv intel_sub_group_shuffle( uint x, uint c );
	15906	uint2 __ovld __conv intel_sub_group_shuffle( uint2 x, uint c );
	15907	uint3 __ovld __conv intel_sub_group_shuffle( uint3 x, uint c );
	15908	uint4 __ovld __conv intel_sub_group_shuffle( uint4 x, uint c );
	15909	uint8 __ovld __conv intel_sub_group_shuffle( uint8 x, uint c );
	15910	uint16 __ovld __conv intel_sub_group_shuffle( uint16 x, uint c );
	15911
	15912	long __ovld __conv intel_sub_group_shuffle( long x, uint c );
	15913	ulong __ovld __conv intel_sub_group_shuffle( ulong x, uint c );
	15914
	15915	float __ovld __conv intel_sub_group_shuffle_down( float cur, float next, uint c );
	15916	float2 __ovld __conv intel_sub_group_shuffle_down( float2 cur, float2 next, uint c );
	15917	float3 __ovld __conv intel_sub_group_shuffle_down( float3 cur, float3 next, uint c );
	15918	float4 __ovld __conv intel_sub_group_shuffle_down( float4 cur, float4 next, uint c );
	15919	float8 __ovld __conv intel_sub_group_shuffle_down( float8 cur, float8 next, uint c );
	15920	float16 __ovld __conv intel_sub_group_shuffle_down( float16 cur, float16 next, uint c );
	15921
	15922	int __ovld __conv intel_sub_group_shuffle_down( int cur, int next, uint c );
	15923	int2 __ovld __conv intel_sub_group_shuffle_down( int2 cur, int2 next, uint c );
	15924	int3 __ovld __conv intel_sub_group_shuffle_down( int3 cur, int3 next, uint c );
	15925	int4 __ovld __conv intel_sub_group_shuffle_down( int4 cur, int4 next, uint c );
	15926	int8 __ovld __conv intel_sub_group_shuffle_down( int8 cur, int8 next, uint c );
	15927	int16 __ovld __conv intel_sub_group_shuffle_down( int16 cur, int16 next, uint c );
	15928
	15929	uint __ovld __conv intel_sub_group_shuffle_down( uint cur, uint next, uint c );
	15930	uint2 __ovld __conv intel_sub_group_shuffle_down( uint2 cur, uint2 next, uint c );
	15931	uint3 __ovld __conv intel_sub_group_shuffle_down( uint3 cur, uint3 next, uint c );
	15932	uint4 __ovld __conv intel_sub_group_shuffle_down( uint4 cur, uint4 next, uint c );
	15933	uint8 __ovld __conv intel_sub_group_shuffle_down( uint8 cur, uint8 next, uint c );
	15934	uint16 __ovld __conv intel_sub_group_shuffle_down( uint16 cur, uint16 next, uint c );
	15935
	15936	long __ovld __conv intel_sub_group_shuffle_down( long prev, long cur, uint c );
	15937	ulong __ovld __conv intel_sub_group_shuffle_down( ulong prev, ulong cur, uint c );
	15938
	15939	float __ovld __conv intel_sub_group_shuffle_up( float prev, float cur, uint c );
	15940	float2 __ovld __conv intel_sub_group_shuffle_up( float2 prev, float2 cur, uint c );
	15941	float3 __ovld __conv intel_sub_group_shuffle_up( float3 prev, float3 cur, uint c );
	15942	float4 __ovld __conv intel_sub_group_shuffle_up( float4 prev, float4 cur, uint c );
	15943	float8 __ovld __conv intel_sub_group_shuffle_up( float8 prev, float8 cur, uint c );
	15944	float16 __ovld __conv intel_sub_group_shuffle_up( float16 prev, float16 cur, uint c );
	15945
	15946	int __ovld __conv intel_sub_group_shuffle_up( int prev, int cur, uint c );
	15947	int2 __ovld __conv intel_sub_group_shuffle_up( int2 prev, int2 cur, uint c );
	15948	int3 __ovld __conv intel_sub_group_shuffle_up( int3 prev, int3 cur, uint c );
	15949	int4 __ovld __conv intel_sub_group_shuffle_up( int4 prev, int4 cur, uint c );
	15950	int8 __ovld __conv intel_sub_group_shuffle_up( int8 prev, int8 cur, uint c );
	15951	int16 __ovld __conv intel_sub_group_shuffle_up( int16 prev, int16 cur, uint c );
	15952
	15953	uint __ovld __conv intel_sub_group_shuffle_up( uint prev, uint cur, uint c );
	15954	uint2 __ovld __conv intel_sub_group_shuffle_up( uint2 prev, uint2 cur, uint c );
	15955	uint3 __ovld __conv intel_sub_group_shuffle_up( uint3 prev, uint3 cur, uint c );
	15956	uint4 __ovld __conv intel_sub_group_shuffle_up( uint4 prev, uint4 cur, uint c );
	15957	uint8 __ovld __conv intel_sub_group_shuffle_up( uint8 prev, uint8 cur, uint c );
	15958	uint16 __ovld __conv intel_sub_group_shuffle_up( uint16 prev, uint16 cur, uint c );
	15959
	15960	long __ovld __conv intel_sub_group_shuffle_up( long prev, long cur, uint c );
	15961	ulong __ovld __conv intel_sub_group_shuffle_up( ulong prev, ulong cur, uint c );
	15962
	15963	float __ovld __conv intel_sub_group_shuffle_xor( float x, uint c );
	15964	float2 __ovld __conv intel_sub_group_shuffle_xor( float2 x, uint c );
	15965	float3 __ovld __conv intel_sub_group_shuffle_xor( float3 x, uint c );
	15966	float4 __ovld __conv intel_sub_group_shuffle_xor( float4 x, uint c );
	15967	float8 __ovld __conv intel_sub_group_shuffle_xor( float8 x, uint c );
	15968	float16 __ovld __conv intel_sub_group_shuffle_xor( float16 x, uint c );
	15969
	15970	int __ovld __conv intel_sub_group_shuffle_xor( int x, uint c );
	15971	int2 __ovld __conv intel_sub_group_shuffle_xor( int2 x, uint c );
	15972	int3 __ovld __conv intel_sub_group_shuffle_xor( int3 x, uint c );
	15973	int4 __ovld __conv intel_sub_group_shuffle_xor( int4 x, uint c );
	15974	int8 __ovld __conv intel_sub_group_shuffle_xor( int8 x, uint c );
	15975	int16 __ovld __conv intel_sub_group_shuffle_xor( int16 x, uint c );
	15976
	15977	uint __ovld __conv intel_sub_group_shuffle_xor( uint x, uint c );
	15978	uint2 __ovld __conv intel_sub_group_shuffle_xor( uint2 x, uint c );
	15979	uint3 __ovld __conv intel_sub_group_shuffle_xor( uint3 x, uint c );
	15980	uint4 __ovld __conv intel_sub_group_shuffle_xor( uint4 x, uint c );
	15981	uint8 __ovld __conv intel_sub_group_shuffle_xor( uint8 x, uint c );
	15982	uint16 __ovld __conv intel_sub_group_shuffle_xor( uint16 x, uint c );
	15983
	15984	long __ovld __conv intel_sub_group_shuffle_xor( long x, uint c );
	15985	ulong __ovld __conv intel_sub_group_shuffle_xor( ulong x, uint c );
	15986
	15987	uint __ovld __conv intel_sub_group_block_read( read_only image2d_t image, int2 coord );
	15988	uint2 __ovld __conv intel_sub_group_block_read2( read_only image2d_t image, int2 coord );
	15989	uint4 __ovld __conv intel_sub_group_block_read4( read_only image2d_t image, int2 coord );
	15990	uint8 __ovld __conv intel_sub_group_block_read8( read_only image2d_t image, int2 coord );
	15991
	15992	#if (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	15993	uint __ovld __conv intel_sub_group_block_read(read_write image2d_t image, int2 coord);
	15994	uint2 __ovld __conv intel_sub_group_block_read2(read_write image2d_t image, int2 coord);
	15995	uint4 __ovld __conv intel_sub_group_block_read4(read_write image2d_t image, int2 coord);
	15996	uint8 __ovld __conv intel_sub_group_block_read8(read_write image2d_t image, int2 coord);
	15997	#endif // (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	15998
	15999	uint __ovld __conv intel_sub_group_block_read( const __global uint* p );
	16000	uint2 __ovld __conv intel_sub_group_block_read2( const __global uint* p );
	16001	uint4 __ovld __conv intel_sub_group_block_read4( const __global uint* p );
	16002	uint8 __ovld __conv intel_sub_group_block_read8( const __global uint* p );
	16003
	16004	void __ovld __conv intel_sub_group_block_write(write_only image2d_t image, int2 coord, uint data);
	16005	void __ovld __conv intel_sub_group_block_write2(write_only image2d_t image, int2 coord, uint2 data);
	16006	void __ovld __conv intel_sub_group_block_write4(write_only image2d_t image, int2 coord, uint4 data);
	16007	void __ovld __conv intel_sub_group_block_write8(write_only image2d_t image, int2 coord, uint8 data);
	16008
	16009	#if (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16010	void __ovld __conv intel_sub_group_block_write(read_write image2d_t image, int2 coord, uint data);
	16011	void __ovld __conv intel_sub_group_block_write2(read_write image2d_t image, int2 coord, uint2 data);
	16012	void __ovld __conv intel_sub_group_block_write4(read_write image2d_t image, int2 coord, uint4 data);
	16013	void __ovld __conv intel_sub_group_block_write8(read_write image2d_t image, int2 coord, uint8 data);
	16014	#endif // (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16015
	16016	void __ovld __conv intel_sub_group_block_write( __global uint* p, uint data );
	16017	void __ovld __conv intel_sub_group_block_write2( __global uint* p, uint2 data );
	16018	void __ovld __conv intel_sub_group_block_write4( __global uint* p, uint4 data );
	16019	void __ovld __conv intel_sub_group_block_write8( __global uint* p, uint8 data );
	16020
	16021	#ifdef cl_khr_fp16
	16022	half __ovld __conv intel_sub_group_shuffle( half x, uint c );
	16023	half __ovld __conv intel_sub_group_shuffle_down( half prev, half cur, uint c );
	16024	half __ovld __conv intel_sub_group_shuffle_up( half prev, half cur, uint c );
	16025	half __ovld __conv intel_sub_group_shuffle_xor( half x, uint c );
	16026	#endif
	16027
	16028	#if defined(cl_khr_fp64)
	16029	double __ovld __conv intel_sub_group_shuffle( double x, uint c );
	16030	double __ovld __conv intel_sub_group_shuffle_down( double prev, double cur, uint c );
	16031	double __ovld __conv intel_sub_group_shuffle_up( double prev, double cur, uint c );
	16032	double __ovld __conv intel_sub_group_shuffle_xor( double x, uint c );
	16033	#endif
	16034
	16035	#endif //cl_intel_subgroups
	16036
	16037	#if defined(cl_intel_subgroups_short)
	16038	short __ovld __conv intel_sub_group_broadcast( short x, uint sub_group_local_id );
	16039	short2 __ovld __conv intel_sub_group_broadcast( short2 x, uint sub_group_local_id );
	16040	short3 __ovld __conv intel_sub_group_broadcast( short3 x, uint sub_group_local_id );
	16041	short4 __ovld __conv intel_sub_group_broadcast( short4 x, uint sub_group_local_id );
	16042	short8 __ovld __conv intel_sub_group_broadcast( short8 x, uint sub_group_local_id );
	16043
	16044	ushort __ovld __conv intel_sub_group_broadcast( ushort x, uint sub_group_local_id );
	16045	ushort2 __ovld __conv intel_sub_group_broadcast( ushort2 x, uint sub_group_local_id );
	16046	ushort3 __ovld __conv intel_sub_group_broadcast( ushort3 x, uint sub_group_local_id );
	16047	ushort4 __ovld __conv intel_sub_group_broadcast( ushort4 x, uint sub_group_local_id );
	16048	ushort8 __ovld __conv intel_sub_group_broadcast( ushort8 x, uint sub_group_local_id );
	16049
	16050	short __ovld __conv intel_sub_group_shuffle( short x, uint c );
	16051	short2 __ovld __conv intel_sub_group_shuffle( short2 x, uint c );
	16052	short3 __ovld __conv intel_sub_group_shuffle( short3 x, uint c );
	16053	short4 __ovld __conv intel_sub_group_shuffle( short4 x, uint c );
	16054	short8 __ovld __conv intel_sub_group_shuffle( short8 x, uint c );
	16055	short16 __ovld __conv intel_sub_group_shuffle( short16 x, uint c);
	16056
	16057	ushort __ovld __conv intel_sub_group_shuffle( ushort x, uint c );
	16058	ushort2 __ovld __conv intel_sub_group_shuffle( ushort2 x, uint c );
	16059	ushort3 __ovld __conv intel_sub_group_shuffle( ushort3 x, uint c );
	16060	ushort4 __ovld __conv intel_sub_group_shuffle( ushort4 x, uint c );
	16061	ushort8 __ovld __conv intel_sub_group_shuffle( ushort8 x, uint c );
	16062	ushort16 __ovld __conv intel_sub_group_shuffle( ushort16 x, uint c );
	16063
	16064	short __ovld __conv intel_sub_group_shuffle_down( short cur, short next, uint c );
	16065	short2 __ovld __conv intel_sub_group_shuffle_down( short2 cur, short2 next, uint c );
	16066	short3 __ovld __conv intel_sub_group_shuffle_down( short3 cur, short3 next, uint c );
	16067	short4 __ovld __conv intel_sub_group_shuffle_down( short4 cur, short4 next, uint c );
	16068	short8 __ovld __conv intel_sub_group_shuffle_down( short8 cur, short8 next, uint c );
	16069	short16 __ovld __conv intel_sub_group_shuffle_down( short16 cur, short16 next, uint c );
	16070
	16071	ushort __ovld __conv intel_sub_group_shuffle_down( ushort cur, ushort next, uint c );
	16072	ushort2 __ovld __conv intel_sub_group_shuffle_down( ushort2 cur, ushort2 next, uint c );
	16073	ushort3 __ovld __conv intel_sub_group_shuffle_down( ushort3 cur, ushort3 next, uint c );
	16074	ushort4 __ovld __conv intel_sub_group_shuffle_down( ushort4 cur, ushort4 next, uint c );
	16075	ushort8 __ovld __conv intel_sub_group_shuffle_down( ushort8 cur, ushort8 next, uint c );
	16076	ushort16 __ovld __conv intel_sub_group_shuffle_down( ushort16 cur, ushort16 next, uint c );
	16077
	16078	short __ovld __conv intel_sub_group_shuffle_up( short cur, short next, uint c );
	16079	short2 __ovld __conv intel_sub_group_shuffle_up( short2 cur, short2 next, uint c );
	16080	short3 __ovld __conv intel_sub_group_shuffle_up( short3 cur, short3 next, uint c );
	16081	short4 __ovld __conv intel_sub_group_shuffle_up( short4 cur, short4 next, uint c );
	16082	short8 __ovld __conv intel_sub_group_shuffle_up( short8 cur, short8 next, uint c );
	16083	short16 __ovld __conv intel_sub_group_shuffle_up( short16 cur, short16 next, uint c );
	16084
	16085	ushort __ovld __conv intel_sub_group_shuffle_up( ushort cur, ushort next, uint c );
	16086	ushort2 __ovld __conv intel_sub_group_shuffle_up( ushort2 cur, ushort2 next, uint c );
	16087	ushort3 __ovld __conv intel_sub_group_shuffle_up( ushort3 cur, ushort3 next, uint c );
	16088	ushort4 __ovld __conv intel_sub_group_shuffle_up( ushort4 cur, ushort4 next, uint c );
	16089	ushort8 __ovld __conv intel_sub_group_shuffle_up( ushort8 cur, ushort8 next, uint c );
	16090	ushort16 __ovld __conv intel_sub_group_shuffle_up( ushort16 cur, ushort16 next, uint c );
	16091
	16092	short __ovld __conv intel_sub_group_shuffle_xor( short x, uint c );
	16093	short2 __ovld __conv intel_sub_group_shuffle_xor( short2 x, uint c );
	16094	short3 __ovld __conv intel_sub_group_shuffle_xor( short3 x, uint c );
	16095	short4 __ovld __conv intel_sub_group_shuffle_xor( short4 x, uint c );
	16096	short8 __ovld __conv intel_sub_group_shuffle_xor( short8 x, uint c );
	16097	short16 __ovld __conv intel_sub_group_shuffle_xor( short16 x, uint c );
	16098
	16099	ushort __ovld __conv intel_sub_group_shuffle_xor( ushort x, uint c );
	16100	ushort2 __ovld __conv intel_sub_group_shuffle_xor( ushort2 x, uint c );
	16101	ushort3 __ovld __conv intel_sub_group_shuffle_xor( ushort3 x, uint c );
	16102	ushort4 __ovld __conv intel_sub_group_shuffle_xor( ushort4 x, uint c );
	16103	ushort8 __ovld __conv intel_sub_group_shuffle_xor( ushort8 x, uint c );
	16104	ushort16 __ovld __conv intel_sub_group_shuffle_xor( ushort16 x, uint c );
	16105
	16106	short __ovld __conv intel_sub_group_reduce_add( short x );
	16107	ushort __ovld __conv intel_sub_group_reduce_add( ushort x );
	16108	short __ovld __conv intel_sub_group_reduce_min( short x );
	16109	ushort __ovld __conv intel_sub_group_reduce_min( ushort x );
	16110	short __ovld __conv intel_sub_group_reduce_max( short x );
	16111	ushort __ovld __conv intel_sub_group_reduce_max( ushort x );
	16112
	16113	short __ovld __conv intel_sub_group_scan_exclusive_add( short x );
	16114	ushort __ovld __conv intel_sub_group_scan_exclusive_add( ushort x );
	16115	short __ovld __conv intel_sub_group_scan_exclusive_min( short x );
	16116	ushort __ovld __conv intel_sub_group_scan_exclusive_min( ushort x );
	16117	short __ovld __conv intel_sub_group_scan_exclusive_max( short x );
	16118	ushort __ovld __conv intel_sub_group_scan_exclusive_max( ushort x );
	16119
	16120	short __ovld __conv intel_sub_group_scan_inclusive_add( short x );
	16121	ushort __ovld __conv intel_sub_group_scan_inclusive_add( ushort x );
	16122	short __ovld __conv intel_sub_group_scan_inclusive_min( short x );
	16123	ushort __ovld __conv intel_sub_group_scan_inclusive_min( ushort x );
	16124	short __ovld __conv intel_sub_group_scan_inclusive_max( short x );
	16125	ushort __ovld __conv intel_sub_group_scan_inclusive_max( ushort x );
	16126
	16127	uint __ovld __conv intel_sub_group_block_read_ui( read_only image2d_t image, int2 byte_coord );
	16128	uint2 __ovld __conv intel_sub_group_block_read_ui2( read_only image2d_t image, int2 byte_coord );
	16129	uint4 __ovld __conv intel_sub_group_block_read_ui4( read_only image2d_t image, int2 byte_coord );
	16130	uint8 __ovld __conv intel_sub_group_block_read_ui8( read_only image2d_t image, int2 byte_coord );
	16131
	16132	#if (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16133	uint __ovld __conv intel_sub_group_block_read_ui( read_write image2d_t image, int2 byte_coord );
	16134	uint2 __ovld __conv intel_sub_group_block_read_ui2( read_write image2d_t image, int2 byte_coord );
	16135	uint4 __ovld __conv intel_sub_group_block_read_ui4( read_write image2d_t image, int2 byte_coord );
	16136	uint8 __ovld __conv intel_sub_group_block_read_ui8( read_write image2d_t image, int2 byte_coord );
	16137	#endif // (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16138
	16139	uint __ovld __conv intel_sub_group_block_read_ui( const __global uint* p );
	16140	uint2 __ovld __conv intel_sub_group_block_read_ui2( const __global uint* p );
	16141	uint4 __ovld __conv intel_sub_group_block_read_ui4( const __global uint* p );
	16142	uint8 __ovld __conv intel_sub_group_block_read_ui8( const __global uint* p );
	16143
	16144	void __ovld __conv intel_sub_group_block_write_ui( read_only image2d_t image, int2 byte_coord, uint data );
	16145	void __ovld __conv intel_sub_group_block_write_ui2( read_only image2d_t image, int2 byte_coord, uint2 data );
	16146	void __ovld __conv intel_sub_group_block_write_ui4( read_only image2d_t image, int2 byte_coord, uint4 data );
	16147	void __ovld __conv intel_sub_group_block_write_ui8( read_only image2d_t image, int2 byte_coord, uint8 data );
	16148
	16149	#if (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16150	void __ovld __conv intel_sub_group_block_write_ui( read_write image2d_t image, int2 byte_coord, uint data );
	16151	void __ovld __conv intel_sub_group_block_write_ui2( read_write image2d_t image, int2 byte_coord, uint2 data );
	16152	void __ovld __conv intel_sub_group_block_write_ui4( read_write image2d_t image, int2 byte_coord, uint4 data );
	16153	void __ovld __conv intel_sub_group_block_write_ui8( read_write image2d_t image, int2 byte_coord, uint8 data );
	16154	#endif // (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16155
	16156	void __ovld __conv intel_sub_group_block_write_ui( __global uint* p, uint data );
	16157	void __ovld __conv intel_sub_group_block_write_ui2( __global uint* p, uint2 data );
	16158	void __ovld __conv intel_sub_group_block_write_ui4( __global uint* p, uint4 data );
	16159	void __ovld __conv intel_sub_group_block_write_ui8( __global uint* p, uint8 data );
	16160
	16161	ushort __ovld __conv intel_sub_group_block_read_us( read_only image2d_t image, int2 coord );
	16162	ushort2 __ovld __conv intel_sub_group_block_read_us2( read_only image2d_t image, int2 coord );
	16163	ushort4 __ovld __conv intel_sub_group_block_read_us4( read_only image2d_t image, int2 coord );
	16164	ushort8 __ovld __conv intel_sub_group_block_read_us8( read_only image2d_t image, int2 coord );
	16165
	16166	#if (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16167	ushort __ovld __conv intel_sub_group_block_read_us(read_write image2d_t image, int2 coord);
	16168	ushort2 __ovld __conv intel_sub_group_block_read_us2(read_write image2d_t image, int2 coord);
	16169	ushort4 __ovld __conv intel_sub_group_block_read_us4(read_write image2d_t image, int2 coord);
	16170	ushort8 __ovld __conv intel_sub_group_block_read_us8(read_write image2d_t image, int2 coord);
	16171	#endif // (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16172
	16173	ushort __ovld __conv intel_sub_group_block_read_us( const __global ushort* p );
	16174	ushort2 __ovld __conv intel_sub_group_block_read_us2( const __global ushort* p );
	16175	ushort4 __ovld __conv intel_sub_group_block_read_us4( const __global ushort* p );
	16176	ushort8 __ovld __conv intel_sub_group_block_read_us8( const __global ushort* p );
	16177
	16178	void __ovld __conv intel_sub_group_block_write_us(write_only image2d_t image, int2 coord, ushort data);
	16179	void __ovld __conv intel_sub_group_block_write_us2(write_only image2d_t image, int2 coord, ushort2 data);
	16180	void __ovld __conv intel_sub_group_block_write_us4(write_only image2d_t image, int2 coord, ushort4 data);
	16181	void __ovld __conv intel_sub_group_block_write_us8(write_only image2d_t image, int2 coord, ushort8 data);
	16182
	16183	#if (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16184	void __ovld __conv intel_sub_group_block_write_us(read_write image2d_t image, int2 coord, ushort data);
	16185	void __ovld __conv intel_sub_group_block_write_us2(read_write image2d_t image, int2 coord, ushort2 data);
	16186	void __ovld __conv intel_sub_group_block_write_us4(read_write image2d_t image, int2 coord, ushort4 data);
	16187	void __ovld __conv intel_sub_group_block_write_us8(read_write image2d_t image, int2 coord, ushort8 data);
	16188	#endif // (__OPENCL_C_VERSION__ >= CL_VERSION_2_0)
	16189
	16190	void __ovld __conv intel_sub_group_block_write_us( __global ushort* p, ushort data );
	16191	void __ovld __conv intel_sub_group_block_write_us2( __global ushort* p, ushort2 data );
	16192	void __ovld __conv intel_sub_group_block_write_us4( __global ushort* p, ushort4 data );
	16193	void __ovld __conv intel_sub_group_block_write_us8( __global ushort* p, ushort8 data );
	16194	#endif // cl_intel_subgroups_short
	16195
15889	16196	#ifdef cl_amd_media_ops
15890	16197	uint __ovld amd_bitalign(uint a, uint b, uint c);
15891	16198	uint2 __ovld amd_bitalign(uint2 a, uint2 b, uint2 c);

c_headers/pmmintrin.h+3-3

...	...	@@ -115,8 +115,8 @@ _mm_hsub_ps(__m128 __a, __m128 __b)
115	115	return __builtin_ia32_hsubps((__v4sf)__a, (__v4sf)__b);
116	116	}
117	117
118		/// \brief Moves and duplicates high-order (odd-indexed) values from a 128-bit
119		/// vector of [4 x float] to float values stored in a 128-bit vector of
	118	/// \brief Moves and duplicates odd-indexed values from a 128-bit vector
	119	/// of [4 x float] to float values stored in a 128-bit vector of
120	120	/// [4 x float].
121	121	///
122	122	/// \headerfile <x86intrin.h>
...	...	@@ -137,7 +137,7 @@ _mm_movehdup_ps(__m128 __a)
137	137	return __builtin_shufflevector((__v4sf)__a, (__v4sf)__a, 1, 1, 3, 3);
138	138	}
139	139
140		/// \brief Duplicates low-order (even-indexed) values from a 128-bit vector of
	140	/// \brief Duplicates even-indexed values from a 128-bit vector of
141	141	/// [4 x float] to float values stored in a 128-bit vector of [4 x float].
142	142	///
143	143	/// \headerfile <x86intrin.h>

c_headers/smmintrin.h+3-3

...	...	@@ -648,7 +648,7 @@ _mm_mul_epi32 (__m128i __V1, __m128i __V2)
648	648	/// input vectors are used as an input for dot product; otherwise that input
649	649	/// is treated as zero. Bits [1:0] determine which elements of the result
650	650	/// will receive a copy of the final dot product, with bit [0] corresponding
651		/// to the lowest element and bit [3] corresponding to the highest element of
	651	/// to the lowest element and bit [1] corresponding to the highest element of
652	652	/// each [2 x double] vector. If a bit is set, the dot product is returned in
653	653	/// the corresponding element; otherwise that element is set to zero.
654	654	#define _mm_dp_pd(X, Y, M) __extension__ ({\
...	...	@@ -866,8 +866,8 @@ _mm_max_epu32 (__m128i __V1, __m128i __V2)
866	866	/// 11: Copies the selected bits from \a Y to result bits [127:96]. \n
867	867	/// Bits[3:0]: If any of these bits are set, the corresponding result
868	868	/// element is cleared.
869		/// \returns A 128-bit vector of [4 x float] containing the copied single-
870		/// precision floating point elements from the operands.
	869	/// \returns A 128-bit vector of [4 x float] containing the copied
	870	/// single-precision floating point elements from the operands.
871	871	#define _mm_insert_ps(X, Y, N) __builtin_ia32_insertps128((X), (Y), (N))
872	872
873	873	/// \brief Extracts a 32-bit integer from a 128-bit vector of [4 x float] and

c_headers/stdbool.h+4-1

...	...	@@ -32,12 +32,15 @@
32	32	#define true 1
33	33	#define false 0
34	34	#elif defined(__GNUC__) && !defined(__STRICT_ANSI__)
35		/* Define _Bool, bool, false, true as a GNU extension. */
	35	/* Define _Bool as a GNU extension. */
36	36	#define _Bool bool
	37	#if __cplusplus < 201103L
	38	/* For C++98, define bool, false, true as a GNU extension. */
37	39	#define bool bool
38	40	#define false false
39	41	#define true true
40	42	#endif
	43	#endif
41	44
42	45	#define __bool_true_false_are_defined 1
43	46

c_headers/vaesintrin.h created+98

...	...	@@ -0,0 +1,98 @@
	1	/*===------------------ vaesintrin.h - VAES intrinsics ---------------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <vaesintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __VAESINTRIN_H
	29	#define __VAESINTRIN_H
	30
	31	/* Default attributes for YMM forms. */
	32	#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("vaes")))
	33
	34	/* Default attributes for ZMM forms. */
	35	#define __DEFAULT_FN_ATTRS_F __attribute__((__always_inline__, __nodebug__, __target__("avx512f,vaes")))
	36
	37
	38	static __inline__ __m256i __DEFAULT_FN_ATTRS
	39	_mm256_aesenc_epi128(__m256i __A, __m256i __B)
	40	{
	41	return (__m256i) __builtin_ia32_aesenc256((__v4di) __A,
	42	(__v4di) __B);
	43	}
	44
	45	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	46	_mm512_aesenc_epi128(__m512i __A, __m512i __B)
	47	{
	48	return (__m512i) __builtin_ia32_aesenc512((__v8di) __A,
	49	(__v8di) __B);
	50	}
	51
	52	static __inline__ __m256i __DEFAULT_FN_ATTRS
	53	_mm256_aesdec_epi128(__m256i __A, __m256i __B)
	54	{
	55	return (__m256i) __builtin_ia32_aesdec256((__v4di) __A,
	56	(__v4di) __B);
	57	}
	58
	59	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	60	_mm512_aesdec_epi128(__m512i __A, __m512i __B)
	61	{
	62	return (__m512i) __builtin_ia32_aesdec512((__v8di) __A,
	63	(__v8di) __B);
	64	}
	65
	66	static __inline__ __m256i __DEFAULT_FN_ATTRS
	67	_mm256_aesenclast_epi128(__m256i __A, __m256i __B)
	68	{
	69	return (__m256i) __builtin_ia32_aesenclast256((__v4di) __A,
	70	(__v4di) __B);
	71	}
	72
	73	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	74	_mm512_aesenclast_epi128(__m512i __A, __m512i __B)
	75	{
	76	return (__m512i) __builtin_ia32_aesenclast512((__v8di) __A,
	77	(__v8di) __B);
	78	}
	79
	80	static __inline__ __m256i __DEFAULT_FN_ATTRS
	81	_mm256_aesdeclast_epi128(__m256i __A, __m256i __B)
	82	{
	83	return (__m256i) __builtin_ia32_aesdeclast256((__v4di) __A,
	84	(__v4di) __B);
	85	}
	86
	87	static __inline__ __m512i __DEFAULT_FN_ATTRS_F
	88	_mm512_aesdeclast_epi128(__m512i __A, __m512i __B)
	89	{
	90	return (__m512i) __builtin_ia32_aesdeclast512((__v8di) __A,
	91	(__v8di) __B);
	92	}
	93
	94
	95	#undef __DEFAULT_FN_ATTRS
	96	#undef __DEFAULT_FN_ATTRS_F
	97
	98	#endif

c_headers/vpclmulqdqintrin.h created+42

...	...	@@ -0,0 +1,42 @@
	1	/*===------------ vpclmulqdqintrin.h - VPCLMULQDQ intrinsics ---------------===
	2	*
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a copy
	5	* of this software and associated documentation files (the "Software"), to deal
	6	* in the Software without restriction, including without limitation the rights
	7	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	8	* copies of the Software, and to permit persons to whom the Software is
	9	* furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	20	* THE SOFTWARE.
	21	*
	22	*===-----------------------------------------------------------------------===
	23	*/
	24	#ifndef __IMMINTRIN_H
	25	#error "Never use <vpclmulqdqintrin.h> directly; include <immintrin.h> instead."
	26	#endif
	27
	28	#ifndef __VPCLMULQDQINTRIN_H
	29	#define __VPCLMULQDQINTRIN_H
	30
	31	#define _mm256_clmulepi64_epi128(A, B, I) __extension__ ({ \
	32	(__m256i)__builtin_ia32_pclmulqdq256((__v4di)(__m256i)(A), \
	33	(__v4di)(__m256i)(B), \
	34	(char)(I)); })
	35
	36	#define _mm512_clmulepi64_epi128(A, B, I) __extension__ ({ \
	37	(__m512i)__builtin_ia32_pclmulqdq512((__v8di)(__m512i)(A), \
	38	(__v8di)(__m512i)(B), \
	39	(char)(I)); })
	40
	41	#endif // __VPCLMULQDQINTRIN_H
	42

c_headers/xmmintrin.h+7-4

...	...	@@ -2035,9 +2035,11 @@ _mm_storer_ps(float *__p, __m128 __a)
2035	2035	_mm_store_ps(__p, __a);
2036	2036	}
2037	2037
2038		#define _MM_HINT_T0 3
2039		#define _MM_HINT_T1 2
2040		#define _MM_HINT_T2 1
	2038	#define _MM_HINT_ET0 7
	2039	#define _MM_HINT_ET1 6
	2040	#define _MM_HINT_T0 3
	2041	#define _MM_HINT_T1 2
	2042	#define _MM_HINT_T2 1
2041	2043	#define _MM_HINT_NTA 0
2042	2044
2043	2045	#ifndef _MSC_VER
...	...	@@ -2068,7 +2070,8 @@ _mm_storer_ps(float *__p, __m128 __a)
2068	2070	/// be generated. \n
2069	2071	/// _MM_HINT_T2: Move data using the T2 hint. The PREFETCHT2 instruction will
2070	2072	/// be generated.
2071		#define _mm_prefetch(a, sel) (__builtin_prefetch((void *)(a), 0, (sel)))
	2073	#define _mm_prefetch(a, sel) (__builtin_prefetch((void *)(a), \
	2074	((sel) >> 2) & 1, (sel) & 0x3))
2072	2075	#endif
2073	2076
2074	2077	/// \brief Stores a 64-bit integer in the specified aligned memory location. To