authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-01-17 06:54:56+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-04-22 15:31:57+02:00
log5110fadf3a22e7a933e0353f9078674da9bf72fe
treead1434121d25f70548ff1bbcaf599ed5069da0a1
parentd629b4c98bd35a05d9f4bf5ec2db287cd26cd644
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: update CPU and feature data to LLVM 22

21 files changed, 1971 insertions(+), 395 deletions(-)

lib/compiler/aro/aro/Compilation.zig-3
......@@ -498,7 +498,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
498498 .{ .fma, "__FMA__" },
499499 .{ .f16c, "__F16C__" },
500500 .{ .gfni, "__GFNI__" },
501 .{ .evex512, "__EVEX512__" },
502501
503502 .{ .avx10_1, "__AVX10_1__" },
504503 .{ .avx10_1, "__AVX10_1_512__" },
......@@ -560,7 +559,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
560559 .{ .amx_complex, "__AMX_COMPLEX__" },
561560 .{ .amx_fp8, "__AMX_FP8__" },
562561 .{ .amx_movrs, "__AMX_MOVRS__" },
563 .{ .amx_transpose, "__AMX_TRANSPOSE__" },
564562 .{ .amx_avx512, "__AMX_AVX512__" },
565563 .{ .amx_tf32, "__AMX_TF32__" },
566564 .{ .cmpccxadd, "__CMPCCXADD__" },
......@@ -798,7 +796,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
798796 .{ .fullfp16, "FP16_SCALAR_ARITHMETIC" },
799797 .{ .dotprod, "DOTPROD" },
800798 .{ .mte, "MEMORY_TAGGING" },
801 .{ .tme, "TME" },
802799 .{ .i8mm, "MATMUL_INT8" },
803800 .{ .lse, "ATOMICS" },
804801 .{ .f64mm, "SVE_MATMUL_FP64" },
lib/std/Target.zig+1-1
......@@ -1224,7 +1224,7 @@ pub const Cpu = struct {
12241224 pub const Set = struct {
12251225 ints: [usize_count]usize,
12261226
1227 pub const needed_bit_count = 317;
1227 pub const needed_bit_count = 347;
12281228 pub const byte_count = (needed_bit_count + 7) / 8;
12291229 pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize);
12301230 pub const Index = std.math.Log2Int(std.meta.Int(.unsigned, usize_count * @bitSizeOf(usize)));
lib/std/Target/aarch64.zig+620-77
......@@ -9,6 +9,7 @@ pub const Feature = enum {
99 addr_lsl_slow_14,
1010 aes,
1111 aggressive_fma,
12 aggressive_interleaving,
1213 alternate_sextload_cvt_f32_pattern,
1314 altnzcv,
1415 alu_lsl_fast,
......@@ -22,6 +23,7 @@ pub const Feature = enum {
2223 bf16,
2324 brbe,
2425 bti,
26 btie,
2527 call_saved_x10,
2628 call_saved_x11,
2729 call_saved_x12,
......@@ -36,6 +38,7 @@ pub const Feature = enum {
3638 ccpp,
3739 chk,
3840 clrbhb,
41 cmh,
3942 cmp_bcc_fusion,
4043 cmpbr,
4144 complxnum,
......@@ -48,7 +51,9 @@ pub const Feature = enum {
4851 disable_fast_inc_vl,
4952 disable_latency_sched_heuristic,
5053 disable_ldp,
54 disable_maximize_scalable_bandwidth,
5155 disable_stp,
56 disable_unpredicated_ld_st_lower,
5257 dit,
5358 dotprod,
5459 ecv,
......@@ -58,6 +63,9 @@ pub const Feature = enum {
5863 ete,
5964 execute_only,
6065 exynos_cheap_as_move,
66 f16f32dot,
67 f16f32mm,
68 f16mm,
6169 f32mm,
6270 f64mm,
6371 f8f16mm,
......@@ -86,7 +94,9 @@ pub const Feature = enum {
8694 fuse_arith_logic,
8795 fuse_crypto_eor,
8896 fuse_csel,
97 fuse_cset,
8998 fuse_literals,
99 gcie,
90100 gcs,
91101 harden_sls_blr,
92102 harden_sls_nocomdat,
......@@ -99,22 +109,27 @@ pub const Feature = enum {
99109 ldp_aligned_only,
100110 lor,
101111 ls64,
112 lscp,
102113 lse,
103114 lse128,
104115 lse2,
105116 lsfe,
106117 lsui,
107118 lut,
119 max_interleave_factor_4,
108120 mec,
109121 mops,
122 mops_go,
110123 mpam,
124 mpamv2,
111125 mte,
126 mtetc,
112127 neon,
113128 nmi,
114129 no_bti_at_return_twice,
115130 no_neg_immediates,
116131 no_sve_fp_ld1r,
117 no_zcz_fp,
132 no_zcz_fpr64,
118133 nv,
119134 occmo,
120135 olympus,
......@@ -125,6 +140,7 @@ pub const Feature = enum {
125140 pauth_lr,
126141 pcdphint,
127142 perfmon,
143 poe2,
128144 pops,
129145 predictable_select_expensive,
130146 predres,
......@@ -174,6 +190,7 @@ pub const Feature = enum {
174190 sme2,
175191 sme2p1,
176192 sme2p2,
193 sme2p3,
177194 sme_b16b16,
178195 sme_f16f16,
179196 sme_f64f64,
......@@ -206,19 +223,22 @@ pub const Feature = enum {
206223 sve2_sm4,
207224 sve2p1,
208225 sve2p2,
226 sve2p3,
209227 sve_aes,
210228 sve_aes2,
211229 sve_b16b16,
230 sve_b16mm,
212231 sve_bfscale,
213232 sve_bitperm,
214233 sve_f16f32mm,
215234 sve_sha3,
216235 sve_sm4,
217236 tagged_globals,
237 tev,
218238 the,
219239 tlb_rmi,
240 tlbid,
220241 tlbiw,
221 tme,
222242 tpidr_el1,
223243 tpidr_el2,
224244 tpidr_el3,
......@@ -230,6 +250,7 @@ pub const Feature = enum {
230250 use_fixed_over_scalable_if_equal_cost,
231251 use_postra_scheduler,
232252 use_reciprocal_square_root,
253 use_wzr_to_vec_move,
233254 v8_1a,
234255 v8_2a,
235256 v8_3a,
......@@ -247,17 +268,20 @@ pub const Feature = enum {
247268 v9_4a,
248269 v9_5a,
249270 v9_6a,
271 v9_7a,
250272 v9a,
251273 vh,
252274 wfxt,
253275 xs,
276 zcm_fpr128,
254277 zcm_fpr32,
255278 zcm_fpr64,
256279 zcm_gpr32,
257280 zcm_gpr64,
258 zcz,
259281 zcz_fp_workaround,
260 zcz_gp,
282 zcz_fpr128,
283 zcz_gpr32,
284 zcz_gpr64,
261285};
262286
263287pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
......@@ -274,9 +298,12 @@ pub const all_features = blk: {
274298 .llvm_name = "a320",
275299 .description = "Cortex-A320 ARM processors",
276300 .dependencies = featureSet(&[_]Feature{
301 .aggressive_interleaving,
277302 .fuse_adrp_add,
278303 .fuse_aes,
304 .use_fixed_over_scalable_if_equal_cost,
279305 .use_postra_scheduler,
306 .use_wzr_to_vec_move,
280307 }),
281308 };
282309 result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{
......@@ -296,6 +323,11 @@ pub const all_features = blk: {
296323 .description = "Enable Aggressive FMA for floating-point.",
297324 .dependencies = featureSet(&[_]Feature{}),
298325 };
326 result[@intFromEnum(Feature.aggressive_interleaving)] = .{
327 .llvm_name = "aggressive-interleaving",
328 .description = "Make use of aggressive interleaving during vectorization",
329 .dependencies = featureSet(&[_]Feature{}),
330 };
299331 result[@intFromEnum(Feature.alternate_sextload_cvt_f32_pattern)] = .{
300332 .llvm_name = "alternate-sextload-cvt-f32-pattern",
301333 .description = "Use alternative pattern for sextload convert to f32",
......@@ -367,6 +399,11 @@ pub const all_features = blk: {
367399 .description = "Enable Branch Target Identification",
368400 .dependencies = featureSet(&[_]Feature{}),
369401 };
402 result[@intFromEnum(Feature.btie)] = .{
403 .llvm_name = "btie",
404 .description = "Enable Enhanced Branch Target Identification extension",
405 .dependencies = featureSet(&[_]Feature{}),
406 };
370407 result[@intFromEnum(Feature.call_saved_x10)] = .{
371408 .llvm_name = "call-saved-x10",
372409 .description = "Make X10 callee saved.",
......@@ -439,6 +476,11 @@ pub const all_features = blk: {
439476 .description = "Enable Clear BHB instruction",
440477 .dependencies = featureSet(&[_]Feature{}),
441478 };
479 result[@intFromEnum(Feature.cmh)] = .{
480 .llvm_name = "cmh",
481 .description = "Enable Armv9.7-A Contention Management Hints",
482 .dependencies = featureSet(&[_]Feature{}),
483 };
442484 result[@intFromEnum(Feature.cmp_bcc_fusion)] = .{
443485 .llvm_name = "cmp-bcc-fusion",
444486 .description = "CPU fuses cmp+bcc operations",
......@@ -506,11 +548,21 @@ pub const all_features = blk: {
506548 .description = "Do not emit ldp",
507549 .dependencies = featureSet(&[_]Feature{}),
508550 };
551 result[@intFromEnum(Feature.disable_maximize_scalable_bandwidth)] = .{
552 .llvm_name = "disable-maximize-scalable-bandwidth",
553 .description = "Determine the maximum scalable vector length for a loop by the largest scalar type rather than the smallest",
554 .dependencies = featureSet(&[_]Feature{}),
555 };
509556 result[@intFromEnum(Feature.disable_stp)] = .{
510557 .llvm_name = "disable-stp",
511558 .description = "Do not emit stp",
512559 .dependencies = featureSet(&[_]Feature{}),
513560 };
561 result[@intFromEnum(Feature.disable_unpredicated_ld_st_lower)] = .{
562 .llvm_name = "disable-unpredicated-ld-st-lower",
563 .description = "Disable lowering unpredicated loads/stores as LDR/STR",
564 .dependencies = featureSet(&[_]Feature{}),
565 };
514566 result[@intFromEnum(Feature.dit)] = .{
515567 .llvm_name = "dit",
516568 .description = "Enable Armv8.4-A Data Independent Timing instructions",
......@@ -560,6 +612,30 @@ pub const all_features = blk: {
560612 .description = "Use Exynos specific handling of cheap instructions",
561613 .dependencies = featureSet(&[_]Feature{}),
562614 };
615 result[@intFromEnum(Feature.f16f32dot)] = .{
616 .llvm_name = "f16f32dot",
617 .description = "Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision",
618 .dependencies = featureSet(&[_]Feature{
619 .fullfp16,
620 .neon,
621 }),
622 };
623 result[@intFromEnum(Feature.f16f32mm)] = .{
624 .llvm_name = "f16f32mm",
625 .description = "Enable Armv9.7-A Advanced SIMD half-precision matrix multiply-accumulate to single-precision",
626 .dependencies = featureSet(&[_]Feature{
627 .fullfp16,
628 .neon,
629 }),
630 };
631 result[@intFromEnum(Feature.f16mm)] = .{
632 .llvm_name = "f16mm",
633 .description = "Enable Armv9.7-A non-widening half-precision matrix multiply-accumulate",
634 .dependencies = featureSet(&[_]Feature{
635 .fullfp16,
636 .neon,
637 }),
638 };
563639 result[@intFromEnum(Feature.f32mm)] = .{
564640 .llvm_name = "f32mm",
565641 .description = "Enable Matrix Multiply FP32 Extension",
......@@ -729,7 +805,12 @@ pub const all_features = blk: {
729805 };
730806 result[@intFromEnum(Feature.fuse_csel)] = .{
731807 .llvm_name = "fuse-csel",
732 .description = "CPU fuses conditional select operations",
808 .description = "CPU can fuse CMP and CSEL operations",
809 .dependencies = featureSet(&[_]Feature{}),
810 };
811 result[@intFromEnum(Feature.fuse_cset)] = .{
812 .llvm_name = "fuse-cset",
813 .description = "CPU can fuse CMP and CSET operations",
733814 .dependencies = featureSet(&[_]Feature{}),
734815 };
735816 result[@intFromEnum(Feature.fuse_literals)] = .{
......@@ -737,6 +818,11 @@ pub const all_features = blk: {
737818 .description = "CPU fuses literal generation operations",
738819 .dependencies = featureSet(&[_]Feature{}),
739820 };
821 result[@intFromEnum(Feature.gcie)] = .{
822 .llvm_name = "gcie",
823 .description = "Enable GICv5 (Generic Interrupt Controller) CPU Interface Extension",
824 .dependencies = featureSet(&[_]Feature{}),
825 };
740826 result[@intFromEnum(Feature.gcs)] = .{
741827 .llvm_name = "gcs",
742828 .description = "Enable Armv9.4-A Guarded Call Stack Extension",
......@@ -805,6 +891,11 @@ pub const all_features = blk: {
805891 .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension",
806892 .dependencies = featureSet(&[_]Feature{}),
807893 };
894 result[@intFromEnum(Feature.lscp)] = .{
895 .llvm_name = "lscp",
896 .description = "Enable Armv9.7-A Load-acquire and store-release pair extension",
897 .dependencies = featureSet(&[_]Feature{}),
898 };
808899 result[@intFromEnum(Feature.lse)] = .{
809900 .llvm_name = "lse",
810901 .description = "Enable Armv8.1-A Large System Extension (LSE) atomic instructions",
......@@ -841,6 +932,11 @@ pub const all_features = blk: {
841932 .neon,
842933 }),
843934 };
935 result[@intFromEnum(Feature.max_interleave_factor_4)] = .{
936 .llvm_name = "max-interleave-factor-4",
937 .description = "Set the MaxInterleaveFactor to 4 (from the default 2)",
938 .dependencies = featureSet(&[_]Feature{}),
939 };
844940 result[@intFromEnum(Feature.mec)] = .{
845941 .llvm_name = "mec",
846942 .description = "Enable Memory Encryption Contexts Extension",
......@@ -853,16 +949,36 @@ pub const all_features = blk: {
853949 .description = "Enable Armv8.8-A memcpy and memset acceleration instructions",
854950 .dependencies = featureSet(&[_]Feature{}),
855951 };
952 result[@intFromEnum(Feature.mops_go)] = .{
953 .llvm_name = "mops-go",
954 .description = "Enable memset acceleration granule only",
955 .dependencies = featureSet(&[_]Feature{
956 .mops,
957 .mte,
958 }),
959 };
856960 result[@intFromEnum(Feature.mpam)] = .{
857961 .llvm_name = "mpam",
858962 .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension",
859963 .dependencies = featureSet(&[_]Feature{}),
860964 };
965 result[@intFromEnum(Feature.mpamv2)] = .{
966 .llvm_name = "mpamv2",
967 .description = "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions",
968 .dependencies = featureSet(&[_]Feature{}),
969 };
861970 result[@intFromEnum(Feature.mte)] = .{
862971 .llvm_name = "mte",
863972 .description = "Enable Memory Tagging Extension",
864973 .dependencies = featureSet(&[_]Feature{}),
865974 };
975 result[@intFromEnum(Feature.mtetc)] = .{
976 .llvm_name = "mtetc",
977 .description = "Enable Virtual Memory Tagging Extension",
978 .dependencies = featureSet(&[_]Feature{
979 .mte,
980 }),
981 };
866982 result[@intFromEnum(Feature.neon)] = .{
867983 .llvm_name = "neon",
868984 .description = "Enable Advanced SIMD instructions",
......@@ -890,9 +1006,9 @@ pub const all_features = blk: {
8901006 .description = "Avoid using LD1RX instructions for FP",
8911007 .dependencies = featureSet(&[_]Feature{}),
8921008 };
893 result[@intFromEnum(Feature.no_zcz_fp)] = .{
894 .llvm_name = "no-zcz-fp",
895 .description = "Has no zero-cycle zeroing instructions for FP registers",
1009 result[@intFromEnum(Feature.no_zcz_fpr64)] = .{
1010 .llvm_name = "no-zcz-fpr64",
1011 .description = "Has no zero-cycle zeroing instructions for FPR64 registers",
8961012 .dependencies = featureSet(&[_]Feature{}),
8971013 };
8981014 result[@intFromEnum(Feature.nv)] = .{
......@@ -914,6 +1030,7 @@ pub const all_features = blk: {
9141030 .enable_select_opt,
9151031 .fuse_adrp_add,
9161032 .fuse_aes,
1033 .max_interleave_factor_4,
9171034 .predictable_select_expensive,
9181035 .use_fixed_over_scalable_if_equal_cost,
9191036 .use_postra_scheduler,
......@@ -956,6 +1073,11 @@ pub const all_features = blk: {
9561073 .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension",
9571074 .dependencies = featureSet(&[_]Feature{}),
9581075 };
1076 result[@intFromEnum(Feature.poe2)] = .{
1077 .llvm_name = "poe2",
1078 .description = "Enable Stage 1 Permission Overlays Extension 2 instructions",
1079 .dependencies = featureSet(&[_]Feature{}),
1080 };
9591081 result[@intFromEnum(Feature.pops)] = .{
9601082 .llvm_name = "pops",
9611083 .description = "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions",
......@@ -1224,6 +1346,13 @@ pub const all_features = blk: {
12241346 .sme2p1,
12251347 }),
12261348 };
1349 result[@intFromEnum(Feature.sme2p3)] = .{
1350 .llvm_name = "sme2p3",
1351 .description = "Enable Armv9.7-A Scalable Matrix Extension 2.3 instructions",
1352 .dependencies = featureSet(&[_]Feature{
1353 .sme2p2,
1354 }),
1355 };
12271356 result[@intFromEnum(Feature.sme_b16b16)] = .{
12281357 .llvm_name = "sme-b16b16",
12291358 .description = "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions",
......@@ -1447,6 +1576,13 @@ pub const all_features = blk: {
14471576 .sve2p1,
14481577 }),
14491578 };
1579 result[@intFromEnum(Feature.sve2p3)] = .{
1580 .llvm_name = "sve2p3",
1581 .description = "Enable Armv9.7-A Scalable Vector Extension 2.3 instructions",
1582 .dependencies = featureSet(&[_]Feature{
1583 .sve2p2,
1584 }),
1585 };
14501586 result[@intFromEnum(Feature.sve_aes)] = .{
14511587 .llvm_name = "sve-aes",
14521588 .description = "Enable SVE AES and quadword SVE polynomial multiply instructions",
......@@ -1464,6 +1600,13 @@ pub const all_features = blk: {
14641600 .description = "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions",
14651601 .dependencies = featureSet(&[_]Feature{}),
14661602 };
1603 result[@intFromEnum(Feature.sve_b16mm)] = .{
1604 .llvm_name = "sve-b16mm",
1605 .description = "Enable Armv9.7-A SVE non-widening BFloat16 matrix multiply-accumulate",
1606 .dependencies = featureSet(&[_]Feature{
1607 .sve,
1608 }),
1609 };
14671610 result[@intFromEnum(Feature.sve_bfscale)] = .{
14681611 .llvm_name = "sve-bfscale",
14691612 .description = "Enable Armv9.6-A SVE BFloat16 scaling instructions",
......@@ -1500,6 +1643,11 @@ pub const all_features = blk: {
15001643 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
15011644 .dependencies = featureSet(&[_]Feature{}),
15021645 };
1646 result[@intFromEnum(Feature.tev)] = .{
1647 .llvm_name = "tev",
1648 .description = "Enable TIndex Exception-like Vector instructions",
1649 .dependencies = featureSet(&[_]Feature{}),
1650 };
15031651 result[@intFromEnum(Feature.the)] = .{
15041652 .llvm_name = "the",
15051653 .description = "Enable Armv8.9-A Translation Hardening Extension",
......@@ -1510,16 +1658,16 @@ pub const all_features = blk: {
15101658 .description = "Enable Armv8.4-A TLB Range and Maintenance instructions",
15111659 .dependencies = featureSet(&[_]Feature{}),
15121660 };
1661 result[@intFromEnum(Feature.tlbid)] = .{
1662 .llvm_name = "tlbid",
1663 .description = "Enable Armv9.7-A TLBI Domains extension",
1664 .dependencies = featureSet(&[_]Feature{}),
1665 };
15131666 result[@intFromEnum(Feature.tlbiw)] = .{
15141667 .llvm_name = "tlbiw",
15151668 .description = "Enable Armv9.5-A TLBI VMALL for Dirty State",
15161669 .dependencies = featureSet(&[_]Feature{}),
15171670 };
1518 result[@intFromEnum(Feature.tme)] = .{
1519 .llvm_name = "tme",
1520 .description = "Enable Transactional Memory Extension",
1521 .dependencies = featureSet(&[_]Feature{}),
1522 };
15231671 result[@intFromEnum(Feature.tpidr_el1)] = .{
15241672 .llvm_name = "tpidr-el1",
15251673 .description = "Permit use of TPIDR_EL1 for the TLS base",
......@@ -1575,6 +1723,11 @@ pub const all_features = blk: {
15751723 .description = "Use the reciprocal square root approximation",
15761724 .dependencies = featureSet(&[_]Feature{}),
15771725 };
1726 result[@intFromEnum(Feature.use_wzr_to_vec_move)] = .{
1727 .llvm_name = "use-wzr-to-vec-move",
1728 .description = "Move from WZR to insert 0 into vector registers",
1729 .dependencies = featureSet(&[_]Feature{}),
1730 };
15781731 result[@intFromEnum(Feature.v8_1a)] = .{
15791732 .llvm_name = "v8.1a",
15801733 .description = "Support ARM v8.1a architecture",
......@@ -1783,6 +1936,16 @@ pub const all_features = blk: {
17831936 .v9_5a,
17841937 }),
17851938 };
1939 result[@intFromEnum(Feature.v9_7a)] = .{
1940 .llvm_name = "v9.7a",
1941 .description = "Support ARM v9.7a architecture",
1942 .dependencies = featureSet(&[_]Feature{
1943 .f16f32dot,
1944 .fprcvt,
1945 .sve2p3,
1946 .v9_6a,
1947 }),
1948 };
17861949 result[@intFromEnum(Feature.v9a)] = .{
17871950 .llvm_name = "v9a",
17881951 .description = "Support ARM v9a architecture",
......@@ -1808,6 +1971,11 @@ pub const all_features = blk: {
18081971 .description = "Enable Armv8.7-A limited-TLB-maintenance instruction",
18091972 .dependencies = featureSet(&[_]Feature{}),
18101973 };
1974 result[@intFromEnum(Feature.zcm_fpr128)] = .{
1975 .llvm_name = "zcm-fpr128",
1976 .description = "Has zero-cycle register moves for FPR128 registers",
1977 .dependencies = featureSet(&[_]Feature{}),
1978 };
18111979 result[@intFromEnum(Feature.zcm_fpr32)] = .{
18121980 .llvm_name = "zcm-fpr32",
18131981 .description = "Has zero-cycle register moves for FPR32 registers",
......@@ -1828,21 +1996,24 @@ pub const all_features = blk: {
18281996 .description = "Has zero-cycle register moves for GPR64 registers",
18291997 .dependencies = featureSet(&[_]Feature{}),
18301998 };
1831 result[@intFromEnum(Feature.zcz)] = .{
1832 .llvm_name = "zcz",
1833 .description = "Has zero-cycle zeroing instructions",
1834 .dependencies = featureSet(&[_]Feature{
1835 .zcz_gp,
1836 }),
1837 };
18381999 result[@intFromEnum(Feature.zcz_fp_workaround)] = .{
18392000 .llvm_name = "zcz-fp-workaround",
18402001 .description = "The zero-cycle floating-point zeroing instruction has a bug",
18412002 .dependencies = featureSet(&[_]Feature{}),
18422003 };
1843 result[@intFromEnum(Feature.zcz_gp)] = .{
1844 .llvm_name = "zcz-gp",
1845 .description = "Has zero-cycle zeroing instructions for generic registers",
2004 result[@intFromEnum(Feature.zcz_fpr128)] = .{
2005 .llvm_name = "zcz-fpr128",
2006 .description = "Has zero-cycle zeroing instructions for FPR128 registers",
2007 .dependencies = featureSet(&[_]Feature{}),
2008 };
2009 result[@intFromEnum(Feature.zcz_gpr32)] = .{
2010 .llvm_name = "zcz-gpr32",
2011 .description = "Has zero-cycle zeroing instructions for GPR32 registers",
2012 .dependencies = featureSet(&[_]Feature{}),
2013 };
2014 result[@intFromEnum(Feature.zcz_gpr64)] = .{
2015 .llvm_name = "zcz-gpr64",
2016 .description = "Has zero-cycle zeroing instructions for GPR64 registers",
18462017 .dependencies = featureSet(&[_]Feature{}),
18472018 };
18482019 const ti = @typeInfo(Feature);
......@@ -1862,6 +2033,8 @@ pub const cpu = struct {
18622033 .aggressive_fma,
18632034 .arith_bcc_fusion,
18642035 .complxnum,
2036 .disable_unpredicated_ld_st_lower,
2037 .max_interleave_factor_4,
18652038 .perfmon,
18662039 .predictable_select_expensive,
18672040 .sha2,
......@@ -1886,6 +2059,7 @@ pub const cpu = struct {
18862059 .fuse_aes,
18872060 .fuse_literals,
18882061 .ldp_aligned_only,
2062 .max_interleave_factor_4,
18892063 .perfmon,
18902064 .rand,
18912065 .sha3,
......@@ -1911,6 +2085,7 @@ pub const cpu = struct {
19112085 .fuse_aes,
19122086 .fuse_literals,
19132087 .ldp_aligned_only,
2088 .max_interleave_factor_4,
19142089 .mte,
19152090 .perfmon,
19162091 .rand,
......@@ -1939,6 +2114,7 @@ pub const cpu = struct {
19392114 .fuse_aes,
19402115 .fuse_literals,
19412116 .ldp_aligned_only,
2117 .max_interleave_factor_4,
19422118 .mte,
19432119 .perfmon,
19442120 .predictable_select_expensive,
......@@ -1951,6 +2127,38 @@ pub const cpu = struct {
19512127 .v8_7a,
19522128 }),
19532129 };
2130 pub const ampere1c: CpuModel = .{
2131 .name = "ampere1c",
2132 .llvm_name = "ampere1c",
2133 .features = featureSet(&[_]Feature{
2134 .aggressive_fma,
2135 .alu_lsl_fast,
2136 .arith_bcc_fusion,
2137 .cmp_bcc_fusion,
2138 .cssc,
2139 .enable_select_opt,
2140 .faminmax,
2141 .fp16fml,
2142 .fp8fma,
2143 .fuse_address,
2144 .fuse_adrp_add,
2145 .fuse_aes,
2146 .fuse_literals,
2147 .lut,
2148 .max_interleave_factor_4,
2149 .mte,
2150 .perfmon,
2151 .predictable_select_expensive,
2152 .rand,
2153 .store_pair_suppress,
2154 .sve_aes,
2155 .sve_b16b16,
2156 .sve_sha3,
2157 .sve_sm4,
2158 .use_postra_scheduler,
2159 .v9_2a,
2160 }),
2161 };
19542162 pub const apple_a10: CpuModel = .{
19552163 .name = "apple_a10",
19562164 .llvm_name = "apple-a10",
......@@ -1964,6 +2172,7 @@ pub const cpu = struct {
19642172 .fuse_aes,
19652173 .fuse_crypto_eor,
19662174 .lor,
2175 .no_zcz_fpr64,
19672176 .pan,
19682177 .perfmon,
19692178 .rdm,
......@@ -1971,9 +2180,11 @@ pub const cpu = struct {
19712180 .store_pair_suppress,
19722181 .v8a,
19732182 .vh,
1974 .zcm_fpr64,
2183 .zcm_fpr128,
19752184 .zcm_gpr64,
1976 .zcz,
2185 .zcz_fpr128,
2186 .zcz_gpr32,
2187 .zcz_gpr64,
19772188 }),
19782189 };
19792190 pub const apple_a11: CpuModel = .{
......@@ -1988,13 +2199,16 @@ pub const cpu = struct {
19882199 .fullfp16,
19892200 .fuse_aes,
19902201 .fuse_crypto_eor,
2202 .no_zcz_fpr64,
19912203 .perfmon,
19922204 .sha2,
19932205 .store_pair_suppress,
19942206 .v8_2a,
1995 .zcm_fpr64,
2207 .zcm_fpr128,
19962208 .zcm_gpr64,
1997 .zcz,
2209 .zcz_fpr128,
2210 .zcz_gpr32,
2211 .zcz_gpr64,
19982212 }),
19992213 };
20002214 pub const apple_a12: CpuModel = .{
......@@ -2009,13 +2223,16 @@ pub const cpu = struct {
20092223 .fullfp16,
20102224 .fuse_aes,
20112225 .fuse_crypto_eor,
2226 .no_zcz_fpr64,
20122227 .perfmon,
20132228 .sha2,
20142229 .store_pair_suppress,
20152230 .v8_3a,
2016 .zcm_fpr64,
2231 .zcm_fpr128,
20172232 .zcm_gpr64,
2018 .zcz,
2233 .zcz_fpr128,
2234 .zcz_gpr32,
2235 .zcz_gpr64,
20192236 }),
20202237 };
20212238 pub const apple_a13: CpuModel = .{
......@@ -2030,13 +2247,16 @@ pub const cpu = struct {
20302247 .fp16fml,
20312248 .fuse_aes,
20322249 .fuse_crypto_eor,
2250 .no_zcz_fpr64,
20332251 .perfmon,
20342252 .sha3,
20352253 .store_pair_suppress,
20362254 .v8_4a,
2037 .zcm_fpr64,
2255 .zcm_fpr128,
20382256 .zcm_gpr64,
2039 .zcz,
2257 .zcz_fpr128,
2258 .zcz_gpr32,
2259 .zcz_gpr64,
20402260 }),
20412261 };
20422262 pub const apple_a14: CpuModel = .{
......@@ -2059,6 +2279,8 @@ pub const cpu = struct {
20592279 .fuse_crypto_eor,
20602280 .fuse_csel,
20612281 .fuse_literals,
2282 .max_interleave_factor_4,
2283 .no_zcz_fpr64,
20622284 .perfmon,
20632285 .predres,
20642286 .sb,
......@@ -2067,9 +2289,11 @@ pub const cpu = struct {
20672289 .ssbs,
20682290 .store_pair_suppress,
20692291 .v8_4a,
2070 .zcm_fpr64,
2292 .zcm_fpr128,
20712293 .zcm_gpr64,
2072 .zcz,
2294 .zcz_fpr128,
2295 .zcz_gpr32,
2296 .zcz_gpr64,
20732297 }),
20742298 };
20752299 pub const apple_a15: CpuModel = .{
......@@ -2090,13 +2314,17 @@ pub const cpu = struct {
20902314 .fuse_crypto_eor,
20912315 .fuse_csel,
20922316 .fuse_literals,
2317 .max_interleave_factor_4,
2318 .no_zcz_fpr64,
20932319 .perfmon,
20942320 .sha3,
20952321 .store_pair_suppress,
20962322 .v8_6a,
2097 .zcm_fpr64,
2323 .zcm_fpr128,
20982324 .zcm_gpr64,
2099 .zcz,
2325 .zcz_fpr128,
2326 .zcz_gpr32,
2327 .zcz_gpr64,
21002328 }),
21012329 };
21022330 pub const apple_a16: CpuModel = .{
......@@ -2118,13 +2346,17 @@ pub const cpu = struct {
21182346 .fuse_csel,
21192347 .fuse_literals,
21202348 .hcx,
2349 .max_interleave_factor_4,
2350 .no_zcz_fpr64,
21212351 .perfmon,
21222352 .sha3,
21232353 .store_pair_suppress,
21242354 .v8_6a,
2125 .zcm_fpr64,
2355 .zcm_fpr128,
21262356 .zcm_gpr64,
2127 .zcz,
2357 .zcz_fpr128,
2358 .zcz_gpr32,
2359 .zcz_gpr64,
21282360 }),
21292361 };
21302362 pub const apple_a17: CpuModel = .{
......@@ -2146,13 +2378,17 @@ pub const cpu = struct {
21462378 .fuse_csel,
21472379 .fuse_literals,
21482380 .hcx,
2381 .max_interleave_factor_4,
2382 .no_zcz_fpr64,
21492383 .perfmon,
21502384 .sha3,
21512385 .store_pair_suppress,
21522386 .v8_6a,
2153 .zcm_fpr64,
2387 .zcm_fpr128,
21542388 .zcm_gpr64,
2155 .zcz,
2389 .zcz_fpr128,
2390 .zcz_gpr32,
2391 .zcz_gpr64,
21562392 }),
21572393 };
21582394 pub const apple_a18: CpuModel = .{
......@@ -2173,15 +2409,58 @@ pub const cpu = struct {
21732409 .fuse_crypto_eor,
21742410 .fuse_csel,
21752411 .fuse_literals,
2412 .max_interleave_factor_4,
2413 .no_zcz_fpr64,
21762414 .perfmon,
21772415 .sha3,
21782416 .sme2,
21792417 .sme_f64f64,
21802418 .sme_i16i64,
21812419 .v8_7a,
2182 .zcm_fpr64,
2420 .zcm_fpr128,
21832421 .zcm_gpr64,
2184 .zcz,
2422 .zcz_fpr128,
2423 .zcz_gpr32,
2424 .zcz_gpr64,
2425 }),
2426 };
2427 pub const apple_a19: CpuModel = .{
2428 .name = "apple_a19",
2429 .llvm_name = "apple-a19",
2430 .features = featureSet(&[_]Feature{
2431 .aes,
2432 .alternate_sextload_cvt_f32_pattern,
2433 .arith_bcc_fusion,
2434 .arith_cbz_fusion,
2435 .cssc,
2436 .disable_latency_sched_heuristic,
2437 .fp16fml,
2438 .fpac,
2439 .fuse_address,
2440 .fuse_adrp_add,
2441 .fuse_aes,
2442 .fuse_arith_logic,
2443 .fuse_crypto_eor,
2444 .fuse_csel,
2445 .fuse_literals,
2446 .hbc,
2447 .max_interleave_factor_4,
2448 .mte,
2449 .no_zcz_fpr64,
2450 .perfmon,
2451 .sha3,
2452 .sme2p1,
2453 .sme_b16b16,
2454 .sme_f16f16,
2455 .sme_f64f64,
2456 .sme_i16i64,
2457 .specres2,
2458 .v8_7a,
2459 .zcm_fpr128,
2460 .zcm_gpr64,
2461 .zcz_fpr128,
2462 .zcz_gpr32,
2463 .zcz_gpr64,
21852464 }),
21862465 };
21872466 pub const apple_a7: CpuModel = .{
......@@ -2195,14 +2474,17 @@ pub const cpu = struct {
21952474 .disable_latency_sched_heuristic,
21962475 .fuse_aes,
21972476 .fuse_crypto_eor,
2477 .no_zcz_fpr64,
21982478 .perfmon,
21992479 .sha2,
22002480 .store_pair_suppress,
22012481 .v8a,
2202 .zcm_fpr64,
2482 .zcm_fpr128,
22032483 .zcm_gpr64,
2204 .zcz,
22052484 .zcz_fp_workaround,
2485 .zcz_fpr128,
2486 .zcz_gpr32,
2487 .zcz_gpr64,
22062488 }),
22072489 };
22082490 pub const apple_a8: CpuModel = .{
......@@ -2216,14 +2498,17 @@ pub const cpu = struct {
22162498 .disable_latency_sched_heuristic,
22172499 .fuse_aes,
22182500 .fuse_crypto_eor,
2501 .no_zcz_fpr64,
22192502 .perfmon,
22202503 .sha2,
22212504 .store_pair_suppress,
22222505 .v8a,
2223 .zcm_fpr64,
2506 .zcm_fpr128,
22242507 .zcm_gpr64,
2225 .zcz,
22262508 .zcz_fp_workaround,
2509 .zcz_fpr128,
2510 .zcz_gpr32,
2511 .zcz_gpr64,
22272512 }),
22282513 };
22292514 pub const apple_a9: CpuModel = .{
......@@ -2237,14 +2522,17 @@ pub const cpu = struct {
22372522 .disable_latency_sched_heuristic,
22382523 .fuse_aes,
22392524 .fuse_crypto_eor,
2525 .no_zcz_fpr64,
22402526 .perfmon,
22412527 .sha2,
22422528 .store_pair_suppress,
22432529 .v8a,
2244 .zcm_fpr64,
2530 .zcm_fpr128,
22452531 .zcm_gpr64,
2246 .zcz,
22472532 .zcz_fp_workaround,
2533 .zcz_fpr128,
2534 .zcz_gpr32,
2535 .zcz_gpr64,
22482536 }),
22492537 };
22502538 pub const apple_m1: CpuModel = .{
......@@ -2267,6 +2555,8 @@ pub const cpu = struct {
22672555 .fuse_crypto_eor,
22682556 .fuse_csel,
22692557 .fuse_literals,
2558 .max_interleave_factor_4,
2559 .no_zcz_fpr64,
22702560 .perfmon,
22712561 .predres,
22722562 .sb,
......@@ -2275,9 +2565,11 @@ pub const cpu = struct {
22752565 .ssbs,
22762566 .store_pair_suppress,
22772567 .v8_4a,
2278 .zcm_fpr64,
2568 .zcm_fpr128,
22792569 .zcm_gpr64,
2280 .zcz,
2570 .zcz_fpr128,
2571 .zcz_gpr32,
2572 .zcz_gpr64,
22812573 }),
22822574 };
22832575 pub const apple_m2: CpuModel = .{
......@@ -2298,13 +2590,17 @@ pub const cpu = struct {
22982590 .fuse_crypto_eor,
22992591 .fuse_csel,
23002592 .fuse_literals,
2593 .max_interleave_factor_4,
2594 .no_zcz_fpr64,
23012595 .perfmon,
23022596 .sha3,
23032597 .store_pair_suppress,
23042598 .v8_6a,
2305 .zcm_fpr64,
2599 .zcm_fpr128,
23062600 .zcm_gpr64,
2307 .zcz,
2601 .zcz_fpr128,
2602 .zcz_gpr32,
2603 .zcz_gpr64,
23082604 }),
23092605 };
23102606 pub const apple_m3: CpuModel = .{
......@@ -2326,13 +2622,17 @@ pub const cpu = struct {
23262622 .fuse_csel,
23272623 .fuse_literals,
23282624 .hcx,
2625 .max_interleave_factor_4,
2626 .no_zcz_fpr64,
23292627 .perfmon,
23302628 .sha3,
23312629 .store_pair_suppress,
23322630 .v8_6a,
2333 .zcm_fpr64,
2631 .zcm_fpr128,
23342632 .zcm_gpr64,
2335 .zcz,
2633 .zcz_fpr128,
2634 .zcz_gpr32,
2635 .zcz_gpr64,
23362636 }),
23372637 };
23382638 pub const apple_m4: CpuModel = .{
......@@ -2353,15 +2653,58 @@ pub const cpu = struct {
23532653 .fuse_crypto_eor,
23542654 .fuse_csel,
23552655 .fuse_literals,
2656 .max_interleave_factor_4,
2657 .no_zcz_fpr64,
23562658 .perfmon,
23572659 .sha3,
23582660 .sme2,
23592661 .sme_f64f64,
23602662 .sme_i16i64,
23612663 .v8_7a,
2362 .zcm_fpr64,
2664 .zcm_fpr128,
2665 .zcm_gpr64,
2666 .zcz_fpr128,
2667 .zcz_gpr32,
2668 .zcz_gpr64,
2669 }),
2670 };
2671 pub const apple_m5: CpuModel = .{
2672 .name = "apple_m5",
2673 .llvm_name = "apple-m5",
2674 .features = featureSet(&[_]Feature{
2675 .aes,
2676 .alternate_sextload_cvt_f32_pattern,
2677 .arith_bcc_fusion,
2678 .arith_cbz_fusion,
2679 .cssc,
2680 .disable_latency_sched_heuristic,
2681 .fp16fml,
2682 .fpac,
2683 .fuse_address,
2684 .fuse_adrp_add,
2685 .fuse_aes,
2686 .fuse_arith_logic,
2687 .fuse_crypto_eor,
2688 .fuse_csel,
2689 .fuse_literals,
2690 .hbc,
2691 .max_interleave_factor_4,
2692 .mte,
2693 .no_zcz_fpr64,
2694 .perfmon,
2695 .sha3,
2696 .sme2p1,
2697 .sme_b16b16,
2698 .sme_f16f16,
2699 .sme_f64f64,
2700 .sme_i16i64,
2701 .specres2,
2702 .v8_7a,
2703 .zcm_fpr128,
23632704 .zcm_gpr64,
2364 .zcz,
2705 .zcz_fpr128,
2706 .zcz_gpr32,
2707 .zcz_gpr64,
23652708 }),
23662709 };
23672710 pub const apple_s10: CpuModel = .{
......@@ -2383,13 +2726,17 @@ pub const cpu = struct {
23832726 .fuse_csel,
23842727 .fuse_literals,
23852728 .hcx,
2729 .max_interleave_factor_4,
2730 .no_zcz_fpr64,
23862731 .perfmon,
23872732 .sha3,
23882733 .store_pair_suppress,
23892734 .v8_6a,
2390 .zcm_fpr64,
2735 .zcm_fpr128,
23912736 .zcm_gpr64,
2392 .zcz,
2737 .zcz_fpr128,
2738 .zcz_gpr32,
2739 .zcz_gpr64,
23932740 }),
23942741 };
23952742 pub const apple_s4: CpuModel = .{
......@@ -2404,13 +2751,16 @@ pub const cpu = struct {
24042751 .fullfp16,
24052752 .fuse_aes,
24062753 .fuse_crypto_eor,
2754 .no_zcz_fpr64,
24072755 .perfmon,
24082756 .sha2,
24092757 .store_pair_suppress,
24102758 .v8_3a,
2411 .zcm_fpr64,
2759 .zcm_fpr128,
24122760 .zcm_gpr64,
2413 .zcz,
2761 .zcz_fpr128,
2762 .zcz_gpr32,
2763 .zcz_gpr64,
24142764 }),
24152765 };
24162766 pub const apple_s5: CpuModel = .{
......@@ -2425,13 +2775,16 @@ pub const cpu = struct {
24252775 .fullfp16,
24262776 .fuse_aes,
24272777 .fuse_crypto_eor,
2778 .no_zcz_fpr64,
24282779 .perfmon,
24292780 .sha2,
24302781 .store_pair_suppress,
24312782 .v8_3a,
2432 .zcm_fpr64,
2783 .zcm_fpr128,
24332784 .zcm_gpr64,
2434 .zcz,
2785 .zcz_fpr128,
2786 .zcz_gpr32,
2787 .zcz_gpr64,
24352788 }),
24362789 };
24372790 pub const apple_s6: CpuModel = .{
......@@ -2446,13 +2799,16 @@ pub const cpu = struct {
24462799 .fp16fml,
24472800 .fuse_aes,
24482801 .fuse_crypto_eor,
2802 .no_zcz_fpr64,
24492803 .perfmon,
24502804 .sha3,
24512805 .store_pair_suppress,
24522806 .v8_4a,
2453 .zcm_fpr64,
2807 .zcm_fpr128,
24542808 .zcm_gpr64,
2455 .zcz,
2809 .zcz_fpr128,
2810 .zcz_gpr32,
2811 .zcz_gpr64,
24562812 }),
24572813 };
24582814 pub const apple_s7: CpuModel = .{
......@@ -2467,13 +2823,16 @@ pub const cpu = struct {
24672823 .fp16fml,
24682824 .fuse_aes,
24692825 .fuse_crypto_eor,
2826 .no_zcz_fpr64,
24702827 .perfmon,
24712828 .sha3,
24722829 .store_pair_suppress,
24732830 .v8_4a,
2474 .zcm_fpr64,
2831 .zcm_fpr128,
24752832 .zcm_gpr64,
2476 .zcz,
2833 .zcz_fpr128,
2834 .zcz_gpr32,
2835 .zcz_gpr64,
24772836 }),
24782837 };
24792838 pub const apple_s8: CpuModel = .{
......@@ -2488,13 +2847,16 @@ pub const cpu = struct {
24882847 .fp16fml,
24892848 .fuse_aes,
24902849 .fuse_crypto_eor,
2850 .no_zcz_fpr64,
24912851 .perfmon,
24922852 .sha3,
24932853 .store_pair_suppress,
24942854 .v8_4a,
2495 .zcm_fpr64,
2855 .zcm_fpr128,
24962856 .zcm_gpr64,
2497 .zcz,
2857 .zcz_fpr128,
2858 .zcz_gpr32,
2859 .zcz_gpr64,
24982860 }),
24992861 };
25002862 pub const apple_s9: CpuModel = .{
......@@ -2516,13 +2878,126 @@ pub const cpu = struct {
25162878 .fuse_csel,
25172879 .fuse_literals,
25182880 .hcx,
2881 .max_interleave_factor_4,
2882 .no_zcz_fpr64,
25192883 .perfmon,
25202884 .sha3,
25212885 .store_pair_suppress,
25222886 .v8_6a,
2523 .zcm_fpr64,
2887 .zcm_fpr128,
25242888 .zcm_gpr64,
2525 .zcz,
2889 .zcz_fpr128,
2890 .zcz_gpr32,
2891 .zcz_gpr64,
2892 }),
2893 };
2894 pub const c1_nano: CpuModel = .{
2895 .name = "c1_nano",
2896 .llvm_name = "c1-nano",
2897 .features = featureSet(&[_]Feature{
2898 .chk,
2899 .clrbhb,
2900 .ete,
2901 .fp16fml,
2902 .fpac,
2903 .fuse_adrp_add,
2904 .fuse_aes,
2905 .mte,
2906 .perfmon,
2907 .rcpc3,
2908 .sme2,
2909 .specres2,
2910 .sve_bitperm,
2911 .use_fixed_over_scalable_if_equal_cost,
2912 .use_postra_scheduler,
2913 .use_wzr_to_vec_move,
2914 .v9_3a,
2915 }),
2916 };
2917 pub const c1_premium: CpuModel = .{
2918 .name = "c1_premium",
2919 .llvm_name = "c1-premium",
2920 .features = featureSet(&[_]Feature{
2921 .alu_lsl_fast,
2922 .avoid_ldapur,
2923 .chk,
2924 .clrbhb,
2925 .enable_select_opt,
2926 .ete,
2927 .fp16fml,
2928 .fpac,
2929 .fuse_adrp_add,
2930 .fuse_aes,
2931 .fuse_csel,
2932 .fuse_cset,
2933 .mte,
2934 .perfmon,
2935 .predictable_select_expensive,
2936 .rcpc3,
2937 .sme2,
2938 .spe,
2939 .specres2,
2940 .sve_bitperm,
2941 .use_fixed_over_scalable_if_equal_cost,
2942 .use_postra_scheduler,
2943 .v9_3a,
2944 }),
2945 };
2946 pub const c1_pro: CpuModel = .{
2947 .name = "c1_pro",
2948 .llvm_name = "c1-pro",
2949 .features = featureSet(&[_]Feature{
2950 .alu_lsl_fast,
2951 .chk,
2952 .clrbhb,
2953 .cmp_bcc_fusion,
2954 .enable_select_opt,
2955 .ete,
2956 .fp16fml,
2957 .fpac,
2958 .fuse_adrp_add,
2959 .fuse_aes,
2960 .fuse_csel,
2961 .fuse_cset,
2962 .mte,
2963 .perfmon,
2964 .predictable_select_expensive,
2965 .rcpc3,
2966 .sme2,
2967 .spe,
2968 .specres2,
2969 .sve_bitperm,
2970 .use_postra_scheduler,
2971 .v9_3a,
2972 }),
2973 };
2974 pub const c1_ultra: CpuModel = .{
2975 .name = "c1_ultra",
2976 .llvm_name = "c1-ultra",
2977 .features = featureSet(&[_]Feature{
2978 .alu_lsl_fast,
2979 .avoid_ldapur,
2980 .chk,
2981 .clrbhb,
2982 .enable_select_opt,
2983 .ete,
2984 .fp16fml,
2985 .fpac,
2986 .fuse_adrp_add,
2987 .fuse_aes,
2988 .fuse_csel,
2989 .fuse_cset,
2990 .mte,
2991 .perfmon,
2992 .predictable_select_expensive,
2993 .rcpc3,
2994 .sme2,
2995 .spe,
2996 .specres2,
2997 .sve_bitperm,
2998 .use_fixed_over_scalable_if_equal_cost,
2999 .use_postra_scheduler,
3000 .v9_3a,
25263001 }),
25273002 };
25283003 pub const carmel: CpuModel = .{
......@@ -2541,12 +3016,15 @@ pub const cpu = struct {
25413016 .features = featureSet(&[_]Feature{
25423017 .alu_lsl_fast,
25433018 .bf16,
3019 .disable_maximize_scalable_bandwidth,
25443020 .enable_select_opt,
25453021 .ete,
25463022 .fp16fml,
25473023 .fpac,
25483024 .fuse_adrp_add,
25493025 .fuse_aes,
3026 .fuse_csel,
3027 .fuse_cset,
25503028 .i8mm,
25513029 .mte,
25523030 .perfmon,
......@@ -2607,6 +3085,7 @@ pub const cpu = struct {
26073085 .sve_bitperm,
26083086 .use_fixed_over_scalable_if_equal_cost,
26093087 .use_postra_scheduler,
3088 .use_wzr_to_vec_move,
26103089 .v9a,
26113090 }),
26123091 };
......@@ -2624,6 +3103,7 @@ pub const cpu = struct {
26243103 .sve_bitperm,
26253104 .use_fixed_over_scalable_if_equal_cost,
26263105 .use_postra_scheduler,
3106 .use_wzr_to_vec_move,
26273107 .v9_2a,
26283108 }),
26293109 };
......@@ -2640,6 +3120,7 @@ pub const cpu = struct {
26403120 .perfmon,
26413121 .sve_bitperm,
26423122 .use_postra_scheduler,
3123 .use_wzr_to_vec_move,
26433124 .v9_2a,
26443125 }),
26453126 };
......@@ -2655,6 +3136,7 @@ pub const cpu = struct {
26553136 .perfmon,
26563137 .sha2,
26573138 .use_postra_scheduler,
3139 .use_wzr_to_vec_move,
26583140 .v8a,
26593141 }),
26603142 };
......@@ -2672,6 +3154,7 @@ pub const cpu = struct {
26723154 .rcpc,
26733155 .sha2,
26743156 .use_postra_scheduler,
3157 .use_wzr_to_vec_move,
26753158 .v8_2a,
26763159 }),
26773160 };
......@@ -2687,6 +3170,7 @@ pub const cpu = struct {
26873170 .fuse_adrp_add,
26883171 .fuse_aes,
26893172 .fuse_literals,
3173 .max_interleave_factor_4,
26903174 .perfmon,
26913175 .predictable_select_expensive,
26923176 .sha2,
......@@ -2747,6 +3231,8 @@ pub const cpu = struct {
27473231 .fpac,
27483232 .fuse_adrp_add,
27493233 .fuse_aes,
3234 .fuse_csel,
3235 .fuse_cset,
27503236 .i8mm,
27513237 .mte,
27523238 .perfmon,
......@@ -2769,6 +3255,8 @@ pub const cpu = struct {
27693255 .fpac,
27703256 .fuse_adrp_add,
27713257 .fuse_aes,
3258 .fuse_csel,
3259 .fuse_cset,
27723260 .i8mm,
27733261 .mte,
27743262 .perfmon,
......@@ -2808,6 +3296,8 @@ pub const cpu = struct {
28083296 .fpac,
28093297 .fuse_adrp_add,
28103298 .fuse_aes,
3299 .fuse_csel,
3300 .fuse_cset,
28113301 .mte,
28123302 .perfmon,
28133303 .predictable_select_expensive,
......@@ -2829,6 +3319,8 @@ pub const cpu = struct {
28293319 .fpac,
28303320 .fuse_adrp_add,
28313321 .fuse_aes,
3322 .fuse_csel,
3323 .fuse_cset,
28323324 .mte,
28333325 .perfmon,
28343326 .predictable_select_expensive,
......@@ -2850,6 +3342,8 @@ pub const cpu = struct {
28503342 .fpac,
28513343 .fuse_adrp_add,
28523344 .fuse_aes,
3345 .fuse_csel,
3346 .fuse_cset,
28533347 .mte,
28543348 .perfmon,
28553349 .predictable_select_expensive,
......@@ -2967,6 +3461,8 @@ pub const cpu = struct {
29673461 .fullfp16,
29683462 .fuse_adrp_add,
29693463 .fuse_aes,
3464 .fuse_csel,
3465 .fuse_cset,
29703466 .perfmon,
29713467 .predictable_select_expensive,
29723468 .rcpc,
......@@ -2990,6 +3486,8 @@ pub const cpu = struct {
29903486 .fullfp16,
29913487 .fuse_adrp_add,
29923488 .fuse_aes,
3489 .fuse_csel,
3490 .fuse_cset,
29933491 .perfmon,
29943492 .predictable_select_expensive,
29953493 .rcpc,
......@@ -3014,6 +3512,8 @@ pub const cpu = struct {
30143512 .fullfp16,
30153513 .fuse_adrp_add,
30163514 .fuse_aes,
3515 .fuse_csel,
3516 .fuse_cset,
30173517 .pauth,
30183518 .perfmon,
30193519 .predictable_select_expensive,
......@@ -3157,6 +3657,8 @@ pub const cpu = struct {
31573657 .fpac,
31583658 .fuse_adrp_add,
31593659 .fuse_aes,
3660 .fuse_csel,
3661 .fuse_cset,
31603662 .mte,
31613663 .perfmon,
31623664 .predictable_select_expensive,
......@@ -3179,6 +3681,8 @@ pub const cpu = struct {
31793681 .fpac,
31803682 .fuse_adrp_add,
31813683 .fuse_aes,
3684 .fuse_csel,
3685 .fuse_cset,
31823686 .mte,
31833687 .perfmon,
31843688 .predictable_select_expensive,
......@@ -3200,14 +3704,17 @@ pub const cpu = struct {
32003704 .disable_latency_sched_heuristic,
32013705 .fuse_aes,
32023706 .fuse_crypto_eor,
3707 .no_zcz_fpr64,
32033708 .perfmon,
32043709 .sha2,
32053710 .store_pair_suppress,
32063711 .v8a,
3207 .zcm_fpr64,
3712 .zcm_fpr128,
32083713 .zcm_gpr64,
3209 .zcz,
32103714 .zcz_fp_workaround,
3715 .zcz_fpr128,
3716 .zcz_gpr32,
3717 .zcz_gpr64,
32113718 }),
32123719 };
32133720 pub const emag: CpuModel = .{
......@@ -3267,6 +3774,7 @@ pub const cpu = struct {
32673774 .fuse_aes,
32683775 .fuse_csel,
32693776 .fuse_literals,
3777 .max_interleave_factor_4,
32703778 .perfmon,
32713779 .predictable_select_expensive,
32723780 .sha2,
......@@ -3293,12 +3801,14 @@ pub const cpu = struct {
32933801 .fuse_arith_logic,
32943802 .fuse_csel,
32953803 .fuse_literals,
3804 .max_interleave_factor_4,
32963805 .perfmon,
32973806 .sha2,
32983807 .store_pair_suppress,
32993808 .use_postra_scheduler,
33003809 .v8_2a,
3301 .zcz,
3810 .zcz_gpr32,
3811 .zcz_gpr64,
33023812 }),
33033813 };
33043814 pub const exynos_m5: CpuModel = .{
......@@ -3319,12 +3829,14 @@ pub const cpu = struct {
33193829 .fuse_arith_logic,
33203830 .fuse_csel,
33213831 .fuse_literals,
3832 .max_interleave_factor_4,
33223833 .perfmon,
33233834 .sha2,
33243835 .store_pair_suppress,
33253836 .use_postra_scheduler,
33263837 .v8_2a,
3327 .zcz,
3838 .zcz_gpr32,
3839 .zcz_gpr64,
33283840 }),
33293841 };
33303842 pub const falkor: CpuModel = .{
......@@ -3334,6 +3846,7 @@ pub const cpu = struct {
33343846 .aes,
33353847 .alu_lsl_fast,
33363848 .crc,
3849 .max_interleave_factor_4,
33373850 .perfmon,
33383851 .predictable_select_expensive,
33393852 .rdm,
......@@ -3342,7 +3855,8 @@ pub const cpu = struct {
33423855 .store_pair_suppress,
33433856 .use_postra_scheduler,
33443857 .v8a,
3345 .zcz,
3858 .zcz_gpr32,
3859 .zcz_gpr64,
33463860 }),
33473861 };
33483862 pub const fujitsu_monaka: CpuModel = .{
......@@ -3382,6 +3896,8 @@ pub const cpu = struct {
33823896 .fpac,
33833897 .fuse_adrp_add,
33843898 .fuse_aes,
3899 .fuse_csel,
3900 .fuse_cset,
33853901 .mte,
33863902 .perfmon,
33873903 .predictable_select_expensive,
......@@ -3422,11 +3938,13 @@ pub const cpu = struct {
34223938 .fpac,
34233939 .fuse_adrp_add,
34243940 .fuse_aes,
3941 .fuse_csel,
3942 .fuse_cset,
34253943 .i8mm,
3944 .max_interleave_factor_4,
34263945 .mte,
34273946 .perfmon,
34283947 .predictable_select_expensive,
3429 .rand,
34303948 .spe,
34313949 .sve_aes,
34323950 .sve_bitperm,
......@@ -3444,13 +3962,15 @@ pub const cpu = struct {
34443962 .aes,
34453963 .alu_lsl_fast,
34463964 .crc,
3965 .max_interleave_factor_4,
34473966 .perfmon,
34483967 .predictable_select_expensive,
34493968 .sha2,
34503969 .store_pair_suppress,
34513970 .use_postra_scheduler,
34523971 .v8a,
3453 .zcz,
3972 .zcz_gpr32,
3973 .zcz_gpr64,
34543974 }),
34553975 };
34563976 pub const neoverse_512tvb: CpuModel = .{
......@@ -3467,6 +3987,7 @@ pub const cpu = struct {
34673987 .fuse_adrp_add,
34683988 .fuse_aes,
34693989 .i8mm,
3990 .max_interleave_factor_4,
34703991 .perfmon,
34713992 .predictable_select_expensive,
34723993 .rand,
......@@ -3524,12 +4045,15 @@ pub const cpu = struct {
35244045 .features = featureSet(&[_]Feature{
35254046 .alu_lsl_fast,
35264047 .bf16,
4048 .disable_maximize_scalable_bandwidth,
35274049 .enable_select_opt,
35284050 .ete,
35294051 .fp16fml,
35304052 .fpac,
35314053 .fuse_adrp_add,
35324054 .fuse_aes,
4055 .fuse_csel,
4056 .fuse_cset,
35334057 .i8mm,
35344058 .mte,
35354059 .perfmon,
......@@ -3550,6 +4074,8 @@ pub const cpu = struct {
35504074 .fpac,
35514075 .fuse_adrp_add,
35524076 .fuse_aes,
4077 .fuse_csel,
4078 .fuse_cset,
35534079 .mte,
35544080 .perfmon,
35554081 .predictable_select_expensive,
......@@ -3569,10 +4095,13 @@ pub const cpu = struct {
35694095 .alu_lsl_fast,
35704096 .bf16,
35714097 .ccdp,
4098 .disable_maximize_scalable_bandwidth,
35724099 .enable_select_opt,
35734100 .fp16fml,
35744101 .fuse_adrp_add,
35754102 .fuse_aes,
4103 .fuse_csel,
4104 .fuse_cset,
35764105 .i8mm,
35774106 .no_sve_fp_ld1r,
35784107 .perfmon,
......@@ -3602,7 +4131,10 @@ pub const cpu = struct {
36024131 .fpac,
36034132 .fuse_adrp_add,
36044133 .fuse_aes,
4134 .fuse_csel,
4135 .fuse_cset,
36054136 .i8mm,
4137 .max_interleave_factor_4,
36064138 .mte,
36074139 .perfmon,
36084140 .predictable_select_expensive,
......@@ -3627,7 +4159,10 @@ pub const cpu = struct {
36274159 .fpac,
36284160 .fuse_adrp_add,
36294161 .fuse_aes,
4162 .fuse_csel,
4163 .fuse_cset,
36304164 .ls64,
4165 .max_interleave_factor_4,
36314166 .mte,
36324167 .perfmon,
36334168 .predictable_select_expensive,
......@@ -3651,7 +4186,10 @@ pub const cpu = struct {
36514186 .fpac,
36524187 .fuse_adrp_add,
36534188 .fuse_aes,
4189 .fuse_csel,
4190 .fuse_cset,
36544191 .ls64,
4192 .max_interleave_factor_4,
36554193 .mte,
36564194 .perfmon,
36574195 .predictable_select_expensive,
......@@ -3700,6 +4238,7 @@ pub const cpu = struct {
37004238 .fuse_adrp_add,
37014239 .fuse_aes,
37024240 .fuse_crypto_eor,
4241 .max_interleave_factor_4,
37034242 .perfmon,
37044243 .rand,
37054244 .sha3,
......@@ -3715,6 +4254,7 @@ pub const cpu = struct {
37154254 .features = featureSet(&[_]Feature{
37164255 .aes,
37174256 .alu_lsl_fast,
4257 .max_interleave_factor_4,
37184258 .perfmon,
37194259 .predictable_select_expensive,
37204260 .sha2,
......@@ -3722,7 +4262,8 @@ pub const cpu = struct {
37224262 .store_pair_suppress,
37234263 .use_postra_scheduler,
37244264 .v8_4a,
3725 .zcz,
4265 .zcz_gpr32,
4266 .zcz_gpr64,
37264267 }),
37274268 };
37284269 pub const thunderx: CpuModel = .{
......@@ -3746,6 +4287,7 @@ pub const cpu = struct {
37464287 .aes,
37474288 .aggressive_fma,
37484289 .arith_bcc_fusion,
4290 .max_interleave_factor_4,
37494291 .predictable_select_expensive,
37504292 .sha2,
37514293 .store_pair_suppress,
......@@ -3761,6 +4303,7 @@ pub const cpu = struct {
37614303 .aggressive_fma,
37624304 .arith_bcc_fusion,
37634305 .balance_fp_ops,
4306 .max_interleave_factor_4,
37644307 .perfmon,
37654308 .predictable_select_expensive,
37664309 .sha2,
lib/std/Target/amdgcn.zig+421-21
......@@ -5,12 +5,17 @@ const CpuFeature = std.Target.Cpu.Feature;
55const CpuModel = std.Target.Cpu.Model;
66
77pub const Feature = enum {
8 @"1024_addressable_vgprs",
89 @"16_bit_insts",
10 @"45_bit_num_records_buffer_resource",
911 @"64_bit_literals",
1012 a16,
13 add_min_max_insts,
1114 add_no_carry_insts,
15 add_sub_u64_insts,
1216 addressablelocalmemorysize163840,
1317 addressablelocalmemorysize32768,
18 addressablelocalmemorysize327680,
1419 addressablelocalmemorysize65536,
1520 agent_scope_fine_grained_remote_memory_atomics,
1621 allocate1_5xvgprs,
......@@ -18,6 +23,7 @@ pub const Feature = enum {
1823 architected_flat_scratch,
1924 architected_sgprs,
2025 ashr_pk_insts,
26 assembler_permissive_wavesize,
2127 atomic_buffer_global_pk_add_f16_insts,
2228 atomic_buffer_global_pk_add_f16_no_rtn_insts,
2329 atomic_buffer_pk_add_bf16_inst,
......@@ -34,15 +40,22 @@ pub const Feature = enum {
3440 auto_waitcnt_before_barrier,
3541 back_off_barrier,
3642 bf16_cvt_insts,
43 bf16_pk_insts,
3744 bf16_trans_insts,
3845 bf8_cvt_scale_insts,
3946 bitop3_insts,
4047 block_vgpr_csr,
4148 bvh_dual_bvh_8_insts,
4249 ci_insts,
50 clusters,
51 cube_insts,
4352 cumode,
4453 cvt_fp8_vop1_bug,
54 cvt_norm_insts,
4555 cvt_pk_f16_f32_inst,
56 cvt_pknorm_vop2_insts,
57 cvt_pknorm_vop3_insts,
58 d16_write_vgpr32,
4659 default_component_broadcast,
4760 default_component_zero,
4861 dl_insts,
......@@ -65,8 +78,7 @@ pub const Feature = enum {
6578 dpp_src1_sgpr,
6679 ds128,
6780 ds_src2_insts,
68 dynamic_vgpr,
69 dynamic_vgpr_block_size_32,
81 emulated_system_scope_atomics,
7082 extended_image_insts,
7183 f16bf16_to_fp6bf6_cvt_scale_insts,
7284 f32_to_f16bf16_cvt_sr_insts,
......@@ -77,10 +89,12 @@ pub const Feature = enum {
7789 flat_buffer_global_fadd_f64_inst,
7890 flat_for_global,
7991 flat_global_insts,
92 flat_gvs_mode,
8093 flat_inst_offsets,
8194 flat_scratch,
8295 flat_scratch_insts,
8396 flat_segment_offset_bug,
97 fma_mix_bf16_insts,
8498 fma_mix_insts,
8599 fmacf64_inst,
86100 fmaf,
......@@ -113,6 +127,7 @@ pub const Feature = enum {
113127 gfx940_insts,
114128 gfx950_insts,
115129 gfx9_insts,
130 globally_addressable_scratch,
116131 gws,
117132 half_rate_64_ops,
118133 ieee_minimum_maximum_insts,
......@@ -128,20 +143,24 @@ pub const Feature = enum {
128143 lds_misaligned_bug,
129144 ldsbankcount16,
130145 ldsbankcount32,
146 lerp_inst,
131147 load_store_opt,
132148 lshl_add_u64_inst,
133149 mad_intra_fwd_bug,
134150 mad_mac_f32_insts,
135151 mad_mix_insts,
152 mad_u32_inst,
136153 mai_insts,
137154 max_hard_clause_length_32,
138155 max_hard_clause_length_63,
139156 max_private_element_size_16,
140157 max_private_element_size_4,
141158 max_private_element_size_8,
159 mcast_load_insts,
142160 memory_atomic_fadd_f32_denormal_support,
143161 mfma_inline_literal_bug,
144162 mimg_r128,
163 min3_max3_pkf16,
145164 minimum3_maximum3_f16,
146165 minimum3_maximum3_f32,
147166 minimum3_maximum3_pkf16,
......@@ -160,6 +179,7 @@ pub const Feature = enum {
160179 partial_nsa_encoding,
161180 permlane16_swap,
162181 permlane32_swap,
182 pk_add_min_max_insts,
163183 pk_fmac_f16_inst,
164184 point_sample_accel,
165185 precise_memory,
......@@ -168,6 +188,7 @@ pub const Feature = enum {
168188 promote_alloca,
169189 prt_strict_null,
170190 pseudo_scalar_trans,
191 qsad_insts,
171192 r128_a16,
172193 real_true16,
173194 relaxed_buffer_oob_mode,
......@@ -176,6 +197,9 @@ pub const Feature = enum {
176197 restricted_soffset,
177198 s_memrealtime,
178199 s_memtime_inst,
200 s_wakeup_barrier_inst,
201 sad_insts,
202 safe_cu_prefetch,
179203 safe_smem_prefetch,
180204 salu_float,
181205 scalar_atomics,
......@@ -190,6 +214,7 @@ pub const Feature = enum {
190214 sdwa_sdst,
191215 sea_islands,
192216 setprio_inc_wg_inst,
217 setreg_vgpr_msb_fixup,
193218 sgpr_init_bug,
194219 shader_cycles_hi_lo_registers,
195220 shader_cycles_register,
......@@ -198,6 +223,8 @@ pub const Feature = enum {
198223 southern_islands,
199224 sramecc,
200225 sramecc_support,
226 tanh_insts,
227 tensor_cvt_lut_insts,
201228 tgsplit,
202229 transpose_load_f4f6_insts,
203230 trap_handler,
......@@ -213,7 +240,9 @@ pub const Feature = enum {
213240 valu_trans_use_hazard,
214241 vcmpx_exec_war_hazard,
215242 vcmpx_permlane_hazard,
243 vgpr_align2,
216244 vgpr_index_mode,
245 vmem_pref_insts,
217246 vmem_to_lds_load_insts,
218247 vmem_to_scalar_write_hazard,
219248 vmem_write_vgpr_in_order,
......@@ -223,6 +252,7 @@ pub const Feature = enum {
223252 vopd,
224253 vscnt,
225254 wait_xcnt,
255 waits_before_system_scope_stores,
226256 wavefrontsize16,
227257 wavefrontsize32,
228258 wavefrontsize64,
......@@ -241,11 +271,21 @@ pub const all_features = blk: {
241271 const len = @typeInfo(Feature).@"enum".fields.len;
242272 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
243273 var result: [len]CpuFeature = undefined;
274 result[@intFromEnum(Feature.@"1024_addressable_vgprs")] = .{
275 .llvm_name = "1024-addressable-vgprs",
276 .description = "Has 1024 addressable VGPRs",
277 .dependencies = featureSet(&[_]Feature{}),
278 };
244279 result[@intFromEnum(Feature.@"16_bit_insts")] = .{
245280 .llvm_name = "16-bit-insts",
246281 .description = "Has i16/f16 instructions",
247282 .dependencies = featureSet(&[_]Feature{}),
248283 };
284 result[@intFromEnum(Feature.@"45_bit_num_records_buffer_resource")] = .{
285 .llvm_name = "45-bit-num-records-buffer-resource",
286 .description = "The buffer resource (V#) supports 45-bit num_records",
287 .dependencies = featureSet(&[_]Feature{}),
288 };
249289 result[@intFromEnum(Feature.@"64_bit_literals")] = .{
250290 .llvm_name = "64-bit-literals",
251291 .description = "Can use 64-bit literals with single DWORD instructions",
......@@ -256,11 +296,21 @@ pub const all_features = blk: {
256296 .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
257297 .dependencies = featureSet(&[_]Feature{}),
258298 };
299 result[@intFromEnum(Feature.add_min_max_insts)] = .{
300 .llvm_name = "add-min-max-insts",
301 .description = "Has v_add_{min|max}_{i|u}32 instructions",
302 .dependencies = featureSet(&[_]Feature{}),
303 };
259304 result[@intFromEnum(Feature.add_no_carry_insts)] = .{
260305 .llvm_name = "add-no-carry-insts",
261306 .description = "Have VALU add/sub instructions without carry out",
262307 .dependencies = featureSet(&[_]Feature{}),
263308 };
309 result[@intFromEnum(Feature.add_sub_u64_insts)] = .{
310 .llvm_name = "add-sub-u64-insts",
311 .description = "Has v_add_u64 and v_sub_u64 instructions",
312 .dependencies = featureSet(&[_]Feature{}),
313 };
264314 result[@intFromEnum(Feature.addressablelocalmemorysize163840)] = .{
265315 .llvm_name = "addressablelocalmemorysize163840",
266316 .description = "The size of local memory in bytes",
......@@ -271,6 +321,11 @@ pub const all_features = blk: {
271321 .description = "The size of local memory in bytes",
272322 .dependencies = featureSet(&[_]Feature{}),
273323 };
324 result[@intFromEnum(Feature.addressablelocalmemorysize327680)] = .{
325 .llvm_name = "addressablelocalmemorysize327680",
326 .description = "The size of local memory in bytes",
327 .dependencies = featureSet(&[_]Feature{}),
328 };
274329 result[@intFromEnum(Feature.addressablelocalmemorysize65536)] = .{
275330 .llvm_name = "addressablelocalmemorysize65536",
276331 .description = "The size of local memory in bytes",
......@@ -306,6 +361,11 @@ pub const all_features = blk: {
306361 .description = "Has Arithmetic Shift Pack instructions",
307362 .dependencies = featureSet(&[_]Feature{}),
308363 };
364 result[@intFromEnum(Feature.assembler_permissive_wavesize)] = .{
365 .llvm_name = "assembler-permissive-wavesize",
366 .description = "allow parsing wave32 and wave64 variants of instructions",
367 .dependencies = featureSet(&[_]Feature{}),
368 };
309369 result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{
310370 .llvm_name = "atomic-buffer-global-pk-add-f16-insts",
311371 .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value",
......@@ -357,12 +417,16 @@ pub const all_features = blk: {
357417 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f32)] = .{
358418 .llvm_name = "atomic-fmin-fmax-flat-f32",
359419 .description = "Has flat memory instructions for atomicrmw fmin/fmax for float",
360 .dependencies = featureSet(&[_]Feature{}),
420 .dependencies = featureSet(&[_]Feature{
421 .flat_address_space,
422 }),
361423 };
362424 result[@intFromEnum(Feature.atomic_fmin_fmax_flat_f64)] = .{
363425 .llvm_name = "atomic-fmin-fmax-flat-f64",
364426 .description = "Has flat memory instructions for atomicrmw fmin/fmax for double",
365 .dependencies = featureSet(&[_]Feature{}),
427 .dependencies = featureSet(&[_]Feature{
428 .flat_address_space,
429 }),
366430 };
367431 result[@intFromEnum(Feature.atomic_fmin_fmax_global_f32)] = .{
368432 .llvm_name = "atomic-fmin-fmax-global-f32",
......@@ -396,6 +460,11 @@ pub const all_features = blk: {
396460 .description = "Has bf16 conversion instructions",
397461 .dependencies = featureSet(&[_]Feature{}),
398462 };
463 result[@intFromEnum(Feature.bf16_pk_insts)] = .{
464 .llvm_name = "bf16-pk-insts",
465 .description = "Has bf16 packed instructions (fma, add, mul, max, min)",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
399468 result[@intFromEnum(Feature.bf16_trans_insts)] = .{
400469 .llvm_name = "bf16-trans-insts",
401470 .description = "Has bf16 transcendental instructions",
......@@ -426,6 +495,16 @@ pub const all_features = blk: {
426495 .description = "Additional instructions for CI+",
427496 .dependencies = featureSet(&[_]Feature{}),
428497 };
498 result[@intFromEnum(Feature.clusters)] = .{
499 .llvm_name = "clusters",
500 .description = "Has clusters of workgroups support",
501 .dependencies = featureSet(&[_]Feature{}),
502 };
503 result[@intFromEnum(Feature.cube_insts)] = .{
504 .llvm_name = "cube-insts",
505 .description = "Has v_cube* instructions",
506 .dependencies = featureSet(&[_]Feature{}),
507 };
429508 result[@intFromEnum(Feature.cumode)] = .{
430509 .llvm_name = "cumode",
431510 .description = "Enable CU wavefront execution mode",
......@@ -438,11 +517,31 @@ pub const all_features = blk: {
438517 .fp8_conversion_insts,
439518 }),
440519 };
520 result[@intFromEnum(Feature.cvt_norm_insts)] = .{
521 .llvm_name = "cvt-norm-insts",
522 .description = "Has v_cvt_norm* instructions",
523 .dependencies = featureSet(&[_]Feature{}),
524 };
441525 result[@intFromEnum(Feature.cvt_pk_f16_f32_inst)] = .{
442526 .llvm_name = "cvt-pk-f16-f32-inst",
443527 .description = "Has cvt_pk_f16_f32 instruction",
444528 .dependencies = featureSet(&[_]Feature{}),
445529 };
530 result[@intFromEnum(Feature.cvt_pknorm_vop2_insts)] = .{
531 .llvm_name = "cvt-pknorm-vop2-insts",
532 .description = "Has v_cvt_pk_norm_*f32 instructions/Has v_cvt_pk_norm_*_f16 instructions",
533 .dependencies = featureSet(&[_]Feature{}),
534 };
535 result[@intFromEnum(Feature.cvt_pknorm_vop3_insts)] = .{
536 .llvm_name = "cvt-pknorm-vop3-insts",
537 .description = "Has v_cvt_pk_norm_*f32 instructions/Has v_cvt_pk_norm_*_f16 instructions",
538 .dependencies = featureSet(&[_]Feature{}),
539 };
540 result[@intFromEnum(Feature.d16_write_vgpr32)] = .{
541 .llvm_name = "d16-write-vgpr32",
542 .description = "D16 instructions potentially have 32-bit data dependencies",
543 .dependencies = featureSet(&[_]Feature{}),
544 };
446545 result[@intFromEnum(Feature.default_component_broadcast)] = .{
447546 .llvm_name = "default-component-broadcast",
448547 .description = "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)",
......@@ -553,14 +652,9 @@ pub const all_features = blk: {
553652 .description = "Has ds_*_src2 instructions",
554653 .dependencies = featureSet(&[_]Feature{}),
555654 };
556 result[@intFromEnum(Feature.dynamic_vgpr)] = .{
557 .llvm_name = "dynamic-vgpr",
558 .description = "Enable dynamic VGPR mode",
559 .dependencies = featureSet(&[_]Feature{}),
560 };
561 result[@intFromEnum(Feature.dynamic_vgpr_block_size_32)] = .{
562 .llvm_name = "dynamic-vgpr-block-size-32",
563 .description = "Use a block size of 32 for dynamic VGPR allocation (default is 16)",
655 result[@intFromEnum(Feature.emulated_system_scope_atomics)] = .{
656 .llvm_name = "emulated-system-scope-atomics",
657 .description = "System scope atomics unsupported by the PCI-e are emulated in HW via CAS loop and functional.",
564658 .dependencies = featureSet(&[_]Feature{}),
565659 };
566660 result[@intFromEnum(Feature.extended_image_insts)] = .{
......@@ -596,7 +690,9 @@ pub const all_features = blk: {
596690 result[@intFromEnum(Feature.flat_atomic_fadd_f32_inst)] = .{
597691 .llvm_name = "flat-atomic-fadd-f32-inst",
598692 .description = "Has flat_atomic_add_f32 instruction",
599 .dependencies = featureSet(&[_]Feature{}),
693 .dependencies = featureSet(&[_]Feature{
694 .flat_address_space,
695 }),
600696 };
601697 result[@intFromEnum(Feature.flat_buffer_global_fadd_f64_inst)] = .{
602698 .llvm_name = "flat-buffer-global-fadd-f64-inst",
......@@ -611,7 +707,16 @@ pub const all_features = blk: {
611707 result[@intFromEnum(Feature.flat_global_insts)] = .{
612708 .llvm_name = "flat-global-insts",
613709 .description = "Have global_* flat memory instructions",
614 .dependencies = featureSet(&[_]Feature{}),
710 .dependencies = featureSet(&[_]Feature{
711 .flat_address_space,
712 }),
713 };
714 result[@intFromEnum(Feature.flat_gvs_mode)] = .{
715 .llvm_name = "flat-gvs-mode",
716 .description = "Have GVS addressing mode with flat_* instructions",
717 .dependencies = featureSet(&[_]Feature{
718 .flat_address_space,
719 }),
615720 };
616721 result[@intFromEnum(Feature.flat_inst_offsets)] = .{
617722 .llvm_name = "flat-inst-offsets",
......@@ -626,13 +731,20 @@ pub const all_features = blk: {
626731 result[@intFromEnum(Feature.flat_scratch_insts)] = .{
627732 .llvm_name = "flat-scratch-insts",
628733 .description = "Have scratch_* flat memory instructions",
629 .dependencies = featureSet(&[_]Feature{}),
734 .dependencies = featureSet(&[_]Feature{
735 .flat_address_space,
736 }),
630737 };
631738 result[@intFromEnum(Feature.flat_segment_offset_bug)] = .{
632739 .llvm_name = "flat-segment-offset-bug",
633740 .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
634741 .dependencies = featureSet(&[_]Feature{}),
635742 };
743 result[@intFromEnum(Feature.fma_mix_bf16_insts)] = .{
744 .llvm_name = "fma-mix-bf16-insts",
745 .description = "Has v_fma_mix_f32_bf16, v_fma_mixlo_bf16, v_fma_mixhi_bf16 instructions",
746 .dependencies = featureSet(&[_]Feature{}),
747 };
636748 result[@intFromEnum(Feature.fma_mix_insts)] = .{
637749 .llvm_name = "fma-mix-insts",
638750 .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
......@@ -722,13 +834,16 @@ pub const all_features = blk: {
722834 .atomic_fmin_fmax_global_f32,
723835 .atomic_fmin_fmax_global_f64,
724836 .ci_insts,
837 .cube_insts,
838 .cvt_norm_insts,
839 .cvt_pknorm_vop2_insts,
840 .cvt_pknorm_vop3_insts,
725841 .default_component_zero,
726842 .dpp,
727843 .dpp8,
728844 .extended_image_insts,
729845 .fast_denormal_f32,
730846 .fast_fmaf,
731 .flat_address_space,
732847 .flat_global_insts,
733848 .flat_inst_offsets,
734849 .flat_scratch_insts,
......@@ -743,14 +858,17 @@ pub const all_features = blk: {
743858 .image_insts,
744859 .int_clamp_insts,
745860 .inv_2pi_inline_imm,
861 .lerp_inst,
746862 .max_hard_clause_length_63,
747863 .mimg_r128,
748864 .movrel,
749865 .no_data_dep_hazard,
750866 .no_sdst_cmpx,
751867 .pk_fmac_f16_inst,
868 .qsad_insts,
752869 .s_memrealtime,
753870 .s_memtime_inst,
871 .sad_insts,
754872 .sdwa,
755873 .sdwa_omod,
756874 .sdwa_scalar,
......@@ -797,13 +915,16 @@ pub const all_features = blk: {
797915 .atomic_fmin_fmax_flat_f32,
798916 .atomic_fmin_fmax_global_f32,
799917 .ci_insts,
918 .cube_insts,
919 .cvt_norm_insts,
920 .cvt_pknorm_vop2_insts,
921 .cvt_pknorm_vop3_insts,
800922 .default_component_zero,
801923 .dpp,
802924 .dpp8,
803925 .extended_image_insts,
804926 .fast_denormal_f32,
805927 .fast_fmaf,
806 .flat_address_space,
807928 .flat_global_insts,
808929 .flat_inst_offsets,
809930 .flat_scratch_insts,
......@@ -821,12 +942,15 @@ pub const all_features = blk: {
821942 .gws,
822943 .int_clamp_insts,
823944 .inv_2pi_inline_imm,
945 .lerp_inst,
824946 .max_hard_clause_length_32,
825947 .mimg_r128,
826948 .movrel,
827949 .no_data_dep_hazard,
828950 .no_sdst_cmpx,
829951 .pk_fmac_f16_inst,
952 .qsad_insts,
953 .sad_insts,
830954 .true16,
831955 .unaligned_buffer_access,
832956 .unaligned_ds_access,
......@@ -850,7 +974,6 @@ pub const all_features = blk: {
850974 .@"16_bit_insts",
851975 .a16,
852976 .add_no_carry_insts,
853 .addressablelocalmemorysize65536,
854977 .agent_scope_fine_grained_remote_memory_atomics,
855978 .aperture_regs,
856979 .atomic_fmin_fmax_flat_f32,
......@@ -861,7 +984,6 @@ pub const all_features = blk: {
861984 .dpp8,
862985 .fast_denormal_f32,
863986 .fast_fmaf,
864 .flat_address_space,
865987 .flat_global_insts,
866988 .flat_inst_offsets,
867989 .flat_scratch_insts,
......@@ -926,11 +1048,14 @@ pub const all_features = blk: {
9261048 .add_no_carry_insts,
9271049 .aperture_regs,
9281050 .ci_insts,
1051 .cube_insts,
1052 .cvt_norm_insts,
1053 .cvt_pknorm_vop2_insts,
1054 .cvt_pknorm_vop3_insts,
9291055 .default_component_zero,
9301056 .dpp,
9311057 .fast_denormal_f32,
9321058 .fast_fmaf,
933 .flat_address_space,
9341059 .flat_global_insts,
9351060 .flat_inst_offsets,
9361061 .flat_scratch_insts,
......@@ -942,10 +1067,13 @@ pub const all_features = blk: {
9421067 .gws,
9431068 .int_clamp_insts,
9441069 .inv_2pi_inline_imm,
1070 .lerp_inst,
9451071 .negative_scratch_offset_bug,
1072 .qsad_insts,
9461073 .r128_a16,
9471074 .s_memrealtime,
9481075 .s_memtime_inst,
1076 .sad_insts,
9491077 .scalar_atomics,
9501078 .scalar_flat_scratch_insts,
9511079 .scalar_stores,
......@@ -997,6 +1125,11 @@ pub const all_features = blk: {
9971125 .description = "Additional instructions for GFX9+",
9981126 .dependencies = featureSet(&[_]Feature{}),
9991127 };
1128 result[@intFromEnum(Feature.globally_addressable_scratch)] = .{
1129 .llvm_name = "globally-addressable-scratch",
1130 .description = "FLAT instructions can access scratch memory for any thread in any wave",
1131 .dependencies = featureSet(&[_]Feature{}),
1132 };
10001133 result[@intFromEnum(Feature.gws)] = .{
10011134 .llvm_name = "gws",
10021135 .description = "Has Global Wave Sync",
......@@ -1072,6 +1205,11 @@ pub const all_features = blk: {
10721205 .description = "The number of LDS banks per compute unit.",
10731206 .dependencies = featureSet(&[_]Feature{}),
10741207 };
1208 result[@intFromEnum(Feature.lerp_inst)] = .{
1209 .llvm_name = "lerp-inst",
1210 .description = "Has v_lerp_u8 instruction",
1211 .dependencies = featureSet(&[_]Feature{}),
1212 };
10751213 result[@intFromEnum(Feature.load_store_opt)] = .{
10761214 .llvm_name = "load-store-opt",
10771215 .description = "Enable SI load/store optimizer pass",
......@@ -1097,6 +1235,11 @@ pub const all_features = blk: {
10971235 .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",
10981236 .dependencies = featureSet(&[_]Feature{}),
10991237 };
1238 result[@intFromEnum(Feature.mad_u32_inst)] = .{
1239 .llvm_name = "mad-u32-inst",
1240 .description = "Has v_mad_u32 instruction",
1241 .dependencies = featureSet(&[_]Feature{}),
1242 };
11001243 result[@intFromEnum(Feature.mai_insts)] = .{
11011244 .llvm_name = "mai-insts",
11021245 .description = "Has mAI instructions",
......@@ -1127,6 +1270,11 @@ pub const all_features = blk: {
11271270 .description = "Maximum private access size may be 8",
11281271 .dependencies = featureSet(&[_]Feature{}),
11291272 };
1273 result[@intFromEnum(Feature.mcast_load_insts)] = .{
1274 .llvm_name = "mcast-load-insts",
1275 .description = "Has multicast load instructions",
1276 .dependencies = featureSet(&[_]Feature{}),
1277 };
11301278 result[@intFromEnum(Feature.memory_atomic_fadd_f32_denormal_support)] = .{
11311279 .llvm_name = "memory-atomic-fadd-f32-denormal-support",
11321280 .description = "global/flat/buffer atomic fadd for float supports denormal handling",
......@@ -1142,6 +1290,11 @@ pub const all_features = blk: {
11421290 .description = "Support 128-bit texture resources",
11431291 .dependencies = featureSet(&[_]Feature{}),
11441292 };
1293 result[@intFromEnum(Feature.min3_max3_pkf16)] = .{
1294 .llvm_name = "min3-max3-pkf16",
1295 .description = "Has v_pk_min3_num_f16 and v_pk_max3_num_f16 instructions",
1296 .dependencies = featureSet(&[_]Feature{}),
1297 };
11451298 result[@intFromEnum(Feature.minimum3_maximum3_f16)] = .{
11461299 .llvm_name = "minimum3-maximum3-f16",
11471300 .description = "Has v_minimum3_f16 and v_maximum3_f16 instructions",
......@@ -1232,6 +1385,11 @@ pub const all_features = blk: {
12321385 .description = "Has v_permlane32_swap_b32 instructions",
12331386 .dependencies = featureSet(&[_]Feature{}),
12341387 };
1388 result[@intFromEnum(Feature.pk_add_min_max_insts)] = .{
1389 .llvm_name = "pk-add-min-max-insts",
1390 .description = "Has v_pk_add_{min|max}_{i|u}16 instructions",
1391 .dependencies = featureSet(&[_]Feature{}),
1392 };
12351393 result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{
12361394 .llvm_name = "pk-fmac-f16-inst",
12371395 .description = "Has v_pk_fmac_f16 instruction",
......@@ -1272,6 +1430,11 @@ pub const all_features = blk: {
12721430 .description = "Has Pseudo Scalar Transcendental instructions",
12731431 .dependencies = featureSet(&[_]Feature{}),
12741432 };
1433 result[@intFromEnum(Feature.qsad_insts)] = .{
1434 .llvm_name = "qsad-insts",
1435 .description = "Has v_qsad* instructions",
1436 .dependencies = featureSet(&[_]Feature{}),
1437 };
12751438 result[@intFromEnum(Feature.r128_a16)] = .{
12761439 .llvm_name = "r128-a16",
12771440 .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
......@@ -1312,6 +1475,21 @@ pub const all_features = blk: {
13121475 .description = "Has s_memtime instruction",
13131476 .dependencies = featureSet(&[_]Feature{}),
13141477 };
1478 result[@intFromEnum(Feature.s_wakeup_barrier_inst)] = .{
1479 .llvm_name = "s-wakeup-barrier-inst",
1480 .description = "Has s_wakeup_barrier instruction.",
1481 .dependencies = featureSet(&[_]Feature{}),
1482 };
1483 result[@intFromEnum(Feature.sad_insts)] = .{
1484 .llvm_name = "sad-insts",
1485 .description = "Has v_sad* instructions",
1486 .dependencies = featureSet(&[_]Feature{}),
1487 };
1488 result[@intFromEnum(Feature.safe_cu_prefetch)] = .{
1489 .llvm_name = "safe-cu-prefetch",
1490 .description = "VMEM CU scope prefetches do not fail on illegal address",
1491 .dependencies = featureSet(&[_]Feature{}),
1492 };
13151493 result[@intFromEnum(Feature.safe_smem_prefetch)] = .{
13161494 .llvm_name = "safe-smem-prefetch",
13171495 .description = "SMEM prefetches do not fail on illegal address",
......@@ -1382,19 +1560,23 @@ pub const all_features = blk: {
13821560 .atomic_fmin_fmax_global_f32,
13831561 .atomic_fmin_fmax_global_f64,
13841562 .ci_insts,
1563 .cube_insts,
1564 .cvt_pknorm_vop2_insts,
13851565 .default_component_zero,
13861566 .ds_src2_insts,
13871567 .extended_image_insts,
1388 .flat_address_space,
13891568 .fp64,
13901569 .gds,
13911570 .gfx7_gfx8_gfx9_insts,
13921571 .gws,
13931572 .image_insts,
1573 .lerp_inst,
13941574 .mad_mac_f32_insts,
13951575 .mimg_r128,
13961576 .movrel,
1577 .qsad_insts,
13971578 .s_memtime_inst,
1579 .sad_insts,
13981580 .trig_reduced_range,
13991581 .unaligned_buffer_access,
14001582 .vmem_write_vgpr_in_order,
......@@ -1406,6 +1588,11 @@ pub const all_features = blk: {
14061588 .description = "Has s_setprio_inc_wg instruction.",
14071589 .dependencies = featureSet(&[_]Feature{}),
14081590 };
1591 result[@intFromEnum(Feature.setreg_vgpr_msb_fixup)] = .{
1592 .llvm_name = "setreg-vgpr-msb-fixup",
1593 .description = "S_SETREG to MODE clobbers VGPR MSB bits, requires fixup",
1594 .dependencies = featureSet(&[_]Feature{}),
1595 };
14091596 result[@intFromEnum(Feature.sgpr_init_bug)] = .{
14101597 .llvm_name = "sgpr-init-bug",
14111598 .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
......@@ -1438,6 +1625,8 @@ pub const all_features = blk: {
14381625 .addressablelocalmemorysize32768,
14391626 .atomic_fmin_fmax_global_f32,
14401627 .atomic_fmin_fmax_global_f64,
1628 .cube_insts,
1629 .cvt_pknorm_vop2_insts,
14411630 .default_component_zero,
14421631 .ds_src2_insts,
14431632 .extended_image_insts,
......@@ -1446,10 +1635,12 @@ pub const all_features = blk: {
14461635 .gws,
14471636 .image_insts,
14481637 .ldsbankcount32,
1638 .lerp_inst,
14491639 .mad_mac_f32_insts,
14501640 .mimg_r128,
14511641 .movrel,
14521642 .s_memtime_inst,
1643 .sad_insts,
14531644 .trig_reduced_range,
14541645 .vmem_write_vgpr_in_order,
14551646 .wavefrontsize64,
......@@ -1465,6 +1656,16 @@ pub const all_features = blk: {
14651656 .description = "Hardware supports SRAMECC",
14661657 .dependencies = featureSet(&[_]Feature{}),
14671658 };
1659 result[@intFromEnum(Feature.tanh_insts)] = .{
1660 .llvm_name = "tanh-insts",
1661 .description = "Has v_tanh_f32/f16 instructions",
1662 .dependencies = featureSet(&[_]Feature{}),
1663 };
1664 result[@intFromEnum(Feature.tensor_cvt_lut_insts)] = .{
1665 .llvm_name = "tensor-cvt-lut-insts",
1666 .description = "Has v_perm_pk16* instructions",
1667 .dependencies = featureSet(&[_]Feature{}),
1668 };
14681669 result[@intFromEnum(Feature.tgsplit)] = .{
14691670 .llvm_name = "tgsplit",
14701671 .description = "Enable threadgroup split execution",
......@@ -1540,11 +1741,21 @@ pub const all_features = blk: {
15401741 .description = "TODO: describe me",
15411742 .dependencies = featureSet(&[_]Feature{}),
15421743 };
1744 result[@intFromEnum(Feature.vgpr_align2)] = .{
1745 .llvm_name = "vgpr-align2",
1746 .description = "VGPR and AGPR tuple operands require even alignment",
1747 .dependencies = featureSet(&[_]Feature{}),
1748 };
15431749 result[@intFromEnum(Feature.vgpr_index_mode)] = .{
15441750 .llvm_name = "vgpr-index-mode",
15451751 .description = "Has VGPR mode register indexing",
15461752 .dependencies = featureSet(&[_]Feature{}),
15471753 };
1754 result[@intFromEnum(Feature.vmem_pref_insts)] = .{
1755 .llvm_name = "vmem-pref-insts",
1756 .description = "Has flat_prefect_b8 and global_prefetch_b8 instructions",
1757 .dependencies = featureSet(&[_]Feature{}),
1758 };
15481759 result[@intFromEnum(Feature.vmem_to_lds_load_insts)] = .{
15491760 .llvm_name = "vmem-to-lds-load-insts",
15501761 .description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_load w/lds bit set or global_load_lds. This does not include scratch_load_lds.",
......@@ -1567,6 +1778,8 @@ pub const all_features = blk: {
15671778 .@"16_bit_insts",
15681779 .addressablelocalmemorysize65536,
15691780 .ci_insts,
1781 .cube_insts,
1782 .cvt_pknorm_vop2_insts,
15701783 .default_component_zero,
15711784 .dpp,
15721785 .ds_src2_insts,
......@@ -1582,11 +1795,14 @@ pub const all_features = blk: {
15821795 .image_insts,
15831796 .int_clamp_insts,
15841797 .inv_2pi_inline_imm,
1798 .lerp_inst,
15851799 .mad_mac_f32_insts,
15861800 .mimg_r128,
15871801 .movrel,
1802 .qsad_insts,
15881803 .s_memrealtime,
15891804 .s_memtime_inst,
1805 .sad_insts,
15901806 .scalar_stores,
15911807 .sdwa,
15921808 .sdwa_mav,
......@@ -1623,6 +1839,11 @@ pub const all_features = blk: {
16231839 .description = "Has s_wait_xcnt instruction",
16241840 .dependencies = featureSet(&[_]Feature{}),
16251841 };
1842 result[@intFromEnum(Feature.waits_before_system_scope_stores)] = .{
1843 .llvm_name = "waits-before-system-scope-stores",
1844 .description = "Target requires waits for loads and atomics before system scope stores",
1845 .dependencies = featureSet(&[_]Feature{}),
1846 };
16261847 result[@intFromEnum(Feature.wavefrontsize16)] = .{
16271848 .llvm_name = "wavefrontsize16",
16281849 .description = "The number of threads per wavefront",
......@@ -2044,6 +2265,8 @@ pub const cpu = struct {
20442265 .architected_flat_scratch,
20452266 .atomic_fadd_no_rtn_insts,
20462267 .atomic_fadd_rtn_insts,
2268 .back_off_barrier,
2269 .d16_write_vgpr32,
20472270 .dl_insts,
20482271 .dot10_insts,
20492272 .dot12_insts,
......@@ -2077,6 +2300,8 @@ pub const cpu = struct {
20772300 .architected_flat_scratch,
20782301 .atomic_fadd_no_rtn_insts,
20792302 .atomic_fadd_rtn_insts,
2303 .back_off_barrier,
2304 .d16_write_vgpr32,
20802305 .dl_insts,
20812306 .dot10_insts,
20822307 .dot12_insts,
......@@ -2108,6 +2333,8 @@ pub const cpu = struct {
21082333 .architected_flat_scratch,
21092334 .atomic_fadd_no_rtn_insts,
21102335 .atomic_fadd_rtn_insts,
2336 .back_off_barrier,
2337 .d16_write_vgpr32,
21112338 .dl_insts,
21122339 .dot10_insts,
21132340 .dot12_insts,
......@@ -2140,6 +2367,8 @@ pub const cpu = struct {
21402367 .architected_flat_scratch,
21412368 .atomic_fadd_no_rtn_insts,
21422369 .atomic_fadd_rtn_insts,
2370 .back_off_barrier,
2371 .d16_write_vgpr32,
21432372 .dl_insts,
21442373 .dot10_insts,
21452374 .dot12_insts,
......@@ -2171,6 +2400,8 @@ pub const cpu = struct {
21712400 .architected_flat_scratch,
21722401 .atomic_fadd_no_rtn_insts,
21732402 .atomic_fadd_rtn_insts,
2403 .back_off_barrier,
2404 .d16_write_vgpr32,
21742405 .dl_insts,
21752406 .dot10_insts,
21762407 .dot12_insts,
......@@ -2188,6 +2419,7 @@ pub const cpu = struct {
21882419 .packed_tid,
21892420 .partial_nsa_encoding,
21902421 .point_sample_accel,
2422 .real_true16,
21912423 .required_export_priority,
21922424 .salu_float,
21932425 .shader_cycles_register,
......@@ -2202,6 +2434,8 @@ pub const cpu = struct {
22022434 .architected_flat_scratch,
22032435 .atomic_fadd_no_rtn_insts,
22042436 .atomic_fadd_rtn_insts,
2437 .back_off_barrier,
2438 .d16_write_vgpr32,
22052439 .dl_insts,
22062440 .dot10_insts,
22072441 .dot12_insts,
......@@ -2219,6 +2453,7 @@ pub const cpu = struct {
22192453 .packed_tid,
22202454 .partial_nsa_encoding,
22212455 .point_sample_accel,
2456 .real_true16,
22222457 .required_export_priority,
22232458 .salu_float,
22242459 .shader_cycles_register,
......@@ -2232,6 +2467,8 @@ pub const cpu = struct {
22322467 .architected_flat_scratch,
22332468 .atomic_fadd_no_rtn_insts,
22342469 .atomic_fadd_rtn_insts,
2470 .back_off_barrier,
2471 .d16_write_vgpr32,
22352472 .dl_insts,
22362473 .dot10_insts,
22372474 .dot12_insts,
......@@ -2249,6 +2486,7 @@ pub const cpu = struct {
22492486 .packed_tid,
22502487 .partial_nsa_encoding,
22512488 .point_sample_accel,
2489 .real_true16,
22522490 .required_export_priority,
22532491 .salu_float,
22542492 .shader_cycles_register,
......@@ -2262,6 +2500,8 @@ pub const cpu = struct {
22622500 .architected_flat_scratch,
22632501 .atomic_fadd_no_rtn_insts,
22642502 .atomic_fadd_rtn_insts,
2503 .back_off_barrier,
2504 .d16_write_vgpr32,
22652505 .dl_insts,
22662506 .dot10_insts,
22672507 .dot12_insts,
......@@ -2278,6 +2518,7 @@ pub const cpu = struct {
22782518 .nsa_encoding,
22792519 .packed_tid,
22802520 .partial_nsa_encoding,
2521 .real_true16,
22812522 .required_export_priority,
22822523 .salu_float,
22832524 .shader_cycles_register,
......@@ -2291,6 +2532,8 @@ pub const cpu = struct {
22912532 .architected_flat_scratch,
22922533 .atomic_fadd_no_rtn_insts,
22932534 .atomic_fadd_rtn_insts,
2535 .back_off_barrier,
2536 .d16_write_vgpr32,
22942537 .dl_insts,
22952538 .dot10_insts,
22962539 .dot12_insts,
......@@ -2309,6 +2552,7 @@ pub const cpu = struct {
23092552 .packed_tid,
23102553 .partial_nsa_encoding,
23112554 .priv_enabled_trap2_nop_bug,
2555 .real_true16,
23122556 .required_export_priority,
23132557 .requires_cov6,
23142558 .shader_cycles_register,
......@@ -2321,6 +2565,7 @@ pub const cpu = struct {
23212565 .name = "gfx1200",
23222566 .llvm_name = "gfx1200",
23232567 .features = featureSet(&[_]Feature{
2568 .addressablelocalmemorysize65536,
23242569 .allocate1_5xvgprs,
23252570 .architected_flat_scratch,
23262571 .architected_sgprs,
......@@ -2331,7 +2576,13 @@ pub const cpu = struct {
23312576 .atomic_fadd_rtn_insts,
23322577 .atomic_flat_pk_add_16_insts,
23332578 .atomic_global_pk_add_bf16_inst,
2579 .back_off_barrier,
23342580 .bvh_dual_bvh_8_insts,
2581 .cube_insts,
2582 .cvt_norm_insts,
2583 .cvt_pknorm_vop2_insts,
2584 .cvt_pknorm_vop3_insts,
2585 .d16_write_vgpr32,
23352586 .dl_insts,
23362587 .dot10_insts,
23372588 .dot11_insts,
......@@ -2346,22 +2597,27 @@ pub const cpu = struct {
23462597 .gfx12,
23472598 .image_insts,
23482599 .ldsbankcount32,
2600 .lerp_inst,
23492601 .memory_atomic_fadd_f32_denormal_support,
23502602 .nsa_encoding,
23512603 .packed_tid,
23522604 .partial_nsa_encoding,
23532605 .pseudo_scalar_trans,
2606 .qsad_insts,
23542607 .restricted_soffset,
2608 .sad_insts,
23552609 .salu_float,
23562610 .scalar_dwordx3_loads,
23572611 .shader_cycles_hi_lo_registers,
23582612 .vcmpx_permlane_hazard,
2613 .waits_before_system_scope_stores,
23592614 }),
23602615 };
23612616 pub const gfx1201: CpuModel = .{
23622617 .name = "gfx1201",
23632618 .llvm_name = "gfx1201",
23642619 .features = featureSet(&[_]Feature{
2620 .addressablelocalmemorysize65536,
23652621 .allocate1_5xvgprs,
23662622 .architected_flat_scratch,
23672623 .architected_sgprs,
......@@ -2372,7 +2628,13 @@ pub const cpu = struct {
23722628 .atomic_fadd_rtn_insts,
23732629 .atomic_flat_pk_add_16_insts,
23742630 .atomic_global_pk_add_bf16_inst,
2631 .back_off_barrier,
23752632 .bvh_dual_bvh_8_insts,
2633 .cube_insts,
2634 .cvt_norm_insts,
2635 .cvt_pknorm_vop2_insts,
2636 .cvt_pknorm_vop3_insts,
2637 .d16_write_vgpr32,
23762638 .dl_insts,
23772639 .dot10_insts,
23782640 .dot11_insts,
......@@ -2387,23 +2649,32 @@ pub const cpu = struct {
23872649 .gfx12,
23882650 .image_insts,
23892651 .ldsbankcount32,
2652 .lerp_inst,
23902653 .memory_atomic_fadd_f32_denormal_support,
23912654 .nsa_encoding,
23922655 .packed_tid,
23932656 .partial_nsa_encoding,
23942657 .pseudo_scalar_trans,
2658 .qsad_insts,
23952659 .restricted_soffset,
2660 .sad_insts,
23962661 .salu_float,
23972662 .scalar_dwordx3_loads,
23982663 .shader_cycles_hi_lo_registers,
23992664 .vcmpx_permlane_hazard,
2665 .waits_before_system_scope_stores,
24002666 }),
24012667 };
24022668 pub const gfx1250: CpuModel = .{
24032669 .name = "gfx1250",
24042670 .llvm_name = "gfx1250",
24052671 .features = featureSet(&[_]Feature{
2672 .@"1024_addressable_vgprs",
2673 .@"45_bit_num_records_buffer_resource",
24062674 .@"64_bit_literals",
2675 .add_min_max_insts,
2676 .add_sub_u64_insts,
2677 .addressablelocalmemorysize327680,
24072678 .architected_flat_scratch,
24082679 .architected_sgprs,
24092680 .ashr_pk_insts,
......@@ -2417,49 +2688,164 @@ pub const cpu = struct {
24172688 .atomic_fmin_fmax_global_f64,
24182689 .atomic_global_pk_add_bf16_inst,
24192690 .bf16_cvt_insts,
2691 .bf16_pk_insts,
24202692 .bf16_trans_insts,
24212693 .bitop3_insts,
2694 .clusters,
2695 .cube_insts,
24222696 .cumode,
2697 .cvt_norm_insts,
24232698 .cvt_pk_f16_f32_inst,
2699 .cvt_pknorm_vop2_insts,
2700 .cvt_pknorm_vop3_insts,
2701 .d16_write_vgpr32,
24242702 .dl_insts,
24252703 .dot7_insts,
24262704 .dot8_insts,
24272705 .dpp_src1_sgpr,
2706 .emulated_system_scope_atomics,
24282707 .flat_atomic_fadd_f32_inst,
24292708 .flat_buffer_global_fadd_f64_inst,
2709 .flat_gvs_mode,
2710 .fma_mix_bf16_insts,
24302711 .fmacf64_inst,
24312712 .fp8_conversion_insts,
24322713 .fp8e5m3_insts,
24332714 .gfx12,
24342715 .gfx1250_insts,
2716 .globally_addressable_scratch,
24352717 .kernarg_preload,
24362718 .lds_barrier_arrive_atomic,
24372719 .ldsbankcount32,
2720 .lerp_inst,
24382721 .lshl_add_u64_inst,
2722 .mad_u32_inst,
24392723 .max_hard_clause_length_63,
2724 .mcast_load_insts,
24402725 .memory_atomic_fadd_f32_denormal_support,
2726 .min3_max3_pkf16,
24412727 .minimum3_maximum3_pkf16,
24422728 .packed_fp32_ops,
24432729 .packed_tid,
24442730 .permlane16_swap,
2731 .pk_add_min_max_insts,
24452732 .prng_inst,
24462733 .pseudo_scalar_trans,
2734 .qsad_insts,
24472735 .restricted_soffset,
2736 .s_wakeup_barrier_inst,
2737 .sad_insts,
24482738 .salu_float,
24492739 .scalar_dwordx3_loads,
24502740 .setprio_inc_wg_inst,
2741 .setreg_vgpr_msb_fixup,
24512742 .shader_cycles_hi_lo_registers,
24522743 .sramecc_support,
2744 .tanh_insts,
2745 .tensor_cvt_lut_insts,
24532746 .transpose_load_f4f6_insts,
24542747 .vcmpx_permlane_hazard,
2748 .vgpr_align2,
2749 .vmem_pref_insts,
24552750 .wait_xcnt,
24562751 .wavefrontsize32,
2752 .xnack,
2753 .xnack_support,
2754 }),
2755 };
2756 pub const gfx1251: CpuModel = .{
2757 .name = "gfx1251",
2758 .llvm_name = "gfx1251",
2759 .features = featureSet(&[_]Feature{
2760 .@"1024_addressable_vgprs",
2761 .@"45_bit_num_records_buffer_resource",
2762 .@"64_bit_literals",
2763 .add_min_max_insts,
2764 .add_sub_u64_insts,
2765 .addressablelocalmemorysize327680,
2766 .architected_flat_scratch,
2767 .architected_sgprs,
2768 .ashr_pk_insts,
2769 .atomic_buffer_global_pk_add_f16_insts,
2770 .atomic_buffer_pk_add_bf16_inst,
2771 .atomic_ds_pk_add_16_insts,
2772 .atomic_fadd_no_rtn_insts,
2773 .atomic_fadd_rtn_insts,
2774 .atomic_flat_pk_add_16_insts,
2775 .atomic_fmin_fmax_flat_f64,
2776 .atomic_fmin_fmax_global_f64,
2777 .atomic_global_pk_add_bf16_inst,
2778 .bf16_cvt_insts,
2779 .bf16_pk_insts,
2780 .bf16_trans_insts,
2781 .bitop3_insts,
2782 .clusters,
2783 .cube_insts,
2784 .cumode,
2785 .cvt_norm_insts,
2786 .cvt_pk_f16_f32_inst,
2787 .cvt_pknorm_vop2_insts,
2788 .cvt_pknorm_vop3_insts,
2789 .d16_write_vgpr32,
2790 .dl_insts,
2791 .dot7_insts,
2792 .dot8_insts,
2793 .dpp_64bit,
2794 .dpp_src1_sgpr,
2795 .emulated_system_scope_atomics,
2796 .flat_atomic_fadd_f32_inst,
2797 .flat_buffer_global_fadd_f64_inst,
2798 .flat_gvs_mode,
2799 .fma_mix_bf16_insts,
2800 .fmacf64_inst,
2801 .fp8_conversion_insts,
2802 .fp8e5m3_insts,
2803 .gfx12,
2804 .gfx1250_insts,
2805 .globally_addressable_scratch,
2806 .kernarg_preload,
2807 .lds_barrier_arrive_atomic,
2808 .ldsbankcount32,
2809 .lerp_inst,
2810 .lshl_add_u64_inst,
2811 .mad_u32_inst,
2812 .max_hard_clause_length_63,
2813 .mcast_load_insts,
2814 .memory_atomic_fadd_f32_denormal_support,
2815 .min3_max3_pkf16,
2816 .minimum3_maximum3_pkf16,
2817 .packed_fp32_ops,
2818 .packed_tid,
2819 .permlane16_swap,
2820 .pk_add_min_max_insts,
2821 .prng_inst,
2822 .pseudo_scalar_trans,
2823 .qsad_insts,
2824 .restricted_soffset,
2825 .s_wakeup_barrier_inst,
2826 .sad_insts,
2827 .salu_float,
2828 .scalar_dwordx3_loads,
2829 .setprio_inc_wg_inst,
2830 .shader_cycles_hi_lo_registers,
2831 .sramecc_support,
2832 .tanh_insts,
2833 .tensor_cvt_lut_insts,
2834 .transpose_load_f4f6_insts,
2835 .vcmpx_permlane_hazard,
2836 .vgpr_align2,
2837 .vmem_pref_insts,
2838 .wait_xcnt,
2839 .wavefrontsize32,
2840 .xnack,
2841 .xnack_support,
24572842 }),
24582843 };
24592844 pub const gfx12_generic: CpuModel = .{
24602845 .name = "gfx12_generic",
24612846 .llvm_name = "gfx12-generic",
24622847 .features = featureSet(&[_]Feature{
2848 .addressablelocalmemorysize65536,
24632849 .allocate1_5xvgprs,
24642850 .architected_flat_scratch,
24652851 .architected_sgprs,
......@@ -2470,7 +2856,13 @@ pub const cpu = struct {
24702856 .atomic_fadd_rtn_insts,
24712857 .atomic_flat_pk_add_16_insts,
24722858 .atomic_global_pk_add_bf16_inst,
2859 .back_off_barrier,
24732860 .bvh_dual_bvh_8_insts,
2861 .cube_insts,
2862 .cvt_norm_insts,
2863 .cvt_pknorm_vop2_insts,
2864 .cvt_pknorm_vop3_insts,
2865 .d16_write_vgpr32,
24742866 .dl_insts,
24752867 .dot10_insts,
24762868 .dot11_insts,
......@@ -2485,17 +2877,21 @@ pub const cpu = struct {
24852877 .gfx12,
24862878 .image_insts,
24872879 .ldsbankcount32,
2880 .lerp_inst,
24882881 .memory_atomic_fadd_f32_denormal_support,
24892882 .nsa_encoding,
24902883 .packed_tid,
24912884 .partial_nsa_encoding,
24922885 .pseudo_scalar_trans,
2886 .qsad_insts,
24932887 .requires_cov6,
24942888 .restricted_soffset,
2889 .sad_insts,
24952890 .salu_float,
24962891 .scalar_dwordx3_loads,
24972892 .shader_cycles_hi_lo_registers,
24982893 .vcmpx_permlane_hazard,
2894 .waits_before_system_scope_stores,
24992895 }),
25002896 };
25012897 pub const gfx600: CpuModel = .{
......@@ -2779,6 +3175,7 @@ pub const cpu = struct {
27793175 .packed_tid,
27803176 .pk_fmac_f16_inst,
27813177 .sramecc_support,
3178 .vgpr_align2,
27823179 }),
27833180 };
27843181 pub const gfx90c: CpuModel = .{
......@@ -2842,6 +3239,7 @@ pub const cpu = struct {
28423239 .packed_tid,
28433240 .pk_fmac_f16_inst,
28443241 .sramecc_support,
3242 .vgpr_align2,
28453243 .xf32_insts,
28463244 }),
28473245 };
......@@ -2897,6 +3295,7 @@ pub const cpu = struct {
28973295 .pk_fmac_f16_inst,
28983296 .prng_inst,
28993297 .sramecc_support,
3298 .vgpr_align2,
29003299 }),
29013300 };
29023301 pub const gfx9_4_generic: CpuModel = .{
......@@ -2943,6 +3342,7 @@ pub const cpu = struct {
29433342 .pk_fmac_f16_inst,
29443343 .requires_cov6,
29453344 .sramecc_support,
3345 .vgpr_align2,
29463346 }),
29473347 };
29483348 pub const gfx9_generic: CpuModel = .{
lib/std/Target/arm.zig+40-6
......@@ -88,6 +88,7 @@ pub const Feature = enum {
8888 has_v9_4a,
8989 has_v9_5a,
9090 has_v9_6a,
91 has_v9_7a,
9192 has_v9a,
9293 hwdiv,
9394 hwdiv_arm,
......@@ -107,7 +108,6 @@ pub const Feature = enum {
107108 mve2beat,
108109 mve4beat,
109110 mve_fp,
110 nacl_trap,
111111 neon,
112112 neon_fpmovs,
113113 neonfp,
......@@ -187,6 +187,7 @@ pub const Feature = enum {
187187 v9_4a,
188188 v9_5a,
189189 v9_6a,
190 v9_7a,
190191 v9a,
191192 vfp2,
192193 vfp2sp,
......@@ -748,6 +749,13 @@ pub const all_features = blk: {
748749 .has_v9_5a,
749750 }),
750751 };
752 result[@intFromEnum(Feature.has_v9_7a)] = .{
753 .llvm_name = "v9.7a",
754 .description = "Support ARM v9.7a instructions",
755 .dependencies = featureSet(&[_]Feature{
756 .has_v9_6a,
757 }),
758 };
751759 result[@intFromEnum(Feature.has_v9a)] = .{
752760 .llvm_name = "v9a",
753761 .description = "Support ARM v9a instructions",
......@@ -859,11 +867,6 @@ pub const all_features = blk: {
859867 .mve,
860868 }),
861869 };
862 result[@intFromEnum(Feature.nacl_trap)] = .{
863 .llvm_name = "nacl-trap",
864 .description = "NaCl trap",
865 .dependencies = featureSet(&[_]Feature{}),
866 };
867870 result[@intFromEnum(Feature.neon)] = .{
868871 .llvm_name = "neon",
869872 .description = "Enable NEON instructions",
......@@ -1579,6 +1582,22 @@ pub const all_features = blk: {
15791582 .virtualization,
15801583 }),
15811584 };
1585 result[@intFromEnum(Feature.v9_7a)] = .{
1586 .llvm_name = "armv9.7-a",
1587 .description = "ARMv97a architecture",
1588 .dependencies = featureSet(&[_]Feature{
1589 .aclass,
1590 .crc,
1591 .db,
1592 .dsp,
1593 .fp_armv8,
1594 .has_v9_7a,
1595 .mp,
1596 .ras,
1597 .trustzone,
1598 .virtualization,
1599 }),
1600 };
15821601 result[@intFromEnum(Feature.v9a)] = .{
15831602 .llvm_name = "armv9-a",
15841603 .description = "ARMv9a architecture",
......@@ -2658,6 +2677,21 @@ pub const cpu = struct {
26582677 .v8m_main,
26592678 }),
26602679 };
2680 pub const star_mc3: CpuModel = .{
2681 .name = "star_mc3",
2682 .llvm_name = "star-mc3",
2683 .features = featureSet(&[_]Feature{
2684 .fp_armv8d16,
2685 .loop_align,
2686 .mve1beat,
2687 .mve_fp,
2688 .no_branch_predictor,
2689 .pacbti,
2690 .slowfpvmlx,
2691 .use_misched,
2692 .v8_1m_main,
2693 }),
2694 };
26612695 pub const strongarm: CpuModel = .{
26622696 .name = "strongarm",
26632697 .llvm_name = "strongarm",
lib/std/Target/bpf.zig+6
......@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
55const CpuModel = std.Target.Cpu.Model;
66
77pub const Feature = enum {
8 allows_misaligned_mem_access,
89 alu32,
910 dummy,
1011 dwarfris,
......@@ -19,6 +20,11 @@ pub const all_features = blk: {
1920 const len = @typeInfo(Feature).@"enum".fields.len;
2021 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
2122 var result: [len]CpuFeature = undefined;
23 result[@intFromEnum(Feature.allows_misaligned_mem_access)] = .{
24 .llvm_name = "allows-misaligned-mem-access",
25 .description = "Allows misaligned memory access",
26 .dependencies = featureSet(&[_]Feature{}),
27 };
2228 result[@intFromEnum(Feature.alu32)] = .{
2329 .llvm_name = "alu32",
2430 .description = "Enable ALU32 instructions",
lib/std/Target/hexagon.zig+41-6
......@@ -25,6 +25,7 @@ pub const Feature = enum {
2525 hvxv73,
2626 hvxv75,
2727 hvxv79,
28 hvxv81,
2829 long_calls,
2930 mem_noshuf,
3031 memops,
......@@ -36,7 +37,6 @@ pub const Feature = enum {
3637 reserved_r19,
3738 small_data,
3839 tinycore,
39 unsafe_fp,
4040 v5,
4141 v55,
4242 v60,
......@@ -50,6 +50,7 @@ pub const Feature = enum {
5050 v73,
5151 v75,
5252 v79,
53 v81,
5354 zreg,
5455};
5556
......@@ -189,6 +190,13 @@ pub const all_features = blk: {
189190 .hvxv75,
190191 }),
191192 };
193 result[@intFromEnum(Feature.hvxv81)] = .{
194 .llvm_name = "hvxv81",
195 .description = "Hexagon HVX instructions",
196 .dependencies = featureSet(&[_]Feature{
197 .hvxv79,
198 }),
199 };
192200 result[@intFromEnum(Feature.long_calls)] = .{
193201 .llvm_name = "long-calls",
194202 .description = "Use constant-extended calls",
......@@ -248,11 +256,6 @@ pub const all_features = blk: {
248256 .description = "Hexagon Tiny Core",
249257 .dependencies = featureSet(&[_]Feature{}),
250258 };
251 result[@intFromEnum(Feature.unsafe_fp)] = .{
252 .llvm_name = "unsafe-fp",
253 .description = "Use unsafe FP math",
254 .dependencies = featureSet(&[_]Feature{}),
255 };
256259 result[@intFromEnum(Feature.v5)] = .{
257260 .llvm_name = "v5",
258261 .description = "Enable Hexagon V5 architecture",
......@@ -318,6 +321,11 @@ pub const all_features = blk: {
318321 .description = "Enable Hexagon V79 architecture",
319322 .dependencies = featureSet(&[_]Feature{}),
320323 };
324 result[@intFromEnum(Feature.v81)] = .{
325 .llvm_name = "v81",
326 .description = "Enable Hexagon V81 architecture",
327 .dependencies = featureSet(&[_]Feature{}),
328 };
321329 result[@intFromEnum(Feature.zreg)] = .{
322330 .llvm_name = "zreg",
323331 .description = "Hexagon ZReg extension instructions",
......@@ -662,4 +670,31 @@ pub const cpu = struct {
662670 .v79,
663671 }),
664672 };
673 pub const hexagonv81: CpuModel = .{
674 .name = "hexagonv81",
675 .llvm_name = "hexagonv81",
676 .features = featureSet(&[_]Feature{
677 .compound,
678 .duplex,
679 .mem_noshuf,
680 .memops,
681 .nvj,
682 .nvs,
683 .small_data,
684 .v5,
685 .v55,
686 .v60,
687 .v62,
688 .v65,
689 .v66,
690 .v67,
691 .v68,
692 .v69,
693 .v71,
694 .v73,
695 .v75,
696 .v79,
697 .v81,
698 }),
699 };
665700};
lib/std/Target/mips.zig+6
......@@ -56,6 +56,7 @@ pub const Feature = enum {
5656 soft_float,
5757 strict_align,
5858 sym32,
59 use_compact_branches,
5960 use_indirect_jump_hazard,
6061 use_tcc_in_div,
6162 vfpu,
......@@ -391,6 +392,11 @@ pub const all_features = blk: {
391392 .description = "Symbols are 32 bit on Mips64",
392393 .dependencies = featureSet(&[_]Feature{}),
393394 };
395 result[@intFromEnum(Feature.use_compact_branches)] = .{
396 .llvm_name = "use-compact-branches",
397 .description = "Use compact branch instructions for MIPS32R6/MIPS64R6",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
394400 result[@intFromEnum(Feature.use_indirect_jump_hazard)] = .{
395401 .llvm_name = "use-indirect-jump-hazard",
396402 .description = "Use indirect jump guards to prevent certain speculation based attacks",
lib/std/Target/nvptx.zig+58-35
......@@ -35,6 +35,7 @@ pub const Feature = enum {
3535 ptx86,
3636 ptx87,
3737 ptx88,
38 ptx90,
3839 sm_100,
3940 sm_100a,
4041 sm_100f,
......@@ -44,6 +45,9 @@ pub const Feature = enum {
4445 sm_103,
4546 sm_103a,
4647 sm_103f,
48 sm_110,
49 sm_110a,
50 sm_110f,
4751 sm_120,
4852 sm_120a,
4953 sm_120f,
......@@ -68,6 +72,7 @@ pub const Feature = enum {
6872 sm_80,
6973 sm_86,
7074 sm_87,
75 sm_88,
7176 sm_89,
7277 sm_90,
7378 sm_90a,
......@@ -232,6 +237,11 @@ pub const all_features = blk: {
232237 .description = "Use PTX version 88",
233238 .dependencies = featureSet(&[_]Feature{}),
234239 };
240 result[@intFromEnum(Feature.ptx90)] = .{
241 .llvm_name = "ptx90",
242 .description = "Use PTX version 90",
243 .dependencies = featureSet(&[_]Feature{}),
244 };
235245 result[@intFromEnum(Feature.sm_100)] = .{
236246 .llvm_name = "sm_100",
237247 .description = "Target SM 100",
......@@ -277,6 +287,21 @@ pub const all_features = blk: {
277287 .description = "Target SM 103f",
278288 .dependencies = featureSet(&[_]Feature{}),
279289 };
290 result[@intFromEnum(Feature.sm_110)] = .{
291 .llvm_name = "sm_110",
292 .description = "Target SM 110",
293 .dependencies = featureSet(&[_]Feature{}),
294 };
295 result[@intFromEnum(Feature.sm_110a)] = .{
296 .llvm_name = "sm_110a",
297 .description = "Target SM 110a",
298 .dependencies = featureSet(&[_]Feature{}),
299 };
300 result[@intFromEnum(Feature.sm_110f)] = .{
301 .llvm_name = "sm_110f",
302 .description = "Target SM 110f",
303 .dependencies = featureSet(&[_]Feature{}),
304 };
280305 result[@intFromEnum(Feature.sm_120)] = .{
281306 .llvm_name = "sm_120",
282307 .description = "Target SM 120",
......@@ -397,6 +422,11 @@ pub const all_features = blk: {
397422 .description = "Target SM 87",
398423 .dependencies = featureSet(&[_]Feature{}),
399424 };
425 result[@intFromEnum(Feature.sm_88)] = .{
426 .llvm_name = "sm_88",
427 .description = "Target SM 88",
428 .dependencies = featureSet(&[_]Feature{}),
429 };
400430 result[@intFromEnum(Feature.sm_89)] = .{
401431 .llvm_name = "sm_89",
402432 .description = "Target SM 89",
......@@ -425,7 +455,6 @@ pub const cpu = struct {
425455 .name = "sm_100",
426456 .llvm_name = "sm_100",
427457 .features = featureSet(&[_]Feature{
428 .ptx86,
429458 .sm_100,
430459 }),
431460 };
......@@ -433,7 +462,6 @@ pub const cpu = struct {
433462 .name = "sm_100a",
434463 .llvm_name = "sm_100a",
435464 .features = featureSet(&[_]Feature{
436 .ptx86,
437465 .sm_100a,
438466 }),
439467 };
......@@ -441,7 +469,6 @@ pub const cpu = struct {
441469 .name = "sm_100f",
442470 .llvm_name = "sm_100f",
443471 .features = featureSet(&[_]Feature{
444 .ptx88,
445472 .sm_100f,
446473 }),
447474 };
......@@ -449,7 +476,6 @@ pub const cpu = struct {
449476 .name = "sm_101",
450477 .llvm_name = "sm_101",
451478 .features = featureSet(&[_]Feature{
452 .ptx86,
453479 .sm_101,
454480 }),
455481 };
......@@ -457,7 +483,6 @@ pub const cpu = struct {
457483 .name = "sm_101a",
458484 .llvm_name = "sm_101a",
459485 .features = featureSet(&[_]Feature{
460 .ptx86,
461486 .sm_101a,
462487 }),
463488 };
......@@ -465,7 +490,6 @@ pub const cpu = struct {
465490 .name = "sm_101f",
466491 .llvm_name = "sm_101f",
467492 .features = featureSet(&[_]Feature{
468 .ptx88,
469493 .sm_101f,
470494 }),
471495 };
......@@ -473,7 +497,6 @@ pub const cpu = struct {
473497 .name = "sm_103",
474498 .llvm_name = "sm_103",
475499 .features = featureSet(&[_]Feature{
476 .ptx88,
477500 .sm_103,
478501 }),
479502 };
......@@ -481,7 +504,6 @@ pub const cpu = struct {
481504 .name = "sm_103a",
482505 .llvm_name = "sm_103a",
483506 .features = featureSet(&[_]Feature{
484 .ptx88,
485507 .sm_103a,
486508 }),
487509 };
......@@ -489,15 +511,34 @@ pub const cpu = struct {
489511 .name = "sm_103f",
490512 .llvm_name = "sm_103f",
491513 .features = featureSet(&[_]Feature{
492 .ptx88,
493514 .sm_103f,
494515 }),
495516 };
517 pub const sm_110: CpuModel = .{
518 .name = "sm_110",
519 .llvm_name = "sm_110",
520 .features = featureSet(&[_]Feature{
521 .sm_110,
522 }),
523 };
524 pub const sm_110a: CpuModel = .{
525 .name = "sm_110a",
526 .llvm_name = "sm_110a",
527 .features = featureSet(&[_]Feature{
528 .sm_110a,
529 }),
530 };
531 pub const sm_110f: CpuModel = .{
532 .name = "sm_110f",
533 .llvm_name = "sm_110f",
534 .features = featureSet(&[_]Feature{
535 .sm_110f,
536 }),
537 };
496538 pub const sm_120: CpuModel = .{
497539 .name = "sm_120",
498540 .llvm_name = "sm_120",
499541 .features = featureSet(&[_]Feature{
500 .ptx87,
501542 .sm_120,
502543 }),
503544 };
......@@ -505,7 +546,6 @@ pub const cpu = struct {
505546 .name = "sm_120a",
506547 .llvm_name = "sm_120a",
507548 .features = featureSet(&[_]Feature{
508 .ptx87,
509549 .sm_120a,
510550 }),
511551 };
......@@ -513,7 +553,6 @@ pub const cpu = struct {
513553 .name = "sm_120f",
514554 .llvm_name = "sm_120f",
515555 .features = featureSet(&[_]Feature{
516 .ptx88,
517556 .sm_120f,
518557 }),
519558 };
......@@ -521,7 +560,6 @@ pub const cpu = struct {
521560 .name = "sm_121",
522561 .llvm_name = "sm_121",
523562 .features = featureSet(&[_]Feature{
524 .ptx88,
525563 .sm_121,
526564 }),
527565 };
......@@ -529,7 +567,6 @@ pub const cpu = struct {
529567 .name = "sm_121a",
530568 .llvm_name = "sm_121a",
531569 .features = featureSet(&[_]Feature{
532 .ptx88,
533570 .sm_121a,
534571 }),
535572 };
......@@ -537,7 +574,6 @@ pub const cpu = struct {
537574 .name = "sm_121f",
538575 .llvm_name = "sm_121f",
539576 .features = featureSet(&[_]Feature{
540 .ptx88,
541577 .sm_121f,
542578 }),
543579 };
......@@ -545,7 +581,6 @@ pub const cpu = struct {
545581 .name = "sm_20",
546582 .llvm_name = "sm_20",
547583 .features = featureSet(&[_]Feature{
548 .ptx32,
549584 .sm_20,
550585 }),
551586 };
......@@ -553,7 +588,6 @@ pub const cpu = struct {
553588 .name = "sm_21",
554589 .llvm_name = "sm_21",
555590 .features = featureSet(&[_]Feature{
556 .ptx32,
557591 .sm_21,
558592 }),
559593 };
......@@ -568,7 +602,6 @@ pub const cpu = struct {
568602 .name = "sm_32",
569603 .llvm_name = "sm_32",
570604 .features = featureSet(&[_]Feature{
571 .ptx40,
572605 .sm_32,
573606 }),
574607 };
......@@ -576,7 +609,6 @@ pub const cpu = struct {
576609 .name = "sm_35",
577610 .llvm_name = "sm_35",
578611 .features = featureSet(&[_]Feature{
579 .ptx32,
580612 .sm_35,
581613 }),
582614 };
......@@ -584,7 +616,6 @@ pub const cpu = struct {
584616 .name = "sm_37",
585617 .llvm_name = "sm_37",
586618 .features = featureSet(&[_]Feature{
587 .ptx41,
588619 .sm_37,
589620 }),
590621 };
......@@ -592,7 +623,6 @@ pub const cpu = struct {
592623 .name = "sm_50",
593624 .llvm_name = "sm_50",
594625 .features = featureSet(&[_]Feature{
595 .ptx40,
596626 .sm_50,
597627 }),
598628 };
......@@ -600,7 +630,6 @@ pub const cpu = struct {
600630 .name = "sm_52",
601631 .llvm_name = "sm_52",
602632 .features = featureSet(&[_]Feature{
603 .ptx41,
604633 .sm_52,
605634 }),
606635 };
......@@ -608,7 +637,6 @@ pub const cpu = struct {
608637 .name = "sm_53",
609638 .llvm_name = "sm_53",
610639 .features = featureSet(&[_]Feature{
611 .ptx42,
612640 .sm_53,
613641 }),
614642 };
......@@ -616,7 +644,6 @@ pub const cpu = struct {
616644 .name = "sm_60",
617645 .llvm_name = "sm_60",
618646 .features = featureSet(&[_]Feature{
619 .ptx50,
620647 .sm_60,
621648 }),
622649 };
......@@ -624,7 +651,6 @@ pub const cpu = struct {
624651 .name = "sm_61",
625652 .llvm_name = "sm_61",
626653 .features = featureSet(&[_]Feature{
627 .ptx50,
628654 .sm_61,
629655 }),
630656 };
......@@ -632,7 +658,6 @@ pub const cpu = struct {
632658 .name = "sm_62",
633659 .llvm_name = "sm_62",
634660 .features = featureSet(&[_]Feature{
635 .ptx50,
636661 .sm_62,
637662 }),
638663 };
......@@ -640,7 +665,6 @@ pub const cpu = struct {
640665 .name = "sm_70",
641666 .llvm_name = "sm_70",
642667 .features = featureSet(&[_]Feature{
643 .ptx60,
644668 .sm_70,
645669 }),
646670 };
......@@ -648,7 +672,6 @@ pub const cpu = struct {
648672 .name = "sm_72",
649673 .llvm_name = "sm_72",
650674 .features = featureSet(&[_]Feature{
651 .ptx61,
652675 .sm_72,
653676 }),
654677 };
......@@ -656,7 +679,6 @@ pub const cpu = struct {
656679 .name = "sm_75",
657680 .llvm_name = "sm_75",
658681 .features = featureSet(&[_]Feature{
659 .ptx63,
660682 .sm_75,
661683 }),
662684 };
......@@ -664,7 +686,6 @@ pub const cpu = struct {
664686 .name = "sm_80",
665687 .llvm_name = "sm_80",
666688 .features = featureSet(&[_]Feature{
667 .ptx70,
668689 .sm_80,
669690 }),
670691 };
......@@ -672,7 +693,6 @@ pub const cpu = struct {
672693 .name = "sm_86",
673694 .llvm_name = "sm_86",
674695 .features = featureSet(&[_]Feature{
675 .ptx71,
676696 .sm_86,
677697 }),
678698 };
......@@ -680,15 +700,20 @@ pub const cpu = struct {
680700 .name = "sm_87",
681701 .llvm_name = "sm_87",
682702 .features = featureSet(&[_]Feature{
683 .ptx74,
684703 .sm_87,
685704 }),
686705 };
706 pub const sm_88: CpuModel = .{
707 .name = "sm_88",
708 .llvm_name = "sm_88",
709 .features = featureSet(&[_]Feature{
710 .sm_88,
711 }),
712 };
687713 pub const sm_89: CpuModel = .{
688714 .name = "sm_89",
689715 .llvm_name = "sm_89",
690716 .features = featureSet(&[_]Feature{
691 .ptx78,
692717 .sm_89,
693718 }),
694719 };
......@@ -696,7 +721,6 @@ pub const cpu = struct {
696721 .name = "sm_90",
697722 .llvm_name = "sm_90",
698723 .features = featureSet(&[_]Feature{
699 .ptx78,
700724 .sm_90,
701725 }),
702726 };
......@@ -704,7 +728,6 @@ pub const cpu = struct {
704728 .name = "sm_90a",
705729 .llvm_name = "sm_90a",
706730 .features = featureSet(&[_]Feature{
707 .ptx80,
708731 .sm_90a,
709732 }),
710733 };
lib/std/Target/powerpc.zig+27-19
......@@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model;
66
77pub const Feature = enum {
88 @"64bit",
9 @"64bit_support",
910 @"64bitregs",
1011 allow_unaligned_fp_access,
1112 altivec,
......@@ -97,7 +98,14 @@ pub const all_features = blk: {
9798 var result: [len]CpuFeature = undefined;
9899 result[@intFromEnum(Feature.@"64bit")] = .{
99100 .llvm_name = "64bit",
100 .description = "Enable 64-bit instructions",
101 .description = "Enable 64-bit mode",
102 .dependencies = featureSet(&[_]Feature{
103 .@"64bit_support",
104 }),
105 };
106 result[@intFromEnum(Feature.@"64bit_support")] = .{
107 .llvm_name = "64bit-support",
108 .description = "Supports 64-bit instructions",
101109 .dependencies = featureSet(&[_]Feature{}),
102110 };
103111 result[@intFromEnum(Feature.@"64bitregs")] = .{
......@@ -705,7 +713,7 @@ pub const cpu = struct {
705713 .name = "970",
706714 .llvm_name = "970",
707715 .features = featureSet(&[_]Feature{
708 .@"64bit",
716 .@"64bit_support",
709717 .altivec,
710718 .fres,
711719 .frsqrte,
......@@ -718,7 +726,7 @@ pub const cpu = struct {
718726 .name = "a2",
719727 .llvm_name = "a2",
720728 .features = featureSet(&[_]Feature{
721 .@"64bit",
729 .@"64bit_support",
722730 .booke,
723731 .cmpb,
724732 .fcpsgn,
......@@ -761,7 +769,7 @@ pub const cpu = struct {
761769 .name = "e5500",
762770 .llvm_name = "e5500",
763771 .features = featureSet(&[_]Feature{
764 .@"64bit",
772 .@"64bit_support",
765773 .booke,
766774 .isel,
767775 .mfocrf,
......@@ -772,7 +780,7 @@ pub const cpu = struct {
772780 .name = "future",
773781 .llvm_name = "future",
774782 .features = featureSet(&[_]Feature{
775 .@"64bit",
783 .@"64bit_support",
776784 .allow_unaligned_fp_access,
777785 .bpermd,
778786 .cmpb,
......@@ -846,7 +854,7 @@ pub const cpu = struct {
846854 .name = "g5",
847855 .llvm_name = "g5",
848856 .features = featureSet(&[_]Feature{
849 .@"64bit",
857 .@"64bit_support",
850858 .altivec,
851859 .fres,
852860 .frsqrte,
......@@ -873,7 +881,7 @@ pub const cpu = struct {
873881 .name = "ppc64",
874882 .llvm_name = "ppc64",
875883 .features = featureSet(&[_]Feature{
876 .@"64bit",
884 .@"64bit_support",
877885 .altivec,
878886 .fres,
879887 .frsqrte,
......@@ -886,7 +894,7 @@ pub const cpu = struct {
886894 .name = "ppc64le",
887895 .llvm_name = "ppc64le",
888896 .features = featureSet(&[_]Feature{
889 .@"64bit",
897 .@"64bit_support",
890898 .allow_unaligned_fp_access,
891899 .bpermd,
892900 .cmpb,
......@@ -926,7 +934,7 @@ pub const cpu = struct {
926934 .name = "pwr10",
927935 .llvm_name = "pwr10",
928936 .features = featureSet(&[_]Feature{
929 .@"64bit",
937 .@"64bit_support",
930938 .allow_unaligned_fp_access,
931939 .bpermd,
932940 .cmpb,
......@@ -973,7 +981,7 @@ pub const cpu = struct {
973981 .name = "pwr11",
974982 .llvm_name = "pwr11",
975983 .features = featureSet(&[_]Feature{
976 .@"64bit",
984 .@"64bit_support",
977985 .allow_unaligned_fp_access,
978986 .bpermd,
979987 .cmpb,
......@@ -1020,7 +1028,7 @@ pub const cpu = struct {
10201028 .name = "pwr3",
10211029 .llvm_name = "pwr3",
10221030 .features = featureSet(&[_]Feature{
1023 .@"64bit",
1031 .@"64bit_support",
10241032 .altivec,
10251033 .fres,
10261034 .frsqrte,
......@@ -1032,7 +1040,7 @@ pub const cpu = struct {
10321040 .name = "pwr4",
10331041 .llvm_name = "pwr4",
10341042 .features = featureSet(&[_]Feature{
1035 .@"64bit",
1043 .@"64bit_support",
10361044 .altivec,
10371045 .fres,
10381046 .frsqrte,
......@@ -1045,7 +1053,7 @@ pub const cpu = struct {
10451053 .name = "pwr5",
10461054 .llvm_name = "pwr5",
10471055 .features = featureSet(&[_]Feature{
1048 .@"64bit",
1056 .@"64bit_support",
10491057 .altivec,
10501058 .fre,
10511059 .fres,
......@@ -1060,7 +1068,7 @@ pub const cpu = struct {
10601068 .name = "pwr5x",
10611069 .llvm_name = "pwr5x",
10621070 .features = featureSet(&[_]Feature{
1063 .@"64bit",
1071 .@"64bit_support",
10641072 .altivec,
10651073 .fprnd,
10661074 .fre,
......@@ -1076,7 +1084,7 @@ pub const cpu = struct {
10761084 .name = "pwr6",
10771085 .llvm_name = "pwr6",
10781086 .features = featureSet(&[_]Feature{
1079 .@"64bit",
1087 .@"64bit_support",
10801088 .altivec,
10811089 .cmpb,
10821090 .fcpsgn,
......@@ -1096,7 +1104,7 @@ pub const cpu = struct {
10961104 .name = "pwr6x",
10971105 .llvm_name = "pwr6x",
10981106 .features = featureSet(&[_]Feature{
1099 .@"64bit",
1107 .@"64bit_support",
11001108 .altivec,
11011109 .cmpb,
11021110 .fcpsgn,
......@@ -1116,7 +1124,7 @@ pub const cpu = struct {
11161124 .name = "pwr7",
11171125 .llvm_name = "pwr7",
11181126 .features = featureSet(&[_]Feature{
1119 .@"64bit",
1127 .@"64bit_support",
11201128 .allow_unaligned_fp_access,
11211129 .bpermd,
11221130 .cmpb,
......@@ -1145,7 +1153,7 @@ pub const cpu = struct {
11451153 .name = "pwr8",
11461154 .llvm_name = "pwr8",
11471155 .features = featureSet(&[_]Feature{
1148 .@"64bit",
1156 .@"64bit_support",
11491157 .allow_unaligned_fp_access,
11501158 .bpermd,
11511159 .cmpb,
......@@ -1185,7 +1193,7 @@ pub const cpu = struct {
11851193 .name = "pwr9",
11861194 .llvm_name = "pwr9",
11871195 .features = featureSet(&[_]Feature{
1188 .@"64bit",
1196 .@"64bit_support",
11891197 .allow_unaligned_fp_access,
11901198 .bpermd,
11911199 .cmpb,
lib/std/Target/riscv.zig+415-177
......@@ -8,49 +8,40 @@ pub const Feature = enum {
88 @"32bit",
99 @"64bit",
1010 a,
11 add_load_fusion,
12 addi_load_fusion,
1113 andes45,
1214 auipc_addi_fusion,
15 auipc_load_fusion,
1316 b,
17 bfext_fusion,
1418 c,
1519 conditional_cmv_fusion,
1620 d,
1721 disable_latency_sched_heuristic,
22 disable_misched_load_clustering,
23 disable_misched_store_clustering,
24 disable_postmisched_load_clustering,
25 disable_postmisched_store_clustering,
1826 dlen_factor_2,
1927 e,
28 enable_vsetvli_sched_heuristic,
2029 exact_asm,
2130 experimental,
2231 experimental_p,
2332 experimental_rvm23u32,
24 experimental_smctr,
25 experimental_ssctr,
33 experimental_smpmpmt,
2634 experimental_svukte,
27 experimental_xqccmp,
28 experimental_xqcia,
29 experimental_xqciac,
30 experimental_xqcibi,
31 experimental_xqcibm,
32 experimental_xqcicli,
33 experimental_xqcicm,
34 experimental_xqcics,
35 experimental_xqcicsr,
36 experimental_xqciint,
37 experimental_xqciio,
38 experimental_xqcilb,
39 experimental_xqcili,
40 experimental_xqcilia,
41 experimental_xqcilo,
42 experimental_xqcilsm,
43 experimental_xqcisim,
44 experimental_xqcisls,
45 experimental_xqcisync,
4635 experimental_xrivosvisni,
4736 experimental_xrivosvizip,
4837 experimental_xsfmclic,
4938 experimental_xsfsclic,
50 experimental_zalasr,
39 experimental_zibi,
5140 experimental_zicfilp,
5241 experimental_zicfiss,
5342 experimental_zvbc32e,
43 experimental_zvfbfa,
44 experimental_zvfofp8min,
5445 experimental_zvkgs,
5546 experimental_zvqdotq,
5647 f,
......@@ -60,6 +51,7 @@ pub const Feature = enum {
6051 ld_add_fusion,
6152 log_vrgather,
6253 lui_addi_fusion,
54 lui_load_fusion,
6355 m,
6456 mips_p8700,
6557 no_default_unroll,
......@@ -73,6 +65,7 @@ pub const Feature = enum {
7365 optimized_nf7_segment_load_store,
7466 optimized_nf8_segment_load_store,
7567 optimized_zero_stride_load,
68 permissive_zalrsc,
7669 predictable_select_expensive,
7770 prefer_vsetvli_over_read_vlenb,
7871 prefer_w_inst,
......@@ -127,15 +120,21 @@ pub const Feature = enum {
127120 shgatpa,
128121 shifted_zextw_fusion,
129122 shlcofideleg,
130 short_forward_branch_opt,
123 short_forward_branch_ialu,
124 short_forward_branch_iload,
125 short_forward_branch_iminmax,
126 short_forward_branch_imul,
131127 shtvala,
132128 shvsatpa,
133129 shvstvala,
134130 shvstvecd,
131 shxadd_load_fusion,
132 single_element_vec_fp64,
135133 smaia,
136134 smcdeleg,
137135 smcntrpmf,
138136 smcsrind,
137 smctr,
139138 smdbltrp,
140139 smepmp,
141140 smmpm,
......@@ -148,6 +147,7 @@ pub const Feature = enum {
148147 sscofpmf,
149148 sscounterenw,
150149 sscsrind,
150 ssctr,
151151 ssdbltrp,
152152 ssnpm,
153153 sspm,
......@@ -179,6 +179,7 @@ pub const Feature = enum {
179179 xandesvbfhcvt,
180180 xandesvdot,
181181 xandesvpackfph,
182 xandesvsinth,
182183 xandesvsintload,
183184 xcvalu,
184185 xcvbi,
......@@ -189,7 +190,28 @@ pub const Feature = enum {
189190 xcvsimd,
190191 xmipscbop,
191192 xmipscmov,
193 xmipsexectl,
192194 xmipslsp,
195 xqccmp,
196 xqci,
197 xqcia,
198 xqciac,
199 xqcibi,
200 xqcibm,
201 xqcicli,
202 xqcicm,
203 xqcics,
204 xqcicsr,
205 xqciint,
206 xqciio,
207 xqcilb,
208 xqcili,
209 xqcilia,
210 xqcilo,
211 xqcilsm,
212 xqcisim,
213 xqcisls,
214 xqcisync,
193215 xsfcease,
194216 xsfmm128t,
195217 xsfmm16t,
......@@ -202,12 +224,18 @@ pub const Feature = enum {
202224 xsfmm64t,
203225 xsfmmbase,
204226 xsfvcp,
227 xsfvfbfexp16e,
228 xsfvfexp16e,
229 xsfvfexp32e,
230 xsfvfexpa,
231 xsfvfexpa64e,
205232 xsfvfnrclipxfqf,
206233 xsfvfwmaccqqq,
207234 xsfvqmaccdod,
208235 xsfvqmaccqoq,
209236 xsifivecdiscarddlone,
210237 xsifivecflushdlone,
238 xsmtvdot,
211239 xtheadba,
212240 xtheadbb,
213241 xtheadbs,
......@@ -226,6 +254,7 @@ pub const Feature = enum {
226254 zaamo,
227255 zabha,
228256 zacas,
257 zalasr,
229258 zalrsc,
230259 zama16b,
231260 zawrs,
......@@ -272,6 +301,7 @@ pub const Feature = enum {
272301 zihintpause,
273302 zihpm,
274303 zilsd,
304 zilsd_4byte_align,
275305 zimop,
276306 zk,
277307 zkn,
......@@ -352,6 +382,16 @@ pub const all_features = blk: {
352382 .zalrsc,
353383 }),
354384 };
385 result[@intFromEnum(Feature.add_load_fusion)] = .{
386 .llvm_name = "add-load-fusion",
387 .description = "Enable ADD(.UW) + load macrofusion",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@intFromEnum(Feature.addi_load_fusion)] = .{
391 .llvm_name = "addi-load-fusion",
392 .description = "Enable ADDI + load macrofusion",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
355395 result[@intFromEnum(Feature.andes45)] = .{
356396 .llvm_name = "andes45",
357397 .description = "Andes 45-Series processors",
......@@ -362,6 +402,11 @@ pub const all_features = blk: {
362402 .description = "Enable AUIPC+ADDI macrofusion",
363403 .dependencies = featureSet(&[_]Feature{}),
364404 };
405 result[@intFromEnum(Feature.auipc_load_fusion)] = .{
406 .llvm_name = "auipc-load-fusion",
407 .description = "Enable AUIPC + load macrofusion",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
365410 result[@intFromEnum(Feature.b)] = .{
366411 .llvm_name = "b",
367412 .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)",
......@@ -371,6 +416,11 @@ pub const all_features = blk: {
371416 .zbs,
372417 }),
373418 };
419 result[@intFromEnum(Feature.bfext_fusion)] = .{
420 .llvm_name = "bfext-fusion",
421 .description = "Enable SLLI+SRLI (bitfield extract) macrofusion",
422 .dependencies = featureSet(&[_]Feature{}),
423 };
374424 result[@intFromEnum(Feature.c)] = .{
375425 .llvm_name = "c",
376426 .description = "'C' (Compressed Instructions)",
......@@ -395,6 +445,26 @@ pub const all_features = blk: {
395445 .description = "Disable latency scheduling heuristic",
396446 .dependencies = featureSet(&[_]Feature{}),
397447 };
448 result[@intFromEnum(Feature.disable_misched_load_clustering)] = .{
449 .llvm_name = "disable-misched-load-clustering",
450 .description = "Disable load clustering in the machine scheduler",
451 .dependencies = featureSet(&[_]Feature{}),
452 };
453 result[@intFromEnum(Feature.disable_misched_store_clustering)] = .{
454 .llvm_name = "disable-misched-store-clustering",
455 .description = "Disable store clustering in the machine scheduler",
456 .dependencies = featureSet(&[_]Feature{}),
457 };
458 result[@intFromEnum(Feature.disable_postmisched_load_clustering)] = .{
459 .llvm_name = "disable-postmisched-load-clustering",
460 .description = "Disable PostRA load clustering in the machine scheduler",
461 .dependencies = featureSet(&[_]Feature{}),
462 };
463 result[@intFromEnum(Feature.disable_postmisched_store_clustering)] = .{
464 .llvm_name = "disable-postmisched-store-clustering",
465 .description = "Disable PostRA store clustering in the machine scheduler",
466 .dependencies = featureSet(&[_]Feature{}),
467 };
398468 result[@intFromEnum(Feature.dlen_factor_2)] = .{
399469 .llvm_name = "dlen-factor-2",
400470 .description = "Vector unit DLEN(data path width) is half of VLEN",
......@@ -405,6 +475,11 @@ pub const all_features = blk: {
405475 .description = "'E' (Embedded Instruction Set with 16 GPRs)",
406476 .dependencies = featureSet(&[_]Feature{}),
407477 };
478 result[@intFromEnum(Feature.enable_vsetvli_sched_heuristic)] = .{
479 .llvm_name = "enable-vsetvli-sched-heuristic",
480 .description = "Enable vsetvli-based scheduling heuristic",
481 .dependencies = featureSet(&[_]Feature{}),
482 };
408483 result[@intFromEnum(Feature.exact_asm)] = .{
409484 .llvm_name = "exact-asm",
410485 .description = "Enable Exact Assembly (Disables Compression and Relaxation)",
......@@ -437,144 +512,16 @@ pub const all_features = blk: {
437512 .zimop,
438513 }),
439514 };
440 result[@intFromEnum(Feature.experimental_smctr)] = .{
441 .llvm_name = "experimental-smctr",
442 .description = "'Smctr' (Control Transfer Records Machine Level)",
443 .dependencies = featureSet(&[_]Feature{
444 .sscsrind,
445 }),
446 };
447 result[@intFromEnum(Feature.experimental_ssctr)] = .{
448 .llvm_name = "experimental-ssctr",
449 .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
450 .dependencies = featureSet(&[_]Feature{
451 .sscsrind,
452 }),
515 result[@intFromEnum(Feature.experimental_smpmpmt)] = .{
516 .llvm_name = "experimental-smpmpmt",
517 .description = "'Smpmpmt' (PMP-based Memory Types Extension)",
518 .dependencies = featureSet(&[_]Feature{}),
453519 };
454520 result[@intFromEnum(Feature.experimental_svukte)] = .{
455521 .llvm_name = "experimental-svukte",
456522 .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",
457523 .dependencies = featureSet(&[_]Feature{}),
458524 };
459 result[@intFromEnum(Feature.experimental_xqccmp)] = .{
460 .llvm_name = "experimental-xqccmp",
461 .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
462 .dependencies = featureSet(&[_]Feature{
463 .zca,
464 }),
465 };
466 result[@intFromEnum(Feature.experimental_xqcia)] = .{
467 .llvm_name = "experimental-xqcia",
468 .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
469 .dependencies = featureSet(&[_]Feature{}),
470 };
471 result[@intFromEnum(Feature.experimental_xqciac)] = .{
472 .llvm_name = "experimental-xqciac",
473 .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
474 .dependencies = featureSet(&[_]Feature{
475 .zca,
476 }),
477 };
478 result[@intFromEnum(Feature.experimental_xqcibi)] = .{
479 .llvm_name = "experimental-xqcibi",
480 .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
481 .dependencies = featureSet(&[_]Feature{
482 .zca,
483 }),
484 };
485 result[@intFromEnum(Feature.experimental_xqcibm)] = .{
486 .llvm_name = "experimental-xqcibm",
487 .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
488 .dependencies = featureSet(&[_]Feature{
489 .zca,
490 }),
491 };
492 result[@intFromEnum(Feature.experimental_xqcicli)] = .{
493 .llvm_name = "experimental-xqcicli",
494 .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
495 .dependencies = featureSet(&[_]Feature{}),
496 };
497 result[@intFromEnum(Feature.experimental_xqcicm)] = .{
498 .llvm_name = "experimental-xqcicm",
499 .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
500 .dependencies = featureSet(&[_]Feature{
501 .zca,
502 }),
503 };
504 result[@intFromEnum(Feature.experimental_xqcics)] = .{
505 .llvm_name = "experimental-xqcics",
506 .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
507 .dependencies = featureSet(&[_]Feature{}),
508 };
509 result[@intFromEnum(Feature.experimental_xqcicsr)] = .{
510 .llvm_name = "experimental-xqcicsr",
511 .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
512 .dependencies = featureSet(&[_]Feature{}),
513 };
514 result[@intFromEnum(Feature.experimental_xqciint)] = .{
515 .llvm_name = "experimental-xqciint",
516 .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
517 .dependencies = featureSet(&[_]Feature{
518 .zca,
519 }),
520 };
521 result[@intFromEnum(Feature.experimental_xqciio)] = .{
522 .llvm_name = "experimental-xqciio",
523 .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
524 .dependencies = featureSet(&[_]Feature{}),
525 };
526 result[@intFromEnum(Feature.experimental_xqcilb)] = .{
527 .llvm_name = "experimental-xqcilb",
528 .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
529 .dependencies = featureSet(&[_]Feature{
530 .zca,
531 }),
532 };
533 result[@intFromEnum(Feature.experimental_xqcili)] = .{
534 .llvm_name = "experimental-xqcili",
535 .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
536 .dependencies = featureSet(&[_]Feature{
537 .zca,
538 }),
539 };
540 result[@intFromEnum(Feature.experimental_xqcilia)] = .{
541 .llvm_name = "experimental-xqcilia",
542 .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
543 .dependencies = featureSet(&[_]Feature{
544 .zca,
545 }),
546 };
547 result[@intFromEnum(Feature.experimental_xqcilo)] = .{
548 .llvm_name = "experimental-xqcilo",
549 .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
550 .dependencies = featureSet(&[_]Feature{
551 .zca,
552 }),
553 };
554 result[@intFromEnum(Feature.experimental_xqcilsm)] = .{
555 .llvm_name = "experimental-xqcilsm",
556 .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
557 .dependencies = featureSet(&[_]Feature{}),
558 };
559 result[@intFromEnum(Feature.experimental_xqcisim)] = .{
560 .llvm_name = "experimental-xqcisim",
561 .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
562 .dependencies = featureSet(&[_]Feature{
563 .zca,
564 }),
565 };
566 result[@intFromEnum(Feature.experimental_xqcisls)] = .{
567 .llvm_name = "experimental-xqcisls",
568 .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
569 .dependencies = featureSet(&[_]Feature{}),
570 };
571 result[@intFromEnum(Feature.experimental_xqcisync)] = .{
572 .llvm_name = "experimental-xqcisync",
573 .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
574 .dependencies = featureSet(&[_]Feature{
575 .zca,
576 }),
577 };
578525 result[@intFromEnum(Feature.experimental_xrivosvisni)] = .{
579526 .llvm_name = "experimental-xrivosvisni",
580527 .description = "'XRivosVisni' (Rivos Vector Integer Small New)",
......@@ -595,9 +542,9 @@ pub const all_features = blk: {
595542 .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",
596543 .dependencies = featureSet(&[_]Feature{}),
597544 };
598 result[@intFromEnum(Feature.experimental_zalasr)] = .{
599 .llvm_name = "experimental-zalasr",
600 .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
545 result[@intFromEnum(Feature.experimental_zibi)] = .{
546 .llvm_name = "experimental-zibi",
547 .description = "'Zibi' (Branch with Immediate)",
601548 .dependencies = featureSet(&[_]Feature{}),
602549 };
603550 result[@intFromEnum(Feature.experimental_zicfilp)] = .{
......@@ -622,6 +569,21 @@ pub const all_features = blk: {
622569 .zve32x,
623570 }),
624571 };
572 result[@intFromEnum(Feature.experimental_zvfbfa)] = .{
573 .llvm_name = "experimental-zvfbfa",
574 .description = "'Zvfbfa' (Additional BF16 vector compute support)",
575 .dependencies = featureSet(&[_]Feature{
576 .zfbfmin,
577 .zve32f,
578 }),
579 };
580 result[@intFromEnum(Feature.experimental_zvfofp8min)] = .{
581 .llvm_name = "experimental-zvfofp8min",
582 .description = "'Zvfofp8min' (Vector OFP8 Converts)",
583 .dependencies = featureSet(&[_]Feature{
584 .zve32f,
585 }),
586 };
625587 result[@intFromEnum(Feature.experimental_zvkgs)] = .{
626588 .llvm_name = "experimental-zvkgs",
627589 .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",
......@@ -673,6 +635,11 @@ pub const all_features = blk: {
673635 .description = "Enable LUI+ADDI macro fusion",
674636 .dependencies = featureSet(&[_]Feature{}),
675637 };
638 result[@intFromEnum(Feature.lui_load_fusion)] = .{
639 .llvm_name = "lui-load-fusion",
640 .description = "Enable LUI + load macrofusion",
641 .dependencies = featureSet(&[_]Feature{}),
642 };
676643 result[@intFromEnum(Feature.m)] = .{
677644 .llvm_name = "m",
678645 .description = "'M' (Integer Multiplication and Division)",
......@@ -740,6 +707,11 @@ pub const all_features = blk: {
740707 .description = "Optimized (perform fewer memory operations)zero-stride vector load",
741708 .dependencies = featureSet(&[_]Feature{}),
742709 };
710 result[@intFromEnum(Feature.permissive_zalrsc)] = .{
711 .llvm_name = "permissive-zalrsc",
712 .description = "Implementation permits non-base instructions between LR/SC pairs",
713 .dependencies = featureSet(&[_]Feature{}),
714 };
743715 result[@intFromEnum(Feature.predictable_select_expensive)] = .{
744716 .llvm_name = "predictable-select-expensive",
745717 .description = "Prefer likely predicted branches over selects",
......@@ -1262,11 +1234,32 @@ pub const all_features = blk: {
12621234 .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",
12631235 .dependencies = featureSet(&[_]Feature{}),
12641236 };
1265 result[@intFromEnum(Feature.short_forward_branch_opt)] = .{
1266 .llvm_name = "short-forward-branch-opt",
1267 .description = "Enable short forward branch optimization",
1237 result[@intFromEnum(Feature.short_forward_branch_ialu)] = .{
1238 .llvm_name = "short-forward-branch-ialu",
1239 .description = "Enable short forward branch optimization for RVI base instructions",
12681240 .dependencies = featureSet(&[_]Feature{}),
12691241 };
1242 result[@intFromEnum(Feature.short_forward_branch_iload)] = .{
1243 .llvm_name = "short-forward-branch-iload",
1244 .description = "Enable short forward branch optimization for load instructions",
1245 .dependencies = featureSet(&[_]Feature{
1246 .short_forward_branch_ialu,
1247 }),
1248 };
1249 result[@intFromEnum(Feature.short_forward_branch_iminmax)] = .{
1250 .llvm_name = "short-forward-branch-iminmax",
1251 .description = "Enable short forward branch optimization for MIN,MAX instructions in Zbb",
1252 .dependencies = featureSet(&[_]Feature{
1253 .short_forward_branch_ialu,
1254 }),
1255 };
1256 result[@intFromEnum(Feature.short_forward_branch_imul)] = .{
1257 .llvm_name = "short-forward-branch-imul",
1258 .description = "Enable short forward branch optimization for MUL instruction",
1259 .dependencies = featureSet(&[_]Feature{
1260 .short_forward_branch_ialu,
1261 }),
1262 };
12701263 result[@intFromEnum(Feature.shtvala)] = .{
12711264 .llvm_name = "shtvala",
12721265 .description = "'Shtvala' (htval provides all needed values)",
......@@ -1287,6 +1280,16 @@ pub const all_features = blk: {
12871280 .description = "'Shvstvecd' (vstvec supports Direct mode)",
12881281 .dependencies = featureSet(&[_]Feature{}),
12891282 };
1283 result[@intFromEnum(Feature.shxadd_load_fusion)] = .{
1284 .llvm_name = "shxadd-load-fusion",
1285 .description = "Enable SH(1|2|3)ADD(.UW) + load macrofusion",
1286 .dependencies = featureSet(&[_]Feature{}),
1287 };
1288 result[@intFromEnum(Feature.single_element_vec_fp64)] = .{
1289 .llvm_name = "single-element-vec-fp64",
1290 .description = "Certain vector FP64 operations produce a single result element per cycle",
1291 .dependencies = featureSet(&[_]Feature{}),
1292 };
12901293 result[@intFromEnum(Feature.smaia)] = .{
12911294 .llvm_name = "smaia",
12921295 .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",
......@@ -1307,6 +1310,13 @@ pub const all_features = blk: {
13071310 .description = "'Smcsrind' (Indirect CSR Access Machine Level)",
13081311 .dependencies = featureSet(&[_]Feature{}),
13091312 };
1313 result[@intFromEnum(Feature.smctr)] = .{
1314 .llvm_name = "smctr",
1315 .description = "'Smctr' (Control Transfer Records Machine Level)",
1316 .dependencies = featureSet(&[_]Feature{
1317 .sscsrind,
1318 }),
1319 };
13101320 result[@intFromEnum(Feature.smdbltrp)] = .{
13111321 .llvm_name = "smdbltrp",
13121322 .description = "'Smdbltrp' (Double Trap Machine Level)",
......@@ -1369,6 +1379,13 @@ pub const all_features = blk: {
13691379 .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)",
13701380 .dependencies = featureSet(&[_]Feature{}),
13711381 };
1382 result[@intFromEnum(Feature.ssctr)] = .{
1383 .llvm_name = "ssctr",
1384 .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
1385 .dependencies = featureSet(&[_]Feature{
1386 .sscsrind,
1387 }),
1388 };
13721389 result[@intFromEnum(Feature.ssdbltrp)] = .{
13731390 .llvm_name = "ssdbltrp",
13741391 .description = "'Ssdbltrp' (Double Trap Supervisor Level)",
......@@ -1537,6 +1554,13 @@ pub const all_features = blk: {
15371554 .f,
15381555 }),
15391556 };
1557 result[@intFromEnum(Feature.xandesvsinth)] = .{
1558 .llvm_name = "xandesvsinth",
1559 .description = "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)",
1560 .dependencies = featureSet(&[_]Feature{
1561 .zve32x,
1562 }),
1563 };
15401564 result[@intFromEnum(Feature.xandesvsintload)] = .{
15411565 .llvm_name = "xandesvsintload",
15421566 .description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",
......@@ -1589,11 +1613,159 @@ pub const all_features = blk: {
15891613 .description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",
15901614 .dependencies = featureSet(&[_]Feature{}),
15911615 };
1616 result[@intFromEnum(Feature.xmipsexectl)] = .{
1617 .llvm_name = "xmipsexectl",
1618 .description = "'XMIPSEXECTL' (MIPS execution control)",
1619 .dependencies = featureSet(&[_]Feature{}),
1620 };
15921621 result[@intFromEnum(Feature.xmipslsp)] = .{
15931622 .llvm_name = "xmipslsp",
15941623 .description = "'XMIPSLSP' (MIPS optimization for hardware load-store bonding)",
15951624 .dependencies = featureSet(&[_]Feature{}),
15961625 };
1626 result[@intFromEnum(Feature.xqccmp)] = .{
1627 .llvm_name = "xqccmp",
1628 .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
1629 .dependencies = featureSet(&[_]Feature{
1630 .zca,
1631 }),
1632 };
1633 result[@intFromEnum(Feature.xqci)] = .{
1634 .llvm_name = "xqci",
1635 .description = "'Xqci' (Qualcomm uC Extension)",
1636 .dependencies = featureSet(&[_]Feature{
1637 .xqcia,
1638 .xqciac,
1639 .xqcibi,
1640 .xqcibm,
1641 .xqcicli,
1642 .xqcicm,
1643 .xqcics,
1644 .xqcicsr,
1645 .xqciint,
1646 .xqciio,
1647 .xqcilb,
1648 .xqcili,
1649 .xqcilia,
1650 .xqcilo,
1651 .xqcilsm,
1652 .xqcisim,
1653 .xqcisls,
1654 .xqcisync,
1655 }),
1656 };
1657 result[@intFromEnum(Feature.xqcia)] = .{
1658 .llvm_name = "xqcia",
1659 .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
1660 .dependencies = featureSet(&[_]Feature{}),
1661 };
1662 result[@intFromEnum(Feature.xqciac)] = .{
1663 .llvm_name = "xqciac",
1664 .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
1665 .dependencies = featureSet(&[_]Feature{
1666 .zca,
1667 }),
1668 };
1669 result[@intFromEnum(Feature.xqcibi)] = .{
1670 .llvm_name = "xqcibi",
1671 .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
1672 .dependencies = featureSet(&[_]Feature{
1673 .zca,
1674 }),
1675 };
1676 result[@intFromEnum(Feature.xqcibm)] = .{
1677 .llvm_name = "xqcibm",
1678 .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
1679 .dependencies = featureSet(&[_]Feature{
1680 .zca,
1681 }),
1682 };
1683 result[@intFromEnum(Feature.xqcicli)] = .{
1684 .llvm_name = "xqcicli",
1685 .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
1686 .dependencies = featureSet(&[_]Feature{}),
1687 };
1688 result[@intFromEnum(Feature.xqcicm)] = .{
1689 .llvm_name = "xqcicm",
1690 .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
1691 .dependencies = featureSet(&[_]Feature{
1692 .zca,
1693 }),
1694 };
1695 result[@intFromEnum(Feature.xqcics)] = .{
1696 .llvm_name = "xqcics",
1697 .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
1698 .dependencies = featureSet(&[_]Feature{}),
1699 };
1700 result[@intFromEnum(Feature.xqcicsr)] = .{
1701 .llvm_name = "xqcicsr",
1702 .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
1703 .dependencies = featureSet(&[_]Feature{}),
1704 };
1705 result[@intFromEnum(Feature.xqciint)] = .{
1706 .llvm_name = "xqciint",
1707 .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
1708 .dependencies = featureSet(&[_]Feature{
1709 .zca,
1710 }),
1711 };
1712 result[@intFromEnum(Feature.xqciio)] = .{
1713 .llvm_name = "xqciio",
1714 .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
1715 .dependencies = featureSet(&[_]Feature{}),
1716 };
1717 result[@intFromEnum(Feature.xqcilb)] = .{
1718 .llvm_name = "xqcilb",
1719 .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
1720 .dependencies = featureSet(&[_]Feature{
1721 .zca,
1722 }),
1723 };
1724 result[@intFromEnum(Feature.xqcili)] = .{
1725 .llvm_name = "xqcili",
1726 .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
1727 .dependencies = featureSet(&[_]Feature{
1728 .zca,
1729 }),
1730 };
1731 result[@intFromEnum(Feature.xqcilia)] = .{
1732 .llvm_name = "xqcilia",
1733 .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
1734 .dependencies = featureSet(&[_]Feature{
1735 .zca,
1736 }),
1737 };
1738 result[@intFromEnum(Feature.xqcilo)] = .{
1739 .llvm_name = "xqcilo",
1740 .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
1741 .dependencies = featureSet(&[_]Feature{
1742 .zca,
1743 }),
1744 };
1745 result[@intFromEnum(Feature.xqcilsm)] = .{
1746 .llvm_name = "xqcilsm",
1747 .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
1748 .dependencies = featureSet(&[_]Feature{}),
1749 };
1750 result[@intFromEnum(Feature.xqcisim)] = .{
1751 .llvm_name = "xqcisim",
1752 .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
1753 .dependencies = featureSet(&[_]Feature{
1754 .zca,
1755 }),
1756 };
1757 result[@intFromEnum(Feature.xqcisls)] = .{
1758 .llvm_name = "xqcisls",
1759 .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
1760 .dependencies = featureSet(&[_]Feature{}),
1761 };
1762 result[@intFromEnum(Feature.xqcisync)] = .{
1763 .llvm_name = "xqcisync",
1764 .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
1765 .dependencies = featureSet(&[_]Feature{
1766 .zca,
1767 }),
1768 };
15971769 result[@intFromEnum(Feature.xsfcease)] = .{
15981770 .llvm_name = "xsfcease",
15991771 .description = "'XSfcease' (SiFive sf.cease Instruction)",
......@@ -1684,6 +1856,40 @@ pub const all_features = blk: {
16841856 .zve32x,
16851857 }),
16861858 };
1859 result[@intFromEnum(Feature.xsfvfbfexp16e)] = .{
1860 .llvm_name = "xsfvfbfexp16e",
1861 .description = "'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16)",
1862 .dependencies = featureSet(&[_]Feature{}),
1863 };
1864 result[@intFromEnum(Feature.xsfvfexp16e)] = .{
1865 .llvm_name = "xsfvfexp16e",
1866 .description = "'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision)",
1867 .dependencies = featureSet(&[_]Feature{
1868 .zvfh,
1869 }),
1870 };
1871 result[@intFromEnum(Feature.xsfvfexp32e)] = .{
1872 .llvm_name = "xsfvfexp32e",
1873 .description = "'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision)",
1874 .dependencies = featureSet(&[_]Feature{
1875 .zve32f,
1876 }),
1877 };
1878 result[@intFromEnum(Feature.xsfvfexpa)] = .{
1879 .llvm_name = "xsfvfexpa",
1880 .description = "'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)",
1881 .dependencies = featureSet(&[_]Feature{
1882 .zve32f,
1883 }),
1884 };
1885 result[@intFromEnum(Feature.xsfvfexpa64e)] = .{
1886 .llvm_name = "xsfvfexpa64e",
1887 .description = "'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision)",
1888 .dependencies = featureSet(&[_]Feature{
1889 .xsfvfexpa,
1890 .zve64d,
1891 }),
1892 };
16871893 result[@intFromEnum(Feature.xsfvfnrclipxfqf)] = .{
16881894 .llvm_name = "xsfvfnrclipxfqf",
16891895 .description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
......@@ -1696,6 +1902,7 @@ pub const all_features = blk: {
16961902 .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",
16971903 .dependencies = featureSet(&[_]Feature{
16981904 .zvfbfmin,
1905 .zvl128b,
16991906 }),
17001907 };
17011908 result[@intFromEnum(Feature.xsfvqmaccdod)] = .{
......@@ -1703,6 +1910,7 @@ pub const all_features = blk: {
17031910 .description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
17041911 .dependencies = featureSet(&[_]Feature{
17051912 .zve32x,
1913 .zvl128b,
17061914 }),
17071915 };
17081916 result[@intFromEnum(Feature.xsfvqmaccqoq)] = .{
......@@ -1710,6 +1918,7 @@ pub const all_features = blk: {
17101918 .description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
17111919 .dependencies = featureSet(&[_]Feature{
17121920 .zve32x,
1921 .zvl256b,
17131922 }),
17141923 };
17151924 result[@intFromEnum(Feature.xsifivecdiscarddlone)] = .{
......@@ -1722,6 +1931,13 @@ pub const all_features = blk: {
17221931 .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)",
17231932 .dependencies = featureSet(&[_]Feature{}),
17241933 };
1934 result[@intFromEnum(Feature.xsmtvdot)] = .{
1935 .llvm_name = "xsmtvdot",
1936 .description = "'XSMTVDot' (SpacemiT Vector Dot Product Extension)",
1937 .dependencies = featureSet(&[_]Feature{
1938 .zve32f,
1939 }),
1940 };
17251941 result[@intFromEnum(Feature.xtheadba)] = .{
17261942 .llvm_name = "xtheadba",
17271943 .description = "'XTHeadBa' (T-Head address calculation instructions)",
......@@ -1820,6 +2036,11 @@ pub const all_features = blk: {
18202036 .zaamo,
18212037 }),
18222038 };
2039 result[@intFromEnum(Feature.zalasr)] = .{
2040 .llvm_name = "zalasr",
2041 .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
2042 .dependencies = featureSet(&[_]Feature{}),
2043 };
18232044 result[@intFromEnum(Feature.zalrsc)] = .{
18242045 .llvm_name = "zalrsc",
18252046 .description = "'Zalrsc' (Load-Reserved/Store-Conditional)",
......@@ -2092,6 +2313,11 @@ pub const all_features = blk: {
20922313 .description = "'Zilsd' (Load/Store Pair Instructions)",
20932314 .dependencies = featureSet(&[_]Feature{}),
20942315 };
2316 result[@intFromEnum(Feature.zilsd_4byte_align)] = .{
2317 .llvm_name = "zilsd-4byte-align",
2318 .description = "Allow 4-byte alignment for Zilsd LD/SD instructions",
2319 .dependencies = featureSet(&[_]Feature{}),
2320 };
20952321 result[@intFromEnum(Feature.zimop)] = .{
20962322 .llvm_name = "zimop",
20972323 .description = "'Zimop' (May-Be-Operations)",
......@@ -2461,7 +2687,7 @@ pub const cpu = struct {
24612687 .features = featureSet(&[_]Feature{
24622688 .andes45,
24632689 .no_default_unroll,
2464 .short_forward_branch_opt,
2690 .short_forward_branch_ialu,
24652691 .use_postra_scheduler,
24662692 }),
24672693 };
......@@ -2491,7 +2717,7 @@ pub const cpu = struct {
24912717 .i,
24922718 .m,
24932719 .no_default_unroll,
2494 .short_forward_branch_opt,
2720 .short_forward_branch_ialu,
24952721 .use_postra_scheduler,
24962722 .xandesperf,
24972723 .zifencei,
......@@ -2523,7 +2749,7 @@ pub const cpu = struct {
25232749 .i,
25242750 .m,
25252751 .no_default_unroll,
2526 .short_forward_branch_opt,
2752 .short_forward_branch_ialu,
25272753 .use_postra_scheduler,
25282754 .xandesperf,
25292755 .zifencei,
......@@ -2540,7 +2766,7 @@ pub const cpu = struct {
25402766 .i,
25412767 .m,
25422768 .no_default_unroll,
2543 .short_forward_branch_opt,
2769 .short_forward_branch_ialu,
25442770 .use_postra_scheduler,
25452771 .v,
25462772 .xandesperf,
......@@ -2559,7 +2785,7 @@ pub const cpu = struct {
25592785 .i,
25602786 .m,
25612787 .no_default_unroll,
2562 .short_forward_branch_opt,
2788 .short_forward_branch_ialu,
25632789 .use_postra_scheduler,
25642790 .xandesperf,
25652791 .zifencei,
......@@ -2577,7 +2803,7 @@ pub const cpu = struct {
25772803 .i,
25782804 .m,
25792805 .no_default_unroll,
2580 .short_forward_branch_opt,
2806 .short_forward_branch_ialu,
25812807 .use_postra_scheduler,
25822808 .xandesperf,
25832809 .zifencei,
......@@ -2648,6 +2874,7 @@ pub const cpu = struct {
26482874 .mips_p8700,
26492875 .xmipscbop,
26502876 .xmipscmov,
2877 .xmipsexectl,
26512878 .xmipslsp,
26522879 .zba,
26532880 .zbb,
......@@ -2703,7 +2930,7 @@ pub const cpu = struct {
27032930 .llvm_name = "sifive-7-series",
27042931 .features = featureSet(&[_]Feature{
27052932 .no_default_unroll,
2706 .short_forward_branch_opt,
2933 .short_forward_branch_ialu,
27072934 .use_postra_scheduler,
27082935 }),
27092936 };
......@@ -2782,7 +3009,7 @@ pub const cpu = struct {
27823009 .i,
27833010 .m,
27843011 .no_default_unroll,
2785 .short_forward_branch_opt,
3012 .short_forward_branch_ialu,
27863013 .use_postra_scheduler,
27873014 .zifencei,
27883015 }),
......@@ -2815,7 +3042,6 @@ pub const cpu = struct {
28153042 .ziccif,
28163043 .zicclsm,
28173044 .ziccrse,
2818 .zicntr,
28193045 .zifencei,
28203046 .zihintntl,
28213047 .zihintpause,
......@@ -2855,7 +3081,6 @@ pub const cpu = struct {
28553081 .ziccif,
28563082 .zicclsm,
28573083 .ziccrse,
2858 .zicntr,
28593084 .zifencei,
28603085 .zihintntl,
28613086 .zihintpause,
......@@ -2918,7 +3143,6 @@ pub const cpu = struct {
29183143 .ziccif,
29193144 .zicclsm,
29203145 .ziccrse,
2921 .zicntr,
29223146 .zifencei,
29233147 .zihintntl,
29243148 .zihintpause,
......@@ -3035,7 +3259,7 @@ pub const cpu = struct {
30353259 .i,
30363260 .m,
30373261 .no_default_unroll,
3038 .short_forward_branch_opt,
3262 .short_forward_branch_ialu,
30393263 .use_postra_scheduler,
30403264 .zifencei,
30413265 .zihintpause,
......@@ -3065,7 +3289,7 @@ pub const cpu = struct {
30653289 .i,
30663290 .m,
30673291 .no_default_unroll,
3068 .short_forward_branch_opt,
3292 .short_forward_branch_ialu,
30693293 .use_postra_scheduler,
30703294 .zifencei,
30713295 }),
......@@ -3083,7 +3307,7 @@ pub const cpu = struct {
30833307 .no_default_unroll,
30843308 .optimized_nf2_segment_load_store,
30853309 .optimized_zero_stride_load,
3086 .short_forward_branch_opt,
3310 .short_forward_branch_ialu,
30873311 .use_postra_scheduler,
30883312 .v,
30893313 .vl_dependent_latency,
......@@ -3111,7 +3335,8 @@ pub const cpu = struct {
31113335 .no_default_unroll,
31123336 .optimized_nf2_segment_load_store,
31133337 .optimized_zero_stride_load,
3114 .short_forward_branch_opt,
3338 .short_forward_branch_ialu,
3339 .single_element_vec_fp64,
31153340 .use_postra_scheduler,
31163341 .v,
31173342 .vl_dependent_latency,
......@@ -3173,6 +3398,7 @@ pub const cpu = struct {
31733398 .unaligned_scalar_mem,
31743399 .v,
31753400 .vxrm_pipeline_flush,
3401 .xsmtvdot,
31763402 .za64rs,
31773403 .zbc,
31783404 .zbkc,
......@@ -3341,6 +3567,13 @@ pub const cpu = struct {
33413567 .log_vrgather,
33423568 .m,
33433569 .no_default_unroll,
3570 .optimized_nf2_segment_load_store,
3571 .optimized_nf3_segment_load_store,
3572 .optimized_nf4_segment_load_store,
3573 .optimized_nf5_segment_load_store,
3574 .optimized_nf6_segment_load_store,
3575 .optimized_nf7_segment_load_store,
3576 .optimized_nf8_segment_load_store,
33443577 .optimized_zero_stride_load,
33453578 .sha,
33463579 .smaia,
......@@ -3400,12 +3633,17 @@ pub const cpu = struct {
34003633 .features = featureSet(&[_]Feature{
34013634 .@"64bit",
34023635 .a,
3636 .add_load_fusion,
34033637 .auipc_addi_fusion,
3638 .auipc_load_fusion,
34043639 .c,
34053640 .d,
3641 .disable_misched_load_clustering,
3642 .disable_postmisched_load_clustering,
3643 .disable_postmisched_store_clustering,
34063644 .i,
3407 .ld_add_fusion,
34083645 .lui_addi_fusion,
3646 .lui_load_fusion,
34093647 .m,
34103648 .shifted_zextw_fusion,
34113649 .ventana_veyron,
lib/std/Target/sparc.zig+17
......@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
55const CpuModel = std.Target.Cpu.Model;
66
77pub const Feature = enum {
8 @"64bit",
89 crypto,
910 deprecated_v8,
1011 detectroundchange,
......@@ -23,6 +24,7 @@ pub const Feature = enum {
2324 leonpwrpsr,
2425 no_fmuls,
2526 no_fsmuld,
27 no_predictor,
2628 osa2011,
2729 popc,
2830 reserve_g1,
......@@ -73,6 +75,13 @@ pub const all_features = blk: {
7375 const len = @typeInfo(Feature).@"enum".fields.len;
7476 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
7577 var result: [len]CpuFeature = undefined;
78 result[@intFromEnum(Feature.@"64bit")] = .{
79 .llvm_name = "64bit",
80 .description = "Enable 64-bit mode",
81 .dependencies = featureSet(&[_]Feature{
82 .v9,
83 }),
84 };
7685 result[@intFromEnum(Feature.crypto)] = .{
7786 .llvm_name = "crypto",
7887 .description = "Enable cryptographic extensions",
......@@ -165,6 +174,11 @@ pub const all_features = blk: {
165174 .description = "Disable the fsmuld instruction.",
166175 .dependencies = featureSet(&[_]Feature{}),
167176 };
177 result[@intFromEnum(Feature.no_predictor)] = .{
178 .llvm_name = "no-predictor",
179 .description = "Processor has no branch predictor, branches stall execution",
180 .dependencies = featureSet(&[_]Feature{}),
181 };
168182 result[@intFromEnum(Feature.osa2011)] = .{
169183 .llvm_name = "osa2011",
170184 .description = "Enable Oracle SPARC Architecture 2011 extensions",
......@@ -586,6 +600,7 @@ pub const cpu = struct {
586600 .llvm_name = "niagara",
587601 .features = featureSet(&[_]Feature{
588602 .deprecated_v8,
603 .no_predictor,
589604 .ua2005,
590605 }),
591606 };
......@@ -594,6 +609,7 @@ pub const cpu = struct {
594609 .llvm_name = "niagara2",
595610 .features = featureSet(&[_]Feature{
596611 .deprecated_v8,
612 .no_predictor,
597613 .popc,
598614 .ua2005,
599615 }),
......@@ -603,6 +619,7 @@ pub const cpu = struct {
603619 .llvm_name = "niagara3",
604620 .features = featureSet(&[_]Feature{
605621 .deprecated_v8,
622 .no_predictor,
606623 .popc,
607624 .ua2005,
608625 .ua2007,
lib/std/Target/wasm.zig+7
......@@ -12,6 +12,7 @@ pub const Feature = enum {
1212 exception_handling,
1313 extended_const,
1414 fp16,
15 gc,
1516 multimemory,
1617 multivalue,
1718 mutable_globals,
......@@ -71,6 +72,11 @@ pub const all_features = blk: {
7172 .description = "Enable FP16 instructions",
7273 .dependencies = featureSet(&[_]Feature{}),
7374 };
75 result[@intFromEnum(Feature.gc)] = .{
76 .llvm_name = "gc",
77 .description = "Enable wasm gc",
78 .dependencies = featureSet(&[_]Feature{}),
79 };
7480 result[@intFromEnum(Feature.multimemory)] = .{
7581 .llvm_name = "multimemory",
7682 .description = "Enable multiple memories",
......@@ -148,6 +154,7 @@ pub const cpu = struct {
148154 .exception_handling,
149155 .extended_const,
150156 .fp16,
157 .gc,
151158 .multimemory,
152159 .multivalue,
153160 .mutable_globals,
lib/std/Target/x86.zig+200-31
......@@ -22,7 +22,6 @@ pub const Feature = enum {
2222 amx_movrs,
2323 amx_tf32,
2424 amx_tile,
25 amx_transpose,
2625 avx,
2726 avx10_1,
2827 avx10_2,
......@@ -67,7 +66,6 @@ pub const Feature = enum {
6766 egpr,
6867 enqcmd,
6968 ermsb,
70 evex512,
7169 f16c,
7270 false_deps_getmant,
7371 false_deps_lzcnt_tzcnt,
......@@ -136,6 +134,7 @@ pub const Feature = enum {
136134 ppx,
137135 prefer_128_bit,
138136 prefer_256_bit,
137 prefer_legacy_setcc,
139138 prefer_mask_registers,
140139 prefer_movmsk_over_vtest,
141140 prefer_no_gather,
......@@ -168,6 +167,7 @@ pub const Feature = enum {
168167 slow_lea,
169168 slow_pmaddwd,
170169 slow_pmulld,
170 slow_pmullq,
171171 slow_shld,
172172 slow_two_mem_ops,
173173 slow_unaligned_mem_16,
......@@ -199,6 +199,7 @@ pub const Feature = enum {
199199 waitpkg,
200200 wbnoinvd,
201201 widekl,
202 x32,
202203 x87,
203204 xop,
204205 xsave,
......@@ -324,13 +325,6 @@ pub const all_features = blk: {
324325 .description = "Support AMX-TILE instructions",
325326 .dependencies = featureSet(&[_]Feature{}),
326327 };
327 result[@intFromEnum(Feature.amx_transpose)] = .{
328 .llvm_name = "amx-transpose",
329 .description = "Support AMX amx-transpose instructions",
330 .dependencies = featureSet(&[_]Feature{
331 .amx_tile,
332 }),
333 };
334328 result[@intFromEnum(Feature.avx)] = .{
335329 .llvm_name = "avx",
336330 .description = "Enable AVX instructions",
......@@ -339,8 +333,8 @@ pub const all_features = blk: {
339333 }),
340334 };
341335 result[@intFromEnum(Feature.avx10_1)] = .{
342 .llvm_name = "avx10.1-512",
343 .description = "Support AVX10.1 up to 512-bit instruction",
336 .llvm_name = "avx10.1",
337 .description = "Support AVX10.1 instruction",
344338 .dependencies = featureSet(&[_]Feature{
345339 .avx512bf16,
346340 .avx512bitalg,
......@@ -356,8 +350,8 @@ pub const all_features = blk: {
356350 }),
357351 };
358352 result[@intFromEnum(Feature.avx10_2)] = .{
359 .llvm_name = "avx10.2-512",
360 .description = "Support AVX10.2 up to 512-bit instruction",
353 .llvm_name = "avx10.2",
354 .description = "Support AVX10.2 instruction",
361355 .dependencies = featureSet(&[_]Feature{
362356 .avx10_1,
363357 }),
......@@ -416,7 +410,6 @@ pub const all_features = blk: {
416410 .description = "Enable AVX-512 instructions",
417411 .dependencies = featureSet(&[_]Feature{
418412 .avx2,
419 .evex512,
420413 .f16c,
421414 .fma,
422415 }),
......@@ -616,11 +609,6 @@ pub const all_features = blk: {
616609 .description = "REP MOVS/STOS are fast",
617610 .dependencies = featureSet(&[_]Feature{}),
618611 };
619 result[@intFromEnum(Feature.evex512)] = .{
620 .llvm_name = "evex512",
621 .description = "Support ZMM and 64-bit mask instructions",
622 .dependencies = featureSet(&[_]Feature{}),
623 };
624612 result[@intFromEnum(Feature.f16c)] = .{
625613 .llvm_name = "f16c",
626614 .description = "Support 16-bit floating point conversion instructions",
......@@ -974,6 +962,11 @@ pub const all_features = blk: {
974962 .description = "Prefer 256-bit AVX instructions",
975963 .dependencies = featureSet(&[_]Feature{}),
976964 };
965 result[@intFromEnum(Feature.prefer_legacy_setcc)] = .{
966 .llvm_name = "prefer-legacy-setcc",
967 .description = "Prefer to emit legacy SetCC.",
968 .dependencies = featureSet(&[_]Feature{}),
969 };
977970 result[@intFromEnum(Feature.prefer_mask_registers)] = .{
978971 .llvm_name = "prefer-mask-registers",
979972 .description = "Prefer AVX512 mask registers over PTEST/MOVMSK",
......@@ -1145,6 +1138,11 @@ pub const all_features = blk: {
11451138 .description = "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)",
11461139 .dependencies = featureSet(&[_]Feature{}),
11471140 };
1141 result[@intFromEnum(Feature.slow_pmullq)] = .{
1142 .llvm_name = "slow-pmullq",
1143 .description = "PMULLQ instruction is slow",
1144 .dependencies = featureSet(&[_]Feature{}),
1145 };
11481146 result[@intFromEnum(Feature.slow_shld)] = .{
11491147 .llvm_name = "slow-shld",
11501148 .description = "SHLD instruction is slow",
......@@ -1325,6 +1323,11 @@ pub const all_features = blk: {
13251323 .kl,
13261324 }),
13271325 };
1326 result[@intFromEnum(Feature.x32)] = .{
1327 .llvm_name = "x32",
1328 .description = "64-bit with ILP32 programming model (e.g. x32 ABI)",
1329 .dependencies = featureSet(&[_]Feature{}),
1330 };
13281331 result[@intFromEnum(Feature.x87)] = .{
13291332 .llvm_name = "x87",
13301333 .description = "Enable X87 float instructions",
......@@ -1393,7 +1396,6 @@ pub const cpu = struct {
13931396 .cx16,
13941397 .f16c,
13951398 .false_deps_perm,
1396 .false_deps_popcnt,
13971399 .fast_15bytenop,
13981400 .fast_gather,
13991401 .fast_scalar_fsqrt,
......@@ -1432,6 +1434,7 @@ pub const cpu = struct {
14321434 .sha,
14331435 .shstk,
14341436 .slow_3ops_lea,
1437 .slow_pmullq,
14351438 .smap,
14361439 .smep,
14371440 .tuning_fast_imm_vector_shift,
......@@ -1490,7 +1493,6 @@ pub const cpu = struct {
14901493 .enqcmd,
14911494 .f16c,
14921495 .false_deps_perm,
1493 .false_deps_popcnt,
14941496 .fast_15bytenop,
14951497 .fast_gather,
14961498 .fast_scalar_fsqrt,
......@@ -1529,6 +1531,7 @@ pub const cpu = struct {
15291531 .sha,
15301532 .shstk,
15311533 .slow_3ops_lea,
1534 .slow_pmullq,
15321535 .smap,
15331536 .smep,
15341537 .tuning_fast_imm_vector_shift,
......@@ -1566,7 +1569,6 @@ pub const cpu = struct {
15661569 .enqcmd,
15671570 .f16c,
15681571 .false_deps_perm,
1569 .false_deps_popcnt,
15701572 .fast_15bytenop,
15711573 .fast_gather,
15721574 .fast_scalar_fsqrt,
......@@ -1606,6 +1608,7 @@ pub const cpu = struct {
16061608 .sha512,
16071609 .shstk,
16081610 .slow_3ops_lea,
1611 .slow_pmullq,
16091612 .sm3,
16101613 .sm4,
16111614 .smap,
......@@ -2204,6 +2207,7 @@ pub const cpu = struct {
22042207 .sahf,
22052208 .sha,
22062209 .slow_3ops_lea,
2210 .slow_pmullq,
22072211 .smap,
22082212 .smep,
22092213 .tuning_fast_imm_vector_shift,
......@@ -2297,7 +2301,6 @@ pub const cpu = struct {
22972301 .enqcmd,
22982302 .f16c,
22992303 .false_deps_perm,
2300 .false_deps_popcnt,
23012304 .fast_15bytenop,
23022305 .fast_gather,
23032306 .fast_scalar_fsqrt,
......@@ -2338,6 +2341,7 @@ pub const cpu = struct {
23382341 .sha512,
23392342 .shstk,
23402343 .slow_3ops_lea,
2344 .slow_pmullq,
23412345 .sm3,
23422346 .sm4,
23432347 .tuning_fast_imm_vector_shift,
......@@ -2464,7 +2468,6 @@ pub const cpu = struct {
24642468 .amx_int8,
24652469 .amx_movrs,
24662470 .amx_tf32,
2467 .amx_transpose,
24682471 .avx10_2,
24692472 .avxifma,
24702473 .avxneconvert,
......@@ -2475,7 +2478,6 @@ pub const cpu = struct {
24752478 .bmi2,
24762479 .branch_hint,
24772480 .ccmp,
2478 .cf,
24792481 .cldemote,
24802482 .clflushopt,
24812483 .clwb,
......@@ -2533,12 +2535,12 @@ pub const cpu = struct {
25332535 .sha,
25342536 .sha512,
25352537 .shstk,
2538 .slow_pmullq,
25362539 .sm3,
25372540 .sm4,
25382541 .tsxldtrk,
25392542 .tuning_fast_imm_vector_shift,
25402543 .uintr,
2541 .usermsr,
25422544 .vaes,
25432545 .vpclmulqdq,
25442546 .vzeroupper,
......@@ -2622,6 +2624,7 @@ pub const cpu = struct {
26222624 .serialize,
26232625 .sha,
26242626 .shstk,
2627 .slow_pmullq,
26252628 .smap,
26262629 .smep,
26272630 .tsxldtrk,
......@@ -2935,6 +2938,7 @@ pub const cpu = struct {
29352938 .serialize,
29362939 .sha,
29372940 .shstk,
2941 .slow_pmullq,
29382942 .tsxldtrk,
29392943 .tuning_fast_imm_vector_shift,
29402944 .uintr,
......@@ -3024,6 +3028,7 @@ pub const cpu = struct {
30243028 .serialize,
30253029 .sha,
30263030 .shstk,
3031 .slow_pmullq,
30273032 .tsxldtrk,
30283033 .tuning_fast_imm_vector_shift,
30293034 .uintr,
......@@ -3181,6 +3186,7 @@ pub const cpu = struct {
31813186 .rdseed,
31823187 .sahf,
31833188 .sha,
3189 .slow_pmullq,
31843190 .tuning_fast_imm_vector_shift,
31853191 .vaes,
31863192 .vpclmulqdq,
......@@ -3245,6 +3251,7 @@ pub const cpu = struct {
32453251 .rdseed,
32463252 .sahf,
32473253 .sha,
3254 .slow_pmullq,
32483255 .tuning_fast_imm_vector_shift,
32493256 .vaes,
32503257 .vpclmulqdq,
......@@ -3475,7 +3482,6 @@ pub const cpu = struct {
34753482 .enqcmd,
34763483 .f16c,
34773484 .false_deps_perm,
3478 .false_deps_popcnt,
34793485 .fast_15bytenop,
34803486 .fast_gather,
34813487 .fast_scalar_fsqrt,
......@@ -3515,6 +3521,7 @@ pub const cpu = struct {
35153521 .sha512,
35163522 .shstk,
35173523 .slow_3ops_lea,
3524 .slow_pmullq,
35183525 .sm3,
35193526 .sm4,
35203527 .tuning_fast_imm_vector_shift,
......@@ -3546,7 +3553,6 @@ pub const cpu = struct {
35463553 .cx16,
35473554 .f16c,
35483555 .false_deps_perm,
3549 .false_deps_popcnt,
35503556 .fast_15bytenop,
35513557 .fast_gather,
35523558 .fast_scalar_fsqrt,
......@@ -3585,6 +3591,7 @@ pub const cpu = struct {
35853591 .sha,
35863592 .shstk,
35873593 .slow_3ops_lea,
3594 .slow_pmullq,
35883595 .smap,
35893596 .smep,
35903597 .tuning_fast_imm_vector_shift,
......@@ -3635,6 +3642,90 @@ pub const cpu = struct {
36353642 .x87,
36363643 }),
36373644 };
3645 pub const novalake: CpuModel = .{
3646 .name = "novalake",
3647 .llvm_name = "novalake",
3648 .features = featureSet(&[_]Feature{
3649 .@"64bit",
3650 .adx,
3651 .allow_light_256_bit,
3652 .avx10_2,
3653 .avxifma,
3654 .avxneconvert,
3655 .avxvnni,
3656 .avxvnniint16,
3657 .avxvnniint8,
3658 .bmi,
3659 .bmi2,
3660 .ccmp,
3661 .clflushopt,
3662 .clwb,
3663 .cmov,
3664 .cmpccxadd,
3665 .cx16,
3666 .egpr,
3667 .enqcmd,
3668 .false_deps_perm,
3669 .fast_15bytenop,
3670 .fast_gather,
3671 .fast_scalar_fsqrt,
3672 .fast_shld_rotate,
3673 .fast_variable_crosslane_shuffle,
3674 .fast_variable_perlane_shuffle,
3675 .fast_vector_fsqrt,
3676 .fsgsbase,
3677 .fxsr,
3678 .gfni,
3679 .hreset,
3680 .idivq_to_divl,
3681 .invpcid,
3682 .lzcnt,
3683 .macrofusion,
3684 .mmx,
3685 .movbe,
3686 .movdir64b,
3687 .movdiri,
3688 .movrs,
3689 .ndd,
3690 .nf,
3691 .no_bypass_delay_blend,
3692 .no_bypass_delay_mov,
3693 .no_bypass_delay_shuffle,
3694 .nopl,
3695 .pconfig,
3696 .pku,
3697 .popcnt,
3698 .ppx,
3699 .prefer_movmsk_over_vtest,
3700 .prefetchi,
3701 .prfchw,
3702 .ptwrite,
3703 .push2pop2,
3704 .rdpid,
3705 .rdrnd,
3706 .rdseed,
3707 .sahf,
3708 .serialize,
3709 .sha,
3710 .sha512,
3711 .shstk,
3712 .slow_3ops_lea,
3713 .slow_pmullq,
3714 .sm3,
3715 .sm4,
3716 .tuning_fast_imm_vector_shift,
3717 .uintr,
3718 .vaes,
3719 .vpclmulqdq,
3720 .vzeroupper,
3721 .waitpkg,
3722 .x87,
3723 .xsavec,
3724 .xsaveopt,
3725 .xsaves,
3726 .zu,
3727 }),
3728 };
36383729 pub const opteron: CpuModel = .{
36393730 .name = "opteron",
36403731 .llvm_name = "opteron",
......@@ -3697,7 +3788,6 @@ pub const cpu = struct {
36973788 .enqcmd,
36983789 .f16c,
36993790 .false_deps_perm,
3700 .false_deps_popcnt,
37013791 .fast_15bytenop,
37023792 .fast_gather,
37033793 .fast_scalar_fsqrt,
......@@ -3726,7 +3816,6 @@ pub const cpu = struct {
37263816 .pku,
37273817 .popcnt,
37283818 .prefer_movmsk_over_vtest,
3729 .prefetchi,
37303819 .prfchw,
37313820 .ptwrite,
37323821 .rdpid,
......@@ -3738,6 +3827,7 @@ pub const cpu = struct {
37383827 .sha512,
37393828 .shstk,
37403829 .slow_3ops_lea,
3830 .slow_pmullq,
37413831 .sm3,
37423832 .sm4,
37433833 .tuning_fast_imm_vector_shift,
......@@ -3908,7 +3998,6 @@ pub const cpu = struct {
39083998 .cx16,
39093999 .f16c,
39104000 .false_deps_perm,
3911 .false_deps_popcnt,
39124001 .fast_15bytenop,
39134002 .fast_gather,
39144003 .fast_scalar_fsqrt,
......@@ -3947,6 +4036,7 @@ pub const cpu = struct {
39474036 .sha,
39484037 .shstk,
39494038 .slow_3ops_lea,
4039 .slow_pmullq,
39504040 .smap,
39514041 .smep,
39524042 .tuning_fast_imm_vector_shift,
......@@ -4013,6 +4103,7 @@ pub const cpu = struct {
40134103 .rdseed,
40144104 .sahf,
40154105 .sha,
4106 .slow_pmullq,
40164107 .smap,
40174108 .smep,
40184109 .tuning_fast_imm_vector_shift,
......@@ -4124,6 +4215,7 @@ pub const cpu = struct {
41244215 .serialize,
41254216 .sha,
41264217 .shstk,
4218 .slow_pmullq,
41274219 .smap,
41284220 .smep,
41294221 .tsxldtrk,
......@@ -4494,6 +4586,7 @@ pub const cpu = struct {
44944586 .sahf,
44954587 .sha,
44964588 .shstk,
4589 .slow_pmullq,
44974590 .smap,
44984591 .smep,
44994592 .tuning_fast_imm_vector_shift,
......@@ -4567,6 +4660,82 @@ pub const cpu = struct {
45674660 .x87,
45684661 }),
45694662 };
4663 pub const wildcatlake: CpuModel = .{
4664 .name = "wildcatlake",
4665 .llvm_name = "wildcatlake",
4666 .features = featureSet(&[_]Feature{
4667 .@"64bit",
4668 .adx,
4669 .allow_light_256_bit,
4670 .avxifma,
4671 .avxneconvert,
4672 .avxvnni,
4673 .avxvnniint16,
4674 .avxvnniint8,
4675 .bmi,
4676 .bmi2,
4677 .clflushopt,
4678 .clwb,
4679 .cmov,
4680 .cmpccxadd,
4681 .cx16,
4682 .enqcmd,
4683 .f16c,
4684 .false_deps_perm,
4685 .fast_15bytenop,
4686 .fast_gather,
4687 .fast_scalar_fsqrt,
4688 .fast_shld_rotate,
4689 .fast_variable_crosslane_shuffle,
4690 .fast_variable_perlane_shuffle,
4691 .fast_vector_fsqrt,
4692 .fma,
4693 .fsgsbase,
4694 .fxsr,
4695 .gfni,
4696 .hreset,
4697 .idivq_to_divl,
4698 .invpcid,
4699 .lzcnt,
4700 .macrofusion,
4701 .mmx,
4702 .movbe,
4703 .movdir64b,
4704 .movdiri,
4705 .no_bypass_delay_blend,
4706 .no_bypass_delay_mov,
4707 .no_bypass_delay_shuffle,
4708 .nopl,
4709 .pconfig,
4710 .pku,
4711 .popcnt,
4712 .prefer_movmsk_over_vtest,
4713 .prfchw,
4714 .ptwrite,
4715 .rdpid,
4716 .rdrnd,
4717 .rdseed,
4718 .sahf,
4719 .serialize,
4720 .sha,
4721 .sha512,
4722 .shstk,
4723 .slow_3ops_lea,
4724 .slow_pmullq,
4725 .sm3,
4726 .sm4,
4727 .tuning_fast_imm_vector_shift,
4728 .uintr,
4729 .vaes,
4730 .vpclmulqdq,
4731 .vzeroupper,
4732 .waitpkg,
4733 .x87,
4734 .xsavec,
4735 .xsaveopt,
4736 .xsaves,
4737 }),
4738 };
45704739 pub const winchip2: CpuModel = .{
45714740 .name = "winchip2",
45724741 .llvm_name = "winchip2",
lib/std/Target/xtensa.zig+65
......@@ -15,6 +15,7 @@ pub const Feature = enum {
1515 div32,
1616 exception,
1717 extendedl32r,
18 forced_atomics,
1819 fp,
1920 highpriinterrupts,
2021 highpriinterrupts_level3,
......@@ -34,6 +35,7 @@ pub const Feature = enum {
3435 prid,
3536 regprotect,
3637 rvector,
38 s32c1i,
3739 sext,
3840 threadptr,
3941 timers1,
......@@ -101,6 +103,11 @@ pub const all_features = blk: {
101103 .description = "Enable Xtensa Extended L32R option",
102104 .dependencies = featureSet(&[_]Feature{}),
103105 };
106 result[@intFromEnum(Feature.forced_atomics)] = .{
107 .llvm_name = "forced-atomics",
108 .description = "Assume that lock-free native-width atomics are available",
109 .dependencies = featureSet(&[_]Feature{}),
110 };
104111 result[@intFromEnum(Feature.fp)] = .{
105112 .llvm_name = "fp",
106113 .description = "Enable Xtensa Single FP instructions",
......@@ -206,6 +213,11 @@ pub const all_features = blk: {
206213 .description = "Enable Xtensa Relocatable Vector option",
207214 .dependencies = featureSet(&[_]Feature{}),
208215 };
216 result[@intFromEnum(Feature.s32c1i)] = .{
217 .llvm_name = "s32c1i",
218 .description = "Enable Xtensa S32C1I option",
219 .dependencies = featureSet(&[_]Feature{}),
220 };
209221 result[@intFromEnum(Feature.sext)] = .{
210222 .llvm_name = "sext",
211223 .description = "Enable Xtensa Sign Extend option",
......@@ -245,6 +257,59 @@ pub const all_features = blk: {
245257};
246258
247259pub const cpu = struct {
260 pub const esp32: CpuModel = .{
261 .name = "esp32",
262 .llvm_name = "esp32",
263 .features = featureSet(&[_]Feature{
264 .bool,
265 .clamps,
266 .coprocessor,
267 .dcache,
268 .debug,
269 .density,
270 .dfpaccel,
271 .div32,
272 .exception,
273 .fp,
274 .highpriinterrupts_level7,
275 .interrupt,
276 .loop,
277 .mac16,
278 .minmax,
279 .miscsr,
280 .mul16,
281 .mul32,
282 .mul32high,
283 .nsa,
284 .prid,
285 .regprotect,
286 .rvector,
287 .s32c1i,
288 .sext,
289 .threadptr,
290 .timers3,
291 .windowed,
292 }),
293 };
294 pub const esp8266: CpuModel = .{
295 .name = "esp8266",
296 .llvm_name = "esp8266",
297 .features = featureSet(&[_]Feature{
298 .debug,
299 .density,
300 .exception,
301 .extendedl32r,
302 .highpriinterrupts_level3,
303 .interrupt,
304 .mul16,
305 .mul32,
306 .nsa,
307 .prid,
308 .regprotect,
309 .rvector,
310 .timers1,
311 }),
312 };
248313 pub const generic: CpuModel = .{
249314 .name = "generic",
250315 .llvm_name = "generic",
lib/std/zig/system/x86.zig-2
......@@ -484,7 +484,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
484484 setFeature(cpu, .rtm, bit(leaf.ebx, 11));
485485 // AVX512 is only supported if the OS supports the context save for it.
486486 setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
487 setFeature(cpu, .evex512, bit(leaf.ebx, 16) and has_avx512_save);
488487 setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
489488 setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
490489 setFeature(cpu, .adx, bit(leaf.ebx, 19));
......@@ -605,7 +604,6 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
605604 .invpcid,
606605 .rtm,
607606 .avx512f,
608 .evex512,
609607 .avx512dq,
610608 .rdseed,
611609 .adx,
src/codegen/llvm.zig+1
......@@ -162,6 +162,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
162162 .{ .v9_4a, "v9.4a" },
163163 .{ .v9_5a, "v9.5a" },
164164 .{ .v9_6a, "v9.6a" },
165 .{ .v9_7a, "v9.7a" },
165166 }),
166167 .powerpc => subArchName(target, .powerpc, .{
167168 .{ .spe, "spe" },
src/codegen/llvm/FuncGen.zig+4-4
......@@ -6639,11 +6639,11 @@ const ParamTypeIterator = struct {
66396639 } else if (isByRef(ty, zcu)) {
66406640 return .byref;
66416641 } else if (target.cpu.arch.isX86() and
6642 !target.cpu.has(.x86, .evex512) and
6642 !target.cpu.has(.x86, .avx512f) and
66436643 ty.totalVectorBits(zcu) >= 512)
66446644 {
66456645 // As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
6646 // "512-bit vector arguments require 'evex512' for AVX512"
6646 // "512-bit vector arguments require 'avx512f' for AVX512"
66476647 return .byref;
66486648 } else {
66496649 return .byval;
......@@ -6899,11 +6899,11 @@ fn returnTypeByRef(zcu: *Zcu, target: *const std.Target, ty: Type) bool {
68996899 if (isByRef(ty, zcu)) {
69006900 return true;
69016901 } else if (target.cpu.arch.isX86() and
6902 !target.cpu.has(.x86, .evex512) and
6902 !target.cpu.has(.x86, .avx512f) and
69036903 ty.totalVectorBits(zcu) >= 512)
69046904 {
69056905 // As of LLVM 18, passing a vector byval with fastcc that is 512 bits or more returns
6906 // "512-bit vector arguments require 'evex512' for AVX512"
6906 // "512-bit vector arguments require 'avx512f' for AVX512"
69076907 return true;
69086908 } else {
69096909 return false;
src/link/Wasm.zig+3
......@@ -2829,6 +2829,7 @@ pub const Feature = packed struct(u8) {
28292829 @"exception-handling",
28302830 @"extended-const",
28312831 fp16,
2832 gc,
28322833 memory64,
28332834 multimemory,
28342835 multivalue,
......@@ -2852,6 +2853,7 @@ pub const Feature = packed struct(u8) {
28522853 .exception_handling => .@"exception-handling",
28532854 .extended_const => .@"extended-const",
28542855 .fp16 => .fp16,
2856 .gc => .gc,
28552857 .multimemory => .multimemory,
28562858 .multivalue => .multivalue,
28572859 .mutable_globals => .@"mutable-globals",
......@@ -2875,6 +2877,7 @@ pub const Feature = packed struct(u8) {
28752877 .@"exception-handling" => .exception_handling,
28762878 .@"extended-const" => .extended_const,
28772879 .fp16 => .fp16,
2880 .gc => .gc,
28782881 .memory64 => null, // Linker-only feature.
28792882 .multimemory => .multimemory,
28802883 .multivalue => .multivalue,
src/target.zig+2
......@@ -388,6 +388,8 @@ pub fn hasDebugInfo(target: *const std.Target) bool {
388388 .ptx85,
389389 .ptx86,
390390 .ptx87,
391 .ptx88,
392 .ptx90,
391393 }),
392394 .bpfel, .bpfeb => false,
393395 else => true,
tools/update_cpu_features.zig+37-13
......@@ -203,6 +203,10 @@ const targets = [_]ArchTarget{
203203 .llvm_name = "ampere1a",
204204 .flatten = true,
205205 },
206 .{
207 .llvm_name = "ampere1c",
208 .flatten = true,
209 },
206210 .{
207211 .llvm_name = "apple-a7",
208212 .flatten = true,
......@@ -247,6 +251,26 @@ const targets = [_]ArchTarget{
247251 .llvm_name = "apple-m4",
248252 .flatten = true,
249253 },
254 .{
255 .llvm_name = "apple-m5",
256 .flatten = true,
257 },
258 .{
259 .llvm_name = "c1-nano",
260 .flatten = true,
261 },
262 .{
263 .llvm_name = "c1-premium",
264 .flatten = true,
265 },
266 .{
267 .llvm_name = "c1-pro",
268 .flatten = true,
269 },
270 .{
271 .llvm_name = "c1-ultra",
272 .flatten = true,
273 },
250274 .{
251275 .llvm_name = "carmel",
252276 .flatten = true,
......@@ -862,6 +886,10 @@ const targets = [_]ArchTarget{
862886 .llvm_name = "armv9.6-a",
863887 .zig_name = "v9_6a",
864888 },
889 .{
890 .llvm_name = "armv9.7-a",
891 .zig_name = "v9_7a",
892 },
865893 .{
866894 .llvm_name = "armv9-a",
867895 .zig_name = "v9a",
......@@ -982,6 +1010,10 @@ const targets = [_]ArchTarget{
9821010 .llvm_name = "v9.6a",
9831011 .zig_name = "has_v9_6a",
9841012 },
1013 .{
1014 .llvm_name = "v9.7a",
1015 .zig_name = "has_v9_7a",
1016 },
9851017 },
9861018 .extra_cpus = &.{
9871019 .{
......@@ -1276,6 +1308,7 @@ const targets = [_]ArchTarget{
12761308 },
12771309 .omit_cpus = &.{
12781310 "generic",
1311 "loongarch32",
12791312 "loongarch64",
12801313 },
12811314 },
......@@ -1557,26 +1590,17 @@ const targets = [_]ArchTarget{
15571590 .llvm_name = "64bit-mode",
15581591 .omit = true,
15591592 },
1560 // Remove these when LLVM removes AVX10.N-256 support.
1561 .{
1562 .llvm_name = "avx10.1-256",
1563 .flatten = true,
1564 },
1565 .{
1566 .llvm_name = "avx10.2-256",
1567 .flatten = true,
1568 },
15691593 .{
15701594 .llvm_name = "avx10.1-512",
1571 .zig_name = "avx10_1",
1595 .omit = true,
15721596 },
15731597 .{
15741598 .llvm_name = "avx10.2-512",
1575 .zig_name = "avx10_2",
1599 .omit = true,
15761600 },
15771601 .{
1578 .llvm_name = "avx512f",
1579 .extra_deps = &.{"evex512"},
1602 .llvm_name = "evex512",
1603 .omit = true,
15801604 },
15811605 .{
15821606 .llvm_name = "alderlake",