From 0fe189415864329769ae5967d504c0574fe41060 Mon Sep 17 00:00:00 2001 From: xtex Date: Fri, 7 Aug 2026 14:52:44 +0800 Subject: [PATCH 1/5] tools: add LoongArch opcode encoding generator This tool reads data from loongarch-opcodes.git and generates three data files. encoding.zig contains an enum of mnemonics, a packed union of packed structs to represent bit-fields in instructions and encoder functions for each instruction. inst_formats.zon contains required target feature set for each instruction, which can be used by the backend to, under debug mode, verify if it emits any instruction that is not supported by the compilation target. It also contains information about slots in each instruction format, their type, location and postprocessing, which can be used by disassemblers. decode_tree.zon is the auto-generated decode tree, which will be used by disassemblers. Signed-off-by: xtex --- tools/gen_loongarch_encoding.zig | 526 +++++++++++++++++++++++++++++++ tools/loongarch/OpcodeDesc.zig | 455 ++++++++++++++++++++++++++ tools/loongarch/decode_tree.zig | 149 +++++++++ tools/loongarch/extra.txt | 9 + 4 files changed, 1139 insertions(+) create mode 100644 tools/gen_loongarch_encoding.zig create mode 100644 tools/loongarch/OpcodeDesc.zig create mode 100644 tools/loongarch/decode_tree.zig create mode 100644 tools/loongarch/extra.txt diff --git a/tools/gen_loongarch_encoding.zig b/tools/gen_loongarch_encoding.zig new file mode 100644 index 0000000000000000000000000000000000000000..767988d51ac1d2b7c2aa33e3b90f040e871fa1c7 --- /dev/null +++ b/tools/gen_loongarch_encoding.zig @@ -0,0 +1,526 @@ +//! Example usage: +//! git clone https://github.com/loongson-community/loongarch-opcodes.git ../loongarch-opcodes +//! zig run tools/gen_loongarch_encoding.zig -- ../loongarch-opcodes . + +const std = @import("std"); +const fs = std.fs; +const Allocator = std.mem.Allocator; +const print = std.debug.print; +const Writer = std.Io.Writer; +const ZonSerializer = std.zon.Serializer; + +const OpcodeDesc = @import("loongarch/OpcodeDesc.zig"); +const decode_tree = @import("loongarch/decode_tree.zig"); + +pub fn main(init: std.process.Init) !void { + const arena = init.arena.allocator(); + const io = init.io; + + var args = try init.minimal.args.iterateAllocator(arena); + const arg0 = args.next().?; + const opcodes_path = args.next() orelse usageAndExit(arg0, 0); + const zig_path = args.next() orelse usageAndExit(arg0, 1); + args.deinit(); + + var desc: OpcodeDesc = .{}; + defer desc.deinit(arena); + + var zig_dir = try std.Io.Dir.cwd().openDir(io, zig_path, .{}); + defer zig_dir.close(io); + + // load opcode data + { + print("Loading description files ..\n", .{}); + var opcodes_dir = try std.Io.Dir.cwd().openDir(io, opcodes_path, .{ .iterate = true }); + defer opcodes_dir.close(io); + var opcodes_iter = opcodes_dir.iterateAssumeFirstIteration(); + while (try opcodes_iter.next(io)) |opcodes_file| { + if (opcodes_file.kind != .file) continue; + if (!std.mem.endsWith(u8, opcodes_file.name, ".txt")) continue; + + print("Loading {s} ...\n", .{opcodes_file.name}); + const data = try opcodes_dir.readFileAlloc(io, opcodes_file.name, arena, .unlimited); + try desc.parse(arena, data); + // `data` is intentionally leaked here because it must live longer than `desc` + // ArenaAllocator should clean them up. + } + + print("Loading extra.txt ...\n", .{}); + const data = try zig_dir.readFileAlloc(io, "tools/loongarch/extra.txt", arena, .unlimited); + try desc.parse(arena, data); + + print("Loaded {} instructions, {} formats\n", .{ desc.opcode.items.len, desc.format.count() }); + desc.sort(); + print("Sorted data\n", .{}); + } + + // generate encoding.zig + { + print("Writing encoding.zig ...\n", .{}); + var buffer: Writer.Allocating = .init(arena); + defer buffer.deinit(); + const writer = &buffer.writer; + + try writer.print( + \\// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. + \\const Register = @import("bits.zig").Register; + \\ + , .{}); + + // mnemonic enum + { + try writer.print("\npub const Mnemonic = enum {{\n", .{}); + for (desc.opcode.items) |*opcode| { + try writer.print(" {f},\n", .{std.zig.fmtIdPU(opcode.name)}); + } + try writer.print("}};\n", .{}); + } + + // instruction struct + { + try writer.print( + \\ + \\pub const Instruction = packed union {{ + \\ word: u32, + \\ + , .{}); + + // format-based variants + { + var format_iter = desc.format.iterator(); + while (format_iter.next()) |entry| + try printFormatStruct(writer, entry.key_ptr.*, entry.value_ptr.*); + } + + // format-based encoders + { + var format_iter = desc.format.iterator(); + while (format_iter.next()) |entry| + try printFormatEncoder(writer, entry.key_ptr.*, entry.value_ptr.*); + } + + // opcode-based encoders + for (desc.opcode.items) |*opcode| { + const encoder_format = if (std.mem.eql(u8, opcode.name, opcode.orig_name)) opcode.orig_format else opcode.format; + try printInstructionEncoder(writer, opcode, encoder_format); + } + + try writer.print("}};\n", .{}); + } + + try zig_dir.writeFile(io, .{ + .sub_path = "src/codegen/loongarch/encoding.zig", + .data = buffer.written(), + }); + } + + // generate decode_tree.zon + { + print("Writing decode_tree.zon ...\n", .{}); + var buffer: Writer.Allocating = .init(arena); + defer buffer.deinit(); + const writer = &buffer.writer; + + try writer.print( + \\// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. + \\ + , .{}); + + try printDecodeTree(writer, arena, &desc); + + try writer.writeAll("\n"); + + try zig_dir.writeFile(io, .{ + .sub_path = "src/codegen/loongarch/decode_tree.zon", + .data = buffer.written(), + }); + } + + // generate inst_formats.zon + { + print("Writing inst_formats.zon ...\n", .{}); + var buffer: Writer.Allocating = .init(arena); + defer buffer.deinit(); + const writer = &buffer.writer; + + try writer.print( + \\// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. + \\ + , .{}); + + var s: ZonSerializer = .{ + .writer = writer, + .options = .{}, + }; + try serializeInstFormats(&s, &desc); + + try writer.writeAll("\n"); + + try zig_dir.writeFile(io, .{ + .sub_path = "src/codegen/loongarch/inst_formats.zon", + .data = buffer.written(), + }); + } + + print("Done.\n", .{}); +} + +fn usageAndExit(arg0: []const u8, code: u8) noreturn { + print( + \\Usage: {s} /path/loongarch-opcodes /path/zig + \\ + \\Updates LoongArch encoding data from loongarch-opcodes.git. + \\ + , .{arg0}); + std.process.exit(code); +} + +fn printFormatStruct(writer: *Writer, name: []const u8, format: *const OpcodeDesc.Format) !void { + if (format.slots[0].tag == .none) return; // skips EMPTY format + + try writer.print(" /// Fields of a `{s}` instruction.", .{name}); + try writer.print("\n {s}: packed struct {{ ", .{name}); + const Field = union(enum) { + funct: struct { width: u5 }, + immediate: struct { + signedness: std.builtin.Signedness, + width: u5, + }, + register: struct { + index: OpcodeDesc.Slot.Index, + width: u5, + }, + }; + var fields_buf: [4 * 2 + 1]Field = undefined; + var fields: std.ArrayList(Field) = .initBuffer(&fields_buf); + + // collect fields + var bit_offset: u6 = 0; + var slots = format.slots; + std.mem.sort(OpcodeDesc.Slot, &slots, false, struct { + fn cmp(_: bool, lhs: OpcodeDesc.Slot, rhs: OpcodeDesc.Slot) bool { + if (lhs.tag == .none) return false; + if (rhs.tag == .none) return true; + return lhs.offset() < rhs.offset(); + } + }.cmp); + for (slots) |slot| { + if (slot.tag == .none) break; + const slot_offset = slot.offset(); + const slot_width = slot.width(); + if (bit_offset != slot_offset) + fields.appendAssumeCapacity(.{ .funct = .{ .width = @truncate(slot_offset - bit_offset) } }); + + switch (slot.tag) { + .none => unreachable, + .imm => { + fields.appendAssumeCapacity(.{ .immediate = .{ + .signedness = slot.payload.imm.signedness, + .width = slot_width, + } }); + }, + .reg => fields.appendAssumeCapacity(.{ .register = .{ + .index = slot.payload.reg.index, + .width = slot_width, + } }), + } + bit_offset = slot_offset + slot_width; + } + if (bit_offset != 32) + fields.appendAssumeCapacity(.{ .funct = .{ .width = @intCast(@as(u6, 32) - bit_offset) } }); + + // detect shadowed immediate field names + const imm_shadowed = imm_shadowed: { + var imm_names: [std.math.maxInt(u6) + 1]bool = @splat(false); + for (fields.items) |field| { + switch (field) { + else => {}, + .immediate => |imm_field| { + var imm_name_key: u6 = imm_field.width; + if (imm_field.signedness == .signed) imm_name_key |= std.math.maxInt(u5) + 1; + if (imm_names[imm_name_key]) break :imm_shadowed true; + imm_names[imm_name_key] = true; + }, + } + } + break :imm_shadowed false; + }; + + // print fields + bit_offset = 0; + for (fields.items, 0..) |field, field_i| { + if (field_i != 0) try writer.writeAll(", "); + switch (field) { + .funct => |pl| { + try writer.print("funct{}: u{}", .{ bit_offset, pl.width }); + bit_offset += pl.width; + }, + .immediate => |pl| { + if (imm_shadowed) { + try writer.print("imm{}: {c}{}", .{ + bit_offset, + @as(u8, switch (pl.signedness) { + .signed => 'i', + .unsigned => 'u', + }), + pl.width, + }); + } else { + try writer.print("{c}i{}: {c}{}", .{ + @as(u8, switch (pl.signedness) { + .signed => 's', + .unsigned => 'u', + }), + pl.width, + @as(u8, switch (pl.signedness) { + .signed => 'i', + .unsigned => 'u', + }), + pl.width, + }); + } + bit_offset += pl.width; + }, + .register => |pl| { + try writer.print("r{s}: u{}", .{ @tagName(pl.index), pl.width }); + bit_offset += pl.width; + }, + } + } + try writer.print(" }},\n", .{}); +} + +fn printFormatEncoder(writer: *Writer, name: []const u8, format: *const OpcodeDesc.Format) !void { + try writer.print("\n /// Encodes a `{s}` instruction.", .{name}); + try writer.print("\n pub inline fn encode{s}(word: u32", .{name}); + for (format.slots, 0..) |slot, slot_i| { + switch (slot.tag) { + .none => break, + .imm => { + const pl = slot.payload.imm; + + try writer.print(", p{}: {c}{}", .{ + slot_i, + @as(u8, switch (pl.signedness) { + .signed => 'i', + .unsigned => 'u', + }), + pl.length, + }); + }, + .reg => try writer.print(", p{}: Register", .{slot_i}), + } + } + try writer.print(") Instruction {{\n", .{}); + if (format.slots[0].tag == .none) { + try writer.print(" return .{{ .word = word }};\n", .{}); + } else { + try writer.print(" return .{{ .word = word", .{}); + for (format.slots, 0..) |slot, slot_i| { + switch (slot.tag) { + .none => break, + .imm => { + const pl = slot.payload.imm; + try writer.print(" |\n (", .{}); + try writer.print("(@as(u32, @as(u{}, @bitCast(p{})))", .{ pl.length, slot_i }); + + switch (pl.post_proc.tag) { + .none => {}, + .add => try writer.print(" - {}", .{pl.post_proc.payload.add}), + .shl => try writer.print(" >> {}", .{pl.post_proc.payload.shl}), + } + + try writer.print(") << {})", .{pl.index.offset()}); + }, + .reg => { + const pl = slot.payload.reg; + try writer.print(" |\n (@as(u32, p{}.encode()) << {})", .{ slot_i, pl.index.offset() }); + }, + } + } + try writer.print(" }};\n", .{}); + } + try writer.print(" }}\n", .{}); +} + +fn printInstructionEncoder(writer: *Writer, opcode: *OpcodeDesc.Opcode, format: *const OpcodeDesc.Format) !void { + try writer.print("\n /// Encodes a `{s}` instruction", .{opcode.name}); + if (opcode.required_features != OpcodeDesc.Opcode.RequiredFeatures{}) { + try writer.writeAll(" (requires "); + var first = true; + const feature_fields = comptime std.meta.fieldNames(OpcodeDesc.Opcode.RequiredFeatures); + inline for (feature_fields) |field| { + if (@field(opcode.required_features, field)) { + if (first) first = false else try writer.writeAll(" & "); + try writer.writeAll(field); + } + } + try writer.writeByte(')'); + } + try writer.writeByte('.'); + try writer.print("\n pub inline fn {f}(", .{std.zig.fmtIdPU(opcode.name)}); + for (format.slots, 0..) |slot, slot_i| { + if (slot_i != 0 and slot.tag != .none) + try writer.print(", ", .{}); + switch (slot.tag) { + .none => break, + .imm => { + const pl = slot.payload.imm; + + try writer.print("p{}: {c}{}", .{ + slot_i, + @as(u8, switch (pl.signedness) { + .signed => 'i', + .unsigned => 'u', + }), + pl.length, + }); + }, + .reg => try writer.print("p{}: Register", .{slot_i}), + } + } + try writer.print(") Instruction {{\n", .{}); + try writer.print(" return encode{s}(0x{x:0>8}", .{ format.name, opcode.word }); + for (format.slots, 0..) |slot, slot_i| { + switch (slot.tag) { + .none => break, + else => try writer.print(", p{}", .{slot_i}), + } + } + try writer.print(");\n", .{}); + try writer.print(" }}\n", .{}); +} + +fn printDecodeTree(writer: *Writer, gpa: Allocator, desc: *const OpcodeDesc) !void { + var arena: std.heap.ArenaAllocator = .init(gpa); + defer arena.deinit(); + const root_node = try decode_tree.populate(arena.allocator(), desc); + try printDecodeTreeNode(writer, root_node, 0); +} + +fn printDecodeTreeNode(writer: *Writer, node: *const decode_tree.Node, indent: usize) !void { + if (node.mask == 0) { + try writer.print(".{{ .instruction = .{f} }}", .{std.zig.fmtId(node.next.instruction.name)}); + } else { + try writer.print(".{{ .mask = 0x{x:0>8}, .cases = .{{\n", .{node.mask}); + for (node.next.cases) |*case| { + try printIndentation(writer, indent + 1); + if (case.catch_all) { + try writer.print(".{{ .then = ", .{}); + try printDecodeTreeNode(writer, case.child, indent + 1); + try writer.print(" }},\n", .{}); + } else { + try writer.print(".{{ .value = 0x{x:0>8}, .then = ", .{case.variant}); + try printDecodeTreeNode(writer, case.child, indent + 1); + try writer.print(" }},\n", .{}); + } + } + try printIndentation(writer, indent); + try writer.print("}} }}", .{}); + } +} + +fn printIndentation(writer: *Writer, indent: usize) !void { + try writer.splatByteAll(' ', 4 * indent); +} + +fn serializeInstFormats(s: *ZonSerializer, desc: *const OpcodeDesc) !void { + var root_struct = try s.beginStruct(.{}); + + { + var instructions_s = try root_struct.beginStructField("instructions", .{}); + for (desc.opcode.items) |*opcode| { + var opcode_s = try instructions_s.beginStructField(opcode.name, .{}); + + try opcode_s.fieldPrefix("word"); + try s.writer.writeAll("0x"); + try s.writer.printInt(opcode.word, 16, .lower, .{ + .alignment = .right, + .fill = '0', + .width = 8, + }); + + try opcode_s.fieldPrefix("format"); + try s.ident(opcode.format.name); + if (opcode.orig_format != opcode.format) { + try opcode_s.fieldPrefix("orig_format"); + try s.ident(opcode.orig_format.name); + } + + if (opcode.orig_name.ptr != opcode.name.ptr) + try opcode_s.field("orig_name", opcode.orig_name, .{}); + + const field_names = comptime std.meta.fieldNames(OpcodeDesc.Opcode.RequiredFeatures); + var num_features: u32 = 0; + inline for (field_names) |field| { + if (@field(opcode.required_features, field)) + num_features += 1; + } + var features_s = try opcode_s.beginTupleField("features", .{ .whitespace_style = .{ .fields = num_features } }); + inline for (field_names) |field| { + if (@field(opcode.required_features, field)) { + try features_s.fieldPrefix(); + try s.ident(field); + } + } + try features_s.end(); + + try opcode_s.end(); + } + try instructions_s.end(); + } + + { + var formats_s = try root_struct.beginStructField("formats", .{}); + for (desc.format.values()) |format| { + var format_s = try formats_s.beginStructField(format.name, .{ .whitespace_style = .{ .wrap = false } }); + + var slots_s = try format_s.beginTupleField("slots", .{}); + for (format.slots) |slot| { + if (slot.tag == .none) break; + var slot_s = try slots_s.beginStructField(.{ .whitespace_style = .{ .wrap = false } }); + switch (slot.tag) { + .none => unreachable, + .reg => { + const pl = slot.payload.reg; + var reg_s = try slot_s.beginStructField("reg", .{ .whitespace_style = .{ .fields = 2 } }); + try reg_s.field("location", pl.index.offset(), .{}); + + try reg_s.fieldPrefix("class"); + try s.ident(@tagName(pl.class)); + + try reg_s.end(); + }, + .imm => { + const pl = slot.payload.imm; + var imm_s = try slot_s.beginStructField("imm", .{ .whitespace_style = .{ .wrap = false } }); + try imm_s.field("location", pl.index.offset(), .{}); + try imm_s.field("length", pl.length, .{}); + + try imm_s.fieldPrefix("signedness"); + try s.ident(@tagName(pl.signedness)); + + if (pl.post_proc.tag != .none) { + var pp_s = try imm_s.beginStructField("post_proc", .{ .whitespace_style = .{ .fields = 1 } }); + switch (pl.post_proc.tag) { + .none => unreachable, + .add => try pp_s.field("add", pl.post_proc.payload.add, .{}), + .shl => try pp_s.field("shl", pl.post_proc.payload.shl, .{}), + } + try pp_s.end(); + } + + try imm_s.end(); + }, + } + try slot_s.end(); + } + try slots_s.end(); + + try format_s.end(); + } + try formats_s.end(); + } + + try root_struct.end(); +} diff --git a/tools/loongarch/OpcodeDesc.zig b/tools/loongarch/OpcodeDesc.zig new file mode 100644 index 0000000000000000000000000000000000000000..e88a65c2718e8cc9d24219d8a7dc4c19b91d8f3d --- /dev/null +++ b/tools/loongarch/OpcodeDesc.zig @@ -0,0 +1,455 @@ +//! Parser for format description files in +//! https://github.com/loongson-community/loongarch-opcodes. + +const std = @import("std"); +const mem = std.mem; +const Allocator = mem.Allocator; +const Reader = std.Io.Reader; + +const OpcodeDesc = @This(); + +/// Maximum number of slots in one instruction format. +const max_slots = 4; + +opcode: std.ArrayList(Opcode) = .empty, +format_pool: std.heap.MemoryPool(Format) = .empty, +format: std.StringArrayHashMapUnmanaged(*Format) = .empty, + +pub fn deinit(desc: *OpcodeDesc, gpa: Allocator) void { + desc.opcode.deinit(gpa); + desc.format.deinit(gpa); + desc.format_pool.deinit(gpa); +} + +/// Instruction format. Slots are filled one by one, ending with reaching max_slots or a .none slot. +pub const Format = struct { + name: []const u8, + slots: [max_slots]Slot, + + pub fn parse(name: []const u8) !Format { + var format: Format = .{ + .name = name, + .slots = .{ .none, .none, .none, .none }, + }; + var reader: Reader = .fixed(name); + var slot_index: std.math.IntFittingRange(0, max_slots) = 0; + parse_empty: { + const str = reader.peekArray(5) catch |err| switch (err) { + error.EndOfStream => break :parse_empty, + else => return err, + }; + if (mem.eql(u8, &str.*, "EMPTY")) + return format; + } + + parse_slots: while (slot_index < max_slots) : (slot_index += 1) { + switch (reader.takeByte() catch |err| switch (err) { + error.EndOfStream => break :parse_slots, + else => return err, + }) { + 'D' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .int, + .index = .d, + } } }, + 'J' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .int, + .index = .j, + } } }, + 'K' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .int, + .index = .k, + } } }, + 'A' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .int, + .index = .a, + } } }, + 'F' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .fp, + .index = try .parse(&reader), + } } }, + 'C' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .fcc, + .index = try .parse(&reader), + } } }, + 'T' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .lbt_scratch, + .index = try .parse(&reader), + } } }, + 'V' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .lsx, + .index = try .parse(&reader), + } } }, + 'X' => format.slots[slot_index] = .{ .tag = .reg, .payload = .{ .reg = .{ + .class = .lasx, + .index = try .parse(&reader), + } } }, + 'S', 'U' => |signedness_ch| { + const signedness: std.builtin.Signedness = if (signedness_ch == 'S') .signed else .unsigned; + while (slot_index < max_slots and continue_imm_slot: { + _ = Slot.Index.fromChar(reader.peekByte() catch |err| switch (err) { + error.EndOfStream => break :continue_imm_slot false, + else => return err, + }) catch break :continue_imm_slot false; + break :continue_imm_slot true; + }) : (slot_index += 1) { + const index: Slot.Index = try .parse(&reader); + const length = try takeInteger(u5, &reader); + const post_proc = post_proc: { + if ('p' == reader.peekByte() catch |err| switch (err) { + error.EndOfStream => ' ', + else => return err, + }) { + reader.toss(1); + break :post_proc try Slot.PostProcess.parse(&reader); + } else break :post_proc Slot.PostProcess.none; + }; + format.slots[slot_index] = .{ .tag = .imm, .payload = .{ .imm = .{ + .index = index, + .length = length, + .signedness = signedness, + .post_proc = post_proc, + } } }; + } + slot_index -= 1; + }, + else => return error.InvalidCharacter, + } + } + + return format; + } +}; + +test "parse format" { + _ = try Format.parse("DJFmSk12m13ps3"); + _ = try Format.parse("DJSk12m13ps3U16pp1"); + _ = try Format.parse("DJK"); +} + +pub const Slot = packed struct { + tag: Slot.Tag, + payload: Slot.Payload, + + comptime { + std.debug.assert(@sizeOf(Slot) == 4); + } + + const Payload = packed union { + none: u16, // unused number, just for padding + imm: packed struct { + index: Index, + length: u5, + signedness: std.builtin.Signedness, + post_proc: PostProcess = .none, + }, + reg: packed struct { + class: enum(u13) { int, fp, fcc, lbt_scratch, lsx, lasx }, + index: Index, + }, + }; + + const Tag = enum(u16) { reg, imm, none }; + + pub const none: Slot = .{ .tag = .none, .payload = .{ .none = 0 } }; + + pub const Index = enum(u3) { + // zig fmt: off + d, j, k, a, m, n, + // zig fmt: on + + pub fn offset(index: Index) u5 { + return switch (index) { + .d => 0, + .j => 5, + .k => 10, + .a => 15, + .m => 16, + .n => 18, + }; + } + + pub fn fromChar(ch: u8) error{UnknownIndexChar}!Index { + return switch (ch) { + 'd' => .d, + 'j' => .j, + 'k' => .k, + 'a' => .a, + 'm' => .m, + 'n' => .n, + else => return error.UnknownIndexChar, + }; + } + + pub const ParseError = Reader.Error || error{UnknownIndexChar}; + pub fn parse(reader: *Reader) Index.ParseError!Index { + return fromChar(try reader.takeByte()); + } + }; + + /// Post-process operations for disassemblying. + pub const PostProcess = packed struct { + tag: PostProcess.Tag, + payload: PostProcess.Payload, + + const Payload = packed union { + /// assembly value = encoded value + N + add: u5, + /// assembly value = encoded value << N + shl: u5, + none: u5, // unused number, for padding + }; + + const Tag = std.meta.FieldEnum(PostProcess.Payload); + + pub const none: PostProcess = .{ .tag = .none, .payload = .{ .none = 0 } }; + + pub const ParseError = Reader.Error || std.fmt.ParseIntError; + pub fn parse(reader: *Reader) PostProcess.ParseError!PostProcess { + switch (try reader.takeByte()) { + 'p' => return .{ + .tag = .add, + .payload = .{ .add = try takeInteger(u4, reader) }, + }, + 's' => return .{ + .tag = .shl, + .payload = .{ .shl = try takeInteger(u4, reader) }, + }, + else => return error.InvalidCharacter, + } + } + }; + + pub fn offset(slot: Slot) u5 { + return switch (slot.tag) { + .none => unreachable, + .imm => slot.payload.imm.index.offset(), + .reg => slot.payload.reg.index.offset(), + }; + } + + pub fn width(slot: Slot) u5 { + return switch (slot.tag) { + .none => unreachable, + .imm => slot.payload.imm.length, + .reg => switch (slot.payload.reg.class) { + .fcc => 3, + else => 5, + }, + }; + } + + pub fn mask(slot: Slot) u32 { + const off = slot.offset(); + const size = slot.width(); + const msb, const overflow = @addWithOverflow(off, size); + if (overflow == 1) { + @branchHint(.unlikely); + return ~((@as(u32, 1) << off) - 1); + } + return ((@as(u32, 1) << msb) - 1) ^ ((@as(u32, 1) << off) - 1); + } +}; + +test "mask" { + try std.testing.expectEqual(0b111100000, (Slot{ .tag = .imm, .payload = .{ .imm = .{ + .index = .j, + .length = 4, + .signedness = .unsigned, + } } }).mask()); + try std.testing.expectEqual(0x7fffffff, (Slot{ .tag = .imm, .payload = .{ .imm = .{ + .index = .d, + .length = 31, + .signedness = .unsigned, + } } }).mask()); + try std.testing.expectEqual(0x7fffffff, (Slot{ .tag = .imm, .payload = .{ .imm = .{ + .index = .d, + .length = 31, + .signedness = .unsigned, + } } }).mask()); + try std.testing.expectEqual(0xffffffe0, (Slot{ .tag = .imm, .payload = .{ .imm = .{ + .index = .j, + .length = 27, + .signedness = .unsigned, + } } }).mask()); + try std.testing.expectEqual(0b111110000000000, (Slot{ .tag = .reg, .payload = .{ .reg = .{ + .class = .int, + .index = .k, + } } }).mask()); +} + +fn takeInteger(comptime T: type, reader: *Reader) (Reader.Error || std.fmt.ParseIntError)!T { + if (std.math.maxInt(T) < 10) { + const ch = try reader.takeByte(); + return std.math.cast(T, ch ^ '0') orelse return error.Overflow; + } + var v: T = 0; + + var ch: u8 = try reader.peekByte(); + if (!std.ascii.isDigit(ch)) return error.InvalidCharacter; + + while (std.ascii.isDigit(ch)) : (ch = reader.peekByte() catch |err| switch (err) { + error.EndOfStream => break, + else => return err, + }) { + v = try std.math.add( + T, + try std.math.add( + T, + try std.math.shlExact(T, v, 3), + try std.math.shlExact(T, v, 1), + ), + std.math.cast(T, ch ^ '0') orelse return error.Overflow, + ); + reader.toss(1); + } + return v; +} + +test takeInteger { + var reader: std.Io.Reader = undefined; + + reader = .fixed("123"); + try std.testing.expectEqual(123, try takeInteger(u8, &reader)); + reader = .fixed("123ignored"); + try std.testing.expectEqual(123, try takeInteger(u8, &reader)); + reader = .fixed("bad"); + try std.testing.expectError(error.InvalidCharacter, takeInteger(u8, &reader)); + reader = .fixed("1"); + try std.testing.expectEqual(1, try takeInteger(u1, &reader)); +} + +pub const Opcode = struct { + word: u32, + name: []const u8, + format: *Format, + orig_name: []const u8, + orig_format: *Format, + required_features: RequiredFeatures, + + pub const RequiredFeatures = packed struct { + @"32bit": bool = false, + @"32s": bool = false, + @"64bit": bool = false, + f: bool = false, + d: bool = false, + lsx: bool = false, + lasx: bool = false, + lbt: bool = false, + lvz: bool = false, + }; +}; + +/// Parses a opcode data file. +/// Caller owns the data string and the data string must live longer +/// than the OpcodeDesc. +pub fn parse(desc: *OpcodeDesc, gpa: Allocator, data: []const u8) !void { + var lines = mem.tokenizeScalar(u8, data, '\n'); + while (lines.next()) |line| { + if (line[0] == '#') continue; // skip comments, not used by upstream but used in tools/loongarch/extra.txt + var tokens = mem.tokenizeScalar(u8, line, ' '); + + const word_buf = tokens.next() orelse return error.UnexpectedEol; + const word = try std.fmt.parseInt(u32, word_buf, 16); + const name = tokens.next() orelse return error.UnexpectedEol; + const format_str = tokens.next() orelse return error.UnexpectedEol; + const format = try desc.getOrParseFormat(gpa, format_str); + + const opcode = try desc.opcode.addOne(gpa); + opcode.* = .{ + .word = word, + .name = name, + .format = format, + .orig_name = name, + .orig_format = format, + .required_features = .{}, + }; + + // parse attributes + while (tokens.next()) |attr| { + if (attr[0] != '@') return error.MalformedAttribute; + if (mem.indexOfScalar(u8, attr, '=')) |eql_pos| { + const attr_name = attr[1..][0 .. eql_pos - 1]; + const attr_val = attr[eql_pos + 1 ..]; + + if (mem.eql(u8, attr_name, "orig_name")) { // manual name + opcode.orig_name = attr_val; + } else if (mem.eql(u8, attr_name, "orig_fmt")) { // manual format + opcode.orig_format = try desc.getOrParseFormat(gpa, attr_val); + } + } else { + const attr_name = attr[1..]; + + if (mem.eql(u8, attr_name, "la32")) { // available in LA32S + if (!opcode.required_features.@"32bit") + opcode.required_features.@"32s" = true; + } else if (mem.eql(u8, attr_name, "primary")) { // available in LA32R + opcode.required_features.@"32bit" = true; + opcode.required_features.@"32s" = false; + } else if (mem.eql(u8, attr_name, "lvz")) { // requires LVZ + opcode.required_features.lvz = false; + } else if (mem.eql(u8, attr_name, "lbt")) { // requires LBT + opcode.required_features.lbt = false; + } + } + } + + // determine based on register usages + for (opcode.format.slots) |slot| { + switch (slot.tag) { + .none => break, + .imm => {}, + .reg => { + switch (slot.payload.reg.class) { + .fp => { + opcode.required_features.f = true; + if (mem.eql(u8, opcode.name, ".d")) { // requires double-precision FP + opcode.required_features.d = true; + } + }, + .fcc => opcode.required_features.f = true, + .lsx => opcode.required_features.lsx = true, + .lasx => opcode.required_features.lasx = true, + .lbt_scratch => opcode.required_features.lbt = true, + else => {}, + } + }, + } + } + + // if there are not any attributes indicating that the instruction requires + // any other features or supports LA32, we assume that it requires LA64. + if (opcode.required_features == Opcode.RequiredFeatures{}) { + opcode.required_features.@"64bit" = true; + } + } +} + +/// Gets or parses a format string. +/// The string must live longer than the OpcodeDesc. +pub fn getOrParseFormat(desc: *OpcodeDesc, gpa: Allocator, format: []const u8) !*Format { + const gop = try desc.format.getOrPut(gpa, format); + if (!gop.found_existing) { + errdefer _ = desc.format.swapRemove(format); + const format_ptr = try desc.format_pool.create(gpa); + errdefer desc.format_pool.destroy(format_ptr); + + format_ptr.* = try Format.parse(format); + gop.value_ptr.* = format_ptr; + } + return gop.value_ptr.*; +} + +pub fn sort(desc: *OpcodeDesc) void { + mem.sort(Opcode, desc.opcode.items, false, struct { + fn cmp(_: bool, lhs: Opcode, rhs: Opcode) bool { + return mem.order(u8, lhs.name, rhs.name) == .lt; + } + }.cmp); + desc.format.sort(struct { + keys: [][]const u8, + + pub fn lessThan(ctx: @This(), a_index: usize, b_index: usize) bool { + return mem.order(u8, ctx.keys[a_index], ctx.keys[b_index]) == .lt; + } + }{ .keys = desc.format.keys() }); +} diff --git a/tools/loongarch/decode_tree.zig b/tools/loongarch/decode_tree.zig new file mode 100644 index 0000000000000000000000000000000000000000..186a3f00efdee9797436257de0a974f5c1056c56 --- /dev/null +++ b/tools/loongarch/decode_tree.zig @@ -0,0 +1,149 @@ +const std = @import("std"); +const Allocator = std.mem.Allocator; +const log = std.log.scoped(.loongarch_decode_tree); + +const OpcodeDesc = @import("OpcodeDesc.zig"); +const Opcode = OpcodeDesc.Opcode; + +pub const Node = struct { + mask: u32, + /// `cases` when mask is non-zero. `instruction` when mask is zero. + next: union { + /// catch-all case + cases: []const Case, + instruction: *const Opcode, + }, +}; + +pub const Case = struct { + catch_all: bool, + variant: u32, // valid only when catch-all is not set + child: *const Node, +}; + +pub fn populate(arena: Allocator, desc: *const OpcodeDesc) !*Node { + var ops: std.ArrayList(*const Opcode) = .empty; + defer ops.deinit(arena); + try ops.ensureUnusedCapacity(arena, desc.opcode.items.len); + for (desc.opcode.items) |*op| ops.appendAssumeCapacity(op); + + return try populateAdvanced(arena, ops.items, 0); +} + +pub fn populateAdvanced(arena: Allocator, ops: []const *const Opcode, checked_mask: u32) !*Node { + if (ops.len == 1) { + const node = try arena.create(Node); + node.* = .{ .mask = 0, .next = .{ .instruction = ops[0] } }; + return node; + } + + // look for unchecked common static bits + common_static_bits: { + var common_mask: u32 = ~checked_mask; + for (ops) |op| { + for (op.format.slots) |slot| { + if (slot.tag == .none) break; + common_mask &= ~slot.mask(); + } + } + if (common_mask == 0) break :common_static_bits; + + // there are some common bits to check + var cases: std.ArrayList(Case) = .empty; + defer cases.deinit(arena); + var known_variants: std.ArrayList(u32) = .empty; + defer known_variants.deinit(arena); + + for (ops) |op| { + const variant = op.word & common_mask; + if (std.mem.indexOfScalar(u32, known_variants.items, variant) == null) { + // new variant + try known_variants.append(arena, variant); + + var variant_ops: std.ArrayList(*const Opcode) = .empty; + defer variant_ops.deinit(arena); + variant_ops.ensureTotalCapacity(arena, ops.len / 2) catch {}; + for (ops) |op1| + if ((op1.word & common_mask) == variant) try variant_ops.append(arena, op1); + + const child = try populateAdvanced(arena, variant_ops.items, checked_mask | common_mask); + try cases.append(arena, .{ + .catch_all = false, + .variant = variant, + .child = child, + }); + } + } + + const node = try arena.create(Node); + node.* = .{ + .mask = common_mask, + .next = .{ .cases = try cases.toOwnedSlice(arena) }, + }; + return node; + } + + // look for bits that are static for some opcodes but dynamic for one opcode, e.g. csrxchg + half_static_bits: { + // these bits are static in at least one opcode + var half_static_mask: u32 = 0; + for (ops) |op| { + var op_static_mask: u32 = 0xffffffff; + for (op.format.slots) |slot| { + if (slot.tag == .none) break; + op_static_mask &= ~slot.mask(); + } + half_static_mask |= op_static_mask; + } + half_static_mask &= ~checked_mask; + if (half_static_mask == 0) break :half_static_bits; + + var cases: std.ArrayList(Case) = .empty; + defer cases.deinit(arena); + var maybe_dynamic_op: ?*const Opcode = null; + + for (ops) |op| { + const variant = op.word & half_static_mask; + + var op_static_mask = ~checked_mask; + for (op.format.slots) |slot| { + if (slot.tag == .none) break; + op_static_mask &= ~slot.mask(); + } + if (op_static_mask != half_static_mask) { + if (maybe_dynamic_op) |dynamic_op| { + log.err("unsupported: {s}, {s}", .{ dynamic_op.name, op.name }); + return error.Unsupported; + } else { + maybe_dynamic_op = op; + continue; + } + } + + const child = try populateAdvanced(arena, &.{op}, checked_mask | half_static_mask); + try cases.append(arena, .{ + .catch_all = false, + .variant = variant, + .child = child, + }); + } + + if (maybe_dynamic_op) |dynamic_op| { + const child = try populateAdvanced(arena, &.{dynamic_op}, checked_mask | half_static_mask); + try cases.append(arena, .{ + .catch_all = true, + .variant = 0, + .child = child, + }); + } else unreachable; + + const node = try arena.create(Node); + node.* = .{ + .mask = half_static_mask, + .next = .{ .cases = try cases.toOwnedSlice(arena) }, + }; + return node; + } + + return error.Unsupported; +} diff --git a/tools/loongarch/extra.txt b/tools/loongarch/extra.txt new file mode 100644 index 0000000000000000000000000000000000000000..116a5a068ad2d3ae5b9f0ea4f600135656f80027 --- /dev/null +++ b/tools/loongarch/extra.txt @@ -0,0 +1,9 @@ +# loongarch-opcodes removed these instructions as their encodings +# collide with csrxchg/gcsrxchg. +# They are added back here to support assembler and disassembler +# as decode_tree.zig has supported generating decode-trees for these +# colliding encodings. +04000000 csrrd DUk14 @primary +04000032 csrwr DUk14 @primary +05000000 gcsrrd DUk14 @lvz +05000032 gcsrwr DUk14 @lvz -- 2.54.0 From 709154ffb87790ef1537f7929df731e70b54f367 Mon Sep 17 00:00:00 2001 From: xtex Date: Fri, 7 Aug 2026 15:04:16 +0800 Subject: [PATCH 2/5] loongarch: add generated encoding data Generated with tools/gen_loongarch_encoding.zig, using loongarch-opcodes version 878c9a2366d1 (Merge pull request #7 from ksco/develop, 2026-03-06) Signed-off-by: xtex --- src/codegen/loongarch/decode_tree.zon | 2817 +++++ src/codegen/loongarch/encoding.zig | 13695 +++++++++++++++++++++++ src/codegen/loongarch/inst_formats.zon | 11059 ++++++++++++++++++ 3 files changed, 27571 insertions(+) create mode 100644 src/codegen/loongarch/decode_tree.zon create mode 100644 src/codegen/loongarch/encoding.zig create mode 100644 src/codegen/loongarch/inst_formats.zon diff --git a/src/codegen/loongarch/decode_tree.zon b/src/codegen/loongarch/decode_tree.zon new file mode 100644 index 0000000000000000000000000000000000000000..2dc1a11fee7f9db7cccb6f6d5fba09604bb38b5c --- /dev/null +++ b/src/codegen/loongarch/decode_tree.zon @@ -0,0 +1,2817 @@ +// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. +.{ .mask = 0xfc000000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x03c00000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x003c0000, .cases = .{ + .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"adc.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"adc.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"adc.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"adc.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"sbc.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"sbc.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"sbc.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"sbc.w" } }, + } } }, + .{ .value = 0x00100000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00008000, .then = .{ .instruction = .@"add.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"add.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .maskeqz } }, + .{ .value = 0x00038000, .then = .{ .instruction = .masknez } }, + .{ .value = 0x00020000, .then = .{ .instruction = .slt } }, + .{ .value = 0x00028000, .then = .{ .instruction = .sltu } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"sub.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"sub.w" } }, + } } }, + .{ .value = 0x00280000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00018000, .then = .{ .instruction = .@"addu12i.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"addu12i.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"break" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .dbgcall } }, + .{ .value = 0x00038000, .then = .{ .instruction = .hypcall } }, + .{ .value = 0x00030000, .then = .{ .instruction = .syscall } }, + } } }, + .{ .value = 0x00140000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00008000, .then = .{ .instruction = .@"and" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .andn } }, + .{ .value = 0x00000000, .then = .{ .instruction = .nor } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"or" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .orn } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"sll.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"srl.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .xor } }, + } } }, + .{ .value = 0x00380000, .then = .{ .mask = 0x00038010, .cases = .{ + .{ .value = 0x00000010, .then = .{ .instruction = .@"armadc.w" } }, + .{ .value = 0x00010010, .then = .{ .instruction = .@"armand.w" } }, + .{ .value = 0x00018010, .then = .{ .instruction = .@"armor.w" } }, + .{ .value = 0x00008010, .then = .{ .instruction = .@"armsbc.w" } }, + .{ .value = 0x00028010, .then = .{ .instruction = .@"armsll.w" } }, + .{ .value = 0x00038010, .then = .{ .instruction = .@"armsra.w" } }, + .{ .value = 0x00030010, .then = .{ .instruction = .@"armsrl.w" } }, + .{ .value = 0x00020010, .then = .{ .instruction = .@"armxor.w" } }, + } } }, + .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"armadd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .armmove } }, + .{ .value = 0x00028000, .then = .{ .mask = 0x000043e0, .cases = .{ + .{ .value = 0x00004000, .then = .{ .instruction = .armsetj } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86setj } }, + } } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"armsub.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"rcr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"rcr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"rcr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"rcr.w" } }, + } } }, + .{ .value = 0x003c0000, .then = .{ .mask = 0x00038010, .cases = .{ + .{ .value = 0x00038010, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x0000000e, .then = .{ .instruction = .@"armmov.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"armmov.w" } }, + .{ .value = 0x0000000c, .then = .{ .instruction = .@"armnot.w" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"armrrx.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86and.b" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86and.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86and.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86and.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86or.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86or.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86or.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86or.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86xor.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86xor.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86xor.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86xor.w" } }, + } } }, + .{ .value = 0x00000010, .then = .{ .instruction = .@"armrotr.w" } }, + .{ .value = 0x00020010, .then = .{ .instruction = .@"armrotri.w" } }, + .{ .value = 0x00008010, .then = .{ .instruction = .@"armslli.w" } }, + .{ .value = 0x00018010, .then = .{ .instruction = .@"armsrai.w" } }, + .{ .value = 0x00010010, .then = .{ .instruction = .@"armsrli.w" } }, + .{ .value = 0x00030000, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86adc.b" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86adc.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86adc.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86adc.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86add.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86add.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86add.du" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86add.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86add.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86add.wu" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86sub.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86sub.d" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86sub.du" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86sub.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86sub.w" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86sub.wu" } }, + } } }, + .{ .value = 0x00028000, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86mul.b" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86mul.bu" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86mul.d" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86mul.du" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86mul.h" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86mul.hu" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86mul.w" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86mul.wu" } }, + } } }, + .{ .value = 0x00038000, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86rcl.b" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86rcl.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86rcl.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86rcl.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86rcr.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86rcr.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86rcr.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86rcr.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86rotl.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86rotl.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86rotl.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86rotl.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86rotr.b" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86rotr.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86rotr.h" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86rotr.w" } }, + } } }, + .{ .value = 0x00030010, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86sbc.b" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86sbc.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86sbc.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86sbc.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86sll.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86sll.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86sll.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86sll.w" } }, + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86sra.b" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86sra.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86sra.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86sra.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86srl.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86srl.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86srl.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86srl.w" } }, + } } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00018000, .then = .{ .instruction = .asrtgt } }, + .{ .value = 0x00010000, .then = .{ .instruction = .asrtle } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002000, .then = .{ .instruction = .@"clo.d" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"clo.w" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"clz.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"clz.w" } }, + .{ .value = 0x00006c00, .then = .{ .instruction = .cpucfg } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"cto.d" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"cto.w" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"ctz.d" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"ctz.w" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .movgr2scr } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .movscr2gr } }, + .{ .value = 0x00006800, .then = .{ .instruction = .@"rdtime.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"rdtimeh.w" } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"rdtimel.w" } }, + .{ .value = 0x00003000, .then = .{ .instruction = .@"revb.2h" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"revb.2w" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"revb.4h" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"revb.d" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"revbit.4b" } }, + .{ .value = 0x00004c00, .then = .{ .instruction = .@"revbit.8b" } }, + .{ .value = 0x00005400, .then = .{ .instruction = .@"revbit.d" } }, + .{ .value = 0x00005000, .then = .{ .instruction = .@"revbit.w" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"revh.2w" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"revh.d" } }, + .{ .value = 0x00005c00, .then = .{ .instruction = .@"sext.b" } }, + .{ .value = 0x00005800, .then = .{ .instruction = .@"sext.h" } }, + .{ .value = 0x00007400, .then = .{ .instruction = .x86mftop } }, + .{ .value = 0x00007000, .then = .{ .instruction = .x86mttop } }, + .{ .value = 0x00007800, .then = .{ .instruction = .x86setloope } }, + .{ .value = 0x00007c00, .then = .{ .instruction = .x86setloopne } }, + } } }, + .{ .value = 0x00008000, .then = .{ .mask = 0x00007c1f, .cases = .{ + .{ .value = 0x00000008, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000020, .then = .{ .instruction = .x86clrtm } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86settm } }, + } } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86dec.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86dec.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86dec.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86dec.w" } }, + .{ .value = 0x00000009, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000020, .then = .{ .instruction = .x86dectop } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86inctop } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86inc.b" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86inc.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86inc.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86inc.w" } }, + } } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"catpick.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"catpick.w" } }, + .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"crc.w.b.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"crc.w.d.w" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"crc.w.h.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"crc.w.w.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"crcc.w.b.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"crcc.w.d.w" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"crcc.w.h.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"crcc.w.w.w" } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"div.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"div.du" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"div.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"div.wu" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"mod.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"mod.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"mod.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"mod.wu" } }, + } } }, + .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00018000, .then = .{ .instruction = .@"mul.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"mul.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"mulh.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"mulh.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"mulh.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"mulh.wu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"mulw.d.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"mulw.d.wu" } }, + } } }, + .{ .value = 0x00180000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"rotr.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"rotr.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"rotr.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"rotr.w" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"sll.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"sra.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"sra.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"srl.d" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .instruction = .@"sladd.d" } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"sladd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"sladd.wu" } }, + } } }, + } } }, + .{ .value = 0x02c00000, .then = .{ .instruction = .@"addi.d" } }, + .{ .value = 0x02800000, .then = .{ .instruction = .@"addi.w" } }, + .{ .value = 0x03400000, .then = .{ .instruction = .andi } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x00200000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x001c0000, .cases = .{ + .{ .value = 0x001c0000, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000040, .then = .{ .instruction = .armmfflag } }, + .{ .value = 0x00000060, .then = .{ .instruction = .armmtflag } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86mfflag } }, + .{ .value = 0x00000020, .then = .{ .instruction = .x86mtflag } }, + } } }, + .{ .value = 0x00100000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"rcri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"rcri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"rcri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"rcri.d" } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"rotri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"rotri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"rotri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"rotri.d" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"slli.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"slli.w" } }, + } } }, + .{ .value = 0x00080000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"srai.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"srai.w" } }, + } } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"srli.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"srli.w" } }, + } } }, + .{ .value = 0x00140000, .then = .{ .mask = 0x0003001f, .cases = .{ + .{ .value = 0x00000018, .then = .{ .instruction = .@"x86rcli.b" } }, + .{ .value = 0x0001001b, .then = .{ .instruction = .@"x86rcli.d" } }, + .{ .value = 0x00000019, .then = .{ .instruction = .@"x86rcli.h" } }, + .{ .value = 0x0000001a, .then = .{ .instruction = .@"x86rcli.w" } }, + .{ .value = 0x00000010, .then = .{ .instruction = .@"x86rcri.b" } }, + .{ .value = 0x00010013, .then = .{ .instruction = .@"x86rcri.d" } }, + .{ .value = 0x00000011, .then = .{ .instruction = .@"x86rcri.h" } }, + .{ .value = 0x00000012, .then = .{ .instruction = .@"x86rcri.w" } }, + .{ .value = 0x00000014, .then = .{ .instruction = .@"x86rotli.b" } }, + .{ .value = 0x00010017, .then = .{ .instruction = .@"x86rotli.d" } }, + .{ .value = 0x00000015, .then = .{ .instruction = .@"x86rotli.h" } }, + .{ .value = 0x00000016, .then = .{ .instruction = .@"x86rotli.w" } }, + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86rotri.b" } }, + .{ .value = 0x0001000f, .then = .{ .instruction = .@"x86rotri.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86rotri.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86rotri.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86slli.b" } }, + .{ .value = 0x00010003, .then = .{ .instruction = .@"x86slli.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86slli.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86slli.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86srai.b" } }, + .{ .value = 0x0001000b, .then = .{ .instruction = .@"x86srai.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86srai.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86srai.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86srli.b" } }, + .{ .value = 0x00010007, .then = .{ .instruction = .@"x86srli.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86srli.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86srli.w" } }, + } } }, + .{ .value = 0x00180000, .then = .{ .instruction = .x86settag } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"bstrins.w" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"bstrpick.w" } }, + } } }, + } } }, + .{ .value = 0x00800000, .then = .{ .instruction = .@"bstrins.d" } }, + .{ .value = 0x00c00000, .then = .{ .instruction = .@"bstrpick.d" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"cu52i.d" } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x003f8000, .cases = .{ + .{ .value = 0x00140000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00000800, .then = .{ .instruction = .@"fabs.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"fabs.s" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"fclass.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"fclass.s" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"flogb.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"flogb.s" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"fneg.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"fneg.s" } }, + .{ .value = 0x00005800, .then = .{ .instruction = .@"frecip.d" } }, + .{ .value = 0x00005400, .then = .{ .instruction = .@"frecip.s" } }, + .{ .value = 0x00007800, .then = .{ .instruction = .@"frecipe.d" } }, + .{ .value = 0x00007400, .then = .{ .instruction = .@"frecipe.s" } }, + .{ .value = 0x00006800, .then = .{ .instruction = .@"frsqrt.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"frsqrt.s" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"fsqrt.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"fsqrt.s" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"fadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"fadd.s" } }, + .{ .value = 0x00130000, .then = .{ .instruction = .@"fcopysign.d" } }, + .{ .value = 0x00128000, .then = .{ .instruction = .@"fcopysign.s" } }, + .{ .value = 0x00148000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00004800, .then = .{ .instruction = .fcsrrd } }, + .{ .value = 0x00004000, .then = .{ .instruction = .fcsrwr } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"fcvt.ld.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"fcvt.ud.d" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"fmov.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"fmov.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"frsqrte.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"frsqrte.s" } }, + .{ .value = 0x00005400, .then = .{ .instruction = .movfcc2fr } }, + .{ .value = 0x00005c00, .then = .{ .instruction = .movfcc2gr } }, + .{ .value = 0x00005000, .then = .{ .instruction = .movfr2fcc } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"movfr2gr.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"movfr2gr.s" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"movfrh2gr.s" } }, + .{ .value = 0x00005800, .then = .{ .instruction = .movgr2fcc } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"movgr2fr.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"movgr2fr.w" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"movgr2frh.w" } }, + } } }, + .{ .value = 0x00150000, .then = .{ .instruction = .@"fcvt.d.ld" } }, + .{ .value = 0x00190000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002400, .then = .{ .instruction = .@"fcvt.d.s" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"fcvt.s.d" } }, + } } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"fdiv.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"fdiv.s" } }, + .{ .value = 0x001d0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002800, .then = .{ .instruction = .@"ffint.d.l" } }, + .{ .value = 0x00002000, .then = .{ .instruction = .@"ffint.d.w" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"ffint.s.l" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"ffint.s.w" } }, + } } }, + .{ .value = 0x00090000, .then = .{ .instruction = .@"fmax.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"fmax.s" } }, + .{ .value = 0x000d0000, .then = .{ .instruction = .@"fmaxa.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"fmaxa.s" } }, + .{ .value = 0x000b0000, .then = .{ .instruction = .@"fmin.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"fmin.s" } }, + .{ .value = 0x000f0000, .then = .{ .instruction = .@"fmina.d" } }, + .{ .value = 0x000e8000, .then = .{ .instruction = .@"fmina.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"fmul.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"fmul.s" } }, + .{ .value = 0x001e0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00004800, .then = .{ .instruction = .@"frint.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"frint.s" } }, + } } }, + .{ .value = 0x00110000, .then = .{ .instruction = .@"fscaleb.d" } }, + .{ .value = 0x00108000, .then = .{ .instruction = .@"fscaleb.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"fsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"fsub.s" } }, + .{ .value = 0x001b0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002800, .then = .{ .instruction = .@"ftint.l.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"ftint.l.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"ftint.w.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"ftint.w.s" } }, + } } }, + .{ .value = 0x001a0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002800, .then = .{ .instruction = .@"ftintrm.l.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"ftintrm.l.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"ftintrm.w.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"ftintrm.w.s" } }, + .{ .value = 0x00006800, .then = .{ .instruction = .@"ftintrp.l.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"ftintrp.l.s" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"ftintrp.w.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"ftintrp.w.s" } }, + } } }, + .{ .value = 0x001a8000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00006800, .then = .{ .instruction = .@"ftintrne.l.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"ftintrne.l.s" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"ftintrne.w.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"ftintrne.w.s" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"ftintrz.l.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"ftintrz.l.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"ftintrz.w.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"ftintrz.w.s" } }, + } } }, + } } }, + .{ .value = 0x03800000, .then = .{ .instruction = .ori } }, + .{ .value = 0x02000000, .then = .{ .instruction = .slti } }, + .{ .value = 0x02400000, .then = .{ .instruction = .sltui } }, + .{ .value = 0x03c00000, .then = .{ .instruction = .xori } }, + } } }, + .{ .value = 0x10000000, .then = .{ .instruction = .@"addu16i.d" } }, + .{ .value = 0x38000000, .then = .{ .mask = 0x03ff8000, .cases = .{ + .{ .value = 0x005d0000, .then = .{ .instruction = .@"amadd.b" } }, + .{ .value = 0x00618000, .then = .{ .instruction = .@"amadd.d" } }, + .{ .value = 0x005d8000, .then = .{ .instruction = .@"amadd.h" } }, + .{ .value = 0x00610000, .then = .{ .instruction = .@"amadd.w" } }, + .{ .value = 0x005f0000, .then = .{ .instruction = .@"amadd_db.b" } }, + .{ .value = 0x006a8000, .then = .{ .instruction = .@"amadd_db.d" } }, + .{ .value = 0x005f8000, .then = .{ .instruction = .@"amadd_db.h" } }, + .{ .value = 0x006a0000, .then = .{ .instruction = .@"amadd_db.w" } }, + .{ .value = 0x00628000, .then = .{ .instruction = .@"amand.d" } }, + .{ .value = 0x00620000, .then = .{ .instruction = .@"amand.w" } }, + .{ .value = 0x006b8000, .then = .{ .instruction = .@"amand_db.d" } }, + .{ .value = 0x006b0000, .then = .{ .instruction = .@"amand_db.w" } }, + .{ .value = 0x00580000, .then = .{ .instruction = .@"amcas.b" } }, + .{ .value = 0x00598000, .then = .{ .instruction = .@"amcas.d" } }, + .{ .value = 0x00588000, .then = .{ .instruction = .@"amcas.h" } }, + .{ .value = 0x00590000, .then = .{ .instruction = .@"amcas.w" } }, + .{ .value = 0x005a0000, .then = .{ .instruction = .@"amcas_db.b" } }, + .{ .value = 0x005b8000, .then = .{ .instruction = .@"amcas_db.d" } }, + .{ .value = 0x005a8000, .then = .{ .instruction = .@"amcas_db.h" } }, + .{ .value = 0x005b0000, .then = .{ .instruction = .@"amcas_db.w" } }, + .{ .value = 0x00658000, .then = .{ .instruction = .@"ammax.d" } }, + .{ .value = 0x00678000, .then = .{ .instruction = .@"ammax.du" } }, + .{ .value = 0x00650000, .then = .{ .instruction = .@"ammax.w" } }, + .{ .value = 0x00670000, .then = .{ .instruction = .@"ammax.wu" } }, + .{ .value = 0x006e8000, .then = .{ .instruction = .@"ammax_db.d" } }, + .{ .value = 0x00708000, .then = .{ .instruction = .@"ammax_db.du" } }, + .{ .value = 0x006e0000, .then = .{ .instruction = .@"ammax_db.w" } }, + .{ .value = 0x00700000, .then = .{ .instruction = .@"ammax_db.wu" } }, + .{ .value = 0x00668000, .then = .{ .instruction = .@"ammin.d" } }, + .{ .value = 0x00688000, .then = .{ .instruction = .@"ammin.du" } }, + .{ .value = 0x00660000, .then = .{ .instruction = .@"ammin.w" } }, + .{ .value = 0x00680000, .then = .{ .instruction = .@"ammin.wu" } }, + .{ .value = 0x006f8000, .then = .{ .instruction = .@"ammin_db.d" } }, + .{ .value = 0x00718000, .then = .{ .instruction = .@"ammin_db.du" } }, + .{ .value = 0x006f0000, .then = .{ .instruction = .@"ammin_db.w" } }, + .{ .value = 0x00710000, .then = .{ .instruction = .@"ammin_db.wu" } }, + .{ .value = 0x00638000, .then = .{ .instruction = .@"amor.d" } }, + .{ .value = 0x00630000, .then = .{ .instruction = .@"amor.w" } }, + .{ .value = 0x006c8000, .then = .{ .instruction = .@"amor_db.d" } }, + .{ .value = 0x006c0000, .then = .{ .instruction = .@"amor_db.w" } }, + .{ .value = 0x005c0000, .then = .{ .instruction = .@"amswap.b" } }, + .{ .value = 0x00608000, .then = .{ .instruction = .@"amswap.d" } }, + .{ .value = 0x005c8000, .then = .{ .instruction = .@"amswap.h" } }, + .{ .value = 0x00600000, .then = .{ .instruction = .@"amswap.w" } }, + .{ .value = 0x005e0000, .then = .{ .instruction = .@"amswap_db.b" } }, + .{ .value = 0x00698000, .then = .{ .instruction = .@"amswap_db.d" } }, + .{ .value = 0x005e8000, .then = .{ .instruction = .@"amswap_db.h" } }, + .{ .value = 0x00690000, .then = .{ .instruction = .@"amswap_db.w" } }, + .{ .value = 0x00648000, .then = .{ .instruction = .@"amxor.d" } }, + .{ .value = 0x00640000, .then = .{ .instruction = .@"amxor.w" } }, + .{ .value = 0x006d8000, .then = .{ .instruction = .@"amxor_db.d" } }, + .{ .value = 0x006d0000, .then = .{ .instruction = .@"amxor_db.w" } }, + .{ .value = 0x00720000, .then = .{ .instruction = .dbar } }, + .{ .value = 0x00748000, .then = .{ .instruction = .@"fldgt.d" } }, + .{ .value = 0x00740000, .then = .{ .instruction = .@"fldgt.s" } }, + .{ .value = 0x00758000, .then = .{ .instruction = .@"fldle.d" } }, + .{ .value = 0x00750000, .then = .{ .instruction = .@"fldle.s" } }, + .{ .value = 0x00340000, .then = .{ .instruction = .@"fldx.d" } }, + .{ .value = 0x00300000, .then = .{ .instruction = .@"fldx.s" } }, + .{ .value = 0x00768000, .then = .{ .instruction = .@"fstgt.d" } }, + .{ .value = 0x00760000, .then = .{ .instruction = .@"fstgt.s" } }, + .{ .value = 0x00778000, .then = .{ .instruction = .@"fstle.d" } }, + .{ .value = 0x00770000, .then = .{ .instruction = .@"fstle.s" } }, + .{ .value = 0x003c0000, .then = .{ .instruction = .@"fstx.d" } }, + .{ .value = 0x00380000, .then = .{ .instruction = .@"fstx.s" } }, + .{ .value = 0x00728000, .then = .{ .instruction = .ibar } }, + .{ .value = 0x00780000, .then = .{ .instruction = .@"ldgt.b" } }, + .{ .value = 0x00798000, .then = .{ .instruction = .@"ldgt.d" } }, + .{ .value = 0x00788000, .then = .{ .instruction = .@"ldgt.h" } }, + .{ .value = 0x00790000, .then = .{ .instruction = .@"ldgt.w" } }, + .{ .value = 0x007a0000, .then = .{ .instruction = .@"ldle.b" } }, + .{ .value = 0x007b8000, .then = .{ .instruction = .@"ldle.d" } }, + .{ .value = 0x007a8000, .then = .{ .instruction = .@"ldle.h" } }, + .{ .value = 0x007b0000, .then = .{ .instruction = .@"ldle.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ldx.b" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"ldx.bu" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"ldx.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"ldx.h" } }, + .{ .value = 0x00240000, .then = .{ .instruction = .@"ldx.hu" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"ldx.w" } }, + .{ .value = 0x00280000, .then = .{ .instruction = .@"ldx.wu" } }, + .{ .value = 0x00578000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00000800, .then = .{ .instruction = .@"llacq.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"llacq.w" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"screl.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"screl.w" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .instruction = .preldx } }, + .{ .value = 0x00570000, .then = .{ .instruction = .@"sc.q" } }, + .{ .value = 0x007c0000, .then = .{ .instruction = .@"stgt.b" } }, + .{ .value = 0x007d8000, .then = .{ .instruction = .@"stgt.d" } }, + .{ .value = 0x007c8000, .then = .{ .instruction = .@"stgt.h" } }, + .{ .value = 0x007d0000, .then = .{ .instruction = .@"stgt.w" } }, + .{ .value = 0x007e0000, .then = .{ .instruction = .@"stle.b" } }, + .{ .value = 0x007f8000, .then = .{ .instruction = .@"stle.d" } }, + .{ .value = 0x007e8000, .then = .{ .instruction = .@"stle.h" } }, + .{ .value = 0x007f0000, .then = .{ .instruction = .@"stle.w" } }, + .{ .value = 0x00100000, .then = .{ .instruction = .@"stx.b" } }, + .{ .value = 0x001c0000, .then = .{ .instruction = .@"stx.d" } }, + .{ .value = 0x00140000, .then = .{ .instruction = .@"stx.h" } }, + .{ .value = 0x00180000, .then = .{ .instruction = .@"stx.w" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .vldx } }, + .{ .value = 0x00440000, .then = .{ .instruction = .vstx } }, + .{ .value = 0x00480000, .then = .{ .instruction = .xvldx } }, + .{ .value = 0x004c0000, .then = .{ .instruction = .xvstx } }, + } } }, + .{ .value = 0x50000000, .then = .{ .instruction = .b } }, + .{ .value = 0x48000000, .then = .{ .mask = 0x00000300, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .bceqz } }, + .{ .value = 0x00000100, .then = .{ .instruction = .bcnez } }, + .{ .value = 0x00000200, .then = .{ .instruction = .jiscr0 } }, + .{ .value = 0x00000300, .then = .{ .instruction = .jiscr1 } }, + } } }, + .{ .value = 0x58000000, .then = .{ .instruction = .beq } }, + .{ .value = 0x40000000, .then = .{ .instruction = .beqz } }, + .{ .value = 0x60000000, .then = .{ .instruction = .bgt } }, + .{ .value = 0x68000000, .then = .{ .instruction = .bgtu } }, + .{ .value = 0x54000000, .then = .{ .instruction = .bl } }, + .{ .value = 0x64000000, .then = .{ .instruction = .ble } }, + .{ .value = 0x6c000000, .then = .{ .instruction = .bleu } }, + .{ .value = 0x5c000000, .then = .{ .instruction = .bne } }, + .{ .value = 0x44000000, .then = .{ .instruction = .bnez } }, + .{ .value = 0x04000000, .then = .{ .mask = 0x03000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .mask = 0x00c00000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .cacop } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x003c0000, .cases = .{ + .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00003800, .then = .{ .instruction = .eret } }, + .{ .value = 0x00002000, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbclr } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbclr } }, + } } }, + .{ .value = 0x00003400, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbfill } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbfill } }, + } } }, + .{ .value = 0x00002400, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbflush } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbflush } }, + } } }, + .{ .value = 0x00002c00, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbrd } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbrd } }, + } } }, + .{ .value = 0x00002800, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbsrch } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbsrch } }, + } } }, + .{ .value = 0x00003000, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbwr } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbwr } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"iocsrrd.b" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"iocsrrd.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"iocsrrd.h" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"iocsrrd.w" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"iocsrwr.b" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"iocsrwr.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"iocsrwr.h" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"iocsrwr.w" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .idle } }, + .{ .value = 0x00018000, .then = .{ .instruction = .tlbinv } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xxx.unknown.1" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .lddir } }, + .{ .value = 0x00040000, .then = .{ .instruction = .ldpte } }, + } } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .csrrd } }, + .{ .value = 0x00000020, .then = .{ .instruction = .csrwr } }, + .{ .then = .{ .instruction = .csrxchg } }, + } } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .gcsrrd } }, + .{ .value = 0x00000020, .then = .{ .instruction = .gcsrwr } }, + .{ .then = .{ .instruction = .gcsrxchg } }, + } } }, + } } }, + .{ .value = 0x14000000, .then = .{ .mask = 0x02000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .instruction = .@"cu32i.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"lu12i.w" } }, + } } }, + .{ .value = 0x0c000000, .then = .{ .mask = 0x03f00000, .cases = .{ + .{ .value = 0x00200000, .then = .{ .mask = 0x000f8018, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"fcmp.caf.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"fcmp.ceq.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"fcmp.cle.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"fcmp.clt.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"fcmp.cne.d" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"fcmp.cor.d" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"fcmp.cueq.d" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"fcmp.cule.d" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"fcmp.cult.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"fcmp.cun.d" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"fcmp.cune.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"fcmp.saf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"fcmp.seq.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"fcmp.sle.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"fcmp.slt.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"fcmp.sne.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"fcmp.sor.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"fcmp.sueq.d" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"fcmp.sule.d" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"fcmp.sult.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"fcmp.sun.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"fcmp.sune.d" } }, + } } }, + .{ .value = 0x00100000, .then = .{ .mask = 0x000f8018, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"fcmp.caf.s" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"fcmp.ceq.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"fcmp.cle.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"fcmp.clt.s" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"fcmp.cne.s" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"fcmp.cor.s" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"fcmp.cueq.s" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"fcmp.cule.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"fcmp.cult.s" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"fcmp.cun.s" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"fcmp.cune.s" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"fcmp.saf.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"fcmp.seq.s" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"fcmp.sle.s" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"fcmp.slt.s" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"fcmp.sne.s" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"fcmp.sor.s" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"fcmp.sueq.s" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"fcmp.sule.s" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"fcmp.sult.s" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"fcmp.sun.s" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"fcmp.sune.s" } }, + } } }, + .{ .value = 0x01000000, .then = .{ .instruction = .fsel } }, + .{ .value = 0x01100000, .then = .{ .instruction = .@"vbitsel.v" } }, + .{ .value = 0x00600000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vfcmp.caf.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcmp.ceq.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfcmp.cle.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfcmp.clt.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"vfcmp.cne.d" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"vfcmp.cor.d" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"vfcmp.cueq.d" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"vfcmp.cule.d" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"vfcmp.cult.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"vfcmp.cun.d" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"vfcmp.cune.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfcmp.saf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcmp.seq.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vfcmp.sle.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vfcmp.slt.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"vfcmp.sne.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"vfcmp.sor.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"vfcmp.sueq.d" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"vfcmp.sule.d" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"vfcmp.sult.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"vfcmp.sun.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"vfcmp.sune.d" } }, + } } }, + .{ .value = 0x00500000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vfcmp.caf.s" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcmp.ceq.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfcmp.cle.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfcmp.clt.s" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"vfcmp.cne.s" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"vfcmp.cor.s" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"vfcmp.cueq.s" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"vfcmp.cule.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"vfcmp.cult.s" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"vfcmp.cun.s" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"vfcmp.cune.s" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfcmp.saf.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcmp.seq.s" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vfcmp.sle.s" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vfcmp.slt.s" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"vfcmp.sne.s" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"vfcmp.sor.s" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"vfcmp.sueq.s" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"vfcmp.sule.s" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"vfcmp.sult.s" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"vfcmp.sun.s" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"vfcmp.sune.s" } }, + } } }, + .{ .value = 0x01500000, .then = .{ .instruction = .@"vshuf.b" } }, + .{ .value = 0x01200000, .then = .{ .instruction = .@"xvbitsel.v" } }, + .{ .value = 0x00a00000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvfcmp.caf.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcmp.ceq.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfcmp.cle.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfcmp.clt.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"xvfcmp.cne.d" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"xvfcmp.cor.d" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"xvfcmp.cueq.d" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"xvfcmp.cule.d" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"xvfcmp.cult.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"xvfcmp.cun.d" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"xvfcmp.cune.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfcmp.saf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcmp.seq.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfcmp.sle.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvfcmp.slt.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"xvfcmp.sne.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"xvfcmp.sor.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"xvfcmp.sueq.d" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"xvfcmp.sule.d" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"xvfcmp.sult.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"xvfcmp.sun.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"xvfcmp.sune.d" } }, + } } }, + .{ .value = 0x00900000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvfcmp.caf.s" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcmp.ceq.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfcmp.cle.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfcmp.clt.s" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"xvfcmp.cne.s" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"xvfcmp.cor.s" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"xvfcmp.cueq.s" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"xvfcmp.cule.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"xvfcmp.cult.s" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"xvfcmp.cun.s" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"xvfcmp.cune.s" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfcmp.saf.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcmp.seq.s" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfcmp.sle.s" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvfcmp.slt.s" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"xvfcmp.sne.s" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"xvfcmp.sor.s" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"xvfcmp.sueq.s" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"xvfcmp.sule.s" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"xvfcmp.sult.s" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"xvfcmp.sun.s" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"xvfcmp.sune.s" } }, + } } }, + .{ .value = 0x01600000, .then = .{ .instruction = .@"xvshuf.b" } }, + } } }, + .{ .value = 0x28000000, .then = .{ .mask = 0x03c00000, .cases = .{ + .{ .value = 0x03800000, .then = .{ .instruction = .@"fld.d" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"fld.s" } }, + .{ .value = 0x03c00000, .then = .{ .instruction = .@"fst.d" } }, + .{ .value = 0x03400000, .then = .{ .instruction = .@"fst.s" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ld.b" } }, + .{ .value = 0x02000000, .then = .{ .instruction = .@"ld.bu" } }, + .{ .value = 0x00c00000, .then = .{ .instruction = .@"ld.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"ld.h" } }, + .{ .value = 0x02400000, .then = .{ .instruction = .@"ld.hu" } }, + .{ .value = 0x00800000, .then = .{ .instruction = .@"ld.w" } }, + .{ .value = 0x02800000, .then = .{ .instruction = .@"ld.wu" } }, + .{ .value = 0x02c00000, .then = .{ .instruction = .preld } }, + .{ .value = 0x01000000, .then = .{ .instruction = .@"st.b" } }, + .{ .value = 0x01c00000, .then = .{ .instruction = .@"st.d" } }, + .{ .value = 0x01400000, .then = .{ .instruction = .@"st.h" } }, + .{ .value = 0x01800000, .then = .{ .instruction = .@"st.w" } }, + } } }, + .{ .value = 0x08000000, .then = .{ .mask = 0x03f00000, .cases = .{ + .{ .value = 0x00200000, .then = .{ .instruction = .@"fmadd.d" } }, + .{ .value = 0x00100000, .then = .{ .instruction = .@"fmadd.s" } }, + .{ .value = 0x00600000, .then = .{ .instruction = .@"fmsub.d" } }, + .{ .value = 0x00500000, .then = .{ .instruction = .@"fmsub.s" } }, + .{ .value = 0x00a00000, .then = .{ .instruction = .@"fnmadd.d" } }, + .{ .value = 0x00900000, .then = .{ .instruction = .@"fnmadd.s" } }, + .{ .value = 0x00e00000, .then = .{ .instruction = .@"fnmsub.d" } }, + .{ .value = 0x00d00000, .then = .{ .instruction = .@"fnmsub.s" } }, + .{ .value = 0x01200000, .then = .{ .instruction = .@"vfmadd.d" } }, + .{ .value = 0x01100000, .then = .{ .instruction = .@"vfmadd.s" } }, + .{ .value = 0x01600000, .then = .{ .instruction = .@"vfmsub.d" } }, + .{ .value = 0x01500000, .then = .{ .instruction = .@"vfmsub.s" } }, + .{ .value = 0x01a00000, .then = .{ .instruction = .@"vfnmadd.d" } }, + .{ .value = 0x01900000, .then = .{ .instruction = .@"vfnmadd.s" } }, + .{ .value = 0x01e00000, .then = .{ .instruction = .@"vfnmsub.d" } }, + .{ .value = 0x01d00000, .then = .{ .instruction = .@"vfnmsub.s" } }, + .{ .value = 0x02200000, .then = .{ .instruction = .@"xvfmadd.d" } }, + .{ .value = 0x02100000, .then = .{ .instruction = .@"xvfmadd.s" } }, + .{ .value = 0x02600000, .then = .{ .instruction = .@"xvfmsub.d" } }, + .{ .value = 0x02500000, .then = .{ .instruction = .@"xvfmsub.s" } }, + .{ .value = 0x02a00000, .then = .{ .instruction = .@"xvfnmadd.d" } }, + .{ .value = 0x02900000, .then = .{ .instruction = .@"xvfnmadd.s" } }, + .{ .value = 0x02e00000, .then = .{ .instruction = .@"xvfnmsub.d" } }, + .{ .value = 0x02d00000, .then = .{ .instruction = .@"xvfnmsub.s" } }, + } } }, + .{ .value = 0x4c000000, .then = .{ .instruction = .jirl } }, + .{ .value = 0x2c000000, .then = .{ .mask = 0x03c00000, .cases = .{ + .{ .value = 0x02800000, .then = .{ .instruction = .@"ldl.d" } }, + .{ .value = 0x02000000, .then = .{ .instruction = .@"ldl.w" } }, + .{ .value = 0x02c00000, .then = .{ .instruction = .@"ldr.d" } }, + .{ .value = 0x02400000, .then = .{ .instruction = .@"ldr.w" } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"stl.d" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"stl.w" } }, + .{ .value = 0x03c00000, .then = .{ .instruction = .@"str.d" } }, + .{ .value = 0x03400000, .then = .{ .instruction = .@"str.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .vld } }, + .{ .value = 0x00400000, .then = .{ .instruction = .vst } }, + .{ .value = 0x00800000, .then = .{ .instruction = .xvld } }, + .{ .value = 0x00c00000, .then = .{ .instruction = .xvst } }, + } } }, + .{ .value = 0x24000000, .then = .{ .mask = 0x03000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .instruction = .@"ldox4.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ldox4.w" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"stox4.d" } }, + .{ .value = 0x01000000, .then = .{ .instruction = .@"stox4.w" } }, + } } }, + .{ .value = 0x20000000, .then = .{ .mask = 0x03000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .instruction = .@"ll.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ll.w" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"sc.d" } }, + .{ .value = 0x01000000, .then = .{ .instruction = .@"sc.w" } }, + } } }, + .{ .value = 0x1c000000, .then = .{ .mask = 0x02000000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .pcaddu12i } }, + .{ .value = 0x02000000, .then = .{ .instruction = .pcaddu18i } }, + } } }, + .{ .value = 0x18000000, .then = .{ .mask = 0x02000000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .pcaddu2i } }, + .{ .value = 0x02000000, .then = .{ .instruction = .pcalau12i } }, + } } }, + .{ .value = 0x70000000, .then = .{ .mask = 0x03fc0000, .cases = .{ + .{ .value = 0x00600000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vabsd.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vabsd.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vabsd.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vabsd.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vabsd.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vabsd.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vabsd.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vabsd.wu" } }, + } } }, + .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vadd.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslt.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vslt.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslt.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslt.wu" } }, + } } }, + .{ .value = 0x012c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vadd.q" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsigncov.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsigncov.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsigncov.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsigncov.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsub.q" } }, + } } }, + .{ .value = 0x005c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vadda.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vadda.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vadda.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vadda.w" } }, + } } }, + .{ .value = 0x02880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddi.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddi.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddi.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddi.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslti.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vslti.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslti.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslti.wu" } }, + } } }, + .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.h" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.hu" } }, + } } }, + .{ .value = 0x003c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.hu.h" } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwod.w.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwev.w.h" } }, + } } }, + .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwod.w.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwev.w.hu" } }, + } } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vaddwod.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vaddwod.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vaddwod.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x01240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vand.v" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vnor.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vor.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vxor.v" } }, + } } }, + .{ .value = 0x03d00000, .then = .{ .instruction = .@"vandi.b" } }, + .{ .value = 0x01280000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vandn.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfrstp.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vfrstp.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vorn.v" } }, + } } }, + .{ .value = 0x00640000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vavg.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vavg.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vavg.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vavg.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vavg.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vavg.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vavg.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vavg.wu" } }, + } } }, + .{ .value = 0x00680000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vavgr.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vavgr.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vavgr.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vavgr.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vavgr.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vavgr.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vavgr.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vavgr.wu" } }, + } } }, + .{ .value = 0x010c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitclr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vbitclr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitclr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitclr.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vbitset.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vbitset.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vbitset.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vbitset.w" } }, + } } }, + .{ .value = 0x03100000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitclri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitclri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitclri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitclri.d" } }, + } } }, + .{ .value = 0x01100000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitrev.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vbitrev.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitrev.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitrev.w" } }, + } } }, + .{ .value = 0x03180000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitrevi.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitrevi.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitrevi.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitrevi.d" } }, + } } }, + .{ .value = 0x03c40000, .then = .{ .instruction = .@"vbitseli.b" } }, + .{ .value = 0x03140000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitseti.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitseti.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitseti.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitseti.d" } }, + } } }, + .{ .value = 0x028c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vbsll.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vbsrl.v" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubi.wu" } }, + } } }, + .{ .value = 0x029c0000, .then = .{ .mask = 0x0003fc00, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vclo.b" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"vclo.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"vclo.h" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"vclo.w" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"vclz.b" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"vclz.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"vclz.h" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"vclz.w" } }, + .{ .value = 0x0002e800, .then = .{ .instruction = .@"vexth.d.w" } }, + .{ .value = 0x0002f800, .then = .{ .instruction = .@"vexth.du.wu" } }, + .{ .value = 0x0002e000, .then = .{ .instruction = .@"vexth.h.b" } }, + .{ .value = 0x0002f000, .then = .{ .instruction = .@"vexth.hu.bu" } }, + .{ .value = 0x0002ec00, .then = .{ .instruction = .@"vexth.q.d" } }, + .{ .value = 0x0002fc00, .then = .{ .instruction = .@"vexth.qu.du" } }, + .{ .value = 0x0002e400, .then = .{ .instruction = .@"vexth.w.h" } }, + .{ .value = 0x0002f400, .then = .{ .instruction = .@"vexth.wu.hu" } }, + .{ .value = 0x0000d800, .then = .{ .instruction = .@"vfclass.d" } }, + .{ .value = 0x0000d400, .then = .{ .instruction = .@"vfclass.s" } }, + .{ .value = 0x0001f400, .then = .{ .instruction = .@"vfcvth.d.s" } }, + .{ .value = 0x0001ec00, .then = .{ .instruction = .@"vfcvth.s.h" } }, + .{ .value = 0x0001f000, .then = .{ .instruction = .@"vfcvtl.d.s" } }, + .{ .value = 0x0001e800, .then = .{ .instruction = .@"vfcvtl.s.h" } }, + .{ .value = 0x00020800, .then = .{ .instruction = .@"vffint.d.l" } }, + .{ .value = 0x00020c00, .then = .{ .instruction = .@"vffint.d.lu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vffint.s.w" } }, + .{ .value = 0x00020400, .then = .{ .instruction = .@"vffint.s.wu" } }, + .{ .value = 0x00021400, .then = .{ .instruction = .@"vffinth.d.w" } }, + .{ .value = 0x00021000, .then = .{ .instruction = .@"vffintl.d.w" } }, + .{ .value = 0x0000c800, .then = .{ .instruction = .@"vflogb.d" } }, + .{ .value = 0x0000c400, .then = .{ .instruction = .@"vflogb.s" } }, + .{ .value = 0x0000f800, .then = .{ .instruction = .@"vfrecip.d" } }, + .{ .value = 0x0000f400, .then = .{ .instruction = .@"vfrecip.s" } }, + .{ .value = 0x00011800, .then = .{ .instruction = .@"vfrecipe.d" } }, + .{ .value = 0x00011400, .then = .{ .instruction = .@"vfrecipe.s" } }, + .{ .value = 0x00013800, .then = .{ .instruction = .@"vfrint.d" } }, + .{ .value = 0x00013400, .then = .{ .instruction = .@"vfrint.s" } }, + .{ .value = 0x00014800, .then = .{ .instruction = .@"vfrintrm.d" } }, + .{ .value = 0x00014400, .then = .{ .instruction = .@"vfrintrm.s" } }, + .{ .value = 0x00017800, .then = .{ .instruction = .@"vfrintrne.d" } }, + .{ .value = 0x00017400, .then = .{ .instruction = .@"vfrintrne.s" } }, + .{ .value = 0x00015800, .then = .{ .instruction = .@"vfrintrp.d" } }, + .{ .value = 0x00015400, .then = .{ .instruction = .@"vfrintrp.s" } }, + .{ .value = 0x00016800, .then = .{ .instruction = .@"vfrintrz.d" } }, + .{ .value = 0x00016400, .then = .{ .instruction = .@"vfrintrz.s" } }, + .{ .value = 0x00010800, .then = .{ .instruction = .@"vfrsqrt.d" } }, + .{ .value = 0x00010400, .then = .{ .instruction = .@"vfrsqrt.s" } }, + .{ .value = 0x00012800, .then = .{ .instruction = .@"vfrsqrte.d" } }, + .{ .value = 0x00012400, .then = .{ .instruction = .@"vfrsqrte.s" } }, + .{ .value = 0x0000e800, .then = .{ .instruction = .@"vfsqrt.d" } }, + .{ .value = 0x0000e400, .then = .{ .instruction = .@"vfsqrt.s" } }, + .{ .value = 0x00023400, .then = .{ .instruction = .@"vftint.l.d" } }, + .{ .value = 0x00025c00, .then = .{ .instruction = .@"vftint.lu.d" } }, + .{ .value = 0x00023000, .then = .{ .instruction = .@"vftint.w.s" } }, + .{ .value = 0x00025800, .then = .{ .instruction = .@"vftint.wu.s" } }, + .{ .value = 0x00028400, .then = .{ .instruction = .@"vftinth.l.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vftintl.l.s" } }, + .{ .value = 0x00023c00, .then = .{ .instruction = .@"vftintrm.l.d" } }, + .{ .value = 0x00023800, .then = .{ .instruction = .@"vftintrm.w.s" } }, + .{ .value = 0x00028c00, .then = .{ .instruction = .@"vftintrmh.l.s" } }, + .{ .value = 0x00028800, .then = .{ .instruction = .@"vftintrml.l.s" } }, + .{ .value = 0x00025400, .then = .{ .instruction = .@"vftintrne.l.d" } }, + .{ .value = 0x00025000, .then = .{ .instruction = .@"vftintrne.w.s" } }, + .{ .value = 0x0002a400, .then = .{ .instruction = .@"vftintrneh.l.s" } }, + .{ .value = 0x0002a000, .then = .{ .instruction = .@"vftintrnel.l.s" } }, + .{ .value = 0x00024400, .then = .{ .instruction = .@"vftintrp.l.d" } }, + .{ .value = 0x00024000, .then = .{ .instruction = .@"vftintrp.w.s" } }, + .{ .value = 0x00029400, .then = .{ .instruction = .@"vftintrph.l.s" } }, + .{ .value = 0x00029000, .then = .{ .instruction = .@"vftintrpl.l.s" } }, + .{ .value = 0x00024c00, .then = .{ .instruction = .@"vftintrz.l.d" } }, + .{ .value = 0x00027400, .then = .{ .instruction = .@"vftintrz.lu.d" } }, + .{ .value = 0x00024800, .then = .{ .instruction = .@"vftintrz.w.s" } }, + .{ .value = 0x00027000, .then = .{ .instruction = .@"vftintrz.wu.s" } }, + .{ .value = 0x00029c00, .then = .{ .instruction = .@"vftintrzh.l.s" } }, + .{ .value = 0x00029800, .then = .{ .instruction = .@"vftintrzl.l.s" } }, + .{ .value = 0x00005000, .then = .{ .instruction = .@"vmskgez.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vmskltz.b" } }, + .{ .value = 0x00004c00, .then = .{ .instruction = .@"vmskltz.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"vmskltz.h" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"vmskltz.w" } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"vmsknz.b" } }, + .{ .value = 0x00003000, .then = .{ .instruction = .@"vneg.b" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"vneg.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"vneg.h" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"vneg.w" } }, + .{ .value = 0x00002000, .then = .{ .instruction = .@"vpcnt.b" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"vpcnt.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"vpcnt.h" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"vpcnt.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vreplgr2vr.b" } }, + .{ .value = 0x00030c00, .then = .{ .instruction = .@"vreplgr2vr.d" } }, + .{ .value = 0x00030400, .then = .{ .instruction = .@"vreplgr2vr.h" } }, + .{ .value = 0x00030800, .then = .{ .instruction = .@"vreplgr2vr.w" } }, + .{ .value = 0x0000b000, .then = .{ .instruction = .@"vsetallnez.b" } }, + .{ .value = 0x0000bc00, .then = .{ .instruction = .@"vsetallnez.d" } }, + .{ .value = 0x0000b400, .then = .{ .instruction = .@"vsetallnez.h" } }, + .{ .value = 0x0000b800, .then = .{ .instruction = .@"vsetallnez.w" } }, + .{ .value = 0x0000a000, .then = .{ .instruction = .@"vsetanyeqz.b" } }, + .{ .value = 0x0000ac00, .then = .{ .instruction = .@"vsetanyeqz.d" } }, + .{ .value = 0x0000a400, .then = .{ .instruction = .@"vsetanyeqz.h" } }, + .{ .value = 0x0000a800, .then = .{ .instruction = .@"vsetanyeqz.w" } }, + .{ .value = 0x00009800, .then = .{ .instruction = .@"vseteqz.v" } }, + .{ .value = 0x00009c00, .then = .{ .instruction = .@"vsetnez.v" } }, + } } }, + .{ .value = 0x00e00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vdiv.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vdiv.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vdiv.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vdiv.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmod.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmod.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmod.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmod.w" } }, + } } }, + .{ .value = 0x00e40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vdiv.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vdiv.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vdiv.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vdiv.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmod.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmod.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmod.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmod.wu" } }, + } } }, + .{ .value = 0x03080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vextl.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsllwil.d.w" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsllwil.h.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsllwil.w.h" } }, + } } }, + } } }, + .{ .value = 0x030c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vextl.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsllwil.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsllwil.hu.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsllwil.wu.hu" } }, + } } }, + } } }, + .{ .value = 0x038c0000, .then = .{ .instruction = .@"vextrins.b" } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"vextrins.d" } }, + .{ .value = 0x03880000, .then = .{ .instruction = .@"vextrins.h" } }, + .{ .value = 0x03840000, .then = .{ .instruction = .@"vextrins.w" } }, + .{ .value = 0x01300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfadd.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfsub.s" } }, + } } }, + .{ .value = 0x01440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcvt.h.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcvt.s.d" } }, + } } }, + .{ .value = 0x01380000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfdiv.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfdiv.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmul.s" } }, + } } }, + .{ .value = 0x01480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vffint.s.l" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vftint.w.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vftintrm.w.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vftintrne.w.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vftintrp.w.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vftintrz.w.d" } }, + } } }, + .{ .value = 0x013c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmax.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfmin.s" } }, + } } }, + .{ .value = 0x01400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmaxa.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmaxa.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfmina.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfmina.s" } }, + } } }, + .{ .value = 0x02980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfrstpi.b" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfrstpi.h" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmepatmsk.v" } }, + } } }, + .{ .value = 0x00540000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vhaddw.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vhaddw.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vhaddw.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vhaddw.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vhsubw.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vhsubw.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vhsubw.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vhsubw.w.h" } }, + } } }, + .{ .value = 0x00580000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vhaddw.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vhaddw.hu.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vhaddw.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vhaddw.wu.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vhsubw.du.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vhsubw.hu.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vhsubw.qu.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vhsubw.wu.hu" } }, + } } }, + .{ .value = 0x011c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vilvh.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vilvh.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vilvh.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vilvh.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vpickev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vpickev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vpickev.w" } }, + } } }, + .{ .value = 0x01180000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vilvl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vilvl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vilvl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vilvl.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpackod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vpackod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vpackod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vpackod.w" } }, + } } }, + .{ .value = 0x02e80000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vinsgr2vr.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vinsgr2vr.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vinsgr2vr.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vinsgr2vr.h" } }, + } } }, + } } }, + .{ .value = 0x03e00000, .then = .{ .instruction = .vldi } }, + .{ .value = 0x00a80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmadd.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmadd.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmadd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmsub.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmsub.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmsub.w" } }, + } } }, + .{ .value = 0x00ac0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.h" } }, + } } }, + .{ .value = 0x00b40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.hu" } }, + } } }, + .{ .value = 0x00bc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x00700000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmax.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmax.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmax.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmin.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmin.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmin.w" } }, + } } }, + .{ .value = 0x00740000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmax.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmax.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmax.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmax.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmin.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmin.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmin.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmin.wu" } }, + } } }, + .{ .value = 0x02900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaxi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaxi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaxi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaxi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmini.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmini.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmini.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmini.w" } }, + } } }, + .{ .value = 0x02940000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaxi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaxi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaxi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaxi.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmini.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmini.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmini.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmini.wu" } }, + } } }, + .{ .value = 0x00840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmuh.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmuh.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmuh.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmuh.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmul.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmul.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmul.w" } }, + } } }, + .{ .value = 0x00880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmuh.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmuh.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmuh.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmuh.wu" } }, + } } }, + .{ .value = 0x00900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.h" } }, + } } }, + .{ .value = 0x00980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.hu" } }, + } } }, + .{ .value = 0x00a00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.hu.h" } }, + } } }, + .{ .value = 0x03dc0000, .then = .{ .instruction = .@"vnori.b" } }, + .{ .value = 0x03d40000, .then = .{ .instruction = .@"vori.b" } }, + .{ .value = 0x01140000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vpackev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpackev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vpackev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vpackev.w" } }, + } } }, + .{ .value = 0x03e40000, .then = .{ .instruction = .@"vpermi.w" } }, + .{ .value = 0x01200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vpickod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vpickod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vpickod.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vreplve.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vreplve.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vreplve.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vreplve.w" } }, + } } }, + .{ .value = 0x02ec0000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickve2gr.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vpickve2gr.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.h" } }, + } } }, + } } }, + .{ .value = 0x02f00000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickve2gr.bu" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vpickve2gr.du" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.wu" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.hu" } }, + } } }, + } } }, + .{ .value = 0x02f40000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vreplvei.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vreplvei.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vreplvei.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vreplvei.h" } }, + } } }, + } } }, + .{ .value = 0x00ec0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vrotr.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vrotr.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vrotr.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vrotr.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsra.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsra.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsra.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsra.w" } }, + } } }, + .{ .value = 0x02a00000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vrotri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vrotri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vrotri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vrotri.d" } }, + } } }, + .{ .value = 0x00440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsadd.w" } }, + } } }, + .{ .value = 0x00480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsadd.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsadd.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsadd.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsadd.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssub.w" } }, + } } }, + .{ .value = 0x03240000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsat.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsat.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsat.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsat.d" } }, + } } }, + .{ .value = 0x03280000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsat.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsat.hu" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsat.wu" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsat.du" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vseq.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vseq.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vseq.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vseq.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsle.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsle.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsle.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsle.w" } }, + } } }, + .{ .value = 0x02800000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vseqi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vseqi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vseqi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vseqi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vslei.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vslei.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vslei.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vslei.w" } }, + } } }, + .{ .value = 0x01780000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vshuf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vshuf.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vshuf.w" } }, + } } }, + .{ .value = 0x03900000, .then = .{ .instruction = .@"vshuf4i.b" } }, + .{ .value = 0x039c0000, .then = .{ .instruction = .@"vshuf4i.d" } }, + .{ .value = 0x03940000, .then = .{ .instruction = .@"vshuf4i.h" } }, + .{ .value = 0x03980000, .then = .{ .instruction = .@"vshuf4i.w" } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsle.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsle.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsle.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsle.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vslt.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vslt.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vslt.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vslt.w" } }, + } } }, + .{ .value = 0x02840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslei.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vslei.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslei.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslei.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vslti.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vslti.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vslti.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vslti.w" } }, + } } }, + .{ .value = 0x00e80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsll.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsll.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsll.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsll.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrl.w" } }, + } } }, + .{ .value = 0x032c0000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vslli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslli.d" } }, + } } }, + .{ .value = 0x03340000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrai.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrai.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrai.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrai.d" } }, + } } }, + .{ .value = 0x00f40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrln.w.d" } }, + } } }, + .{ .value = 0x03580000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrani.d.q" } }, + } } }, + .{ .value = 0x00f00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrar.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrar.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrar.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrar.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrlr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlr.w" } }, + } } }, + .{ .value = 0x02a80000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrari.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrari.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrari.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrari.d" } }, + } } }, + .{ .value = 0x00f80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrlrn.w.d" } }, + } } }, + .{ .value = 0x035c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrarni.d.q" } }, + } } }, + .{ .value = 0x03300000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrli.d" } }, + } } }, + .{ .value = 0x03400000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrlni.d.q" } }, + } } }, + .{ .value = 0x02a40000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrlri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlri.d" } }, + } } }, + .{ .value = 0x03440000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrlrni.d.q" } }, + } } }, + .{ .value = 0x00fc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrln.w.d" } }, + } } }, + .{ .value = 0x01040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssran.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssran.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssran.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrln.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrln.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrln.wu.d" } }, + } } }, + .{ .value = 0x03600000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrani.d.q" } }, + } } }, + .{ .value = 0x03640000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrani.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrani.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrani.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrani.du.q" } }, + } } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrlrn.w.d" } }, + } } }, + .{ .value = 0x01080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssrarn.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssrarn.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssrarn.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrn.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrn.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrlrn.wu.d" } }, + } } }, + .{ .value = 0x03680000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrarni.d.q" } }, + } } }, + .{ .value = 0x036c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrarni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrarni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrarni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrarni.du.q" } }, + } } }, + .{ .value = 0x03480000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlni.d.q" } }, + } } }, + .{ .value = 0x034c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlni.du.q" } }, + } } }, + .{ .value = 0x03500000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlrni.d.q" } }, + } } }, + .{ .value = 0x03540000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlrni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlrni.du.q" } }, + } } }, + .{ .value = 0x004c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssub.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssub.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssub.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssub.wu" } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsub.w" } }, + } } }, + .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwod.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwod.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwod.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwod.w.h" } }, + } } }, + .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwod.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwod.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwod.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwod.w.hu" } }, + } } }, + .{ .value = 0x03d80000, .then = .{ .instruction = .@"vxori.b" } }, + } } }, + .{ .value = 0x74000000, .then = .{ .mask = 0x03fc0000, .cases = .{ + .{ .value = 0x029c0000, .then = .{ .mask = 0x0003fc00, .cases = .{ + .{ .value = 0x00031800, .then = .{ .instruction = .@"vext2xv.d.b" } }, + .{ .value = 0x00032000, .then = .{ .instruction = .@"vext2xv.d.h" } }, + .{ .value = 0x00032400, .then = .{ .instruction = .@"vext2xv.d.w" } }, + .{ .value = 0x00033000, .then = .{ .instruction = .@"vext2xv.du.bu" } }, + .{ .value = 0x00033800, .then = .{ .instruction = .@"vext2xv.du.hu" } }, + .{ .value = 0x00033c00, .then = .{ .instruction = .@"vext2xv.du.wu" } }, + .{ .value = 0x00031000, .then = .{ .instruction = .@"vext2xv.h.b" } }, + .{ .value = 0x00032800, .then = .{ .instruction = .@"vext2xv.hu.bu" } }, + .{ .value = 0x00031400, .then = .{ .instruction = .@"vext2xv.w.b" } }, + .{ .value = 0x00031c00, .then = .{ .instruction = .@"vext2xv.w.h" } }, + .{ .value = 0x00032c00, .then = .{ .instruction = .@"vext2xv.wu.bu" } }, + .{ .value = 0x00033400, .then = .{ .instruction = .@"vext2xv.wu.hu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvclo.b" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"xvclo.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"xvclo.h" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"xvclo.w" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"xvclz.b" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"xvclz.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"xvclz.h" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"xvclz.w" } }, + .{ .value = 0x0002e800, .then = .{ .instruction = .@"xvexth.d.w" } }, + .{ .value = 0x0002f800, .then = .{ .instruction = .@"xvexth.du.wu" } }, + .{ .value = 0x0002e000, .then = .{ .instruction = .@"xvexth.h.b" } }, + .{ .value = 0x0002f000, .then = .{ .instruction = .@"xvexth.hu.bu" } }, + .{ .value = 0x0002ec00, .then = .{ .instruction = .@"xvexth.q.d" } }, + .{ .value = 0x0002fc00, .then = .{ .instruction = .@"xvexth.qu.du" } }, + .{ .value = 0x0002e400, .then = .{ .instruction = .@"xvexth.w.h" } }, + .{ .value = 0x0002f400, .then = .{ .instruction = .@"xvexth.wu.hu" } }, + .{ .value = 0x0000d800, .then = .{ .instruction = .@"xvfclass.d" } }, + .{ .value = 0x0000d400, .then = .{ .instruction = .@"xvfclass.s" } }, + .{ .value = 0x0001f400, .then = .{ .instruction = .@"xvfcvth.d.s" } }, + .{ .value = 0x0001ec00, .then = .{ .instruction = .@"xvfcvth.s.h" } }, + .{ .value = 0x0001f000, .then = .{ .instruction = .@"xvfcvtl.d.s" } }, + .{ .value = 0x0001e800, .then = .{ .instruction = .@"xvfcvtl.s.h" } }, + .{ .value = 0x00020800, .then = .{ .instruction = .@"xvffint.d.l" } }, + .{ .value = 0x00020c00, .then = .{ .instruction = .@"xvffint.d.lu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvffint.s.w" } }, + .{ .value = 0x00020400, .then = .{ .instruction = .@"xvffint.s.wu" } }, + .{ .value = 0x00021400, .then = .{ .instruction = .@"xvffinth.d.w" } }, + .{ .value = 0x00021000, .then = .{ .instruction = .@"xvffintl.d.w" } }, + .{ .value = 0x0000c800, .then = .{ .instruction = .@"xvflogb.d" } }, + .{ .value = 0x0000c400, .then = .{ .instruction = .@"xvflogb.s" } }, + .{ .value = 0x0000f800, .then = .{ .instruction = .@"xvfrecip.d" } }, + .{ .value = 0x0000f400, .then = .{ .instruction = .@"xvfrecip.s" } }, + .{ .value = 0x00011800, .then = .{ .instruction = .@"xvfrecipe.d" } }, + .{ .value = 0x00011400, .then = .{ .instruction = .@"xvfrecipe.s" } }, + .{ .value = 0x00013800, .then = .{ .instruction = .@"xvfrint.d" } }, + .{ .value = 0x00013400, .then = .{ .instruction = .@"xvfrint.s" } }, + .{ .value = 0x00014800, .then = .{ .instruction = .@"xvfrintrm.d" } }, + .{ .value = 0x00014400, .then = .{ .instruction = .@"xvfrintrm.s" } }, + .{ .value = 0x00017800, .then = .{ .instruction = .@"xvfrintrne.d" } }, + .{ .value = 0x00017400, .then = .{ .instruction = .@"xvfrintrne.s" } }, + .{ .value = 0x00015800, .then = .{ .instruction = .@"xvfrintrp.d" } }, + .{ .value = 0x00015400, .then = .{ .instruction = .@"xvfrintrp.s" } }, + .{ .value = 0x00016800, .then = .{ .instruction = .@"xvfrintrz.d" } }, + .{ .value = 0x00016400, .then = .{ .instruction = .@"xvfrintrz.s" } }, + .{ .value = 0x00010800, .then = .{ .instruction = .@"xvfrsqrt.d" } }, + .{ .value = 0x00010400, .then = .{ .instruction = .@"xvfrsqrt.s" } }, + .{ .value = 0x00012800, .then = .{ .instruction = .@"xvfrsqrte.d" } }, + .{ .value = 0x00012400, .then = .{ .instruction = .@"xvfrsqrte.s" } }, + .{ .value = 0x0000e800, .then = .{ .instruction = .@"xvfsqrt.d" } }, + .{ .value = 0x0000e400, .then = .{ .instruction = .@"xvfsqrt.s" } }, + .{ .value = 0x00023400, .then = .{ .instruction = .@"xvftint.l.d" } }, + .{ .value = 0x00025c00, .then = .{ .instruction = .@"xvftint.lu.d" } }, + .{ .value = 0x00023000, .then = .{ .instruction = .@"xvftint.w.s" } }, + .{ .value = 0x00025800, .then = .{ .instruction = .@"xvftint.wu.s" } }, + .{ .value = 0x00028400, .then = .{ .instruction = .@"xvftinth.l.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvftintl.l.s" } }, + .{ .value = 0x00023c00, .then = .{ .instruction = .@"xvftintrm.l.d" } }, + .{ .value = 0x00023800, .then = .{ .instruction = .@"xvftintrm.w.s" } }, + .{ .value = 0x00028c00, .then = .{ .instruction = .@"xvftintrmh.l.s" } }, + .{ .value = 0x00028800, .then = .{ .instruction = .@"xvftintrml.l.s" } }, + .{ .value = 0x00025400, .then = .{ .instruction = .@"xvftintrne.l.d" } }, + .{ .value = 0x00025000, .then = .{ .instruction = .@"xvftintrne.w.s" } }, + .{ .value = 0x0002a400, .then = .{ .instruction = .@"xvftintrneh.l.s" } }, + .{ .value = 0x0002a000, .then = .{ .instruction = .@"xvftintrnel.l.s" } }, + .{ .value = 0x00024400, .then = .{ .instruction = .@"xvftintrp.l.d" } }, + .{ .value = 0x00024000, .then = .{ .instruction = .@"xvftintrp.w.s" } }, + .{ .value = 0x00029400, .then = .{ .instruction = .@"xvftintrph.l.s" } }, + .{ .value = 0x00029000, .then = .{ .instruction = .@"xvftintrpl.l.s" } }, + .{ .value = 0x00024c00, .then = .{ .instruction = .@"xvftintrz.l.d" } }, + .{ .value = 0x00027400, .then = .{ .instruction = .@"xvftintrz.lu.d" } }, + .{ .value = 0x00024800, .then = .{ .instruction = .@"xvftintrz.w.s" } }, + .{ .value = 0x00027000, .then = .{ .instruction = .@"xvftintrz.wu.s" } }, + .{ .value = 0x00029c00, .then = .{ .instruction = .@"xvftintrzh.l.s" } }, + .{ .value = 0x00029800, .then = .{ .instruction = .@"xvftintrzl.l.s" } }, + .{ .value = 0x00005000, .then = .{ .instruction = .@"xvmskgez.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvmskltz.b" } }, + .{ .value = 0x00004c00, .then = .{ .instruction = .@"xvmskltz.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"xvmskltz.h" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"xvmskltz.w" } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"xvmsknz.b" } }, + .{ .value = 0x00003000, .then = .{ .instruction = .@"xvneg.b" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"xvneg.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"xvneg.h" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"xvneg.w" } }, + .{ .value = 0x00002000, .then = .{ .instruction = .@"xvpcnt.b" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"xvpcnt.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"xvpcnt.h" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"xvpcnt.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplgr2vr.b" } }, + .{ .value = 0x00030c00, .then = .{ .instruction = .@"xvreplgr2vr.d" } }, + .{ .value = 0x00030400, .then = .{ .instruction = .@"xvreplgr2vr.h" } }, + .{ .value = 0x00030800, .then = .{ .instruction = .@"xvreplgr2vr.w" } }, + .{ .value = 0x0000b000, .then = .{ .instruction = .@"xvsetallnez.b" } }, + .{ .value = 0x0000bc00, .then = .{ .instruction = .@"xvsetallnez.d" } }, + .{ .value = 0x0000b400, .then = .{ .instruction = .@"xvsetallnez.h" } }, + .{ .value = 0x0000b800, .then = .{ .instruction = .@"xvsetallnez.w" } }, + .{ .value = 0x0000a000, .then = .{ .instruction = .@"xvsetanyeqz.b" } }, + .{ .value = 0x0000ac00, .then = .{ .instruction = .@"xvsetanyeqz.d" } }, + .{ .value = 0x0000a400, .then = .{ .instruction = .@"xvsetanyeqz.h" } }, + .{ .value = 0x0000a800, .then = .{ .instruction = .@"xvsetanyeqz.w" } }, + .{ .value = 0x00009800, .then = .{ .instruction = .@"xvseteqz.v" } }, + .{ .value = 0x00009c00, .then = .{ .instruction = .@"xvsetnez.v" } }, + } } }, + .{ .value = 0x00600000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvabsd.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvabsd.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvabsd.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvabsd.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvabsd.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvabsd.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvabsd.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvabsd.wu" } }, + } } }, + .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvadd.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslt.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslt.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslt.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslt.wu" } }, + } } }, + .{ .value = 0x012c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvadd.q" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsigncov.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsigncov.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsigncov.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsigncov.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsub.q" } }, + } } }, + .{ .value = 0x005c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvadda.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvadda.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvadda.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvadda.w" } }, + } } }, + .{ .value = 0x02880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddi.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddi.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddi.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddi.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslti.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslti.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslti.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslti.wu" } }, + } } }, + .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.h" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.hu" } }, + } } }, + .{ .value = 0x003c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.hu.h" } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwod.w.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwev.w.h" } }, + } } }, + .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwod.w.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwev.w.hu" } }, + } } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvaddwod.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvaddwod.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvaddwod.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x01240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvand.v" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvnor.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvor.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvxor.v" } }, + } } }, + .{ .value = 0x03d00000, .then = .{ .instruction = .@"xvandi.b" } }, + .{ .value = 0x01280000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvandn.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfrstp.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfrstp.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvorn.v" } }, + } } }, + .{ .value = 0x00640000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvavg.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvavg.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvavg.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvavg.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvavg.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvavg.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvavg.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvavg.wu" } }, + } } }, + .{ .value = 0x00680000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvavgr.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvavgr.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvavgr.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvavgr.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvavgr.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvavgr.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvavgr.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvavgr.wu" } }, + } } }, + .{ .value = 0x010c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitclr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvbitclr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitclr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitclr.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvbitset.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvbitset.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvbitset.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvbitset.w" } }, + } } }, + .{ .value = 0x03100000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitclri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitclri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitclri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitclri.d" } }, + } } }, + .{ .value = 0x01100000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitrev.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvbitrev.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitrev.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitrev.w" } }, + } } }, + .{ .value = 0x03180000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitrevi.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitrevi.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitrevi.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitrevi.d" } }, + } } }, + .{ .value = 0x03c40000, .then = .{ .instruction = .@"xvbitseli.b" } }, + .{ .value = 0x03140000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitseti.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitseti.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitseti.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitseti.d" } }, + } } }, + .{ .value = 0x028c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvbsll.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvbsrl.v" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubi.wu" } }, + } } }, + .{ .value = 0x00e00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvdiv.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvdiv.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvdiv.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvdiv.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmod.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmod.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmod.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmod.w" } }, + } } }, + .{ .value = 0x00e40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvdiv.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvdiv.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvdiv.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvdiv.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmod.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmod.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmod.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmod.wu" } }, + } } }, + .{ .value = 0x03080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvextl.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsllwil.d.w" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsllwil.h.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsllwil.w.h" } }, + } } }, + } } }, + .{ .value = 0x030c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvextl.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsllwil.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsllwil.hu.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsllwil.wu.hu" } }, + } } }, + } } }, + .{ .value = 0x038c0000, .then = .{ .instruction = .@"xvextrins.b" } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"xvextrins.d" } }, + .{ .value = 0x03880000, .then = .{ .instruction = .@"xvextrins.h" } }, + .{ .value = 0x03840000, .then = .{ .instruction = .@"xvextrins.w" } }, + .{ .value = 0x01300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfadd.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfsub.s" } }, + } } }, + .{ .value = 0x01440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcvt.h.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcvt.s.d" } }, + } } }, + .{ .value = 0x01380000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfdiv.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfdiv.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmul.s" } }, + } } }, + .{ .value = 0x01480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvffint.s.l" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvftint.w.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvftintrm.w.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvftintrne.w.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvftintrp.w.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvftintrz.w.d" } }, + } } }, + .{ .value = 0x013c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmax.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfmin.s" } }, + } } }, + .{ .value = 0x01400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmaxa.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmaxa.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfmina.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfmina.s" } }, + } } }, + .{ .value = 0x02980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfrstpi.b" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfrstpi.h" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmepatmsk.v" } }, + } } }, + .{ .value = 0x00540000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvhaddw.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvhaddw.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvhaddw.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvhaddw.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvhsubw.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvhsubw.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvhsubw.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvhsubw.w.h" } }, + } } }, + .{ .value = 0x00580000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvhaddw.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvhaddw.hu.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvhaddw.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvhaddw.wu.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvhsubw.du.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvhsubw.hu.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvhsubw.qu.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvhsubw.wu.hu" } }, + } } }, + .{ .value = 0x011c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvilvh.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvilvh.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvilvh.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvilvh.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvpickev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvpickev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvpickev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvpickev.w" } }, + } } }, + .{ .value = 0x01180000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvilvl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvilvl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvilvl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvilvl.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvpackod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvpackod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvpackod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvpackod.w" } }, + } } }, + .{ .value = 0x02e80000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvinsgr2vr.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvinsgr2vr.w" } }, + } } }, + .{ .value = 0x02fc0000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvinsve0.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvinsve0.w" } }, + } } }, + .{ .value = 0x03e00000, .then = .{ .instruction = .xvldi } }, + .{ .value = 0x00a80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmadd.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmadd.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmadd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmsub.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmsub.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmsub.w" } }, + } } }, + .{ .value = 0x00ac0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.h" } }, + } } }, + .{ .value = 0x00b40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.hu" } }, + } } }, + .{ .value = 0x00bc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x00700000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmax.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmax.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmax.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmin.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmin.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmin.w" } }, + } } }, + .{ .value = 0x00740000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmax.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmax.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmax.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmax.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmin.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmin.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmin.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmin.wu" } }, + } } }, + .{ .value = 0x02900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaxi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaxi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaxi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaxi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmini.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmini.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmini.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmini.w" } }, + } } }, + .{ .value = 0x02940000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaxi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaxi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaxi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaxi.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmini.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmini.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmini.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmini.wu" } }, + } } }, + .{ .value = 0x00840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmuh.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmuh.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmuh.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmuh.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmul.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmul.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmul.w" } }, + } } }, + .{ .value = 0x00880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmuh.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmuh.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmuh.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmuh.wu" } }, + } } }, + .{ .value = 0x00900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.h" } }, + } } }, + .{ .value = 0x00980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.hu" } }, + } } }, + .{ .value = 0x00a00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.hu.h" } }, + } } }, + .{ .value = 0x03dc0000, .then = .{ .instruction = .@"xvnori.b" } }, + .{ .value = 0x03d40000, .then = .{ .instruction = .@"xvori.b" } }, + .{ .value = 0x01140000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvpackev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvpackev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvpackev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvpackev.w" } }, + } } }, + .{ .value = 0x017c0000, .then = .{ .instruction = .@"xvperm.w" } }, + .{ .value = 0x03e80000, .then = .{ .instruction = .@"xvpermi.d" } }, + .{ .value = 0x03ec0000, .then = .{ .instruction = .@"xvpermi.q" } }, + .{ .value = 0x03e40000, .then = .{ .instruction = .@"xvpermi.w" } }, + .{ .value = 0x01200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvpickod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvpickod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvpickod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvpickod.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvreplve.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvreplve.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvreplve.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplve.w" } }, + } } }, + .{ .value = 0x03000000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve.w" } }, + } } }, + .{ .value = 0x02ec0000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve2gr.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve2gr.w" } }, + } } }, + .{ .value = 0x02f00000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve2gr.du" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve2gr.wu" } }, + } } }, + .{ .value = 0x02f40000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvrepl128vei.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"xvrepl128vei.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrepl128vei.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrepl128vei.h" } }, + } } }, + } } }, + .{ .value = 0x03040000, .then = .{ .mask = 0x0003fc00, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplve0.b" } }, + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvreplve0.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvreplve0.h" } }, + .{ .value = 0x0003f000, .then = .{ .instruction = .@"xvreplve0.q" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvreplve0.w" } }, + } } }, + .{ .value = 0x00ec0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvrotr.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvrotr.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvrotr.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvrotr.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsra.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsra.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsra.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsra.w" } }, + } } }, + .{ .value = 0x02a00000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrotri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvrotri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvrotri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvrotri.d" } }, + } } }, + .{ .value = 0x00440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsadd.w" } }, + } } }, + .{ .value = 0x00480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsadd.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsadd.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsadd.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsadd.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssub.w" } }, + } } }, + .{ .value = 0x03240000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsat.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsat.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsat.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsat.d" } }, + } } }, + .{ .value = 0x03280000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsat.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsat.hu" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsat.wu" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsat.du" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvseq.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvseq.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvseq.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvseq.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsle.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsle.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsle.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsle.w" } }, + } } }, + .{ .value = 0x02800000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvseqi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvseqi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvseqi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvseqi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslei.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslei.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslei.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslei.w" } }, + } } }, + .{ .value = 0x01780000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvshuf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvshuf.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvshuf.w" } }, + } } }, + .{ .value = 0x03900000, .then = .{ .instruction = .@"xvshuf4i.b" } }, + .{ .value = 0x039c0000, .then = .{ .instruction = .@"xvshuf4i.d" } }, + .{ .value = 0x03940000, .then = .{ .instruction = .@"xvshuf4i.h" } }, + .{ .value = 0x03980000, .then = .{ .instruction = .@"xvshuf4i.w" } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsle.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsle.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsle.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsle.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslt.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslt.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslt.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslt.w" } }, + } } }, + .{ .value = 0x02840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslei.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslei.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslei.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslei.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslti.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslti.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslti.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslti.w" } }, + } } }, + .{ .value = 0x00e80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsll.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsll.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsll.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsll.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrl.w" } }, + } } }, + .{ .value = 0x032c0000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvslli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslli.d" } }, + } } }, + .{ .value = 0x03340000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrai.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrai.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrai.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrai.d" } }, + } } }, + .{ .value = 0x00f40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrln.w.d" } }, + } } }, + .{ .value = 0x03580000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrani.d.q" } }, + } } }, + .{ .value = 0x00f00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrar.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrar.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrar.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrar.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrlr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlr.w" } }, + } } }, + .{ .value = 0x02a80000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrari.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrari.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrari.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrari.d" } }, + } } }, + .{ .value = 0x00f80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrlrn.w.d" } }, + } } }, + .{ .value = 0x035c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrarni.d.q" } }, + } } }, + .{ .value = 0x03300000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrli.d" } }, + } } }, + .{ .value = 0x03400000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrlni.d.q" } }, + } } }, + .{ .value = 0x02a40000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrlri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlri.d" } }, + } } }, + .{ .value = 0x03440000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrlrni.d.q" } }, + } } }, + .{ .value = 0x00fc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrln.w.d" } }, + } } }, + .{ .value = 0x01040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssran.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssran.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssran.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrln.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrln.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrln.wu.d" } }, + } } }, + .{ .value = 0x03600000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrani.d.q" } }, + } } }, + .{ .value = 0x03640000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrani.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrani.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrani.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrani.du.q" } }, + } } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrlrn.w.d" } }, + } } }, + .{ .value = 0x01080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssrarn.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssrarn.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssrarn.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrn.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrn.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrlrn.wu.d" } }, + } } }, + .{ .value = 0x03680000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrarni.d.q" } }, + } } }, + .{ .value = 0x036c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrarni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrarni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrarni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrarni.du.q" } }, + } } }, + .{ .value = 0x03480000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlni.d.q" } }, + } } }, + .{ .value = 0x034c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlni.du.q" } }, + } } }, + .{ .value = 0x03500000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlrni.d.q" } }, + } } }, + .{ .value = 0x03540000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlrni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlrni.du.q" } }, + } } }, + .{ .value = 0x004c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssub.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssub.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssub.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssub.wu" } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsub.w" } }, + } } }, + .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwod.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwod.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwod.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwod.w.h" } }, + } } }, + .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwod.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwod.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwod.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwod.w.hu" } }, + } } }, + .{ .value = 0x03d80000, .then = .{ .instruction = .@"xvxori.b" } }, + } } }, + .{ .value = 0x30000000, .then = .{ .mask = 0x03800000, .cases = .{ + .{ .value = 0x00800000, .then = .{ .instruction = .@"vldrepl.b" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00600000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vldrepl.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"vldrepl.h" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"vldrepl.w" } }, + } } }, + .{ .value = 0x01800000, .then = .{ .instruction = .@"vstelm.b" } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x00600000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vstelm.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"vstelm.h" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"vstelm.w" } }, + } } }, + .{ .value = 0x02800000, .then = .{ .instruction = .@"xvldrepl.b" } }, + .{ .value = 0x02000000, .then = .{ .mask = 0x00600000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvldrepl.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"xvldrepl.h" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"xvldrepl.w" } }, + } } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"xvstelm.b" } }, + .{ .value = 0x03000000, .then = .{ .mask = 0x00400000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00200000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvstelm.d" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"xvstelm.w" } }, + } } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"xvstelm.h" } }, + } } }, + } } }, +} } diff --git a/src/codegen/loongarch/encoding.zig b/src/codegen/loongarch/encoding.zig new file mode 100644 index 0000000000000000000000000000000000000000..e90b0e2bd75ce2f9a025a2bc3acd450b5d63d4d9 --- /dev/null +++ b/src/codegen/loongarch/encoding.zig @@ -0,0 +1,13695 @@ +// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. +const Register = @import("bits.zig").Register; + +pub const Mnemonic = enum { + @"adc.b", + @"adc.d", + @"adc.h", + @"adc.w", + @"add.d", + @"add.w", + @"addi.d", + @"addi.w", + @"addu12i.d", + @"addu12i.w", + @"addu16i.d", + @"amadd.b", + @"amadd.d", + @"amadd.h", + @"amadd.w", + @"amadd_db.b", + @"amadd_db.d", + @"amadd_db.h", + @"amadd_db.w", + @"amand.d", + @"amand.w", + @"amand_db.d", + @"amand_db.w", + @"amcas.b", + @"amcas.d", + @"amcas.h", + @"amcas.w", + @"amcas_db.b", + @"amcas_db.d", + @"amcas_db.h", + @"amcas_db.w", + @"ammax.d", + @"ammax.du", + @"ammax.w", + @"ammax.wu", + @"ammax_db.d", + @"ammax_db.du", + @"ammax_db.w", + @"ammax_db.wu", + @"ammin.d", + @"ammin.du", + @"ammin.w", + @"ammin.wu", + @"ammin_db.d", + @"ammin_db.du", + @"ammin_db.w", + @"ammin_db.wu", + @"amor.d", + @"amor.w", + @"amor_db.d", + @"amor_db.w", + @"amswap.b", + @"amswap.d", + @"amswap.h", + @"amswap.w", + @"amswap_db.b", + @"amswap_db.d", + @"amswap_db.h", + @"amswap_db.w", + @"amxor.d", + @"amxor.w", + @"amxor_db.d", + @"amxor_db.w", + @"and", + andi, + andn, + @"armadc.w", + @"armadd.w", + @"armand.w", + armmfflag, + @"armmov.d", + @"armmov.w", + armmove, + armmtflag, + @"armnot.w", + @"armor.w", + @"armrotr.w", + @"armrotri.w", + @"armrrx.w", + @"armsbc.w", + armsetj, + @"armsll.w", + @"armslli.w", + @"armsra.w", + @"armsrai.w", + @"armsrl.w", + @"armsrli.w", + @"armsub.w", + @"armxor.w", + asrtgt, + asrtle, + b, + bceqz, + bcnez, + beq, + beqz, + bgt, + bgtu, + bl, + ble, + bleu, + bne, + bnez, + @"break", + @"bstrins.d", + @"bstrins.w", + @"bstrpick.d", + @"bstrpick.w", + cacop, + @"catpick.d", + @"catpick.w", + @"clo.d", + @"clo.w", + @"clz.d", + @"clz.w", + cpucfg, + @"crc.w.b.w", + @"crc.w.d.w", + @"crc.w.h.w", + @"crc.w.w.w", + @"crcc.w.b.w", + @"crcc.w.d.w", + @"crcc.w.h.w", + @"crcc.w.w.w", + csrrd, + csrwr, + csrxchg, + @"cto.d", + @"cto.w", + @"ctz.d", + @"ctz.w", + @"cu32i.d", + @"cu52i.d", + dbar, + dbgcall, + @"div.d", + @"div.du", + @"div.w", + @"div.wu", + eret, + @"fabs.d", + @"fabs.s", + @"fadd.d", + @"fadd.s", + @"fclass.d", + @"fclass.s", + @"fcmp.caf.d", + @"fcmp.caf.s", + @"fcmp.ceq.d", + @"fcmp.ceq.s", + @"fcmp.cle.d", + @"fcmp.cle.s", + @"fcmp.clt.d", + @"fcmp.clt.s", + @"fcmp.cne.d", + @"fcmp.cne.s", + @"fcmp.cor.d", + @"fcmp.cor.s", + @"fcmp.cueq.d", + @"fcmp.cueq.s", + @"fcmp.cule.d", + @"fcmp.cule.s", + @"fcmp.cult.d", + @"fcmp.cult.s", + @"fcmp.cun.d", + @"fcmp.cun.s", + @"fcmp.cune.d", + @"fcmp.cune.s", + @"fcmp.saf.d", + @"fcmp.saf.s", + @"fcmp.seq.d", + @"fcmp.seq.s", + @"fcmp.sle.d", + @"fcmp.sle.s", + @"fcmp.slt.d", + @"fcmp.slt.s", + @"fcmp.sne.d", + @"fcmp.sne.s", + @"fcmp.sor.d", + @"fcmp.sor.s", + @"fcmp.sueq.d", + @"fcmp.sueq.s", + @"fcmp.sule.d", + @"fcmp.sule.s", + @"fcmp.sult.d", + @"fcmp.sult.s", + @"fcmp.sun.d", + @"fcmp.sun.s", + @"fcmp.sune.d", + @"fcmp.sune.s", + @"fcopysign.d", + @"fcopysign.s", + fcsrrd, + fcsrwr, + @"fcvt.d.ld", + @"fcvt.d.s", + @"fcvt.ld.d", + @"fcvt.s.d", + @"fcvt.ud.d", + @"fdiv.d", + @"fdiv.s", + @"ffint.d.l", + @"ffint.d.w", + @"ffint.s.l", + @"ffint.s.w", + @"fld.d", + @"fld.s", + @"fldgt.d", + @"fldgt.s", + @"fldle.d", + @"fldle.s", + @"fldx.d", + @"fldx.s", + @"flogb.d", + @"flogb.s", + @"fmadd.d", + @"fmadd.s", + @"fmax.d", + @"fmax.s", + @"fmaxa.d", + @"fmaxa.s", + @"fmin.d", + @"fmin.s", + @"fmina.d", + @"fmina.s", + @"fmov.d", + @"fmov.s", + @"fmsub.d", + @"fmsub.s", + @"fmul.d", + @"fmul.s", + @"fneg.d", + @"fneg.s", + @"fnmadd.d", + @"fnmadd.s", + @"fnmsub.d", + @"fnmsub.s", + @"frecip.d", + @"frecip.s", + @"frecipe.d", + @"frecipe.s", + @"frint.d", + @"frint.s", + @"frsqrt.d", + @"frsqrt.s", + @"frsqrte.d", + @"frsqrte.s", + @"fscaleb.d", + @"fscaleb.s", + fsel, + @"fsqrt.d", + @"fsqrt.s", + @"fst.d", + @"fst.s", + @"fstgt.d", + @"fstgt.s", + @"fstle.d", + @"fstle.s", + @"fstx.d", + @"fstx.s", + @"fsub.d", + @"fsub.s", + @"ftint.l.d", + @"ftint.l.s", + @"ftint.w.d", + @"ftint.w.s", + @"ftintrm.l.d", + @"ftintrm.l.s", + @"ftintrm.w.d", + @"ftintrm.w.s", + @"ftintrne.l.d", + @"ftintrne.l.s", + @"ftintrne.w.d", + @"ftintrne.w.s", + @"ftintrp.l.d", + @"ftintrp.l.s", + @"ftintrp.w.d", + @"ftintrp.w.s", + @"ftintrz.l.d", + @"ftintrz.l.s", + @"ftintrz.w.d", + @"ftintrz.w.s", + gcsrrd, + gcsrwr, + gcsrxchg, + gtlbclr, + gtlbfill, + gtlbflush, + gtlbrd, + gtlbsrch, + gtlbwr, + hypcall, + ibar, + idle, + @"iocsrrd.b", + @"iocsrrd.d", + @"iocsrrd.h", + @"iocsrrd.w", + @"iocsrwr.b", + @"iocsrwr.d", + @"iocsrwr.h", + @"iocsrwr.w", + jirl, + jiscr0, + jiscr1, + @"ld.b", + @"ld.bu", + @"ld.d", + @"ld.h", + @"ld.hu", + @"ld.w", + @"ld.wu", + lddir, + @"ldgt.b", + @"ldgt.d", + @"ldgt.h", + @"ldgt.w", + @"ldl.d", + @"ldl.w", + @"ldle.b", + @"ldle.d", + @"ldle.h", + @"ldle.w", + @"ldox4.d", + @"ldox4.w", + ldpte, + @"ldr.d", + @"ldr.w", + @"ldx.b", + @"ldx.bu", + @"ldx.d", + @"ldx.h", + @"ldx.hu", + @"ldx.w", + @"ldx.wu", + @"ll.d", + @"ll.w", + @"llacq.d", + @"llacq.w", + @"lu12i.w", + maskeqz, + masknez, + @"mod.d", + @"mod.du", + @"mod.w", + @"mod.wu", + movfcc2fr, + movfcc2gr, + movfr2fcc, + @"movfr2gr.d", + @"movfr2gr.s", + @"movfrh2gr.s", + movgr2fcc, + @"movgr2fr.d", + @"movgr2fr.w", + @"movgr2frh.w", + movgr2scr, + movscr2gr, + @"mul.d", + @"mul.w", + @"mulh.d", + @"mulh.du", + @"mulh.w", + @"mulh.wu", + @"mulw.d.w", + @"mulw.d.wu", + nor, + @"or", + ori, + orn, + pcaddu12i, + pcaddu18i, + pcaddu2i, + pcalau12i, + preld, + preldx, + @"rcr.b", + @"rcr.d", + @"rcr.h", + @"rcr.w", + @"rcri.b", + @"rcri.d", + @"rcri.h", + @"rcri.w", + @"rdtime.d", + @"rdtimeh.w", + @"rdtimel.w", + @"revb.2h", + @"revb.2w", + @"revb.4h", + @"revb.d", + @"revbit.4b", + @"revbit.8b", + @"revbit.d", + @"revbit.w", + @"revh.2w", + @"revh.d", + @"rotr.b", + @"rotr.d", + @"rotr.h", + @"rotr.w", + @"rotri.b", + @"rotri.d", + @"rotri.h", + @"rotri.w", + @"sbc.b", + @"sbc.d", + @"sbc.h", + @"sbc.w", + @"sc.d", + @"sc.q", + @"sc.w", + @"screl.d", + @"screl.w", + @"sext.b", + @"sext.h", + @"sladd.d", + @"sladd.w", + @"sladd.wu", + @"sll.d", + @"sll.w", + @"slli.d", + @"slli.w", + slt, + slti, + sltu, + sltui, + @"sra.d", + @"sra.w", + @"srai.d", + @"srai.w", + @"srl.d", + @"srl.w", + @"srli.d", + @"srli.w", + @"st.b", + @"st.d", + @"st.h", + @"st.w", + @"stgt.b", + @"stgt.d", + @"stgt.h", + @"stgt.w", + @"stl.d", + @"stl.w", + @"stle.b", + @"stle.d", + @"stle.h", + @"stle.w", + @"stox4.d", + @"stox4.w", + @"str.d", + @"str.w", + @"stx.b", + @"stx.d", + @"stx.h", + @"stx.w", + @"sub.d", + @"sub.w", + syscall, + tlbclr, + tlbfill, + tlbflush, + tlbinv, + tlbrd, + tlbsrch, + tlbwr, + @"vabsd.b", + @"vabsd.bu", + @"vabsd.d", + @"vabsd.du", + @"vabsd.h", + @"vabsd.hu", + @"vabsd.w", + @"vabsd.wu", + @"vadd.b", + @"vadd.d", + @"vadd.h", + @"vadd.q", + @"vadd.w", + @"vadda.b", + @"vadda.d", + @"vadda.h", + @"vadda.w", + @"vaddi.bu", + @"vaddi.du", + @"vaddi.hu", + @"vaddi.wu", + @"vaddwev.d.w", + @"vaddwev.d.wu", + @"vaddwev.d.wu.w", + @"vaddwev.h.b", + @"vaddwev.h.bu", + @"vaddwev.h.bu.b", + @"vaddwev.q.d", + @"vaddwev.q.du", + @"vaddwev.q.du.d", + @"vaddwev.w.h", + @"vaddwev.w.hu", + @"vaddwev.w.hu.h", + @"vaddwod.d.w", + @"vaddwod.d.wu", + @"vaddwod.d.wu.w", + @"vaddwod.h.b", + @"vaddwod.h.bu", + @"vaddwod.h.bu.b", + @"vaddwod.q.d", + @"vaddwod.q.du", + @"vaddwod.q.du.d", + @"vaddwod.w.h", + @"vaddwod.w.hu", + @"vaddwod.w.hu.h", + @"vand.v", + @"vandi.b", + @"vandn.v", + @"vavg.b", + @"vavg.bu", + @"vavg.d", + @"vavg.du", + @"vavg.h", + @"vavg.hu", + @"vavg.w", + @"vavg.wu", + @"vavgr.b", + @"vavgr.bu", + @"vavgr.d", + @"vavgr.du", + @"vavgr.h", + @"vavgr.hu", + @"vavgr.w", + @"vavgr.wu", + @"vbitclr.b", + @"vbitclr.d", + @"vbitclr.h", + @"vbitclr.w", + @"vbitclri.b", + @"vbitclri.d", + @"vbitclri.h", + @"vbitclri.w", + @"vbitrev.b", + @"vbitrev.d", + @"vbitrev.h", + @"vbitrev.w", + @"vbitrevi.b", + @"vbitrevi.d", + @"vbitrevi.h", + @"vbitrevi.w", + @"vbitsel.v", + @"vbitseli.b", + @"vbitset.b", + @"vbitset.d", + @"vbitset.h", + @"vbitset.w", + @"vbitseti.b", + @"vbitseti.d", + @"vbitseti.h", + @"vbitseti.w", + @"vbsll.v", + @"vbsrl.v", + @"vclo.b", + @"vclo.d", + @"vclo.h", + @"vclo.w", + @"vclz.b", + @"vclz.d", + @"vclz.h", + @"vclz.w", + @"vdiv.b", + @"vdiv.bu", + @"vdiv.d", + @"vdiv.du", + @"vdiv.h", + @"vdiv.hu", + @"vdiv.w", + @"vdiv.wu", + @"vext2xv.d.b", + @"vext2xv.d.h", + @"vext2xv.d.w", + @"vext2xv.du.bu", + @"vext2xv.du.hu", + @"vext2xv.du.wu", + @"vext2xv.h.b", + @"vext2xv.hu.bu", + @"vext2xv.w.b", + @"vext2xv.w.h", + @"vext2xv.wu.bu", + @"vext2xv.wu.hu", + @"vexth.d.w", + @"vexth.du.wu", + @"vexth.h.b", + @"vexth.hu.bu", + @"vexth.q.d", + @"vexth.qu.du", + @"vexth.w.h", + @"vexth.wu.hu", + @"vextl.q.d", + @"vextl.qu.du", + @"vextrins.b", + @"vextrins.d", + @"vextrins.h", + @"vextrins.w", + @"vfadd.d", + @"vfadd.s", + @"vfclass.d", + @"vfclass.s", + @"vfcmp.caf.d", + @"vfcmp.caf.s", + @"vfcmp.ceq.d", + @"vfcmp.ceq.s", + @"vfcmp.cle.d", + @"vfcmp.cle.s", + @"vfcmp.clt.d", + @"vfcmp.clt.s", + @"vfcmp.cne.d", + @"vfcmp.cne.s", + @"vfcmp.cor.d", + @"vfcmp.cor.s", + @"vfcmp.cueq.d", + @"vfcmp.cueq.s", + @"vfcmp.cule.d", + @"vfcmp.cule.s", + @"vfcmp.cult.d", + @"vfcmp.cult.s", + @"vfcmp.cun.d", + @"vfcmp.cun.s", + @"vfcmp.cune.d", + @"vfcmp.cune.s", + @"vfcmp.saf.d", + @"vfcmp.saf.s", + @"vfcmp.seq.d", + @"vfcmp.seq.s", + @"vfcmp.sle.d", + @"vfcmp.sle.s", + @"vfcmp.slt.d", + @"vfcmp.slt.s", + @"vfcmp.sne.d", + @"vfcmp.sne.s", + @"vfcmp.sor.d", + @"vfcmp.sor.s", + @"vfcmp.sueq.d", + @"vfcmp.sueq.s", + @"vfcmp.sule.d", + @"vfcmp.sule.s", + @"vfcmp.sult.d", + @"vfcmp.sult.s", + @"vfcmp.sun.d", + @"vfcmp.sun.s", + @"vfcmp.sune.d", + @"vfcmp.sune.s", + @"vfcvt.h.s", + @"vfcvt.s.d", + @"vfcvth.d.s", + @"vfcvth.s.h", + @"vfcvtl.d.s", + @"vfcvtl.s.h", + @"vfdiv.d", + @"vfdiv.s", + @"vffint.d.l", + @"vffint.d.lu", + @"vffint.s.l", + @"vffint.s.w", + @"vffint.s.wu", + @"vffinth.d.w", + @"vffintl.d.w", + @"vflogb.d", + @"vflogb.s", + @"vfmadd.d", + @"vfmadd.s", + @"vfmax.d", + @"vfmax.s", + @"vfmaxa.d", + @"vfmaxa.s", + @"vfmin.d", + @"vfmin.s", + @"vfmina.d", + @"vfmina.s", + @"vfmsub.d", + @"vfmsub.s", + @"vfmul.d", + @"vfmul.s", + @"vfnmadd.d", + @"vfnmadd.s", + @"vfnmsub.d", + @"vfnmsub.s", + @"vfrecip.d", + @"vfrecip.s", + @"vfrecipe.d", + @"vfrecipe.s", + @"vfrint.d", + @"vfrint.s", + @"vfrintrm.d", + @"vfrintrm.s", + @"vfrintrne.d", + @"vfrintrne.s", + @"vfrintrp.d", + @"vfrintrp.s", + @"vfrintrz.d", + @"vfrintrz.s", + @"vfrsqrt.d", + @"vfrsqrt.s", + @"vfrsqrte.d", + @"vfrsqrte.s", + @"vfrstp.b", + @"vfrstp.h", + @"vfrstpi.b", + @"vfrstpi.h", + @"vfsqrt.d", + @"vfsqrt.s", + @"vfsub.d", + @"vfsub.s", + @"vftint.l.d", + @"vftint.lu.d", + @"vftint.w.d", + @"vftint.w.s", + @"vftint.wu.s", + @"vftinth.l.s", + @"vftintl.l.s", + @"vftintrm.l.d", + @"vftintrm.w.d", + @"vftintrm.w.s", + @"vftintrmh.l.s", + @"vftintrml.l.s", + @"vftintrne.l.d", + @"vftintrne.w.d", + @"vftintrne.w.s", + @"vftintrneh.l.s", + @"vftintrnel.l.s", + @"vftintrp.l.d", + @"vftintrp.w.d", + @"vftintrp.w.s", + @"vftintrph.l.s", + @"vftintrpl.l.s", + @"vftintrz.l.d", + @"vftintrz.lu.d", + @"vftintrz.w.d", + @"vftintrz.w.s", + @"vftintrz.wu.s", + @"vftintrzh.l.s", + @"vftintrzl.l.s", + @"vhaddw.d.w", + @"vhaddw.du.wu", + @"vhaddw.h.b", + @"vhaddw.hu.bu", + @"vhaddw.q.d", + @"vhaddw.qu.du", + @"vhaddw.w.h", + @"vhaddw.wu.hu", + @"vhsubw.d.w", + @"vhsubw.du.wu", + @"vhsubw.h.b", + @"vhsubw.hu.bu", + @"vhsubw.q.d", + @"vhsubw.qu.du", + @"vhsubw.w.h", + @"vhsubw.wu.hu", + @"vilvh.b", + @"vilvh.d", + @"vilvh.h", + @"vilvh.w", + @"vilvl.b", + @"vilvl.d", + @"vilvl.h", + @"vilvl.w", + @"vinsgr2vr.b", + @"vinsgr2vr.d", + @"vinsgr2vr.h", + @"vinsgr2vr.w", + vld, + vldi, + @"vldrepl.b", + @"vldrepl.d", + @"vldrepl.h", + @"vldrepl.w", + vldx, + @"vmadd.b", + @"vmadd.d", + @"vmadd.h", + @"vmadd.w", + @"vmaddwev.d.w", + @"vmaddwev.d.wu", + @"vmaddwev.d.wu.w", + @"vmaddwev.h.b", + @"vmaddwev.h.bu", + @"vmaddwev.h.bu.b", + @"vmaddwev.q.d", + @"vmaddwev.q.du", + @"vmaddwev.q.du.d", + @"vmaddwev.w.h", + @"vmaddwev.w.hu", + @"vmaddwev.w.hu.h", + @"vmaddwod.d.w", + @"vmaddwod.d.wu", + @"vmaddwod.d.wu.w", + @"vmaddwod.h.b", + @"vmaddwod.h.bu", + @"vmaddwod.h.bu.b", + @"vmaddwod.q.d", + @"vmaddwod.q.du", + @"vmaddwod.q.du.d", + @"vmaddwod.w.h", + @"vmaddwod.w.hu", + @"vmaddwod.w.hu.h", + @"vmax.b", + @"vmax.bu", + @"vmax.d", + @"vmax.du", + @"vmax.h", + @"vmax.hu", + @"vmax.w", + @"vmax.wu", + @"vmaxi.b", + @"vmaxi.bu", + @"vmaxi.d", + @"vmaxi.du", + @"vmaxi.h", + @"vmaxi.hu", + @"vmaxi.w", + @"vmaxi.wu", + @"vmepatmsk.v", + @"vmin.b", + @"vmin.bu", + @"vmin.d", + @"vmin.du", + @"vmin.h", + @"vmin.hu", + @"vmin.w", + @"vmin.wu", + @"vmini.b", + @"vmini.bu", + @"vmini.d", + @"vmini.du", + @"vmini.h", + @"vmini.hu", + @"vmini.w", + @"vmini.wu", + @"vmod.b", + @"vmod.bu", + @"vmod.d", + @"vmod.du", + @"vmod.h", + @"vmod.hu", + @"vmod.w", + @"vmod.wu", + @"vmskgez.b", + @"vmskltz.b", + @"vmskltz.d", + @"vmskltz.h", + @"vmskltz.w", + @"vmsknz.b", + @"vmsub.b", + @"vmsub.d", + @"vmsub.h", + @"vmsub.w", + @"vmuh.b", + @"vmuh.bu", + @"vmuh.d", + @"vmuh.du", + @"vmuh.h", + @"vmuh.hu", + @"vmuh.w", + @"vmuh.wu", + @"vmul.b", + @"vmul.d", + @"vmul.h", + @"vmul.w", + @"vmulwev.d.w", + @"vmulwev.d.wu", + @"vmulwev.d.wu.w", + @"vmulwev.h.b", + @"vmulwev.h.bu", + @"vmulwev.h.bu.b", + @"vmulwev.q.d", + @"vmulwev.q.du", + @"vmulwev.q.du.d", + @"vmulwev.w.h", + @"vmulwev.w.hu", + @"vmulwev.w.hu.h", + @"vmulwod.d.w", + @"vmulwod.d.wu", + @"vmulwod.d.wu.w", + @"vmulwod.h.b", + @"vmulwod.h.bu", + @"vmulwod.h.bu.b", + @"vmulwod.q.d", + @"vmulwod.q.du", + @"vmulwod.q.du.d", + @"vmulwod.w.h", + @"vmulwod.w.hu", + @"vmulwod.w.hu.h", + @"vneg.b", + @"vneg.d", + @"vneg.h", + @"vneg.w", + @"vnor.v", + @"vnori.b", + @"vor.v", + @"vori.b", + @"vorn.v", + @"vpackev.b", + @"vpackev.d", + @"vpackev.h", + @"vpackev.w", + @"vpackod.b", + @"vpackod.d", + @"vpackod.h", + @"vpackod.w", + @"vpcnt.b", + @"vpcnt.d", + @"vpcnt.h", + @"vpcnt.w", + @"vpermi.w", + @"vpickev.b", + @"vpickev.d", + @"vpickev.h", + @"vpickev.w", + @"vpickod.b", + @"vpickod.d", + @"vpickod.h", + @"vpickod.w", + @"vpickve2gr.b", + @"vpickve2gr.bu", + @"vpickve2gr.d", + @"vpickve2gr.du", + @"vpickve2gr.h", + @"vpickve2gr.hu", + @"vpickve2gr.w", + @"vpickve2gr.wu", + @"vreplgr2vr.b", + @"vreplgr2vr.d", + @"vreplgr2vr.h", + @"vreplgr2vr.w", + @"vreplve.b", + @"vreplve.d", + @"vreplve.h", + @"vreplve.w", + @"vreplvei.b", + @"vreplvei.d", + @"vreplvei.h", + @"vreplvei.w", + @"vrotr.b", + @"vrotr.d", + @"vrotr.h", + @"vrotr.w", + @"vrotri.b", + @"vrotri.d", + @"vrotri.h", + @"vrotri.w", + @"vsadd.b", + @"vsadd.bu", + @"vsadd.d", + @"vsadd.du", + @"vsadd.h", + @"vsadd.hu", + @"vsadd.w", + @"vsadd.wu", + @"vsat.b", + @"vsat.bu", + @"vsat.d", + @"vsat.du", + @"vsat.h", + @"vsat.hu", + @"vsat.w", + @"vsat.wu", + @"vseq.b", + @"vseq.d", + @"vseq.h", + @"vseq.w", + @"vseqi.b", + @"vseqi.d", + @"vseqi.h", + @"vseqi.w", + @"vsetallnez.b", + @"vsetallnez.d", + @"vsetallnez.h", + @"vsetallnez.w", + @"vsetanyeqz.b", + @"vsetanyeqz.d", + @"vsetanyeqz.h", + @"vsetanyeqz.w", + @"vseteqz.v", + @"vsetnez.v", + @"vshuf.b", + @"vshuf.d", + @"vshuf.h", + @"vshuf.w", + @"vshuf4i.b", + @"vshuf4i.d", + @"vshuf4i.h", + @"vshuf4i.w", + @"vsigncov.b", + @"vsigncov.d", + @"vsigncov.h", + @"vsigncov.w", + @"vsle.b", + @"vsle.bu", + @"vsle.d", + @"vsle.du", + @"vsle.h", + @"vsle.hu", + @"vsle.w", + @"vsle.wu", + @"vslei.b", + @"vslei.bu", + @"vslei.d", + @"vslei.du", + @"vslei.h", + @"vslei.hu", + @"vslei.w", + @"vslei.wu", + @"vsll.b", + @"vsll.d", + @"vsll.h", + @"vsll.w", + @"vslli.b", + @"vslli.d", + @"vslli.h", + @"vslli.w", + @"vsllwil.d.w", + @"vsllwil.du.wu", + @"vsllwil.h.b", + @"vsllwil.hu.bu", + @"vsllwil.w.h", + @"vsllwil.wu.hu", + @"vslt.b", + @"vslt.bu", + @"vslt.d", + @"vslt.du", + @"vslt.h", + @"vslt.hu", + @"vslt.w", + @"vslt.wu", + @"vslti.b", + @"vslti.bu", + @"vslti.d", + @"vslti.du", + @"vslti.h", + @"vslti.hu", + @"vslti.w", + @"vslti.wu", + @"vsra.b", + @"vsra.d", + @"vsra.h", + @"vsra.w", + @"vsrai.b", + @"vsrai.d", + @"vsrai.h", + @"vsrai.w", + @"vsran.b.h", + @"vsran.h.w", + @"vsran.w.d", + @"vsrani.b.h", + @"vsrani.d.q", + @"vsrani.h.w", + @"vsrani.w.d", + @"vsrar.b", + @"vsrar.d", + @"vsrar.h", + @"vsrar.w", + @"vsrari.b", + @"vsrari.d", + @"vsrari.h", + @"vsrari.w", + @"vsrarn.b.h", + @"vsrarn.h.w", + @"vsrarn.w.d", + @"vsrarni.b.h", + @"vsrarni.d.q", + @"vsrarni.h.w", + @"vsrarni.w.d", + @"vsrl.b", + @"vsrl.d", + @"vsrl.h", + @"vsrl.w", + @"vsrli.b", + @"vsrli.d", + @"vsrli.h", + @"vsrli.w", + @"vsrln.b.h", + @"vsrln.h.w", + @"vsrln.w.d", + @"vsrlni.b.h", + @"vsrlni.d.q", + @"vsrlni.h.w", + @"vsrlni.w.d", + @"vsrlr.b", + @"vsrlr.d", + @"vsrlr.h", + @"vsrlr.w", + @"vsrlri.b", + @"vsrlri.d", + @"vsrlri.h", + @"vsrlri.w", + @"vsrlrn.b.h", + @"vsrlrn.h.w", + @"vsrlrn.w.d", + @"vsrlrni.b.h", + @"vsrlrni.d.q", + @"vsrlrni.h.w", + @"vsrlrni.w.d", + @"vssran.b.h", + @"vssran.bu.h", + @"vssran.h.w", + @"vssran.hu.w", + @"vssran.w.d", + @"vssran.wu.d", + @"vssrani.b.h", + @"vssrani.bu.h", + @"vssrani.d.q", + @"vssrani.du.q", + @"vssrani.h.w", + @"vssrani.hu.w", + @"vssrani.w.d", + @"vssrani.wu.d", + @"vssrarn.b.h", + @"vssrarn.bu.h", + @"vssrarn.h.w", + @"vssrarn.hu.w", + @"vssrarn.w.d", + @"vssrarn.wu.d", + @"vssrarni.b.h", + @"vssrarni.bu.h", + @"vssrarni.d.q", + @"vssrarni.du.q", + @"vssrarni.h.w", + @"vssrarni.hu.w", + @"vssrarni.w.d", + @"vssrarni.wu.d", + @"vssrln.b.h", + @"vssrln.bu.h", + @"vssrln.h.w", + @"vssrln.hu.w", + @"vssrln.w.d", + @"vssrln.wu.d", + @"vssrlni.b.h", + @"vssrlni.bu.h", + @"vssrlni.d.q", + @"vssrlni.du.q", + @"vssrlni.h.w", + @"vssrlni.hu.w", + @"vssrlni.w.d", + @"vssrlni.wu.d", + @"vssrlrn.b.h", + @"vssrlrn.bu.h", + @"vssrlrn.h.w", + @"vssrlrn.hu.w", + @"vssrlrn.w.d", + @"vssrlrn.wu.d", + @"vssrlrni.b.h", + @"vssrlrni.bu.h", + @"vssrlrni.d.q", + @"vssrlrni.du.q", + @"vssrlrni.h.w", + @"vssrlrni.hu.w", + @"vssrlrni.w.d", + @"vssrlrni.wu.d", + @"vssub.b", + @"vssub.bu", + @"vssub.d", + @"vssub.du", + @"vssub.h", + @"vssub.hu", + @"vssub.w", + @"vssub.wu", + vst, + @"vstelm.b", + @"vstelm.d", + @"vstelm.h", + @"vstelm.w", + vstx, + @"vsub.b", + @"vsub.d", + @"vsub.h", + @"vsub.q", + @"vsub.w", + @"vsubi.bu", + @"vsubi.du", + @"vsubi.hu", + @"vsubi.wu", + @"vsubwev.d.w", + @"vsubwev.d.wu", + @"vsubwev.h.b", + @"vsubwev.h.bu", + @"vsubwev.q.d", + @"vsubwev.q.du", + @"vsubwev.w.h", + @"vsubwev.w.hu", + @"vsubwod.d.w", + @"vsubwod.d.wu", + @"vsubwod.h.b", + @"vsubwod.h.bu", + @"vsubwod.q.d", + @"vsubwod.q.du", + @"vsubwod.w.h", + @"vsubwod.w.hu", + @"vxor.v", + @"vxori.b", + @"x86adc.b", + @"x86adc.d", + @"x86adc.h", + @"x86adc.w", + @"x86add.b", + @"x86add.d", + @"x86add.du", + @"x86add.h", + @"x86add.w", + @"x86add.wu", + @"x86and.b", + @"x86and.d", + @"x86and.h", + @"x86and.w", + x86clrtm, + @"x86dec.b", + @"x86dec.d", + @"x86dec.h", + @"x86dec.w", + x86dectop, + @"x86inc.b", + @"x86inc.d", + @"x86inc.h", + @"x86inc.w", + x86inctop, + x86mfflag, + x86mftop, + x86mtflag, + x86mttop, + @"x86mul.b", + @"x86mul.bu", + @"x86mul.d", + @"x86mul.du", + @"x86mul.h", + @"x86mul.hu", + @"x86mul.w", + @"x86mul.wu", + @"x86or.b", + @"x86or.d", + @"x86or.h", + @"x86or.w", + @"x86rcl.b", + @"x86rcl.d", + @"x86rcl.h", + @"x86rcl.w", + @"x86rcli.b", + @"x86rcli.d", + @"x86rcli.h", + @"x86rcli.w", + @"x86rcr.b", + @"x86rcr.d", + @"x86rcr.h", + @"x86rcr.w", + @"x86rcri.b", + @"x86rcri.d", + @"x86rcri.h", + @"x86rcri.w", + @"x86rotl.b", + @"x86rotl.d", + @"x86rotl.h", + @"x86rotl.w", + @"x86rotli.b", + @"x86rotli.d", + @"x86rotli.h", + @"x86rotli.w", + @"x86rotr.b", + @"x86rotr.d", + @"x86rotr.h", + @"x86rotr.w", + @"x86rotri.b", + @"x86rotri.d", + @"x86rotri.h", + @"x86rotri.w", + @"x86sbc.b", + @"x86sbc.d", + @"x86sbc.h", + @"x86sbc.w", + x86setj, + x86setloope, + x86setloopne, + x86settag, + x86settm, + @"x86sll.b", + @"x86sll.d", + @"x86sll.h", + @"x86sll.w", + @"x86slli.b", + @"x86slli.d", + @"x86slli.h", + @"x86slli.w", + @"x86sra.b", + @"x86sra.d", + @"x86sra.h", + @"x86sra.w", + @"x86srai.b", + @"x86srai.d", + @"x86srai.h", + @"x86srai.w", + @"x86srl.b", + @"x86srl.d", + @"x86srl.h", + @"x86srl.w", + @"x86srli.b", + @"x86srli.d", + @"x86srli.h", + @"x86srli.w", + @"x86sub.b", + @"x86sub.d", + @"x86sub.du", + @"x86sub.h", + @"x86sub.w", + @"x86sub.wu", + @"x86xor.b", + @"x86xor.d", + @"x86xor.h", + @"x86xor.w", + xor, + xori, + @"xvabsd.b", + @"xvabsd.bu", + @"xvabsd.d", + @"xvabsd.du", + @"xvabsd.h", + @"xvabsd.hu", + @"xvabsd.w", + @"xvabsd.wu", + @"xvadd.b", + @"xvadd.d", + @"xvadd.h", + @"xvadd.q", + @"xvadd.w", + @"xvadda.b", + @"xvadda.d", + @"xvadda.h", + @"xvadda.w", + @"xvaddi.bu", + @"xvaddi.du", + @"xvaddi.hu", + @"xvaddi.wu", + @"xvaddwev.d.w", + @"xvaddwev.d.wu", + @"xvaddwev.d.wu.w", + @"xvaddwev.h.b", + @"xvaddwev.h.bu", + @"xvaddwev.h.bu.b", + @"xvaddwev.q.d", + @"xvaddwev.q.du", + @"xvaddwev.q.du.d", + @"xvaddwev.w.h", + @"xvaddwev.w.hu", + @"xvaddwev.w.hu.h", + @"xvaddwod.d.w", + @"xvaddwod.d.wu", + @"xvaddwod.d.wu.w", + @"xvaddwod.h.b", + @"xvaddwod.h.bu", + @"xvaddwod.h.bu.b", + @"xvaddwod.q.d", + @"xvaddwod.q.du", + @"xvaddwod.q.du.d", + @"xvaddwod.w.h", + @"xvaddwod.w.hu", + @"xvaddwod.w.hu.h", + @"xvand.v", + @"xvandi.b", + @"xvandn.v", + @"xvavg.b", + @"xvavg.bu", + @"xvavg.d", + @"xvavg.du", + @"xvavg.h", + @"xvavg.hu", + @"xvavg.w", + @"xvavg.wu", + @"xvavgr.b", + @"xvavgr.bu", + @"xvavgr.d", + @"xvavgr.du", + @"xvavgr.h", + @"xvavgr.hu", + @"xvavgr.w", + @"xvavgr.wu", + @"xvbitclr.b", + @"xvbitclr.d", + @"xvbitclr.h", + @"xvbitclr.w", + @"xvbitclri.b", + @"xvbitclri.d", + @"xvbitclri.h", + @"xvbitclri.w", + @"xvbitrev.b", + @"xvbitrev.d", + @"xvbitrev.h", + @"xvbitrev.w", + @"xvbitrevi.b", + @"xvbitrevi.d", + @"xvbitrevi.h", + @"xvbitrevi.w", + @"xvbitsel.v", + @"xvbitseli.b", + @"xvbitset.b", + @"xvbitset.d", + @"xvbitset.h", + @"xvbitset.w", + @"xvbitseti.b", + @"xvbitseti.d", + @"xvbitseti.h", + @"xvbitseti.w", + @"xvbsll.v", + @"xvbsrl.v", + @"xvclo.b", + @"xvclo.d", + @"xvclo.h", + @"xvclo.w", + @"xvclz.b", + @"xvclz.d", + @"xvclz.h", + @"xvclz.w", + @"xvdiv.b", + @"xvdiv.bu", + @"xvdiv.d", + @"xvdiv.du", + @"xvdiv.h", + @"xvdiv.hu", + @"xvdiv.w", + @"xvdiv.wu", + @"xvexth.d.w", + @"xvexth.du.wu", + @"xvexth.h.b", + @"xvexth.hu.bu", + @"xvexth.q.d", + @"xvexth.qu.du", + @"xvexth.w.h", + @"xvexth.wu.hu", + @"xvextl.q.d", + @"xvextl.qu.du", + @"xvextrins.b", + @"xvextrins.d", + @"xvextrins.h", + @"xvextrins.w", + @"xvfadd.d", + @"xvfadd.s", + @"xvfclass.d", + @"xvfclass.s", + @"xvfcmp.caf.d", + @"xvfcmp.caf.s", + @"xvfcmp.ceq.d", + @"xvfcmp.ceq.s", + @"xvfcmp.cle.d", + @"xvfcmp.cle.s", + @"xvfcmp.clt.d", + @"xvfcmp.clt.s", + @"xvfcmp.cne.d", + @"xvfcmp.cne.s", + @"xvfcmp.cor.d", + @"xvfcmp.cor.s", + @"xvfcmp.cueq.d", + @"xvfcmp.cueq.s", + @"xvfcmp.cule.d", + @"xvfcmp.cule.s", + @"xvfcmp.cult.d", + @"xvfcmp.cult.s", + @"xvfcmp.cun.d", + @"xvfcmp.cun.s", + @"xvfcmp.cune.d", + @"xvfcmp.cune.s", + @"xvfcmp.saf.d", + @"xvfcmp.saf.s", + @"xvfcmp.seq.d", + @"xvfcmp.seq.s", + @"xvfcmp.sle.d", + @"xvfcmp.sle.s", + @"xvfcmp.slt.d", + @"xvfcmp.slt.s", + @"xvfcmp.sne.d", + @"xvfcmp.sne.s", + @"xvfcmp.sor.d", + @"xvfcmp.sor.s", + @"xvfcmp.sueq.d", + @"xvfcmp.sueq.s", + @"xvfcmp.sule.d", + @"xvfcmp.sule.s", + @"xvfcmp.sult.d", + @"xvfcmp.sult.s", + @"xvfcmp.sun.d", + @"xvfcmp.sun.s", + @"xvfcmp.sune.d", + @"xvfcmp.sune.s", + @"xvfcvt.h.s", + @"xvfcvt.s.d", + @"xvfcvth.d.s", + @"xvfcvth.s.h", + @"xvfcvtl.d.s", + @"xvfcvtl.s.h", + @"xvfdiv.d", + @"xvfdiv.s", + @"xvffint.d.l", + @"xvffint.d.lu", + @"xvffint.s.l", + @"xvffint.s.w", + @"xvffint.s.wu", + @"xvffinth.d.w", + @"xvffintl.d.w", + @"xvflogb.d", + @"xvflogb.s", + @"xvfmadd.d", + @"xvfmadd.s", + @"xvfmax.d", + @"xvfmax.s", + @"xvfmaxa.d", + @"xvfmaxa.s", + @"xvfmin.d", + @"xvfmin.s", + @"xvfmina.d", + @"xvfmina.s", + @"xvfmsub.d", + @"xvfmsub.s", + @"xvfmul.d", + @"xvfmul.s", + @"xvfnmadd.d", + @"xvfnmadd.s", + @"xvfnmsub.d", + @"xvfnmsub.s", + @"xvfrecip.d", + @"xvfrecip.s", + @"xvfrecipe.d", + @"xvfrecipe.s", + @"xvfrint.d", + @"xvfrint.s", + @"xvfrintrm.d", + @"xvfrintrm.s", + @"xvfrintrne.d", + @"xvfrintrne.s", + @"xvfrintrp.d", + @"xvfrintrp.s", + @"xvfrintrz.d", + @"xvfrintrz.s", + @"xvfrsqrt.d", + @"xvfrsqrt.s", + @"xvfrsqrte.d", + @"xvfrsqrte.s", + @"xvfrstp.b", + @"xvfrstp.h", + @"xvfrstpi.b", + @"xvfrstpi.h", + @"xvfsqrt.d", + @"xvfsqrt.s", + @"xvfsub.d", + @"xvfsub.s", + @"xvftint.l.d", + @"xvftint.lu.d", + @"xvftint.w.d", + @"xvftint.w.s", + @"xvftint.wu.s", + @"xvftinth.l.s", + @"xvftintl.l.s", + @"xvftintrm.l.d", + @"xvftintrm.w.d", + @"xvftintrm.w.s", + @"xvftintrmh.l.s", + @"xvftintrml.l.s", + @"xvftintrne.l.d", + @"xvftintrne.w.d", + @"xvftintrne.w.s", + @"xvftintrneh.l.s", + @"xvftintrnel.l.s", + @"xvftintrp.l.d", + @"xvftintrp.w.d", + @"xvftintrp.w.s", + @"xvftintrph.l.s", + @"xvftintrpl.l.s", + @"xvftintrz.l.d", + @"xvftintrz.lu.d", + @"xvftintrz.w.d", + @"xvftintrz.w.s", + @"xvftintrz.wu.s", + @"xvftintrzh.l.s", + @"xvftintrzl.l.s", + @"xvhaddw.d.w", + @"xvhaddw.du.wu", + @"xvhaddw.h.b", + @"xvhaddw.hu.bu", + @"xvhaddw.q.d", + @"xvhaddw.qu.du", + @"xvhaddw.w.h", + @"xvhaddw.wu.hu", + @"xvhsubw.d.w", + @"xvhsubw.du.wu", + @"xvhsubw.h.b", + @"xvhsubw.hu.bu", + @"xvhsubw.q.d", + @"xvhsubw.qu.du", + @"xvhsubw.w.h", + @"xvhsubw.wu.hu", + @"xvilvh.b", + @"xvilvh.d", + @"xvilvh.h", + @"xvilvh.w", + @"xvilvl.b", + @"xvilvl.d", + @"xvilvl.h", + @"xvilvl.w", + @"xvinsgr2vr.d", + @"xvinsgr2vr.w", + @"xvinsve0.d", + @"xvinsve0.w", + xvld, + xvldi, + @"xvldrepl.b", + @"xvldrepl.d", + @"xvldrepl.h", + @"xvldrepl.w", + xvldx, + @"xvmadd.b", + @"xvmadd.d", + @"xvmadd.h", + @"xvmadd.w", + @"xvmaddwev.d.w", + @"xvmaddwev.d.wu", + @"xvmaddwev.d.wu.w", + @"xvmaddwev.h.b", + @"xvmaddwev.h.bu", + @"xvmaddwev.h.bu.b", + @"xvmaddwev.q.d", + @"xvmaddwev.q.du", + @"xvmaddwev.q.du.d", + @"xvmaddwev.w.h", + @"xvmaddwev.w.hu", + @"xvmaddwev.w.hu.h", + @"xvmaddwod.d.w", + @"xvmaddwod.d.wu", + @"xvmaddwod.d.wu.w", + @"xvmaddwod.h.b", + @"xvmaddwod.h.bu", + @"xvmaddwod.h.bu.b", + @"xvmaddwod.q.d", + @"xvmaddwod.q.du", + @"xvmaddwod.q.du.d", + @"xvmaddwod.w.h", + @"xvmaddwod.w.hu", + @"xvmaddwod.w.hu.h", + @"xvmax.b", + @"xvmax.bu", + @"xvmax.d", + @"xvmax.du", + @"xvmax.h", + @"xvmax.hu", + @"xvmax.w", + @"xvmax.wu", + @"xvmaxi.b", + @"xvmaxi.bu", + @"xvmaxi.d", + @"xvmaxi.du", + @"xvmaxi.h", + @"xvmaxi.hu", + @"xvmaxi.w", + @"xvmaxi.wu", + @"xvmepatmsk.v", + @"xvmin.b", + @"xvmin.bu", + @"xvmin.d", + @"xvmin.du", + @"xvmin.h", + @"xvmin.hu", + @"xvmin.w", + @"xvmin.wu", + @"xvmini.b", + @"xvmini.bu", + @"xvmini.d", + @"xvmini.du", + @"xvmini.h", + @"xvmini.hu", + @"xvmini.w", + @"xvmini.wu", + @"xvmod.b", + @"xvmod.bu", + @"xvmod.d", + @"xvmod.du", + @"xvmod.h", + @"xvmod.hu", + @"xvmod.w", + @"xvmod.wu", + @"xvmskgez.b", + @"xvmskltz.b", + @"xvmskltz.d", + @"xvmskltz.h", + @"xvmskltz.w", + @"xvmsknz.b", + @"xvmsub.b", + @"xvmsub.d", + @"xvmsub.h", + @"xvmsub.w", + @"xvmuh.b", + @"xvmuh.bu", + @"xvmuh.d", + @"xvmuh.du", + @"xvmuh.h", + @"xvmuh.hu", + @"xvmuh.w", + @"xvmuh.wu", + @"xvmul.b", + @"xvmul.d", + @"xvmul.h", + @"xvmul.w", + @"xvmulwev.d.w", + @"xvmulwev.d.wu", + @"xvmulwev.d.wu.w", + @"xvmulwev.h.b", + @"xvmulwev.h.bu", + @"xvmulwev.h.bu.b", + @"xvmulwev.q.d", + @"xvmulwev.q.du", + @"xvmulwev.q.du.d", + @"xvmulwev.w.h", + @"xvmulwev.w.hu", + @"xvmulwev.w.hu.h", + @"xvmulwod.d.w", + @"xvmulwod.d.wu", + @"xvmulwod.d.wu.w", + @"xvmulwod.h.b", + @"xvmulwod.h.bu", + @"xvmulwod.h.bu.b", + @"xvmulwod.q.d", + @"xvmulwod.q.du", + @"xvmulwod.q.du.d", + @"xvmulwod.w.h", + @"xvmulwod.w.hu", + @"xvmulwod.w.hu.h", + @"xvneg.b", + @"xvneg.d", + @"xvneg.h", + @"xvneg.w", + @"xvnor.v", + @"xvnori.b", + @"xvor.v", + @"xvori.b", + @"xvorn.v", + @"xvpackev.b", + @"xvpackev.d", + @"xvpackev.h", + @"xvpackev.w", + @"xvpackod.b", + @"xvpackod.d", + @"xvpackod.h", + @"xvpackod.w", + @"xvpcnt.b", + @"xvpcnt.d", + @"xvpcnt.h", + @"xvpcnt.w", + @"xvperm.w", + @"xvpermi.d", + @"xvpermi.q", + @"xvpermi.w", + @"xvpickev.b", + @"xvpickev.d", + @"xvpickev.h", + @"xvpickev.w", + @"xvpickod.b", + @"xvpickod.d", + @"xvpickod.h", + @"xvpickod.w", + @"xvpickve.d", + @"xvpickve.w", + @"xvpickve2gr.d", + @"xvpickve2gr.du", + @"xvpickve2gr.w", + @"xvpickve2gr.wu", + @"xvrepl128vei.b", + @"xvrepl128vei.d", + @"xvrepl128vei.h", + @"xvrepl128vei.w", + @"xvreplgr2vr.b", + @"xvreplgr2vr.d", + @"xvreplgr2vr.h", + @"xvreplgr2vr.w", + @"xvreplve.b", + @"xvreplve.d", + @"xvreplve.h", + @"xvreplve.w", + @"xvreplve0.b", + @"xvreplve0.d", + @"xvreplve0.h", + @"xvreplve0.q", + @"xvreplve0.w", + @"xvrotr.b", + @"xvrotr.d", + @"xvrotr.h", + @"xvrotr.w", + @"xvrotri.b", + @"xvrotri.d", + @"xvrotri.h", + @"xvrotri.w", + @"xvsadd.b", + @"xvsadd.bu", + @"xvsadd.d", + @"xvsadd.du", + @"xvsadd.h", + @"xvsadd.hu", + @"xvsadd.w", + @"xvsadd.wu", + @"xvsat.b", + @"xvsat.bu", + @"xvsat.d", + @"xvsat.du", + @"xvsat.h", + @"xvsat.hu", + @"xvsat.w", + @"xvsat.wu", + @"xvseq.b", + @"xvseq.d", + @"xvseq.h", + @"xvseq.w", + @"xvseqi.b", + @"xvseqi.d", + @"xvseqi.h", + @"xvseqi.w", + @"xvsetallnez.b", + @"xvsetallnez.d", + @"xvsetallnez.h", + @"xvsetallnez.w", + @"xvsetanyeqz.b", + @"xvsetanyeqz.d", + @"xvsetanyeqz.h", + @"xvsetanyeqz.w", + @"xvseteqz.v", + @"xvsetnez.v", + @"xvshuf.b", + @"xvshuf.d", + @"xvshuf.h", + @"xvshuf.w", + @"xvshuf4i.b", + @"xvshuf4i.d", + @"xvshuf4i.h", + @"xvshuf4i.w", + @"xvsigncov.b", + @"xvsigncov.d", + @"xvsigncov.h", + @"xvsigncov.w", + @"xvsle.b", + @"xvsle.bu", + @"xvsle.d", + @"xvsle.du", + @"xvsle.h", + @"xvsle.hu", + @"xvsle.w", + @"xvsle.wu", + @"xvslei.b", + @"xvslei.bu", + @"xvslei.d", + @"xvslei.du", + @"xvslei.h", + @"xvslei.hu", + @"xvslei.w", + @"xvslei.wu", + @"xvsll.b", + @"xvsll.d", + @"xvsll.h", + @"xvsll.w", + @"xvslli.b", + @"xvslli.d", + @"xvslli.h", + @"xvslli.w", + @"xvsllwil.d.w", + @"xvsllwil.du.wu", + @"xvsllwil.h.b", + @"xvsllwil.hu.bu", + @"xvsllwil.w.h", + @"xvsllwil.wu.hu", + @"xvslt.b", + @"xvslt.bu", + @"xvslt.d", + @"xvslt.du", + @"xvslt.h", + @"xvslt.hu", + @"xvslt.w", + @"xvslt.wu", + @"xvslti.b", + @"xvslti.bu", + @"xvslti.d", + @"xvslti.du", + @"xvslti.h", + @"xvslti.hu", + @"xvslti.w", + @"xvslti.wu", + @"xvsra.b", + @"xvsra.d", + @"xvsra.h", + @"xvsra.w", + @"xvsrai.b", + @"xvsrai.d", + @"xvsrai.h", + @"xvsrai.w", + @"xvsran.b.h", + @"xvsran.h.w", + @"xvsran.w.d", + @"xvsrani.b.h", + @"xvsrani.d.q", + @"xvsrani.h.w", + @"xvsrani.w.d", + @"xvsrar.b", + @"xvsrar.d", + @"xvsrar.h", + @"xvsrar.w", + @"xvsrari.b", + @"xvsrari.d", + @"xvsrari.h", + @"xvsrari.w", + @"xvsrarn.b.h", + @"xvsrarn.h.w", + @"xvsrarn.w.d", + @"xvsrarni.b.h", + @"xvsrarni.d.q", + @"xvsrarni.h.w", + @"xvsrarni.w.d", + @"xvsrl.b", + @"xvsrl.d", + @"xvsrl.h", + @"xvsrl.w", + @"xvsrli.b", + @"xvsrli.d", + @"xvsrli.h", + @"xvsrli.w", + @"xvsrln.b.h", + @"xvsrln.h.w", + @"xvsrln.w.d", + @"xvsrlni.b.h", + @"xvsrlni.d.q", + @"xvsrlni.h.w", + @"xvsrlni.w.d", + @"xvsrlr.b", + @"xvsrlr.d", + @"xvsrlr.h", + @"xvsrlr.w", + @"xvsrlri.b", + @"xvsrlri.d", + @"xvsrlri.h", + @"xvsrlri.w", + @"xvsrlrn.b.h", + @"xvsrlrn.h.w", + @"xvsrlrn.w.d", + @"xvsrlrni.b.h", + @"xvsrlrni.d.q", + @"xvsrlrni.h.w", + @"xvsrlrni.w.d", + @"xvssran.b.h", + @"xvssran.bu.h", + @"xvssran.h.w", + @"xvssran.hu.w", + @"xvssran.w.d", + @"xvssran.wu.d", + @"xvssrani.b.h", + @"xvssrani.bu.h", + @"xvssrani.d.q", + @"xvssrani.du.q", + @"xvssrani.h.w", + @"xvssrani.hu.w", + @"xvssrani.w.d", + @"xvssrani.wu.d", + @"xvssrarn.b.h", + @"xvssrarn.bu.h", + @"xvssrarn.h.w", + @"xvssrarn.hu.w", + @"xvssrarn.w.d", + @"xvssrarn.wu.d", + @"xvssrarni.b.h", + @"xvssrarni.bu.h", + @"xvssrarni.d.q", + @"xvssrarni.du.q", + @"xvssrarni.h.w", + @"xvssrarni.hu.w", + @"xvssrarni.w.d", + @"xvssrarni.wu.d", + @"xvssrln.b.h", + @"xvssrln.bu.h", + @"xvssrln.h.w", + @"xvssrln.hu.w", + @"xvssrln.w.d", + @"xvssrln.wu.d", + @"xvssrlni.b.h", + @"xvssrlni.bu.h", + @"xvssrlni.d.q", + @"xvssrlni.du.q", + @"xvssrlni.h.w", + @"xvssrlni.hu.w", + @"xvssrlni.w.d", + @"xvssrlni.wu.d", + @"xvssrlrn.b.h", + @"xvssrlrn.bu.h", + @"xvssrlrn.h.w", + @"xvssrlrn.hu.w", + @"xvssrlrn.w.d", + @"xvssrlrn.wu.d", + @"xvssrlrni.b.h", + @"xvssrlrni.bu.h", + @"xvssrlrni.d.q", + @"xvssrlrni.du.q", + @"xvssrlrni.h.w", + @"xvssrlrni.hu.w", + @"xvssrlrni.w.d", + @"xvssrlrni.wu.d", + @"xvssub.b", + @"xvssub.bu", + @"xvssub.d", + @"xvssub.du", + @"xvssub.h", + @"xvssub.hu", + @"xvssub.w", + @"xvssub.wu", + xvst, + @"xvstelm.b", + @"xvstelm.d", + @"xvstelm.h", + @"xvstelm.w", + xvstx, + @"xvsub.b", + @"xvsub.d", + @"xvsub.h", + @"xvsub.q", + @"xvsub.w", + @"xvsubi.bu", + @"xvsubi.du", + @"xvsubi.hu", + @"xvsubi.wu", + @"xvsubwev.d.w", + @"xvsubwev.d.wu", + @"xvsubwev.h.b", + @"xvsubwev.h.bu", + @"xvsubwev.q.d", + @"xvsubwev.q.du", + @"xvsubwev.w.h", + @"xvsubwev.w.hu", + @"xvsubwod.d.w", + @"xvsubwod.d.wu", + @"xvsubwod.h.b", + @"xvsubwod.h.bu", + @"xvsubwod.q.d", + @"xvsubwod.q.du", + @"xvsubwod.w.h", + @"xvsubwod.w.hu", + @"xvxor.v", + @"xvxori.b", + @"xxx.unknown.1", +}; + +pub const Instruction = packed union { + word: u32, + /// Fields of a `CdFj` instruction. + CdFj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CdFjFk` instruction. + CdFjFk: packed struct { rd: u3, funct3: u2, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `CdJ` instruction. + CdJ: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CdVj` instruction. + CdVj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CdXj` instruction. + CdXj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CjSd5k16` instruction. + CjSd5k16: packed struct { si5: i5, rj: u3, funct8: u2, si16: i16, funct26: u6 }, + /// Fields of a `CjSd5k16ps2` instruction. + CjSd5k16ps2: packed struct { si5: i5, rj: u3, funct8: u2, si16: i16, funct26: u6 }, + /// Fields of a `D` instruction. + D: packed struct { rd: u5, funct5: u27 }, + /// Fields of a `DCj` instruction. + DCj: packed struct { rd: u5, rj: u3, funct8: u24 }, + /// Fields of a `DFj` instruction. + DFj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `DJ` instruction. + DJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `DJK` instruction. + DJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `DJKUa2` instruction. + DJKUa2: packed struct { rd: u5, rj: u5, rk: u5, ui2: u2, funct17: u15 }, + /// Fields of a `DJKUa2pp1` instruction. + DJKUa2pp1: packed struct { rd: u5, rj: u5, rk: u5, ui2: u2, funct17: u15 }, + /// Fields of a `DJKUa3` instruction. + DJKUa3: packed struct { rd: u5, rj: u5, rk: u5, ui3: u3, funct18: u14 }, + /// Fields of a `DJSk12` instruction. + DJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `DJSk14` instruction. + DJSk14: packed struct { rd: u5, rj: u5, si14: i14, funct24: u8 }, + /// Fields of a `DJSk14ps2` instruction. + DJSk14ps2: packed struct { rd: u5, rj: u5, si14: i14, funct24: u8 }, + /// Fields of a `DJSk16` instruction. + DJSk16: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `DJSk16ps2` instruction. + DJSk16ps2: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `DJSk5` instruction. + DJSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 }, + /// Fields of a `DJUk12` instruction. + DJUk12: packed struct { rd: u5, rj: u5, ui12: u12, funct22: u10 }, + /// Fields of a `DJUk14` instruction. + DJUk14: packed struct { rd: u5, rj: u5, ui14: u14, funct24: u8 }, + /// Fields of a `DJUk3` instruction. + DJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `DJUk4` instruction. + DJUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `DJUk5` instruction. + DJUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `DJUk5Um5` instruction. + DJUk5Um5: packed struct { rd: u5, rj: u5, imm10: u5, funct15: u1, imm16: u5, funct21: u11 }, + /// Fields of a `DJUk6` instruction. + DJUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `DJUk6Um6` instruction. + DJUk6Um6: packed struct { rd: u5, rj: u5, imm10: u6, imm16: u6, funct22: u10 }, + /// Fields of a `DJUk8` instruction. + DJUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `DJUm5Uk5` instruction. + DJUm5Uk5: packed struct { rd: u5, rj: u5, imm10: u5, funct15: u1, imm16: u5, funct21: u11 }, + /// Fields of a `DJUm6Uk6` instruction. + DJUm6Uk6: packed struct { rd: u5, rj: u5, imm10: u6, imm16: u6, funct22: u10 }, + /// Fields of a `DKJ` instruction. + DKJ: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `DSj20` instruction. + DSj20: packed struct { rd: u5, si20: i20, funct25: u7 }, + /// Fields of a `DTj` instruction. + DTj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `DUj5` instruction. + DUj5: packed struct { rd: u5, ui5: u5, funct10: u22 }, + /// Fields of a `DUj5Uk8` instruction. + DUj5Uk8: packed struct { rd: u5, ui5: u5, ui8: u8, funct18: u14 }, + /// Fields of a `DUk14` instruction. + DUk14: packed struct { rd: u5, funct5: u5, ui14: u14, funct24: u8 }, + /// Fields of a `DUk4` instruction. + DUk4: packed struct { rd: u5, funct5: u5, ui4: u4, funct14: u18 }, + /// Fields of a `DUk8` instruction. + DUk8: packed struct { rd: u5, funct5: u5, ui8: u8, funct18: u14 }, + /// Fields of a `DVjUk1` instruction. + DVjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `DVjUk2` instruction. + DVjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `DVjUk3` instruction. + DVjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `DVjUk4` instruction. + DVjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `DXjUk2` instruction. + DXjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `DXjUk3` instruction. + DXjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `FdCj` instruction. + FdCj: packed struct { rd: u5, rj: u3, funct8: u24 }, + /// Fields of a `FdFj` instruction. + FdFj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `FdFjFk` instruction. + FdFjFk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `FdFjFkCa` instruction. + FdFjFkCa: packed struct { rd: u5, rj: u5, rk: u5, ra: u3, funct18: u14 }, + /// Fields of a `FdFjFkFa` instruction. + FdFjFkFa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 }, + /// Fields of a `FdJ` instruction. + FdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `FdJK` instruction. + FdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `FdJSk12` instruction. + FdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `J` instruction. + J: packed struct { funct0: u5, rj: u5, funct10: u22 }, + /// Fields of a `JDSk16ps2` instruction. + JDSk16ps2: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `JK` instruction. + JK: packed struct { funct0: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `JKUd4` instruction. + JKUd4: packed struct { ui4: u4, funct4: u1, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `JKUd5` instruction. + JKUd5: packed struct { ui5: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `JSd5k16` instruction. + JSd5k16: packed struct { si5: i5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `JSd5k16ps2` instruction. + JSd5k16ps2: packed struct { si5: i5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `JUd4Uk5` instruction. + JUd4Uk5: packed struct { ui4: u4, funct4: u1, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `JUd5` instruction. + JUd5: packed struct { ui5: u5, rj: u5, funct10: u22 }, + /// Fields of a `JUd5Sk12` instruction. + JUd5Sk12: packed struct { ui5: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `JUk3` instruction. + JUk3: packed struct { funct0: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `JUk4` instruction. + JUk4: packed struct { funct0: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `JUk5` instruction. + JUk5: packed struct { funct0: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `JUk5Ud4` instruction. + JUk5Ud4: packed struct { ui4: u4, funct4: u1, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `JUk6` instruction. + JUk6: packed struct { funct0: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `JUk8` instruction. + JUk8: packed struct { funct0: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `Sd10k16` instruction. + Sd10k16: packed struct { si10: i10, si16: i16, funct26: u6 }, + /// Fields of a `Sd10k16ps2` instruction. + Sd10k16ps2: packed struct { si10: i10, si16: i16, funct26: u6 }, + /// Fields of a `Sd5k16` instruction. + Sd5k16: packed struct { si5: i5, funct5: u5, si16: i16, funct26: u6 }, + /// Fields of a `Sd5k16ps2` instruction. + Sd5k16ps2: packed struct { si5: i5, funct5: u5, si16: i16, funct26: u6 }, + /// Fields of a `TdJ` instruction. + TdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `Ud15` instruction. + Ud15: packed struct { ui15: u15, funct15: u17 }, + /// Fields of a `Ud5JK` instruction. + Ud5JK: packed struct { ui5: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `Ud5JSk12` instruction. + Ud5JSk12: packed struct { ui5: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `Uj3` instruction. + Uj3: packed struct { funct0: u5, ui3: u3, funct8: u24 }, + /// Fields of a `VdJ` instruction. + VdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `VdJK` instruction. + VdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `VdJSk10` instruction. + VdJSk10: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `VdJSk10ps2` instruction. + VdJSk10ps2: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `VdJSk11` instruction. + VdJSk11: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `VdJSk11ps1` instruction. + VdJSk11ps1: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `VdJSk12` instruction. + VdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `VdJSk8Un1` instruction. + VdJSk8Un1: packed struct { rd: u5, rj: u5, si8: i8, ui1: u1, funct19: u13 }, + /// Fields of a `VdJSk8Un2` instruction. + VdJSk8Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `VdJSk8Un3` instruction. + VdJSk8Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `VdJSk8Un4` instruction. + VdJSk8Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 }, + /// Fields of a `VdJSk8ps1Un3` instruction. + VdJSk8ps1Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `VdJSk8ps2Un2` instruction. + VdJSk8ps2Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `VdJSk8ps3Un1` instruction. + VdJSk8ps3Un1: packed struct { rd: u5, rj: u5, si8: i8, ui1: u1, funct19: u13 }, + /// Fields of a `VdJSk9` instruction. + VdJSk9: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `VdJSk9ps3` instruction. + VdJSk9ps3: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `VdJUk1` instruction. + VdJUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `VdJUk2` instruction. + VdJUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `VdJUk3` instruction. + VdJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `VdJUk4` instruction. + VdJUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `VdSj13` instruction. + VdSj13: packed struct { rd: u5, si13: i13, funct18: u14 }, + /// Fields of a `VdUj5Uk5` instruction. + VdUj5Uk5: packed struct { rd: u5, imm5: u5, imm10: u5, funct15: u17 }, + /// Fields of a `VdVj` instruction. + VdVj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `VdVjK` instruction. + VdVjK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `VdVjSk5` instruction. + VdVjSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 }, + /// Fields of a `VdVjUk1` instruction. + VdVjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `VdVjUk2` instruction. + VdVjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `VdVjUk3` instruction. + VdVjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `VdVjUk4` instruction. + VdVjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `VdVjUk5` instruction. + VdVjUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `VdVjUk6` instruction. + VdVjUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `VdVjUk7` instruction. + VdVjUk7: packed struct { rd: u5, rj: u5, ui7: u7, funct17: u15 }, + /// Fields of a `VdVjUk8` instruction. + VdVjUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `VdVjVk` instruction. + VdVjVk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `VdVjVkVa` instruction. + VdVjVkVa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 }, + /// Fields of a `XdJ` instruction. + XdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `XdJK` instruction. + XdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `XdJSk10` instruction. + XdJSk10: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `XdJSk10ps2` instruction. + XdJSk10ps2: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `XdJSk11` instruction. + XdJSk11: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `XdJSk11ps1` instruction. + XdJSk11ps1: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `XdJSk12` instruction. + XdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `XdJSk8Un2` instruction. + XdJSk8Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `XdJSk8Un3` instruction. + XdJSk8Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `XdJSk8Un4` instruction. + XdJSk8Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 }, + /// Fields of a `XdJSk8Un5` instruction. + XdJSk8Un5: packed struct { rd: u5, rj: u5, si8: i8, ui5: u5, funct23: u9 }, + /// Fields of a `XdJSk8ps1Un4` instruction. + XdJSk8ps1Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 }, + /// Fields of a `XdJSk8ps2Un3` instruction. + XdJSk8ps2Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `XdJSk8ps3Un2` instruction. + XdJSk8ps3Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `XdJSk9` instruction. + XdJSk9: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `XdJSk9ps3` instruction. + XdJSk9ps3: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `XdJUk2` instruction. + XdJUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `XdJUk3` instruction. + XdJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `XdSj13` instruction. + XdSj13: packed struct { rd: u5, si13: i13, funct18: u14 }, + /// Fields of a `XdUj5Uk5` instruction. + XdUj5Uk5: packed struct { rd: u5, imm5: u5, imm10: u5, funct15: u17 }, + /// Fields of a `XdXj` instruction. + XdXj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `XdXjK` instruction. + XdXjK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `XdXjSk5` instruction. + XdXjSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 }, + /// Fields of a `XdXjUk1` instruction. + XdXjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `XdXjUk2` instruction. + XdXjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `XdXjUk3` instruction. + XdXjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `XdXjUk4` instruction. + XdXjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `XdXjUk5` instruction. + XdXjUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `XdXjUk6` instruction. + XdXjUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `XdXjUk7` instruction. + XdXjUk7: packed struct { rd: u5, rj: u5, ui7: u7, funct17: u15 }, + /// Fields of a `XdXjUk8` instruction. + XdXjUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `XdXjXk` instruction. + XdXjXk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `XdXjXkXa` instruction. + XdXjXkXa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 }, + + /// Encodes a `CdFj` instruction. + pub inline fn encodeCdFj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CdFjFk` instruction. + pub inline fn encodeCdFjFk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `CdJ` instruction. + pub inline fn encodeCdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CdVj` instruction. + pub inline fn encodeCdVj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CdXj` instruction. + pub inline fn encodeCdXj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CjSd5k16` instruction. + pub inline fn encodeCjSd5k16(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `CjSd5k16ps2` instruction. + pub inline fn encodeCjSd5k16ps2(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `D` instruction. + pub inline fn encodeD(word: u32, p0: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) }; + } + + /// Encodes a `DCj` instruction. + pub inline fn encodeDCj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DFj` instruction. + pub inline fn encodeDFj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DJ` instruction. + pub inline fn encodeDJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DJK` instruction. + pub inline fn encodeDJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `DJKUa2` instruction. + pub inline fn encodeDJKUa2(word: u32, p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 15) }; + } + + /// Encodes a `DJKUa2pp1` instruction. + pub inline fn encodeDJKUa2pp1(word: u32, p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + ((@as(u32, @as(u2, @bitCast(p3))) - 1) << 15) }; + } + + /// Encodes a `DJKUa3` instruction. + pub inline fn encodeDJKUa3(word: u32, p0: Register, p1: Register, p2: Register, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 15) }; + } + + /// Encodes a `DJSk12` instruction. + pub inline fn encodeDJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJSk14` instruction. + pub inline fn encodeDJSk14(word: u32, p0: Register, p1: Register, p2: i14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u14, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJSk14ps2` instruction. + pub inline fn encodeDJSk14ps2(word: u32, p0: Register, p1: Register, p2: i14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u14, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `DJSk16` instruction. + pub inline fn encodeDJSk16(word: u32, p0: Register, p1: Register, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u16, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJSk16ps2` instruction. + pub inline fn encodeDJSk16ps2(word: u32, p0: Register, p1: Register, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `DJSk5` instruction. + pub inline fn encodeDJSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk12` instruction. + pub inline fn encodeDJUk12(word: u32, p0: Register, p1: Register, p2: u12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk14` instruction. + pub inline fn encodeDJUk14(word: u32, p0: Register, p1: Register, p2: u14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u14, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk3` instruction. + pub inline fn encodeDJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk4` instruction. + pub inline fn encodeDJUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk5` instruction. + pub inline fn encodeDJUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk5Um5` instruction. + pub inline fn encodeDJUk5Um5(word: u32, p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u5, @bitCast(p3)))) << 16) }; + } + + /// Encodes a `DJUk6` instruction. + pub inline fn encodeDJUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk6Um6` instruction. + pub inline fn encodeDJUk6Um6(word: u32, p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u6, @bitCast(p3)))) << 16) }; + } + + /// Encodes a `DJUk8` instruction. + pub inline fn encodeDJUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUm5Uk5` instruction. + pub inline fn encodeDJUm5Uk5(word: u32, p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 16) | + ((@as(u32, @as(u5, @bitCast(p3)))) << 10) }; + } + + /// Encodes a `DJUm6Uk6` instruction. + pub inline fn encodeDJUm6Uk6(word: u32, p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 16) | + ((@as(u32, @as(u6, @bitCast(p3)))) << 10) }; + } + + /// Encodes a `DKJ` instruction. + pub inline fn encodeDKJ(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 10) | + (@as(u32, p2.encode()) << 5) }; + } + + /// Encodes a `DSj20` instruction. + pub inline fn encodeDSj20(word: u32, p0: Register, p1: i20) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u20, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `DTj` instruction. + pub inline fn encodeDTj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DUj5` instruction. + pub inline fn encodeDUj5(word: u32, p0: Register, p1: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `DUj5Uk8` instruction. + pub inline fn encodeDUj5Uk8(word: u32, p0: Register, p1: u5, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DUk14` instruction. + pub inline fn encodeDUk14(word: u32, p0: Register, p1: u14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u14, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `DUk4` instruction. + pub inline fn encodeDUk4(word: u32, p0: Register, p1: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u4, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `DUk8` instruction. + pub inline fn encodeDUk8(word: u32, p0: Register, p1: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u8, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `DVjUk1` instruction. + pub inline fn encodeDVjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DVjUk2` instruction. + pub inline fn encodeDVjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DVjUk3` instruction. + pub inline fn encodeDVjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DVjUk4` instruction. + pub inline fn encodeDVjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DXjUk2` instruction. + pub inline fn encodeDXjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DXjUk3` instruction. + pub inline fn encodeDXjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `EMPTY` instruction. + pub inline fn encodeEMPTY(word: u32) Instruction { + return .{ .word = word }; + } + + /// Encodes a `FdCj` instruction. + pub inline fn encodeFdCj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `FdFj` instruction. + pub inline fn encodeFdFj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `FdFjFk` instruction. + pub inline fn encodeFdFjFk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `FdFjFkCa` instruction. + pub inline fn encodeFdFjFkCa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `FdFjFkFa` instruction. + pub inline fn encodeFdFjFkFa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `FdJ` instruction. + pub inline fn encodeFdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `FdJK` instruction. + pub inline fn encodeFdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `FdJSk12` instruction. + pub inline fn encodeFdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `J` instruction. + pub inline fn encodeJ(word: u32, p0: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) }; + } + + /// Encodes a `JDSk16ps2` instruction. + pub inline fn encodeJDSk16ps2(word: u32, p0: Register, p1: Register, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 0) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `JK` instruction. + pub inline fn encodeJK(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 10) }; + } + + /// Encodes a `JKUd4` instruction. + pub inline fn encodeJKUd4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 10) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 0) }; + } + + /// Encodes a `JKUd5` instruction. + pub inline fn encodeJKUd5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 10) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 0) }; + } + + /// Encodes a `JSd5k16` instruction. + pub inline fn encodeJSd5k16(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `JSd5k16ps2` instruction. + pub inline fn encodeJSd5k16ps2(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `JUd4Uk5` instruction. + pub inline fn encodeJUd4Uk5(word: u32, p0: Register, p1: u4, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `JUd5` instruction. + pub inline fn encodeJUd5(word: u32, p0: Register, p1: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) }; + } + + /// Encodes a `JUd5Sk12` instruction. + pub inline fn encodeJUd5Sk12(word: u32, p0: Register, p1: u5, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `JUk3` instruction. + pub inline fn encodeJUk3(word: u32, p0: Register, p1: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk4` instruction. + pub inline fn encodeJUk4(word: u32, p0: Register, p1: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk5` instruction. + pub inline fn encodeJUk5(word: u32, p0: Register, p1: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk5Ud4` instruction. + pub inline fn encodeJUk5Ud4(word: u32, p0: Register, p1: u5, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 10) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 0) }; + } + + /// Encodes a `JUk6` instruction. + pub inline fn encodeJUk6(word: u32, p0: Register, p1: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk8` instruction. + pub inline fn encodeJUk8(word: u32, p0: Register, p1: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `Sd10k16` instruction. + pub inline fn encodeSd10k16(word: u32, p0: i10, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u10, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `Sd10k16ps2` instruction. + pub inline fn encodeSd10k16ps2(word: u32, p0: i10, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u10, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1))) >> 2) << 10) }; + } + + /// Encodes a `Sd5k16` instruction. + pub inline fn encodeSd5k16(word: u32, p0: i5, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `Sd5k16ps2` instruction. + pub inline fn encodeSd5k16ps2(word: u32, p0: i5, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1))) >> 2) << 10) }; + } + + /// Encodes a `TdJ` instruction. + pub inline fn encodeTdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `Ud15` instruction. + pub inline fn encodeUd15(word: u32, p0: u15) Instruction { + return .{ .word = word | + ((@as(u32, @as(u15, @bitCast(p0)))) << 0) }; + } + + /// Encodes a `Ud5JK` instruction. + pub inline fn encodeUd5JK(word: u32, p0: u5, p1: Register, p2: Register) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `Ud5JSk12` instruction. + pub inline fn encodeUd5JSk12(word: u32, p0: u5, p1: Register, p2: i12) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `Uj3` instruction. + pub inline fn encodeUj3(word: u32, p0: u3) Instruction { + return .{ .word = word | + ((@as(u32, @as(u3, @bitCast(p0)))) << 5) }; + } + + /// Encodes a `VdJ` instruction. + pub inline fn encodeVdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `VdJK` instruction. + pub inline fn encodeVdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `VdJSk10` instruction. + pub inline fn encodeVdJSk10(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk10ps2` instruction. + pub inline fn encodeVdJSk10ps2(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `VdJSk11` instruction. + pub inline fn encodeVdJSk11(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk11ps1` instruction. + pub inline fn encodeVdJSk11ps1(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2))) >> 1) << 10) }; + } + + /// Encodes a `VdJSk12` instruction. + pub inline fn encodeVdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk8Un1` instruction. + pub inline fn encodeVdJSk8Un1(word: u32, p0: Register, p1: Register, p2: i8, p3: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u1, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8Un2` instruction. + pub inline fn encodeVdJSk8Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8Un3` instruction. + pub inline fn encodeVdJSk8Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8Un4` instruction. + pub inline fn encodeVdJSk8Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u4, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8ps1Un3` instruction. + pub inline fn encodeVdJSk8ps1Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 1) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8ps2Un2` instruction. + pub inline fn encodeVdJSk8ps2Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 2) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8ps3Un1` instruction. + pub inline fn encodeVdJSk8ps3Un1(word: u32, p0: Register, p1: Register, p2: i8, p3: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 3) << 10) | + ((@as(u32, @as(u1, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk9` instruction. + pub inline fn encodeVdJSk9(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk9ps3` instruction. + pub inline fn encodeVdJSk9ps3(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2))) >> 3) << 10) }; + } + + /// Encodes a `VdJUk1` instruction. + pub inline fn encodeVdJUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJUk2` instruction. + pub inline fn encodeVdJUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJUk3` instruction. + pub inline fn encodeVdJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJUk4` instruction. + pub inline fn encodeVdJUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdSj13` instruction. + pub inline fn encodeVdSj13(word: u32, p0: Register, p1: i13) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u13, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `VdUj5Uk5` instruction. + pub inline fn encodeVdUj5Uk5(word: u32, p0: Register, p1: u5, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVj` instruction. + pub inline fn encodeVdVj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `VdVjK` instruction. + pub inline fn encodeVdVjK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `VdVjSk5` instruction. + pub inline fn encodeVdVjSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk1` instruction. + pub inline fn encodeVdVjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk2` instruction. + pub inline fn encodeVdVjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk3` instruction. + pub inline fn encodeVdVjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk4` instruction. + pub inline fn encodeVdVjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk5` instruction. + pub inline fn encodeVdVjUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk6` instruction. + pub inline fn encodeVdVjUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk7` instruction. + pub inline fn encodeVdVjUk7(word: u32, p0: Register, p1: Register, p2: u7) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u7, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk8` instruction. + pub inline fn encodeVdVjUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjVk` instruction. + pub inline fn encodeVdVjVk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `VdVjVkVa` instruction. + pub inline fn encodeVdVjVkVa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `XdJ` instruction. + pub inline fn encodeXdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `XdJK` instruction. + pub inline fn encodeXdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `XdJSk10` instruction. + pub inline fn encodeXdJSk10(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk10ps2` instruction. + pub inline fn encodeXdJSk10ps2(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `XdJSk11` instruction. + pub inline fn encodeXdJSk11(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk11ps1` instruction. + pub inline fn encodeXdJSk11ps1(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2))) >> 1) << 10) }; + } + + /// Encodes a `XdJSk12` instruction. + pub inline fn encodeXdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk8Un2` instruction. + pub inline fn encodeXdJSk8Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8Un3` instruction. + pub inline fn encodeXdJSk8Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8Un4` instruction. + pub inline fn encodeXdJSk8Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u4, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8Un5` instruction. + pub inline fn encodeXdJSk8Un5(word: u32, p0: Register, p1: Register, p2: i8, p3: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u5, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8ps1Un4` instruction. + pub inline fn encodeXdJSk8ps1Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 1) << 10) | + ((@as(u32, @as(u4, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8ps2Un3` instruction. + pub inline fn encodeXdJSk8ps2Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 2) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8ps3Un2` instruction. + pub inline fn encodeXdJSk8ps3Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 3) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk9` instruction. + pub inline fn encodeXdJSk9(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk9ps3` instruction. + pub inline fn encodeXdJSk9ps3(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2))) >> 3) << 10) }; + } + + /// Encodes a `XdJUk2` instruction. + pub inline fn encodeXdJUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJUk3` instruction. + pub inline fn encodeXdJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdSj13` instruction. + pub inline fn encodeXdSj13(word: u32, p0: Register, p1: i13) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u13, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `XdUj5Uk5` instruction. + pub inline fn encodeXdUj5Uk5(word: u32, p0: Register, p1: u5, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXj` instruction. + pub inline fn encodeXdXj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `XdXjK` instruction. + pub inline fn encodeXdXjK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `XdXjSk5` instruction. + pub inline fn encodeXdXjSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk1` instruction. + pub inline fn encodeXdXjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk2` instruction. + pub inline fn encodeXdXjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk3` instruction. + pub inline fn encodeXdXjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk4` instruction. + pub inline fn encodeXdXjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk5` instruction. + pub inline fn encodeXdXjUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk6` instruction. + pub inline fn encodeXdXjUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk7` instruction. + pub inline fn encodeXdXjUk7(word: u32, p0: Register, p1: Register, p2: u7) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u7, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk8` instruction. + pub inline fn encodeXdXjUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjXk` instruction. + pub inline fn encodeXdXjXk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `XdXjXkXa` instruction. + pub inline fn encodeXdXjXkXa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `adc.b` instruction (requires 64bit). + pub inline fn @"adc.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00300000, p0, p1, p2); + } + + /// Encodes a `adc.d` instruction (requires 64bit). + pub inline fn @"adc.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00318000, p0, p1, p2); + } + + /// Encodes a `adc.h` instruction (requires 64bit). + pub inline fn @"adc.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00308000, p0, p1, p2); + } + + /// Encodes a `adc.w` instruction (requires 64bit). + pub inline fn @"adc.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00310000, p0, p1, p2); + } + + /// Encodes a `add.d` instruction (requires 64bit). + pub inline fn @"add.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00108000, p0, p1, p2); + } + + /// Encodes a `add.w` instruction (requires 32bit). + pub inline fn @"add.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00100000, p0, p1, p2); + } + + /// Encodes a `addi.d` instruction (requires 64bit). + pub inline fn @"addi.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02c00000, p0, p1, p2); + } + + /// Encodes a `addi.w` instruction (requires 32bit). + pub inline fn @"addi.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02800000, p0, p1, p2); + } + + /// Encodes a `addu12i.d` instruction (requires 64bit). + pub inline fn @"addu12i.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeDJSk5(0x00298000, p0, p1, p2); + } + + /// Encodes a `addu12i.w` instruction (requires 64bit). + pub inline fn @"addu12i.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeDJSk5(0x00290000, p0, p1, p2); + } + + /// Encodes a `addu16i.d` instruction (requires 64bit). + pub inline fn @"addu16i.d"(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x10000000, p0, p1, p2); + } + + /// Encodes a `amadd.b` instruction (requires 64bit). + pub inline fn @"amadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385d0000, p0, p1, p2); + } + + /// Encodes a `amadd.d` instruction (requires 64bit). + pub inline fn @"amadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38618000, p0, p1, p2); + } + + /// Encodes a `amadd.h` instruction (requires 64bit). + pub inline fn @"amadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385d8000, p0, p1, p2); + } + + /// Encodes a `amadd.w` instruction (requires 64bit). + pub inline fn @"amadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38610000, p0, p1, p2); + } + + /// Encodes a `amadd_db.b` instruction (requires 64bit). + pub inline fn @"amadd_db.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385f0000, p0, p1, p2); + } + + /// Encodes a `amadd_db.d` instruction (requires 64bit). + pub inline fn @"amadd_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386a8000, p0, p1, p2); + } + + /// Encodes a `amadd_db.h` instruction (requires 64bit). + pub inline fn @"amadd_db.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385f8000, p0, p1, p2); + } + + /// Encodes a `amadd_db.w` instruction (requires 64bit). + pub inline fn @"amadd_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386a0000, p0, p1, p2); + } + + /// Encodes a `amand.d` instruction (requires 64bit). + pub inline fn @"amand.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38628000, p0, p1, p2); + } + + /// Encodes a `amand.w` instruction (requires 64bit). + pub inline fn @"amand.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38620000, p0, p1, p2); + } + + /// Encodes a `amand_db.d` instruction (requires 64bit). + pub inline fn @"amand_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386b8000, p0, p1, p2); + } + + /// Encodes a `amand_db.w` instruction (requires 64bit). + pub inline fn @"amand_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386b0000, p0, p1, p2); + } + + /// Encodes a `amcas.b` instruction (requires 64bit). + pub inline fn @"amcas.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38580000, p0, p1, p2); + } + + /// Encodes a `amcas.d` instruction (requires 64bit). + pub inline fn @"amcas.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38598000, p0, p1, p2); + } + + /// Encodes a `amcas.h` instruction (requires 64bit). + pub inline fn @"amcas.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38588000, p0, p1, p2); + } + + /// Encodes a `amcas.w` instruction (requires 64bit). + pub inline fn @"amcas.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38590000, p0, p1, p2); + } + + /// Encodes a `amcas_db.b` instruction (requires 64bit). + pub inline fn @"amcas_db.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385a0000, p0, p1, p2); + } + + /// Encodes a `amcas_db.d` instruction (requires 64bit). + pub inline fn @"amcas_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385b8000, p0, p1, p2); + } + + /// Encodes a `amcas_db.h` instruction (requires 64bit). + pub inline fn @"amcas_db.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385a8000, p0, p1, p2); + } + + /// Encodes a `amcas_db.w` instruction (requires 64bit). + pub inline fn @"amcas_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385b0000, p0, p1, p2); + } + + /// Encodes a `ammax.d` instruction (requires 64bit). + pub inline fn @"ammax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38658000, p0, p1, p2); + } + + /// Encodes a `ammax.du` instruction (requires 64bit). + pub inline fn @"ammax.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38678000, p0, p1, p2); + } + + /// Encodes a `ammax.w` instruction (requires 64bit). + pub inline fn @"ammax.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38650000, p0, p1, p2); + } + + /// Encodes a `ammax.wu` instruction (requires 64bit). + pub inline fn @"ammax.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38670000, p0, p1, p2); + } + + /// Encodes a `ammax_db.d` instruction (requires 64bit). + pub inline fn @"ammax_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386e8000, p0, p1, p2); + } + + /// Encodes a `ammax_db.du` instruction (requires 64bit). + pub inline fn @"ammax_db.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38708000, p0, p1, p2); + } + + /// Encodes a `ammax_db.w` instruction (requires 64bit). + pub inline fn @"ammax_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386e0000, p0, p1, p2); + } + + /// Encodes a `ammax_db.wu` instruction (requires 64bit). + pub inline fn @"ammax_db.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38700000, p0, p1, p2); + } + + /// Encodes a `ammin.d` instruction (requires 64bit). + pub inline fn @"ammin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38668000, p0, p1, p2); + } + + /// Encodes a `ammin.du` instruction (requires 64bit). + pub inline fn @"ammin.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38688000, p0, p1, p2); + } + + /// Encodes a `ammin.w` instruction (requires 64bit). + pub inline fn @"ammin.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38660000, p0, p1, p2); + } + + /// Encodes a `ammin.wu` instruction (requires 64bit). + pub inline fn @"ammin.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38680000, p0, p1, p2); + } + + /// Encodes a `ammin_db.d` instruction (requires 64bit). + pub inline fn @"ammin_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386f8000, p0, p1, p2); + } + + /// Encodes a `ammin_db.du` instruction (requires 64bit). + pub inline fn @"ammin_db.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38718000, p0, p1, p2); + } + + /// Encodes a `ammin_db.w` instruction (requires 64bit). + pub inline fn @"ammin_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386f0000, p0, p1, p2); + } + + /// Encodes a `ammin_db.wu` instruction (requires 64bit). + pub inline fn @"ammin_db.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38710000, p0, p1, p2); + } + + /// Encodes a `amor.d` instruction (requires 64bit). + pub inline fn @"amor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38638000, p0, p1, p2); + } + + /// Encodes a `amor.w` instruction (requires 64bit). + pub inline fn @"amor.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38630000, p0, p1, p2); + } + + /// Encodes a `amor_db.d` instruction (requires 64bit). + pub inline fn @"amor_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386c8000, p0, p1, p2); + } + + /// Encodes a `amor_db.w` instruction (requires 64bit). + pub inline fn @"amor_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386c0000, p0, p1, p2); + } + + /// Encodes a `amswap.b` instruction (requires 64bit). + pub inline fn @"amswap.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385c0000, p0, p1, p2); + } + + /// Encodes a `amswap.d` instruction (requires 64bit). + pub inline fn @"amswap.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38608000, p0, p1, p2); + } + + /// Encodes a `amswap.h` instruction (requires 64bit). + pub inline fn @"amswap.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385c8000, p0, p1, p2); + } + + /// Encodes a `amswap.w` instruction (requires 64bit). + pub inline fn @"amswap.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38600000, p0, p1, p2); + } + + /// Encodes a `amswap_db.b` instruction (requires 64bit). + pub inline fn @"amswap_db.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385e0000, p0, p1, p2); + } + + /// Encodes a `amswap_db.d` instruction (requires 64bit). + pub inline fn @"amswap_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38698000, p0, p1, p2); + } + + /// Encodes a `amswap_db.h` instruction (requires 64bit). + pub inline fn @"amswap_db.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385e8000, p0, p1, p2); + } + + /// Encodes a `amswap_db.w` instruction (requires 64bit). + pub inline fn @"amswap_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38690000, p0, p1, p2); + } + + /// Encodes a `amxor.d` instruction (requires 64bit). + pub inline fn @"amxor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38648000, p0, p1, p2); + } + + /// Encodes a `amxor.w` instruction (requires 64bit). + pub inline fn @"amxor.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38640000, p0, p1, p2); + } + + /// Encodes a `amxor_db.d` instruction (requires 64bit). + pub inline fn @"amxor_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386d8000, p0, p1, p2); + } + + /// Encodes a `amxor_db.w` instruction (requires 64bit). + pub inline fn @"amxor_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386d0000, p0, p1, p2); + } + + /// Encodes a `and` instruction (requires 32bit). + pub inline fn @"and"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00148000, p0, p1, p2); + } + + /// Encodes a `andi` instruction (requires 32bit). + pub inline fn andi(p0: Register, p1: Register, p2: u12) Instruction { + return encodeDJUk12(0x03400000, p0, p1, p2); + } + + /// Encodes a `andn` instruction (requires 32bit). + pub inline fn andn(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00168000, p0, p1, p2); + } + + /// Encodes a `armadc.w` instruction (requires 64bit). + pub inline fn @"armadc.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00380010, p0, p1, p2); + } + + /// Encodes a `armadd.w` instruction (requires 64bit). + pub inline fn @"armadd.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00370010, p0, p1, p2); + } + + /// Encodes a `armand.w` instruction (requires 64bit). + pub inline fn @"armand.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00390010, p0, p1, p2); + } + + /// Encodes a `armmfflag` instruction (requires 64bit). + pub inline fn armmfflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0040, p0, p1); + } + + /// Encodes a `armmov.d` instruction (requires 64bit). + pub inline fn @"armmov.d"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01e, p0, p1); + } + + /// Encodes a `armmov.w` instruction (requires 64bit). + pub inline fn @"armmov.w"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01d, p0, p1); + } + + /// Encodes a `armmove` instruction (requires 64bit). + pub inline fn armmove(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDJUk4(0x00364000, p0, p1, p2); + } + + /// Encodes a `armmtflag` instruction (requires 64bit). + pub inline fn armmtflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0060, p0, p1); + } + + /// Encodes a `armnot.w` instruction (requires 64bit). + pub inline fn @"armnot.w"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01c, p0, p1); + } + + /// Encodes a `armor.w` instruction (requires 64bit). + pub inline fn @"armor.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00398010, p0, p1, p2); + } + + /// Encodes a `armrotr.w` instruction (requires 64bit). + pub inline fn @"armrotr.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003c0010, p0, p1, p2); + } + + /// Encodes a `armrotri.w` instruction (requires 64bit). + pub inline fn @"armrotri.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003e0010, p0, p1, p2); + } + + /// Encodes a `armrrx.w` instruction (requires 64bit). + pub inline fn @"armrrx.w"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01f, p0, p1); + } + + /// Encodes a `armsbc.w` instruction (requires 64bit). + pub inline fn @"armsbc.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00388010, p0, p1, p2); + } + + /// Encodes a `armsetj` instruction (requires 64bit). + pub inline fn armsetj(p0: Register, p1: u4) Instruction { + return encodeDUk4(0x0036c000, p0, p1); + } + + /// Encodes a `armsll.w` instruction (requires 64bit). + pub inline fn @"armsll.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003a8010, p0, p1, p2); + } + + /// Encodes a `armslli.w` instruction (requires 64bit). + pub inline fn @"armslli.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003c8010, p0, p1, p2); + } + + /// Encodes a `armsra.w` instruction (requires 64bit). + pub inline fn @"armsra.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003b8010, p0, p1, p2); + } + + /// Encodes a `armsrai.w` instruction (requires 64bit). + pub inline fn @"armsrai.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003d8010, p0, p1, p2); + } + + /// Encodes a `armsrl.w` instruction (requires 64bit). + pub inline fn @"armsrl.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003b0010, p0, p1, p2); + } + + /// Encodes a `armsrli.w` instruction (requires 64bit). + pub inline fn @"armsrli.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003d0010, p0, p1, p2); + } + + /// Encodes a `armsub.w` instruction (requires 64bit). + pub inline fn @"armsub.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00378010, p0, p1, p2); + } + + /// Encodes a `armxor.w` instruction (requires 64bit). + pub inline fn @"armxor.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003a0010, p0, p1, p2); + } + + /// Encodes a `asrtgt` instruction (requires 64bit). + pub inline fn asrtgt(p0: Register, p1: Register) Instruction { + return encodeJK(0x00018000, p0, p1); + } + + /// Encodes a `asrtle` instruction (requires 64bit). + pub inline fn asrtle(p0: Register, p1: Register) Instruction { + return encodeJK(0x00010000, p0, p1); + } + + /// Encodes a `b` instruction (requires 32bit). + pub inline fn b(p0: i10, p1: i16) Instruction { + return encodeSd10k16ps2(0x50000000, p0, p1); + } + + /// Encodes a `bceqz` instruction (requires f). + pub inline fn bceqz(p0: Register, p1: i5, p2: i16) Instruction { + return encodeCjSd5k16ps2(0x48000000, p0, p1, p2); + } + + /// Encodes a `bcnez` instruction (requires f). + pub inline fn bcnez(p0: Register, p1: i5, p2: i16) Instruction { + return encodeCjSd5k16ps2(0x48000100, p0, p1, p2); + } + + /// Encodes a `beq` instruction (requires 32bit). + pub inline fn beq(p0: Register, p1: Register, p2: i16) Instruction { + return encodeJDSk16ps2(0x58000000, p0, p1, p2); + } + + /// Encodes a `beqz` instruction (requires 32s). + pub inline fn beqz(p0: Register, p1: i5, p2: i16) Instruction { + return encodeJSd5k16ps2(0x40000000, p0, p1, p2); + } + + /// Encodes a `bgt` instruction (requires 32bit). + pub inline fn bgt(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x60000000, p0, p1, p2); + } + + /// Encodes a `bgtu` instruction (requires 32bit). + pub inline fn bgtu(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x68000000, p0, p1, p2); + } + + /// Encodes a `bl` instruction (requires 32bit). + pub inline fn bl(p0: i10, p1: i16) Instruction { + return encodeSd10k16ps2(0x54000000, p0, p1); + } + + /// Encodes a `ble` instruction (requires 32bit). + pub inline fn ble(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x64000000, p0, p1, p2); + } + + /// Encodes a `bleu` instruction (requires 32bit). + pub inline fn bleu(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x6c000000, p0, p1, p2); + } + + /// Encodes a `bne` instruction (requires 32bit). + pub inline fn bne(p0: Register, p1: Register, p2: i16) Instruction { + return encodeJDSk16ps2(0x5c000000, p0, p1, p2); + } + + /// Encodes a `bnez` instruction (requires 32s). + pub inline fn bnez(p0: Register, p1: i5, p2: i16) Instruction { + return encodeJSd5k16ps2(0x44000000, p0, p1, p2); + } + + /// Encodes a `break` instruction (requires 32bit). + pub inline fn @"break"(p0: u15) Instruction { + return encodeUd15(0x002a0000, p0); + } + + /// Encodes a `bstrins.d` instruction (requires 64bit). + pub inline fn @"bstrins.d"(p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return encodeDJUm6Uk6(0x00800000, p0, p1, p2, p3); + } + + /// Encodes a `bstrins.w` instruction (requires 32s). + pub inline fn @"bstrins.w"(p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return encodeDJUm5Uk5(0x00600000, p0, p1, p2, p3); + } + + /// Encodes a `bstrpick.d` instruction (requires 64bit). + pub inline fn @"bstrpick.d"(p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return encodeDJUm6Uk6(0x00c00000, p0, p1, p2, p3); + } + + /// Encodes a `bstrpick.w` instruction (requires 32s). + pub inline fn @"bstrpick.w"(p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return encodeDJUm5Uk5(0x00608000, p0, p1, p2, p3); + } + + /// Encodes a `cacop` instruction (requires 32bit). + pub inline fn cacop(p0: u5, p1: Register, p2: i12) Instruction { + return encodeUd5JSk12(0x06000000, p0, p1, p2); + } + + /// Encodes a `catpick.d` instruction (requires 64bit). + pub inline fn @"catpick.d"(p0: Register, p1: Register, p2: Register, p3: u3) Instruction { + return encodeDJKUa3(0x000c0000, p0, p1, p2, p3); + } + + /// Encodes a `catpick.w` instruction (requires 32s). + pub inline fn @"catpick.w"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x00080000, p0, p1, p2, p3); + } + + /// Encodes a `clo.d` instruction (requires 64bit). + pub inline fn @"clo.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002000, p0, p1); + } + + /// Encodes a `clo.w` instruction (requires 32s). + pub inline fn @"clo.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001000, p0, p1); + } + + /// Encodes a `clz.d` instruction (requires 64bit). + pub inline fn @"clz.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002400, p0, p1); + } + + /// Encodes a `clz.w` instruction (requires 32s). + pub inline fn @"clz.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001400, p0, p1); + } + + /// Encodes a `cpucfg` instruction (requires 32s). + pub inline fn cpucfg(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006c00, p0, p1); + } + + /// Encodes a `crc.w.b.w` instruction (requires 64bit). + pub inline fn @"crc.w.b.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00240000, p0, p1, p2); + } + + /// Encodes a `crc.w.d.w` instruction (requires 64bit). + pub inline fn @"crc.w.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00258000, p0, p1, p2); + } + + /// Encodes a `crc.w.h.w` instruction (requires 64bit). + pub inline fn @"crc.w.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00248000, p0, p1, p2); + } + + /// Encodes a `crc.w.w.w` instruction (requires 64bit). + pub inline fn @"crc.w.w.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00250000, p0, p1, p2); + } + + /// Encodes a `crcc.w.b.w` instruction (requires 64bit). + pub inline fn @"crcc.w.b.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00260000, p0, p1, p2); + } + + /// Encodes a `crcc.w.d.w` instruction (requires 64bit). + pub inline fn @"crcc.w.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00278000, p0, p1, p2); + } + + /// Encodes a `crcc.w.h.w` instruction (requires 64bit). + pub inline fn @"crcc.w.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00268000, p0, p1, p2); + } + + /// Encodes a `crcc.w.w.w` instruction (requires 64bit). + pub inline fn @"crcc.w.w.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00270000, p0, p1, p2); + } + + /// Encodes a `csrrd` instruction (requires 32bit). + pub inline fn csrrd(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x04000000, p0, p1); + } + + /// Encodes a `csrwr` instruction (requires 32bit). + pub inline fn csrwr(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x04000032, p0, p1); + } + + /// Encodes a `csrxchg` instruction (requires 32bit). + pub inline fn csrxchg(p0: Register, p1: Register, p2: u14) Instruction { + return encodeDJUk14(0x04000000, p0, p1, p2); + } + + /// Encodes a `cto.d` instruction (requires 64bit). + pub inline fn @"cto.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002800, p0, p1); + } + + /// Encodes a `cto.w` instruction (requires 32s). + pub inline fn @"cto.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001800, p0, p1); + } + + /// Encodes a `ctz.d` instruction (requires 64bit). + pub inline fn @"ctz.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002c00, p0, p1); + } + + /// Encodes a `ctz.w` instruction (requires 32s). + pub inline fn @"ctz.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001c00, p0, p1); + } + + /// Encodes a `cu32i.d` instruction (requires 64bit). + pub inline fn @"cu32i.d"(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x16000000, p0, p1); + } + + /// Encodes a `cu52i.d` instruction (requires 64bit). + pub inline fn @"cu52i.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x03000000, p0, p1, p2); + } + + /// Encodes a `dbar` instruction (requires 32bit). + pub inline fn dbar(p0: u15) Instruction { + return encodeUd15(0x38720000, p0); + } + + /// Encodes a `dbgcall` instruction (requires 64bit). + pub inline fn dbgcall(p0: u15) Instruction { + return encodeUd15(0x002a8000, p0); + } + + /// Encodes a `div.d` instruction (requires 64bit). + pub inline fn @"div.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00220000, p0, p1, p2); + } + + /// Encodes a `div.du` instruction (requires 64bit). + pub inline fn @"div.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00230000, p0, p1, p2); + } + + /// Encodes a `div.w` instruction (requires 32bit). + pub inline fn @"div.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00200000, p0, p1, p2); + } + + /// Encodes a `div.wu` instruction (requires 32bit). + pub inline fn @"div.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00210000, p0, p1, p2); + } + + /// Encodes a `eret` instruction (requires 32bit). + pub inline fn eret() Instruction { + return encodeEMPTY(0x06483800); + } + + /// Encodes a `fabs.d` instruction (requires f). + pub inline fn @"fabs.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01140800, p0, p1); + } + + /// Encodes a `fabs.s` instruction (requires f). + pub inline fn @"fabs.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01140400, p0, p1); + } + + /// Encodes a `fadd.d` instruction (requires f). + pub inline fn @"fadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01010000, p0, p1, p2); + } + + /// Encodes a `fadd.s` instruction (requires f). + pub inline fn @"fadd.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01008000, p0, p1, p2); + } + + /// Encodes a `fclass.d` instruction (requires f). + pub inline fn @"fclass.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01143800, p0, p1); + } + + /// Encodes a `fclass.s` instruction (requires f). + pub inline fn @"fclass.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01143400, p0, p1); + } + + /// Encodes a `fcmp.caf.d` instruction (requires f). + pub inline fn @"fcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c200000, p0, p1, p2); + } + + /// Encodes a `fcmp.caf.s` instruction (requires f). + pub inline fn @"fcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c100000, p0, p1, p2); + } + + /// Encodes a `fcmp.ceq.d` instruction (requires f). + pub inline fn @"fcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c220000, p0, p1, p2); + } + + /// Encodes a `fcmp.ceq.s` instruction (requires f). + pub inline fn @"fcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c120000, p0, p1, p2); + } + + /// Encodes a `fcmp.cle.d` instruction (requires f). + pub inline fn @"fcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c230000, p0, p1, p2); + } + + /// Encodes a `fcmp.cle.s` instruction (requires f). + pub inline fn @"fcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c130000, p0, p1, p2); + } + + /// Encodes a `fcmp.clt.d` instruction (requires f). + pub inline fn @"fcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c210000, p0, p1, p2); + } + + /// Encodes a `fcmp.clt.s` instruction (requires f). + pub inline fn @"fcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c110000, p0, p1, p2); + } + + /// Encodes a `fcmp.cne.d` instruction (requires f). + pub inline fn @"fcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c280000, p0, p1, p2); + } + + /// Encodes a `fcmp.cne.s` instruction (requires f). + pub inline fn @"fcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c180000, p0, p1, p2); + } + + /// Encodes a `fcmp.cor.d` instruction (requires f). + pub inline fn @"fcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2a0000, p0, p1, p2); + } + + /// Encodes a `fcmp.cor.s` instruction (requires f). + pub inline fn @"fcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1a0000, p0, p1, p2); + } + + /// Encodes a `fcmp.cueq.d` instruction (requires f). + pub inline fn @"fcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c260000, p0, p1, p2); + } + + /// Encodes a `fcmp.cueq.s` instruction (requires f). + pub inline fn @"fcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c160000, p0, p1, p2); + } + + /// Encodes a `fcmp.cule.d` instruction (requires f). + pub inline fn @"fcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c270000, p0, p1, p2); + } + + /// Encodes a `fcmp.cule.s` instruction (requires f). + pub inline fn @"fcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c170000, p0, p1, p2); + } + + /// Encodes a `fcmp.cult.d` instruction (requires f). + pub inline fn @"fcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c250000, p0, p1, p2); + } + + /// Encodes a `fcmp.cult.s` instruction (requires f). + pub inline fn @"fcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c150000, p0, p1, p2); + } + + /// Encodes a `fcmp.cun.d` instruction (requires f). + pub inline fn @"fcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c240000, p0, p1, p2); + } + + /// Encodes a `fcmp.cun.s` instruction (requires f). + pub inline fn @"fcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c140000, p0, p1, p2); + } + + /// Encodes a `fcmp.cune.d` instruction (requires f). + pub inline fn @"fcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2c0000, p0, p1, p2); + } + + /// Encodes a `fcmp.cune.s` instruction (requires f). + pub inline fn @"fcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1c0000, p0, p1, p2); + } + + /// Encodes a `fcmp.saf.d` instruction (requires f). + pub inline fn @"fcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c208000, p0, p1, p2); + } + + /// Encodes a `fcmp.saf.s` instruction (requires f). + pub inline fn @"fcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c108000, p0, p1, p2); + } + + /// Encodes a `fcmp.seq.d` instruction (requires f). + pub inline fn @"fcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c228000, p0, p1, p2); + } + + /// Encodes a `fcmp.seq.s` instruction (requires f). + pub inline fn @"fcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c128000, p0, p1, p2); + } + + /// Encodes a `fcmp.sle.d` instruction (requires f). + pub inline fn @"fcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c238000, p0, p1, p2); + } + + /// Encodes a `fcmp.sle.s` instruction (requires f). + pub inline fn @"fcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c138000, p0, p1, p2); + } + + /// Encodes a `fcmp.slt.d` instruction (requires f). + pub inline fn @"fcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c218000, p0, p1, p2); + } + + /// Encodes a `fcmp.slt.s` instruction (requires f). + pub inline fn @"fcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c118000, p0, p1, p2); + } + + /// Encodes a `fcmp.sne.d` instruction (requires f). + pub inline fn @"fcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c288000, p0, p1, p2); + } + + /// Encodes a `fcmp.sne.s` instruction (requires f). + pub inline fn @"fcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c188000, p0, p1, p2); + } + + /// Encodes a `fcmp.sor.d` instruction (requires f). + pub inline fn @"fcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2a8000, p0, p1, p2); + } + + /// Encodes a `fcmp.sor.s` instruction (requires f). + pub inline fn @"fcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1a8000, p0, p1, p2); + } + + /// Encodes a `fcmp.sueq.d` instruction (requires f). + pub inline fn @"fcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c268000, p0, p1, p2); + } + + /// Encodes a `fcmp.sueq.s` instruction (requires f). + pub inline fn @"fcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c168000, p0, p1, p2); + } + + /// Encodes a `fcmp.sule.d` instruction (requires f). + pub inline fn @"fcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c278000, p0, p1, p2); + } + + /// Encodes a `fcmp.sule.s` instruction (requires f). + pub inline fn @"fcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c178000, p0, p1, p2); + } + + /// Encodes a `fcmp.sult.d` instruction (requires f). + pub inline fn @"fcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c258000, p0, p1, p2); + } + + /// Encodes a `fcmp.sult.s` instruction (requires f). + pub inline fn @"fcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c158000, p0, p1, p2); + } + + /// Encodes a `fcmp.sun.d` instruction (requires f). + pub inline fn @"fcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c248000, p0, p1, p2); + } + + /// Encodes a `fcmp.sun.s` instruction (requires f). + pub inline fn @"fcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c148000, p0, p1, p2); + } + + /// Encodes a `fcmp.sune.d` instruction (requires f). + pub inline fn @"fcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2c8000, p0, p1, p2); + } + + /// Encodes a `fcmp.sune.s` instruction (requires f). + pub inline fn @"fcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1c8000, p0, p1, p2); + } + + /// Encodes a `fcopysign.d` instruction (requires f). + pub inline fn @"fcopysign.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01130000, p0, p1, p2); + } + + /// Encodes a `fcopysign.s` instruction (requires f). + pub inline fn @"fcopysign.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01128000, p0, p1, p2); + } + + /// Encodes a `fcsrrd` instruction (requires 64bit). + pub inline fn fcsrrd(p0: Register, p1: u5) Instruction { + return encodeDUj5(0x0114c800, p0, p1); + } + + /// Encodes a `fcsrwr` instruction (requires 64bit). + pub inline fn fcsrwr(p0: Register, p1: u5) Instruction { + return encodeJUd5(0x0114c000, p0, p1); + } + + /// Encodes a `fcvt.d.ld` instruction (requires f). + pub inline fn @"fcvt.d.ld"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01150000, p0, p1, p2); + } + + /// Encodes a `fcvt.d.s` instruction (requires f). + pub inline fn @"fcvt.d.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01192400, p0, p1); + } + + /// Encodes a `fcvt.ld.d` instruction (requires f). + pub inline fn @"fcvt.ld.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x0114e000, p0, p1); + } + + /// Encodes a `fcvt.s.d` instruction (requires f). + pub inline fn @"fcvt.s.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01191800, p0, p1); + } + + /// Encodes a `fcvt.ud.d` instruction (requires f). + pub inline fn @"fcvt.ud.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x0114e400, p0, p1); + } + + /// Encodes a `fdiv.d` instruction (requires f). + pub inline fn @"fdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01070000, p0, p1, p2); + } + + /// Encodes a `fdiv.s` instruction (requires f). + pub inline fn @"fdiv.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01068000, p0, p1, p2); + } + + /// Encodes a `ffint.d.l` instruction (requires f). + pub inline fn @"ffint.d.l"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d2800, p0, p1); + } + + /// Encodes a `ffint.d.w` instruction (requires f). + pub inline fn @"ffint.d.w"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d2000, p0, p1); + } + + /// Encodes a `ffint.s.l` instruction (requires f). + pub inline fn @"ffint.s.l"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d1800, p0, p1); + } + + /// Encodes a `ffint.s.w` instruction (requires f). + pub inline fn @"ffint.s.w"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d1000, p0, p1); + } + + /// Encodes a `fld.d` instruction (requires f). + pub inline fn @"fld.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2b800000, p0, p1, p2); + } + + /// Encodes a `fld.s` instruction (requires f). + pub inline fn @"fld.s"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2b000000, p0, p1, p2); + } + + /// Encodes a `fldgt.d` instruction (requires f). + pub inline fn @"fldgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38748000, p0, p1, p2); + } + + /// Encodes a `fldgt.s` instruction (requires f). + pub inline fn @"fldgt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38740000, p0, p1, p2); + } + + /// Encodes a `fldle.d` instruction (requires f). + pub inline fn @"fldle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38758000, p0, p1, p2); + } + + /// Encodes a `fldle.s` instruction (requires f). + pub inline fn @"fldle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38750000, p0, p1, p2); + } + + /// Encodes a `fldx.d` instruction (requires f). + pub inline fn @"fldx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38340000, p0, p1, p2); + } + + /// Encodes a `fldx.s` instruction (requires f). + pub inline fn @"fldx.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38300000, p0, p1, p2); + } + + /// Encodes a `flogb.d` instruction (requires f). + pub inline fn @"flogb.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01142800, p0, p1); + } + + /// Encodes a `flogb.s` instruction (requires f). + pub inline fn @"flogb.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01142400, p0, p1); + } + + /// Encodes a `fmadd.d` instruction (requires f). + pub inline fn @"fmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08200000, p0, p1, p2, p3); + } + + /// Encodes a `fmadd.s` instruction (requires f). + pub inline fn @"fmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08100000, p0, p1, p2, p3); + } + + /// Encodes a `fmax.d` instruction (requires f). + pub inline fn @"fmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01090000, p0, p1, p2); + } + + /// Encodes a `fmax.s` instruction (requires f). + pub inline fn @"fmax.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01088000, p0, p1, p2); + } + + /// Encodes a `fmaxa.d` instruction (requires f). + pub inline fn @"fmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010d0000, p0, p1, p2); + } + + /// Encodes a `fmaxa.s` instruction (requires f). + pub inline fn @"fmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010c8000, p0, p1, p2); + } + + /// Encodes a `fmin.d` instruction (requires f). + pub inline fn @"fmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010b0000, p0, p1, p2); + } + + /// Encodes a `fmin.s` instruction (requires f). + pub inline fn @"fmin.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010a8000, p0, p1, p2); + } + + /// Encodes a `fmina.d` instruction (requires f). + pub inline fn @"fmina.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010f0000, p0, p1, p2); + } + + /// Encodes a `fmina.s` instruction (requires f). + pub inline fn @"fmina.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010e8000, p0, p1, p2); + } + + /// Encodes a `fmov.d` instruction (requires f). + pub inline fn @"fmov.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01149800, p0, p1); + } + + /// Encodes a `fmov.s` instruction (requires f). + pub inline fn @"fmov.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01149400, p0, p1); + } + + /// Encodes a `fmsub.d` instruction (requires f). + pub inline fn @"fmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08600000, p0, p1, p2, p3); + } + + /// Encodes a `fmsub.s` instruction (requires f). + pub inline fn @"fmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08500000, p0, p1, p2, p3); + } + + /// Encodes a `fmul.d` instruction (requires f). + pub inline fn @"fmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01050000, p0, p1, p2); + } + + /// Encodes a `fmul.s` instruction (requires f). + pub inline fn @"fmul.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01048000, p0, p1, p2); + } + + /// Encodes a `fneg.d` instruction (requires f). + pub inline fn @"fneg.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01141800, p0, p1); + } + + /// Encodes a `fneg.s` instruction (requires f). + pub inline fn @"fneg.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01141400, p0, p1); + } + + /// Encodes a `fnmadd.d` instruction (requires f). + pub inline fn @"fnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08a00000, p0, p1, p2, p3); + } + + /// Encodes a `fnmadd.s` instruction (requires f). + pub inline fn @"fnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08900000, p0, p1, p2, p3); + } + + /// Encodes a `fnmsub.d` instruction (requires f). + pub inline fn @"fnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08e00000, p0, p1, p2, p3); + } + + /// Encodes a `fnmsub.s` instruction (requires f). + pub inline fn @"fnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08d00000, p0, p1, p2, p3); + } + + /// Encodes a `frecip.d` instruction (requires f). + pub inline fn @"frecip.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01145800, p0, p1); + } + + /// Encodes a `frecip.s` instruction (requires f). + pub inline fn @"frecip.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01145400, p0, p1); + } + + /// Encodes a `frecipe.d` instruction (requires f). + pub inline fn @"frecipe.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01147800, p0, p1); + } + + /// Encodes a `frecipe.s` instruction (requires f). + pub inline fn @"frecipe.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01147400, p0, p1); + } + + /// Encodes a `frint.d` instruction (requires f). + pub inline fn @"frint.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011e4800, p0, p1); + } + + /// Encodes a `frint.s` instruction (requires f). + pub inline fn @"frint.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011e4400, p0, p1); + } + + /// Encodes a `frsqrt.d` instruction (requires f). + pub inline fn @"frsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01146800, p0, p1); + } + + /// Encodes a `frsqrt.s` instruction (requires f). + pub inline fn @"frsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01146400, p0, p1); + } + + /// Encodes a `frsqrte.d` instruction (requires f). + pub inline fn @"frsqrte.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01148800, p0, p1); + } + + /// Encodes a `frsqrte.s` instruction (requires f). + pub inline fn @"frsqrte.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01148400, p0, p1); + } + + /// Encodes a `fscaleb.d` instruction (requires f). + pub inline fn @"fscaleb.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01110000, p0, p1, p2); + } + + /// Encodes a `fscaleb.s` instruction (requires f). + pub inline fn @"fscaleb.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01108000, p0, p1, p2); + } + + /// Encodes a `fsel` instruction (requires f). + pub inline fn fsel(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkCa(0x0d000000, p0, p1, p2, p3); + } + + /// Encodes a `fsqrt.d` instruction (requires f). + pub inline fn @"fsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01144800, p0, p1); + } + + /// Encodes a `fsqrt.s` instruction (requires f). + pub inline fn @"fsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01144400, p0, p1); + } + + /// Encodes a `fst.d` instruction (requires f). + pub inline fn @"fst.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2bc00000, p0, p1, p2); + } + + /// Encodes a `fst.s` instruction (requires f). + pub inline fn @"fst.s"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2b400000, p0, p1, p2); + } + + /// Encodes a `fstgt.d` instruction (requires f). + pub inline fn @"fstgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38768000, p0, p1, p2); + } + + /// Encodes a `fstgt.s` instruction (requires f). + pub inline fn @"fstgt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38760000, p0, p1, p2); + } + + /// Encodes a `fstle.d` instruction (requires f). + pub inline fn @"fstle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38778000, p0, p1, p2); + } + + /// Encodes a `fstle.s` instruction (requires f). + pub inline fn @"fstle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38770000, p0, p1, p2); + } + + /// Encodes a `fstx.d` instruction (requires f). + pub inline fn @"fstx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x383c0000, p0, p1, p2); + } + + /// Encodes a `fstx.s` instruction (requires f). + pub inline fn @"fstx.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38380000, p0, p1, p2); + } + + /// Encodes a `fsub.d` instruction (requires f). + pub inline fn @"fsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01030000, p0, p1, p2); + } + + /// Encodes a `fsub.s` instruction (requires f). + pub inline fn @"fsub.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01028000, p0, p1, p2); + } + + /// Encodes a `ftint.l.d` instruction (requires f). + pub inline fn @"ftint.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b2800, p0, p1); + } + + /// Encodes a `ftint.l.s` instruction (requires f). + pub inline fn @"ftint.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b2400, p0, p1); + } + + /// Encodes a `ftint.w.d` instruction (requires f). + pub inline fn @"ftint.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b0800, p0, p1); + } + + /// Encodes a `ftint.w.s` instruction (requires f). + pub inline fn @"ftint.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b0400, p0, p1); + } + + /// Encodes a `ftintrm.l.d` instruction (requires f). + pub inline fn @"ftintrm.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a2800, p0, p1); + } + + /// Encodes a `ftintrm.l.s` instruction (requires f). + pub inline fn @"ftintrm.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a2400, p0, p1); + } + + /// Encodes a `ftintrm.w.d` instruction (requires f). + pub inline fn @"ftintrm.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a0800, p0, p1); + } + + /// Encodes a `ftintrm.w.s` instruction (requires f). + pub inline fn @"ftintrm.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a0400, p0, p1); + } + + /// Encodes a `ftintrne.l.d` instruction (requires f). + pub inline fn @"ftintrne.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ae800, p0, p1); + } + + /// Encodes a `ftintrne.l.s` instruction (requires f). + pub inline fn @"ftintrne.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ae400, p0, p1); + } + + /// Encodes a `ftintrne.w.d` instruction (requires f). + pub inline fn @"ftintrne.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ac800, p0, p1); + } + + /// Encodes a `ftintrne.w.s` instruction (requires f). + pub inline fn @"ftintrne.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ac400, p0, p1); + } + + /// Encodes a `ftintrp.l.d` instruction (requires f). + pub inline fn @"ftintrp.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a6800, p0, p1); + } + + /// Encodes a `ftintrp.l.s` instruction (requires f). + pub inline fn @"ftintrp.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a6400, p0, p1); + } + + /// Encodes a `ftintrp.w.d` instruction (requires f). + pub inline fn @"ftintrp.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a4800, p0, p1); + } + + /// Encodes a `ftintrp.w.s` instruction (requires f). + pub inline fn @"ftintrp.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a4400, p0, p1); + } + + /// Encodes a `ftintrz.l.d` instruction (requires f). + pub inline fn @"ftintrz.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011aa800, p0, p1); + } + + /// Encodes a `ftintrz.l.s` instruction (requires f). + pub inline fn @"ftintrz.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011aa400, p0, p1); + } + + /// Encodes a `ftintrz.w.d` instruction (requires f). + pub inline fn @"ftintrz.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a8800, p0, p1); + } + + /// Encodes a `ftintrz.w.s` instruction (requires f). + pub inline fn @"ftintrz.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a8400, p0, p1); + } + + /// Encodes a `gcsrrd` instruction (requires 64bit). + pub inline fn gcsrrd(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x05000000, p0, p1); + } + + /// Encodes a `gcsrwr` instruction (requires 64bit). + pub inline fn gcsrwr(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x05000032, p0, p1); + } + + /// Encodes a `gcsrxchg` instruction (requires 64bit). + pub inline fn gcsrxchg(p0: Register, p1: Register, p2: u14) Instruction { + return encodeDJUk14(0x05000000, p0, p1, p2); + } + + /// Encodes a `gtlbclr` instruction (requires 64bit). + pub inline fn gtlbclr() Instruction { + return encodeEMPTY(0x06482001); + } + + /// Encodes a `gtlbfill` instruction (requires 64bit). + pub inline fn gtlbfill() Instruction { + return encodeEMPTY(0x06483401); + } + + /// Encodes a `gtlbflush` instruction (requires 64bit). + pub inline fn gtlbflush() Instruction { + return encodeEMPTY(0x06482401); + } + + /// Encodes a `gtlbrd` instruction (requires 64bit). + pub inline fn gtlbrd() Instruction { + return encodeEMPTY(0x06482c01); + } + + /// Encodes a `gtlbsrch` instruction (requires 64bit). + pub inline fn gtlbsrch() Instruction { + return encodeEMPTY(0x06482801); + } + + /// Encodes a `gtlbwr` instruction (requires 64bit). + pub inline fn gtlbwr() Instruction { + return encodeEMPTY(0x06483001); + } + + /// Encodes a `hypcall` instruction (requires 64bit). + pub inline fn hypcall(p0: u15) Instruction { + return encodeUd15(0x002b8000, p0); + } + + /// Encodes a `ibar` instruction (requires 32bit). + pub inline fn ibar(p0: u15) Instruction { + return encodeUd15(0x38728000, p0); + } + + /// Encodes a `idle` instruction (requires 32bit). + pub inline fn idle(p0: u15) Instruction { + return encodeUd15(0x06488000, p0); + } + + /// Encodes a `iocsrrd.b` instruction (requires 64bit). + pub inline fn @"iocsrrd.b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480000, p0, p1); + } + + /// Encodes a `iocsrrd.d` instruction (requires 64bit). + pub inline fn @"iocsrrd.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480c00, p0, p1); + } + + /// Encodes a `iocsrrd.h` instruction (requires 64bit). + pub inline fn @"iocsrrd.h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480400, p0, p1); + } + + /// Encodes a `iocsrrd.w` instruction (requires 64bit). + pub inline fn @"iocsrrd.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480800, p0, p1); + } + + /// Encodes a `iocsrwr.b` instruction (requires 64bit). + pub inline fn @"iocsrwr.b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481000, p0, p1); + } + + /// Encodes a `iocsrwr.d` instruction (requires 64bit). + pub inline fn @"iocsrwr.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481c00, p0, p1); + } + + /// Encodes a `iocsrwr.h` instruction (requires 64bit). + pub inline fn @"iocsrwr.h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481400, p0, p1); + } + + /// Encodes a `iocsrwr.w` instruction (requires 64bit). + pub inline fn @"iocsrwr.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481800, p0, p1); + } + + /// Encodes a `jirl` instruction (requires 32bit). + pub inline fn jirl(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16ps2(0x4c000000, p0, p1, p2); + } + + /// Encodes a `jiscr0` instruction (requires 64bit). + pub inline fn jiscr0(p0: i5, p1: i16) Instruction { + return encodeSd5k16ps2(0x48000200, p0, p1); + } + + /// Encodes a `jiscr1` instruction (requires 64bit). + pub inline fn jiscr1(p0: i5, p1: i16) Instruction { + return encodeSd5k16ps2(0x48000300, p0, p1); + } + + /// Encodes a `ld.b` instruction (requires 32bit). + pub inline fn @"ld.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28000000, p0, p1, p2); + } + + /// Encodes a `ld.bu` instruction (requires 32bit). + pub inline fn @"ld.bu"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2a000000, p0, p1, p2); + } + + /// Encodes a `ld.d` instruction (requires 64bit). + pub inline fn @"ld.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28c00000, p0, p1, p2); + } + + /// Encodes a `ld.h` instruction (requires 32bit). + pub inline fn @"ld.h"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28400000, p0, p1, p2); + } + + /// Encodes a `ld.hu` instruction (requires 32bit). + pub inline fn @"ld.hu"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2a400000, p0, p1, p2); + } + + /// Encodes a `ld.w` instruction (requires 32bit). + pub inline fn @"ld.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28800000, p0, p1, p2); + } + + /// Encodes a `ld.wu` instruction (requires 64bit). + pub inline fn @"ld.wu"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2a800000, p0, p1, p2); + } + + /// Encodes a `lddir` instruction (requires 64bit). + pub inline fn lddir(p0: Register, p1: Register, p2: u8) Instruction { + return encodeDJUk8(0x06400000, p0, p1, p2); + } + + /// Encodes a `ldgt.b` instruction (requires 64bit). + pub inline fn @"ldgt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38780000, p0, p1, p2); + } + + /// Encodes a `ldgt.d` instruction (requires 64bit). + pub inline fn @"ldgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38798000, p0, p1, p2); + } + + /// Encodes a `ldgt.h` instruction (requires 64bit). + pub inline fn @"ldgt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38788000, p0, p1, p2); + } + + /// Encodes a `ldgt.w` instruction (requires 64bit). + pub inline fn @"ldgt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38790000, p0, p1, p2); + } + + /// Encodes a `ldl.d` instruction (requires 64bit). + pub inline fn @"ldl.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2e800000, p0, p1, p2); + } + + /// Encodes a `ldl.w` instruction (requires 64bit). + pub inline fn @"ldl.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2e000000, p0, p1, p2); + } + + /// Encodes a `ldle.b` instruction (requires 64bit). + pub inline fn @"ldle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387a0000, p0, p1, p2); + } + + /// Encodes a `ldle.d` instruction (requires 64bit). + pub inline fn @"ldle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387b8000, p0, p1, p2); + } + + /// Encodes a `ldle.h` instruction (requires 64bit). + pub inline fn @"ldle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387a8000, p0, p1, p2); + } + + /// Encodes a `ldle.w` instruction (requires 64bit). + pub inline fn @"ldle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387b0000, p0, p1, p2); + } + + /// Encodes a `ldox4.d` instruction (requires 64bit). + pub inline fn @"ldox4.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x26000000, p0, p1, p2); + } + + /// Encodes a `ldox4.w` instruction (requires 64bit). + pub inline fn @"ldox4.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x24000000, p0, p1, p2); + } + + /// Encodes a `ldpte` instruction (requires 64bit). + pub inline fn ldpte(p0: Register, p1: u8) Instruction { + return encodeJUk8(0x06440000, p0, p1); + } + + /// Encodes a `ldr.d` instruction (requires 64bit). + pub inline fn @"ldr.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2ec00000, p0, p1, p2); + } + + /// Encodes a `ldr.w` instruction (requires 64bit). + pub inline fn @"ldr.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2e400000, p0, p1, p2); + } + + /// Encodes a `ldx.b` instruction (requires 64bit). + pub inline fn @"ldx.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38000000, p0, p1, p2); + } + + /// Encodes a `ldx.bu` instruction (requires 64bit). + pub inline fn @"ldx.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38200000, p0, p1, p2); + } + + /// Encodes a `ldx.d` instruction (requires 64bit). + pub inline fn @"ldx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x380c0000, p0, p1, p2); + } + + /// Encodes a `ldx.h` instruction (requires 64bit). + pub inline fn @"ldx.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38040000, p0, p1, p2); + } + + /// Encodes a `ldx.hu` instruction (requires 64bit). + pub inline fn @"ldx.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38240000, p0, p1, p2); + } + + /// Encodes a `ldx.w` instruction (requires 64bit). + pub inline fn @"ldx.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38080000, p0, p1, p2); + } + + /// Encodes a `ldx.wu` instruction (requires 64bit). + pub inline fn @"ldx.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38280000, p0, p1, p2); + } + + /// Encodes a `ll.d` instruction (requires 64bit). + pub inline fn @"ll.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x22000000, p0, p1, p2); + } + + /// Encodes a `ll.w` instruction (requires 32bit). + pub inline fn @"ll.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x20000000, p0, p1, p2); + } + + /// Encodes a `llacq.d` instruction (requires 64bit). + pub inline fn @"llacq.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578800, p0, p1); + } + + /// Encodes a `llacq.w` instruction (requires 64bit). + pub inline fn @"llacq.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578000, p0, p1); + } + + /// Encodes a `lu12i.w` instruction (requires 32bit). + pub inline fn @"lu12i.w"(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x14000000, p0, p1); + } + + /// Encodes a `maskeqz` instruction (requires 32s). + pub inline fn maskeqz(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00130000, p0, p1, p2); + } + + /// Encodes a `masknez` instruction (requires 32s). + pub inline fn masknez(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00138000, p0, p1, p2); + } + + /// Encodes a `mod.d` instruction (requires 64bit). + pub inline fn @"mod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00228000, p0, p1, p2); + } + + /// Encodes a `mod.du` instruction (requires 64bit). + pub inline fn @"mod.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00238000, p0, p1, p2); + } + + /// Encodes a `mod.w` instruction (requires 32bit). + pub inline fn @"mod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00208000, p0, p1, p2); + } + + /// Encodes a `mod.wu` instruction (requires 32bit). + pub inline fn @"mod.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00218000, p0, p1, p2); + } + + /// Encodes a `movfcc2fr` instruction (requires f). + pub inline fn movfcc2fr(p0: Register, p1: Register) Instruction { + return encodeFdCj(0x0114d400, p0, p1); + } + + /// Encodes a `movfcc2gr` instruction (requires f). + pub inline fn movfcc2gr(p0: Register, p1: Register) Instruction { + return encodeDCj(0x0114dc00, p0, p1); + } + + /// Encodes a `movfr2fcc` instruction (requires f). + pub inline fn movfr2fcc(p0: Register, p1: Register) Instruction { + return encodeCdFj(0x0114d000, p0, p1); + } + + /// Encodes a `movfr2gr.d` instruction (requires f). + pub inline fn @"movfr2gr.d"(p0: Register, p1: Register) Instruction { + return encodeDFj(0x0114b800, p0, p1); + } + + /// Encodes a `movfr2gr.s` instruction (requires f). + pub inline fn @"movfr2gr.s"(p0: Register, p1: Register) Instruction { + return encodeDFj(0x0114b400, p0, p1); + } + + /// Encodes a `movfrh2gr.s` instruction (requires f). + pub inline fn @"movfrh2gr.s"(p0: Register, p1: Register) Instruction { + return encodeDFj(0x0114bc00, p0, p1); + } + + /// Encodes a `movgr2fcc` instruction (requires f). + pub inline fn movgr2fcc(p0: Register, p1: Register) Instruction { + return encodeCdJ(0x0114d800, p0, p1); + } + + /// Encodes a `movgr2fr.d` instruction (requires f). + pub inline fn @"movgr2fr.d"(p0: Register, p1: Register) Instruction { + return encodeFdJ(0x0114a800, p0, p1); + } + + /// Encodes a `movgr2fr.w` instruction (requires f). + pub inline fn @"movgr2fr.w"(p0: Register, p1: Register) Instruction { + return encodeFdJ(0x0114a400, p0, p1); + } + + /// Encodes a `movgr2frh.w` instruction (requires f). + pub inline fn @"movgr2frh.w"(p0: Register, p1: Register) Instruction { + return encodeFdJ(0x0114ac00, p0, p1); + } + + /// Encodes a `movgr2scr` instruction (requires lbt). + pub inline fn movgr2scr(p0: Register, p1: Register) Instruction { + return encodeTdJ(0x00000800, p0, p1); + } + + /// Encodes a `movscr2gr` instruction (requires lbt). + pub inline fn movscr2gr(p0: Register, p1: Register) Instruction { + return encodeDTj(0x00000c00, p0, p1); + } + + /// Encodes a `mul.d` instruction (requires 64bit). + pub inline fn @"mul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001d8000, p0, p1, p2); + } + + /// Encodes a `mul.w` instruction (requires 32bit). + pub inline fn @"mul.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001c0000, p0, p1, p2); + } + + /// Encodes a `mulh.d` instruction (requires 64bit). + pub inline fn @"mulh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001e0000, p0, p1, p2); + } + + /// Encodes a `mulh.du` instruction (requires 64bit). + pub inline fn @"mulh.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001e8000, p0, p1, p2); + } + + /// Encodes a `mulh.w` instruction (requires 32bit). + pub inline fn @"mulh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001c8000, p0, p1, p2); + } + + /// Encodes a `mulh.wu` instruction (requires 32bit). + pub inline fn @"mulh.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001d0000, p0, p1, p2); + } + + /// Encodes a `mulw.d.w` instruction (requires 64bit). + pub inline fn @"mulw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001f0000, p0, p1, p2); + } + + /// Encodes a `mulw.d.wu` instruction (requires 64bit). + pub inline fn @"mulw.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001f8000, p0, p1, p2); + } + + /// Encodes a `nor` instruction (requires 32bit). + pub inline fn nor(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00140000, p0, p1, p2); + } + + /// Encodes a `or` instruction (requires 32bit). + pub inline fn @"or"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00150000, p0, p1, p2); + } + + /// Encodes a `ori` instruction (requires 32bit). + pub inline fn ori(p0: Register, p1: Register, p2: u12) Instruction { + return encodeDJUk12(0x03800000, p0, p1, p2); + } + + /// Encodes a `orn` instruction (requires 32bit). + pub inline fn orn(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00160000, p0, p1, p2); + } + + /// Encodes a `pcaddu12i` instruction (requires 32bit). + pub inline fn pcaddu12i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x1c000000, p0, p1); + } + + /// Encodes a `pcaddu18i` instruction (requires 64bit). + pub inline fn pcaddu18i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x1e000000, p0, p1); + } + + /// Encodes a `pcaddu2i` instruction (requires 32bit). + pub inline fn pcaddu2i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x18000000, p0, p1); + } + + /// Encodes a `pcalau12i` instruction (requires 32s). + pub inline fn pcalau12i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x1a000000, p0, p1); + } + + /// Encodes a `preld` instruction (requires 32bit). + pub inline fn preld(p0: u5, p1: Register, p2: i12) Instruction { + return encodeUd5JSk12(0x2ac00000, p0, p1, p2); + } + + /// Encodes a `preldx` instruction (requires 64bit). + pub inline fn preldx(p0: u5, p1: Register, p2: Register) Instruction { + return encodeUd5JK(0x382c0000, p0, p1, p2); + } + + /// Encodes a `rcr.b` instruction (requires 64bit). + pub inline fn @"rcr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00340000, p0, p1, p2); + } + + /// Encodes a `rcr.d` instruction (requires 64bit). + pub inline fn @"rcr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00358000, p0, p1, p2); + } + + /// Encodes a `rcr.h` instruction (requires 64bit). + pub inline fn @"rcr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00348000, p0, p1, p2); + } + + /// Encodes a `rcr.w` instruction (requires 64bit). + pub inline fn @"rcr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00350000, p0, p1, p2); + } + + /// Encodes a `rcri.b` instruction (requires 64bit). + pub inline fn @"rcri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDJUk3(0x00502000, p0, p1, p2); + } + + /// Encodes a `rcri.d` instruction (requires 64bit). + pub inline fn @"rcri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00510000, p0, p1, p2); + } + + /// Encodes a `rcri.h` instruction (requires 64bit). + pub inline fn @"rcri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDJUk4(0x00504000, p0, p1, p2); + } + + /// Encodes a `rcri.w` instruction (requires 64bit). + pub inline fn @"rcri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00508000, p0, p1, p2); + } + + /// Encodes a `rdtime.d` instruction (requires 64bit). + pub inline fn @"rdtime.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006800, p0, p1); + } + + /// Encodes a `rdtimeh.w` instruction (requires 32bit). + pub inline fn @"rdtimeh.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006400, p0, p1); + } + + /// Encodes a `rdtimel.w` instruction (requires 32bit). + pub inline fn @"rdtimel.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006000, p0, p1); + } + + /// Encodes a `revb.2h` instruction (requires 32s). + pub inline fn @"revb.2h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003000, p0, p1); + } + + /// Encodes a `revb.2w` instruction (requires 64bit). + pub inline fn @"revb.2w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003800, p0, p1); + } + + /// Encodes a `revb.4h` instruction (requires 64bit). + pub inline fn @"revb.4h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003400, p0, p1); + } + + /// Encodes a `revb.d` instruction (requires 64bit). + pub inline fn @"revb.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003c00, p0, p1); + } + + /// Encodes a `revbit.4b` instruction (requires 32s). + pub inline fn @"revbit.4b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004800, p0, p1); + } + + /// Encodes a `revbit.8b` instruction (requires 64bit). + pub inline fn @"revbit.8b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004c00, p0, p1); + } + + /// Encodes a `revbit.d` instruction (requires 64bit). + pub inline fn @"revbit.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005400, p0, p1); + } + + /// Encodes a `revbit.w` instruction (requires 32s). + pub inline fn @"revbit.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005000, p0, p1); + } + + /// Encodes a `revh.2w` instruction (requires 64bit). + pub inline fn @"revh.2w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004000, p0, p1); + } + + /// Encodes a `revh.d` instruction (requires 64bit). + pub inline fn @"revh.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004400, p0, p1); + } + + /// Encodes a `rotr.b` instruction (requires 64bit). + pub inline fn @"rotr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001a0000, p0, p1, p2); + } + + /// Encodes a `rotr.d` instruction (requires 64bit). + pub inline fn @"rotr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001b8000, p0, p1, p2); + } + + /// Encodes a `rotr.h` instruction (requires 64bit). + pub inline fn @"rotr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001a8000, p0, p1, p2); + } + + /// Encodes a `rotr.w` instruction (requires 32s). + pub inline fn @"rotr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001b0000, p0, p1, p2); + } + + /// Encodes a `rotri.b` instruction (requires 64bit). + pub inline fn @"rotri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDJUk3(0x004c2000, p0, p1, p2); + } + + /// Encodes a `rotri.d` instruction (requires 64bit). + pub inline fn @"rotri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x004d0000, p0, p1, p2); + } + + /// Encodes a `rotri.h` instruction (requires 64bit). + pub inline fn @"rotri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDJUk4(0x004c4000, p0, p1, p2); + } + + /// Encodes a `rotri.w` instruction (requires 32s). + pub inline fn @"rotri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x004c8000, p0, p1, p2); + } + + /// Encodes a `sbc.b` instruction (requires 64bit). + pub inline fn @"sbc.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00320000, p0, p1, p2); + } + + /// Encodes a `sbc.d` instruction (requires 64bit). + pub inline fn @"sbc.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00338000, p0, p1, p2); + } + + /// Encodes a `sbc.h` instruction (requires 64bit). + pub inline fn @"sbc.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00328000, p0, p1, p2); + } + + /// Encodes a `sbc.w` instruction (requires 64bit). + pub inline fn @"sbc.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00330000, p0, p1, p2); + } + + /// Encodes a `sc.d` instruction (requires 64bit). + pub inline fn @"sc.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x23000000, p0, p1, p2); + } + + /// Encodes a `sc.q` instruction (requires 64bit). + pub inline fn @"sc.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38570000, p0, p1, p2); + } + + /// Encodes a `sc.w` instruction (requires 32bit). + pub inline fn @"sc.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x21000000, p0, p1, p2); + } + + /// Encodes a `screl.d` instruction (requires 64bit). + pub inline fn @"screl.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578c00, p0, p1); + } + + /// Encodes a `screl.w` instruction (requires 64bit). + pub inline fn @"screl.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578400, p0, p1); + } + + /// Encodes a `sext.b` instruction (requires 32s). + pub inline fn @"sext.b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005c00, p0, p1); + } + + /// Encodes a `sext.h` instruction (requires 32s). + pub inline fn @"sext.h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005800, p0, p1); + } + + /// Encodes a `sladd.d` instruction (requires 64bit). + pub inline fn @"sladd.d"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x002c0000, p0, p1, p2, p3); + } + + /// Encodes a `sladd.w` instruction (requires 32s). + pub inline fn @"sladd.w"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x00040000, p0, p1, p2, p3); + } + + /// Encodes a `sladd.wu` instruction (requires 64bit). + pub inline fn @"sladd.wu"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x00060000, p0, p1, p2, p3); + } + + /// Encodes a `sll.d` instruction (requires 64bit). + pub inline fn @"sll.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00188000, p0, p1, p2); + } + + /// Encodes a `sll.w` instruction (requires 32bit). + pub inline fn @"sll.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00170000, p0, p1, p2); + } + + /// Encodes a `slli.d` instruction (requires 64bit). + pub inline fn @"slli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00410000, p0, p1, p2); + } + + /// Encodes a `slli.w` instruction (requires 32bit). + pub inline fn @"slli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00408000, p0, p1, p2); + } + + /// Encodes a `slt` instruction (requires 32bit). + pub inline fn slt(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00120000, p0, p1, p2); + } + + /// Encodes a `slti` instruction (requires 32bit). + pub inline fn slti(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02000000, p0, p1, p2); + } + + /// Encodes a `sltu` instruction (requires 32bit). + pub inline fn sltu(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00128000, p0, p1, p2); + } + + /// Encodes a `sltui` instruction (requires 32bit). + pub inline fn sltui(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02400000, p0, p1, p2); + } + + /// Encodes a `sra.d` instruction (requires 64bit). + pub inline fn @"sra.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00198000, p0, p1, p2); + } + + /// Encodes a `sra.w` instruction (requires 32bit). + pub inline fn @"sra.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00180000, p0, p1, p2); + } + + /// Encodes a `srai.d` instruction (requires 64bit). + pub inline fn @"srai.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00490000, p0, p1, p2); + } + + /// Encodes a `srai.w` instruction (requires 32bit). + pub inline fn @"srai.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00488000, p0, p1, p2); + } + + /// Encodes a `srl.d` instruction (requires 64bit). + pub inline fn @"srl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00190000, p0, p1, p2); + } + + /// Encodes a `srl.w` instruction (requires 32bit). + pub inline fn @"srl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00178000, p0, p1, p2); + } + + /// Encodes a `srli.d` instruction (requires 64bit). + pub inline fn @"srli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00450000, p0, p1, p2); + } + + /// Encodes a `srli.w` instruction (requires 32bit). + pub inline fn @"srli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00448000, p0, p1, p2); + } + + /// Encodes a `st.b` instruction (requires 32bit). + pub inline fn @"st.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29000000, p0, p1, p2); + } + + /// Encodes a `st.d` instruction (requires 64bit). + pub inline fn @"st.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29c00000, p0, p1, p2); + } + + /// Encodes a `st.h` instruction (requires 32bit). + pub inline fn @"st.h"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29400000, p0, p1, p2); + } + + /// Encodes a `st.w` instruction (requires 32bit). + pub inline fn @"st.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29800000, p0, p1, p2); + } + + /// Encodes a `stgt.b` instruction (requires 64bit). + pub inline fn @"stgt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387c0000, p0, p1, p2); + } + + /// Encodes a `stgt.d` instruction (requires 64bit). + pub inline fn @"stgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387d8000, p0, p1, p2); + } + + /// Encodes a `stgt.h` instruction (requires 64bit). + pub inline fn @"stgt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387c8000, p0, p1, p2); + } + + /// Encodes a `stgt.w` instruction (requires 64bit). + pub inline fn @"stgt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387d0000, p0, p1, p2); + } + + /// Encodes a `stl.d` instruction (requires 64bit). + pub inline fn @"stl.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2f800000, p0, p1, p2); + } + + /// Encodes a `stl.w` instruction (requires 64bit). + pub inline fn @"stl.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2f000000, p0, p1, p2); + } + + /// Encodes a `stle.b` instruction (requires 64bit). + pub inline fn @"stle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387e0000, p0, p1, p2); + } + + /// Encodes a `stle.d` instruction (requires 64bit). + pub inline fn @"stle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387f8000, p0, p1, p2); + } + + /// Encodes a `stle.h` instruction (requires 64bit). + pub inline fn @"stle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387e8000, p0, p1, p2); + } + + /// Encodes a `stle.w` instruction (requires 64bit). + pub inline fn @"stle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387f0000, p0, p1, p2); + } + + /// Encodes a `stox4.d` instruction (requires 64bit). + pub inline fn @"stox4.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x27000000, p0, p1, p2); + } + + /// Encodes a `stox4.w` instruction (requires 64bit). + pub inline fn @"stox4.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x25000000, p0, p1, p2); + } + + /// Encodes a `str.d` instruction (requires 64bit). + pub inline fn @"str.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2fc00000, p0, p1, p2); + } + + /// Encodes a `str.w` instruction (requires 64bit). + pub inline fn @"str.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2f400000, p0, p1, p2); + } + + /// Encodes a `stx.b` instruction (requires 64bit). + pub inline fn @"stx.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38100000, p0, p1, p2); + } + + /// Encodes a `stx.d` instruction (requires 64bit). + pub inline fn @"stx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x381c0000, p0, p1, p2); + } + + /// Encodes a `stx.h` instruction (requires 64bit). + pub inline fn @"stx.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38140000, p0, p1, p2); + } + + /// Encodes a `stx.w` instruction (requires 64bit). + pub inline fn @"stx.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38180000, p0, p1, p2); + } + + /// Encodes a `sub.d` instruction (requires 64bit). + pub inline fn @"sub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00118000, p0, p1, p2); + } + + /// Encodes a `sub.w` instruction (requires 32bit). + pub inline fn @"sub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00110000, p0, p1, p2); + } + + /// Encodes a `syscall` instruction (requires 32bit). + pub inline fn syscall(p0: u15) Instruction { + return encodeUd15(0x002b0000, p0); + } + + /// Encodes a `tlbclr` instruction (requires 64bit). + pub inline fn tlbclr() Instruction { + return encodeEMPTY(0x06482000); + } + + /// Encodes a `tlbfill` instruction (requires 32bit). + pub inline fn tlbfill() Instruction { + return encodeEMPTY(0x06483400); + } + + /// Encodes a `tlbflush` instruction (requires 64bit). + pub inline fn tlbflush() Instruction { + return encodeEMPTY(0x06482400); + } + + /// Encodes a `tlbinv` instruction (requires 32bit). + pub inline fn tlbinv(p0: Register, p1: Register, p2: u5) Instruction { + return encodeJKUd5(0x06498000, p0, p1, p2); + } + + /// Encodes a `tlbrd` instruction (requires 32bit). + pub inline fn tlbrd() Instruction { + return encodeEMPTY(0x06482c00); + } + + /// Encodes a `tlbsrch` instruction (requires 32bit). + pub inline fn tlbsrch() Instruction { + return encodeEMPTY(0x06482800); + } + + /// Encodes a `tlbwr` instruction (requires 32bit). + pub inline fn tlbwr() Instruction { + return encodeEMPTY(0x06483000); + } + + /// Encodes a `vabsd.b` instruction (requires lsx). + pub inline fn @"vabsd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70600000, p0, p1, p2); + } + + /// Encodes a `vabsd.bu` instruction (requires lsx). + pub inline fn @"vabsd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70620000, p0, p1, p2); + } + + /// Encodes a `vabsd.d` instruction (requires lsx). + pub inline fn @"vabsd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70618000, p0, p1, p2); + } + + /// Encodes a `vabsd.du` instruction (requires lsx). + pub inline fn @"vabsd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70638000, p0, p1, p2); + } + + /// Encodes a `vabsd.h` instruction (requires lsx). + pub inline fn @"vabsd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70608000, p0, p1, p2); + } + + /// Encodes a `vabsd.hu` instruction (requires lsx). + pub inline fn @"vabsd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70628000, p0, p1, p2); + } + + /// Encodes a `vabsd.w` instruction (requires lsx). + pub inline fn @"vabsd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70610000, p0, p1, p2); + } + + /// Encodes a `vabsd.wu` instruction (requires lsx). + pub inline fn @"vabsd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70630000, p0, p1, p2); + } + + /// Encodes a `vadd.b` instruction (requires lsx). + pub inline fn @"vadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700a0000, p0, p1, p2); + } + + /// Encodes a `vadd.d` instruction (requires lsx). + pub inline fn @"vadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700b8000, p0, p1, p2); + } + + /// Encodes a `vadd.h` instruction (requires lsx). + pub inline fn @"vadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700a8000, p0, p1, p2); + } + + /// Encodes a `vadd.q` instruction (requires lsx). + pub inline fn @"vadd.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712d0000, p0, p1, p2); + } + + /// Encodes a `vadd.w` instruction (requires lsx). + pub inline fn @"vadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700b0000, p0, p1, p2); + } + + /// Encodes a `vadda.b` instruction (requires lsx). + pub inline fn @"vadda.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705c0000, p0, p1, p2); + } + + /// Encodes a `vadda.d` instruction (requires lsx). + pub inline fn @"vadda.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705d8000, p0, p1, p2); + } + + /// Encodes a `vadda.h` instruction (requires lsx). + pub inline fn @"vadda.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705c8000, p0, p1, p2); + } + + /// Encodes a `vadda.w` instruction (requires lsx). + pub inline fn @"vadda.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705d0000, p0, p1, p2); + } + + /// Encodes a `vaddi.bu` instruction (requires lsx). + pub inline fn @"vaddi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728a0000, p0, p1, p2); + } + + /// Encodes a `vaddi.du` instruction (requires lsx). + pub inline fn @"vaddi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728b8000, p0, p1, p2); + } + + /// Encodes a `vaddi.hu` instruction (requires lsx). + pub inline fn @"vaddi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728a8000, p0, p1, p2); + } + + /// Encodes a `vaddi.wu` instruction (requires lsx). + pub inline fn @"vaddi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728b0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.d.w` instruction (requires lsx). + pub inline fn @"vaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701f0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.d.wu` instruction (requires lsx). + pub inline fn @"vaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702f0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.d.wu.w` instruction (requires lsx). + pub inline fn @"vaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703f0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.h.b` instruction (requires lsx). + pub inline fn @"vaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701e0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.h.bu` instruction (requires lsx). + pub inline fn @"vaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702e0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.h.bu.b` instruction (requires lsx). + pub inline fn @"vaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703e0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.q.d` instruction (requires lsx). + pub inline fn @"vaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701f8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.q.du` instruction (requires lsx). + pub inline fn @"vaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702f8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.q.du.d` instruction (requires lsx). + pub inline fn @"vaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703f8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.w.h` instruction (requires lsx). + pub inline fn @"vaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701e8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.w.hu` instruction (requires lsx). + pub inline fn @"vaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702e8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.w.hu.h` instruction (requires lsx). + pub inline fn @"vaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703e8000, p0, p1, p2); + } + + /// Encodes a `vaddwod.d.w` instruction (requires lsx). + pub inline fn @"vaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70230000, p0, p1, p2); + } + + /// Encodes a `vaddwod.d.wu` instruction (requires lsx). + pub inline fn @"vaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70330000, p0, p1, p2); + } + + /// Encodes a `vaddwod.d.wu.w` instruction (requires lsx). + pub inline fn @"vaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70410000, p0, p1, p2); + } + + /// Encodes a `vaddwod.h.b` instruction (requires lsx). + pub inline fn @"vaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70220000, p0, p1, p2); + } + + /// Encodes a `vaddwod.h.bu` instruction (requires lsx). + pub inline fn @"vaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70320000, p0, p1, p2); + } + + /// Encodes a `vaddwod.h.bu.b` instruction (requires lsx). + pub inline fn @"vaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70400000, p0, p1, p2); + } + + /// Encodes a `vaddwod.q.d` instruction (requires lsx). + pub inline fn @"vaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70238000, p0, p1, p2); + } + + /// Encodes a `vaddwod.q.du` instruction (requires lsx). + pub inline fn @"vaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70338000, p0, p1, p2); + } + + /// Encodes a `vaddwod.q.du.d` instruction (requires lsx). + pub inline fn @"vaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70418000, p0, p1, p2); + } + + /// Encodes a `vaddwod.w.h` instruction (requires lsx). + pub inline fn @"vaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70228000, p0, p1, p2); + } + + /// Encodes a `vaddwod.w.hu` instruction (requires lsx). + pub inline fn @"vaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70328000, p0, p1, p2); + } + + /// Encodes a `vaddwod.w.hu.h` instruction (requires lsx). + pub inline fn @"vaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70408000, p0, p1, p2); + } + + /// Encodes a `vand.v` instruction (requires lsx). + pub inline fn @"vand.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71260000, p0, p1, p2); + } + + /// Encodes a `vandi.b` instruction (requires lsx). + pub inline fn @"vandi.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73d00000, p0, p1, p2); + } + + /// Encodes a `vandn.v` instruction (requires lsx). + pub inline fn @"vandn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71280000, p0, p1, p2); + } + + /// Encodes a `vavg.b` instruction (requires lsx). + pub inline fn @"vavg.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70640000, p0, p1, p2); + } + + /// Encodes a `vavg.bu` instruction (requires lsx). + pub inline fn @"vavg.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70660000, p0, p1, p2); + } + + /// Encodes a `vavg.d` instruction (requires lsx). + pub inline fn @"vavg.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70658000, p0, p1, p2); + } + + /// Encodes a `vavg.du` instruction (requires lsx). + pub inline fn @"vavg.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70678000, p0, p1, p2); + } + + /// Encodes a `vavg.h` instruction (requires lsx). + pub inline fn @"vavg.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70648000, p0, p1, p2); + } + + /// Encodes a `vavg.hu` instruction (requires lsx). + pub inline fn @"vavg.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70668000, p0, p1, p2); + } + + /// Encodes a `vavg.w` instruction (requires lsx). + pub inline fn @"vavg.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70650000, p0, p1, p2); + } + + /// Encodes a `vavg.wu` instruction (requires lsx). + pub inline fn @"vavg.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70670000, p0, p1, p2); + } + + /// Encodes a `vavgr.b` instruction (requires lsx). + pub inline fn @"vavgr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70680000, p0, p1, p2); + } + + /// Encodes a `vavgr.bu` instruction (requires lsx). + pub inline fn @"vavgr.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706a0000, p0, p1, p2); + } + + /// Encodes a `vavgr.d` instruction (requires lsx). + pub inline fn @"vavgr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70698000, p0, p1, p2); + } + + /// Encodes a `vavgr.du` instruction (requires lsx). + pub inline fn @"vavgr.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706b8000, p0, p1, p2); + } + + /// Encodes a `vavgr.h` instruction (requires lsx). + pub inline fn @"vavgr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70688000, p0, p1, p2); + } + + /// Encodes a `vavgr.hu` instruction (requires lsx). + pub inline fn @"vavgr.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706a8000, p0, p1, p2); + } + + /// Encodes a `vavgr.w` instruction (requires lsx). + pub inline fn @"vavgr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70690000, p0, p1, p2); + } + + /// Encodes a `vavgr.wu` instruction (requires lsx). + pub inline fn @"vavgr.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706b0000, p0, p1, p2); + } + + /// Encodes a `vbitclr.b` instruction (requires lsx). + pub inline fn @"vbitclr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710c0000, p0, p1, p2); + } + + /// Encodes a `vbitclr.d` instruction (requires lsx). + pub inline fn @"vbitclr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710d8000, p0, p1, p2); + } + + /// Encodes a `vbitclr.h` instruction (requires lsx). + pub inline fn @"vbitclr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710c8000, p0, p1, p2); + } + + /// Encodes a `vbitclr.w` instruction (requires lsx). + pub inline fn @"vbitclr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710d0000, p0, p1, p2); + } + + /// Encodes a `vbitclri.b` instruction (requires lsx). + pub inline fn @"vbitclri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73102000, p0, p1, p2); + } + + /// Encodes a `vbitclri.d` instruction (requires lsx). + pub inline fn @"vbitclri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73110000, p0, p1, p2); + } + + /// Encodes a `vbitclri.h` instruction (requires lsx). + pub inline fn @"vbitclri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73104000, p0, p1, p2); + } + + /// Encodes a `vbitclri.w` instruction (requires lsx). + pub inline fn @"vbitclri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73108000, p0, p1, p2); + } + + /// Encodes a `vbitrev.b` instruction (requires lsx). + pub inline fn @"vbitrev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71100000, p0, p1, p2); + } + + /// Encodes a `vbitrev.d` instruction (requires lsx). + pub inline fn @"vbitrev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71118000, p0, p1, p2); + } + + /// Encodes a `vbitrev.h` instruction (requires lsx). + pub inline fn @"vbitrev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71108000, p0, p1, p2); + } + + /// Encodes a `vbitrev.w` instruction (requires lsx). + pub inline fn @"vbitrev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71110000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.b` instruction (requires lsx). + pub inline fn @"vbitrevi.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73182000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.d` instruction (requires lsx). + pub inline fn @"vbitrevi.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73190000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.h` instruction (requires lsx). + pub inline fn @"vbitrevi.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73184000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.w` instruction (requires lsx). + pub inline fn @"vbitrevi.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73188000, p0, p1, p2); + } + + /// Encodes a `vbitsel.v` instruction (requires lsx). + pub inline fn @"vbitsel.v"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x0d100000, p0, p1, p2, p3); + } + + /// Encodes a `vbitseli.b` instruction (requires lsx). + pub inline fn @"vbitseli.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73c40000, p0, p1, p2); + } + + /// Encodes a `vbitset.b` instruction (requires lsx). + pub inline fn @"vbitset.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710e0000, p0, p1, p2); + } + + /// Encodes a `vbitset.d` instruction (requires lsx). + pub inline fn @"vbitset.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710f8000, p0, p1, p2); + } + + /// Encodes a `vbitset.h` instruction (requires lsx). + pub inline fn @"vbitset.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710e8000, p0, p1, p2); + } + + /// Encodes a `vbitset.w` instruction (requires lsx). + pub inline fn @"vbitset.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710f0000, p0, p1, p2); + } + + /// Encodes a `vbitseti.b` instruction (requires lsx). + pub inline fn @"vbitseti.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73142000, p0, p1, p2); + } + + /// Encodes a `vbitseti.d` instruction (requires lsx). + pub inline fn @"vbitseti.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73150000, p0, p1, p2); + } + + /// Encodes a `vbitseti.h` instruction (requires lsx). + pub inline fn @"vbitseti.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73144000, p0, p1, p2); + } + + /// Encodes a `vbitseti.w` instruction (requires lsx). + pub inline fn @"vbitseti.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73148000, p0, p1, p2); + } + + /// Encodes a `vbsll.v` instruction (requires lsx). + pub inline fn @"vbsll.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728e0000, p0, p1, p2); + } + + /// Encodes a `vbsrl.v` instruction (requires lsx). + pub inline fn @"vbsrl.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728e8000, p0, p1, p2); + } + + /// Encodes a `vclo.b` instruction (requires lsx). + pub inline fn @"vclo.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0000, p0, p1); + } + + /// Encodes a `vclo.d` instruction (requires lsx). + pub inline fn @"vclo.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0c00, p0, p1); + } + + /// Encodes a `vclo.h` instruction (requires lsx). + pub inline fn @"vclo.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0400, p0, p1); + } + + /// Encodes a `vclo.w` instruction (requires lsx). + pub inline fn @"vclo.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0800, p0, p1); + } + + /// Encodes a `vclz.b` instruction (requires lsx). + pub inline fn @"vclz.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1000, p0, p1); + } + + /// Encodes a `vclz.d` instruction (requires lsx). + pub inline fn @"vclz.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1c00, p0, p1); + } + + /// Encodes a `vclz.h` instruction (requires lsx). + pub inline fn @"vclz.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1400, p0, p1); + } + + /// Encodes a `vclz.w` instruction (requires lsx). + pub inline fn @"vclz.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1800, p0, p1); + } + + /// Encodes a `vdiv.b` instruction (requires lsx). + pub inline fn @"vdiv.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e00000, p0, p1, p2); + } + + /// Encodes a `vdiv.bu` instruction (requires lsx). + pub inline fn @"vdiv.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e40000, p0, p1, p2); + } + + /// Encodes a `vdiv.d` instruction (requires lsx). + pub inline fn @"vdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e18000, p0, p1, p2); + } + + /// Encodes a `vdiv.du` instruction (requires lsx). + pub inline fn @"vdiv.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e58000, p0, p1, p2); + } + + /// Encodes a `vdiv.h` instruction (requires lsx). + pub inline fn @"vdiv.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e08000, p0, p1, p2); + } + + /// Encodes a `vdiv.hu` instruction (requires lsx). + pub inline fn @"vdiv.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e48000, p0, p1, p2); + } + + /// Encodes a `vdiv.w` instruction (requires lsx). + pub inline fn @"vdiv.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e10000, p0, p1, p2); + } + + /// Encodes a `vdiv.wu` instruction (requires lsx). + pub inline fn @"vdiv.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e50000, p0, p1, p2); + } + + /// Encodes a `vext2xv.d.b` instruction (requires lasx). + pub inline fn @"vext2xv.d.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1800, p0, p1); + } + + /// Encodes a `vext2xv.d.h` instruction (requires lasx). + pub inline fn @"vext2xv.d.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2000, p0, p1); + } + + /// Encodes a `vext2xv.d.w` instruction (requires lasx). + pub inline fn @"vext2xv.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2400, p0, p1); + } + + /// Encodes a `vext2xv.du.bu` instruction (requires lasx). + pub inline fn @"vext2xv.du.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3000, p0, p1); + } + + /// Encodes a `vext2xv.du.hu` instruction (requires lasx). + pub inline fn @"vext2xv.du.hu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3800, p0, p1); + } + + /// Encodes a `vext2xv.du.wu` instruction (requires lasx). + pub inline fn @"vext2xv.du.wu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3c00, p0, p1); + } + + /// Encodes a `vext2xv.h.b` instruction (requires lasx). + pub inline fn @"vext2xv.h.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1000, p0, p1); + } + + /// Encodes a `vext2xv.hu.bu` instruction (requires lasx). + pub inline fn @"vext2xv.hu.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2800, p0, p1); + } + + /// Encodes a `vext2xv.w.b` instruction (requires lasx). + pub inline fn @"vext2xv.w.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1400, p0, p1); + } + + /// Encodes a `vext2xv.w.h` instruction (requires lasx). + pub inline fn @"vext2xv.w.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1c00, p0, p1); + } + + /// Encodes a `vext2xv.wu.bu` instruction (requires lasx). + pub inline fn @"vext2xv.wu.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2c00, p0, p1); + } + + /// Encodes a `vext2xv.wu.hu` instruction (requires lasx). + pub inline fn @"vext2xv.wu.hu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3400, p0, p1); + } + + /// Encodes a `vexth.d.w` instruction (requires lsx). + pub inline fn @"vexth.d.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ee800, p0, p1); + } + + /// Encodes a `vexth.du.wu` instruction (requires lsx). + pub inline fn @"vexth.du.wu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ef800, p0, p1); + } + + /// Encodes a `vexth.h.b` instruction (requires lsx). + pub inline fn @"vexth.h.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ee000, p0, p1); + } + + /// Encodes a `vexth.hu.bu` instruction (requires lsx). + pub inline fn @"vexth.hu.bu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ef000, p0, p1); + } + + /// Encodes a `vexth.q.d` instruction (requires lsx). + pub inline fn @"vexth.q.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729eec00, p0, p1); + } + + /// Encodes a `vexth.qu.du` instruction (requires lsx). + pub inline fn @"vexth.qu.du"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729efc00, p0, p1); + } + + /// Encodes a `vexth.w.h` instruction (requires lsx). + pub inline fn @"vexth.w.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ee400, p0, p1); + } + + /// Encodes a `vexth.wu.hu` instruction (requires lsx). + pub inline fn @"vexth.wu.hu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ef400, p0, p1); + } + + /// Encodes a `vextl.q.d` instruction (requires lsx). + pub inline fn @"vextl.q.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x73090000, p0, p1); + } + + /// Encodes a `vextl.qu.du` instruction (requires lsx). + pub inline fn @"vextl.qu.du"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x730d0000, p0, p1); + } + + /// Encodes a `vextrins.b` instruction (requires lsx). + pub inline fn @"vextrins.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x738c0000, p0, p1, p2); + } + + /// Encodes a `vextrins.d` instruction (requires lsx). + pub inline fn @"vextrins.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73800000, p0, p1, p2); + } + + /// Encodes a `vextrins.h` instruction (requires lsx). + pub inline fn @"vextrins.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73880000, p0, p1, p2); + } + + /// Encodes a `vextrins.w` instruction (requires lsx). + pub inline fn @"vextrins.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73840000, p0, p1, p2); + } + + /// Encodes a `vfadd.d` instruction (requires lsx). + pub inline fn @"vfadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71310000, p0, p1, p2); + } + + /// Encodes a `vfadd.s` instruction (requires lsx). + pub inline fn @"vfadd.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71308000, p0, p1, p2); + } + + /// Encodes a `vfclass.d` instruction (requires lsx). + pub inline fn @"vfclass.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cd800, p0, p1); + } + + /// Encodes a `vfclass.s` instruction (requires lsx). + pub inline fn @"vfclass.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cd400, p0, p1); + } + + /// Encodes a `vfcmp.caf.d` instruction (requires lsx). + pub inline fn @"vfcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c600000, p0, p1, p2); + } + + /// Encodes a `vfcmp.caf.s` instruction (requires lsx). + pub inline fn @"vfcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c500000, p0, p1, p2); + } + + /// Encodes a `vfcmp.ceq.d` instruction (requires lsx). + pub inline fn @"vfcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c620000, p0, p1, p2); + } + + /// Encodes a `vfcmp.ceq.s` instruction (requires lsx). + pub inline fn @"vfcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c520000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cle.d` instruction (requires lsx). + pub inline fn @"vfcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c630000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cle.s` instruction (requires lsx). + pub inline fn @"vfcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c530000, p0, p1, p2); + } + + /// Encodes a `vfcmp.clt.d` instruction (requires lsx). + pub inline fn @"vfcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c610000, p0, p1, p2); + } + + /// Encodes a `vfcmp.clt.s` instruction (requires lsx). + pub inline fn @"vfcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c510000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cne.d` instruction (requires lsx). + pub inline fn @"vfcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c680000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cne.s` instruction (requires lsx). + pub inline fn @"vfcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c580000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cor.d` instruction (requires lsx). + pub inline fn @"vfcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6a0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cor.s` instruction (requires lsx). + pub inline fn @"vfcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5a0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cueq.d` instruction (requires lsx). + pub inline fn @"vfcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c660000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cueq.s` instruction (requires lsx). + pub inline fn @"vfcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c560000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cule.d` instruction (requires lsx). + pub inline fn @"vfcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c670000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cule.s` instruction (requires lsx). + pub inline fn @"vfcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c570000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cult.d` instruction (requires lsx). + pub inline fn @"vfcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c650000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cult.s` instruction (requires lsx). + pub inline fn @"vfcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c550000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cun.d` instruction (requires lsx). + pub inline fn @"vfcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c640000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cun.s` instruction (requires lsx). + pub inline fn @"vfcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c540000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cune.d` instruction (requires lsx). + pub inline fn @"vfcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6c0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cune.s` instruction (requires lsx). + pub inline fn @"vfcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5c0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.saf.d` instruction (requires lsx). + pub inline fn @"vfcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c608000, p0, p1, p2); + } + + /// Encodes a `vfcmp.saf.s` instruction (requires lsx). + pub inline fn @"vfcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c508000, p0, p1, p2); + } + + /// Encodes a `vfcmp.seq.d` instruction (requires lsx). + pub inline fn @"vfcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c628000, p0, p1, p2); + } + + /// Encodes a `vfcmp.seq.s` instruction (requires lsx). + pub inline fn @"vfcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c528000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sle.d` instruction (requires lsx). + pub inline fn @"vfcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c638000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sle.s` instruction (requires lsx). + pub inline fn @"vfcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c538000, p0, p1, p2); + } + + /// Encodes a `vfcmp.slt.d` instruction (requires lsx). + pub inline fn @"vfcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c618000, p0, p1, p2); + } + + /// Encodes a `vfcmp.slt.s` instruction (requires lsx). + pub inline fn @"vfcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c518000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sne.d` instruction (requires lsx). + pub inline fn @"vfcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c688000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sne.s` instruction (requires lsx). + pub inline fn @"vfcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c588000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sor.d` instruction (requires lsx). + pub inline fn @"vfcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6a8000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sor.s` instruction (requires lsx). + pub inline fn @"vfcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5a8000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sueq.d` instruction (requires lsx). + pub inline fn @"vfcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c668000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sueq.s` instruction (requires lsx). + pub inline fn @"vfcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c568000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sule.d` instruction (requires lsx). + pub inline fn @"vfcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c678000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sule.s` instruction (requires lsx). + pub inline fn @"vfcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c578000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sult.d` instruction (requires lsx). + pub inline fn @"vfcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c658000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sult.s` instruction (requires lsx). + pub inline fn @"vfcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c558000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sun.d` instruction (requires lsx). + pub inline fn @"vfcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c648000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sun.s` instruction (requires lsx). + pub inline fn @"vfcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c548000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sune.d` instruction (requires lsx). + pub inline fn @"vfcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6c8000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sune.s` instruction (requires lsx). + pub inline fn @"vfcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5c8000, p0, p1, p2); + } + + /// Encodes a `vfcvt.h.s` instruction (requires lsx). + pub inline fn @"vfcvt.h.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71460000, p0, p1, p2); + } + + /// Encodes a `vfcvt.s.d` instruction (requires lsx). + pub inline fn @"vfcvt.s.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71468000, p0, p1, p2); + } + + /// Encodes a `vfcvth.d.s` instruction (requires lsx). + pub inline fn @"vfcvth.d.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729df400, p0, p1); + } + + /// Encodes a `vfcvth.s.h` instruction (requires lsx). + pub inline fn @"vfcvth.s.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729dec00, p0, p1); + } + + /// Encodes a `vfcvtl.d.s` instruction (requires lsx). + pub inline fn @"vfcvtl.d.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729df000, p0, p1); + } + + /// Encodes a `vfcvtl.s.h` instruction (requires lsx). + pub inline fn @"vfcvtl.s.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729de800, p0, p1); + } + + /// Encodes a `vfdiv.d` instruction (requires lsx). + pub inline fn @"vfdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713b0000, p0, p1, p2); + } + + /// Encodes a `vfdiv.s` instruction (requires lsx). + pub inline fn @"vfdiv.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713a8000, p0, p1, p2); + } + + /// Encodes a `vffint.d.l` instruction (requires lsx). + pub inline fn @"vffint.d.l"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0800, p0, p1); + } + + /// Encodes a `vffint.d.lu` instruction (requires lsx). + pub inline fn @"vffint.d.lu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0c00, p0, p1); + } + + /// Encodes a `vffint.s.l` instruction (requires lsx). + pub inline fn @"vffint.s.l"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71480000, p0, p1, p2); + } + + /// Encodes a `vffint.s.w` instruction (requires lsx). + pub inline fn @"vffint.s.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0000, p0, p1); + } + + /// Encodes a `vffint.s.wu` instruction (requires lsx). + pub inline fn @"vffint.s.wu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0400, p0, p1); + } + + /// Encodes a `vffinth.d.w` instruction (requires lsx). + pub inline fn @"vffinth.d.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e1400, p0, p1); + } + + /// Encodes a `vffintl.d.w` instruction (requires lsx). + pub inline fn @"vffintl.d.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e1000, p0, p1); + } + + /// Encodes a `vflogb.d` instruction (requires lsx). + pub inline fn @"vflogb.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cc800, p0, p1); + } + + /// Encodes a `vflogb.s` instruction (requires lsx). + pub inline fn @"vflogb.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cc400, p0, p1); + } + + /// Encodes a `vfmadd.d` instruction (requires lsx). + pub inline fn @"vfmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09200000, p0, p1, p2, p3); + } + + /// Encodes a `vfmadd.s` instruction (requires lsx). + pub inline fn @"vfmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09100000, p0, p1, p2, p3); + } + + /// Encodes a `vfmax.d` instruction (requires lsx). + pub inline fn @"vfmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713d0000, p0, p1, p2); + } + + /// Encodes a `vfmax.s` instruction (requires lsx). + pub inline fn @"vfmax.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713c8000, p0, p1, p2); + } + + /// Encodes a `vfmaxa.d` instruction (requires lsx). + pub inline fn @"vfmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71410000, p0, p1, p2); + } + + /// Encodes a `vfmaxa.s` instruction (requires lsx). + pub inline fn @"vfmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71408000, p0, p1, p2); + } + + /// Encodes a `vfmin.d` instruction (requires lsx). + pub inline fn @"vfmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713f0000, p0, p1, p2); + } + + /// Encodes a `vfmin.s` instruction (requires lsx). + pub inline fn @"vfmin.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713e8000, p0, p1, p2); + } + + /// Encodes a `vfmina.d` instruction (requires lsx). + pub inline fn @"vfmina.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71430000, p0, p1, p2); + } + + /// Encodes a `vfmina.s` instruction (requires lsx). + pub inline fn @"vfmina.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71428000, p0, p1, p2); + } + + /// Encodes a `vfmsub.d` instruction (requires lsx). + pub inline fn @"vfmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09600000, p0, p1, p2, p3); + } + + /// Encodes a `vfmsub.s` instruction (requires lsx). + pub inline fn @"vfmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09500000, p0, p1, p2, p3); + } + + /// Encodes a `vfmul.d` instruction (requires lsx). + pub inline fn @"vfmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71390000, p0, p1, p2); + } + + /// Encodes a `vfmul.s` instruction (requires lsx). + pub inline fn @"vfmul.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71388000, p0, p1, p2); + } + + /// Encodes a `vfnmadd.d` instruction (requires lsx). + pub inline fn @"vfnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09a00000, p0, p1, p2, p3); + } + + /// Encodes a `vfnmadd.s` instruction (requires lsx). + pub inline fn @"vfnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09900000, p0, p1, p2, p3); + } + + /// Encodes a `vfnmsub.d` instruction (requires lsx). + pub inline fn @"vfnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09e00000, p0, p1, p2, p3); + } + + /// Encodes a `vfnmsub.s` instruction (requires lsx). + pub inline fn @"vfnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09d00000, p0, p1, p2, p3); + } + + /// Encodes a `vfrecip.d` instruction (requires lsx). + pub inline fn @"vfrecip.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cf800, p0, p1); + } + + /// Encodes a `vfrecip.s` instruction (requires lsx). + pub inline fn @"vfrecip.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cf400, p0, p1); + } + + /// Encodes a `vfrecipe.d` instruction (requires lsx). + pub inline fn @"vfrecipe.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d1800, p0, p1); + } + + /// Encodes a `vfrecipe.s` instruction (requires lsx). + pub inline fn @"vfrecipe.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d1400, p0, p1); + } + + /// Encodes a `vfrint.d` instruction (requires lsx). + pub inline fn @"vfrint.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d3800, p0, p1); + } + + /// Encodes a `vfrint.s` instruction (requires lsx). + pub inline fn @"vfrint.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d3400, p0, p1); + } + + /// Encodes a `vfrintrm.d` instruction (requires lsx). + pub inline fn @"vfrintrm.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d4800, p0, p1); + } + + /// Encodes a `vfrintrm.s` instruction (requires lsx). + pub inline fn @"vfrintrm.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d4400, p0, p1); + } + + /// Encodes a `vfrintrne.d` instruction (requires lsx). + pub inline fn @"vfrintrne.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d7800, p0, p1); + } + + /// Encodes a `vfrintrne.s` instruction (requires lsx). + pub inline fn @"vfrintrne.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d7400, p0, p1); + } + + /// Encodes a `vfrintrp.d` instruction (requires lsx). + pub inline fn @"vfrintrp.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d5800, p0, p1); + } + + /// Encodes a `vfrintrp.s` instruction (requires lsx). + pub inline fn @"vfrintrp.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d5400, p0, p1); + } + + /// Encodes a `vfrintrz.d` instruction (requires lsx). + pub inline fn @"vfrintrz.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d6800, p0, p1); + } + + /// Encodes a `vfrintrz.s` instruction (requires lsx). + pub inline fn @"vfrintrz.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d6400, p0, p1); + } + + /// Encodes a `vfrsqrt.d` instruction (requires lsx). + pub inline fn @"vfrsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d0800, p0, p1); + } + + /// Encodes a `vfrsqrt.s` instruction (requires lsx). + pub inline fn @"vfrsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d0400, p0, p1); + } + + /// Encodes a `vfrsqrte.d` instruction (requires lsx). + pub inline fn @"vfrsqrte.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d2800, p0, p1); + } + + /// Encodes a `vfrsqrte.s` instruction (requires lsx). + pub inline fn @"vfrsqrte.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d2400, p0, p1); + } + + /// Encodes a `vfrstp.b` instruction (requires lsx). + pub inline fn @"vfrstp.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712b0000, p0, p1, p2); + } + + /// Encodes a `vfrstp.h` instruction (requires lsx). + pub inline fn @"vfrstp.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712b8000, p0, p1, p2); + } + + /// Encodes a `vfrstpi.b` instruction (requires lsx). + pub inline fn @"vfrstpi.b"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x729a0000, p0, p1, p2); + } + + /// Encodes a `vfrstpi.h` instruction (requires lsx). + pub inline fn @"vfrstpi.h"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x729a8000, p0, p1, p2); + } + + /// Encodes a `vfsqrt.d` instruction (requires lsx). + pub inline fn @"vfsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ce800, p0, p1); + } + + /// Encodes a `vfsqrt.s` instruction (requires lsx). + pub inline fn @"vfsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ce400, p0, p1); + } + + /// Encodes a `vfsub.d` instruction (requires lsx). + pub inline fn @"vfsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71330000, p0, p1, p2); + } + + /// Encodes a `vfsub.s` instruction (requires lsx). + pub inline fn @"vfsub.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71328000, p0, p1, p2); + } + + /// Encodes a `vftint.l.d` instruction (requires lsx). + pub inline fn @"vftint.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3400, p0, p1); + } + + /// Encodes a `vftint.lu.d` instruction (requires lsx). + pub inline fn @"vftint.lu.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5c00, p0, p1); + } + + /// Encodes a `vftint.w.d` instruction (requires lsx). + pub inline fn @"vftint.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71498000, p0, p1, p2); + } + + /// Encodes a `vftint.w.s` instruction (requires lsx). + pub inline fn @"vftint.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3000, p0, p1); + } + + /// Encodes a `vftint.wu.s` instruction (requires lsx). + pub inline fn @"vftint.wu.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5800, p0, p1); + } + + /// Encodes a `vftinth.l.s` instruction (requires lsx). + pub inline fn @"vftinth.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8400, p0, p1); + } + + /// Encodes a `vftintl.l.s` instruction (requires lsx). + pub inline fn @"vftintl.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8000, p0, p1); + } + + /// Encodes a `vftintrm.l.d` instruction (requires lsx). + pub inline fn @"vftintrm.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3c00, p0, p1); + } + + /// Encodes a `vftintrm.w.d` instruction (requires lsx). + pub inline fn @"vftintrm.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714a0000, p0, p1, p2); + } + + /// Encodes a `vftintrm.w.s` instruction (requires lsx). + pub inline fn @"vftintrm.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3800, p0, p1); + } + + /// Encodes a `vftintrmh.l.s` instruction (requires lsx). + pub inline fn @"vftintrmh.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8c00, p0, p1); + } + + /// Encodes a `vftintrml.l.s` instruction (requires lsx). + pub inline fn @"vftintrml.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8800, p0, p1); + } + + /// Encodes a `vftintrne.l.d` instruction (requires lsx). + pub inline fn @"vftintrne.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5400, p0, p1); + } + + /// Encodes a `vftintrne.w.d` instruction (requires lsx). + pub inline fn @"vftintrne.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714b8000, p0, p1, p2); + } + + /// Encodes a `vftintrne.w.s` instruction (requires lsx). + pub inline fn @"vftintrne.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5000, p0, p1); + } + + /// Encodes a `vftintrneh.l.s` instruction (requires lsx). + pub inline fn @"vftintrneh.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ea400, p0, p1); + } + + /// Encodes a `vftintrnel.l.s` instruction (requires lsx). + pub inline fn @"vftintrnel.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ea000, p0, p1); + } + + /// Encodes a `vftintrp.l.d` instruction (requires lsx). + pub inline fn @"vftintrp.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4400, p0, p1); + } + + /// Encodes a `vftintrp.w.d` instruction (requires lsx). + pub inline fn @"vftintrp.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714a8000, p0, p1, p2); + } + + /// Encodes a `vftintrp.w.s` instruction (requires lsx). + pub inline fn @"vftintrp.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4000, p0, p1); + } + + /// Encodes a `vftintrph.l.s` instruction (requires lsx). + pub inline fn @"vftintrph.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9400, p0, p1); + } + + /// Encodes a `vftintrpl.l.s` instruction (requires lsx). + pub inline fn @"vftintrpl.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9000, p0, p1); + } + + /// Encodes a `vftintrz.l.d` instruction (requires lsx). + pub inline fn @"vftintrz.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4c00, p0, p1); + } + + /// Encodes a `vftintrz.lu.d` instruction (requires lsx). + pub inline fn @"vftintrz.lu.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e7400, p0, p1); + } + + /// Encodes a `vftintrz.w.d` instruction (requires lsx). + pub inline fn @"vftintrz.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714b0000, p0, p1, p2); + } + + /// Encodes a `vftintrz.w.s` instruction (requires lsx). + pub inline fn @"vftintrz.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4800, p0, p1); + } + + /// Encodes a `vftintrz.wu.s` instruction (requires lsx). + pub inline fn @"vftintrz.wu.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e7000, p0, p1); + } + + /// Encodes a `vftintrzh.l.s` instruction (requires lsx). + pub inline fn @"vftintrzh.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9c00, p0, p1); + } + + /// Encodes a `vftintrzl.l.s` instruction (requires lsx). + pub inline fn @"vftintrzl.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9800, p0, p1); + } + + /// Encodes a `vhaddw.d.w` instruction (requires lsx). + pub inline fn @"vhaddw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70550000, p0, p1, p2); + } + + /// Encodes a `vhaddw.du.wu` instruction (requires lsx). + pub inline fn @"vhaddw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70590000, p0, p1, p2); + } + + /// Encodes a `vhaddw.h.b` instruction (requires lsx). + pub inline fn @"vhaddw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70540000, p0, p1, p2); + } + + /// Encodes a `vhaddw.hu.bu` instruction (requires lsx). + pub inline fn @"vhaddw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70580000, p0, p1, p2); + } + + /// Encodes a `vhaddw.q.d` instruction (requires lsx). + pub inline fn @"vhaddw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70558000, p0, p1, p2); + } + + /// Encodes a `vhaddw.qu.du` instruction (requires lsx). + pub inline fn @"vhaddw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70598000, p0, p1, p2); + } + + /// Encodes a `vhaddw.w.h` instruction (requires lsx). + pub inline fn @"vhaddw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70548000, p0, p1, p2); + } + + /// Encodes a `vhaddw.wu.hu` instruction (requires lsx). + pub inline fn @"vhaddw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70588000, p0, p1, p2); + } + + /// Encodes a `vhsubw.d.w` instruction (requires lsx). + pub inline fn @"vhsubw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70570000, p0, p1, p2); + } + + /// Encodes a `vhsubw.du.wu` instruction (requires lsx). + pub inline fn @"vhsubw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705b0000, p0, p1, p2); + } + + /// Encodes a `vhsubw.h.b` instruction (requires lsx). + pub inline fn @"vhsubw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70560000, p0, p1, p2); + } + + /// Encodes a `vhsubw.hu.bu` instruction (requires lsx). + pub inline fn @"vhsubw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705a0000, p0, p1, p2); + } + + /// Encodes a `vhsubw.q.d` instruction (requires lsx). + pub inline fn @"vhsubw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70578000, p0, p1, p2); + } + + /// Encodes a `vhsubw.qu.du` instruction (requires lsx). + pub inline fn @"vhsubw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705b8000, p0, p1, p2); + } + + /// Encodes a `vhsubw.w.h` instruction (requires lsx). + pub inline fn @"vhsubw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70568000, p0, p1, p2); + } + + /// Encodes a `vhsubw.wu.hu` instruction (requires lsx). + pub inline fn @"vhsubw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705a8000, p0, p1, p2); + } + + /// Encodes a `vilvh.b` instruction (requires lsx). + pub inline fn @"vilvh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711c0000, p0, p1, p2); + } + + /// Encodes a `vilvh.d` instruction (requires lsx). + pub inline fn @"vilvh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711d8000, p0, p1, p2); + } + + /// Encodes a `vilvh.h` instruction (requires lsx). + pub inline fn @"vilvh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711c8000, p0, p1, p2); + } + + /// Encodes a `vilvh.w` instruction (requires lsx). + pub inline fn @"vilvh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711d0000, p0, p1, p2); + } + + /// Encodes a `vilvl.b` instruction (requires lsx). + pub inline fn @"vilvl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711a0000, p0, p1, p2); + } + + /// Encodes a `vilvl.d` instruction (requires lsx). + pub inline fn @"vilvl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711b8000, p0, p1, p2); + } + + /// Encodes a `vilvl.h` instruction (requires lsx). + pub inline fn @"vilvl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711a8000, p0, p1, p2); + } + + /// Encodes a `vilvl.w` instruction (requires lsx). + pub inline fn @"vilvl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711b0000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.b` instruction (requires lsx). + pub inline fn @"vinsgr2vr.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdJUk4(0x72eb8000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.d` instruction (requires lsx). + pub inline fn @"vinsgr2vr.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeVdJUk1(0x72ebf000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.h` instruction (requires lsx). + pub inline fn @"vinsgr2vr.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdJUk3(0x72ebc000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.w` instruction (requires lsx). + pub inline fn @"vinsgr2vr.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeVdJUk2(0x72ebe000, p0, p1, p2); + } + + /// Encodes a `vld` instruction (requires lsx). + pub inline fn vld(p0: Register, p1: Register, p2: i12) Instruction { + return encodeVdJSk12(0x2c000000, p0, p1, p2); + } + + /// Encodes a `vldi` instruction (requires lsx). + pub inline fn vldi(p0: Register, p1: i13) Instruction { + return encodeVdSj13(0x73e00000, p0, p1); + } + + /// Encodes a `vldrepl.b` instruction (requires lsx). + pub inline fn @"vldrepl.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeVdJSk12(0x30800000, p0, p1, p2); + } + + /// Encodes a `vldrepl.d` instruction (requires lsx). + pub inline fn @"vldrepl.d"(p0: Register, p1: Register, p2: i9) Instruction { + return encodeVdJSk9ps3(0x30100000, p0, p1, p2); + } + + /// Encodes a `vldrepl.h` instruction (requires lsx). + pub inline fn @"vldrepl.h"(p0: Register, p1: Register, p2: i11) Instruction { + return encodeVdJSk11ps1(0x30400000, p0, p1, p2); + } + + /// Encodes a `vldrepl.w` instruction (requires lsx). + pub inline fn @"vldrepl.w"(p0: Register, p1: Register, p2: i10) Instruction { + return encodeVdJSk10ps2(0x30200000, p0, p1, p2); + } + + /// Encodes a `vldx` instruction (requires lsx). + pub inline fn vldx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdJK(0x38400000, p0, p1, p2); + } + + /// Encodes a `vmadd.b` instruction (requires lsx). + pub inline fn @"vmadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a80000, p0, p1, p2); + } + + /// Encodes a `vmadd.d` instruction (requires lsx). + pub inline fn @"vmadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a98000, p0, p1, p2); + } + + /// Encodes a `vmadd.h` instruction (requires lsx). + pub inline fn @"vmadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a88000, p0, p1, p2); + } + + /// Encodes a `vmadd.w` instruction (requires lsx). + pub inline fn @"vmadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a90000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.d.w` instruction (requires lsx). + pub inline fn @"vmaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ad0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.d.wu` instruction (requires lsx). + pub inline fn @"vmaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b50000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.d.wu.w` instruction (requires lsx). + pub inline fn @"vmaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bd0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.h.b` instruction (requires lsx). + pub inline fn @"vmaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ac0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.h.bu` instruction (requires lsx). + pub inline fn @"vmaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b40000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.h.bu.b` instruction (requires lsx). + pub inline fn @"vmaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bc0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.q.d` instruction (requires lsx). + pub inline fn @"vmaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ad8000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.q.du` instruction (requires lsx). + pub inline fn @"vmaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b58000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.q.du.d` instruction (requires lsx). + pub inline fn @"vmaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bd8000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.w.h` instruction (requires lsx). + pub inline fn @"vmaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ac8000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.w.hu` instruction (requires lsx). + pub inline fn @"vmaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b48000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.w.hu.h` instruction (requires lsx). + pub inline fn @"vmaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bc8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.d.w` instruction (requires lsx). + pub inline fn @"vmaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70af0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.d.wu` instruction (requires lsx). + pub inline fn @"vmaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b70000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.d.wu.w` instruction (requires lsx). + pub inline fn @"vmaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bf0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.h.b` instruction (requires lsx). + pub inline fn @"vmaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ae0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.h.bu` instruction (requires lsx). + pub inline fn @"vmaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b60000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.h.bu.b` instruction (requires lsx). + pub inline fn @"vmaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70be0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.q.d` instruction (requires lsx). + pub inline fn @"vmaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70af8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.q.du` instruction (requires lsx). + pub inline fn @"vmaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b78000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.q.du.d` instruction (requires lsx). + pub inline fn @"vmaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bf8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.w.h` instruction (requires lsx). + pub inline fn @"vmaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ae8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.w.hu` instruction (requires lsx). + pub inline fn @"vmaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b68000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.w.hu.h` instruction (requires lsx). + pub inline fn @"vmaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70be8000, p0, p1, p2); + } + + /// Encodes a `vmax.b` instruction (requires lsx). + pub inline fn @"vmax.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70700000, p0, p1, p2); + } + + /// Encodes a `vmax.bu` instruction (requires lsx). + pub inline fn @"vmax.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70740000, p0, p1, p2); + } + + /// Encodes a `vmax.d` instruction (requires lsx). + pub inline fn @"vmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70718000, p0, p1, p2); + } + + /// Encodes a `vmax.du` instruction (requires lsx). + pub inline fn @"vmax.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70758000, p0, p1, p2); + } + + /// Encodes a `vmax.h` instruction (requires lsx). + pub inline fn @"vmax.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70708000, p0, p1, p2); + } + + /// Encodes a `vmax.hu` instruction (requires lsx). + pub inline fn @"vmax.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70748000, p0, p1, p2); + } + + /// Encodes a `vmax.w` instruction (requires lsx). + pub inline fn @"vmax.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70710000, p0, p1, p2); + } + + /// Encodes a `vmax.wu` instruction (requires lsx). + pub inline fn @"vmax.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70750000, p0, p1, p2); + } + + /// Encodes a `vmaxi.b` instruction (requires lsx). + pub inline fn @"vmaxi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72900000, p0, p1, p2); + } + + /// Encodes a `vmaxi.bu` instruction (requires lsx). + pub inline fn @"vmaxi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72940000, p0, p1, p2); + } + + /// Encodes a `vmaxi.d` instruction (requires lsx). + pub inline fn @"vmaxi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72918000, p0, p1, p2); + } + + /// Encodes a `vmaxi.du` instruction (requires lsx). + pub inline fn @"vmaxi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72958000, p0, p1, p2); + } + + /// Encodes a `vmaxi.h` instruction (requires lsx). + pub inline fn @"vmaxi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72908000, p0, p1, p2); + } + + /// Encodes a `vmaxi.hu` instruction (requires lsx). + pub inline fn @"vmaxi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72948000, p0, p1, p2); + } + + /// Encodes a `vmaxi.w` instruction (requires lsx). + pub inline fn @"vmaxi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72910000, p0, p1, p2); + } + + /// Encodes a `vmaxi.wu` instruction (requires lsx). + pub inline fn @"vmaxi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72950000, p0, p1, p2); + } + + /// Encodes a `vmepatmsk.v` instruction (requires lsx). + pub inline fn @"vmepatmsk.v"(p0: Register, p1: u5, p2: u5) Instruction { + return encodeVdUj5Uk5(0x729b8000, p0, p1, p2); + } + + /// Encodes a `vmin.b` instruction (requires lsx). + pub inline fn @"vmin.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70720000, p0, p1, p2); + } + + /// Encodes a `vmin.bu` instruction (requires lsx). + pub inline fn @"vmin.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70760000, p0, p1, p2); + } + + /// Encodes a `vmin.d` instruction (requires lsx). + pub inline fn @"vmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70738000, p0, p1, p2); + } + + /// Encodes a `vmin.du` instruction (requires lsx). + pub inline fn @"vmin.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70778000, p0, p1, p2); + } + + /// Encodes a `vmin.h` instruction (requires lsx). + pub inline fn @"vmin.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70728000, p0, p1, p2); + } + + /// Encodes a `vmin.hu` instruction (requires lsx). + pub inline fn @"vmin.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70768000, p0, p1, p2); + } + + /// Encodes a `vmin.w` instruction (requires lsx). + pub inline fn @"vmin.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70730000, p0, p1, p2); + } + + /// Encodes a `vmin.wu` instruction (requires lsx). + pub inline fn @"vmin.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70770000, p0, p1, p2); + } + + /// Encodes a `vmini.b` instruction (requires lsx). + pub inline fn @"vmini.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72920000, p0, p1, p2); + } + + /// Encodes a `vmini.bu` instruction (requires lsx). + pub inline fn @"vmini.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72960000, p0, p1, p2); + } + + /// Encodes a `vmini.d` instruction (requires lsx). + pub inline fn @"vmini.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72938000, p0, p1, p2); + } + + /// Encodes a `vmini.du` instruction (requires lsx). + pub inline fn @"vmini.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72978000, p0, p1, p2); + } + + /// Encodes a `vmini.h` instruction (requires lsx). + pub inline fn @"vmini.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72928000, p0, p1, p2); + } + + /// Encodes a `vmini.hu` instruction (requires lsx). + pub inline fn @"vmini.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72968000, p0, p1, p2); + } + + /// Encodes a `vmini.w` instruction (requires lsx). + pub inline fn @"vmini.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72930000, p0, p1, p2); + } + + /// Encodes a `vmini.wu` instruction (requires lsx). + pub inline fn @"vmini.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72970000, p0, p1, p2); + } + + /// Encodes a `vmod.b` instruction (requires lsx). + pub inline fn @"vmod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e20000, p0, p1, p2); + } + + /// Encodes a `vmod.bu` instruction (requires lsx). + pub inline fn @"vmod.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e60000, p0, p1, p2); + } + + /// Encodes a `vmod.d` instruction (requires lsx). + pub inline fn @"vmod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e38000, p0, p1, p2); + } + + /// Encodes a `vmod.du` instruction (requires lsx). + pub inline fn @"vmod.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e78000, p0, p1, p2); + } + + /// Encodes a `vmod.h` instruction (requires lsx). + pub inline fn @"vmod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e28000, p0, p1, p2); + } + + /// Encodes a `vmod.hu` instruction (requires lsx). + pub inline fn @"vmod.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e68000, p0, p1, p2); + } + + /// Encodes a `vmod.w` instruction (requires lsx). + pub inline fn @"vmod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e30000, p0, p1, p2); + } + + /// Encodes a `vmod.wu` instruction (requires lsx). + pub inline fn @"vmod.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e70000, p0, p1, p2); + } + + /// Encodes a `vmskgez.b` instruction (requires lsx). + pub inline fn @"vmskgez.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c5000, p0, p1); + } + + /// Encodes a `vmskltz.b` instruction (requires lsx). + pub inline fn @"vmskltz.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4000, p0, p1); + } + + /// Encodes a `vmskltz.d` instruction (requires lsx). + pub inline fn @"vmskltz.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4c00, p0, p1); + } + + /// Encodes a `vmskltz.h` instruction (requires lsx). + pub inline fn @"vmskltz.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4400, p0, p1); + } + + /// Encodes a `vmskltz.w` instruction (requires lsx). + pub inline fn @"vmskltz.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4800, p0, p1); + } + + /// Encodes a `vmsknz.b` instruction (requires lsx). + pub inline fn @"vmsknz.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c6000, p0, p1); + } + + /// Encodes a `vmsub.b` instruction (requires lsx). + pub inline fn @"vmsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70aa0000, p0, p1, p2); + } + + /// Encodes a `vmsub.d` instruction (requires lsx). + pub inline fn @"vmsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ab8000, p0, p1, p2); + } + + /// Encodes a `vmsub.h` instruction (requires lsx). + pub inline fn @"vmsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70aa8000, p0, p1, p2); + } + + /// Encodes a `vmsub.w` instruction (requires lsx). + pub inline fn @"vmsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ab0000, p0, p1, p2); + } + + /// Encodes a `vmuh.b` instruction (requires lsx). + pub inline fn @"vmuh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70860000, p0, p1, p2); + } + + /// Encodes a `vmuh.bu` instruction (requires lsx). + pub inline fn @"vmuh.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70880000, p0, p1, p2); + } + + /// Encodes a `vmuh.d` instruction (requires lsx). + pub inline fn @"vmuh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70878000, p0, p1, p2); + } + + /// Encodes a `vmuh.du` instruction (requires lsx). + pub inline fn @"vmuh.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70898000, p0, p1, p2); + } + + /// Encodes a `vmuh.h` instruction (requires lsx). + pub inline fn @"vmuh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70868000, p0, p1, p2); + } + + /// Encodes a `vmuh.hu` instruction (requires lsx). + pub inline fn @"vmuh.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70888000, p0, p1, p2); + } + + /// Encodes a `vmuh.w` instruction (requires lsx). + pub inline fn @"vmuh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70870000, p0, p1, p2); + } + + /// Encodes a `vmuh.wu` instruction (requires lsx). + pub inline fn @"vmuh.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70890000, p0, p1, p2); + } + + /// Encodes a `vmul.b` instruction (requires lsx). + pub inline fn @"vmul.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70840000, p0, p1, p2); + } + + /// Encodes a `vmul.d` instruction (requires lsx). + pub inline fn @"vmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70858000, p0, p1, p2); + } + + /// Encodes a `vmul.h` instruction (requires lsx). + pub inline fn @"vmul.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70848000, p0, p1, p2); + } + + /// Encodes a `vmul.w` instruction (requires lsx). + pub inline fn @"vmul.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70850000, p0, p1, p2); + } + + /// Encodes a `vmulwev.d.w` instruction (requires lsx). + pub inline fn @"vmulwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70910000, p0, p1, p2); + } + + /// Encodes a `vmulwev.d.wu` instruction (requires lsx). + pub inline fn @"vmulwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70990000, p0, p1, p2); + } + + /// Encodes a `vmulwev.d.wu.w` instruction (requires lsx). + pub inline fn @"vmulwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a10000, p0, p1, p2); + } + + /// Encodes a `vmulwev.h.b` instruction (requires lsx). + pub inline fn @"vmulwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70900000, p0, p1, p2); + } + + /// Encodes a `vmulwev.h.bu` instruction (requires lsx). + pub inline fn @"vmulwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70980000, p0, p1, p2); + } + + /// Encodes a `vmulwev.h.bu.b` instruction (requires lsx). + pub inline fn @"vmulwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a00000, p0, p1, p2); + } + + /// Encodes a `vmulwev.q.d` instruction (requires lsx). + pub inline fn @"vmulwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70918000, p0, p1, p2); + } + + /// Encodes a `vmulwev.q.du` instruction (requires lsx). + pub inline fn @"vmulwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70998000, p0, p1, p2); + } + + /// Encodes a `vmulwev.q.du.d` instruction (requires lsx). + pub inline fn @"vmulwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a18000, p0, p1, p2); + } + + /// Encodes a `vmulwev.w.h` instruction (requires lsx). + pub inline fn @"vmulwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70908000, p0, p1, p2); + } + + /// Encodes a `vmulwev.w.hu` instruction (requires lsx). + pub inline fn @"vmulwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70988000, p0, p1, p2); + } + + /// Encodes a `vmulwev.w.hu.h` instruction (requires lsx). + pub inline fn @"vmulwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a08000, p0, p1, p2); + } + + /// Encodes a `vmulwod.d.w` instruction (requires lsx). + pub inline fn @"vmulwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70930000, p0, p1, p2); + } + + /// Encodes a `vmulwod.d.wu` instruction (requires lsx). + pub inline fn @"vmulwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709b0000, p0, p1, p2); + } + + /// Encodes a `vmulwod.d.wu.w` instruction (requires lsx). + pub inline fn @"vmulwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a30000, p0, p1, p2); + } + + /// Encodes a `vmulwod.h.b` instruction (requires lsx). + pub inline fn @"vmulwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70920000, p0, p1, p2); + } + + /// Encodes a `vmulwod.h.bu` instruction (requires lsx). + pub inline fn @"vmulwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709a0000, p0, p1, p2); + } + + /// Encodes a `vmulwod.h.bu.b` instruction (requires lsx). + pub inline fn @"vmulwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a20000, p0, p1, p2); + } + + /// Encodes a `vmulwod.q.d` instruction (requires lsx). + pub inline fn @"vmulwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70938000, p0, p1, p2); + } + + /// Encodes a `vmulwod.q.du` instruction (requires lsx). + pub inline fn @"vmulwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709b8000, p0, p1, p2); + } + + /// Encodes a `vmulwod.q.du.d` instruction (requires lsx). + pub inline fn @"vmulwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a38000, p0, p1, p2); + } + + /// Encodes a `vmulwod.w.h` instruction (requires lsx). + pub inline fn @"vmulwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70928000, p0, p1, p2); + } + + /// Encodes a `vmulwod.w.hu` instruction (requires lsx). + pub inline fn @"vmulwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709a8000, p0, p1, p2); + } + + /// Encodes a `vmulwod.w.hu.h` instruction (requires lsx). + pub inline fn @"vmulwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a28000, p0, p1, p2); + } + + /// Encodes a `vneg.b` instruction (requires lsx). + pub inline fn @"vneg.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3000, p0, p1); + } + + /// Encodes a `vneg.d` instruction (requires lsx). + pub inline fn @"vneg.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3c00, p0, p1); + } + + /// Encodes a `vneg.h` instruction (requires lsx). + pub inline fn @"vneg.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3400, p0, p1); + } + + /// Encodes a `vneg.w` instruction (requires lsx). + pub inline fn @"vneg.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3800, p0, p1); + } + + /// Encodes a `vnor.v` instruction (requires lsx). + pub inline fn @"vnor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71278000, p0, p1, p2); + } + + /// Encodes a `vnori.b` instruction (requires lsx). + pub inline fn @"vnori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73dc0000, p0, p1, p2); + } + + /// Encodes a `vor.v` instruction (requires lsx). + pub inline fn @"vor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71268000, p0, p1, p2); + } + + /// Encodes a `vori.b` instruction (requires lsx). + pub inline fn @"vori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73d40000, p0, p1, p2); + } + + /// Encodes a `vorn.v` instruction (requires lsx). + pub inline fn @"vorn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71288000, p0, p1, p2); + } + + /// Encodes a `vpackev.b` instruction (requires lsx). + pub inline fn @"vpackev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71160000, p0, p1, p2); + } + + /// Encodes a `vpackev.d` instruction (requires lsx). + pub inline fn @"vpackev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71178000, p0, p1, p2); + } + + /// Encodes a `vpackev.h` instruction (requires lsx). + pub inline fn @"vpackev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71168000, p0, p1, p2); + } + + /// Encodes a `vpackev.w` instruction (requires lsx). + pub inline fn @"vpackev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71170000, p0, p1, p2); + } + + /// Encodes a `vpackod.b` instruction (requires lsx). + pub inline fn @"vpackod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71180000, p0, p1, p2); + } + + /// Encodes a `vpackod.d` instruction (requires lsx). + pub inline fn @"vpackod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71198000, p0, p1, p2); + } + + /// Encodes a `vpackod.h` instruction (requires lsx). + pub inline fn @"vpackod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71188000, p0, p1, p2); + } + + /// Encodes a `vpackod.w` instruction (requires lsx). + pub inline fn @"vpackod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71190000, p0, p1, p2); + } + + /// Encodes a `vpcnt.b` instruction (requires lsx). + pub inline fn @"vpcnt.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2000, p0, p1); + } + + /// Encodes a `vpcnt.d` instruction (requires lsx). + pub inline fn @"vpcnt.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2c00, p0, p1); + } + + /// Encodes a `vpcnt.h` instruction (requires lsx). + pub inline fn @"vpcnt.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2400, p0, p1); + } + + /// Encodes a `vpcnt.w` instruction (requires lsx). + pub inline fn @"vpcnt.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2800, p0, p1); + } + + /// Encodes a `vpermi.w` instruction (requires lsx). + pub inline fn @"vpermi.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73e40000, p0, p1, p2); + } + + /// Encodes a `vpickev.b` instruction (requires lsx). + pub inline fn @"vpickev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711e0000, p0, p1, p2); + } + + /// Encodes a `vpickev.d` instruction (requires lsx). + pub inline fn @"vpickev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711f8000, p0, p1, p2); + } + + /// Encodes a `vpickev.h` instruction (requires lsx). + pub inline fn @"vpickev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711e8000, p0, p1, p2); + } + + /// Encodes a `vpickev.w` instruction (requires lsx). + pub inline fn @"vpickev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711f0000, p0, p1, p2); + } + + /// Encodes a `vpickod.b` instruction (requires lsx). + pub inline fn @"vpickod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71200000, p0, p1, p2); + } + + /// Encodes a `vpickod.d` instruction (requires lsx). + pub inline fn @"vpickod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71218000, p0, p1, p2); + } + + /// Encodes a `vpickod.h` instruction (requires lsx). + pub inline fn @"vpickod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71208000, p0, p1, p2); + } + + /// Encodes a `vpickod.w` instruction (requires lsx). + pub inline fn @"vpickod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71210000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.b` instruction (requires lsx). + pub inline fn @"vpickve2gr.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDVjUk4(0x72ef8000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.bu` instruction (requires lsx). + pub inline fn @"vpickve2gr.bu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDVjUk4(0x72f38000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.d` instruction (requires lsx). + pub inline fn @"vpickve2gr.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeDVjUk1(0x72eff000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.du` instruction (requires lsx). + pub inline fn @"vpickve2gr.du"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeDVjUk1(0x72f3f000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.h` instruction (requires lsx). + pub inline fn @"vpickve2gr.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDVjUk3(0x72efc000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.hu` instruction (requires lsx). + pub inline fn @"vpickve2gr.hu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDVjUk3(0x72f3c000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.w` instruction (requires lsx). + pub inline fn @"vpickve2gr.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDVjUk2(0x72efe000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.wu` instruction (requires lsx). + pub inline fn @"vpickve2gr.wu"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDVjUk2(0x72f3e000, p0, p1, p2); + } + + /// Encodes a `vreplgr2vr.b` instruction (requires lsx). + pub inline fn @"vreplgr2vr.b"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0000, p0, p1); + } + + /// Encodes a `vreplgr2vr.d` instruction (requires lsx). + pub inline fn @"vreplgr2vr.d"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0c00, p0, p1); + } + + /// Encodes a `vreplgr2vr.h` instruction (requires lsx). + pub inline fn @"vreplgr2vr.h"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0400, p0, p1); + } + + /// Encodes a `vreplgr2vr.w` instruction (requires lsx). + pub inline fn @"vreplgr2vr.w"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0800, p0, p1); + } + + /// Encodes a `vreplve.b` instruction (requires lsx). + pub inline fn @"vreplve.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71220000, p0, p1, p2); + } + + /// Encodes a `vreplve.d` instruction (requires lsx). + pub inline fn @"vreplve.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71238000, p0, p1, p2); + } + + /// Encodes a `vreplve.h` instruction (requires lsx). + pub inline fn @"vreplve.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71228000, p0, p1, p2); + } + + /// Encodes a `vreplve.w` instruction (requires lsx). + pub inline fn @"vreplve.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71230000, p0, p1, p2); + } + + /// Encodes a `vreplvei.b` instruction (requires lsx). + pub inline fn @"vreplvei.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72f78000, p0, p1, p2); + } + + /// Encodes a `vreplvei.d` instruction (requires lsx). + pub inline fn @"vreplvei.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeVdVjUk1(0x72f7f000, p0, p1, p2); + } + + /// Encodes a `vreplvei.h` instruction (requires lsx). + pub inline fn @"vreplvei.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72f7c000, p0, p1, p2); + } + + /// Encodes a `vreplvei.w` instruction (requires lsx). + pub inline fn @"vreplvei.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeVdVjUk2(0x72f7e000, p0, p1, p2); + } + + /// Encodes a `vrotr.b` instruction (requires lsx). + pub inline fn @"vrotr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ee0000, p0, p1, p2); + } + + /// Encodes a `vrotr.d` instruction (requires lsx). + pub inline fn @"vrotr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ef8000, p0, p1, p2); + } + + /// Encodes a `vrotr.h` instruction (requires lsx). + pub inline fn @"vrotr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ee8000, p0, p1, p2); + } + + /// Encodes a `vrotr.w` instruction (requires lsx). + pub inline fn @"vrotr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ef0000, p0, p1, p2); + } + + /// Encodes a `vrotri.b` instruction (requires lsx). + pub inline fn @"vrotri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72a02000, p0, p1, p2); + } + + /// Encodes a `vrotri.d` instruction (requires lsx). + pub inline fn @"vrotri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x72a10000, p0, p1, p2); + } + + /// Encodes a `vrotri.h` instruction (requires lsx). + pub inline fn @"vrotri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72a04000, p0, p1, p2); + } + + /// Encodes a `vrotri.w` instruction (requires lsx). + pub inline fn @"vrotri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72a08000, p0, p1, p2); + } + + /// Encodes a `vsadd.b` instruction (requires lsx). + pub inline fn @"vsadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70460000, p0, p1, p2); + } + + /// Encodes a `vsadd.bu` instruction (requires lsx). + pub inline fn @"vsadd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704a0000, p0, p1, p2); + } + + /// Encodes a `vsadd.d` instruction (requires lsx). + pub inline fn @"vsadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70478000, p0, p1, p2); + } + + /// Encodes a `vsadd.du` instruction (requires lsx). + pub inline fn @"vsadd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704b8000, p0, p1, p2); + } + + /// Encodes a `vsadd.h` instruction (requires lsx). + pub inline fn @"vsadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70468000, p0, p1, p2); + } + + /// Encodes a `vsadd.hu` instruction (requires lsx). + pub inline fn @"vsadd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704a8000, p0, p1, p2); + } + + /// Encodes a `vsadd.w` instruction (requires lsx). + pub inline fn @"vsadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70470000, p0, p1, p2); + } + + /// Encodes a `vsadd.wu` instruction (requires lsx). + pub inline fn @"vsadd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704b0000, p0, p1, p2); + } + + /// Encodes a `vsat.b` instruction (requires lsx). + pub inline fn @"vsat.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73242000, p0, p1, p2); + } + + /// Encodes a `vsat.bu` instruction (requires lsx). + pub inline fn @"vsat.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73282000, p0, p1, p2); + } + + /// Encodes a `vsat.d` instruction (requires lsx). + pub inline fn @"vsat.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73250000, p0, p1, p2); + } + + /// Encodes a `vsat.du` instruction (requires lsx). + pub inline fn @"vsat.du"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73290000, p0, p1, p2); + } + + /// Encodes a `vsat.h` instruction (requires lsx). + pub inline fn @"vsat.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73244000, p0, p1, p2); + } + + /// Encodes a `vsat.hu` instruction (requires lsx). + pub inline fn @"vsat.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73284000, p0, p1, p2); + } + + /// Encodes a `vsat.w` instruction (requires lsx). + pub inline fn @"vsat.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73248000, p0, p1, p2); + } + + /// Encodes a `vsat.wu` instruction (requires lsx). + pub inline fn @"vsat.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73288000, p0, p1, p2); + } + + /// Encodes a `vseq.b` instruction (requires lsx). + pub inline fn @"vseq.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70000000, p0, p1, p2); + } + + /// Encodes a `vseq.d` instruction (requires lsx). + pub inline fn @"vseq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70018000, p0, p1, p2); + } + + /// Encodes a `vseq.h` instruction (requires lsx). + pub inline fn @"vseq.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70008000, p0, p1, p2); + } + + /// Encodes a `vseq.w` instruction (requires lsx). + pub inline fn @"vseq.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70010000, p0, p1, p2); + } + + /// Encodes a `vseqi.b` instruction (requires lsx). + pub inline fn @"vseqi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72800000, p0, p1, p2); + } + + /// Encodes a `vseqi.d` instruction (requires lsx). + pub inline fn @"vseqi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72818000, p0, p1, p2); + } + + /// Encodes a `vseqi.h` instruction (requires lsx). + pub inline fn @"vseqi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72808000, p0, p1, p2); + } + + /// Encodes a `vseqi.w` instruction (requires lsx). + pub inline fn @"vseqi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72810000, p0, p1, p2); + } + + /// Encodes a `vsetallnez.b` instruction (requires f & lsx). + pub inline fn @"vsetallnez.b"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cb000, p0, p1); + } + + /// Encodes a `vsetallnez.d` instruction (requires f & lsx). + pub inline fn @"vsetallnez.d"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cbc00, p0, p1); + } + + /// Encodes a `vsetallnez.h` instruction (requires f & lsx). + pub inline fn @"vsetallnez.h"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cb400, p0, p1); + } + + /// Encodes a `vsetallnez.w` instruction (requires f & lsx). + pub inline fn @"vsetallnez.w"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cb800, p0, p1); + } + + /// Encodes a `vsetanyeqz.b` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.b"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729ca000, p0, p1); + } + + /// Encodes a `vsetanyeqz.d` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.d"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cac00, p0, p1); + } + + /// Encodes a `vsetanyeqz.h` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.h"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729ca400, p0, p1); + } + + /// Encodes a `vsetanyeqz.w` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.w"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729ca800, p0, p1); + } + + /// Encodes a `vseteqz.v` instruction (requires f & lsx). + pub inline fn @"vseteqz.v"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729c9800, p0, p1); + } + + /// Encodes a `vsetnez.v` instruction (requires f & lsx). + pub inline fn @"vsetnez.v"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729c9c00, p0, p1); + } + + /// Encodes a `vshuf.b` instruction (requires lsx). + pub inline fn @"vshuf.b"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x0d500000, p0, p1, p2, p3); + } + + /// Encodes a `vshuf.d` instruction (requires lsx). + pub inline fn @"vshuf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x717b8000, p0, p1, p2); + } + + /// Encodes a `vshuf.h` instruction (requires lsx). + pub inline fn @"vshuf.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x717a8000, p0, p1, p2); + } + + /// Encodes a `vshuf.w` instruction (requires lsx). + pub inline fn @"vshuf.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x717b0000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.b` instruction (requires lsx). + pub inline fn @"vshuf4i.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73900000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.d` instruction (requires lsx). + pub inline fn @"vshuf4i.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x739c0000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.h` instruction (requires lsx). + pub inline fn @"vshuf4i.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73940000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.w` instruction (requires lsx). + pub inline fn @"vshuf4i.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73980000, p0, p1, p2); + } + + /// Encodes a `vsigncov.b` instruction (requires lsx). + pub inline fn @"vsigncov.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712e0000, p0, p1, p2); + } + + /// Encodes a `vsigncov.d` instruction (requires lsx). + pub inline fn @"vsigncov.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712f8000, p0, p1, p2); + } + + /// Encodes a `vsigncov.h` instruction (requires lsx). + pub inline fn @"vsigncov.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712e8000, p0, p1, p2); + } + + /// Encodes a `vsigncov.w` instruction (requires lsx). + pub inline fn @"vsigncov.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712f0000, p0, p1, p2); + } + + /// Encodes a `vsle.b` instruction (requires lsx). + pub inline fn @"vsle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70020000, p0, p1, p2); + } + + /// Encodes a `vsle.bu` instruction (requires lsx). + pub inline fn @"vsle.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70040000, p0, p1, p2); + } + + /// Encodes a `vsle.d` instruction (requires lsx). + pub inline fn @"vsle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70038000, p0, p1, p2); + } + + /// Encodes a `vsle.du` instruction (requires lsx). + pub inline fn @"vsle.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70058000, p0, p1, p2); + } + + /// Encodes a `vsle.h` instruction (requires lsx). + pub inline fn @"vsle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70028000, p0, p1, p2); + } + + /// Encodes a `vsle.hu` instruction (requires lsx). + pub inline fn @"vsle.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70048000, p0, p1, p2); + } + + /// Encodes a `vsle.w` instruction (requires lsx). + pub inline fn @"vsle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70030000, p0, p1, p2); + } + + /// Encodes a `vsle.wu` instruction (requires lsx). + pub inline fn @"vsle.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70050000, p0, p1, p2); + } + + /// Encodes a `vslei.b` instruction (requires lsx). + pub inline fn @"vslei.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72820000, p0, p1, p2); + } + + /// Encodes a `vslei.bu` instruction (requires lsx). + pub inline fn @"vslei.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72840000, p0, p1, p2); + } + + /// Encodes a `vslei.d` instruction (requires lsx). + pub inline fn @"vslei.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72838000, p0, p1, p2); + } + + /// Encodes a `vslei.du` instruction (requires lsx). + pub inline fn @"vslei.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72858000, p0, p1, p2); + } + + /// Encodes a `vslei.h` instruction (requires lsx). + pub inline fn @"vslei.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72828000, p0, p1, p2); + } + + /// Encodes a `vslei.hu` instruction (requires lsx). + pub inline fn @"vslei.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72848000, p0, p1, p2); + } + + /// Encodes a `vslei.w` instruction (requires lsx). + pub inline fn @"vslei.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72830000, p0, p1, p2); + } + + /// Encodes a `vslei.wu` instruction (requires lsx). + pub inline fn @"vslei.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72850000, p0, p1, p2); + } + + /// Encodes a `vsll.b` instruction (requires lsx). + pub inline fn @"vsll.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e80000, p0, p1, p2); + } + + /// Encodes a `vsll.d` instruction (requires lsx). + pub inline fn @"vsll.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e98000, p0, p1, p2); + } + + /// Encodes a `vsll.h` instruction (requires lsx). + pub inline fn @"vsll.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e88000, p0, p1, p2); + } + + /// Encodes a `vsll.w` instruction (requires lsx). + pub inline fn @"vsll.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e90000, p0, p1, p2); + } + + /// Encodes a `vslli.b` instruction (requires lsx). + pub inline fn @"vslli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x732c2000, p0, p1, p2); + } + + /// Encodes a `vslli.d` instruction (requires lsx). + pub inline fn @"vslli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x732d0000, p0, p1, p2); + } + + /// Encodes a `vslli.h` instruction (requires lsx). + pub inline fn @"vslli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x732c4000, p0, p1, p2); + } + + /// Encodes a `vslli.w` instruction (requires lsx). + pub inline fn @"vslli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x732c8000, p0, p1, p2); + } + + /// Encodes a `vsllwil.d.w` instruction (requires lsx). + pub inline fn @"vsllwil.d.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73088000, p0, p1, p2); + } + + /// Encodes a `vsllwil.du.wu` instruction (requires lsx). + pub inline fn @"vsllwil.du.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x730c8000, p0, p1, p2); + } + + /// Encodes a `vsllwil.h.b` instruction (requires lsx). + pub inline fn @"vsllwil.h.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73082000, p0, p1, p2); + } + + /// Encodes a `vsllwil.hu.bu` instruction (requires lsx). + pub inline fn @"vsllwil.hu.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x730c2000, p0, p1, p2); + } + + /// Encodes a `vsllwil.w.h` instruction (requires lsx). + pub inline fn @"vsllwil.w.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73084000, p0, p1, p2); + } + + /// Encodes a `vsllwil.wu.hu` instruction (requires lsx). + pub inline fn @"vsllwil.wu.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x730c4000, p0, p1, p2); + } + + /// Encodes a `vslt.b` instruction (requires lsx). + pub inline fn @"vslt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70060000, p0, p1, p2); + } + + /// Encodes a `vslt.bu` instruction (requires lsx). + pub inline fn @"vslt.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70080000, p0, p1, p2); + } + + /// Encodes a `vslt.d` instruction (requires lsx). + pub inline fn @"vslt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70078000, p0, p1, p2); + } + + /// Encodes a `vslt.du` instruction (requires lsx). + pub inline fn @"vslt.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70098000, p0, p1, p2); + } + + /// Encodes a `vslt.h` instruction (requires lsx). + pub inline fn @"vslt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70068000, p0, p1, p2); + } + + /// Encodes a `vslt.hu` instruction (requires lsx). + pub inline fn @"vslt.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70088000, p0, p1, p2); + } + + /// Encodes a `vslt.w` instruction (requires lsx). + pub inline fn @"vslt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70070000, p0, p1, p2); + } + + /// Encodes a `vslt.wu` instruction (requires lsx). + pub inline fn @"vslt.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70090000, p0, p1, p2); + } + + /// Encodes a `vslti.b` instruction (requires lsx). + pub inline fn @"vslti.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72860000, p0, p1, p2); + } + + /// Encodes a `vslti.bu` instruction (requires lsx). + pub inline fn @"vslti.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72880000, p0, p1, p2); + } + + /// Encodes a `vslti.d` instruction (requires lsx). + pub inline fn @"vslti.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72878000, p0, p1, p2); + } + + /// Encodes a `vslti.du` instruction (requires lsx). + pub inline fn @"vslti.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72898000, p0, p1, p2); + } + + /// Encodes a `vslti.h` instruction (requires lsx). + pub inline fn @"vslti.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72868000, p0, p1, p2); + } + + /// Encodes a `vslti.hu` instruction (requires lsx). + pub inline fn @"vslti.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72888000, p0, p1, p2); + } + + /// Encodes a `vslti.w` instruction (requires lsx). + pub inline fn @"vslti.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72870000, p0, p1, p2); + } + + /// Encodes a `vslti.wu` instruction (requires lsx). + pub inline fn @"vslti.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72890000, p0, p1, p2); + } + + /// Encodes a `vsra.b` instruction (requires lsx). + pub inline fn @"vsra.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ec0000, p0, p1, p2); + } + + /// Encodes a `vsra.d` instruction (requires lsx). + pub inline fn @"vsra.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ed8000, p0, p1, p2); + } + + /// Encodes a `vsra.h` instruction (requires lsx). + pub inline fn @"vsra.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ec8000, p0, p1, p2); + } + + /// Encodes a `vsra.w` instruction (requires lsx). + pub inline fn @"vsra.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ed0000, p0, p1, p2); + } + + /// Encodes a `vsrai.b` instruction (requires lsx). + pub inline fn @"vsrai.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73342000, p0, p1, p2); + } + + /// Encodes a `vsrai.d` instruction (requires lsx). + pub inline fn @"vsrai.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73350000, p0, p1, p2); + } + + /// Encodes a `vsrai.h` instruction (requires lsx). + pub inline fn @"vsrai.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73344000, p0, p1, p2); + } + + /// Encodes a `vsrai.w` instruction (requires lsx). + pub inline fn @"vsrai.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73348000, p0, p1, p2); + } + + /// Encodes a `vsran.b.h` instruction (requires lsx). + pub inline fn @"vsran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f68000, p0, p1, p2); + } + + /// Encodes a `vsran.h.w` instruction (requires lsx). + pub inline fn @"vsran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f70000, p0, p1, p2); + } + + /// Encodes a `vsran.w.d` instruction (requires lsx). + pub inline fn @"vsran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f78000, p0, p1, p2); + } + + /// Encodes a `vsrani.b.h` instruction (requires lsx). + pub inline fn @"vsrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73584000, p0, p1, p2); + } + + /// Encodes a `vsrani.d.q` instruction (requires lsx). + pub inline fn @"vsrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x735a0000, p0, p1, p2); + } + + /// Encodes a `vsrani.h.w` instruction (requires lsx). + pub inline fn @"vsrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73588000, p0, p1, p2); + } + + /// Encodes a `vsrani.w.d` instruction (requires lsx). + pub inline fn @"vsrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73590000, p0, p1, p2); + } + + /// Encodes a `vsrar.b` instruction (requires lsx). + pub inline fn @"vsrar.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f20000, p0, p1, p2); + } + + /// Encodes a `vsrar.d` instruction (requires lsx). + pub inline fn @"vsrar.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f38000, p0, p1, p2); + } + + /// Encodes a `vsrar.h` instruction (requires lsx). + pub inline fn @"vsrar.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f28000, p0, p1, p2); + } + + /// Encodes a `vsrar.w` instruction (requires lsx). + pub inline fn @"vsrar.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f30000, p0, p1, p2); + } + + /// Encodes a `vsrari.b` instruction (requires lsx). + pub inline fn @"vsrari.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72a82000, p0, p1, p2); + } + + /// Encodes a `vsrari.d` instruction (requires lsx). + pub inline fn @"vsrari.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x72a90000, p0, p1, p2); + } + + /// Encodes a `vsrari.h` instruction (requires lsx). + pub inline fn @"vsrari.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72a84000, p0, p1, p2); + } + + /// Encodes a `vsrari.w` instruction (requires lsx). + pub inline fn @"vsrari.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72a88000, p0, p1, p2); + } + + /// Encodes a `vsrarn.b.h` instruction (requires lsx). + pub inline fn @"vsrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fa8000, p0, p1, p2); + } + + /// Encodes a `vsrarn.h.w` instruction (requires lsx). + pub inline fn @"vsrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fb0000, p0, p1, p2); + } + + /// Encodes a `vsrarn.w.d` instruction (requires lsx). + pub inline fn @"vsrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fb8000, p0, p1, p2); + } + + /// Encodes a `vsrarni.b.h` instruction (requires lsx). + pub inline fn @"vsrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x735c4000, p0, p1, p2); + } + + /// Encodes a `vsrarni.d.q` instruction (requires lsx). + pub inline fn @"vsrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x735e0000, p0, p1, p2); + } + + /// Encodes a `vsrarni.h.w` instruction (requires lsx). + pub inline fn @"vsrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x735c8000, p0, p1, p2); + } + + /// Encodes a `vsrarni.w.d` instruction (requires lsx). + pub inline fn @"vsrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x735d0000, p0, p1, p2); + } + + /// Encodes a `vsrl.b` instruction (requires lsx). + pub inline fn @"vsrl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ea0000, p0, p1, p2); + } + + /// Encodes a `vsrl.d` instruction (requires lsx). + pub inline fn @"vsrl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70eb8000, p0, p1, p2); + } + + /// Encodes a `vsrl.h` instruction (requires lsx). + pub inline fn @"vsrl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ea8000, p0, p1, p2); + } + + /// Encodes a `vsrl.w` instruction (requires lsx). + pub inline fn @"vsrl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70eb0000, p0, p1, p2); + } + + /// Encodes a `vsrli.b` instruction (requires lsx). + pub inline fn @"vsrli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73302000, p0, p1, p2); + } + + /// Encodes a `vsrli.d` instruction (requires lsx). + pub inline fn @"vsrli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73310000, p0, p1, p2); + } + + /// Encodes a `vsrli.h` instruction (requires lsx). + pub inline fn @"vsrli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73304000, p0, p1, p2); + } + + /// Encodes a `vsrli.w` instruction (requires lsx). + pub inline fn @"vsrli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73308000, p0, p1, p2); + } + + /// Encodes a `vsrln.b.h` instruction (requires lsx). + pub inline fn @"vsrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f48000, p0, p1, p2); + } + + /// Encodes a `vsrln.h.w` instruction (requires lsx). + pub inline fn @"vsrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f50000, p0, p1, p2); + } + + /// Encodes a `vsrln.w.d` instruction (requires lsx). + pub inline fn @"vsrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f58000, p0, p1, p2); + } + + /// Encodes a `vsrlni.b.h` instruction (requires lsx). + pub inline fn @"vsrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73404000, p0, p1, p2); + } + + /// Encodes a `vsrlni.d.q` instruction (requires lsx). + pub inline fn @"vsrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73420000, p0, p1, p2); + } + + /// Encodes a `vsrlni.h.w` instruction (requires lsx). + pub inline fn @"vsrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73408000, p0, p1, p2); + } + + /// Encodes a `vsrlni.w.d` instruction (requires lsx). + pub inline fn @"vsrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73410000, p0, p1, p2); + } + + /// Encodes a `vsrlr.b` instruction (requires lsx). + pub inline fn @"vsrlr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f00000, p0, p1, p2); + } + + /// Encodes a `vsrlr.d` instruction (requires lsx). + pub inline fn @"vsrlr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f18000, p0, p1, p2); + } + + /// Encodes a `vsrlr.h` instruction (requires lsx). + pub inline fn @"vsrlr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f08000, p0, p1, p2); + } + + /// Encodes a `vsrlr.w` instruction (requires lsx). + pub inline fn @"vsrlr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f10000, p0, p1, p2); + } + + /// Encodes a `vsrlri.b` instruction (requires lsx). + pub inline fn @"vsrlri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72a42000, p0, p1, p2); + } + + /// Encodes a `vsrlri.d` instruction (requires lsx). + pub inline fn @"vsrlri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x72a50000, p0, p1, p2); + } + + /// Encodes a `vsrlri.h` instruction (requires lsx). + pub inline fn @"vsrlri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72a44000, p0, p1, p2); + } + + /// Encodes a `vsrlri.w` instruction (requires lsx). + pub inline fn @"vsrlri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72a48000, p0, p1, p2); + } + + /// Encodes a `vsrlrn.b.h` instruction (requires lsx). + pub inline fn @"vsrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f88000, p0, p1, p2); + } + + /// Encodes a `vsrlrn.h.w` instruction (requires lsx). + pub inline fn @"vsrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f90000, p0, p1, p2); + } + + /// Encodes a `vsrlrn.w.d` instruction (requires lsx). + pub inline fn @"vsrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f98000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.b.h` instruction (requires lsx). + pub inline fn @"vsrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73444000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.d.q` instruction (requires lsx). + pub inline fn @"vsrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73460000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.h.w` instruction (requires lsx). + pub inline fn @"vsrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73448000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.w.d` instruction (requires lsx). + pub inline fn @"vsrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73450000, p0, p1, p2); + } + + /// Encodes a `vssran.b.h` instruction (requires lsx). + pub inline fn @"vssran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fe8000, p0, p1, p2); + } + + /// Encodes a `vssran.bu.h` instruction (requires lsx). + pub inline fn @"vssran.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71068000, p0, p1, p2); + } + + /// Encodes a `vssran.h.w` instruction (requires lsx). + pub inline fn @"vssran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ff0000, p0, p1, p2); + } + + /// Encodes a `vssran.hu.w` instruction (requires lsx). + pub inline fn @"vssran.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71070000, p0, p1, p2); + } + + /// Encodes a `vssran.w.d` instruction (requires lsx). + pub inline fn @"vssran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ff8000, p0, p1, p2); + } + + /// Encodes a `vssran.wu.d` instruction (requires lsx). + pub inline fn @"vssran.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71078000, p0, p1, p2); + } + + /// Encodes a `vssrani.b.h` instruction (requires lsx). + pub inline fn @"vssrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73604000, p0, p1, p2); + } + + /// Encodes a `vssrani.bu.h` instruction (requires lsx). + pub inline fn @"vssrani.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73644000, p0, p1, p2); + } + + /// Encodes a `vssrani.d.q` instruction (requires lsx). + pub inline fn @"vssrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73620000, p0, p1, p2); + } + + /// Encodes a `vssrani.du.q` instruction (requires lsx). + pub inline fn @"vssrani.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73660000, p0, p1, p2); + } + + /// Encodes a `vssrani.h.w` instruction (requires lsx). + pub inline fn @"vssrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73608000, p0, p1, p2); + } + + /// Encodes a `vssrani.hu.w` instruction (requires lsx). + pub inline fn @"vssrani.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73648000, p0, p1, p2); + } + + /// Encodes a `vssrani.w.d` instruction (requires lsx). + pub inline fn @"vssrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73610000, p0, p1, p2); + } + + /// Encodes a `vssrani.wu.d` instruction (requires lsx). + pub inline fn @"vssrani.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73650000, p0, p1, p2); + } + + /// Encodes a `vssrarn.b.h` instruction (requires lsx). + pub inline fn @"vssrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71028000, p0, p1, p2); + } + + /// Encodes a `vssrarn.bu.h` instruction (requires lsx). + pub inline fn @"vssrarn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710a8000, p0, p1, p2); + } + + /// Encodes a `vssrarn.h.w` instruction (requires lsx). + pub inline fn @"vssrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71030000, p0, p1, p2); + } + + /// Encodes a `vssrarn.hu.w` instruction (requires lsx). + pub inline fn @"vssrarn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710b0000, p0, p1, p2); + } + + /// Encodes a `vssrarn.w.d` instruction (requires lsx). + pub inline fn @"vssrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71038000, p0, p1, p2); + } + + /// Encodes a `vssrarn.wu.d` instruction (requires lsx). + pub inline fn @"vssrarn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710b8000, p0, p1, p2); + } + + /// Encodes a `vssrarni.b.h` instruction (requires lsx). + pub inline fn @"vssrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73684000, p0, p1, p2); + } + + /// Encodes a `vssrarni.bu.h` instruction (requires lsx). + pub inline fn @"vssrarni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x736c4000, p0, p1, p2); + } + + /// Encodes a `vssrarni.d.q` instruction (requires lsx). + pub inline fn @"vssrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x736a0000, p0, p1, p2); + } + + /// Encodes a `vssrarni.du.q` instruction (requires lsx). + pub inline fn @"vssrarni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x736e0000, p0, p1, p2); + } + + /// Encodes a `vssrarni.h.w` instruction (requires lsx). + pub inline fn @"vssrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73688000, p0, p1, p2); + } + + /// Encodes a `vssrarni.hu.w` instruction (requires lsx). + pub inline fn @"vssrarni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x736c8000, p0, p1, p2); + } + + /// Encodes a `vssrarni.w.d` instruction (requires lsx). + pub inline fn @"vssrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73690000, p0, p1, p2); + } + + /// Encodes a `vssrarni.wu.d` instruction (requires lsx). + pub inline fn @"vssrarni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x736d0000, p0, p1, p2); + } + + /// Encodes a `vssrln.b.h` instruction (requires lsx). + pub inline fn @"vssrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fc8000, p0, p1, p2); + } + + /// Encodes a `vssrln.bu.h` instruction (requires lsx). + pub inline fn @"vssrln.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71048000, p0, p1, p2); + } + + /// Encodes a `vssrln.h.w` instruction (requires lsx). + pub inline fn @"vssrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fd0000, p0, p1, p2); + } + + /// Encodes a `vssrln.hu.w` instruction (requires lsx). + pub inline fn @"vssrln.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71050000, p0, p1, p2); + } + + /// Encodes a `vssrln.w.d` instruction (requires lsx). + pub inline fn @"vssrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fd8000, p0, p1, p2); + } + + /// Encodes a `vssrln.wu.d` instruction (requires lsx). + pub inline fn @"vssrln.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71058000, p0, p1, p2); + } + + /// Encodes a `vssrlni.b.h` instruction (requires lsx). + pub inline fn @"vssrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73484000, p0, p1, p2); + } + + /// Encodes a `vssrlni.bu.h` instruction (requires lsx). + pub inline fn @"vssrlni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x734c4000, p0, p1, p2); + } + + /// Encodes a `vssrlni.d.q` instruction (requires lsx). + pub inline fn @"vssrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x734a0000, p0, p1, p2); + } + + /// Encodes a `vssrlni.du.q` instruction (requires lsx). + pub inline fn @"vssrlni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x734e0000, p0, p1, p2); + } + + /// Encodes a `vssrlni.h.w` instruction (requires lsx). + pub inline fn @"vssrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73488000, p0, p1, p2); + } + + /// Encodes a `vssrlni.hu.w` instruction (requires lsx). + pub inline fn @"vssrlni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x734c8000, p0, p1, p2); + } + + /// Encodes a `vssrlni.w.d` instruction (requires lsx). + pub inline fn @"vssrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73490000, p0, p1, p2); + } + + /// Encodes a `vssrlni.wu.d` instruction (requires lsx). + pub inline fn @"vssrlni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x734d0000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.b.h` instruction (requires lsx). + pub inline fn @"vssrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71008000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.bu.h` instruction (requires lsx). + pub inline fn @"vssrlrn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71088000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.h.w` instruction (requires lsx). + pub inline fn @"vssrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71010000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.hu.w` instruction (requires lsx). + pub inline fn @"vssrlrn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71090000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.w.d` instruction (requires lsx). + pub inline fn @"vssrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71018000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.wu.d` instruction (requires lsx). + pub inline fn @"vssrlrn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71098000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.b.h` instruction (requires lsx). + pub inline fn @"vssrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73504000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.bu.h` instruction (requires lsx). + pub inline fn @"vssrlrni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73544000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.d.q` instruction (requires lsx). + pub inline fn @"vssrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73520000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.du.q` instruction (requires lsx). + pub inline fn @"vssrlrni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73560000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.h.w` instruction (requires lsx). + pub inline fn @"vssrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73508000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.hu.w` instruction (requires lsx). + pub inline fn @"vssrlrni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73548000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.w.d` instruction (requires lsx). + pub inline fn @"vssrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73510000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.wu.d` instruction (requires lsx). + pub inline fn @"vssrlrni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73550000, p0, p1, p2); + } + + /// Encodes a `vssub.b` instruction (requires lsx). + pub inline fn @"vssub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70480000, p0, p1, p2); + } + + /// Encodes a `vssub.bu` instruction (requires lsx). + pub inline fn @"vssub.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704c0000, p0, p1, p2); + } + + /// Encodes a `vssub.d` instruction (requires lsx). + pub inline fn @"vssub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70498000, p0, p1, p2); + } + + /// Encodes a `vssub.du` instruction (requires lsx). + pub inline fn @"vssub.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704d8000, p0, p1, p2); + } + + /// Encodes a `vssub.h` instruction (requires lsx). + pub inline fn @"vssub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70488000, p0, p1, p2); + } + + /// Encodes a `vssub.hu` instruction (requires lsx). + pub inline fn @"vssub.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704c8000, p0, p1, p2); + } + + /// Encodes a `vssub.w` instruction (requires lsx). + pub inline fn @"vssub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70490000, p0, p1, p2); + } + + /// Encodes a `vssub.wu` instruction (requires lsx). + pub inline fn @"vssub.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704d0000, p0, p1, p2); + } + + /// Encodes a `vst` instruction (requires lsx). + pub inline fn vst(p0: Register, p1: Register, p2: i12) Instruction { + return encodeVdJSk12(0x2c400000, p0, p1, p2); + } + + /// Encodes a `vstelm.b` instruction (requires lsx). + pub inline fn @"vstelm.b"(p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return encodeVdJSk8Un4(0x31800000, p0, p1, p2, p3); + } + + /// Encodes a `vstelm.d` instruction (requires lsx). + pub inline fn @"vstelm.d"(p0: Register, p1: Register, p2: i8, p3: u1) Instruction { + return encodeVdJSk8ps3Un1(0x31100000, p0, p1, p2, p3); + } + + /// Encodes a `vstelm.h` instruction (requires lsx). + pub inline fn @"vstelm.h"(p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return encodeVdJSk8ps1Un3(0x31400000, p0, p1, p2, p3); + } + + /// Encodes a `vstelm.w` instruction (requires lsx). + pub inline fn @"vstelm.w"(p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return encodeVdJSk8ps2Un2(0x31200000, p0, p1, p2, p3); + } + + /// Encodes a `vstx` instruction (requires lsx). + pub inline fn vstx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdJK(0x38440000, p0, p1, p2); + } + + /// Encodes a `vsub.b` instruction (requires lsx). + pub inline fn @"vsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700c0000, p0, p1, p2); + } + + /// Encodes a `vsub.d` instruction (requires lsx). + pub inline fn @"vsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700d8000, p0, p1, p2); + } + + /// Encodes a `vsub.h` instruction (requires lsx). + pub inline fn @"vsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700c8000, p0, p1, p2); + } + + /// Encodes a `vsub.q` instruction (requires lsx). + pub inline fn @"vsub.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712d8000, p0, p1, p2); + } + + /// Encodes a `vsub.w` instruction (requires lsx). + pub inline fn @"vsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700d0000, p0, p1, p2); + } + + /// Encodes a `vsubi.bu` instruction (requires lsx). + pub inline fn @"vsubi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728c0000, p0, p1, p2); + } + + /// Encodes a `vsubi.du` instruction (requires lsx). + pub inline fn @"vsubi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728d8000, p0, p1, p2); + } + + /// Encodes a `vsubi.hu` instruction (requires lsx). + pub inline fn @"vsubi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728c8000, p0, p1, p2); + } + + /// Encodes a `vsubi.wu` instruction (requires lsx). + pub inline fn @"vsubi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728d0000, p0, p1, p2); + } + + /// Encodes a `vsubwev.d.w` instruction (requires lsx). + pub inline fn @"vsubwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70210000, p0, p1, p2); + } + + /// Encodes a `vsubwev.d.wu` instruction (requires lsx). + pub inline fn @"vsubwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70310000, p0, p1, p2); + } + + /// Encodes a `vsubwev.h.b` instruction (requires lsx). + pub inline fn @"vsubwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70200000, p0, p1, p2); + } + + /// Encodes a `vsubwev.h.bu` instruction (requires lsx). + pub inline fn @"vsubwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70300000, p0, p1, p2); + } + + /// Encodes a `vsubwev.q.d` instruction (requires lsx). + pub inline fn @"vsubwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70218000, p0, p1, p2); + } + + /// Encodes a `vsubwev.q.du` instruction (requires lsx). + pub inline fn @"vsubwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70318000, p0, p1, p2); + } + + /// Encodes a `vsubwev.w.h` instruction (requires lsx). + pub inline fn @"vsubwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70208000, p0, p1, p2); + } + + /// Encodes a `vsubwev.w.hu` instruction (requires lsx). + pub inline fn @"vsubwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70308000, p0, p1, p2); + } + + /// Encodes a `vsubwod.d.w` instruction (requires lsx). + pub inline fn @"vsubwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70250000, p0, p1, p2); + } + + /// Encodes a `vsubwod.d.wu` instruction (requires lsx). + pub inline fn @"vsubwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70350000, p0, p1, p2); + } + + /// Encodes a `vsubwod.h.b` instruction (requires lsx). + pub inline fn @"vsubwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70240000, p0, p1, p2); + } + + /// Encodes a `vsubwod.h.bu` instruction (requires lsx). + pub inline fn @"vsubwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70340000, p0, p1, p2); + } + + /// Encodes a `vsubwod.q.d` instruction (requires lsx). + pub inline fn @"vsubwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70258000, p0, p1, p2); + } + + /// Encodes a `vsubwod.q.du` instruction (requires lsx). + pub inline fn @"vsubwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70358000, p0, p1, p2); + } + + /// Encodes a `vsubwod.w.h` instruction (requires lsx). + pub inline fn @"vsubwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70248000, p0, p1, p2); + } + + /// Encodes a `vsubwod.w.hu` instruction (requires lsx). + pub inline fn @"vsubwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70348000, p0, p1, p2); + } + + /// Encodes a `vxor.v` instruction (requires lsx). + pub inline fn @"vxor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71270000, p0, p1, p2); + } + + /// Encodes a `vxori.b` instruction (requires lsx). + pub inline fn @"vxori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73d80000, p0, p1, p2); + } + + /// Encodes a `x86adc.b` instruction (requires 64bit). + pub inline fn @"x86adc.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000c, p0, p1); + } + + /// Encodes a `x86adc.d` instruction (requires 64bit). + pub inline fn @"x86adc.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000f, p0, p1); + } + + /// Encodes a `x86adc.h` instruction (requires 64bit). + pub inline fn @"x86adc.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000d, p0, p1); + } + + /// Encodes a `x86adc.w` instruction (requires 64bit). + pub inline fn @"x86adc.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000e, p0, p1); + } + + /// Encodes a `x86add.b` instruction (requires 64bit). + pub inline fn @"x86add.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0004, p0, p1); + } + + /// Encodes a `x86add.d` instruction (requires 64bit). + pub inline fn @"x86add.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0007, p0, p1); + } + + /// Encodes a `x86add.du` instruction (requires 64bit). + pub inline fn @"x86add.du"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0001, p0, p1); + } + + /// Encodes a `x86add.h` instruction (requires 64bit). + pub inline fn @"x86add.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0005, p0, p1); + } + + /// Encodes a `x86add.w` instruction (requires 64bit). + pub inline fn @"x86add.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0006, p0, p1); + } + + /// Encodes a `x86add.wu` instruction (requires 64bit). + pub inline fn @"x86add.wu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0000, p0, p1); + } + + /// Encodes a `x86and.b` instruction (requires 64bit). + pub inline fn @"x86and.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8010, p0, p1); + } + + /// Encodes a `x86and.d` instruction (requires 64bit). + pub inline fn @"x86and.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8013, p0, p1); + } + + /// Encodes a `x86and.h` instruction (requires 64bit). + pub inline fn @"x86and.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8011, p0, p1); + } + + /// Encodes a `x86and.w` instruction (requires 64bit). + pub inline fn @"x86and.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8012, p0, p1); + } + + /// Encodes a `x86clrtm` instruction (requires 64bit). + pub inline fn x86clrtm() Instruction { + return encodeEMPTY(0x00008028); + } + + /// Encodes a `x86dec.b` instruction (requires 64bit). + pub inline fn @"x86dec.b"(p0: Register) Instruction { + return encodeJ(0x00008004, p0); + } + + /// Encodes a `x86dec.d` instruction (requires 64bit). + pub inline fn @"x86dec.d"(p0: Register) Instruction { + return encodeJ(0x00008007, p0); + } + + /// Encodes a `x86dec.h` instruction (requires 64bit). + pub inline fn @"x86dec.h"(p0: Register) Instruction { + return encodeJ(0x00008005, p0); + } + + /// Encodes a `x86dec.w` instruction (requires 64bit). + pub inline fn @"x86dec.w"(p0: Register) Instruction { + return encodeJ(0x00008006, p0); + } + + /// Encodes a `x86dectop` instruction (requires 64bit). + pub inline fn x86dectop() Instruction { + return encodeEMPTY(0x00008029); + } + + /// Encodes a `x86inc.b` instruction (requires 64bit). + pub inline fn @"x86inc.b"(p0: Register) Instruction { + return encodeJ(0x00008000, p0); + } + + /// Encodes a `x86inc.d` instruction (requires 64bit). + pub inline fn @"x86inc.d"(p0: Register) Instruction { + return encodeJ(0x00008003, p0); + } + + /// Encodes a `x86inc.h` instruction (requires 64bit). + pub inline fn @"x86inc.h"(p0: Register) Instruction { + return encodeJ(0x00008001, p0); + } + + /// Encodes a `x86inc.w` instruction (requires 64bit). + pub inline fn @"x86inc.w"(p0: Register) Instruction { + return encodeJ(0x00008002, p0); + } + + /// Encodes a `x86inctop` instruction (requires 64bit). + pub inline fn x86inctop() Instruction { + return encodeEMPTY(0x00008009); + } + + /// Encodes a `x86mfflag` instruction (requires 64bit). + pub inline fn x86mfflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0000, p0, p1); + } + + /// Encodes a `x86mftop` instruction (requires 64bit). + pub inline fn x86mftop(p0: Register) Instruction { + return encodeD(0x00007400, p0); + } + + /// Encodes a `x86mtflag` instruction (requires 64bit). + pub inline fn x86mtflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0020, p0, p1); + } + + /// Encodes a `x86mttop` instruction (requires 64bit). + pub inline fn x86mttop(p0: u3) Instruction { + return encodeUj3(0x00007000, p0); + } + + /// Encodes a `x86mul.b` instruction (requires 64bit). + pub inline fn @"x86mul.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8000, p0, p1); + } + + /// Encodes a `x86mul.bu` instruction (requires 64bit). + pub inline fn @"x86mul.bu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8004, p0, p1); + } + + /// Encodes a `x86mul.d` instruction (requires 64bit). + pub inline fn @"x86mul.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8003, p0, p1); + } + + /// Encodes a `x86mul.du` instruction (requires 64bit). + pub inline fn @"x86mul.du"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8007, p0, p1); + } + + /// Encodes a `x86mul.h` instruction (requires 64bit). + pub inline fn @"x86mul.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8001, p0, p1); + } + + /// Encodes a `x86mul.hu` instruction (requires 64bit). + pub inline fn @"x86mul.hu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8005, p0, p1); + } + + /// Encodes a `x86mul.w` instruction (requires 64bit). + pub inline fn @"x86mul.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8002, p0, p1); + } + + /// Encodes a `x86mul.wu` instruction (requires 64bit). + pub inline fn @"x86mul.wu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8006, p0, p1); + } + + /// Encodes a `x86or.b` instruction (requires 64bit). + pub inline fn @"x86or.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8014, p0, p1); + } + + /// Encodes a `x86or.d` instruction (requires 64bit). + pub inline fn @"x86or.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8017, p0, p1); + } + + /// Encodes a `x86or.h` instruction (requires 64bit). + pub inline fn @"x86or.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8015, p0, p1); + } + + /// Encodes a `x86or.w` instruction (requires 64bit). + pub inline fn @"x86or.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8016, p0, p1); + } + + /// Encodes a `x86rcl.b` instruction (requires 64bit). + pub inline fn @"x86rcl.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800c, p0, p1); + } + + /// Encodes a `x86rcl.d` instruction (requires 64bit). + pub inline fn @"x86rcl.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800f, p0, p1); + } + + /// Encodes a `x86rcl.h` instruction (requires 64bit). + pub inline fn @"x86rcl.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800d, p0, p1); + } + + /// Encodes a `x86rcl.w` instruction (requires 64bit). + pub inline fn @"x86rcl.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800e, p0, p1); + } + + /// Encodes a `x86rcli.b` instruction (requires 64bit). + pub inline fn @"x86rcli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542018, p0, p1); + } + + /// Encodes a `x86rcli.d` instruction (requires 64bit). + pub inline fn @"x86rcli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x0055001b, p0, p1); + } + + /// Encodes a `x86rcli.h` instruction (requires 64bit). + pub inline fn @"x86rcli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544019, p0, p1); + } + + /// Encodes a `x86rcli.w` instruction (requires 64bit). + pub inline fn @"x86rcli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x0054801a, p0, p1); + } + + /// Encodes a `x86rcr.b` instruction (requires 64bit). + pub inline fn @"x86rcr.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8008, p0, p1); + } + + /// Encodes a `x86rcr.d` instruction (requires 64bit). + pub inline fn @"x86rcr.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800b, p0, p1); + } + + /// Encodes a `x86rcr.h` instruction (requires 64bit). + pub inline fn @"x86rcr.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8009, p0, p1); + } + + /// Encodes a `x86rcr.w` instruction (requires 64bit). + pub inline fn @"x86rcr.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800a, p0, p1); + } + + /// Encodes a `x86rcri.b` instruction (requires 64bit). + pub inline fn @"x86rcri.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542010, p0, p1); + } + + /// Encodes a `x86rcri.d` instruction (requires 64bit). + pub inline fn @"x86rcri.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550013, p0, p1); + } + + /// Encodes a `x86rcri.h` instruction (requires 64bit). + pub inline fn @"x86rcri.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544011, p0, p1); + } + + /// Encodes a `x86rcri.w` instruction (requires 64bit). + pub inline fn @"x86rcri.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548012, p0, p1); + } + + /// Encodes a `x86rotl.b` instruction (requires 64bit). + pub inline fn @"x86rotl.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8004, p0, p1); + } + + /// Encodes a `x86rotl.d` instruction (requires 64bit). + pub inline fn @"x86rotl.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8007, p0, p1); + } + + /// Encodes a `x86rotl.h` instruction (requires 64bit). + pub inline fn @"x86rotl.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8005, p0, p1); + } + + /// Encodes a `x86rotl.w` instruction (requires 64bit). + pub inline fn @"x86rotl.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8006, p0, p1); + } + + /// Encodes a `x86rotli.b` instruction (requires 64bit). + pub inline fn @"x86rotli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542014, p0, p1); + } + + /// Encodes a `x86rotli.d` instruction (requires 64bit). + pub inline fn @"x86rotli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550017, p0, p1); + } + + /// Encodes a `x86rotli.h` instruction (requires 64bit). + pub inline fn @"x86rotli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544015, p0, p1); + } + + /// Encodes a `x86rotli.w` instruction (requires 64bit). + pub inline fn @"x86rotli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548016, p0, p1); + } + + /// Encodes a `x86rotr.b` instruction (requires 64bit). + pub inline fn @"x86rotr.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8000, p0, p1); + } + + /// Encodes a `x86rotr.d` instruction (requires 64bit). + pub inline fn @"x86rotr.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8002, p0, p1); + } + + /// Encodes a `x86rotr.h` instruction (requires 64bit). + pub inline fn @"x86rotr.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8001, p0, p1); + } + + /// Encodes a `x86rotr.w` instruction (requires 64bit). + pub inline fn @"x86rotr.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8003, p0, p1); + } + + /// Encodes a `x86rotri.b` instruction (requires 64bit). + pub inline fn @"x86rotri.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x0054200c, p0, p1); + } + + /// Encodes a `x86rotri.d` instruction (requires 64bit). + pub inline fn @"x86rotri.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x0055000f, p0, p1); + } + + /// Encodes a `x86rotri.h` instruction (requires 64bit). + pub inline fn @"x86rotri.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x0054400d, p0, p1); + } + + /// Encodes a `x86rotri.w` instruction (requires 64bit). + pub inline fn @"x86rotri.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x0054800e, p0, p1); + } + + /// Encodes a `x86sbc.b` instruction (requires 64bit). + pub inline fn @"x86sbc.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0010, p0, p1); + } + + /// Encodes a `x86sbc.d` instruction (requires 64bit). + pub inline fn @"x86sbc.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0013, p0, p1); + } + + /// Encodes a `x86sbc.h` instruction (requires 64bit). + pub inline fn @"x86sbc.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0011, p0, p1); + } + + /// Encodes a `x86sbc.w` instruction (requires 64bit). + pub inline fn @"x86sbc.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0012, p0, p1); + } + + /// Encodes a `x86setj` instruction (requires 64bit). + pub inline fn x86setj(p0: Register, p1: u4) Instruction { + return encodeDUk4(0x00368000, p0, p1); + } + + /// Encodes a `x86setloope` instruction (requires 64bit). + pub inline fn x86setloope(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00007800, p0, p1); + } + + /// Encodes a `x86setloopne` instruction (requires 64bit). + pub inline fn x86setloopne(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00007c00, p0, p1); + } + + /// Encodes a `x86settag` instruction (requires 64bit). + pub inline fn x86settag(p0: Register, p1: u5, p2: u8) Instruction { + return encodeDUj5Uk8(0x00580000, p0, p1, p2); + } + + /// Encodes a `x86settm` instruction (requires 64bit). + pub inline fn x86settm() Instruction { + return encodeEMPTY(0x00008008); + } + + /// Encodes a `x86sll.b` instruction (requires 64bit). + pub inline fn @"x86sll.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0014, p0, p1); + } + + /// Encodes a `x86sll.d` instruction (requires 64bit). + pub inline fn @"x86sll.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0017, p0, p1); + } + + /// Encodes a `x86sll.h` instruction (requires 64bit). + pub inline fn @"x86sll.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0015, p0, p1); + } + + /// Encodes a `x86sll.w` instruction (requires 64bit). + pub inline fn @"x86sll.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0016, p0, p1); + } + + /// Encodes a `x86slli.b` instruction (requires 64bit). + pub inline fn @"x86slli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542000, p0, p1); + } + + /// Encodes a `x86slli.d` instruction (requires 64bit). + pub inline fn @"x86slli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550003, p0, p1); + } + + /// Encodes a `x86slli.h` instruction (requires 64bit). + pub inline fn @"x86slli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544001, p0, p1); + } + + /// Encodes a `x86slli.w` instruction (requires 64bit). + pub inline fn @"x86slli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548002, p0, p1); + } + + /// Encodes a `x86sra.b` instruction (requires 64bit). + pub inline fn @"x86sra.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001c, p0, p1); + } + + /// Encodes a `x86sra.d` instruction (requires 64bit). + pub inline fn @"x86sra.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001f, p0, p1); + } + + /// Encodes a `x86sra.h` instruction (requires 64bit). + pub inline fn @"x86sra.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001d, p0, p1); + } + + /// Encodes a `x86sra.w` instruction (requires 64bit). + pub inline fn @"x86sra.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001e, p0, p1); + } + + /// Encodes a `x86srai.b` instruction (requires 64bit). + pub inline fn @"x86srai.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542008, p0, p1); + } + + /// Encodes a `x86srai.d` instruction (requires 64bit). + pub inline fn @"x86srai.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x0055000b, p0, p1); + } + + /// Encodes a `x86srai.h` instruction (requires 64bit). + pub inline fn @"x86srai.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544009, p0, p1); + } + + /// Encodes a `x86srai.w` instruction (requires 64bit). + pub inline fn @"x86srai.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x0054800a, p0, p1); + } + + /// Encodes a `x86srl.b` instruction (requires 64bit). + pub inline fn @"x86srl.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0018, p0, p1); + } + + /// Encodes a `x86srl.d` instruction (requires 64bit). + pub inline fn @"x86srl.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001b, p0, p1); + } + + /// Encodes a `x86srl.h` instruction (requires 64bit). + pub inline fn @"x86srl.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0019, p0, p1); + } + + /// Encodes a `x86srl.w` instruction (requires 64bit). + pub inline fn @"x86srl.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001a, p0, p1); + } + + /// Encodes a `x86srli.b` instruction (requires 64bit). + pub inline fn @"x86srli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542004, p0, p1); + } + + /// Encodes a `x86srli.d` instruction (requires 64bit). + pub inline fn @"x86srli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550007, p0, p1); + } + + /// Encodes a `x86srli.h` instruction (requires 64bit). + pub inline fn @"x86srli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544005, p0, p1); + } + + /// Encodes a `x86srli.w` instruction (requires 64bit). + pub inline fn @"x86srli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548006, p0, p1); + } + + /// Encodes a `x86sub.b` instruction (requires 64bit). + pub inline fn @"x86sub.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0008, p0, p1); + } + + /// Encodes a `x86sub.d` instruction (requires 64bit). + pub inline fn @"x86sub.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000b, p0, p1); + } + + /// Encodes a `x86sub.du` instruction (requires 64bit). + pub inline fn @"x86sub.du"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0003, p0, p1); + } + + /// Encodes a `x86sub.h` instruction (requires 64bit). + pub inline fn @"x86sub.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0009, p0, p1); + } + + /// Encodes a `x86sub.w` instruction (requires 64bit). + pub inline fn @"x86sub.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000a, p0, p1); + } + + /// Encodes a `x86sub.wu` instruction (requires 64bit). + pub inline fn @"x86sub.wu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0002, p0, p1); + } + + /// Encodes a `x86xor.b` instruction (requires 64bit). + pub inline fn @"x86xor.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8018, p0, p1); + } + + /// Encodes a `x86xor.d` instruction (requires 64bit). + pub inline fn @"x86xor.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f801b, p0, p1); + } + + /// Encodes a `x86xor.h` instruction (requires 64bit). + pub inline fn @"x86xor.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8019, p0, p1); + } + + /// Encodes a `x86xor.w` instruction (requires 64bit). + pub inline fn @"x86xor.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f801a, p0, p1); + } + + /// Encodes a `xor` instruction (requires 32bit). + pub inline fn xor(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00158000, p0, p1, p2); + } + + /// Encodes a `xori` instruction (requires 32bit). + pub inline fn xori(p0: Register, p1: Register, p2: u12) Instruction { + return encodeDJUk12(0x03c00000, p0, p1, p2); + } + + /// Encodes a `xvabsd.b` instruction (requires lasx). + pub inline fn @"xvabsd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74600000, p0, p1, p2); + } + + /// Encodes a `xvabsd.bu` instruction (requires lasx). + pub inline fn @"xvabsd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74620000, p0, p1, p2); + } + + /// Encodes a `xvabsd.d` instruction (requires lasx). + pub inline fn @"xvabsd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74618000, p0, p1, p2); + } + + /// Encodes a `xvabsd.du` instruction (requires lasx). + pub inline fn @"xvabsd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74638000, p0, p1, p2); + } + + /// Encodes a `xvabsd.h` instruction (requires lasx). + pub inline fn @"xvabsd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74608000, p0, p1, p2); + } + + /// Encodes a `xvabsd.hu` instruction (requires lasx). + pub inline fn @"xvabsd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74628000, p0, p1, p2); + } + + /// Encodes a `xvabsd.w` instruction (requires lasx). + pub inline fn @"xvabsd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74610000, p0, p1, p2); + } + + /// Encodes a `xvabsd.wu` instruction (requires lasx). + pub inline fn @"xvabsd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74630000, p0, p1, p2); + } + + /// Encodes a `xvadd.b` instruction (requires lasx). + pub inline fn @"xvadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740a0000, p0, p1, p2); + } + + /// Encodes a `xvadd.d` instruction (requires lasx). + pub inline fn @"xvadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740b8000, p0, p1, p2); + } + + /// Encodes a `xvadd.h` instruction (requires lasx). + pub inline fn @"xvadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740a8000, p0, p1, p2); + } + + /// Encodes a `xvadd.q` instruction (requires lasx). + pub inline fn @"xvadd.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752d0000, p0, p1, p2); + } + + /// Encodes a `xvadd.w` instruction (requires lasx). + pub inline fn @"xvadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740b0000, p0, p1, p2); + } + + /// Encodes a `xvadda.b` instruction (requires lasx). + pub inline fn @"xvadda.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745c0000, p0, p1, p2); + } + + /// Encodes a `xvadda.d` instruction (requires lasx). + pub inline fn @"xvadda.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745d8000, p0, p1, p2); + } + + /// Encodes a `xvadda.h` instruction (requires lasx). + pub inline fn @"xvadda.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745c8000, p0, p1, p2); + } + + /// Encodes a `xvadda.w` instruction (requires lasx). + pub inline fn @"xvadda.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745d0000, p0, p1, p2); + } + + /// Encodes a `xvaddi.bu` instruction (requires lasx). + pub inline fn @"xvaddi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768a0000, p0, p1, p2); + } + + /// Encodes a `xvaddi.du` instruction (requires lasx). + pub inline fn @"xvaddi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768b8000, p0, p1, p2); + } + + /// Encodes a `xvaddi.hu` instruction (requires lasx). + pub inline fn @"xvaddi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768a8000, p0, p1, p2); + } + + /// Encodes a `xvaddi.wu` instruction (requires lasx). + pub inline fn @"xvaddi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768b0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.d.w` instruction (requires lasx). + pub inline fn @"xvaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741f0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.d.wu` instruction (requires lasx). + pub inline fn @"xvaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742f0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.d.wu.w` instruction (requires lasx). + pub inline fn @"xvaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743f0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.h.b` instruction (requires lasx). + pub inline fn @"xvaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741e0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.h.bu` instruction (requires lasx). + pub inline fn @"xvaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742e0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.h.bu.b` instruction (requires lasx). + pub inline fn @"xvaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743e0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.q.d` instruction (requires lasx). + pub inline fn @"xvaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741f8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.q.du` instruction (requires lasx). + pub inline fn @"xvaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742f8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.q.du.d` instruction (requires lasx). + pub inline fn @"xvaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743f8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.w.h` instruction (requires lasx). + pub inline fn @"xvaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741e8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.w.hu` instruction (requires lasx). + pub inline fn @"xvaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742e8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.w.hu.h` instruction (requires lasx). + pub inline fn @"xvaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743e8000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.d.w` instruction (requires lasx). + pub inline fn @"xvaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74230000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.d.wu` instruction (requires lasx). + pub inline fn @"xvaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74330000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.d.wu.w` instruction (requires lasx). + pub inline fn @"xvaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74410000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.h.b` instruction (requires lasx). + pub inline fn @"xvaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74220000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.h.bu` instruction (requires lasx). + pub inline fn @"xvaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74320000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.h.bu.b` instruction (requires lasx). + pub inline fn @"xvaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74400000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.q.d` instruction (requires lasx). + pub inline fn @"xvaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74238000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.q.du` instruction (requires lasx). + pub inline fn @"xvaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74338000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.q.du.d` instruction (requires lasx). + pub inline fn @"xvaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74418000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.w.h` instruction (requires lasx). + pub inline fn @"xvaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74228000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.w.hu` instruction (requires lasx). + pub inline fn @"xvaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74328000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.w.hu.h` instruction (requires lasx). + pub inline fn @"xvaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74408000, p0, p1, p2); + } + + /// Encodes a `xvand.v` instruction (requires lasx). + pub inline fn @"xvand.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75260000, p0, p1, p2); + } + + /// Encodes a `xvandi.b` instruction (requires lasx). + pub inline fn @"xvandi.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77d00000, p0, p1, p2); + } + + /// Encodes a `xvandn.v` instruction (requires lasx). + pub inline fn @"xvandn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75280000, p0, p1, p2); + } + + /// Encodes a `xvavg.b` instruction (requires lasx). + pub inline fn @"xvavg.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74640000, p0, p1, p2); + } + + /// Encodes a `xvavg.bu` instruction (requires lasx). + pub inline fn @"xvavg.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74660000, p0, p1, p2); + } + + /// Encodes a `xvavg.d` instruction (requires lasx). + pub inline fn @"xvavg.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74658000, p0, p1, p2); + } + + /// Encodes a `xvavg.du` instruction (requires lasx). + pub inline fn @"xvavg.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74678000, p0, p1, p2); + } + + /// Encodes a `xvavg.h` instruction (requires lasx). + pub inline fn @"xvavg.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74648000, p0, p1, p2); + } + + /// Encodes a `xvavg.hu` instruction (requires lasx). + pub inline fn @"xvavg.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74668000, p0, p1, p2); + } + + /// Encodes a `xvavg.w` instruction (requires lasx). + pub inline fn @"xvavg.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74650000, p0, p1, p2); + } + + /// Encodes a `xvavg.wu` instruction (requires lasx). + pub inline fn @"xvavg.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74670000, p0, p1, p2); + } + + /// Encodes a `xvavgr.b` instruction (requires lasx). + pub inline fn @"xvavgr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74680000, p0, p1, p2); + } + + /// Encodes a `xvavgr.bu` instruction (requires lasx). + pub inline fn @"xvavgr.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746a0000, p0, p1, p2); + } + + /// Encodes a `xvavgr.d` instruction (requires lasx). + pub inline fn @"xvavgr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74698000, p0, p1, p2); + } + + /// Encodes a `xvavgr.du` instruction (requires lasx). + pub inline fn @"xvavgr.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746b8000, p0, p1, p2); + } + + /// Encodes a `xvavgr.h` instruction (requires lasx). + pub inline fn @"xvavgr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74688000, p0, p1, p2); + } + + /// Encodes a `xvavgr.hu` instruction (requires lasx). + pub inline fn @"xvavgr.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746a8000, p0, p1, p2); + } + + /// Encodes a `xvavgr.w` instruction (requires lasx). + pub inline fn @"xvavgr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74690000, p0, p1, p2); + } + + /// Encodes a `xvavgr.wu` instruction (requires lasx). + pub inline fn @"xvavgr.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746b0000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.b` instruction (requires lasx). + pub inline fn @"xvbitclr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750c0000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.d` instruction (requires lasx). + pub inline fn @"xvbitclr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750d8000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.h` instruction (requires lasx). + pub inline fn @"xvbitclr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750c8000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.w` instruction (requires lasx). + pub inline fn @"xvbitclr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750d0000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.b` instruction (requires lasx). + pub inline fn @"xvbitclri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77102000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.d` instruction (requires lasx). + pub inline fn @"xvbitclri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77110000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.h` instruction (requires lasx). + pub inline fn @"xvbitclri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77104000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.w` instruction (requires lasx). + pub inline fn @"xvbitclri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77108000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.b` instruction (requires lasx). + pub inline fn @"xvbitrev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75100000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.d` instruction (requires lasx). + pub inline fn @"xvbitrev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75118000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.h` instruction (requires lasx). + pub inline fn @"xvbitrev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75108000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.w` instruction (requires lasx). + pub inline fn @"xvbitrev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75110000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.b` instruction (requires lasx). + pub inline fn @"xvbitrevi.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77182000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.d` instruction (requires lasx). + pub inline fn @"xvbitrevi.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77190000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.h` instruction (requires lasx). + pub inline fn @"xvbitrevi.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77184000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.w` instruction (requires lasx). + pub inline fn @"xvbitrevi.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77188000, p0, p1, p2); + } + + /// Encodes a `xvbitsel.v` instruction (requires lasx). + pub inline fn @"xvbitsel.v"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0d200000, p0, p1, p2, p3); + } + + /// Encodes a `xvbitseli.b` instruction (requires lasx). + pub inline fn @"xvbitseli.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77c40000, p0, p1, p2); + } + + /// Encodes a `xvbitset.b` instruction (requires lasx). + pub inline fn @"xvbitset.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750e0000, p0, p1, p2); + } + + /// Encodes a `xvbitset.d` instruction (requires lasx). + pub inline fn @"xvbitset.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750f8000, p0, p1, p2); + } + + /// Encodes a `xvbitset.h` instruction (requires lasx). + pub inline fn @"xvbitset.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750e8000, p0, p1, p2); + } + + /// Encodes a `xvbitset.w` instruction (requires lasx). + pub inline fn @"xvbitset.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750f0000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.b` instruction (requires lasx). + pub inline fn @"xvbitseti.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77142000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.d` instruction (requires lasx). + pub inline fn @"xvbitseti.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77150000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.h` instruction (requires lasx). + pub inline fn @"xvbitseti.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77144000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.w` instruction (requires lasx). + pub inline fn @"xvbitseti.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77148000, p0, p1, p2); + } + + /// Encodes a `xvbsll.v` instruction (requires lasx). + pub inline fn @"xvbsll.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768e0000, p0, p1, p2); + } + + /// Encodes a `xvbsrl.v` instruction (requires lasx). + pub inline fn @"xvbsrl.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768e8000, p0, p1, p2); + } + + /// Encodes a `xvclo.b` instruction (requires lasx). + pub inline fn @"xvclo.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0000, p0, p1); + } + + /// Encodes a `xvclo.d` instruction (requires lasx). + pub inline fn @"xvclo.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0c00, p0, p1); + } + + /// Encodes a `xvclo.h` instruction (requires lasx). + pub inline fn @"xvclo.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0400, p0, p1); + } + + /// Encodes a `xvclo.w` instruction (requires lasx). + pub inline fn @"xvclo.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0800, p0, p1); + } + + /// Encodes a `xvclz.b` instruction (requires lasx). + pub inline fn @"xvclz.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1000, p0, p1); + } + + /// Encodes a `xvclz.d` instruction (requires lasx). + pub inline fn @"xvclz.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1c00, p0, p1); + } + + /// Encodes a `xvclz.h` instruction (requires lasx). + pub inline fn @"xvclz.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1400, p0, p1); + } + + /// Encodes a `xvclz.w` instruction (requires lasx). + pub inline fn @"xvclz.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1800, p0, p1); + } + + /// Encodes a `xvdiv.b` instruction (requires lasx). + pub inline fn @"xvdiv.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e00000, p0, p1, p2); + } + + /// Encodes a `xvdiv.bu` instruction (requires lasx). + pub inline fn @"xvdiv.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e40000, p0, p1, p2); + } + + /// Encodes a `xvdiv.d` instruction (requires lasx). + pub inline fn @"xvdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e18000, p0, p1, p2); + } + + /// Encodes a `xvdiv.du` instruction (requires lasx). + pub inline fn @"xvdiv.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e58000, p0, p1, p2); + } + + /// Encodes a `xvdiv.h` instruction (requires lasx). + pub inline fn @"xvdiv.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e08000, p0, p1, p2); + } + + /// Encodes a `xvdiv.hu` instruction (requires lasx). + pub inline fn @"xvdiv.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e48000, p0, p1, p2); + } + + /// Encodes a `xvdiv.w` instruction (requires lasx). + pub inline fn @"xvdiv.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e10000, p0, p1, p2); + } + + /// Encodes a `xvdiv.wu` instruction (requires lasx). + pub inline fn @"xvdiv.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e50000, p0, p1, p2); + } + + /// Encodes a `xvexth.d.w` instruction (requires lasx). + pub inline fn @"xvexth.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ee800, p0, p1); + } + + /// Encodes a `xvexth.du.wu` instruction (requires lasx). + pub inline fn @"xvexth.du.wu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ef800, p0, p1); + } + + /// Encodes a `xvexth.h.b` instruction (requires lasx). + pub inline fn @"xvexth.h.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ee000, p0, p1); + } + + /// Encodes a `xvexth.hu.bu` instruction (requires lasx). + pub inline fn @"xvexth.hu.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ef000, p0, p1); + } + + /// Encodes a `xvexth.q.d` instruction (requires lasx). + pub inline fn @"xvexth.q.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769eec00, p0, p1); + } + + /// Encodes a `xvexth.qu.du` instruction (requires lasx). + pub inline fn @"xvexth.qu.du"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769efc00, p0, p1); + } + + /// Encodes a `xvexth.w.h` instruction (requires lasx). + pub inline fn @"xvexth.w.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ee400, p0, p1); + } + + /// Encodes a `xvexth.wu.hu` instruction (requires lasx). + pub inline fn @"xvexth.wu.hu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ef400, p0, p1); + } + + /// Encodes a `xvextl.q.d` instruction (requires lasx). + pub inline fn @"xvextl.q.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x77090000, p0, p1); + } + + /// Encodes a `xvextl.qu.du` instruction (requires lasx). + pub inline fn @"xvextl.qu.du"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x770d0000, p0, p1); + } + + /// Encodes a `xvextrins.b` instruction (requires lasx). + pub inline fn @"xvextrins.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x778c0000, p0, p1, p2); + } + + /// Encodes a `xvextrins.d` instruction (requires lasx). + pub inline fn @"xvextrins.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77800000, p0, p1, p2); + } + + /// Encodes a `xvextrins.h` instruction (requires lasx). + pub inline fn @"xvextrins.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77880000, p0, p1, p2); + } + + /// Encodes a `xvextrins.w` instruction (requires lasx). + pub inline fn @"xvextrins.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77840000, p0, p1, p2); + } + + /// Encodes a `xvfadd.d` instruction (requires lasx). + pub inline fn @"xvfadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75310000, p0, p1, p2); + } + + /// Encodes a `xvfadd.s` instruction (requires lasx). + pub inline fn @"xvfadd.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75308000, p0, p1, p2); + } + + /// Encodes a `xvfclass.d` instruction (requires lasx). + pub inline fn @"xvfclass.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cd800, p0, p1); + } + + /// Encodes a `xvfclass.s` instruction (requires lasx). + pub inline fn @"xvfclass.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cd400, p0, p1); + } + + /// Encodes a `xvfcmp.caf.d` instruction (requires lasx). + pub inline fn @"xvfcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca00000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.caf.s` instruction (requires lasx). + pub inline fn @"xvfcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c900000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.ceq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca20000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.ceq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c920000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cle.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca30000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cle.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c930000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.clt.d` instruction (requires lasx). + pub inline fn @"xvfcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca10000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.clt.s` instruction (requires lasx). + pub inline fn @"xvfcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c910000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cne.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca80000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cne.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c980000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cor.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0caa0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cor.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9a0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cueq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca60000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cueq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c960000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cule.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca70000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cule.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c970000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cult.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca50000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cult.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c950000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cun.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca40000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cun.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c940000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cune.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0cac0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cune.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9c0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.saf.d` instruction (requires lasx). + pub inline fn @"xvfcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca08000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.saf.s` instruction (requires lasx). + pub inline fn @"xvfcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c908000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.seq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca28000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.seq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c928000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sle.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca38000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sle.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c938000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.slt.d` instruction (requires lasx). + pub inline fn @"xvfcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca18000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.slt.s` instruction (requires lasx). + pub inline fn @"xvfcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c918000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sne.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca88000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sne.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c988000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sor.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0caa8000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sor.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9a8000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sueq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca68000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sueq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c968000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sule.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca78000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sule.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c978000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sult.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca58000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sult.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c958000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sun.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca48000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sun.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c948000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sune.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0cac8000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sune.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9c8000, p0, p1, p2); + } + + /// Encodes a `xvfcvt.h.s` instruction (requires lasx). + pub inline fn @"xvfcvt.h.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75460000, p0, p1, p2); + } + + /// Encodes a `xvfcvt.s.d` instruction (requires lasx). + pub inline fn @"xvfcvt.s.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75468000, p0, p1, p2); + } + + /// Encodes a `xvfcvth.d.s` instruction (requires lasx). + pub inline fn @"xvfcvth.d.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769df400, p0, p1); + } + + /// Encodes a `xvfcvth.s.h` instruction (requires lasx). + pub inline fn @"xvfcvth.s.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769dec00, p0, p1); + } + + /// Encodes a `xvfcvtl.d.s` instruction (requires lasx). + pub inline fn @"xvfcvtl.d.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769df000, p0, p1); + } + + /// Encodes a `xvfcvtl.s.h` instruction (requires lasx). + pub inline fn @"xvfcvtl.s.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769de800, p0, p1); + } + + /// Encodes a `xvfdiv.d` instruction (requires lasx). + pub inline fn @"xvfdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753b0000, p0, p1, p2); + } + + /// Encodes a `xvfdiv.s` instruction (requires lasx). + pub inline fn @"xvfdiv.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753a8000, p0, p1, p2); + } + + /// Encodes a `xvffint.d.l` instruction (requires lasx). + pub inline fn @"xvffint.d.l"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0800, p0, p1); + } + + /// Encodes a `xvffint.d.lu` instruction (requires lasx). + pub inline fn @"xvffint.d.lu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0c00, p0, p1); + } + + /// Encodes a `xvffint.s.l` instruction (requires lasx). + pub inline fn @"xvffint.s.l"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75480000, p0, p1, p2); + } + + /// Encodes a `xvffint.s.w` instruction (requires lasx). + pub inline fn @"xvffint.s.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0000, p0, p1); + } + + /// Encodes a `xvffint.s.wu` instruction (requires lasx). + pub inline fn @"xvffint.s.wu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0400, p0, p1); + } + + /// Encodes a `xvffinth.d.w` instruction (requires lasx). + pub inline fn @"xvffinth.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e1400, p0, p1); + } + + /// Encodes a `xvffintl.d.w` instruction (requires lasx). + pub inline fn @"xvffintl.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e1000, p0, p1); + } + + /// Encodes a `xvflogb.d` instruction (requires lasx). + pub inline fn @"xvflogb.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cc800, p0, p1); + } + + /// Encodes a `xvflogb.s` instruction (requires lasx). + pub inline fn @"xvflogb.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cc400, p0, p1); + } + + /// Encodes a `xvfmadd.d` instruction (requires lasx). + pub inline fn @"xvfmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a200000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmadd.s` instruction (requires lasx). + pub inline fn @"xvfmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a100000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmax.d` instruction (requires lasx). + pub inline fn @"xvfmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753d0000, p0, p1, p2); + } + + /// Encodes a `xvfmax.s` instruction (requires lasx). + pub inline fn @"xvfmax.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753c8000, p0, p1, p2); + } + + /// Encodes a `xvfmaxa.d` instruction (requires lasx). + pub inline fn @"xvfmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75410000, p0, p1, p2); + } + + /// Encodes a `xvfmaxa.s` instruction (requires lasx). + pub inline fn @"xvfmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75408000, p0, p1, p2); + } + + /// Encodes a `xvfmin.d` instruction (requires lasx). + pub inline fn @"xvfmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753f0000, p0, p1, p2); + } + + /// Encodes a `xvfmin.s` instruction (requires lasx). + pub inline fn @"xvfmin.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753e8000, p0, p1, p2); + } + + /// Encodes a `xvfmina.d` instruction (requires lasx). + pub inline fn @"xvfmina.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75430000, p0, p1, p2); + } + + /// Encodes a `xvfmina.s` instruction (requires lasx). + pub inline fn @"xvfmina.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75428000, p0, p1, p2); + } + + /// Encodes a `xvfmsub.d` instruction (requires lasx). + pub inline fn @"xvfmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a600000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmsub.s` instruction (requires lasx). + pub inline fn @"xvfmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a500000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmul.d` instruction (requires lasx). + pub inline fn @"xvfmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75390000, p0, p1, p2); + } + + /// Encodes a `xvfmul.s` instruction (requires lasx). + pub inline fn @"xvfmul.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75388000, p0, p1, p2); + } + + /// Encodes a `xvfnmadd.d` instruction (requires lasx). + pub inline fn @"xvfnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0aa00000, p0, p1, p2, p3); + } + + /// Encodes a `xvfnmadd.s` instruction (requires lasx). + pub inline fn @"xvfnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a900000, p0, p1, p2, p3); + } + + /// Encodes a `xvfnmsub.d` instruction (requires lasx). + pub inline fn @"xvfnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0ae00000, p0, p1, p2, p3); + } + + /// Encodes a `xvfnmsub.s` instruction (requires lasx). + pub inline fn @"xvfnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0ad00000, p0, p1, p2, p3); + } + + /// Encodes a `xvfrecip.d` instruction (requires lasx). + pub inline fn @"xvfrecip.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cf800, p0, p1); + } + + /// Encodes a `xvfrecip.s` instruction (requires lasx). + pub inline fn @"xvfrecip.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cf400, p0, p1); + } + + /// Encodes a `xvfrecipe.d` instruction (requires lasx). + pub inline fn @"xvfrecipe.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d1800, p0, p1); + } + + /// Encodes a `xvfrecipe.s` instruction (requires lasx). + pub inline fn @"xvfrecipe.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d1400, p0, p1); + } + + /// Encodes a `xvfrint.d` instruction (requires lasx). + pub inline fn @"xvfrint.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d3800, p0, p1); + } + + /// Encodes a `xvfrint.s` instruction (requires lasx). + pub inline fn @"xvfrint.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d3400, p0, p1); + } + + /// Encodes a `xvfrintrm.d` instruction (requires lasx). + pub inline fn @"xvfrintrm.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d4800, p0, p1); + } + + /// Encodes a `xvfrintrm.s` instruction (requires lasx). + pub inline fn @"xvfrintrm.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d4400, p0, p1); + } + + /// Encodes a `xvfrintrne.d` instruction (requires lasx). + pub inline fn @"xvfrintrne.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d7800, p0, p1); + } + + /// Encodes a `xvfrintrne.s` instruction (requires lasx). + pub inline fn @"xvfrintrne.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d7400, p0, p1); + } + + /// Encodes a `xvfrintrp.d` instruction (requires lasx). + pub inline fn @"xvfrintrp.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d5800, p0, p1); + } + + /// Encodes a `xvfrintrp.s` instruction (requires lasx). + pub inline fn @"xvfrintrp.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d5400, p0, p1); + } + + /// Encodes a `xvfrintrz.d` instruction (requires lasx). + pub inline fn @"xvfrintrz.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d6800, p0, p1); + } + + /// Encodes a `xvfrintrz.s` instruction (requires lasx). + pub inline fn @"xvfrintrz.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d6400, p0, p1); + } + + /// Encodes a `xvfrsqrt.d` instruction (requires lasx). + pub inline fn @"xvfrsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d0800, p0, p1); + } + + /// Encodes a `xvfrsqrt.s` instruction (requires lasx). + pub inline fn @"xvfrsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d0400, p0, p1); + } + + /// Encodes a `xvfrsqrte.d` instruction (requires lasx). + pub inline fn @"xvfrsqrte.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d2800, p0, p1); + } + + /// Encodes a `xvfrsqrte.s` instruction (requires lasx). + pub inline fn @"xvfrsqrte.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d2400, p0, p1); + } + + /// Encodes a `xvfrstp.b` instruction (requires lasx). + pub inline fn @"xvfrstp.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752b0000, p0, p1, p2); + } + + /// Encodes a `xvfrstp.h` instruction (requires lasx). + pub inline fn @"xvfrstp.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752b8000, p0, p1, p2); + } + + /// Encodes a `xvfrstpi.b` instruction (requires lasx). + pub inline fn @"xvfrstpi.b"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x769a0000, p0, p1, p2); + } + + /// Encodes a `xvfrstpi.h` instruction (requires lasx). + pub inline fn @"xvfrstpi.h"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x769a8000, p0, p1, p2); + } + + /// Encodes a `xvfsqrt.d` instruction (requires lasx). + pub inline fn @"xvfsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ce800, p0, p1); + } + + /// Encodes a `xvfsqrt.s` instruction (requires lasx). + pub inline fn @"xvfsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ce400, p0, p1); + } + + /// Encodes a `xvfsub.d` instruction (requires lasx). + pub inline fn @"xvfsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75330000, p0, p1, p2); + } + + /// Encodes a `xvfsub.s` instruction (requires lasx). + pub inline fn @"xvfsub.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75328000, p0, p1, p2); + } + + /// Encodes a `xvftint.l.d` instruction (requires lasx). + pub inline fn @"xvftint.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3400, p0, p1); + } + + /// Encodes a `xvftint.lu.d` instruction (requires lasx). + pub inline fn @"xvftint.lu.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5c00, p0, p1); + } + + /// Encodes a `xvftint.w.d` instruction (requires lasx). + pub inline fn @"xvftint.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75498000, p0, p1, p2); + } + + /// Encodes a `xvftint.w.s` instruction (requires lasx). + pub inline fn @"xvftint.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3000, p0, p1); + } + + /// Encodes a `xvftint.wu.s` instruction (requires lasx). + pub inline fn @"xvftint.wu.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5800, p0, p1); + } + + /// Encodes a `xvftinth.l.s` instruction (requires lasx). + pub inline fn @"xvftinth.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8400, p0, p1); + } + + /// Encodes a `xvftintl.l.s` instruction (requires lasx). + pub inline fn @"xvftintl.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8000, p0, p1); + } + + /// Encodes a `xvftintrm.l.d` instruction (requires lasx). + pub inline fn @"xvftintrm.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3c00, p0, p1); + } + + /// Encodes a `xvftintrm.w.d` instruction (requires lasx). + pub inline fn @"xvftintrm.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754a0000, p0, p1, p2); + } + + /// Encodes a `xvftintrm.w.s` instruction (requires lasx). + pub inline fn @"xvftintrm.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3800, p0, p1); + } + + /// Encodes a `xvftintrmh.l.s` instruction (requires lasx). + pub inline fn @"xvftintrmh.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8c00, p0, p1); + } + + /// Encodes a `xvftintrml.l.s` instruction (requires lasx). + pub inline fn @"xvftintrml.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8800, p0, p1); + } + + /// Encodes a `xvftintrne.l.d` instruction (requires lasx). + pub inline fn @"xvftintrne.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5400, p0, p1); + } + + /// Encodes a `xvftintrne.w.d` instruction (requires lasx). + pub inline fn @"xvftintrne.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754b8000, p0, p1, p2); + } + + /// Encodes a `xvftintrne.w.s` instruction (requires lasx). + pub inline fn @"xvftintrne.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5000, p0, p1); + } + + /// Encodes a `xvftintrneh.l.s` instruction (requires lasx). + pub inline fn @"xvftintrneh.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ea400, p0, p1); + } + + /// Encodes a `xvftintrnel.l.s` instruction (requires lasx). + pub inline fn @"xvftintrnel.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ea000, p0, p1); + } + + /// Encodes a `xvftintrp.l.d` instruction (requires lasx). + pub inline fn @"xvftintrp.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4400, p0, p1); + } + + /// Encodes a `xvftintrp.w.d` instruction (requires lasx). + pub inline fn @"xvftintrp.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754a8000, p0, p1, p2); + } + + /// Encodes a `xvftintrp.w.s` instruction (requires lasx). + pub inline fn @"xvftintrp.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4000, p0, p1); + } + + /// Encodes a `xvftintrph.l.s` instruction (requires lasx). + pub inline fn @"xvftintrph.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9400, p0, p1); + } + + /// Encodes a `xvftintrpl.l.s` instruction (requires lasx). + pub inline fn @"xvftintrpl.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9000, p0, p1); + } + + /// Encodes a `xvftintrz.l.d` instruction (requires lasx). + pub inline fn @"xvftintrz.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4c00, p0, p1); + } + + /// Encodes a `xvftintrz.lu.d` instruction (requires lasx). + pub inline fn @"xvftintrz.lu.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e7400, p0, p1); + } + + /// Encodes a `xvftintrz.w.d` instruction (requires lasx). + pub inline fn @"xvftintrz.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754b0000, p0, p1, p2); + } + + /// Encodes a `xvftintrz.w.s` instruction (requires lasx). + pub inline fn @"xvftintrz.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4800, p0, p1); + } + + /// Encodes a `xvftintrz.wu.s` instruction (requires lasx). + pub inline fn @"xvftintrz.wu.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e7000, p0, p1); + } + + /// Encodes a `xvftintrzh.l.s` instruction (requires lasx). + pub inline fn @"xvftintrzh.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9c00, p0, p1); + } + + /// Encodes a `xvftintrzl.l.s` instruction (requires lasx). + pub inline fn @"xvftintrzl.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9800, p0, p1); + } + + /// Encodes a `xvhaddw.d.w` instruction (requires lasx). + pub inline fn @"xvhaddw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74550000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.du.wu` instruction (requires lasx). + pub inline fn @"xvhaddw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74590000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.h.b` instruction (requires lasx). + pub inline fn @"xvhaddw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74540000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.hu.bu` instruction (requires lasx). + pub inline fn @"xvhaddw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74580000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.q.d` instruction (requires lasx). + pub inline fn @"xvhaddw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74558000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.qu.du` instruction (requires lasx). + pub inline fn @"xvhaddw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74598000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.w.h` instruction (requires lasx). + pub inline fn @"xvhaddw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74548000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.wu.hu` instruction (requires lasx). + pub inline fn @"xvhaddw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74588000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.d.w` instruction (requires lasx). + pub inline fn @"xvhsubw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74570000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.du.wu` instruction (requires lasx). + pub inline fn @"xvhsubw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745b0000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.h.b` instruction (requires lasx). + pub inline fn @"xvhsubw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74560000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.hu.bu` instruction (requires lasx). + pub inline fn @"xvhsubw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745a0000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.q.d` instruction (requires lasx). + pub inline fn @"xvhsubw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74578000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.qu.du` instruction (requires lasx). + pub inline fn @"xvhsubw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745b8000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.w.h` instruction (requires lasx). + pub inline fn @"xvhsubw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74568000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.wu.hu` instruction (requires lasx). + pub inline fn @"xvhsubw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745a8000, p0, p1, p2); + } + + /// Encodes a `xvilvh.b` instruction (requires lasx). + pub inline fn @"xvilvh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751c0000, p0, p1, p2); + } + + /// Encodes a `xvilvh.d` instruction (requires lasx). + pub inline fn @"xvilvh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751d8000, p0, p1, p2); + } + + /// Encodes a `xvilvh.h` instruction (requires lasx). + pub inline fn @"xvilvh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751c8000, p0, p1, p2); + } + + /// Encodes a `xvilvh.w` instruction (requires lasx). + pub inline fn @"xvilvh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751d0000, p0, p1, p2); + } + + /// Encodes a `xvilvl.b` instruction (requires lasx). + pub inline fn @"xvilvl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751a0000, p0, p1, p2); + } + + /// Encodes a `xvilvl.d` instruction (requires lasx). + pub inline fn @"xvilvl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751b8000, p0, p1, p2); + } + + /// Encodes a `xvilvl.h` instruction (requires lasx). + pub inline fn @"xvilvl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751a8000, p0, p1, p2); + } + + /// Encodes a `xvilvl.w` instruction (requires lasx). + pub inline fn @"xvilvl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751b0000, p0, p1, p2); + } + + /// Encodes a `xvinsgr2vr.d` instruction (requires lasx). + pub inline fn @"xvinsgr2vr.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdJUk2(0x76ebe000, p0, p1, p2); + } + + /// Encodes a `xvinsgr2vr.w` instruction (requires lasx). + pub inline fn @"xvinsgr2vr.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdJUk3(0x76ebc000, p0, p1, p2); + } + + /// Encodes a `xvinsve0.d` instruction (requires lasx). + pub inline fn @"xvinsve0.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdXjUk2(0x76ffe000, p0, p1, p2); + } + + /// Encodes a `xvinsve0.w` instruction (requires lasx). + pub inline fn @"xvinsve0.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76ffc000, p0, p1, p2); + } + + /// Encodes a `xvld` instruction (requires lasx). + pub inline fn xvld(p0: Register, p1: Register, p2: i12) Instruction { + return encodeXdJSk12(0x2c800000, p0, p1, p2); + } + + /// Encodes a `xvldi` instruction (requires lasx). + pub inline fn xvldi(p0: Register, p1: i13) Instruction { + return encodeXdSj13(0x77e00000, p0, p1); + } + + /// Encodes a `xvldrepl.b` instruction (requires lasx). + pub inline fn @"xvldrepl.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeXdJSk12(0x32800000, p0, p1, p2); + } + + /// Encodes a `xvldrepl.d` instruction (requires lasx). + pub inline fn @"xvldrepl.d"(p0: Register, p1: Register, p2: i9) Instruction { + return encodeXdJSk9ps3(0x32100000, p0, p1, p2); + } + + /// Encodes a `xvldrepl.h` instruction (requires lasx). + pub inline fn @"xvldrepl.h"(p0: Register, p1: Register, p2: i11) Instruction { + return encodeXdJSk11ps1(0x32400000, p0, p1, p2); + } + + /// Encodes a `xvldrepl.w` instruction (requires lasx). + pub inline fn @"xvldrepl.w"(p0: Register, p1: Register, p2: i10) Instruction { + return encodeXdJSk10ps2(0x32200000, p0, p1, p2); + } + + /// Encodes a `xvldx` instruction (requires lasx). + pub inline fn xvldx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdJK(0x38480000, p0, p1, p2); + } + + /// Encodes a `xvmadd.b` instruction (requires lasx). + pub inline fn @"xvmadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a80000, p0, p1, p2); + } + + /// Encodes a `xvmadd.d` instruction (requires lasx). + pub inline fn @"xvmadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a98000, p0, p1, p2); + } + + /// Encodes a `xvmadd.h` instruction (requires lasx). + pub inline fn @"xvmadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a88000, p0, p1, p2); + } + + /// Encodes a `xvmadd.w` instruction (requires lasx). + pub inline fn @"xvmadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a90000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.d.w` instruction (requires lasx). + pub inline fn @"xvmaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ad0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.d.wu` instruction (requires lasx). + pub inline fn @"xvmaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b50000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bd0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.h.b` instruction (requires lasx). + pub inline fn @"xvmaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ac0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.h.bu` instruction (requires lasx). + pub inline fn @"xvmaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b40000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bc0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.q.d` instruction (requires lasx). + pub inline fn @"xvmaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ad8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.q.du` instruction (requires lasx). + pub inline fn @"xvmaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b58000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.q.du.d` instruction (requires lasx). + pub inline fn @"xvmaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bd8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.w.h` instruction (requires lasx). + pub inline fn @"xvmaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ac8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.w.hu` instruction (requires lasx). + pub inline fn @"xvmaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b48000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bc8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.d.w` instruction (requires lasx). + pub inline fn @"xvmaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74af0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.d.wu` instruction (requires lasx). + pub inline fn @"xvmaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b70000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bf0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.h.b` instruction (requires lasx). + pub inline fn @"xvmaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ae0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.h.bu` instruction (requires lasx). + pub inline fn @"xvmaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b60000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74be0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.q.d` instruction (requires lasx). + pub inline fn @"xvmaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74af8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.q.du` instruction (requires lasx). + pub inline fn @"xvmaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b78000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.q.du.d` instruction (requires lasx). + pub inline fn @"xvmaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bf8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.w.h` instruction (requires lasx). + pub inline fn @"xvmaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ae8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.w.hu` instruction (requires lasx). + pub inline fn @"xvmaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b68000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74be8000, p0, p1, p2); + } + + /// Encodes a `xvmax.b` instruction (requires lasx). + pub inline fn @"xvmax.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74700000, p0, p1, p2); + } + + /// Encodes a `xvmax.bu` instruction (requires lasx). + pub inline fn @"xvmax.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74740000, p0, p1, p2); + } + + /// Encodes a `xvmax.d` instruction (requires lasx). + pub inline fn @"xvmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74718000, p0, p1, p2); + } + + /// Encodes a `xvmax.du` instruction (requires lasx). + pub inline fn @"xvmax.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74758000, p0, p1, p2); + } + + /// Encodes a `xvmax.h` instruction (requires lasx). + pub inline fn @"xvmax.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74708000, p0, p1, p2); + } + + /// Encodes a `xvmax.hu` instruction (requires lasx). + pub inline fn @"xvmax.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74748000, p0, p1, p2); + } + + /// Encodes a `xvmax.w` instruction (requires lasx). + pub inline fn @"xvmax.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74710000, p0, p1, p2); + } + + /// Encodes a `xvmax.wu` instruction (requires lasx). + pub inline fn @"xvmax.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74750000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.b` instruction (requires lasx). + pub inline fn @"xvmaxi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76900000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.bu` instruction (requires lasx). + pub inline fn @"xvmaxi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76940000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.d` instruction (requires lasx). + pub inline fn @"xvmaxi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76918000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.du` instruction (requires lasx). + pub inline fn @"xvmaxi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76958000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.h` instruction (requires lasx). + pub inline fn @"xvmaxi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76908000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.hu` instruction (requires lasx). + pub inline fn @"xvmaxi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76948000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.w` instruction (requires lasx). + pub inline fn @"xvmaxi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76910000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.wu` instruction (requires lasx). + pub inline fn @"xvmaxi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76950000, p0, p1, p2); + } + + /// Encodes a `xvmepatmsk.v` instruction (requires lasx). + pub inline fn @"xvmepatmsk.v"(p0: Register, p1: u5, p2: u5) Instruction { + return encodeXdUj5Uk5(0x769b8000, p0, p1, p2); + } + + /// Encodes a `xvmin.b` instruction (requires lasx). + pub inline fn @"xvmin.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74720000, p0, p1, p2); + } + + /// Encodes a `xvmin.bu` instruction (requires lasx). + pub inline fn @"xvmin.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74760000, p0, p1, p2); + } + + /// Encodes a `xvmin.d` instruction (requires lasx). + pub inline fn @"xvmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74738000, p0, p1, p2); + } + + /// Encodes a `xvmin.du` instruction (requires lasx). + pub inline fn @"xvmin.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74778000, p0, p1, p2); + } + + /// Encodes a `xvmin.h` instruction (requires lasx). + pub inline fn @"xvmin.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74728000, p0, p1, p2); + } + + /// Encodes a `xvmin.hu` instruction (requires lasx). + pub inline fn @"xvmin.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74768000, p0, p1, p2); + } + + /// Encodes a `xvmin.w` instruction (requires lasx). + pub inline fn @"xvmin.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74730000, p0, p1, p2); + } + + /// Encodes a `xvmin.wu` instruction (requires lasx). + pub inline fn @"xvmin.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74770000, p0, p1, p2); + } + + /// Encodes a `xvmini.b` instruction (requires lasx). + pub inline fn @"xvmini.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76920000, p0, p1, p2); + } + + /// Encodes a `xvmini.bu` instruction (requires lasx). + pub inline fn @"xvmini.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76960000, p0, p1, p2); + } + + /// Encodes a `xvmini.d` instruction (requires lasx). + pub inline fn @"xvmini.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76938000, p0, p1, p2); + } + + /// Encodes a `xvmini.du` instruction (requires lasx). + pub inline fn @"xvmini.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76978000, p0, p1, p2); + } + + /// Encodes a `xvmini.h` instruction (requires lasx). + pub inline fn @"xvmini.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76928000, p0, p1, p2); + } + + /// Encodes a `xvmini.hu` instruction (requires lasx). + pub inline fn @"xvmini.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76968000, p0, p1, p2); + } + + /// Encodes a `xvmini.w` instruction (requires lasx). + pub inline fn @"xvmini.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76930000, p0, p1, p2); + } + + /// Encodes a `xvmini.wu` instruction (requires lasx). + pub inline fn @"xvmini.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76970000, p0, p1, p2); + } + + /// Encodes a `xvmod.b` instruction (requires lasx). + pub inline fn @"xvmod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e20000, p0, p1, p2); + } + + /// Encodes a `xvmod.bu` instruction (requires lasx). + pub inline fn @"xvmod.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e60000, p0, p1, p2); + } + + /// Encodes a `xvmod.d` instruction (requires lasx). + pub inline fn @"xvmod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e38000, p0, p1, p2); + } + + /// Encodes a `xvmod.du` instruction (requires lasx). + pub inline fn @"xvmod.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e78000, p0, p1, p2); + } + + /// Encodes a `xvmod.h` instruction (requires lasx). + pub inline fn @"xvmod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e28000, p0, p1, p2); + } + + /// Encodes a `xvmod.hu` instruction (requires lasx). + pub inline fn @"xvmod.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e68000, p0, p1, p2); + } + + /// Encodes a `xvmod.w` instruction (requires lasx). + pub inline fn @"xvmod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e30000, p0, p1, p2); + } + + /// Encodes a `xvmod.wu` instruction (requires lasx). + pub inline fn @"xvmod.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e70000, p0, p1, p2); + } + + /// Encodes a `xvmskgez.b` instruction (requires lasx). + pub inline fn @"xvmskgez.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c5000, p0, p1); + } + + /// Encodes a `xvmskltz.b` instruction (requires lasx). + pub inline fn @"xvmskltz.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4000, p0, p1); + } + + /// Encodes a `xvmskltz.d` instruction (requires lasx). + pub inline fn @"xvmskltz.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4c00, p0, p1); + } + + /// Encodes a `xvmskltz.h` instruction (requires lasx). + pub inline fn @"xvmskltz.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4400, p0, p1); + } + + /// Encodes a `xvmskltz.w` instruction (requires lasx). + pub inline fn @"xvmskltz.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4800, p0, p1); + } + + /// Encodes a `xvmsknz.b` instruction (requires lasx). + pub inline fn @"xvmsknz.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c6000, p0, p1); + } + + /// Encodes a `xvmsub.b` instruction (requires lasx). + pub inline fn @"xvmsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74aa0000, p0, p1, p2); + } + + /// Encodes a `xvmsub.d` instruction (requires lasx). + pub inline fn @"xvmsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ab8000, p0, p1, p2); + } + + /// Encodes a `xvmsub.h` instruction (requires lasx). + pub inline fn @"xvmsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74aa8000, p0, p1, p2); + } + + /// Encodes a `xvmsub.w` instruction (requires lasx). + pub inline fn @"xvmsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ab0000, p0, p1, p2); + } + + /// Encodes a `xvmuh.b` instruction (requires lasx). + pub inline fn @"xvmuh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74860000, p0, p1, p2); + } + + /// Encodes a `xvmuh.bu` instruction (requires lasx). + pub inline fn @"xvmuh.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74880000, p0, p1, p2); + } + + /// Encodes a `xvmuh.d` instruction (requires lasx). + pub inline fn @"xvmuh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74878000, p0, p1, p2); + } + + /// Encodes a `xvmuh.du` instruction (requires lasx). + pub inline fn @"xvmuh.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74898000, p0, p1, p2); + } + + /// Encodes a `xvmuh.h` instruction (requires lasx). + pub inline fn @"xvmuh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74868000, p0, p1, p2); + } + + /// Encodes a `xvmuh.hu` instruction (requires lasx). + pub inline fn @"xvmuh.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74888000, p0, p1, p2); + } + + /// Encodes a `xvmuh.w` instruction (requires lasx). + pub inline fn @"xvmuh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74870000, p0, p1, p2); + } + + /// Encodes a `xvmuh.wu` instruction (requires lasx). + pub inline fn @"xvmuh.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74890000, p0, p1, p2); + } + + /// Encodes a `xvmul.b` instruction (requires lasx). + pub inline fn @"xvmul.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74840000, p0, p1, p2); + } + + /// Encodes a `xvmul.d` instruction (requires lasx). + pub inline fn @"xvmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74858000, p0, p1, p2); + } + + /// Encodes a `xvmul.h` instruction (requires lasx). + pub inline fn @"xvmul.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74848000, p0, p1, p2); + } + + /// Encodes a `xvmul.w` instruction (requires lasx). + pub inline fn @"xvmul.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74850000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.d.w` instruction (requires lasx). + pub inline fn @"xvmulwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74910000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.d.wu` instruction (requires lasx). + pub inline fn @"xvmulwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74990000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmulwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a10000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.h.b` instruction (requires lasx). + pub inline fn @"xvmulwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74900000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.h.bu` instruction (requires lasx). + pub inline fn @"xvmulwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74980000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmulwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a00000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.q.d` instruction (requires lasx). + pub inline fn @"xvmulwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74918000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.q.du` instruction (requires lasx). + pub inline fn @"xvmulwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74998000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.q.du.d` instruction (requires lasx). + pub inline fn @"xvmulwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a18000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.w.h` instruction (requires lasx). + pub inline fn @"xvmulwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74908000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.w.hu` instruction (requires lasx). + pub inline fn @"xvmulwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74988000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmulwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a08000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.d.w` instruction (requires lasx). + pub inline fn @"xvmulwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74930000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.d.wu` instruction (requires lasx). + pub inline fn @"xvmulwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749b0000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmulwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a30000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.h.b` instruction (requires lasx). + pub inline fn @"xvmulwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74920000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.h.bu` instruction (requires lasx). + pub inline fn @"xvmulwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749a0000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmulwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a20000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.q.d` instruction (requires lasx). + pub inline fn @"xvmulwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74938000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.q.du` instruction (requires lasx). + pub inline fn @"xvmulwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749b8000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.q.du.d` instruction (requires lasx). + pub inline fn @"xvmulwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a38000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.w.h` instruction (requires lasx). + pub inline fn @"xvmulwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74928000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.w.hu` instruction (requires lasx). + pub inline fn @"xvmulwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749a8000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmulwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a28000, p0, p1, p2); + } + + /// Encodes a `xvneg.b` instruction (requires lasx). + pub inline fn @"xvneg.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3000, p0, p1); + } + + /// Encodes a `xvneg.d` instruction (requires lasx). + pub inline fn @"xvneg.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3c00, p0, p1); + } + + /// Encodes a `xvneg.h` instruction (requires lasx). + pub inline fn @"xvneg.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3400, p0, p1); + } + + /// Encodes a `xvneg.w` instruction (requires lasx). + pub inline fn @"xvneg.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3800, p0, p1); + } + + /// Encodes a `xvnor.v` instruction (requires lasx). + pub inline fn @"xvnor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75278000, p0, p1, p2); + } + + /// Encodes a `xvnori.b` instruction (requires lasx). + pub inline fn @"xvnori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77dc0000, p0, p1, p2); + } + + /// Encodes a `xvor.v` instruction (requires lasx). + pub inline fn @"xvor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75268000, p0, p1, p2); + } + + /// Encodes a `xvori.b` instruction (requires lasx). + pub inline fn @"xvori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77d40000, p0, p1, p2); + } + + /// Encodes a `xvorn.v` instruction (requires lasx). + pub inline fn @"xvorn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75288000, p0, p1, p2); + } + + /// Encodes a `xvpackev.b` instruction (requires lasx). + pub inline fn @"xvpackev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75160000, p0, p1, p2); + } + + /// Encodes a `xvpackev.d` instruction (requires lasx). + pub inline fn @"xvpackev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75178000, p0, p1, p2); + } + + /// Encodes a `xvpackev.h` instruction (requires lasx). + pub inline fn @"xvpackev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75168000, p0, p1, p2); + } + + /// Encodes a `xvpackev.w` instruction (requires lasx). + pub inline fn @"xvpackev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75170000, p0, p1, p2); + } + + /// Encodes a `xvpackod.b` instruction (requires lasx). + pub inline fn @"xvpackod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75180000, p0, p1, p2); + } + + /// Encodes a `xvpackod.d` instruction (requires lasx). + pub inline fn @"xvpackod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75198000, p0, p1, p2); + } + + /// Encodes a `xvpackod.h` instruction (requires lasx). + pub inline fn @"xvpackod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75188000, p0, p1, p2); + } + + /// Encodes a `xvpackod.w` instruction (requires lasx). + pub inline fn @"xvpackod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75190000, p0, p1, p2); + } + + /// Encodes a `xvpcnt.b` instruction (requires lasx). + pub inline fn @"xvpcnt.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2000, p0, p1); + } + + /// Encodes a `xvpcnt.d` instruction (requires lasx). + pub inline fn @"xvpcnt.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2c00, p0, p1); + } + + /// Encodes a `xvpcnt.h` instruction (requires lasx). + pub inline fn @"xvpcnt.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2400, p0, p1); + } + + /// Encodes a `xvpcnt.w` instruction (requires lasx). + pub inline fn @"xvpcnt.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2800, p0, p1); + } + + /// Encodes a `xvperm.w` instruction (requires lasx). + pub inline fn @"xvperm.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757d0000, p0, p1, p2); + } + + /// Encodes a `xvpermi.d` instruction (requires lasx). + pub inline fn @"xvpermi.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77e80000, p0, p1, p2); + } + + /// Encodes a `xvpermi.q` instruction (requires lasx). + pub inline fn @"xvpermi.q"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77ec0000, p0, p1, p2); + } + + /// Encodes a `xvpermi.w` instruction (requires lasx). + pub inline fn @"xvpermi.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77e40000, p0, p1, p2); + } + + /// Encodes a `xvpickev.b` instruction (requires lasx). + pub inline fn @"xvpickev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751e0000, p0, p1, p2); + } + + /// Encodes a `xvpickev.d` instruction (requires lasx). + pub inline fn @"xvpickev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751f8000, p0, p1, p2); + } + + /// Encodes a `xvpickev.h` instruction (requires lasx). + pub inline fn @"xvpickev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751e8000, p0, p1, p2); + } + + /// Encodes a `xvpickev.w` instruction (requires lasx). + pub inline fn @"xvpickev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751f0000, p0, p1, p2); + } + + /// Encodes a `xvpickod.b` instruction (requires lasx). + pub inline fn @"xvpickod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75200000, p0, p1, p2); + } + + /// Encodes a `xvpickod.d` instruction (requires lasx). + pub inline fn @"xvpickod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75218000, p0, p1, p2); + } + + /// Encodes a `xvpickod.h` instruction (requires lasx). + pub inline fn @"xvpickod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75208000, p0, p1, p2); + } + + /// Encodes a `xvpickod.w` instruction (requires lasx). + pub inline fn @"xvpickod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75210000, p0, p1, p2); + } + + /// Encodes a `xvpickve.d` instruction (requires lasx). + pub inline fn @"xvpickve.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdXjUk2(0x7703e000, p0, p1, p2); + } + + /// Encodes a `xvpickve.w` instruction (requires lasx). + pub inline fn @"xvpickve.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x7703c000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.d` instruction (requires lasx). + pub inline fn @"xvpickve2gr.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDXjUk2(0x76efe000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.du` instruction (requires lasx). + pub inline fn @"xvpickve2gr.du"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDXjUk2(0x76f3e000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.w` instruction (requires lasx). + pub inline fn @"xvpickve2gr.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDXjUk3(0x76efc000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.wu` instruction (requires lasx). + pub inline fn @"xvpickve2gr.wu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDXjUk3(0x76f3c000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.b` instruction (requires lasx). + pub inline fn @"xvrepl128vei.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76f78000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.d` instruction (requires lasx). + pub inline fn @"xvrepl128vei.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeXdXjUk1(0x76f7f000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.h` instruction (requires lasx). + pub inline fn @"xvrepl128vei.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76f7c000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.w` instruction (requires lasx). + pub inline fn @"xvrepl128vei.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdXjUk2(0x76f7e000, p0, p1, p2); + } + + /// Encodes a `xvreplgr2vr.b` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.b"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0000, p0, p1); + } + + /// Encodes a `xvreplgr2vr.d` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.d"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0c00, p0, p1); + } + + /// Encodes a `xvreplgr2vr.h` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.h"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0400, p0, p1); + } + + /// Encodes a `xvreplgr2vr.w` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.w"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0800, p0, p1); + } + + /// Encodes a `xvreplve.b` instruction (requires lasx). + pub inline fn @"xvreplve.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75220000, p0, p1, p2); + } + + /// Encodes a `xvreplve.d` instruction (requires lasx). + pub inline fn @"xvreplve.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75238000, p0, p1, p2); + } + + /// Encodes a `xvreplve.h` instruction (requires lasx). + pub inline fn @"xvreplve.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75228000, p0, p1, p2); + } + + /// Encodes a `xvreplve.w` instruction (requires lasx). + pub inline fn @"xvreplve.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75230000, p0, p1, p2); + } + + /// Encodes a `xvreplve0.b` instruction (requires lasx). + pub inline fn @"xvreplve0.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x77070000, p0, p1); + } + + /// Encodes a `xvreplve0.d` instruction (requires lasx). + pub inline fn @"xvreplve0.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x7707e000, p0, p1); + } + + /// Encodes a `xvreplve0.h` instruction (requires lasx). + pub inline fn @"xvreplve0.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x77078000, p0, p1); + } + + /// Encodes a `xvreplve0.q` instruction (requires lasx). + pub inline fn @"xvreplve0.q"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x7707f000, p0, p1); + } + + /// Encodes a `xvreplve0.w` instruction (requires lasx). + pub inline fn @"xvreplve0.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x7707c000, p0, p1); + } + + /// Encodes a `xvrotr.b` instruction (requires lasx). + pub inline fn @"xvrotr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ee0000, p0, p1, p2); + } + + /// Encodes a `xvrotr.d` instruction (requires lasx). + pub inline fn @"xvrotr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ef8000, p0, p1, p2); + } + + /// Encodes a `xvrotr.h` instruction (requires lasx). + pub inline fn @"xvrotr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ee8000, p0, p1, p2); + } + + /// Encodes a `xvrotr.w` instruction (requires lasx). + pub inline fn @"xvrotr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ef0000, p0, p1, p2); + } + + /// Encodes a `xvrotri.b` instruction (requires lasx). + pub inline fn @"xvrotri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76a02000, p0, p1, p2); + } + + /// Encodes a `xvrotri.d` instruction (requires lasx). + pub inline fn @"xvrotri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x76a10000, p0, p1, p2); + } + + /// Encodes a `xvrotri.h` instruction (requires lasx). + pub inline fn @"xvrotri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76a04000, p0, p1, p2); + } + + /// Encodes a `xvrotri.w` instruction (requires lasx). + pub inline fn @"xvrotri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76a08000, p0, p1, p2); + } + + /// Encodes a `xvsadd.b` instruction (requires lasx). + pub inline fn @"xvsadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74460000, p0, p1, p2); + } + + /// Encodes a `xvsadd.bu` instruction (requires lasx). + pub inline fn @"xvsadd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744a0000, p0, p1, p2); + } + + /// Encodes a `xvsadd.d` instruction (requires lasx). + pub inline fn @"xvsadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74478000, p0, p1, p2); + } + + /// Encodes a `xvsadd.du` instruction (requires lasx). + pub inline fn @"xvsadd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744b8000, p0, p1, p2); + } + + /// Encodes a `xvsadd.h` instruction (requires lasx). + pub inline fn @"xvsadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74468000, p0, p1, p2); + } + + /// Encodes a `xvsadd.hu` instruction (requires lasx). + pub inline fn @"xvsadd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744a8000, p0, p1, p2); + } + + /// Encodes a `xvsadd.w` instruction (requires lasx). + pub inline fn @"xvsadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74470000, p0, p1, p2); + } + + /// Encodes a `xvsadd.wu` instruction (requires lasx). + pub inline fn @"xvsadd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744b0000, p0, p1, p2); + } + + /// Encodes a `xvsat.b` instruction (requires lasx). + pub inline fn @"xvsat.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77242000, p0, p1, p2); + } + + /// Encodes a `xvsat.bu` instruction (requires lasx). + pub inline fn @"xvsat.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77282000, p0, p1, p2); + } + + /// Encodes a `xvsat.d` instruction (requires lasx). + pub inline fn @"xvsat.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77250000, p0, p1, p2); + } + + /// Encodes a `xvsat.du` instruction (requires lasx). + pub inline fn @"xvsat.du"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77290000, p0, p1, p2); + } + + /// Encodes a `xvsat.h` instruction (requires lasx). + pub inline fn @"xvsat.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77244000, p0, p1, p2); + } + + /// Encodes a `xvsat.hu` instruction (requires lasx). + pub inline fn @"xvsat.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77284000, p0, p1, p2); + } + + /// Encodes a `xvsat.w` instruction (requires lasx). + pub inline fn @"xvsat.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77248000, p0, p1, p2); + } + + /// Encodes a `xvsat.wu` instruction (requires lasx). + pub inline fn @"xvsat.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77288000, p0, p1, p2); + } + + /// Encodes a `xvseq.b` instruction (requires lasx). + pub inline fn @"xvseq.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74000000, p0, p1, p2); + } + + /// Encodes a `xvseq.d` instruction (requires lasx). + pub inline fn @"xvseq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74018000, p0, p1, p2); + } + + /// Encodes a `xvseq.h` instruction (requires lasx). + pub inline fn @"xvseq.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74008000, p0, p1, p2); + } + + /// Encodes a `xvseq.w` instruction (requires lasx). + pub inline fn @"xvseq.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74010000, p0, p1, p2); + } + + /// Encodes a `xvseqi.b` instruction (requires lasx). + pub inline fn @"xvseqi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76800000, p0, p1, p2); + } + + /// Encodes a `xvseqi.d` instruction (requires lasx). + pub inline fn @"xvseqi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76818000, p0, p1, p2); + } + + /// Encodes a `xvseqi.h` instruction (requires lasx). + pub inline fn @"xvseqi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76808000, p0, p1, p2); + } + + /// Encodes a `xvseqi.w` instruction (requires lasx). + pub inline fn @"xvseqi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76810000, p0, p1, p2); + } + + /// Encodes a `xvsetallnez.b` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.b"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cb000, p0, p1); + } + + /// Encodes a `xvsetallnez.d` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.d"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cbc00, p0, p1); + } + + /// Encodes a `xvsetallnez.h` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.h"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cb400, p0, p1); + } + + /// Encodes a `xvsetallnez.w` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.w"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cb800, p0, p1); + } + + /// Encodes a `xvsetanyeqz.b` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.b"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769ca000, p0, p1); + } + + /// Encodes a `xvsetanyeqz.d` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.d"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cac00, p0, p1); + } + + /// Encodes a `xvsetanyeqz.h` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.h"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769ca400, p0, p1); + } + + /// Encodes a `xvsetanyeqz.w` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.w"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769ca800, p0, p1); + } + + /// Encodes a `xvseteqz.v` instruction (requires f & lasx). + pub inline fn @"xvseteqz.v"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769c9800, p0, p1); + } + + /// Encodes a `xvsetnez.v` instruction (requires f & lasx). + pub inline fn @"xvsetnez.v"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769c9c00, p0, p1); + } + + /// Encodes a `xvshuf.b` instruction (requires lasx). + pub inline fn @"xvshuf.b"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0d600000, p0, p1, p2, p3); + } + + /// Encodes a `xvshuf.d` instruction (requires lasx). + pub inline fn @"xvshuf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757b8000, p0, p1, p2); + } + + /// Encodes a `xvshuf.h` instruction (requires lasx). + pub inline fn @"xvshuf.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757a8000, p0, p1, p2); + } + + /// Encodes a `xvshuf.w` instruction (requires lasx). + pub inline fn @"xvshuf.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757b0000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.b` instruction (requires lasx). + pub inline fn @"xvshuf4i.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77900000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.d` instruction (requires lasx). + pub inline fn @"xvshuf4i.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x779c0000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.h` instruction (requires lasx). + pub inline fn @"xvshuf4i.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77940000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.w` instruction (requires lasx). + pub inline fn @"xvshuf4i.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77980000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.b` instruction (requires lasx). + pub inline fn @"xvsigncov.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752e0000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.d` instruction (requires lasx). + pub inline fn @"xvsigncov.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752f8000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.h` instruction (requires lasx). + pub inline fn @"xvsigncov.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752e8000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.w` instruction (requires lasx). + pub inline fn @"xvsigncov.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752f0000, p0, p1, p2); + } + + /// Encodes a `xvsle.b` instruction (requires lasx). + pub inline fn @"xvsle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74020000, p0, p1, p2); + } + + /// Encodes a `xvsle.bu` instruction (requires lasx). + pub inline fn @"xvsle.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74040000, p0, p1, p2); + } + + /// Encodes a `xvsle.d` instruction (requires lasx). + pub inline fn @"xvsle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74038000, p0, p1, p2); + } + + /// Encodes a `xvsle.du` instruction (requires lasx). + pub inline fn @"xvsle.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74058000, p0, p1, p2); + } + + /// Encodes a `xvsle.h` instruction (requires lasx). + pub inline fn @"xvsle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74028000, p0, p1, p2); + } + + /// Encodes a `xvsle.hu` instruction (requires lasx). + pub inline fn @"xvsle.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74048000, p0, p1, p2); + } + + /// Encodes a `xvsle.w` instruction (requires lasx). + pub inline fn @"xvsle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74030000, p0, p1, p2); + } + + /// Encodes a `xvsle.wu` instruction (requires lasx). + pub inline fn @"xvsle.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74050000, p0, p1, p2); + } + + /// Encodes a `xvslei.b` instruction (requires lasx). + pub inline fn @"xvslei.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76820000, p0, p1, p2); + } + + /// Encodes a `xvslei.bu` instruction (requires lasx). + pub inline fn @"xvslei.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76840000, p0, p1, p2); + } + + /// Encodes a `xvslei.d` instruction (requires lasx). + pub inline fn @"xvslei.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76838000, p0, p1, p2); + } + + /// Encodes a `xvslei.du` instruction (requires lasx). + pub inline fn @"xvslei.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76858000, p0, p1, p2); + } + + /// Encodes a `xvslei.h` instruction (requires lasx). + pub inline fn @"xvslei.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76828000, p0, p1, p2); + } + + /// Encodes a `xvslei.hu` instruction (requires lasx). + pub inline fn @"xvslei.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76848000, p0, p1, p2); + } + + /// Encodes a `xvslei.w` instruction (requires lasx). + pub inline fn @"xvslei.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76830000, p0, p1, p2); + } + + /// Encodes a `xvslei.wu` instruction (requires lasx). + pub inline fn @"xvslei.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76850000, p0, p1, p2); + } + + /// Encodes a `xvsll.b` instruction (requires lasx). + pub inline fn @"xvsll.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e80000, p0, p1, p2); + } + + /// Encodes a `xvsll.d` instruction (requires lasx). + pub inline fn @"xvsll.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e98000, p0, p1, p2); + } + + /// Encodes a `xvsll.h` instruction (requires lasx). + pub inline fn @"xvsll.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e88000, p0, p1, p2); + } + + /// Encodes a `xvsll.w` instruction (requires lasx). + pub inline fn @"xvsll.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e90000, p0, p1, p2); + } + + /// Encodes a `xvslli.b` instruction (requires lasx). + pub inline fn @"xvslli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x772c2000, p0, p1, p2); + } + + /// Encodes a `xvslli.d` instruction (requires lasx). + pub inline fn @"xvslli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x772d0000, p0, p1, p2); + } + + /// Encodes a `xvslli.h` instruction (requires lasx). + pub inline fn @"xvslli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x772c4000, p0, p1, p2); + } + + /// Encodes a `xvslli.w` instruction (requires lasx). + pub inline fn @"xvslli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x772c8000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.d.w` instruction (requires lasx). + pub inline fn @"xvsllwil.d.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77088000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.du.wu` instruction (requires lasx). + pub inline fn @"xvsllwil.du.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x770c8000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.h.b` instruction (requires lasx). + pub inline fn @"xvsllwil.h.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77082000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.hu.bu` instruction (requires lasx). + pub inline fn @"xvsllwil.hu.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x770c2000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.w.h` instruction (requires lasx). + pub inline fn @"xvsllwil.w.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77084000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.wu.hu` instruction (requires lasx). + pub inline fn @"xvsllwil.wu.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x770c4000, p0, p1, p2); + } + + /// Encodes a `xvslt.b` instruction (requires lasx). + pub inline fn @"xvslt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74060000, p0, p1, p2); + } + + /// Encodes a `xvslt.bu` instruction (requires lasx). + pub inline fn @"xvslt.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74080000, p0, p1, p2); + } + + /// Encodes a `xvslt.d` instruction (requires lasx). + pub inline fn @"xvslt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74078000, p0, p1, p2); + } + + /// Encodes a `xvslt.du` instruction (requires lasx). + pub inline fn @"xvslt.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74098000, p0, p1, p2); + } + + /// Encodes a `xvslt.h` instruction (requires lasx). + pub inline fn @"xvslt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74068000, p0, p1, p2); + } + + /// Encodes a `xvslt.hu` instruction (requires lasx). + pub inline fn @"xvslt.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74088000, p0, p1, p2); + } + + /// Encodes a `xvslt.w` instruction (requires lasx). + pub inline fn @"xvslt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74070000, p0, p1, p2); + } + + /// Encodes a `xvslt.wu` instruction (requires lasx). + pub inline fn @"xvslt.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74090000, p0, p1, p2); + } + + /// Encodes a `xvslti.b` instruction (requires lasx). + pub inline fn @"xvslti.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76860000, p0, p1, p2); + } + + /// Encodes a `xvslti.bu` instruction (requires lasx). + pub inline fn @"xvslti.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76880000, p0, p1, p2); + } + + /// Encodes a `xvslti.d` instruction (requires lasx). + pub inline fn @"xvslti.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76878000, p0, p1, p2); + } + + /// Encodes a `xvslti.du` instruction (requires lasx). + pub inline fn @"xvslti.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76898000, p0, p1, p2); + } + + /// Encodes a `xvslti.h` instruction (requires lasx). + pub inline fn @"xvslti.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76868000, p0, p1, p2); + } + + /// Encodes a `xvslti.hu` instruction (requires lasx). + pub inline fn @"xvslti.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76888000, p0, p1, p2); + } + + /// Encodes a `xvslti.w` instruction (requires lasx). + pub inline fn @"xvslti.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76870000, p0, p1, p2); + } + + /// Encodes a `xvslti.wu` instruction (requires lasx). + pub inline fn @"xvslti.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76890000, p0, p1, p2); + } + + /// Encodes a `xvsra.b` instruction (requires lasx). + pub inline fn @"xvsra.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ec0000, p0, p1, p2); + } + + /// Encodes a `xvsra.d` instruction (requires lasx). + pub inline fn @"xvsra.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ed8000, p0, p1, p2); + } + + /// Encodes a `xvsra.h` instruction (requires lasx). + pub inline fn @"xvsra.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ec8000, p0, p1, p2); + } + + /// Encodes a `xvsra.w` instruction (requires lasx). + pub inline fn @"xvsra.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ed0000, p0, p1, p2); + } + + /// Encodes a `xvsrai.b` instruction (requires lasx). + pub inline fn @"xvsrai.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77342000, p0, p1, p2); + } + + /// Encodes a `xvsrai.d` instruction (requires lasx). + pub inline fn @"xvsrai.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77350000, p0, p1, p2); + } + + /// Encodes a `xvsrai.h` instruction (requires lasx). + pub inline fn @"xvsrai.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77344000, p0, p1, p2); + } + + /// Encodes a `xvsrai.w` instruction (requires lasx). + pub inline fn @"xvsrai.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77348000, p0, p1, p2); + } + + /// Encodes a `xvsran.b.h` instruction (requires lasx). + pub inline fn @"xvsran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f68000, p0, p1, p2); + } + + /// Encodes a `xvsran.h.w` instruction (requires lasx). + pub inline fn @"xvsran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f70000, p0, p1, p2); + } + + /// Encodes a `xvsran.w.d` instruction (requires lasx). + pub inline fn @"xvsran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f78000, p0, p1, p2); + } + + /// Encodes a `xvsrani.b.h` instruction (requires lasx). + pub inline fn @"xvsrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77584000, p0, p1, p2); + } + + /// Encodes a `xvsrani.d.q` instruction (requires lasx). + pub inline fn @"xvsrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x775a0000, p0, p1, p2); + } + + /// Encodes a `xvsrani.h.w` instruction (requires lasx). + pub inline fn @"xvsrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77588000, p0, p1, p2); + } + + /// Encodes a `xvsrani.w.d` instruction (requires lasx). + pub inline fn @"xvsrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77590000, p0, p1, p2); + } + + /// Encodes a `xvsrar.b` instruction (requires lasx). + pub inline fn @"xvsrar.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f20000, p0, p1, p2); + } + + /// Encodes a `xvsrar.d` instruction (requires lasx). + pub inline fn @"xvsrar.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f38000, p0, p1, p2); + } + + /// Encodes a `xvsrar.h` instruction (requires lasx). + pub inline fn @"xvsrar.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f28000, p0, p1, p2); + } + + /// Encodes a `xvsrar.w` instruction (requires lasx). + pub inline fn @"xvsrar.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f30000, p0, p1, p2); + } + + /// Encodes a `xvsrari.b` instruction (requires lasx). + pub inline fn @"xvsrari.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76a82000, p0, p1, p2); + } + + /// Encodes a `xvsrari.d` instruction (requires lasx). + pub inline fn @"xvsrari.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x76a90000, p0, p1, p2); + } + + /// Encodes a `xvsrari.h` instruction (requires lasx). + pub inline fn @"xvsrari.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76a84000, p0, p1, p2); + } + + /// Encodes a `xvsrari.w` instruction (requires lasx). + pub inline fn @"xvsrari.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76a88000, p0, p1, p2); + } + + /// Encodes a `xvsrarn.b.h` instruction (requires lasx). + pub inline fn @"xvsrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fa8000, p0, p1, p2); + } + + /// Encodes a `xvsrarn.h.w` instruction (requires lasx). + pub inline fn @"xvsrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fb0000, p0, p1, p2); + } + + /// Encodes a `xvsrarn.w.d` instruction (requires lasx). + pub inline fn @"xvsrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fb8000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.b.h` instruction (requires lasx). + pub inline fn @"xvsrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x775c4000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.d.q` instruction (requires lasx). + pub inline fn @"xvsrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x775e0000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.h.w` instruction (requires lasx). + pub inline fn @"xvsrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x775c8000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.w.d` instruction (requires lasx). + pub inline fn @"xvsrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x775d0000, p0, p1, p2); + } + + /// Encodes a `xvsrl.b` instruction (requires lasx). + pub inline fn @"xvsrl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ea0000, p0, p1, p2); + } + + /// Encodes a `xvsrl.d` instruction (requires lasx). + pub inline fn @"xvsrl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74eb8000, p0, p1, p2); + } + + /// Encodes a `xvsrl.h` instruction (requires lasx). + pub inline fn @"xvsrl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ea8000, p0, p1, p2); + } + + /// Encodes a `xvsrl.w` instruction (requires lasx). + pub inline fn @"xvsrl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74eb0000, p0, p1, p2); + } + + /// Encodes a `xvsrli.b` instruction (requires lasx). + pub inline fn @"xvsrli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77302000, p0, p1, p2); + } + + /// Encodes a `xvsrli.d` instruction (requires lasx). + pub inline fn @"xvsrli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77310000, p0, p1, p2); + } + + /// Encodes a `xvsrli.h` instruction (requires lasx). + pub inline fn @"xvsrli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77304000, p0, p1, p2); + } + + /// Encodes a `xvsrli.w` instruction (requires lasx). + pub inline fn @"xvsrli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77308000, p0, p1, p2); + } + + /// Encodes a `xvsrln.b.h` instruction (requires lasx). + pub inline fn @"xvsrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f48000, p0, p1, p2); + } + + /// Encodes a `xvsrln.h.w` instruction (requires lasx). + pub inline fn @"xvsrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f50000, p0, p1, p2); + } + + /// Encodes a `xvsrln.w.d` instruction (requires lasx). + pub inline fn @"xvsrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f58000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.b.h` instruction (requires lasx). + pub inline fn @"xvsrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77404000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.d.q` instruction (requires lasx). + pub inline fn @"xvsrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77420000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.h.w` instruction (requires lasx). + pub inline fn @"xvsrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77408000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.w.d` instruction (requires lasx). + pub inline fn @"xvsrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77410000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.b` instruction (requires lasx). + pub inline fn @"xvsrlr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f00000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.d` instruction (requires lasx). + pub inline fn @"xvsrlr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f18000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.h` instruction (requires lasx). + pub inline fn @"xvsrlr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f08000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.w` instruction (requires lasx). + pub inline fn @"xvsrlr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f10000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.b` instruction (requires lasx). + pub inline fn @"xvsrlri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76a42000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.d` instruction (requires lasx). + pub inline fn @"xvsrlri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x76a50000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.h` instruction (requires lasx). + pub inline fn @"xvsrlri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76a44000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.w` instruction (requires lasx). + pub inline fn @"xvsrlri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76a48000, p0, p1, p2); + } + + /// Encodes a `xvsrlrn.b.h` instruction (requires lasx). + pub inline fn @"xvsrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f88000, p0, p1, p2); + } + + /// Encodes a `xvsrlrn.h.w` instruction (requires lasx). + pub inline fn @"xvsrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f90000, p0, p1, p2); + } + + /// Encodes a `xvsrlrn.w.d` instruction (requires lasx). + pub inline fn @"xvsrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f98000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.b.h` instruction (requires lasx). + pub inline fn @"xvsrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77444000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.d.q` instruction (requires lasx). + pub inline fn @"xvsrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77460000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.h.w` instruction (requires lasx). + pub inline fn @"xvsrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77448000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.w.d` instruction (requires lasx). + pub inline fn @"xvsrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77450000, p0, p1, p2); + } + + /// Encodes a `xvssran.b.h` instruction (requires lasx). + pub inline fn @"xvssran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fe8000, p0, p1, p2); + } + + /// Encodes a `xvssran.bu.h` instruction (requires lasx). + pub inline fn @"xvssran.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75068000, p0, p1, p2); + } + + /// Encodes a `xvssran.h.w` instruction (requires lasx). + pub inline fn @"xvssran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ff0000, p0, p1, p2); + } + + /// Encodes a `xvssran.hu.w` instruction (requires lasx). + pub inline fn @"xvssran.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75070000, p0, p1, p2); + } + + /// Encodes a `xvssran.w.d` instruction (requires lasx). + pub inline fn @"xvssran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ff8000, p0, p1, p2); + } + + /// Encodes a `xvssran.wu.d` instruction (requires lasx). + pub inline fn @"xvssran.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75078000, p0, p1, p2); + } + + /// Encodes a `xvssrani.b.h` instruction (requires lasx). + pub inline fn @"xvssrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77604000, p0, p1, p2); + } + + /// Encodes a `xvssrani.bu.h` instruction (requires lasx). + pub inline fn @"xvssrani.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77644000, p0, p1, p2); + } + + /// Encodes a `xvssrani.d.q` instruction (requires lasx). + pub inline fn @"xvssrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77620000, p0, p1, p2); + } + + /// Encodes a `xvssrani.du.q` instruction (requires lasx). + pub inline fn @"xvssrani.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77660000, p0, p1, p2); + } + + /// Encodes a `xvssrani.h.w` instruction (requires lasx). + pub inline fn @"xvssrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77608000, p0, p1, p2); + } + + /// Encodes a `xvssrani.hu.w` instruction (requires lasx). + pub inline fn @"xvssrani.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77648000, p0, p1, p2); + } + + /// Encodes a `xvssrani.w.d` instruction (requires lasx). + pub inline fn @"xvssrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77610000, p0, p1, p2); + } + + /// Encodes a `xvssrani.wu.d` instruction (requires lasx). + pub inline fn @"xvssrani.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77650000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.b.h` instruction (requires lasx). + pub inline fn @"xvssrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75028000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.bu.h` instruction (requires lasx). + pub inline fn @"xvssrarn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750a8000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.h.w` instruction (requires lasx). + pub inline fn @"xvssrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75030000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.hu.w` instruction (requires lasx). + pub inline fn @"xvssrarn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750b0000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.w.d` instruction (requires lasx). + pub inline fn @"xvssrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75038000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.wu.d` instruction (requires lasx). + pub inline fn @"xvssrarn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750b8000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.b.h` instruction (requires lasx). + pub inline fn @"xvssrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77684000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.bu.h` instruction (requires lasx). + pub inline fn @"xvssrarni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x776c4000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.d.q` instruction (requires lasx). + pub inline fn @"xvssrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x776a0000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.du.q` instruction (requires lasx). + pub inline fn @"xvssrarni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x776e0000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.h.w` instruction (requires lasx). + pub inline fn @"xvssrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77688000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.hu.w` instruction (requires lasx). + pub inline fn @"xvssrarni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x776c8000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.w.d` instruction (requires lasx). + pub inline fn @"xvssrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77690000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.wu.d` instruction (requires lasx). + pub inline fn @"xvssrarni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x776d0000, p0, p1, p2); + } + + /// Encodes a `xvssrln.b.h` instruction (requires lasx). + pub inline fn @"xvssrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fc8000, p0, p1, p2); + } + + /// Encodes a `xvssrln.bu.h` instruction (requires lasx). + pub inline fn @"xvssrln.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75048000, p0, p1, p2); + } + + /// Encodes a `xvssrln.h.w` instruction (requires lasx). + pub inline fn @"xvssrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fd0000, p0, p1, p2); + } + + /// Encodes a `xvssrln.hu.w` instruction (requires lasx). + pub inline fn @"xvssrln.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75050000, p0, p1, p2); + } + + /// Encodes a `xvssrln.w.d` instruction (requires lasx). + pub inline fn @"xvssrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fd8000, p0, p1, p2); + } + + /// Encodes a `xvssrln.wu.d` instruction (requires lasx). + pub inline fn @"xvssrln.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75058000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.b.h` instruction (requires lasx). + pub inline fn @"xvssrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77484000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.bu.h` instruction (requires lasx). + pub inline fn @"xvssrlni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x774c4000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.d.q` instruction (requires lasx). + pub inline fn @"xvssrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x774a0000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.du.q` instruction (requires lasx). + pub inline fn @"xvssrlni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x774e0000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.h.w` instruction (requires lasx). + pub inline fn @"xvssrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77488000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.hu.w` instruction (requires lasx). + pub inline fn @"xvssrlni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x774c8000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.w.d` instruction (requires lasx). + pub inline fn @"xvssrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77490000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.wu.d` instruction (requires lasx). + pub inline fn @"xvssrlni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x774d0000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.b.h` instruction (requires lasx). + pub inline fn @"xvssrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75008000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.bu.h` instruction (requires lasx). + pub inline fn @"xvssrlrn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75088000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.h.w` instruction (requires lasx). + pub inline fn @"xvssrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75010000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.hu.w` instruction (requires lasx). + pub inline fn @"xvssrlrn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75090000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.w.d` instruction (requires lasx). + pub inline fn @"xvssrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75018000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.wu.d` instruction (requires lasx). + pub inline fn @"xvssrlrn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75098000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.b.h` instruction (requires lasx). + pub inline fn @"xvssrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77504000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.bu.h` instruction (requires lasx). + pub inline fn @"xvssrlrni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77544000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.d.q` instruction (requires lasx). + pub inline fn @"xvssrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77520000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.du.q` instruction (requires lasx). + pub inline fn @"xvssrlrni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77560000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.h.w` instruction (requires lasx). + pub inline fn @"xvssrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77508000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.hu.w` instruction (requires lasx). + pub inline fn @"xvssrlrni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77548000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.w.d` instruction (requires lasx). + pub inline fn @"xvssrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77510000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.wu.d` instruction (requires lasx). + pub inline fn @"xvssrlrni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77550000, p0, p1, p2); + } + + /// Encodes a `xvssub.b` instruction (requires lasx). + pub inline fn @"xvssub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74480000, p0, p1, p2); + } + + /// Encodes a `xvssub.bu` instruction (requires lasx). + pub inline fn @"xvssub.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744c0000, p0, p1, p2); + } + + /// Encodes a `xvssub.d` instruction (requires lasx). + pub inline fn @"xvssub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74498000, p0, p1, p2); + } + + /// Encodes a `xvssub.du` instruction (requires lasx). + pub inline fn @"xvssub.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744d8000, p0, p1, p2); + } + + /// Encodes a `xvssub.h` instruction (requires lasx). + pub inline fn @"xvssub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74488000, p0, p1, p2); + } + + /// Encodes a `xvssub.hu` instruction (requires lasx). + pub inline fn @"xvssub.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744c8000, p0, p1, p2); + } + + /// Encodes a `xvssub.w` instruction (requires lasx). + pub inline fn @"xvssub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74490000, p0, p1, p2); + } + + /// Encodes a `xvssub.wu` instruction (requires lasx). + pub inline fn @"xvssub.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744d0000, p0, p1, p2); + } + + /// Encodes a `xvst` instruction (requires lasx). + pub inline fn xvst(p0: Register, p1: Register, p2: i12) Instruction { + return encodeXdJSk12(0x2cc00000, p0, p1, p2); + } + + /// Encodes a `xvstelm.b` instruction (requires lasx). + pub inline fn @"xvstelm.b"(p0: Register, p1: Register, p2: i8, p3: u5) Instruction { + return encodeXdJSk8Un5(0x33800000, p0, p1, p2, p3); + } + + /// Encodes a `xvstelm.d` instruction (requires lasx). + pub inline fn @"xvstelm.d"(p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return encodeXdJSk8ps3Un2(0x33100000, p0, p1, p2, p3); + } + + /// Encodes a `xvstelm.h` instruction (requires lasx). + pub inline fn @"xvstelm.h"(p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return encodeXdJSk8ps1Un4(0x33400000, p0, p1, p2, p3); + } + + /// Encodes a `xvstelm.w` instruction (requires lasx). + pub inline fn @"xvstelm.w"(p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return encodeXdJSk8ps2Un3(0x33200000, p0, p1, p2, p3); + } + + /// Encodes a `xvstx` instruction (requires lasx). + pub inline fn xvstx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdJK(0x384c0000, p0, p1, p2); + } + + /// Encodes a `xvsub.b` instruction (requires lasx). + pub inline fn @"xvsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740c0000, p0, p1, p2); + } + + /// Encodes a `xvsub.d` instruction (requires lasx). + pub inline fn @"xvsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740d8000, p0, p1, p2); + } + + /// Encodes a `xvsub.h` instruction (requires lasx). + pub inline fn @"xvsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740c8000, p0, p1, p2); + } + + /// Encodes a `xvsub.q` instruction (requires lasx). + pub inline fn @"xvsub.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752d8000, p0, p1, p2); + } + + /// Encodes a `xvsub.w` instruction (requires lasx). + pub inline fn @"xvsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740d0000, p0, p1, p2); + } + + /// Encodes a `xvsubi.bu` instruction (requires lasx). + pub inline fn @"xvsubi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768c0000, p0, p1, p2); + } + + /// Encodes a `xvsubi.du` instruction (requires lasx). + pub inline fn @"xvsubi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768d8000, p0, p1, p2); + } + + /// Encodes a `xvsubi.hu` instruction (requires lasx). + pub inline fn @"xvsubi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768c8000, p0, p1, p2); + } + + /// Encodes a `xvsubi.wu` instruction (requires lasx). + pub inline fn @"xvsubi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768d0000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.d.w` instruction (requires lasx). + pub inline fn @"xvsubwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74210000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.d.wu` instruction (requires lasx). + pub inline fn @"xvsubwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74310000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.h.b` instruction (requires lasx). + pub inline fn @"xvsubwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74200000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.h.bu` instruction (requires lasx). + pub inline fn @"xvsubwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74300000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.q.d` instruction (requires lasx). + pub inline fn @"xvsubwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74218000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.q.du` instruction (requires lasx). + pub inline fn @"xvsubwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74318000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.w.h` instruction (requires lasx). + pub inline fn @"xvsubwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74208000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.w.hu` instruction (requires lasx). + pub inline fn @"xvsubwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74308000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.d.w` instruction (requires lasx). + pub inline fn @"xvsubwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74250000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.d.wu` instruction (requires lasx). + pub inline fn @"xvsubwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74350000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.h.b` instruction (requires lasx). + pub inline fn @"xvsubwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74240000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.h.bu` instruction (requires lasx). + pub inline fn @"xvsubwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74340000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.q.d` instruction (requires lasx). + pub inline fn @"xvsubwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74258000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.q.du` instruction (requires lasx). + pub inline fn @"xvsubwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74358000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.w.h` instruction (requires lasx). + pub inline fn @"xvsubwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74248000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.w.hu` instruction (requires lasx). + pub inline fn @"xvsubwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74348000, p0, p1, p2); + } + + /// Encodes a `xvxor.v` instruction (requires lasx). + pub inline fn @"xvxor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75270000, p0, p1, p2); + } + + /// Encodes a `xvxori.b` instruction (requires lasx). + pub inline fn @"xvxori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77d80000, p0, p1, p2); + } + + /// Encodes a `xxx.unknown.1` instruction (requires 64bit). + pub inline fn @"xxx.unknown.1"() Instruction { + return encodeEMPTY(0x06493000); + } +}; diff --git a/src/codegen/loongarch/inst_formats.zon b/src/codegen/loongarch/inst_formats.zon new file mode 100644 index 0000000000000000000000000000000000000000..78ba4dd6ad38c6fc7b800082fd3f91230f7c3f7b --- /dev/null +++ b/src/codegen/loongarch/inst_formats.zon @@ -0,0 +1,11059 @@ +// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. +.{ + .instructions = .{ + .@"adc.b" = .{ + .word = 0x00300000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"adc.d" = .{ + .word = 0x00318000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"adc.h" = .{ + .word = 0x00308000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"adc.w" = .{ + .word = 0x00310000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"add.d" = .{ + .word = 0x00108000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"add.w" = .{ + .word = 0x00100000, + .format = .DJK, + .features = .{.@"32bit"}, + }, + .@"addi.d" = .{ + .word = 0x02c00000, + .format = .DJSk12, + .features = .{.@"64bit"}, + }, + .@"addi.w" = .{ + .word = 0x02800000, + .format = .DJSk12, + .features = .{.@"32bit"}, + }, + .@"addu12i.d" = .{ + .word = 0x00298000, + .format = .DJSk5, + .features = .{.@"64bit"}, + }, + .@"addu12i.w" = .{ + .word = 0x00290000, + .format = .DJSk5, + .features = .{.@"64bit"}, + }, + .@"addu16i.d" = .{ + .word = 0x10000000, + .format = .DJSk16, + .features = .{.@"64bit"}, + }, + .@"amadd.b" = .{ + .word = 0x385d0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd.d" = .{ + .word = 0x38618000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd.h" = .{ + .word = 0x385d8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd.w" = .{ + .word = 0x38610000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.b" = .{ + .word = 0x385f0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.d" = .{ + .word = 0x386a8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.h" = .{ + .word = 0x385f8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.w" = .{ + .word = 0x386a0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand.d" = .{ + .word = 0x38628000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand.w" = .{ + .word = 0x38620000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand_db.d" = .{ + .word = 0x386b8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand_db.w" = .{ + .word = 0x386b0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.b" = .{ + .word = 0x38580000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.d" = .{ + .word = 0x38598000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.h" = .{ + .word = 0x38588000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.w" = .{ + .word = 0x38590000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.b" = .{ + .word = 0x385a0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.d" = .{ + .word = 0x385b8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.h" = .{ + .word = 0x385a8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.w" = .{ + .word = 0x385b0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.d" = .{ + .word = 0x38658000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.du" = .{ + .word = 0x38678000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.w" = .{ + .word = 0x38650000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.wu" = .{ + .word = 0x38670000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.d" = .{ + .word = 0x386e8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.du" = .{ + .word = 0x38708000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.w" = .{ + .word = 0x386e0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.wu" = .{ + .word = 0x38700000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.d" = .{ + .word = 0x38668000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.du" = .{ + .word = 0x38688000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.w" = .{ + .word = 0x38660000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.wu" = .{ + .word = 0x38680000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.d" = .{ + .word = 0x386f8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.du" = .{ + .word = 0x38718000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.w" = .{ + .word = 0x386f0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.wu" = .{ + .word = 0x38710000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor.d" = .{ + .word = 0x38638000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor.w" = .{ + .word = 0x38630000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor_db.d" = .{ + .word = 0x386c8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor_db.w" = .{ + .word = 0x386c0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.b" = .{ + .word = 0x385c0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.d" = .{ + .word = 0x38608000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.h" = .{ + .word = 0x385c8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.w" = .{ + .word = 0x38600000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.b" = .{ + .word = 0x385e0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.d" = .{ + .word = 0x38698000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.h" = .{ + .word = 0x385e8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.w" = .{ + .word = 0x38690000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor.d" = .{ + .word = 0x38648000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor.w" = .{ + .word = 0x38640000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor_db.d" = .{ + .word = 0x386d8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor_db.w" = .{ + .word = 0x386d0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"and" = .{ + .word = 0x00148000, + .format = .DJK, + .features = .{.@"32bit"}, + }, + .andi = .{ + .word = 0x03400000, + .format = .DJUk12, + .features = .{.@"32bit"}, + }, + .andn = .{ + .word = 0x00168000, + .format = .DJK, + .features = .{.@"32bit"}, + }, + .@"armadc.w" = .{ + .word = 0x00380010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armadd.w" = .{ + .word = 0x00370010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armand.w" = .{ + .word = 0x00390010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .armmfflag = .{ + .word = 0x005c0040, + .format = .DUk8, + .features = .{.@"64bit"}, + }, + .@"armmov.d" = .{ + .word = 0x003fc01e, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .@"armmov.w" = .{ + .word = 0x003fc01d, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .armmove = .{ + .word = 0x00364000, + .format = .DJUk4, + .features = .{.@"64bit"}, + }, + .armmtflag = .{ + .word = 0x005c0060, + .format = .DUk8, + .features = .{.@"64bit"}, + }, + .@"armnot.w" = .{ + .word = 0x003fc01c, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .@"armor.w" = .{ + .word = 0x00398010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armrotr.w" = .{ + .word = 0x003c0010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armrotri.w" = .{ + .word = 0x003e0010, + .format = .JUd4Uk5, + .orig_format = .JUk5Ud4, + .features = .{.@"64bit"}, + }, + .@"armrrx.w" = .{ + .word = 0x003fc01f, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .@"armsbc.w" = .{ + .word = 0x00388010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .armsetj = .{ + .word = 0x0036c000, + .format = .DUk4, + .orig_name = "setarmj", + .features = .{.@"64bit"}, + }, + .@"armsll.w" = .{ + .word = 0x003a8010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armslli.w" = .{ + .word = 0x003c8010, + .format = .JUd4Uk5, + .orig_format = .JUk5Ud4, + .features = .{.@"64bit"}, + }, + .@"armsra.w" = .{ + .word = 0x003b8010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armsrai.w" = .{ + .word = 0x003d8010, + .format = .JUd4Uk5, + .orig_format = .JUk5Ud4, + .features = .{.@"64bit"}, + }, + .@"armsrl.w" = .{ + .word = 0x003b0010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armsrli.w" = .{ + .word = 0x003d0010, + .format = .JUd4Uk5, + .orig_format = .JUk5Ud4, + .features = .{.@"64bit"}, + }, + .@"armsub.w" = .{ + .word = 0x00378010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armxor.w" = .{ + .word = 0x003a0010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .asrtgt = .{ + .word = 0x00018000, + .format = .JK, + .orig_name = "asrtgt.d", + .features = .{.@"64bit"}, + }, + .asrtle = .{ + .word = 0x00010000, + .format = .JK, + .orig_name = "asrtle.d", + .features = .{.@"64bit"}, + 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.lasx } }, + } }, + .CjSd5k16 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .fcc } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .CjSd5k16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .fcc } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .D = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + } }, + .DCj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .fcc } }, + } }, + .DFj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + } }, + .DJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .DJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .DJKUa2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 15, .length = 2, .signedness = .unsigned } }, + } }, + .DJKUa2pp1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 15, .length = 2, .signedness = .unsigned, .post_proc = .{ .add = 1 } } }, + } }, + .DJKUa3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 15, .length = 3, .signedness = .unsigned } }, + } }, + .DJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .DJSk14 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .signed } }, + } }, + .DJSk14ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .DJSk16 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .DJSk16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .DJSk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } }, + } }, + .DJUk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .unsigned } }, + } }, + .DJUk14 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .unsigned } }, + } }, + .DJUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .DJUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .DJUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .DJUk5Um5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 16, .length = 5, .signedness = .unsigned } }, + } }, + .DJUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .DJUk6Um6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + .{ .imm = .{ .location = 16, .length = 6, .signedness = .unsigned } }, + } }, + .DJUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .DJUm5Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 16, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .DJUm6Uk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 16, .length = 6, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .DKJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .DSj20 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 5, .length = 20, .signedness = .signed } }, + } }, + .DTj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lbt_scratch } }, + } }, + .DUj5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + } }, + .DUj5Uk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .DUk14 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .unsigned } }, + } }, + .DUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .DUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .DVjUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .DVjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .DVjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .DVjUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .DXjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .DXjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .EMPTY = .{ .slots = .{} }, + .FdCj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fcc } }, + } }, + .FdFj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + } }, + .FdFjFk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + } }, + .FdFjFkCa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + .{ .reg = .{ .location = 15, .class = .fcc } }, + } }, + .FdFjFkFa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + .{ .reg = .{ .location = 15, .class = .fp } }, + } }, + .FdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .FdJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .FdJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .J = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .JDSk16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .JK = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .JKUd4 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } }, + } }, + .JKUd5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + } }, + .JSd5k16 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .JSd5k16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .JUd4Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .JUd5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + } }, + .JUd5Sk12 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .JUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .JUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .JUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .JUk5Ud4 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } }, + } }, + .JUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .JUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .Sd10k16 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 10, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .Sd10k16ps2 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 10, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .Sd5k16 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .Sd5k16ps2 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .TdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lbt_scratch } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .Ud15 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 15, .signedness = .unsigned } }, + } }, + .Ud5JK = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .Ud5JSk12 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .Uj3 = .{ .slots = .{ + .{ .imm = .{ .location = 5, .length = 3, .signedness = .unsigned } }, + } }, + .VdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .VdJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .VdJSk10 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed } }, + } }, + .VdJSk10ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .VdJSk11 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed } }, + } }, + .VdJSk11ps1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + } }, + .VdJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .VdJSk8Un1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 1, .signedness = .unsigned } }, + } }, + .VdJSk8Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .VdJSk8Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .VdJSk8Un4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } }, + } }, + .VdJSk8ps1Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .VdJSk8ps2Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .VdJSk8ps3Un1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + .{ .imm = .{ .location = 18, .length = 1, .signedness = .unsigned } }, + } }, + .VdJSk9 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed } }, + } }, + .VdJSk9ps3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + } }, + .VdJUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .VdJUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .VdJUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .VdJUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .VdSj13 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .imm = .{ .location = 5, .length = 13, .signedness = .signed } }, + } }, + .VdUj5Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .VdVj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + } }, + .VdVjK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .VdVjSk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } }, + } }, + .VdVjUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .VdVjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .VdVjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .VdVjUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .VdVjUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .VdVjUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .VdVjUk7 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 7, .signedness = .unsigned } }, + } }, + .VdVjUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .VdVjVk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .reg = .{ .location = 10, .class = .lsx } }, + } }, + .VdVjVkVa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .reg = .{ .location = 10, .class = .lsx } }, + .{ .reg = .{ .location = 15, .class = .lsx } }, + } }, + .XdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .XdJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .XdJSk10 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed } }, + } }, + .XdJSk10ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .XdJSk11 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed } }, + } }, + .XdJSk11ps1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + } }, + .XdJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .XdJSk8Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .XdJSk8Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .XdJSk8Un4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } }, + } }, + .XdJSk8Un5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 5, .signedness = .unsigned } }, + } }, + .XdJSk8ps1Un4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } }, + } }, + .XdJSk8ps2Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .XdJSk8ps3Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .XdJSk9 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed } }, + } }, + .XdJSk9ps3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + } }, + .XdJUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .XdJUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .XdSj13 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .imm = .{ .location = 5, .length = 13, .signedness = .signed } }, + } }, + .XdUj5Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .XdXj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + } }, + .XdXjK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .XdXjSk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } }, + } }, + .XdXjUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .XdXjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .XdXjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .XdXjUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .XdXjUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .XdXjUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .XdXjUk7 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 7, .signedness = .unsigned } }, + } }, + .XdXjUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .XdXjXk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .reg = .{ .location = 10, .class = .lasx } }, + } }, + .XdXjXkXa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .reg = .{ .location = 10, .class = .lasx } }, + .{ .reg = .{ .location = 15, .class = .lasx } }, + } }, + }, +} -- 2.54.0 From 054f867dc0fa3867f2ff951ca26afd92202c0718 Mon Sep 17 00:00:00 2001 From: xtex Date: Fri, 7 Aug 2026 15:09:19 +0800 Subject: [PATCH 3/5] dev: add loongarch-linux dev env --- src/dev.zig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/dev.zig b/src/dev.zig index 47acafc9ce5ba1e279b32624b0190b891792d8c1..1de9810eb00f5e754fea549b3f0f9fa3d5484d8f 100644 --- a/src/dev.zig +++ b/src/dev.zig @@ -56,6 +56,10 @@ pub const Env = enum { /// - `zig build-* -fincremental -fno-llvm -fno-lld -target x86_64-windows --listen=-` @"x86_64-windows", + /// - sema + /// - `zig build-* -fincremental -fno-llvm -fno-lld -target loongarch(32/64)-linux --listen=-` + @"loongarch-linux", + pub inline fn supports(comptime dev_env: Env, comptime feature: Feature) bool { return switch (dev_env) { .full => true, @@ -97,6 +101,7 @@ pub const Env = enum { .riscv64_backend, .sparc64_backend, .spirv_backend, + .loongarch_backend, .lld_linker, .coff_linker, .coff2_linker, @@ -225,6 +230,15 @@ pub const Env = enum { => true, else => Env.sema.supports(feature), }, + .@"loongarch-linux" => switch (feature) { + .stdio_listen, + .incremental, + .legalize, + .loongarch_backend, + .elf2_linker, + => true, + else => Env.sema.supports(feature), + }, }; } @@ -288,6 +302,7 @@ pub const Feature = enum { riscv64_backend, sparc64_backend, spirv_backend, + loongarch_backend, lld_linker, coff_linker, -- 2.54.0 From 726f539fe5975afee1ad857bff0c59032f146516 Mon Sep 17 00:00:00 2001 From: xtex Date: Fri, 7 Aug 2026 15:12:14 +0800 Subject: [PATCH 4/5] loongarch: scaffold a self-hosted LoongArch backend Signed-off-by: xtex --- CMakeLists.txt | 9 + lib/std/lang.zig | 4 + src/Zcu.zig | 4 + src/codegen.zig | 12 +- src/codegen/loongarch.zig | 163 + src/codegen/loongarch/Assemble.zig | 255 + src/codegen/loongarch/Disassemble.zig | 220 + src/codegen/loongarch/Mir.zig | 275 + src/codegen/loongarch/Select.zig | 7518 +++++++++++++++++++++++++ src/codegen/loongarch/bits.zig | 243 + src/target.zig | 4 +- 11 files changed, 8705 insertions(+), 2 deletions(-) create mode 100644 src/codegen/loongarch.zig create mode 100644 src/codegen/loongarch/Assemble.zig create mode 100644 src/codegen/loongarch/Disassemble.zig create mode 100644 src/codegen/loongarch/Mir.zig create mode 100644 src/codegen/loongarch/Select.zig create mode 100644 src/codegen/loongarch/bits.zig diff --git a/CMakeLists.txt b/CMakeLists.txt index 14df4e9b568d8fb6c5b924f6cd4e3c9778dc5e21..82628930580e9212f634682807d2640247aa5130 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -359,6 +359,15 @@ set(ZIG_STAGE2_SOURCES src/codegen/llvm.zig src/codegen/llvm/bindings.zig src/codegen/loongarch/abi.zig + src/codegen/loongarch/encoding.zig + src/codegen/loongarch/decode_tree.zon + src/codegen/loongarch/inst_formats.zon + src/codegen/loongarch/Assemble.zig + src/codegen/loongarch/Disassemble.zig + src/codegen/loongarch/Mir.zig + src/codegen/loongarch/bits.zig + src/codegen/loongarch/Select.zig + src/codegen/loongarch.zig src/codegen/s390x/abi.zig src/crash_report.zig src/dev.zig diff --git a/lib/std/lang.zig b/lib/std/lang.zig index c5ff616dc563537fc7016535e07872e9d657362b..293c08f7ec5960b38f2b39dbccee8529ddb90066 100644 --- a/lib/std/lang.zig +++ b/lib/std/lang.zig @@ -1313,6 +1313,9 @@ pub const CompilerBackend = enum(u64) { /// The reference implementation self-hosted compiler of Zig, using the /// powerpc backend. stage2_powerpc = 12, + /// The reference implementation self-hosted compiler of Zig, using the + /// loongarch backend. + stage2_loongarch = 13, _, }; @@ -1340,6 +1343,7 @@ pub const panic: type = p: { break :p root.panic; } break :p switch (builtin.zig_backend) { + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, => std.debug.simple_panic, diff --git a/src/Zcu.zig b/src/Zcu.zig index 5f64440990c95be60453ee38c1dde3d2850a058f..3b34c24505a0bef0a332d12ce7f075ba00d6b224 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -4725,6 +4725,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.lang.CallingConvention) union(enum) .spirv_task, .spirv_mesh => target.os.tag == .vulkan, else => false, }, + .stage2_loongarch => switch (cc) { + .loongarch64_lp64, .loongarch32_ilp32, .naked => true, + else => false, + }, }; if (!backend_ok) return .{ .bad_backend = backend }; return .ok; diff --git a/src/codegen.zig b/src/codegen.zig index 326a9f1e2f52b90bb40bf4006000c3864a47fed5..a505721eccea3794c4ff9df5a7018d10e8639527 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -23,6 +23,7 @@ const Alignment = InternPool.Alignment; const dev = @import("dev.zig"); pub const aarch64 = @import("codegen/aarch64.zig"); +pub const loongarch = @import("codegen/loongarch.zig"); pub const Error = link.Error; @@ -33,6 +34,7 @@ fn devFeatureForBackend(backend: std.lang.CompilerBackend) dev.Feature { .stage2_arm => .arm_backend, .stage2_c => .c_backend, .stage2_llvm => .llvm_backend, + .stage2_loongarch => .loongarch_backend, .stage2_powerpc => unreachable, .stage2_riscv64 => .riscv64_backend, .stage2_sparc64 => .sparc64_backend, @@ -51,6 +53,7 @@ fn importBackend(comptime backend: std.lang.CompilerBackend) type { .stage2_arm => unreachable, .stage2_c => @import("codegen/c.zig"), .stage2_llvm => @import("codegen/llvm.zig"), + .stage2_loongarch => loongarch, .stage2_powerpc => unreachable, .stage2_riscv64 => @import("codegen/riscv64/CodeGen.zig"), .stage2_sparc64 => @import("codegen/sparc64/CodeGen.zig"), @@ -71,6 +74,7 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co .stage2_wasm, .stage2_x86_64, .stage2_aarch64, + .stage2_loongarch, .stage2_x86, .stage2_riscv64, .stage2_sparc64, @@ -87,7 +91,7 @@ pub fn wantsLiveness(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) bool { const target = &zcu.navFileScope(nav_index).mod.?.resolved_target.result; return switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) { else => true, - .stage2_aarch64 => false, + .stage2_aarch64, .stage2_loongarch => false, }; } @@ -96,6 +100,7 @@ pub fn wantsLiveness(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) bool { /// union of all MIR types. The active tag is known from the backend in use; see `AnyMir.tag`. pub const AnyMir = union { aarch64: if (dev.env.supports(.aarch64_backend)) @import("codegen/aarch64/Mir.zig") else noreturn, + loongarch: if (dev.env.supports(.loongarch_backend)) @import("codegen/loongarch/Mir.zig") else noreturn, riscv64: if (dev.env.supports(.riscv64_backend)) @import("codegen/riscv64/Mir.zig") else noreturn, sparc64: if (dev.env.supports(.sparc64_backend)) @import("codegen/sparc64/Mir.zig") else noreturn, x86_64: if (dev.env.supports(.x86_64_backend)) @import("codegen/x86_64/Mir.zig") else noreturn, @@ -106,6 +111,7 @@ pub const AnyMir = union { pub inline fn tag(comptime backend: std.lang.CompilerBackend) []const u8 { return switch (backend) { .stage2_aarch64 => "aarch64", + .stage2_loongarch => "loongarch", .stage2_riscv64 => "riscv64", .stage2_sparc64 => "sparc64", .stage2_x86_64 => "x86_64", @@ -122,6 +128,7 @@ pub const AnyMir = union { switch (backend) { else => unreachable, inline .stage2_aarch64, + .stage2_loongarch, .stage2_riscv64, .stage2_sparc64, .stage2_x86_64, @@ -151,6 +158,7 @@ pub fn generateFunction( switch (target_util.zigBackend(target, false)) { else => unreachable, inline .stage2_aarch64, + .stage2_loongarch, .stage2_riscv64, .stage2_sparc64, .stage2_x86_64, @@ -194,6 +202,7 @@ pub fn emitFunction( switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) { else => unreachable, inline .stage2_aarch64, + .stage2_loongarch, .stage2_riscv64, .stage2_sparc64, .stage2_x86_64, @@ -1292,4 +1301,5 @@ pub fn flattenType(items_buf: []FlattenedItem, ty: Type, zcu: *Zcu, opts: struct test { _ = aarch64; + _ = loongarch; } diff --git a/src/codegen/loongarch.zig b/src/codegen/loongarch.zig new file mode 100644 index 0000000000000000000000000000000000000000..040c43d693de071c2123527c95f8d66dcdef3ceb --- /dev/null +++ b/src/codegen/loongarch.zig @@ -0,0 +1,163 @@ +pub const Mir = @import("loongarch/Mir.zig"); +const Select = @import("loongarch/Select.zig"); +const bits = @import("loongarch/bits.zig"); +pub const Disassemble = @import("loongarch/Disassemble.zig"); +pub const encoding = @import("loongarch/encoding.zig"); + +test { + _ = bits; + _ = Disassemble; +} + +pub fn legalizeFeatures(_: *const std.Target) ?*const Air.Legalize.Features { + return comptime &.initMany(&.{ + .expand_bit_cast_safe, + .expand_int_cast_safe, + .expand_int_from_float_safe, + .expand_int_from_float_optimized_safe, + .expand_add_safe, + .expand_sub_safe, + .expand_mul_safe, + .expand_packed_load, + .expand_packed_store, + .expand_packed_agg_field_val, + .expand_packed_aggregate_init, + .soft_f16, + .soft_f32, + .soft_f64, + .soft_f80, + }); +} + +pub fn generate( + _: *link.File, + pt: Zcu.PerThread, + func_index: InternPool.Index, + air: *const Air, + liveness: *const ?Air.Liveness, +) !Mir { + const zcu = pt.zcu; + const gpa = zcu.gpa; + const ip = &zcu.intern_pool; + const func = zcu.funcInfo(func_index); + const func_zir = func.zir_body_inst.resolveFull(ip).?; + const file = zcu.fileByIndex(func_zir.file); + const named_params_len = file.zir.?.getParamBody(func_zir.inst).len; + const func_type = ip.indexToKey(func.ty).func_type; + assert(liveness.* == null); + + // Initialize ISel + const mod = zcu.navFileScope(func.owner_nav).mod.?; + var isel: Select = .{ + .pt = pt, + .target = &mod.resolved_target.result, + .opt_mode = mod.optimize_mode, + .air = air.*, + .nav_index = zcu.funcInfo(func_index).owner_nav, + }; + defer isel.deinit(); + assert(try isel.active_blocks.fetchPut(gpa, Select.Block.main, .{ .target_label = 0 }) == null); + defer isel.active_blocks.entries.items(.value)[0].deinit(&isel); + + const air_main_body = air.getMainBody(); + + // Calculate parameter & return hints and layouts + var cc_it1: Select.CallAbiIterator = .{ + .cc = &func_type.cc, + .isel = &isel, + .stack_pointer = .fp, + }; + var cc_it2 = cc_it1; + + switch (func_type.cc) { + // naked functions cannot have any arguments + // Otherwise, SP will always be moved to allocate space for the saved FP and _start will be broken. + .naked => {}, + // FP is required to load byval arguments passed on stack now + // TODO: use FP only when necessary + else => isel.saved_registers.insert(.fp), + } + + const ret_layout_vi: ?Select.Value.Index = ret: { + const ret_vi1 = try cc_it1.resolve(.fromInterned(func_type.return_type), true) orelse break :ret null; + const ret_vi2 = try cc_it2.resolve(.fromInterned(func_type.return_type), true) orelse unreachable; + ret_vi2.deref(&isel); + tracking_log.debug("{f} <- %main", .{ret_vi1}); + try isel.live_values.putNoClobber(gpa, Select.Block.main, ret_vi1); + break :ret ret_vi2; + }; + + var arg_layouts: std.ArrayList(Select.Value.Index) = .empty; + defer arg_layouts.deinit(gpa); + for (air_main_body) |air_inst_index| { + if (air.instructions.items(.tag)[@backingInt(air_inst_index)] != .arg) break; + const arg = air.instructions.items(.data)[@backingInt(air_inst_index)].arg; + const param_ty = arg.ty.toType(); + if (arg.zir_param_index >= named_params_len) + assert(func_type.is_var_args); + const param_vi1 = try cc_it1.resolve(param_ty, false) orelse unreachable; + const param_vi2 = try cc_it2.resolve(param_ty, false) orelse unreachable; + tracking_log.debug("{f} <- %{d}", .{ param_vi1, @backingInt(air_inst_index) }); + try isel.live_values.putNoClobber(gpa, air_inst_index, param_vi1); + try arg_layouts.append(gpa, param_vi2); + } + if (arg_layouts.items.len != 0) + isel.arg_layouts = try arg_layouts.toOwnedSlice(gpa); + + // Analyze + try isel.analyze(air_main_body); + try isel.finishAnalysis(); + isel.verify(false); + + // Generate body + assert(isel.instructions.items.len == 0); + try isel.body(air_main_body); + if (isel.live_values.fetchRemove(Select.Block.main)) |ret_vi| { + defer ret_vi.value.deref(&isel); + + switch (ret_vi.value.parent(&isel)) { + .none, .value => {}, + .address => |ret_addr_vi| { + tracking_log.debug("live-in by-ref return address", .{}); + try ret_addr_vi.defLiveIn(&isel, ret_layout_vi.?.parent(&isel).address, .{}); + }, + .constant => unreachable, + } + } + + // Generate prologue and epilogue + const prologue = isel.instructions.items.len; + const epilogue = try isel.layout(cc_it1, mod); + + // Verification + isel.verify(true); + try isel.verifyTargetFeatures(); + + // Finalization + const instructions = try isel.instructions.toOwnedSlice(gpa); + var mir: Mir = .{ + .prologue = instructions[prologue..epilogue], + .body = instructions[0..prologue], + .epilogue = instructions[epilogue..], + .nav_relocs = &.{}, + .uav_relocs = &.{}, + .lazy_relocs = &.{}, + .global_relocs = &.{}, + .internal_relocs = &.{}, + }; + errdefer mir.deinit(gpa); + mir.nav_relocs = try isel.nav_relocs.toOwnedSlice(gpa); + mir.uav_relocs = try isel.uav_relocs.toOwnedSlice(gpa); + mir.lazy_relocs = try isel.lazy_relocs.toOwnedSlice(gpa); + mir.global_relocs = try isel.global_relocs.toOwnedSlice(gpa); + mir.internal_relocs = try isel.internal_relocs.toOwnedSlice(gpa); + return mir; +} + +const Air = @import("../Air.zig"); +const assert = std.debug.assert; +const InternPool = @import("../InternPool.zig"); +const link = @import("../link.zig"); +const std = @import("std"); +const tracking_log = std.log.scoped(.tracking); +const Zcu = @import("../Zcu.zig"); diff --git a/src/codegen/loongarch/Assemble.zig b/src/codegen/loongarch/Assemble.zig new file mode 100644 index 0000000000000000000000000000000000000000..9738ed9f4b03b1539d7be6f50888c8d13c4aad04 --- /dev/null +++ b/src/codegen/loongarch/Assemble.zig @@ -0,0 +1,255 @@ +source: []const u8, +args: std.StringHashMapUnmanaged(Operand) = .empty, + +pub const Operand = union(enum) { + register: Register, + signed_imm: i64, + unsigned_imm: u64, +}; + +pub fn deinit(as: *Assemble, gpa: std.mem.Allocator) void { + as.args.deinit(gpa); +} + +pub fn nextLine(as: *Assemble) []const u8 { + const line_len = std.mem.findScalar(u8, as.source, '\n') orelse { + const line = as.source; + as.source = ""; + return line; + }; + const line = as.source[0..line_len]; + as.source = as.source[line_len + 1 ..]; + return line; +} + +pub fn parseLine(as: *Assemble, orig_line: []const u8) !?Instruction { + var line = orig_line; + + // strip comment + if (std.mem.find(u8, line, "//")) |comment_i| line = line[comment_i..]; + + var token_it = std.mem.tokenizeAny(u8, line, " \t"); + if (token_it.next()) |mnemonic_str| { + log.debug("- '{s}'", .{line}); + log.debug(" - mnemonic: {s}", .{mnemonic_str}); + var op_it: OperandIterator = .init(as, token_it.rest()); + const instruction = parseInstruction(mnemonic_str, &op_it) orelse return error.InvalidSyntax; + if (!op_it.isEnd()) { + log.debug("find unrecognized operands", .{}); + return error.InvalidSyntax; + } + return instruction; + } else return null; +} + +const OperandIterator = struct { + as: *Assemble, + iter: std.mem.SplitIterator(u8, .scalar), + + fn init(as: *Assemble, ops: []const u8) OperandIterator { + log.debug(" - operands: {s}", .{ops}); + return .{ + .as = as, + .iter = std.mem.splitScalar(u8, ops, ','), + }; + } + + fn isEnd(it: *OperandIterator) bool { + return it.iter.peek() == null; + } + + fn next(it: *OperandIterator) ?[]const u8 { + if (it.iter.next()) |op| { + const res = std.mem.trim(u8, op, " \t"); + log.debug(" - {s}", .{res}); + return res; + } + return null; + } + + fn tryResolveArg(it: *OperandIterator, tmpl: []const u8) !?*Operand { + if (tmpl.len < 2) + return null; + if (tmpl[0] == '%' and tmpl[1] == '[' and tmpl[tmpl.len - 1] == ']') { + const arg_name = tmpl[2..][0 .. tmpl.len - 3]; + if (it.as.args.getPtr(arg_name)) |arg_op| + return arg_op; + } + return null; + } + + fn nextReg(it: *OperandIterator) ?Register { + if (it.next()) |name| { + return if (try it.tryResolveArg(name)) |arg_op| + switch (arg_op.*) { + .register => |reg| reg, + else => null, + } + else + Register.parse(name); + } + return null; + } + + fn nextImm(it: *OperandIterator, T: type) ?T { + if (it.next()) |imm_str| { + return if (try it.tryResolveArg(imm_str)) |arg_op| + switch (arg_op.*) { + inline .signed_imm, .unsigned_imm => |imm| if (std.math.cast(T, imm)) |imm_cast| + imm_cast + else + null, + else => null, + } + else + std.fmt.parseInt(T, imm_str, 0) catch null; + } + return null; + } +}; + +fn parseInstruction(mnemonic: []const u8, ops: *OperandIterator) ?Instruction { + @setEvalBranchQuota(3_000); + + // find override matchers + inline for (@typeInfo(matcher_overrides).@"struct".decl_names) |decl| { + if (mnemonicEql(decl, mnemonic)) { + const matcher = @field(matcher_overrides, decl); + return switch (@typeInfo(@TypeOf(matcher))) { + .@"fn" => matcher(ops), + .enum_literal => defaultMatcher(@field(Mnemonic, decl), ops), + .null => return null, + else => unreachable, + }; + } + } + + // find default matchers + inline for (@typeInfo(@TypeOf(inst_formats.instructions)).@"struct".field_names) |decl| { + if (@hasDecl(matcher_overrides, decl)) continue; + if (mnemonicEql(decl, mnemonic)) + return defaultMatcher(@field(Mnemonic, decl), ops); + } + + log.debug(" unmatched mnemonic", .{}); + return null; +} + +fn mnemonicEql(mnemonic: []const u8, rhs: []const u8) bool { + if (mnemonic.len != rhs.len) return false; + for (mnemonic, rhs) |l, r| { + assert(!std.ascii.isUpper(l)); + if (l != std.ascii.toLower(r)) return false; + } + return true; +} + +fn defaultMatcher(comptime mnemonic: Mnemonic, ops: *OperandIterator) ?Instruction { + const inst_info = @field(inst_formats.instructions, @tagName(mnemonic)); + const format = if (@hasField(@TypeOf(inst_info), "orig_format") and !@hasField(@TypeOf(inst_info), "orig_name")) + inst_info.orig_format + else + inst_info.format; + // TODO check features + return defaultMatcherFormat(@tagName(format), inst_info.word, ops); +} + +fn defaultMatcherFormat(comptime format: []const u8, word: u32, ops: *OperandIterator) ?Instruction { + const format_info = @field(inst_formats.formats, format); + const encodeFn = @field(encoding.Instruction, "encode" ++ format); + const EncodeArgs = std.meta.ArgsTuple(@TypeOf(encodeFn)); + var encode_args: EncodeArgs = undefined; + encode_args[0] = word; + inline for (format_info.slots, 1..) |slot, slot_i| { + const Slot = @TypeOf(slot); + if (@hasField(Slot, "reg")) { + const class = slot.reg.class; + const reg = ops.nextReg() orelse return null; + if (reg.class() != switch (class) { + .int => .int, + .fp, .lsx, .lasx => .fp, + .fcc => .fcc, + .lbt_scratch => .int, + else => unreachable, + }) + return null; + encode_args[slot_i] = reg; + } else if (@hasField(Slot, "imm")) { + const signedness = @field(std.builtin.Signedness, @tagName(slot.imm.signedness)); + const ImmValue = @Int(signedness, slot.imm.length); + encode_args[slot_i] = ops.nextImm(ImmValue) orelse return null; + } else { + @compileLog("Current slot:", slot); + @compileError("Invalid operand slot info"); + } + } + return @call(.always_inline, encodeFn, encode_args); +} + +const matcher_overrides = struct { + const b = null; + const bl = null; + const beqz = null; + const bnez = null; + const bceqz = null; + const bcnez = null; + const bgt = null; + const bgtu = null; + const ble = null; + const bleu = null; + + const @"xxx.unknown.1" = null; + const csrrd = null; + const csrwr = null; + const gcsrrd = null; + const gcsrwr = null; + const csrxchg = null; + const cacop = null; + const invtlb = null; + const tlbinv = null; + const preld = null; + const preldx = null; + const dbcl = null; + const ertn = null; + const pcaddi = null; + const @"ext.w.b" = null; + const @"ext.w.h" = null; + const @"ldptr.w" = null; + const @"ldptr.d" = null; + const @"stptr.w" = null; + const @"stptr.d" = null; + const @"bitrev.w" = null; + const @"bitrev.d" = null; + const @"bitrev.4b" = null; + const @"bitrev.8b" = null; + const @"asrtle.d" = null; + const @"asrtgt.d" = null; + const @"lu32i.d" = null; + const lu52i = null; + const @"alsl.w" = null; + const @"alsl.wu" = null; + const @"alsl.d" = null; + const @"bytepick.w" = null; + const @"bytepick.d" = null; + + pub fn move(ops: *OperandIterator) ?Instruction { + const rd = ops.nextReg() orelse return null; + const rj = ops.nextReg() orelse return null; + return .ori(rd, rj, 0); + } + + pub fn nop(_: *OperandIterator) ?Instruction { + return .andi(.zero, .zero, 0); + } +}; + +const Assemble = @This(); +const assert = std.debug.assert; +const encoding = @import("encoding.zig"); +const bits = @import("bits.zig"); +const Instruction = encoding.Instruction; +const Mnemonic = encoding.Mnemonic; +const Register = bits.Register; +const std = @import("std"); +const log = std.log.scoped(.@"asm"); +const inst_formats = @import("inst_formats.zon"); diff --git a/src/codegen/loongarch/Disassemble.zig b/src/codegen/loongarch/Disassemble.zig new file mode 100644 index 0000000000000000000000000000000000000000..fb781a59582684ca2a4331998f161b069dde3ebe --- /dev/null +++ b/src/codegen/loongarch/Disassemble.zig @@ -0,0 +1,220 @@ +const encoding = @import("encoding.zig"); +const Mnemonic = encoding.Mnemonic; +const Instruction = encoding.Instruction; +const bits = @import("bits.zig"); +const Register = bits.Register; +const Disassemble = @This(); + +const decode_tree = @import("decode_tree.zon"); +const inst_formats = @import("inst_formats.zon"); + +mnemonic_operands_separator: []const u8 = " ", +operands_separator: []const u8 = ", ", +enable_aliases: bool = false, +preferred_style: Style = .manual, + +pub const Style = enum { + /// Encoding style, used by loongson-community/loongarch-opcodes. + /// + /// Output operands are not post-processed, sorted with slot offset. + encoding, + /// Manual style, used by the official manual and assembly code. + /// + /// Output operands are post-processed. + manual, +}; + +pub fn printInstruction(dis: *const Disassemble, inst: Instruction, writer: *std.Io.Writer) std.Io.Writer.Error!void { + @setEvalBranchQuota(3000); + const mnemonic = decodeMnemonic(inst) orelse return try writer.print("(UNKNOWN: 0x{x:0>8})", .{inst.word}); + + inline for (@typeInfo(Mnemonic).@"enum".field_names) |mnemonic_field| try_mnemonic: { + if (@field(Mnemonic, mnemonic_field) != mnemonic) break :try_mnemonic; + + const inst_info = @field(inst_formats.instructions, mnemonic_field); + const InstInfo = @TypeOf(inst_info); + + switch (dis.preferred_style) { + .encoding => { + try writer.writeAll(mnemonic_field); + const format = inst_info.format; + if (format != .EMPTY) try writer.writeAll(dis.mnemonic_operands_separator); + try dis.printOperands(@field(inst_formats.formats, @tagName(format)), inst, writer); + }, + .manual => { + try writer.writeAll(if (@hasField(InstInfo, "orig_name")) inst_info.orig_name else mnemonic_field); + const format = if (@hasField(InstInfo, "orig_format")) inst_info.orig_format else inst_info.format; + if (format != .EMPTY) try writer.writeAll(dis.mnemonic_operands_separator); + try dis.printOperands(@field(inst_formats.formats, @tagName(format)), inst, writer); + }, + } + return; + } +} + +pub fn printInstructionAlloc(dis: *const Disassemble, inst: Instruction, gpa: std.mem.Allocator) (std.Io.Writer.Error || std.mem.Allocator.Error)![]u8 { + var writer: std.Io.Writer.Allocating = .init(gpa); + defer writer.deinit(); + try dis.printInstruction(inst, &writer.writer); + return try writer.toOwnedSlice(); +} + +test printInstruction { + const dis: Disassemble = .{}; + + const testDisasm = struct { + fn testDisasm(expected: []const u8, inst: u32) !void { + const assembly = try dis.printInstructionAlloc(.{ .word = inst }, std.testing.allocator); + defer std.testing.allocator.free(assembly); + try std.testing.expectEqualStrings(expected, assembly); + } + }.testDisasm; + + try testDisasm("fcmp.caf.s $fcc0, $f1, $f2", 0x0c100820); + try testDisasm("ertn", 0x06483800); + try testDisasm("addi.d $r8, $r0, 0xa", 0x02c02808); +} + +pub fn fmtInstruction(dis: Disassemble, inst: Instruction) struct { + dis: Disassemble, + inst: Instruction, + + pub fn format(data: @This(), w: *std.Io.Writer) std.Io.Writer.Error!void { + try data.dis.printInstruction(data.inst, w); + } +} { + return .{ .dis = dis, .inst = inst }; +} + +pub fn decodeMnemonic(inst: Instruction) ?Mnemonic { + return decodeMnemonicWithTree(decode_tree, inst); +} + +/// Decodes mnemonics with a node in the decode tree. +fn decodeMnemonicWithTree(comptime tree: anytype, inst: Instruction) ?Mnemonic { + const Tree = @TypeOf(tree); + if (@hasField(Tree, "instruction")) { + return @field(Mnemonic, @tagName(tree.instruction)); + } else if (@hasField(Tree, "mask")) { + const value = inst.word & tree.mask; + inline for (tree.cases) |case| try_case: { + if (@hasField(@TypeOf(case), "value")) { + if (value != case.value) break :try_case; + } + const then = case.then; + + if (@hasField(@TypeOf(then), "instruction")) { + // manually inline here to reduce decoder functions of leaf nodes + return @field(Mnemonic, @tagName(then.instruction)); + } else return decodeMnemonicWithTree(then, inst); + } + return null; + } else { + @compileLog("Current decode-tree node:", tree); + @compileError("Invalid decode-tree node"); + } +} + +test decodeMnemonic { + try std.testing.expectEqual(Mnemonic.@"fcmp.caf.s", decodeMnemonic(.{ .word = 0x0c100820 }).?); + try std.testing.expectEqual(Mnemonic.eret, decodeMnemonic(.{ .word = 0x06483800 }).?); + try std.testing.expectEqual(Mnemonic.@"addi.d", decodeMnemonic(.{ .word = 0x02c02808 }).?); +} + +pub fn printOperands(dis: *const Disassemble, comptime format: anytype, inst: Instruction, writer: *std.Io.Writer) std.Io.Writer.Error!void { + const word = inst.word; + inline for (format.slots, 0..) |slot, slot_i| { + if (slot_i != 0) try writer.writeAll(dis.operands_separator); + + const Slot = @TypeOf(slot); + if (@hasField(Slot, "reg")) { + const location = slot.reg.location; + const class = slot.reg.class; + + const reg: u5 = if (class == .fcc) + @as(u3, @truncate(word >> location)) + else + @as(u5, @truncate(word >> location)); + + try dis.printRegister(writer, class, reg); + } else if (@hasField(Slot, "imm")) { + const signedness = @field(std.builtin.Signedness, @tagName(slot.imm.signedness)); + const ImmValue = @Int(signedness, slot.imm.length); + const UnsignedImmValue = @Int(.unsigned, slot.imm.length); + const Imm32 = @Int(signedness, 32); + // extend to 32-bit so postprocess won't overflow + var value: Imm32 = @as(ImmValue, @bitCast(@as(UnsignedImmValue, @truncate(word >> slot.imm.location)))); + + if (@hasField(@TypeOf(slot.imm), "post_proc")) { + const postproc = slot.imm.post_proc; + const PostProc = @TypeOf(postproc); + if (@hasField(PostProc, "shl")) value <<= postproc.shl; + if (@hasField(PostProc, "add")) value += postproc.add; + } + + if (signedness == .unsigned) { + try writer.print("0x{x}", .{value}); + } else { + if (value >= 0) + try writer.print("0x{x}", .{value}) + else + try writer.print("-0x{x}", .{@abs(value)}); + } + } else { + @compileLog("Current slot:", slot); + @compileError("Invalid operand slot info"); + } + } +} + +fn printRegister(dis: *const Disassemble, writer: *std.Io.Writer, comptime class: anytype, orig_reg: u5) std.Io.Writer.Error!void { + var reg = orig_reg; + const reg_prefix = prefix: { + if (dis.enable_aliases) { + switch (class) { + .int => switch (reg) { + 1 => return try writer.print("$ra", .{}), + 3 => return try writer.print("$sp", .{}), + 4...11 => { + reg -= 4; + break :prefix "a"; + }, + 12...20 => { + reg -= 12; + break :prefix "t"; + }, + 22 => return try writer.print("$fp", .{}), + 23...31 => { + reg -= 23; + break :prefix "s"; + }, + else => {}, + }, + .fp => switch (reg) { + 0...7 => break :prefix "fa", + 8...23 => { + reg -= 8; + break :prefix "ft"; + }, + 24...31 => { + reg -= 24; + break :prefix "fs"; + }, + }, + else => {}, + } + } + break :prefix switch (class) { + .int => "r", + .fp => "f", + .fcc => "fcc", + .lsx => "v", + .lasx => "x", + else => unreachable, + }; + }; + + try writer.print("${s}{d}", .{ reg_prefix, reg }); +} + +const std = @import("std"); diff --git a/src/codegen/loongarch/Mir.zig b/src/codegen/loongarch/Mir.zig new file mode 100644 index 0000000000000000000000000000000000000000..44f6cfd3165cdeb04d2f0e063d214b5da34be361 --- /dev/null +++ b/src/codegen/loongarch/Mir.zig @@ -0,0 +1,275 @@ +const Mir = @This(); +const Instruction = @import("encoding.zig").Instruction; +const Disassemble = @import("Disassemble.zig"); + +prologue: []const Instruction, +body: []const Instruction, +epilogue: []const Instruction, +nav_relocs: []const Reloc.Nav, +uav_relocs: []const Reloc.Uav, +lazy_relocs: []const Reloc.Lazy, +global_relocs: []const Reloc.Global, +internal_relocs: []const Reloc.Internal, + +pub const Reloc = struct { + label: u32, + addend: i64 align(@alignOf(u32)) = 0, + + pub const Nav = struct { + nav: InternPool.Nav.Index, + reloc: Reloc, + }; + + pub const Uav = struct { + uav: InternPool.Key.Ptr.BaseAddr.Uav, + reloc: Reloc, + }; + + pub const Lazy = struct { + symbol: link.File.LazySymbol, + reloc: Reloc, + }; + + pub const Global = struct { + name: [*:0]const u8, + reloc: Reloc, + }; + + pub const Literal = struct { + label: u32, + }; + + pub const Internal = struct { + // Target MIR index + target: usize = 0, + label: u32, + }; +}; + +pub fn deinit(mir: *Mir, gpa: std.mem.Allocator) void { + assert(mir.body.ptr + mir.body.len == mir.prologue.ptr); + assert(mir.prologue.ptr + mir.prologue.len == mir.epilogue.ptr); + gpa.free(mir.body.ptr[0 .. mir.body.len + mir.prologue.len + mir.epilogue.len]); + gpa.free(mir.nav_relocs); + gpa.free(mir.uav_relocs); + gpa.free(mir.lazy_relocs); + gpa.free(mir.global_relocs); + gpa.free(mir.internal_relocs); + mir.* = undefined; +} + +pub fn emit( + mir: Mir, + lf: *link.File, + pt: Zcu.PerThread, + func_index: InternPool.Index, + atom_index: link.File.AtomId, + w: *std.Io.Writer, + debug_output: link.File.DebugInfoOutput, +) !void { + _ = debug_output; + const zcu = pt.zcu; + const ip = &zcu.intern_pool; + const func = zcu.funcInfo(func_index); + const nav = ip.getNav(func.owner_nav); + mir_log.debug("{f}:", .{nav.fqn.fmt(ip)}); + + const code_len = mir.prologue.len + mir.body.len + mir.epilogue.len; + try w.rebase(w.end, @sizeOf(Instruction) * code_len); + emitInstructionsBackward(w, mir.prologue) catch unreachable; + emitInstructionsBackward(w, mir.body) catch unreachable; + const body_end: u32 = @intCast(w.end); + emitInstructionsBackward(w, mir.epilogue) catch unreachable; + mir_log.debug("", .{}); + + for (mir.nav_relocs) |nav_reloc| emitReloc( + lf, + zcu, + atom_index, + try @import("../../codegen.zig").genNavRef( + lf, + pt, + nav_reloc.nav, + ), + mir.body[nav_reloc.reloc.label], + body_end - @sizeOf(Instruction) * (1 + nav_reloc.reloc.label), + nav_reloc.reloc.addend, + ) catch |err| + return zcu.codegenFail(func.owner_nav, "emit reloc failed: {t}", .{err}); + for (mir.uav_relocs) |uav_reloc| emitReloc( + lf, + zcu, + atom_index, + try lf.lowerUav( + pt, + uav_reloc.uav.val, + ZigType.fromInterned(uav_reloc.uav.orig_ty).ptrAlignment(zcu), + ), + mir.body[uav_reloc.reloc.label], + body_end - @sizeOf(Instruction) * (1 + uav_reloc.reloc.label), + uav_reloc.reloc.addend, + ) catch |err| + return zcu.codegenFail(func.owner_nav, "emit reloc failed: {t}", .{err}); + for (mir.lazy_relocs) |lazy_reloc| emitReloc( + lf, + zcu, + atom_index, + if (lf.cast(.elf)) |ef| + @fromBackingInt(ef.zigObjectPtr().?.getOrCreateMetadataForLazySymbol(ef, pt, lazy_reloc.symbol) catch |err| + return zcu.codegenFail(func.owner_nav, "{s} creating lazy symbol", .{@errorName(err)})) + else if (lf.cast(.elf2)) |elf| + elf.lazySymbol(lazy_reloc.symbol) catch |err| + return zcu.codegenFail(func.owner_nav, "emit lazy symbol: {t}", .{err}) + else + return zcu.codegenFail(func.owner_nav, "external symbols unimplemented for {s}", .{@tagName(lf.tag)}), + mir.body[lazy_reloc.reloc.label], + body_end - @sizeOf(Instruction) * (1 + lazy_reloc.reloc.label), + lazy_reloc.reloc.addend, + ) catch |err| + return zcu.codegenFail(func.owner_nav, "emit reloc failed: {t}", .{err}); + for (mir.global_relocs) |global_reloc| emitReloc( + lf, + zcu, + atom_index, + if (lf.cast(.elf)) |ef| + @fromBackingInt(try ef.getGlobalSymbol(std.mem.span(global_reloc.name), null)) + else if (lf.cast(.elf2)) |elf| elf.externSymbol(.{ + .name = std.mem.span(global_reloc.name), + .lib_name = null, + .type = .FUNC, + }) catch |err| + return zcu.codegenFail(func.owner_nav, "emit global symbol failed: {t}", .{err}) else return zcu.codegenFail(func.owner_nav, "external symbols unimplemented for {s}", .{@tagName(lf.tag)}), + mir.body[global_reloc.reloc.label], + body_end - @sizeOf(Instruction) * (1 + global_reloc.reloc.label), + global_reloc.reloc.addend, + ) catch |err| + return zcu.codegenFail(func.owner_nav, "emit reloc failed: {t}", .{err}); + + const func_nav = try @import("../../codegen.zig").genNavRef( + lf, + pt, + func.owner_nav, + ); + for (mir.internal_relocs) |internal_reloc| emitReloc( + lf, + zcu, + atom_index, + func_nav, + mir.body[internal_reloc.label], + body_end - @sizeOf(Instruction) * (1 + internal_reloc.label), + @sizeOf(Instruction) * (@as(i64, @intCast(mir.prologue.len + mir.body.len - internal_reloc.target))), + ) catch |err| + return zcu.codegenFail(func.owner_nav, "emit reloc failed: {t}", .{err}); +} + +fn emitInstructionsForward(w: *std.Io.Writer, instructions: []const Instruction) !void { + for (instructions) |instruction| try emitInstruction(w, instruction); +} +fn emitInstructionsBackward(w: *std.Io.Writer, instructions: []const Instruction) !void { + var instruction_index = instructions.len; + while (instruction_index > 0) { + instruction_index -= 1; + try emitInstruction(w, instructions[instruction_index]); + } +} +fn emitInstruction(w: *std.Io.Writer, instruction: Instruction) !void { + mir_log.debug(" {f}", .{(Disassemble{}).fmtInstruction(instruction)}); + try w.writeInt(@FieldType(Instruction, "word"), instruction.word, .little); +} + +fn emitReloc( + lf: *link.File, + zcu: *Zcu, + atom_index: link.File.AtomId, + sym_index: link.File.SymbolId, + instruction: Instruction, + offset: u32, + addend: i64, +) !void { + const mnemonic = Disassemble.decodeMnemonic(instruction) orelse { + mir_log.debug("cannot decode instruction 0x{x}", .{instruction.word}); + unreachable; + }; + switch (mnemonic) { + else => { + mir_log.debug("unimplemented reloc on {t}", .{mnemonic}); + unreachable; + }, + .pcaddu18i => if (lf.cast(.elf2)) |ef| { + try ef.addReloc(atom_index, offset, sym_index, addend, .{ .LARCH = .CALL36 }); + } else if (lf.cast(.elf)) |ef| { + const zo = ef.zigObjectPtr().?; + const atom = zo.symbol(@backingInt(atom_index)).atom(ef).?; + try atom.addReloc(zcu.gpa, .{ + .r_offset = offset, + .r_info = @as(u64, @backingInt(sym_index)) << 32 | @backingInt(std.elf.R_LARCH.CALL36), + .r_addend = @bitCast(addend), + }, zo); + } else unreachable, + .b, .bl => if (lf.cast(.elf2)) |ef| { + try ef.addReloc(atom_index, offset, sym_index, addend, .{ .LARCH = .B26 }); + } else if (lf.cast(.elf)) |ef| { + const zo = ef.zigObjectPtr().?; + const atom = zo.symbol(@backingInt(atom_index)).atom(ef).?; + try atom.addReloc(zcu.gpa, .{ + .r_offset = offset, + .r_info = @as(u64, @backingInt(sym_index)) << 32 | @backingInt(std.elf.R_LARCH.B26), + .r_addend = @bitCast(addend), + }, zo); + } else unreachable, + .beq, .bne, .ble, .bgt, .bleu, .bgtu => if (lf.cast(.elf2)) |ef| { + try ef.addReloc(atom_index, offset, sym_index, addend, .{ .LARCH = .B16 }); + } else if (lf.cast(.elf)) |ef| { + const zo = ef.zigObjectPtr().?; + const atom = zo.symbol(@backingInt(atom_index)).atom(ef).?; + try atom.addReloc(zcu.gpa, .{ + .r_offset = offset, + .r_info = @as(u64, @backingInt(sym_index)) << 32 | @backingInt(std.elf.R_LARCH.B16), + .r_addend = @bitCast(addend), + }, zo); + } else unreachable, + .beqz, .bnez, .bceqz, .bcnez => if (lf.cast(.elf2)) |ef| { + try ef.addReloc(atom_index, offset, sym_index, addend, .{ .LARCH = .B21 }); + } else if (lf.cast(.elf)) |ef| { + const zo = ef.zigObjectPtr().?; + const atom = zo.symbol(@backingInt(atom_index)).atom(ef).?; + try atom.addReloc(zcu.gpa, .{ + .r_offset = offset, + .r_info = @as(u64, @backingInt(sym_index)) << 32 | @backingInt(std.elf.R_LARCH.B21), + .r_addend = @bitCast(addend), + }, zo); + } else unreachable, + .pcalau12i => if (lf.cast(.elf2)) |ef| { + try ef.addReloc(atom_index, offset, sym_index, addend, .{ .LARCH = .PCALA_HI20 }); + } else if (lf.cast(.elf)) |ef| { + const zo = ef.zigObjectPtr().?; + const atom = zo.symbol(@backingInt(atom_index)).atom(ef).?; + try atom.addReloc(zcu.gpa, .{ + .r_offset = offset, + .r_info = @as(u64, @backingInt(sym_index)) << 32 | @backingInt(std.elf.R_LARCH.PCALA_HI20), + .r_addend = @bitCast(addend), + }, zo); + } else unreachable, + .@"addi.d" => if (lf.cast(.elf2)) |ef| { + try ef.addReloc(atom_index, offset, sym_index, addend, .{ .LARCH = .PCALA_LO12 }); + } else if (lf.cast(.elf)) |ef| { + const zo = ef.zigObjectPtr().?; + const atom = zo.symbol(@backingInt(atom_index)).atom(ef).?; + try atom.addReloc(zcu.gpa, .{ + .r_offset = offset, + .r_info = @as(u64, @backingInt(sym_index)) << 32 | @backingInt(std.elf.R_LARCH.PCALA_LO12), + .r_addend = @bitCast(addend), + }, zo); + } else unreachable, + } +} + +const Air = @import("../../Air.zig"); +const assert = std.debug.assert; +const mir_log = std.log.scoped(.mir); +const InternPool = @import("../../InternPool.zig"); +const link = @import("../../link.zig"); +const std = @import("std"); +const target_util = @import("../../target.zig"); +const Zcu = @import("../../Zcu.zig"); +const ZigType = @import("../../Type.zig"); diff --git a/src/codegen/loongarch/Select.zig b/src/codegen/loongarch/Select.zig new file mode 100644 index 0000000000000000000000000000000000000000..2e7d1a4c4986d8292be757a73ddcfa925409ee7b --- /dev/null +++ b/src/codegen/loongarch/Select.zig @@ -0,0 +1,7518 @@ +const Register = @import("bits.zig").Register; +const encoding = @import("encoding.zig"); +const Instruction = encoding.Instruction; +const Mir = @import("Mir.zig"); +const Assemble = @import("Assemble.zig"); +const Disassemble = @import("Disassemble.zig"); + +const verify_target_features = false; +const assume_memmove_no_overlap = true; +/// https://github.com/ziglang/zig/issues/11307 +/// Enabling this flag generates "break 0xAA" for unimplemented things. +const debug_trap_unimplemented_code = false; +/// Saves AIR index to $r21 for debugging. +const debug_r21_as_air = false; + +pt: Zcu.PerThread, +target: *const std.Target, +opt_mode: std.builtin.OptimizeMode, +air: Air, +nav_index: InternPool.Nav.Index, + +// WIP MIR +saved_registers: RegisterSet = .empty, +instructions: std.ArrayList(Instruction) = .empty, +nav_relocs: std.ArrayList(Mir.Reloc.Nav) = .empty, +uav_relocs: std.ArrayList(Mir.Reloc.Uav) = .empty, +lazy_relocs: std.ArrayList(Mir.Reloc.Lazy) = .empty, +global_relocs: std.ArrayList(Mir.Reloc.Global) = .empty, +internal_relocs: std.ArrayList(Mir.Reloc.Internal) = .empty, + +// Stack Frame +returns: bool = false, +stack_size: u24 = 0, +stack_align: InternPool.Alignment = .@"16", +/// Relocations for reading incoming registers. +/// +/// The instruction must be `ori rd, rj, 0`. +/// These relocations are applied in `Select.layout`, +/// and the instruction may be replaced with `ld.[w/d] rd, sp, ?` +/// if `rj` is spilled to stack. +/// +/// See `Select.ldIncoming`. +layout_relocs: std.ArrayList(usize) = .empty, + +// Value Tracking +live_registers: LiveRegisters = .initFill(.free), +live_values: std.AutoHashMapUnmanaged(Air.Inst.Index, Value.Index) = .empty, +values: std.ArrayList(Value) = .empty, +value_types: std.ArrayList(ZigType) = .empty, + +// Calling Convention +arg_layouts: []const Value.Index = &.{}, + +// Analysis +/// Definition order of AIR instructions. +def_order: std.AutoArrayHashMapUnmanaged(Air.Inst.Index, void) = .empty, +/// Stack of active blocks. Value is undefined during analysis. +active_blocks: std.AutoArrayHashMapUnmanaged(Air.Inst.Index, Block) = .empty, +/// Loops. The last entry is Loop.invalid, which is added in `finishAnalysis`. +loops: std.AutoArrayHashMapUnmanaged(Air.Inst.Index, Loop) = .empty, +/// Stack of active loops. +active_loops: std.ArrayList(Loop.Index) = .empty, +/// Loop liveness +loop_outer_live: struct { + /// Pairs of loops and AIRs that is used in the loop body but is defined + /// earlier than the loop entry. + /// Populated during analysis phase, in analyseUse. + /// + /// Includes only references where the loop and the AIR are in the same upper loop. + /// For example, in the following structure: + /// %1 arg + /// %2 arg + /// %3 arg + /// %4 loop (loop 0) + /// %5 add %1 %2 + /// %6 loop (loop 1) + /// %7 add %3 %5 + /// %8 add %2 %5 + /// Only (loop 0, %1), (loop 0, %2), (loop 0, %3), (loop 1, %5) will be recorded, because, + /// although %2 and %3 are used in loop 1, they are in the outer layer of loop 0, not loop 1. + set: std.AutoArrayHashMapUnmanaged(struct { Loop.Index, Air.Inst.Index }, void) = .empty, + /// List representation of `loop_live.set`, for faster indexing. + list: std.ArrayList(Air.Inst.Index) = .empty, +} = .{}, + +pub const RegisterSet = std.enums.EnumSet(Register); +pub const LiveRegisters = std.enums.EnumArray(Register, Value.Index); + +pub const Block = struct { + snapshot: LocationSnapshot = .empty, + target_label: u32, + + pub const main: Air.Inst.Index = @fromBackingInt( + std.math.maxInt(@typeInfo(Air.Inst.Index).@"enum".tag_type), + ); + + pub fn deinit(target_block: *Block, isel: *Select) void { + target_block.snapshot.deinit(isel); + } + + fn branch(target_block: *Block, isel: *Select) !void { + if (isel.instructions.items.len > target_block.target_label) { + try isel.internal_relocs.append(isel.pt.zcu.gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = target_block.target_label, + }); + try isel.emit(.b(0, 0)); + } + try target_block.snapshot.merge(isel); + } +}; + +pub const Loop = struct { + def_order: u32, + outer_live: u32, + repeat_list: u32, + /// Used during code selection. Location snapshot before entering loop bodyies. + /// Cleared after leaving the loop body. + snapshot: LocationSnapshot = .empty, + /// Used during code selection. Registers that are written during a loop body. + /// See Select.markRegWritten. + /// After leaving a loop, written register set is copied to the outer loop. + written_regs: RegisterSet = .empty, + + pub const invalid: Air.Inst.Index = @fromBackingInt( + std.math.maxInt(@typeInfo(Air.Inst.Index).@"enum".tag_type), + ); + + pub const Index = enum(u32) { + _, + + fn inst(li: Loop.Index, isel: *Select) Air.Inst.Index { + return isel.loops.keys()[@backingInt(li)]; + } + + fn get(li: Loop.Index, isel: *Select) *Loop { + return &isel.loops.values()[@backingInt(li)]; + } + }; + + pub const empty_list: u32 = std.math.maxInt(u32); + + fn branch(target_loop: *Loop, isel: *Select) !void { + try isel.instructions.ensureUnusedCapacity(isel.pt.zcu.gpa, 1); + const repeat_list_tail = target_loop.repeat_list; + target_loop.repeat_list = @intCast(isel.instructions.items.len); + isel.instructions.appendAssumeCapacity(@bitCast(repeat_list_tail)); + try target_loop.snapshot.merge(isel); + } +}; + +pub fn deinit(isel: *Select) void { + const gpa = isel.pt.zcu.gpa; + + isel.instructions.deinit(gpa); + isel.nav_relocs.deinit(gpa); + isel.uav_relocs.deinit(gpa); + isel.lazy_relocs.deinit(gpa); + isel.global_relocs.deinit(gpa); + isel.internal_relocs.deinit(gpa); + + isel.layout_relocs.deinit(gpa); + + isel.live_values.deinit(gpa); + isel.values.deinit(gpa); + isel.value_types.deinit(gpa); + + if (isel.arg_layouts.len != 0) gpa.free(isel.arg_layouts); + + isel.def_order.deinit(gpa); + isel.active_blocks.deinit(gpa); + isel.loops.deinit(gpa); + isel.active_loops.deinit(gpa); + isel.loop_outer_live.set.deinit(gpa); + isel.loop_outer_live.list.deinit(gpa); + + isel.* = undefined; +} + +/// A node in the value tree. +pub const Value = struct { + refs: u32, + flags: Flags, + offset_from_parent: u64, + parent_payload: Parent.Payload, + location_payload: LocationInfo.Payload, + parts: Value.Index, + + /// Must be at least 16 to compute call ABI. + /// Must be at least 16, the largest hardware alignment. + pub const max_parts = 16; + pub const PartsLen = std.math.IntFittingRange(0, Value.max_parts); + + comptime { + if (!std.debug.runtime_safety) assert(@sizeOf(Value) == 32); + } + + pub const Flags = packed struct(u32) { + alignment: InternPool.Alignment, + parent_tag: Parent.Tag, + location_tag: LocationInfo.Tag, + parts_len_minus_one: std.math.IntFittingRange(0, Value.max_parts - 1), + splitted: bool, + unused: u17 = 0, + }; + + pub const Parent = union(enum(u2)) { + none: void, + value: Value.Index, + constant: Constant, + /// Dereferencing. Only used for layout values at ABI boundaries. + address: Value.Index, + + pub const Tag = @typeInfo(Parent).@"union".tag_type.?; + pub const Payload = Payload: { + const info = @typeInfo(Parent).@"union"; + break :Payload @Union(.auto, null, info.field_names, info.field_types[0..], &@splat(.{})); + }; + }; + + pub const LocationInfo = union(enum(u2)) { + /// Small values that fit into a register + small: struct { + flags: packed struct { + /// Byte-size of the part + size: u6, + /// Way in which the unused bits are filled + /// For subtrees whose root has Parent.address, immutable after initialization + extension: Extension, + /// Register access modifier + hint_modifier: Register.Modifier, + /// Preferred register, maybe ignore, $zero = unset + hint_register: Register, + /// The current expected location + location_tag: Location.Tag, + }, + location_payload: Location.Payload, + }, + /// Large values that can only be stored in stack slots + large: struct { + /// Byte-size of the part + size: u32, + /// The current expected location + /// Well-shaped values are always in pcs extended, ill-shaped are garbage extended + stack_slot: Indirect, + }, + /// Extreme values that are too large to be materialized in stack slots + extreme: struct { + size: u64, + }, + + pub const Tag = @typeInfo(LocationInfo).@"union".tag_type.?; + pub const Payload = Payload: { + const info = @typeInfo(LocationInfo).@"union"; + break :Payload @Union(.auto, null, info.field_names, info.field_types[0..], &@splat(.{})); + }; + }; + + pub const Location = union(enum(u1)) { + register: Register.Alias, + stack_slot: Indirect, + + pub const unallocated: Location = .{ .register = .zero }; + + pub inline fn isUnallocated(loc: Location) bool { + return switch (loc) { + .register => |ra| ra.reg == Register.zero, + else => false, + }; + } + + fn tryLock(loc: Location, isel: *Select) RegLock { + return if (loc.asRegister()) |reg| isel.tryLockReg(reg) else .empty; + } + + pub fn asRegisterAlias(loc: Location) ?Register.Alias { + return switch (loc) { + .register => |ra| if (ra.reg == Register.zero) null else ra, + else => null, + }; + } + + pub fn asRegister(loc: Location) ?Register { + return if (loc.asRegisterAlias()) |ra| ra.reg else null; + } + + pub fn asStackSlot(loc: Location) ?Indirect { + return switch (loc) { + .stack_slot => |stack_slot| stack_slot, + else => null, + }; + } + + pub fn format(loc: Location, w: *std.Io.Writer) std.Io.Writer.Error!void { + if (loc.isUnallocated()) return w.writeAll("unallocated"); + switch (loc) { + inline else => |loc_pl| try loc_pl.format(w), + } + } + + pub fn markRegWritten(loc: Location, isel: *Select) void { + if (loc.asRegister()) |loc_reg| isel.markRegWritten(loc_reg); + } + + pub const Tag = @typeInfo(Location).@"union".tag_type.?; + pub const Payload = Payload: { + const info = @typeInfo(Location).@"union"; + break :Payload @Union(.auto, null, info.field_names, info.field_types[0..], &@splat(.{})); + }; + }; + + // TODO far indirect + pub const Indirect = packed struct(u32) { + base: Register, + offset: i25, + + pub const unallocated: Indirect = .{ .base = .zero, .offset = 0 }; + + pub fn withOffset(ind: Indirect, offset: i25) Indirect { + return .{ + .base = ind.base, + .offset = ind.offset + offset, + }; + } + + pub fn format(self: Indirect, w: *std.Io.Writer) std.Io.Writer.Error!void { + try w.print("[${t}, #{s}0x{x}]", .{ + self.base, + if (self.offset < 0) "-" else "", + @abs(self.offset), + }); + } + }; + + pub const Extension = enum(u2) { + garbage, + sign_ext, + zero_ext, + + pub fn fromSignedness(signedness: std.builtin.Signedness) Extension { + return switch (signedness) { + .signed => .sign_ext, + .unsigned => .zero_ext, + }; + } + + fn signednessForLoad(fill_mode: Extension) std.builtin.Signedness { + return switch (fill_mode) { + .garbage, .zero_ext => .unsigned, + .sign_ext => .signed, + }; + } + + pub fn mix(a: Extension, b: Extension) Extension { + if (a == b) return a; + return .garbage; + } + + fn pcsMode(isel: *Select, ty: ZigType) Extension { + const zcu = isel.pt.zcu; + const int_info = switch (ty.zigTypeTag(zcu)) { + .bool => ZigType.u1.intInfo(zcu), + .int, .@"enum", .error_set => ty.intInfo(zcu), + else => return .garbage, + }; + return switch (int_info.bits) { + 32 => .sign_ext, + else => .fromSignedness(int_info.signedness), + }; + } + }; + + pub const Index = enum(u32) { + allocating = std.math.maxInt(u32) - 1, + free = std.math.maxInt(u32) - 0, + _, + + fn get(vi: Value.Index, isel: *Select) *Value { + return &isel.values.items[@backingInt(vi)]; + } + + fn typeOf(vi: Value.Index, isel: *Select) ?ZigType { + const ty = isel.value_types.items[@backingInt(vi)]; + if (ty.ip_index == .none) return null; + return ty; + } + + pub fn format(vi: Value.Index, w: *std.Io.Writer) std.Io.Writer.Error!void { + return switch (vi) { + _ => w.print("${d}", .{@backingInt(vi)}), + .allocating => w.writeAll("(allocating)"), + .free => w.writeAll("(free)"), + }; + } + + fn setAlignment(vi: Value.Index, isel: *Select, new_alignment: InternPool.Alignment) void { + vi.get(isel).flags.alignment = new_alignment; + } + + pub fn alignment(vi: Value.Index, isel: *Select) InternPool.Alignment { + return vi.get(isel).flags.alignment; + } + + pub fn setParent(vi: Value.Index, isel: *Select, new_parent: Parent) void { + const value = vi.get(isel); + if (value.refs > 0) { + switch (value.flags.parent_tag) { + .none, .constant => {}, + inline .address, .value => |tag| @field(value.parent_payload, @tagName(tag)).deref(isel), + } + switch (new_parent) { + .none => unreachable, + .constant => {}, + .address, .value => |parent_vi| _ = parent_vi.ref(isel), + } + } + value.flags.parent_tag = new_parent; + value.parent_payload = switch (new_parent) { + .none => unreachable, + inline else => |payload, tag| @unionInit(Parent.Payload, @tagName(tag), payload), + }; + } + + pub fn parent(vi: Value.Index, isel: *Select) Parent { + const value = vi.get(isel); + return switch (value.flags.parent_tag) { + inline else => |tag| @unionInit( + Parent, + @tagName(tag), + @field(value.parent_payload, @tagName(tag)), + ), + }; + } + + pub fn parentValue(vi: Value.Index, isel: *Select) ?Value.Index { + const value = vi.get(isel); + return switch (value.flags.parent_tag) { + .value => value.parent_payload.value, + else => null, + }; + } + + pub fn valueRoot(initial_vi: Value.Index, isel: *Select) struct { u64, Value.Index } { + var offset: u64 = 0; + var vi = initial_vi; + parent: switch (vi.parent(isel)) { + else => return .{ offset, vi }, + .value => |parent_vi| { + offset += vi.get(isel).offset_from_parent; + vi = parent_vi; + continue :parent parent_vi.parent(isel); + }, + } + } + + pub fn locationInfo(vi: Value.Index, isel: *Select) LocationInfo { + const value = vi.get(isel); + return switch (value.flags.location_tag) { + inline else => |tag| @unionInit( + LocationInfo, + @tagName(tag), + @field(value.location_payload, @tagName(tag)), + ), + }; + } + + pub fn isSmall(vi: Value.Index, isel: *Select) bool { + return vi.get(isel).flags.location_tag == .small; + } + + pub fn setSmallLocation(vi: Value.Index, isel: *Select, new_location: Location) void { + const value = vi.get(isel); + value.location_payload.small.flags.location_tag = new_location; + value.location_payload.small.location_payload = switch (new_location) { + inline else => |payload, tag| @unionInit(Location.Payload, @tagName(tag), payload), + }; + } + + pub fn smallLocation(vi: Value.Index, isel: *Select) Location { + const value = vi.get(isel); + return switch (value.location_payload.small.flags.location_tag) { + inline else => |tag| @unionInit( + Location, + @tagName(tag), + @field(value.location_payload.small.location_payload, @tagName(tag)), + ), + }; + } + + pub fn positionInParent(vi: Value.Index, isel: *Select) struct { u64, u64 } { + return .{ vi.get(isel).offset_from_parent, vi.size(isel) }; + } + + pub fn offsetIn(initial_vi: Value.Index, isel: *Select, ancestor_vi: Value.Index) u64 { + if (initial_vi == ancestor_vi) return 0; + var offset: u64 = 0; + var vi = initial_vi; + parent: switch (vi.parent(isel)) { + else => unreachable, // ancestor_vi is not an ancestor of initial_vi + .value => |parent_vi| { + offset += vi.get(isel).offset_from_parent; + if (parent_vi != ancestor_vi) { + vi = parent_vi; + continue :parent parent_vi.parent(isel); + } else return offset; + }, + } + } + + pub fn size(vi: Value.Index, isel: *Select) u64 { + return switch (vi.locationInfo(isel)) { + .small => |loc| loc.flags.size, + inline else => |loc| loc.size, + }; + } + + pub fn bitSize(vi: Value.Index, isel: *Select) u64 { + if (vi.typeOf(isel)) |init_ty| bit_size: { + const zcu = isel.pt.zcu; + var ty = init_ty; + check_ty: while (true) { + switch (ty.zigTypeTag(zcu)) { + else => {}, + .error_union => break :bit_size, + .@"struct", .@"union" => if (ty.containerLayout(zcu) != .@"packed") break :bit_size, + .pointer, .optional => if (!ty.isPtrAtRuntime(zcu)) break :bit_size, + .array, .vector => { + ty = ty.childType(zcu); + continue :check_ty; + }, + } + break :check_ty; + } + return init_ty.bitSize(zcu); + } + return vi.size(isel) * 8; + } + + fn setExtension(vi: Value.Index, isel: *Select, new_mode: Extension) void { + const value = vi.get(isel); + if (value.flags.location_tag == .small) + value.location_payload.small.flags.extension = new_mode; + } + + /// For values on stack, unused bits are the highest ((size * 8) - bit_size) bits. + /// For values on registers, unused bits are the highest (ra_width - bit_size) bits. + /// That is, for a u3 (3b, 1B) stored in LA64 GPR (64b, 8B), the unused bits to be filled + /// are reg[3..63] instead of reg[3..7]. + pub fn extension(vi: Value.Index, isel: *Select) Extension { + const value = vi.get(isel); + return switch (value.flags.location_tag) { + .small => value.location_payload.small.flags.extension, + .large, .extreme => if (vi.typeOf(isel)) |ty| .pcsMode(isel, ty) else .garbage, + }; + } + + fn setHintModifier(vi: Value.Index, isel: *Select, new_modifier: Register.Modifier) void { + vi.get(isel).location_payload.small.flags.hint_modifier = new_modifier; + } + + pub fn hintModifier(vi: Value.Index, isel: *Select) Register.Modifier { + return switch (vi.locationInfo(isel)) { + .small => |loc| loc.flags.hint_modifier, + .large, .extreme => .undef, + }; + } + + fn setHintRegister(vi: Value.Index, isel: *Select, new_hint: Register) void { + vi.get(isel).location_payload.small.flags.hint_register = new_hint; + } + + pub fn hintRegister(vi: Value.Index, isel: *Select) ?Register { + return switch (vi.locationInfo(isel)) { + .small => |loc| switch (loc.flags.hint_register) { + Register.zero => null, + else => |hint_reg| hint_reg, + }, + .large, .extreme => null, + }; + } + + pub fn hintRegisterAlias(vi: Value.Index, isel: *Select) ?Register.Alias { + return switch (vi.locationInfo(isel)) { + .small => |loc| switch (loc.flags.hint_register) { + Register.zero => null, + else => |hint_reg| .{ .mod = vi.hintModifier(isel), .reg = hint_reg }, + }, + .large, .extreme => null, + }; + } + + pub fn location(vi: Value.Index, isel: *Select) ?Location { + return switch (vi.locationInfo(isel)) { + .small => |loc| if (loc.flags.location_tag == .register and loc.location_payload.register.reg == Register.zero) + null + else switch (loc.flags.location_tag) { + inline else => |tag| @unionInit( + Location, + @tagName(tag), + @field(loc.location_payload, @tagName(tag)), + ), + }, + .large => |loc| if (loc.stack_slot == Indirect.unallocated) + null + else + .{ .stack_slot = loc.stack_slot }, + .extreme => null, + }; + } + + pub fn register(vi: Value.Index, isel: *Select) ?Register.Alias { + return switch (vi.location(isel) orelse return null) { + .register => |ra| ra, + .stack_slot => null, + }; + } + + pub fn stackSlot(vi: Value.Index, isel: *Select) ?Indirect { + return switch (vi.location(isel) orelse return null) { + .register => null, + .stack_slot => |slot| slot, + }; + } + + /// Takes the expected location. Registers are free. + fn takeLocation(vi: Value.Index, isel: *Select) ?Location { + const value = vi.get(isel); + return switch (value.flags.location_tag) { + .small => loc: { + const loc = vi.smallLocation(isel); + if (loc.isUnallocated()) break :loc null; + if (loc.asRegister()) |reg| { + const live_vi = isel.live_registers.getPtr(reg); + assert(live_vi.* == vi); + live_vi.* = .free; + } + vi.setSmallLocation(isel, .unallocated); + break :loc loc; + }, + .large => loc: { + const stack_slot = value.location_payload.large.stack_slot; + if (stack_slot == Indirect.unallocated) break :loc null; + value.location_payload.large.stack_slot = .unallocated; + break :loc .{ .stack_slot = stack_slot }; + }, + .extreme => null, + }; + } + + /// Takes the expected location. Registers are free and marked written. + fn takeLocationMarkWritten(vi: Value.Index, isel: *Select) ?Location { + const maybe_loc = vi.takeLocation(isel); + if (maybe_loc) |loc| loc.markRegWritten(isel); + return maybe_loc; + } + + fn setStackSlot(vi: Value.Index, isel: *Select, new_slot: Indirect) void { + const value = vi.get(isel); + return switch (value.flags.location_tag) { + .small => vi.setSmallLocation(isel, .{ .stack_slot = new_slot }), + .large => value.location_payload.large.stack_slot = new_slot, + .extreme => unreachable, + }; + } + + pub fn isUsed(vi: Value.Index, isel: *Select) bool { + return vi.valueRoot(isel)[1].parent(isel) != .none or vi.hasLocationRecursive(isel); + } + + fn hasLocationRecursive(vi: Value.Index, isel: *Select) bool { + if (vi.location(isel) != null) return true; + var part_it = vi.parts(isel); + if (part_it.only() == null) + while (part_it.next()) |part_vi| + if (part_vi.hasLocationRecursive(isel)) return true; + return false; + } + + fn setParts(vi: Value.Index, isel: *Select, parts_len: Value.PartsLen) void { + assert(parts_len > 1); + const value = vi.get(isel); + assert(value.flags.parts_len_minus_one == 0); + value.parts = @fromBackingInt(@intCast(isel.values.items.len)); + value.flags.parts_len_minus_one = @intCast(parts_len - 1); + } + + fn addPart(vi: Value.Index, isel: *Select, part_offset: u64, part_size: u64, maybe_ty: ?ZigType) Value.Index { + const part_vi = isel.initValueAdvanced( + vi.alignment(isel), + part_offset, + part_size, + maybe_ty, + ); + if (maybe_ty) |ty| + tracking_log.debug("{f} <- {f}[{d}] ({d}B, {f})", .{ part_vi, vi, part_offset, part_size, isel.fmtType(ty) }) + else + tracking_log.debug("{f} <- {f}[{d}] ({d}B, untyped)", .{ part_vi, vi, part_offset, part_size }); + part_vi.setParent(isel, .{ .value = vi }); + return part_vi; + } + + fn addIntPart(vi: Value.Index, isel: *Select, part_offset: u64, part_size: u64, part_bit_size: u9) !Value.Index { + const part_vi = isel.initValueAdvanced(vi.alignment(isel), part_offset, part_size, try isel.pt.intType(.unsigned, part_bit_size)); + tracking_log.debug("{f} <- {f}[{d}] ({d}B, {d}b)", .{ part_vi, vi, part_offset, part_size, part_bit_size }); + part_vi.setParent(isel, .{ .value = vi }); + return part_vi; + } + + pub fn parts(vi: Value.Index, isel: *Select) Value.PartIterator { + const value = vi.get(isel); + return switch (value.flags.parts_len_minus_one) { + 0 => .initOne(vi), + else => |parts_len_minus_one| .{ + .vi = value.parts, + .remaining = @as(Value.PartsLen, parts_len_minus_one) + 1, + }, + }; + } + + pub fn hasParts(vi: Value.Index, isel: *Select) bool { + return vi.get(isel).flags.parts_len_minus_one != 0; + } + + fn partAtOffset(vi: Value.Index, isel: *Select, offset: u64) Value.Index { + const SearchPartIndex = std.math.IntFittingRange(0, Value.max_parts * 2 - 1); + const value = vi.get(isel); + var last: SearchPartIndex = value.flags.parts_len_minus_one; + if (last == 0) return vi; + var first: SearchPartIndex = 0; + last += 1; + while (true) { + const mid = (first + last) / 2; + const mid_vi: Value.Index = @fromBackingInt(@backingInt(value.parts) + mid); + if (mid == first) return mid_vi; + if (offset < mid_vi.get(isel).offset_from_parent) last = mid else first = mid; + } + } + + fn partExact(vi: Value.Index, isel: *Select, offset: u64, part_size: u64) !Value.Index { + try vi.split(isel, false); + const part_vi = vi.partAtOffset(isel, offset); + if (part_vi.offsetIn(isel, vi) != offset or part_vi.size(isel) != part_size) { + isel.dumpValues(.all); + tracking_log.debug("{f}.partExact({}, {}) selected {f}", .{ vi, offset, part_size, part_vi }); + unreachable; + } + return part_vi; + } + + fn partExactRecursive(vi: Value.Index, isel: *Select, init_offset: u64, part_size: u64) !Value.Index { + if (init_offset == 0 and vi.size(isel) == part_size) return vi; + var part_vi = vi; + var offset = init_offset; + while (true) { + try part_vi.split(isel, false); + const subpart_vi = part_vi.partAtOffset(isel, offset); + if (subpart_vi == part_vi) { + isel.dumpValues(.all); + tracking_log.debug("{f}.partExactRecursive({}, {}) selected {f}", .{ vi, init_offset, part_size, part_vi }); + unreachable; + } + const subpart_offset = subpart_vi.get(isel).offset_from_parent; + offset -= subpart_offset; + if (offset == 0 and subpart_vi.size(isel) == part_size) return subpart_vi; + part_vi = subpart_vi; + } + } + + fn partAtLargerThan(vi: Value.Index, isel: *Select, offset: u64, part_size: u64) !Value.Index { + try vi.split(isel, false); + const part_vi = vi.partAtOffset(isel, offset); + if (part_vi.offsetIn(isel, vi) != offset or part_vi.size(isel) < part_size) { + isel.dumpValues(.all); + tracking_log.debug("{f}.partAtLargerThan({}, {}) selected {f}", .{ vi, offset, part_size, part_vi }); + unreachable; + } + return part_vi; + } + + fn walk(vi: Value.Index, isel: *Select, opts: Walk.Options) Walk { + return .{ .isel = isel, .root_vi = vi, .next_vi = vi, .opts = opts }; + } + + fn ref(initial_vi: Value.Index, isel: *Select) Value.Index { + var vi = initial_vi; + while (true) { + const refs = &vi.get(isel).refs; + refs.* += 1; + if (refs.* > 1) return initial_vi; + switch (vi.parent(isel)) { + .none, .constant => {}, + .address, .value => |parent_vi| { + vi = parent_vi; + continue; + }, + } + return initial_vi; + } + } + + pub fn deref(initial_vi: Value.Index, isel: *Select) void { + var vi = initial_vi; + while (true) { + const refs = &vi.get(isel).refs; + refs.* -= 1; + if (refs.* > 0) return; + switch (vi.parent(isel)) { + .none, .constant => {}, + .address, .value => |parent_vi| { + vi = parent_vi; + continue; + }, + } + return; + } + } + + /// Allocates a stack slot for this value, not updating the value location. + fn allocStackSlot(vi: Value.Index, isel: *Select) Indirect { + const offset = vi.alignment(isel).forward(isel.stack_size); + isel.stack_size = @intCast(offset + vi.size(isel)); + tracking_log.debug("[sp, #0x{x}] -> allocated for {f}", .{ @abs(offset), vi }); + return .{ + .base = .sp, + .offset = @intCast(offset), + }; + } + + /// Allocates a register for this value, not updating the value location. + fn allocRegister(vi: Value.Index, isel: *Select) !?Register.Alias { + // Try to allocate hint register + if (vi.hintRegister(isel)) |hint_reg| { + const live_vi = isel.live_registers.getPtr(hint_reg); + if (live_vi.* == .free) { + live_vi.* = .allocating; + isel.saved_registers.insert(hint_reg); + return .{ .reg = hint_reg, .mod = vi.hintModifier(isel) }; + } + } + // Try to allocate a register + const value = vi.get(isel); + switch (value.flags.location_tag) { + .small => { + const reg_mod = vi.hintModifier(isel); + const reg = try isel.allocReg(reg_mod.class()); + return .{ .reg = reg, .mod = reg_mod }; + }, + .large, .extreme => return null, + } + } + + fn reextend(vi: Value.Index, isel: *Select, new_ext: Extension) !void { + if (!vi.isSmall(isel)) return; + return vi.reextendAdvanced(isel, vi.bitSize(isel), null, new_ext); + } + + fn reextendToGarbage(vi: Value.Index, isel: *Select) !void { + if (!vi.isSmall(isel)) return; + return vi.reextendAdvanced(isel, vi.bitSize(isel), null, .garbage); + } + + fn reextendToPcs(vi: Value.Index, isel: *Select) !void { + if (!vi.isSmall(isel)) return; + const ty = vi.typeOf(isel) orelse unreachable; // cannot reextend ill-shaped values to PCS mode + return vi.reextendAdvanced(isel, vi.bitSize(isel), null, .pcsMode(isel, ty)); + } + + fn reextendAdvanced( + vi: Value.Index, + isel: *Select, + old_bits: u64, + override_old_ext: ?Extension, + new_ext: Extension, + ) !void { + if (vi.location(isel) == null) return; + const value = vi.get(isel); + const old_ext = override_old_ext orelse vi.extension(isel); + const bit_size = vi.bitSize(isel); + if (bit_size == 0) return; + const vi_bits = vi.size(isel) * 8; + const old_unused_bits = vi_bits - @min(old_bits, vi_bits); + const new_unused_bits = vi_bits - bit_size; + const dst_ext, const src_ext = if (bit_size == old_bits) + .{ old_ext, new_ext } + else if (bit_size < old_bits) + .{ .garbage, new_ext } + else ext_config: { + // To cast an ABI int to a wider one, signedness of the int must be specified + // in new_ext, so bits that are previously unused but now used can be properly + // re-filled. + if (old_ext != .garbage) + break :ext_config .{ old_ext, new_ext } + else + break :ext_config .{ .zero_ext, new_ext }; + }; + const unused_bits = @max(new_unused_bits, old_unused_bits); + if (dst_ext == src_ext and bit_size <= old_bits) return; + tracking_log.debug("{f}: {t} ({t}) -> {t} ({t}), {d}b -> {d}b", .{ vi, src_ext, new_ext, dst_ext, old_ext, old_bits, bit_size }); + + // avoid setting extension to .garbage to reduce MIR for sequences like + // zero_ext -> garbage -> zero_ext + if (dst_ext == .garbage) return; + if (value.flags.location_tag == .small) + value.location_payload.small.flags.extension = new_ext; + if (vi_bits <= isel.gprBits()) { + const vi_mat = try vi.mat(isel, .{ .pref = .only_reg }); + try isel.fillUnusedBits( + vi_mat.reg(), + vi_mat.reg(), + dst_ext, + src_ext, + @intCast(vi_mat.ra().mod.bitSize(isel.target) - vi_bits + unused_bits), + ); + try vi_mat.finish(isel); + } else { + const unused_bytes = std.math.divCeil(u64, unused_bits, 8) catch unreachable; + assert(unused_bytes <= isel.gprSize()); // TODO larger extending + const used_bytes = vi.size(isel) - unused_bytes; + + var hit = false; + var walker = vi.walk(isel, .{}); + while (walker.next()) |part_vi| { + const part_offset = part_vi.offsetIn(isel, vi); + const part_size = part_vi.size(isel); + const part_end = part_offset + part_size; + if (part_end <= used_bytes) continue; + if (part_size > isel.gprSize()) continue; + + walker.skipChildren(part_vi); + + const part_mat = try part_vi.mat(isel, .{ .pref = .only_reg }); + try isel.fillUnusedBits( + part_mat.reg(), + part_mat.reg(), + dst_ext, + src_ext, + @intCast(unused_bits - ((vi.size(isel) - part_end) * 8)), + ); + try part_mat.finish(isel); + if (hit) unreachable; // TODO + hit = true; + } + } + } + + /// Defines ancestors by combining their children + fn defChildren(def_vi: Value.Index, isel: *Select) !void { + if (def_vi.parentValue(isel)) |parent_vi| + try parent_vi.defChildren(isel); + assert(def_vi.hasParts(isel)); + if (def_vi.location(isel) == null) return; + wip_mir_log.debug(" | # merge children -> {f}", .{def_vi}); + const def_bit_size = def_vi.bitSize(isel); + + // If def_vi fits into a register, reextend def_vi + var reextend_parts = true; + if (def_vi.isSmall(isel)) { + const maybe_mixed_ext = mix_ext: { + var maybe_mixed_ext: ?Extension = null; + var part_it = def_vi.parts(isel); + while (part_it.next()) |part_vi| { + const part_offset, const part_size = part_vi.positionInParent(isel); + if ((part_offset + part_size) * 8 > def_bit_size) { + if (maybe_mixed_ext) |mixed_ext| + maybe_mixed_ext = mixed_ext.mix(part_vi.extension(isel)) + else + maybe_mixed_ext = part_vi.extension(isel); + } + } + break :mix_ext maybe_mixed_ext; + }; + if (maybe_mixed_ext) |mixed_ext| { + try def_vi.reextend(isel, mixed_ext); + reextend_parts = false; + } + } + + const def_loc = def_vi.takeLocationMarkWritten(isel).?; + const def_reg_lock = def_loc.tryLock(isel); + defer def_reg_lock.unlock(isel); + const def_ext = def_vi.extension(isel); + var part_it = def_vi.parts(isel); + while (part_it.next()) |part_vi| { + const part_offset, const part_size = part_vi.positionInParent(isel); + const part_mat = try part_vi.mat(isel, .{}); + try isel.moveLoc(def_loc, part_offset, part_mat.loc(), 0, part_size, .preserved); + try part_mat.finish(isel); + if (reextend_parts) + try part_vi.reextend(isel, def_ext); + } + } + + /// Defines descendants by deriving from their parents + fn defParent(def_vi: Value.Index, isel: *Select) !void { + if (def_vi.hasParts(isel)) { + // DFS descendants + var part_it = def_vi.parts(isel); + while (part_it.next()) |part_vi| try part_vi.defParent(isel); + } + wip_mir_log.debug(" | # derive parent -> {f}", .{def_vi}); + const parent_vi = def_vi.parentValue(isel).?; + try def_vi.reextendAdvanced(isel, parent_vi.bitSize(isel), null, parent_vi.extension(isel)); + const def_loc = def_vi.takeLocationMarkWritten(isel) orelse return; + const def_offset, const def_size = def_vi.positionInParent(isel); + const parent_mat = try parent_vi.mat(isel, .{}); + try isel.moveLoc(def_loc, 0, parent_mat.loc(), def_offset, def_size, .none); + try parent_mat.finish(isel); + } + + /// Defines ancestors and descendants + fn collectDefs(vi: Value.Index, isel: *Select) !void { + if (vi.parentValue(isel)) |parent_vi| + try parent_vi.defChildren(isel); + if (vi.hasParts(isel)) { + var part_it = vi.parts(isel); + while (part_it.next()) |part_vi| try part_vi.defParent(isel); + } + } + + /// Defines a value with a location. + /// Returned location must be free-ed by caller. + /// Extension unchanged. + fn def(vi: Value.Index, isel: *Select) error{ AlreadyReported, OutOfMemory }!?Location { + try vi.collectDefs(isel); + return vi.takeLocationMarkWritten(isel); + } + + /// Defines a value with a register. + /// Returned registers are free-ed. + /// Extension unchanged. + fn defReg(vi: Value.Index, isel: *Select) !?Register.Alias { + const value = vi.get(isel); + assert(value.flags.location_tag == .small); // must fit into a register + try vi.collectDefs(isel); + + const loc = vi.takeLocationMarkWritten(isel) orelse return null; + switch (loc) { + .register => |ra| return ra, + .stack_slot => |stack| { + const reg_mod = vi.hintModifier(isel); + const reg = try isel.allocRegForWrite(reg_mod.class()); + defer isel.freeReg(reg); + const ra: Register.Alias = .{ .mod = reg_mod, .reg = reg }; + try isel.storeReg(reg, vi.size(isel), stack.base, stack.offset); + return ra; + }, + } + } + + /// Defines a value with a register. + /// Returned registers are free-ed. + /// Extension unchanged. + fn defRegMod(vi: Value.Index, isel: *Select, mod: Register.Modifier) !?Register { + assert(mod != .undef); + const loc = try vi.defReg(isel) orelse return null; + if (loc.mod == mod) return loc.reg; + const new_reg = try isel.allocRegForWrite(mod.class()); + try isel.moveReg( + loc, + 0, + .{ .reg = new_reg, .mod = mod }, + 0, + @min(loc.mod.bitSize(isel.target), mod.bitSize(isel.target)), + .none, + ); + return new_reg; + } + + /// Defines a value with a stack slot. + /// Reextended in PCS mode. + fn defStack(vi: Value.Index, isel: *Select) !?Indirect { + try vi.reextendToPcs(isel); + try vi.collectDefs(isel); + const loc = vi.takeLocationMarkWritten(isel) orelse return null; + switch (loc) { + .register => |ra| { + const stack_slot = vi.allocStackSlot(isel); + try isel.loadReg(ra.reg, vi.size(isel), vi.extension(isel).signednessForLoad(), stack_slot.base, stack_slot.offset); + return stack_slot; + }, + .stack_slot => |stack| return stack, + } + } + + /// Defines a value with undefined bytes. + fn defUndef(vi: Value.Index, isel: *Select) !void { + try vi.reextendToGarbage(isel); + try vi.collectDefs(isel); + const loc = vi.takeLocationMarkWritten(isel) orelse return; + wip_mir_log.debug(" | # undef -> {f}", .{vi}); + try isel.moveUndef(loc, vi.size(isel)); + } + + /// Defines a value by loading from memory. + /// Reextended to PCS mode. + /// + /// Returns true if vi has a location. + fn defLoad( + vi: Value.Index, + isel: *Select, + base_reg: Register, + offset: u64, + opts: MemoryAccessOptions, + ) !bool { + try vi.reextendToPcs(isel); + try vi.collectDefs(isel); + const loc = vi.takeLocationMarkWritten(isel) orelse return false; + wip_mir_log.debug(" | # load {f} <- [${t}, #{d}] ({d}B)", .{ vi, base_reg, offset, vi.size(isel) }); + _ = opts; + + try isel.moveLoc( + loc, + 0, + .{ .stack_slot = .{ .base = base_reg, .offset = 0 } }, + offset, + vi.size(isel), + .none, + ); + return true; + } + + /// Defines a value by copying another value. + /// PCS aware. + fn defMove(dst_vi: Value.Index, isel: *Select, src_ref: Air.Inst.Ref) !void { + try dst_vi.defCopy(isel, try isel.use(src_ref)); + } + + /// Defines a value by copying another value. + /// PCS aware. + fn defCopy(dst_vi: Value.Index, isel: *Select, src_vi: Value.Index) !void { + try dst_vi.collectDefs(isel); + wip_mir_log.debug(" | # copy {f} <- {f}", .{ dst_vi, src_vi }); + const copy_size = @min(dst_vi.size(isel), src_vi.size(isel)); + + // select reextension strategy + const ext_strat: enum { dst_to_src, src_to_dst } = ext_strat: { + const dst_has_loc = dst_vi.location(isel) != null; + const src_has_loc = src_vi.location(isel) != null; + if (dst_has_loc and !src_has_loc and src_vi.isSmall(isel)) break :ext_strat .src_to_dst; + if (src_has_loc and !dst_has_loc) break :ext_strat .dst_to_src; + break :ext_strat .dst_to_src; // random choice + }; + + // reextend dst + if (ext_strat == .dst_to_src) { + try dst_vi.reextendAdvanced( + isel, + dst_vi.bitSize(isel), + null, + src_vi.extension(isel), + ); + } + + // do copy + { + const loc = dst_vi.takeLocation(isel) orelse return; + const src_mat = try src_vi.mat(isel, .{ + .size = @intCast(copy_size), + .pref = switch (loc) { + .register => .prefer_reg, + .stack_slot => .prefer_stack, + }, + .hint_ra = loc.asRegisterAlias() orelse .zero, + .hint_stack = loc.asStackSlot() orelse .unallocated, + }); + const src_loc = src_mat.loc(); + if (!std.meta.eql(loc, src_loc)) { + loc.markRegWritten(isel); + try isel.moveLoc(loc, 0, src_mat.loc(), 0, copy_size, .none); + } + try src_mat.finish(isel); + } + + // reextend src + if (ext_strat == .src_to_dst) { + try src_vi.reextend(isel, dst_vi.extension(isel)); + } + } + + /// Defines a value in a certain layout, commonly used near basic block boundaries. + /// Reextends to PCS mode. + pub fn defLiveIn(def_vi: Value.Index, isel: *Select, layout_vi: Value.Index, opts: struct { + /// Whether registers should be freed. + fill_regs: bool = true, + }) !void { + wip_mir_log.debug(" | # live in {f}, layout={f}", .{ def_vi, layout_vi }); + assert(def_vi.size(isel) == layout_vi.size(isel)); + const gpa = isel.pt.zcu.gpa; + + var maybe_def_addr_mat: ?Value.Mat = null; + switch (def_vi.parent(isel)) { + .none => {}, + .value => |parent_vi| try parent_vi.defChildren(isel), + .address => |def_addr_vi| { + switch (layout_vi.parent(isel)) { + .address => |layout_addr_vi| { + try def_addr_vi.defLiveIn(isel, layout_addr_vi, opts); + }, + .none, .value => { + maybe_def_addr_mat = try def_vi.parent(isel).address.matIntRegZeroExt(isel); + }, + .constant => unreachable, + } + }, + .constant => unreachable, + } + + // TODO optimize this O(n^2) + var def_walk = def_vi.walk(isel, .{}); + while (def_walk.next()) |def_part_vi| { + const part_offset = def_part_vi.offsetIn(isel, def_vi); + const part_size = def_part_vi.size(isel); + const part_end_plus1 = part_offset + part_size; + + var layout_walk = layout_vi.walk(isel, .{}); + var layout_parts: std.ArrayList(struct { + vi: Value.Index, + offset: u64, + end_plus1: u64, + }) = .empty; + defer layout_parts.deinit(gpa); + var maybe_mixed_layout_ext: ?Extension = null; + while (layout_walk.next()) |layout_part_vi| { + if (layout_part_vi.location(isel) == null and layout_part_vi.hintRegister(isel) == null) continue; + const layout_part_offset = layout_part_vi.offsetIn(isel, layout_vi); + const layout_part_size = layout_part_vi.size(isel); + const layout_part_end_plus1 = layout_part_offset + layout_part_size; + if (layout_part_end_plus1 <= part_offset or + layout_part_offset >= part_end_plus1) continue; + + try layout_parts.append(gpa, .{ + .vi = layout_part_vi, + .offset = layout_part_offset, + .end_plus1 = layout_part_end_plus1, + }); + + const layout_part_ext = layout_part_vi.extension(isel); + if (maybe_mixed_layout_ext) |mixed_layout_ext| { + maybe_mixed_layout_ext = mixed_layout_ext.mix(layout_part_ext); + } else { + maybe_mixed_layout_ext = layout_part_ext; + } + } + if (maybe_mixed_layout_ext) |mixed_layout_ext| { + try def_part_vi.reextend(isel, mixed_layout_ext); + } else unreachable; + + const def_part_loc = if (maybe_def_addr_mat == null or def_part_vi != def_vi) def_part_loc: { + break :def_part_loc def_part_vi.takeLocationMarkWritten(isel) orelse continue; + } else def_part_loc: { + break :def_part_loc maybe_def_addr_mat.?.loc(); + }; + const def_part_lock = def_part_loc.tryLock(isel); + defer def_part_lock.unlock(isel); + + for (layout_parts.items) |layout_part| { + const dst_offset = layout_part.offset -| part_offset; + const src_offset = part_offset -| layout_part.offset; + + const mat_size = @min(part_end_plus1, layout_part.end_plus1) - @max(part_offset, layout_part.offset); + assert(mat_size != 0); + const src_loc: Location = if (layout_part.vi.location(isel)) |loc| + loc + else if (layout_part.vi.hintRegisterAlias(isel)) |hint_ra| + .{ .register = hint_ra } + else + unreachable; + if (opts.fill_regs) { + if (src_loc.asRegister()) |src_reg| + _ = try isel.fillReg(src_reg); + } + // TODO: replace reextending def_part_vi to .zero_ext with moveLoc .wipe when applicable + try isel.moveLoc(def_part_loc, dst_offset, src_loc, src_offset, mat_size, .preserved); + } + } + if (maybe_def_addr_mat) |def_addr_mat| try def_addr_mat.finish(isel); + } + + const MemoryAccessOptions = struct { + // TODO unimplemented, remove? + @"volatile": bool = false, + }; + + const MatOptions = struct { + /// Offset of materialized part + offset: u64 = 0, + /// Size, coerced to [0, part size - offset] + size: u32 = std.math.maxInt(u32), + /// Location preference + pref: LocPreference = .none, + reg_mod: Register.Modifier = .undef, + /// Expected extension mode + extension: Extension = .garbage, + hint_ra: Register.Alias = .zero, + hint_stack: Indirect = .unallocated, + + const LocPreference = enum { + none, + /// Loads value to a register if possible, otherwise returns a stack slot + prefer_reg, + /// Loads value to a register, asserts the value fitting into a register + only_reg, + /// If there isn't an exisiting location, allocate a stack slot + prefer_stack, + /// Stores value to a stack slot + only_stack, + }; + }; + + /// Materializes a value + fn mat(vi: Value.Index, isel: *Select, opts: MatOptions) Mat.Error!Mat { + // try vi.split(isel, true); + const mat_size = @min(opts.size, @as(u32, @intCast(vi.size(isel) - opts.offset))); + const loc_pref = if (opts.extension == .garbage) + opts.pref + else switch (opts.pref) { + .none, .prefer_reg, .prefer_stack => .prefer_reg, + .only_reg, .only_stack => |loc_pref| loc_pref, + }; + var maybe_prev_loc: ?Location = null; + const loc: Location, var full = loc: { + // Try to reuse existing location + if (vi.location(isel)) |loc| { + maybe_prev_loc = loc; + switch (loc) { + .register => |loc_ra| if (opts.offset == 0 and (opts.reg_mod == .undef or opts.reg_mod == loc_ra.mod)) { + switch (loc_pref) { + .none, .prefer_reg, .only_reg, .prefer_stack => break :loc .{ loc, false }, + .only_stack => {}, + } + }, + .stack_slot => switch (loc_pref) { + .none, .prefer_stack, .only_stack => break :loc .{ loc, true }, + .prefer_reg, .only_reg => {}, + }, + } + } + if (loc_pref != .only_stack and loc_pref != .prefer_stack) { + // Try to allocate hint RA + if (opts.hint_ra.reg != Register.zero) { + if (isel.live_registers.get(opts.hint_ra.reg) == .free) { + isel.saved_registers.insert(opts.hint_ra.reg); + break :loc .{ .{ .register = opts.hint_ra }, false }; + } + } + // Try to allocate a register + if (opts.reg_mod == .undef or opts.reg_mod == vi.hintModifier(isel)) { + if (try vi.allocRegister(isel)) |ra| + break :loc .{ .{ .register = ra }, false }; + } else try_alloc: { + const reg = isel.allocReg(opts.reg_mod.class()) catch break :try_alloc; + break :loc .{ .{ .register = .{ .reg = reg, .mod = opts.reg_mod } }, false }; + } + } + // Use existing stack slot if cannot mat into regs + switch (loc_pref) { + .none, .prefer_stack, .only_stack => {}, + .prefer_reg => if (maybe_prev_loc) |loc| break :loc .{ loc, true }, + .only_reg => unreachable, // too large to fit in registers + } + // Use hint stack slot + if (false) { + // TODO needs stack slot tracking + if (opts.hint_stack != .unallocated) { + break :loc .{ .{ .stack_slot = opts.hint_stack }, false }; + } + } + // Allocate on stack + break :loc .{ .{ .stack_slot = vi.allocStackSlot(isel) }, true }; + }; + if (maybe_prev_loc) |prev_loc| { + if (std.meta.eql(loc, prev_loc)) { + if (opts.extension != .garbage) { + try vi.reextendAdvanced(isel, vi.bitSize(isel), null, opts.extension); + } + _ = vi.takeLocation(isel); + } + } + if (loc.asRegister()) |reg| { + const live_vi = isel.live_registers.getPtr(reg); + switch (live_vi.*) { + _ => unreachable, + .allocating => {}, + .free => live_vi.* = .allocating, + } + full = opts.offset == 0 and mat_size == vi.size(isel); + } + if (full) { + tracking_log.debug("{f}[{d}..{d}] -> {f}[...] (mat, {t})", .{ vi, opts.offset, opts.offset + mat_size - 1, loc, opts.extension }); + } else { + tracking_log.debug("{f}[{d}..{d}] -> {f} (mat, {t})", .{ vi, opts.offset, opts.offset + mat_size - 1, loc, opts.extension }); + } + return .{ + .vi = vi, + .location = loc, + .offset = opts.offset, + .size = mat_size, + .extension = opts.extension, + .full = full, + }; + } + + fn matReg(vi: Value.Index, isel: *Select) !Mat { + return vi.mat(isel, .{ .pref = .only_reg }); + } + + fn matRegMod(vi: Value.Index, isel: *Select, mod: Register.Modifier) !Mat { + return vi.mat(isel, .{ .pref = .only_reg, .reg_mod = mod }); + } + + fn matIntRegZeroExt(vi: Value.Index, isel: *Select) !Mat { + return vi.mat(isel, .{ + .pref = .only_reg, + .reg_mod = .integer, + .extension = .zero_ext, + }); + } + + /// Moves the address of vi, plus offset, to ptr_reg + fn matAddress(vi: Value.Index, isel: *Select, ptr_reg: Register, offset: u64) !void { + wip_mir_log.debug(" | # address ${t} <- (&{f} + {d})", .{ ptr_reg, vi, offset }); + const offset_from_root, const root_vi = vi.valueRoot(isel); + const total_root_offset = offset_from_root + offset; + switch (root_vi.parent(isel)) { + .none => { + const value_mat = try vi.mat(isel, .{ .pref = .only_stack }); + const value_stack = value_mat.loc().stack_slot; + try isel.addImm(ptr_reg, value_stack.base, @as(i65, value_stack.offset) + offset); + try value_mat.finish(isel); + }, + .address => |addr_vi| { + const addr_mat = try addr_vi.mat(isel, .{ + .pref = .only_reg, + .hint_ra = .{ .mod = .integer, .reg = ptr_reg }, + }); + try isel.addImm(ptr_reg, addr_mat.reg(), total_root_offset); + try addr_mat.finish(isel); + }, + .value => unreachable, + .constant => |constant| { + const pt = isel.pt; + const zcu = pt.zcu; + + try isel.uav_relocs.append(zcu.gpa, .{ + .uav = .{ + .val = constant.toIntern(), + .orig_ty = (try pt.singleConstPtrType(constant.typeOf(zcu))).toIntern(), + }, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(total_root_offset), + }, + }); + try isel.emit(.@"addi.d"(ptr_reg, ptr_reg, 0)); + try isel.uav_relocs.append(zcu.gpa, .{ + .uav = .{ + .val = constant.toIntern(), + .orig_ty = (try pt.singleConstPtrType(constant.typeOf(zcu))).toIntern(), + }, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(total_root_offset), + }, + }); + try isel.emit(.pcalau12i(ptr_reg, 0)); + }, + } + } + + /// Stores a value to memory. + fn matStore( + vi: Value.Index, + isel: *Select, + base_reg: Register, + offset: u64, + opts: MemoryAccessOptions, + ) !void { + wip_mir_log.debug(" | # store {f} -> [${t}, #{d}]", .{ vi, base_reg, offset }); + _ = opts; + + const hint_stack: Indirect = if (std.math.cast(@FieldType(Indirect, "offset"), offset)) |stack_off| + .{ .base = base_reg, .offset = stack_off } + else + .unallocated; + const value_mat = try vi.mat(isel, .{ .hint_stack = hint_stack }); + try isel.moveLoc( + .{ .stack_slot = .{ .base = base_reg, .offset = 0 } }, + offset, + value_mat.loc(), + 0, + vi.size(isel), + .none, + ); + try value_mat.finish(isel); + } + + /// Stores a value in a certain layout, commonly used near basic block boundaries. + /// Reextends to PCS mode. + fn matLiveOut( + vi: Value.Index, + isel: *Select, + layout_vi: Value.Index, + opts: struct { + mode: enum { param, ret }, + }, + ) !void { + wip_mir_log.debug(" | # live out {f}, layout={f}, opts: regs={t}", .{ vi, layout_vi, opts.mode }); + + wip_mir_log.debug(" | # live out {f}: fill registers", .{vi}); + switch (opts.mode) { + .param => { + var layout_walk = layout_vi.walk(isel, .{}); + while (layout_walk.next()) |part_vi| { + if (part_vi.hintRegister(isel)) |part_reg| { + _ = try isel.fillReg(part_reg); + } + } + }, + .ret => { + var layout_walk = layout_vi.walk(isel, .{}); + while (layout_walk.next()) |part_vi| { + if (part_vi.hintRegister(isel)) |part_reg| { + assert(try isel.forgetReg(part_reg)); + _ = isel.lockReg(part_reg); + } + } + }, + } + + wip_mir_log.debug(" | # live out {f}: move values", .{vi}); + var layout_walk = layout_vi.walk(isel, .{}); + while (layout_walk.next()) |part_vi| { + if (part_vi.hintRegisterAlias(isel)) |part_ra| { + const part_offset = part_vi.offsetIn(isel, layout_vi); + const part_size = part_vi.size(isel); + + if (opts.mode == .ret) isel.freeReg(part_ra.reg); + const value_mat = try vi.mat(isel, .{ + .hint_ra = part_ra, + .offset = part_offset, + .size = @intCast(part_size), + .extension = part_vi.extension(isel), + }); + try isel.moveLoc(.{ .register = part_ra }, 0, value_mat.loc(), 0, part_size, .none); + try value_mat.finish(isel); + } + + if (part_vi.location(isel)) |layout_part_loc| { + const layout_part_stack = layout_part_loc.asStackSlot().?; + const part_offset = part_vi.offsetIn(isel, layout_vi); + const part_size = part_vi.size(isel); + + const value_mat = try vi.mat(isel, .{ + .hint_stack = layout_part_stack, + .offset = part_offset, + .size = @intCast(part_size), + .extension = part_vi.extension(isel), + }); + try isel.moveLoc(.{ .stack_slot = layout_part_stack }, 0, value_mat.loc(), 0, part_size, .none); + try value_mat.finish(isel); + } + } + } + + /// Moves the expected location to another location. + fn moveTo(vi: Value.Index, isel: *Select, src_loc: Location) !void { + if (src_loc.asRegister()) |src_reg| _ = try isel.fillReg(src_reg); + tracking_log.debug("{f} -> {f} (move to)", .{ vi, src_loc }); + if (vi.takeLocationMarkWritten(isel)) |dst_loc| + try isel.moveLoc(dst_loc, 0, src_loc, 0, vi.size(isel), .none); + if (vi.isSmall(isel)) { + vi.setSmallLocation(isel, src_loc); + if (src_loc.asRegister()) |src_reg| { + const src_live_vi = isel.live_registers.getPtr(src_reg); + assert(src_live_vi.* == .free); + src_live_vi.* = vi; + } + } else { + switch (src_loc) { + .register => unreachable, // large values cannot be moved into a register + .stack_slot => |src_stack| vi.setStackSlot(isel, src_stack), + } + } + } + + pub fn isSplitted(vi: Value.Index, isel: *Select) bool { + const value = vi.get(isel); + return value.flags.parts_len_minus_one != 0 or value.flags.splitted; + } + + pub fn split(vi: Value.Index, isel: *Select, force: bool) !void { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + + const value1 = vi.get(isel); + if (value1.flags.splitted and !force) return; + value1.flags.splitted = true; + if (value1.flags.parts_len_minus_one != 0) return; + var ty = vi.typeOf(isel) orelse { + if (force) + return vi.splitBlindly(isel) + else + return; + }; + + try isel.values.ensureUnusedCapacity(zcu.gpa, Value.max_parts); + try isel.value_types.ensureUnusedCapacity(zcu.gpa, Value.max_parts); + const value = vi.get(isel); + type_key: switch (ip.indexToKey(ty.toIntern())) { + else => return isel.fail("unimplemented Value.split({f})", .{isel.fmtType(ty)}), + .int_type => |int_type| { + const gpr_size = isel.gprSize(); + const gpr_bits = isel.gprBits(); + const parts_len = std.math.divCeil(u16, int_type.bits, gpr_bits) catch unreachable; + if (parts_len == 1) break :type_key; + vi.setParts(isel, @intCast(parts_len)); + for (0..parts_len) |part_index| + _ = try vi.addIntPart( + isel, + part_index * gpr_size, + gpr_size, + @intCast(@min(int_type.bits - (part_index * gpr_bits), gpr_bits)), + ); + }, + .ptr_type => |ptr_type| switch (ptr_type.flags.size) { + .one, .many, .c => break :type_key, + .slice => { + const ptr_size = isel.gprSize(); + vi.setParts(isel, 2); + _ = vi.addPart(isel, 0, ptr_size, ty.slicePtrFieldType(zcu)); + _ = vi.addPart(isel, ptr_size, ptr_size, .usize); + }, + }, + .opt_type => |child_type| if (ty.optionalReprIsPayload(zcu)) { + ty = .fromInterned(child_type); + continue :type_key ip.indexToKey(child_type); + } else { + const child_ty: ZigType = .fromInterned(child_type); + const child_size = child_ty.abiSize(zcu); + vi.setParts(isel, 2); + _ = vi.addPart(isel, 0, child_size, child_ty); + _ = vi.addPart(isel, child_size, 1, .bool); + }, + .array_type => |array_type| { + const full_len = array_type.lenIncludingSentinel(); + const child_ty: ZigType = .fromInterned(array_type.child); + const child_size = child_ty.abiSize(zcu); + const aligned_size = child_ty.abiAlignment(zcu).forward(child_size); + if (full_len == 1) { + continue :type_key ip.indexToKey(child_ty.ip_index); + } else if (full_len <= Value.max_parts) { + vi.setParts(isel, @intCast(full_len)); + for (0..@intCast(full_len)) |part_i| { + _ = vi.addPart( + isel, + @intCast(part_i * aligned_size), + child_size, + child_ty, + ); + } + } else { + // Construct a tree with minimum nodes and depth + // Minimum number of direct/indirect intermediate nodes to contain full_len leaf nodes + const min_intermediate_nodes = (std.math.divCeil(u64, full_len - 1, Value.max_parts - 1) catch unreachable) - 1; + assert(min_intermediate_nodes >= 1); + // Number of direct intermediate children + const intermediate_children = @min(Value.max_parts, min_intermediate_nodes); + // Number of direct leaf children + const leaf_children = @as(u64, Value.max_parts) - intermediate_children; + // Number of indirect leaf children + const indirect_leaf_children = full_len - leaf_children; + // Length of each intermediate children + const group_len = indirect_leaf_children / intermediate_children; + const group_tail = indirect_leaf_children % intermediate_children; + const tail_group_len = group_len + group_tail; + const group_size = group_len * child_size; + const tail_group_size = tail_group_len * child_size; + const group_aligned_size = group_len * aligned_size; + const group_ty: ZigType = if (intermediate_children == 1) undefined else try isel.pt.arrayType(.{ + .child = child_ty.ip_index, + .len = group_len, + }); + const tail_group_ty = if (array_type.sentinel == .none) try isel.pt.arrayType(.{ + .child = child_ty.ip_index, + .len = tail_group_len, + }) else try isel.pt.arrayType(.{ + .child = child_ty.ip_index, + .len = tail_group_len - 1, + .sentinel = array_type.sentinel, + }); + + vi.setParts(isel, Value.max_parts); + for (0..@intCast(leaf_children)) |part_i| { + _ = vi.addPart( + isel, + @intCast(part_i * aligned_size), + child_size, + child_ty, + ); + } + const leaf_offset = leaf_children * aligned_size; + for (0..@intCast(intermediate_children - 1)) |part_i| { + _ = vi.addPart( + isel, + @intCast(leaf_offset + (part_i * group_aligned_size)), + group_size, + group_ty, + ); + } + _ = vi.addPart( + isel, + @intCast(leaf_offset + ((intermediate_children - 1) * group_aligned_size)), + tail_group_size, + tail_group_ty, + ); + } + }, + .anyframe_type => unreachable, + .error_union_type => |error_union_type| { + const payload_ty: ZigType = .fromInterned(error_union_type.payload_type); + const error_set_offset = codegen.errUnionErrorOffset(payload_ty, zcu); + const payload_offset = codegen.errUnionPayloadOffset(payload_ty, zcu); + + var fields: [2]SplitStructField = undefined; + var part_len: usize = 0; + for (0..2) |field_index| { + const field_name: enum { error_set, payload } = switch (field_index) { + 0 => if (error_set_offset < payload_offset) .error_set else .payload, + 1 => if (error_set_offset < payload_offset) .payload else .error_set, + else => unreachable, + }; + const field_ty: ZigType, const field_begin = switch (field_name) { + .error_set => .{ .fromInterned(error_union_type.error_set_type), error_set_offset }, + .payload => .{ payload_ty, payload_offset }, + }; + const field_size = field_ty.abiSize(zcu); + if (field_size == 0) continue; + + fields[part_len] = .{ .offset = field_begin, .size = field_size }; + part_len += 1; + } + + try vi.splitStruct(isel, fields[0..part_len], .{ + .ty_size = vi.size(isel), + .ty_alignment = vi.alignment(isel), + .combine = false, + }); + }, + .simple_type => |simple_type| switch (simple_type) { + .f16, .f32, .f64, .f128, .c_longdouble => return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)}), + .f80 => continue :type_key .{ .int_type = .{ .signedness = .unsigned, .bits = 80 } }, + .usize, + .isize, + .c_char, + .c_short, + .c_ushort, + .c_int, + .c_uint, + .c_long, + .c_ulong, + .c_longlong, + .c_ulonglong, + => continue :type_key .{ .int_type = ty.intInfo(zcu) }, + .anyopaque, + .void, + .type, + .comptime_int, + .comptime_float, + .noreturn, + .null, + .undefined, + .enum_literal, + .adhoc_inferred_error_set, + .generic_poison, + => unreachable, + .bool => continue :type_key .{ .int_type = .{ .signedness = .unsigned, .bits = 1 } }, + .anyerror => continue :type_key .{ .int_type = .{ + .signedness = .unsigned, + .bits = zcu.errorSetBits(), + } }, + }, + .struct_type => { + const loaded_struct = ip.loadStructType(ty.toIntern()); + switch (loaded_struct.layout) { + .auto, .@"extern" => {}, + .@"packed" => { + ty = .fromInterned(loaded_struct.packed_backing_int_type); + continue :type_key ip.indexToKey(loaded_struct.packed_backing_int_type); + }, + } + + var field_end: u64 = 0; + var field_it = loaded_struct.iterateRuntimeOrder(ip); + var fields: []SplitStructField = try zcu.gpa.alloc(SplitStructField, loaded_struct.field_types.len); + defer zcu.gpa.free(fields); + var part_len: usize = 0; + while (field_it.next()) |field_index| { + const field_ty: ZigType = .fromInterned(loaded_struct.field_types.get(ip)[field_index]); + const field_begin = switch (loaded_struct.field_aligns.getOrNone(ip, field_index)) { + .none => field_ty.abiAlignment(zcu), + else => |field_align| field_align, + }.forward(field_end); + const field_size = field_ty.abiSize(zcu); + if (field_size == 0) continue; + field_end = field_begin + field_size; + + fields[part_len] = .{ .offset = field_begin, .size = field_size, .ty = field_ty }; + part_len += 1; + } + + try vi.splitStruct(isel, fields[0..part_len], .{ + .ty_size = vi.size(isel), + .ty_alignment = vi.alignment(isel), + .combine = true, + }); + }, + .tuple_type => |tuple_type| { + var field_end: u64 = 0; + var fields: []SplitStructField = try zcu.gpa.alloc(SplitStructField, tuple_type.types.len); + defer zcu.gpa.free(fields); + var part_len: usize = 0; + + for (tuple_type.types.get(ip), tuple_type.values.get(ip)) |field_type, field_value| { + if (field_value != .none) continue; + const field_ty: ZigType = .fromInterned(field_type); + const field_begin = field_ty.abiAlignment(zcu).forward(field_end); + const field_size = field_ty.abiSize(zcu); + if (field_size == 0) continue; + field_end = field_begin + field_size; + + fields[part_len] = .{ .offset = field_begin, .size = field_size, .ty = field_ty }; + part_len += 1; + } + + try vi.splitStruct(isel, fields[0..part_len], .{ + .ty_size = vi.size(isel), + .ty_alignment = vi.alignment(isel), + .combine = true, + }); + }, + .union_type => { + const loaded_union = ip.loadUnionType(ty.toIntern()); + switch (loaded_union.layout) { + .auto, .@"extern" => {}, + .@"packed" => continue :type_key .{ .int_type = .{ + .signedness = .unsigned, + .bits = @intCast(ty.bitSize(zcu)), + } }, + } + + const union_layout = ZigType.getUnionLayout(loaded_union, zcu); + const tag_offset = union_layout.tagOffset(); + const payload_offset = union_layout.payloadOffset(); + + var field_end: u64 = 0; + var fields: [2]SplitStructField = undefined; + var part_len: usize = 0; + + for (0..2) |field_index| { + const field_name: enum { tag, payload } = switch (field_index) { + 0 => if (tag_offset < payload_offset) .tag else .payload, + 1 => if (tag_offset < payload_offset) .payload else .tag, + else => unreachable, + }; + const field_size, const field_begin = switch (field_name) { + .tag => .{ union_layout.tag_size, tag_offset }, + .payload => .{ union_layout.payload_size, payload_offset }, + }; + if (field_size == 0) continue; + field_end = field_begin + field_size; + + fields[part_len] = .{ .offset = field_begin, .size = field_size }; + part_len += 1; + } + + try vi.splitStruct(isel, fields[0..part_len], .{ + .ty_size = vi.size(isel), + .ty_alignment = vi.alignment(isel), + .combine = false, + }); + }, + .opaque_type, .func_type => continue :type_key .{ .simple_type = .anyopaque }, + .enum_type => continue :type_key ip.indexToKey(ip.loadEnumType(ty.toIntern()).int_tag_type), + .error_set_type, + .inferred_error_set_type, + => continue :type_key .{ .simple_type = .anyerror }, + } + + if (force and value.flags.parts_len_minus_one == 0) try vi.splitBlindly(isel); + } + + pub fn splitBlindly(vi: Value.Index, isel: *Select) !void { + const value = vi.get(isel); + value.flags.splitted = true; + if (value.flags.parts_len_minus_one != 0) return; + + return isel.fail("splitBlindly unimplemented", .{}); + } + + const SplitStructField = struct { + offset: u64, + size: u64, + ty: ZigType = .void, + }; + + const SplitStructOpts = struct { + ty_size: u64, + ty_alignment: InternPool.Alignment, + combine: bool, + }; + + fn splitStruct(vi: Value.Index, isel: *Select, fields: []SplitStructField, opts: SplitStructOpts) !void { + const min_part_log2_stride: u5 = switch (opts.ty_size) { + 0...4 => 0, + 5...8 => 2, + 9...16 => 3, + else => 4, + }; + if (fields.len > Value.max_parts and + (std.math.divCeil(u64, opts.ty_size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts) + { + // fast path for structs with too many parts + return; + } + + // split parts with combination + const Part = struct { + offset: u64, + size: u64, + ty: ZigType, + vi: Value.Index, + subparts: Value.PartsLen, + }; + var new_parts: [Value.max_parts]Part = undefined; + var parts_len: Value.PartsLen = 0; + var field_end: u64 = 0; + for (fields) |*struct_field| { + const field_ty = struct_field.ty; + const field_begin = struct_field.offset; + const field_size = struct_field.size; + field_end = field_begin + field_size; + if (opts.combine and parts_len > 0) combine: { + const prev_part = &new_parts[parts_len - 1]; + const combined_size = field_end - prev_part.offset; + if (combined_size > @as(u64, 1) << @min( + min_part_log2_stride, + opts.ty_alignment.toLog2Units(), + @ctz(prev_part.offset), + )) break :combine; + prev_part.size = combined_size; + prev_part.ty = undefined; + prev_part.subparts += 1; + continue; + } + if (parts_len == Value.max_parts) return; + new_parts[parts_len] = .{ + .offset = field_begin, + .size = field_size, + .ty = field_ty, + .vi = undefined, + .subparts = 1, + }; + parts_len += 1; + } + if (parts_len <= 1) return; + vi.setParts(isel, parts_len); + for (new_parts[0..parts_len]) |*part| { + part.vi = vi.addPart( + isel, + part.offset, + part.size, + if (part.subparts == 1 and part.ty.ip_index != .void_type) part.ty else null, + ); + } + const last_part = new_parts[parts_len - 1]; + const remaining_size = opts.ty_size - last_part.offset - last_part.size; + if (remaining_size != 0) + _ = vi.addPart(isel, last_part.offset, remaining_size, null); + + // split combined parts + var part_index: Value.PartsLen = 0; + for (fields) |*struct_field| { + const field_ty = struct_field.ty; + const field_begin = struct_field.offset; + const field_size = struct_field.size; + + var new_part = &new_parts[part_index]; + while (new_part.offset + new_part.size <= field_begin) { + part_index += 1; + new_part = &new_parts[part_index]; + } + if (new_part.subparts == 1) continue; + if (!new_part.vi.hasParts(isel)) + new_part.vi.setParts(isel, new_part.subparts); + _ = new_part.vi.addPart( + isel, + field_begin - new_part.offset, + field_size, + if (field_ty.ip_index != .void_type) field_ty else null, + ); + } + } + }; + + pub const PartIterator = struct { + vi: Value.Index, + remaining: Value.PartsLen, + + fn initOne(vi: Value.Index) PartIterator { + return .{ .vi = vi, .remaining = 1 }; + } + + pub fn next(it: *PartIterator) ?Value.Index { + if (it.remaining == 0) return null; + it.remaining -= 1; + defer it.vi = @fromBackingInt(@backingInt(it.vi) + 1); + return it.vi; + } + + pub fn peek(it: PartIterator) ?Value.Index { + var it_mut = it; + return it_mut.next(); + } + + pub fn only(it: PartIterator) ?Value.Index { + return if (it.remaining == 1) it.vi else null; + } + }; + + const Mat = struct { + vi: Value.Index, + /// Position of the materialized part + offset: u64, + /// Size of the materialized part + size: u32, + /// Expected live-in extension mode + extension: Extension, + /// Register are locked. + location: Location, + /// Whether the location stores the whole value or the materialized part + full: bool, + + comptime { + if (!std.debug.runtime_safety) assert(@sizeOf(Mat) <= 32); + } + + const Error = error{ OutOfMemory, AlreadyReported }; + + pub fn ra(mat: Value.Mat) Register.Alias { + return mat.location.register; + } + + pub fn reg(mat: Value.Mat) Register { + return mat.location.register.reg; + } + + pub fn loc(mat: Value.Mat) Location { + return switch (mat.location) { + .register => |loc_ra| .{ .register = loc_ra }, + .stack_slot => |stack_slot| if (mat.full) + .{ .stack_slot = stack_slot.withOffset(@intCast(mat.offset)) } + else + .{ .stack_slot = stack_slot }, + }; + } + + fn finish(mat: Value.Mat, isel: *Select) Mat.Error!void { + const vi = mat.vi; + const value = vi.get(isel); + tracking_log.debug("{f}[{d}..{d}] <- {f} (mat finish)", .{ vi, mat.offset, mat.offset + mat.size - 1, mat.loc() }); + + if (mat.location.asRegister()) |mat_reg| + isel.freeReg(mat_reg); + + const offset_from_root, const root_vi = vi.valueRoot(isel); + switch (root_vi.parent(isel)) { + .none => { + // Try to set the location as expected + if (mat.full and vi.location(isel) == null) { + switch (value.flags.location_tag) { + .extreme => unreachable, + .small => { + vi.setSmallLocation(isel, mat.location); + vi.setExtension(isel, mat.extension); + if (mat.location.asRegister()) |loc_reg| + isel.live_registers.set(loc_reg, vi); + return; + }, + .large => switch (mat.location) { + .stack_slot => |stack_slot| { + value.location_payload.large.stack_slot = stack_slot; + try vi.reextendAdvanced(isel, vi.bitSize(isel), mat.extension, vi.extension(isel)); + return; + }, + else => {}, + }, + } + } + + // Initialize a location and copy + if (vi.location(isel) == null) { + switch (value.flags.location_tag) { + .extreme => unreachable, + .small => { + const new_ra = (try vi.allocRegister(isel)).?; + vi.setSmallLocation(isel, .{ .register = new_ra }); + isel.live_registers.set(new_ra.reg, vi); + }, + .large => value.location_payload.large.stack_slot = vi.allocStackSlot(isel), + } + } + switch (value.flags.location_tag) { + .extreme => unreachable, + .small => {}, + .large => { + try vi.reextendAdvanced(isel, vi.bitSize(isel), mat.extension, vi.extension(isel)); + }, + } + const vi_loc = vi.location(isel).?; + const maybe_loc_reg = vi_loc.asRegister(); + if (maybe_loc_reg) |loc_reg| { + const loc_live = isel.live_registers.getPtr(loc_reg); + assert(loc_live.* == vi); + loc_live.* = .allocating; + } + vi_loc.markRegWritten(isel); + try isel.moveLoc( + mat.location, + if (mat.full) mat.offset else 0, + vi_loc, + mat.offset, + mat.size, + .preserved, + ); + if (maybe_loc_reg) |loc_reg| { + const loc_live = isel.live_registers.getPtr(loc_reg); + assert(loc_live.* == .allocating); + loc_live.* = vi; + } + }, + .value => unreachable, + .address => |addr_vi| { + try vi.reextendAdvanced(isel, vi.bitSize(isel), mat.extension, vi.extension(isel)); + + // reextend + reextend: { + const dst_ext = vi.extension(isel); + const src_ext = mat.extension; + if (dst_ext == src_ext or dst_ext == .garbage) break :reextend; + + const bit_size = vi.bitSize(isel); + if (bit_size == 0) break :reextend; + + switch (mat.location) { + .register => |loc_ra| { + const offset_fixup = if (mat.full) 0 else mat.offset; + const reg_bits = loc_ra.mod.bitSize(isel.target); + const unused_bits = reg_bits - @min(bit_size - (offset_fixup * 8), reg_bits); + try isel.fillUnusedBits(loc_ra.reg, loc_ra.reg, dst_ext, src_ext, @intCast(unused_bits)); + }, + .stack_slot => |stack| { + const total_size = vi.size(isel); + const unused_bits = (total_size * 8) - bit_size; + const reg_mod: Register.Modifier = if (vi.isSmall(isel)) vi.hintModifier(isel) else .integer; + const reg_class = reg_mod.class(); + const reg_size = reg_mod.byteSize(isel.target); + const reg_alignment: InternPool.Alignment = .fromByteUnits(reg_size); + const base_offset = @as(i65, stack.offset) - (if (mat.full) 0 else mat.offset); + + var offset = reg_alignment.backward(bit_size / 8); + const tmp_reg = try isel.allocRegForWrite(reg_class); + defer isel.freeReg(tmp_reg); + while (offset < total_size) { + const part_size = @min(reg_size, total_size - offset); + defer offset += part_size; + + try isel.storeReg(tmp_reg, part_size, stack.base, base_offset + offset); + try isel.fillUnusedBits(tmp_reg, tmp_reg, dst_ext, src_ext, @intCast(unused_bits)); + try isel.loadReg(tmp_reg, part_size, vi.extension(isel).signednessForLoad(), stack.base, base_offset + offset); + } + }, + } + } + + const addr_mat = try addr_vi.matIntRegZeroExt(isel); + assert(addr_mat.ra().mod == .integer); + try isel.moveLoc( + mat.location, + if (mat.full) mat.offset else 0, + .{ .stack_slot = .{ .base = addr_mat.reg(), .offset = 0 } }, + offset_from_root + mat.offset, + mat.size, + .none, + ); + try addr_mat.finish(isel); + }, + .constant => |constant| { + const mat_loc = mat.loc(); + mat_loc.markRegWritten(isel); + try isel.moveConstant(mat_loc, constant, offset_from_root + mat.offset, mat.size); + }, + } + } + }; + + /// DFS iterator over a sub-tree. + const Walk = struct { + isel: *Select, + root_vi: Value.Index, + next_vi: Value.Index, + opts: Options, + + const Options = packed struct { + /// Reversed order + reverse: bool = true, + /// Whether to include root nodes + root: bool = true, + /// Whether to include intermdiate nodes + /// (i.e. nodes that are not leaf vertexes) + intermdiate: bool = true, + /// Whether to include leaf vertexes + leaves: bool = true, + }; + + pub fn next(it: *Walk) ?Value.Index { + const isel = it.isel; + const opts = it.opts; + while (it.next_vi != .free) { + const node_vi = it.next_vi; + + // find next node + next_node: { + // go to the first child + if (node_vi.hasParts(isel)) { + it.next_vi = if (!opts.reverse) + node_vi.get(isel).parts + else last_child: { + const node_value = node_vi.get(isel); + break :last_child @fromBackingInt(@backingInt(node_value.parts) + node_value.flags.parts_len_minus_one); + }; + break :next_node; + } + if (node_vi.parentValue(isel) != null) { + var iter_vi = node_vi; + while (true) { + // go to the next sibling + const parent_vi = iter_vi.get(isel).parent_payload.value; + const parent_value = parent_vi.get(isel); + if (!opts.reverse) { + const last_sibling = @backingInt(parent_value.parts) + parent_value.flags.parts_len_minus_one; + if (@backingInt(iter_vi) < last_sibling) { + it.next_vi = @fromBackingInt(@backingInt(iter_vi) + 1); + break :next_node; + } + } else { + if (@backingInt(iter_vi) > @backingInt(parent_value.parts)) { + it.next_vi = @fromBackingInt(@backingInt(iter_vi) - 1); + break :next_node; + } + } + // return to ancestor's sibling + if (parent_value.flags.parent_tag == .value) + iter_vi = parent_vi + else + break; + } + } + it.next_vi = .free; + } + + // filter nodes + if (!it.opts.root and node_vi == it.root_vi) continue; + if (!it.opts.intermdiate and node_vi.hasParts(isel)) continue; + if (!it.opts.leaves and !node_vi.hasParts(isel)) continue; + return node_vi; + } + return null; + } + + pub fn skipChildren(it: *Walk, current_vi: Value.Index) void { + const isel = it.isel; + const current_value = current_vi.get(isel); + if (current_value.flags.parts_len_minus_one != 0) { + const last_part = @backingInt(current_value.parts) + current_value.flags.parts_len_minus_one; + it.next_vi = @fromBackingInt(last_part); + _ = it.next(); + } + } + + pub fn peek(it: Walk) ?Value.Index { + var it_mut = it; + return it_mut.next(); + } + }; +}; + +fn fail(isel: *Select, comptime format: []const u8, args: anytype) error{ OutOfMemory, AlreadyReported } { + @branchHint(.cold); + wip_mir_log.debug("codegen error: " ++ format, args); + return isel.pt.zcu.codegenFail(isel.nav_index, format, args); +} + +fn failUnimplemented(isel: *Select, comptime format: []const u8, args: anytype) error{ OutOfMemory, AlreadyReported }!void { + @branchHint(.cold); + if (debug_trap_unimplemented_code) { + const gpa = isel.pt.zcu.gpa; + + const msg = try std.fmt.allocPrintSentinel(gpa, format, args, 0); + defer gpa.free(msg); + wip_mir_log.err("{s}", .{msg}); + try isel.emit(.@"break"(0xaa)); + try isel.moveDebugString(.r22, msg); + } else return isel.fail(format, args); +} + +fn moveDebugString(isel: *Select, reg: Register, msg: [:0]const u8) error{ OutOfMemory, AlreadyReported }!void { + @branchHint(.cold); + assert(debug_trap_unimplemented_code); + + const pt = isel.pt; + const zcu = pt.zcu; + const ip = &zcu.intern_pool; + const gpa = zcu.gpa; + + const msg_ty = try pt.arrayType(.{ + .len = msg.len, + .child = .u8_type, + .sentinel = .zero_u8, + }); + const msg_str = try ip.getOrPutString(gpa, zcu.comp.io, pt.tid, msg, .maybe_embedded_nulls); + const msg_val = try pt.intern(.{ .aggregate = .{ + .ty = msg_ty.ip_index, + .storage = .{ .bytes = msg_str }, + } }); + const msg_ptr = try pt.intern(.{ .ptr = .{ + .ty = .manyptr_const_u8_sentinel_0_type, + .base_addr = .{ .uav = .{ + .val = msg_val, + .orig_ty = .manyptr_const_u8_sentinel_0_type, + } }, + .byte_offset = 0, + } }); + try isel.moveConstant( + .{ .register = .{ .reg = reg, .mod = .integer } }, + .fromInterned(msg_ptr), + 0, + isel.gprSize(), + ); +} + +pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + const gpa = zcu.gpa; + const air_tags = isel.air.instructions.items(.tag); + const air_data = isel.air.instructions.items(.data); + const initial_def_order_len = isel.def_order.count(); + + for (air_body) |air_inst_index| { + switch (air_tags[@backingInt(air_inst_index)]) { + else => |air_tag| return isel.fail("unimplemented analyze for {t}", .{air_tag}), + .arg, + .ret_addr, + .frame_addr, + .err_return_trace, + .save_err_return_trace_index, + .runtime_nav_ptr, + .c_va_start, + => { + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .add, + .add_safe, + .add_optimized, + .add_wrap, + .add_sat, + .sub, + .sub_safe, + .sub_optimized, + .sub_wrap, + .sub_sat, + .mul, + .mul_safe, + .mul_optimized, + .mul_wrap, + .mul_sat, + .div_float, + .div_float_optimized, + .div_trunc, + .div_trunc_optimized, + .div_floor, + .div_floor_optimized, + .div_exact, + .div_exact_optimized, + .rem, + .rem_optimized, + .mod, + .mod_optimized, + .max, + .min, + .bit_and, + .bit_or, + .shr, + .shr_exact, + .shl, + .shl_exact, + .shl_sat, + .xor, + .cmp_lt, + .cmp_lt_optimized, + .cmp_lte, + .cmp_lte_optimized, + .cmp_eq, + .cmp_eq_optimized, + .cmp_gte, + .cmp_gte_optimized, + .cmp_gt, + .cmp_gt_optimized, + .cmp_neq, + .cmp_neq_optimized, + .array_elem_val, + .slice_elem_val, + .ptr_elem_val, + => { + const bin_op = air_data[@backingInt(air_inst_index)].bin_op; + + try isel.analyzeUse(bin_op.lhs); + try isel.analyzeUse(bin_op.rhs); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .ptr_add, + .ptr_sub, + .add_with_overflow, + .sub_with_overflow, + .mul_with_overflow, + .shl_with_overflow, + .slice, + .slice_elem_ptr, + .ptr_elem_ptr, + => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const bin_op = isel.air.extraData(Air.Bin, ty_pl.payload).data; + + try isel.analyzeUse(bin_op.lhs); + try isel.analyzeUse(bin_op.rhs); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .alloc => { + const ty = air_data[@backingInt(air_inst_index)].ty; + + isel.stack_align = isel.stack_align.maxStrict(ty.ptrAlignment(zcu)); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .inferred_alloc, + .inferred_alloc_comptime, + .wasm_memory_size, + .wasm_memory_grow, + .work_item_id, + .work_group_size, + .work_group_id, + => unreachable, + .ret, .ret_safe, .ret_load => { + const un_op = air_data[@backingInt(air_inst_index)].un_op; + isel.returns = true; + + assert(isel.active_blocks.keys()[0] == Block.main); + + try isel.analyzeUse(un_op); + }, + .ret_ptr => { + const ty = air_data[@backingInt(air_inst_index)].ty; + + if (isel.live_values.get(Block.main)) |ret_vi| { + switch (ret_vi.parent(isel)) { + .none => isel.stack_align = isel.stack_align.maxStrict(ty.ptrAlignment(zcu)), + .value, .constant => unreachable, + .address => |address_vi| try isel.live_values.putNoClobber(gpa, air_inst_index, address_vi.ref(isel)), + } + if (ret_vi.stackSlot(isel) != null) + isel.stack_align = isel.stack_align.maxStrict(ty.ptrAlignment(zcu)); + } + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .assembly => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.Asm, ty_pl.payload); + const operands: []const Air.Inst.Ref = @ptrCast(isel.air.extra.items[extra.end..][0 .. extra.data.flags.outputs_len + extra.data.inputs_len]); + + for (operands) |operand| if (operand != .none) try isel.analyzeUse(operand); + if (ty_pl.ty != .void_type) try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .not, + .clz, + .ctz, + .popcount, + .byte_swap, + .bit_reverse, + .abs, + .load, + .fptrunc, + .fpext, + .int_cast, + .int_cast_safe, + .trunc, + .optional_payload, + .optional_payload_ptr, + .optional_payload_ptr_set, + .wrap_optional, + .unwrap_errunion_payload, + .unwrap_errunion_err, + .unwrap_errunion_payload_ptr, + .unwrap_errunion_err_ptr, + .errunion_payload_ptr_set, + .wrap_errunion_payload, + .wrap_errunion_err, + .struct_field_ptr_index_0, + .struct_field_ptr_index_1, + .struct_field_ptr_index_2, + .struct_field_ptr_index_3, + .get_union_tag, + .ptr_slice_len_ptr, + .ptr_slice_ptr_ptr, + .array_to_slice, + .int_from_float, + .int_from_float_optimized, + .int_from_float_safe, + .int_from_float_optimized_safe, + .float_from_int, + .splat, + .error_set_has_value, + .addrspace_cast, + .c_va_arg, + .c_va_copy, + .bit_cast, + .ptr_cast, + .ptr_from_int, + .int_from_ptr, + .error_cast, + .error_from_int, + .int_from_error, + .union_from_enum, + => { + const ty_op = air_data[@backingInt(air_inst_index)].ty_op; + + try isel.analyzeUse(ty_op.operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .loop => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.Block, ty_pl.payload); + + try isel.active_loops.append(gpa, @fromBackingInt(@intCast(isel.loops.count()))); + try isel.loops.putNoClobber(gpa, air_inst_index, .{ + .def_order = @intCast(isel.def_order.count()), + .outer_live = 0, + .repeat_list = undefined, + }); + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + assert(isel.active_loops.pop().?.inst(isel) == air_inst_index); + }, + .repeat, .trap, .unreach => {}, + .br => { + const br = air_data[@backingInt(air_inst_index)].br; + try isel.analyzeUse(br.operand); + }, + .breakpoint, .dbg_stmt, .dbg_empty_stmt, .dbg_var_ptr, .dbg_var_val, .dbg_arg_inline, .c_va_end => {}, + .sqrt, + .sin, + .cos, + .tan, + .exp, + .exp2, + .log, + .log2, + .log10, + .floor, + .ceil, + .round, + .trunc_float, + .neg, + .neg_optimized, + .is_null, + .is_non_null, + .is_null_ptr, + .is_non_null_ptr, + .is_err, + .is_non_err, + .is_err_ptr, + .is_non_err_ptr, + .is_named_enum_value, + .tag_name, + .error_name, + => { + const un_op = air_data[@backingInt(air_inst_index)].un_op; + + try isel.analyzeUse(un_op); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .cmp_vector, .cmp_vector_optimized => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.VectorCmp, ty_pl.payload).data; + + try isel.analyzeUse(extra.lhs); + try isel.analyzeUse(extra.rhs); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .store, + .store_safe, + .set_union_tag, + .memset, + .memset_safe, + .memcpy, + .memmove, + .atomic_store_unordered, + .atomic_store_monotonic, + .atomic_store_release, + .atomic_store_seq_cst, + => { + const bin_op = air_data[@backingInt(air_inst_index)].bin_op; + + try isel.analyzeUse(bin_op.lhs); + try isel.analyzeUse(bin_op.rhs); + }, + .struct_field_ptr, .agg_field_val => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.StructField, ty_pl.payload).data; + + try isel.analyzeUse(extra.struct_operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .aggregate_init => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const elements: []const Air.Inst.Ref = @ptrCast(isel.air.extra.items[ty_pl.payload..][0..@intCast(ty_pl.ty.toType().arrayLen(zcu))]); + + for (elements) |element| try isel.analyzeUse(element); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .union_init => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.UnionInit, ty_pl.payload).data; + + try isel.analyzeUse(extra.init); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .prefetch => { + const prefetch = air_data[@backingInt(air_inst_index)].prefetch; + try isel.analyzeUse(prefetch.ptr); + }, + .field_parent_ptr => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.FieldParentPtr, ty_pl.payload).data; + + try isel.analyzeUse(extra.field_ptr); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .set_err_return_trace => { + const un_op = air_data[@backingInt(air_inst_index)].un_op; + try isel.analyzeUse(un_op); + }, + inline .block, .dbg_inline_block => |air_tag| { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(switch (air_tag) { + else => comptime unreachable, + .block => Air.Block, + .dbg_inline_block => Air.DbgInlineBlock, + }, ty_pl.payload); + const result_ty = ty_pl.ty.toInterned().?; + + if (result_ty == .noreturn_type) { + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + break; + } + + assert(!(try isel.active_blocks.getOrPut(gpa, air_inst_index)).found_existing); + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + const block_entry = isel.active_blocks.pop().?; + assert(block_entry.key == air_inst_index); + + if (result_ty != .void_type) try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .call, + .call_always_tail, + .call_never_tail, + .call_never_inline, + => { + const pl_op = air_data[@backingInt(air_inst_index)].pl_op; + const extra = isel.air.extraData(Air.Call, pl_op.payload); + const args: []const Air.Inst.Ref = @ptrCast(isel.air.extra.items[extra.end..][0..extra.data.args_len]); + isel.saved_registers.insert(.ra); + const callee_ty = isel.air.typeOf(pl_op.operand, ip); + const func_info = switch (ip.indexToKey(callee_ty.toIntern())) { + else => unreachable, + .func_type => |func_type| func_type, + .ptr_type => |ptr_type| ip.indexToKey(ptr_type.child).func_type, + }; + + try isel.analyzeUse(pl_op.operand); + var cc_it: CallAbiIterator = .{ .isel = isel, .cc = &func_info.cc }; + + const ret_ty = isel.air.typeOfIndex(air_inst_index, ip); + if (try cc_it.resolve(ret_ty, true)) |ret_vi| { + tracking_log.debug("{f} <- %{d} (call return)", .{ ret_vi, @backingInt(air_inst_index) }); + switch (ret_vi.parent(isel)) { + .none => {}, + .value, .constant => unreachable, + .address => |address_vi| { + defer address_vi.deref(isel); + const ret_value = ret_vi.get(isel); + ret_value.flags.parent_tag = .none; + ret_value.parent_payload = .{ .none = {} }; + }, + } + try isel.live_values.putNoClobber(gpa, air_inst_index, ret_vi); + + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + } + + for (args) |arg| { + { + const restore_values_len = isel.values.items.len; + defer isel.values.shrinkRetainingCapacity(restore_values_len); + defer isel.value_types.shrinkRetainingCapacity(restore_values_len); + + const param_ty = isel.air.typeOf(arg, ip); + const param_vi = try cc_it.resolve(param_ty, false) orelse continue; + defer param_vi.deref(isel); + + const passed_vi = switch (param_vi.parent(isel)) { + .none => param_vi, + .value, .constant => unreachable, + .address => |address_vi| address_vi, + }; + if (passed_vi.stackSlot(isel)) |stack_slot| { + assert(stack_slot.base == Register.sp); + isel.stack_size = @max( + isel.stack_size, + stack_slot.offset + @as(u24, @intCast(passed_vi.size(isel))), + ); + } + } + + try isel.analyzeUse(arg); + } + }, + .cond_br => { + const pl_op = air_data[@backingInt(air_inst_index)].pl_op; + const extra = isel.air.extraData(Air.CondBr, pl_op.payload); + + try isel.analyzeUse(pl_op.operand); + + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.then_body_len])); + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end + extra.data.then_body_len ..][0..extra.data.else_body_len])); + }, + .switch_br => { + const switch_br = isel.air.unwrapSwitch(air_inst_index); + + try isel.analyzeUse(switch_br.operand); + + var cases_it = switch_br.iterateCases(); + while (cases_it.next()) |case| try isel.analyze(case.body); + if (switch_br.else_body_len > 0) try isel.analyze(cases_it.elseBody()); + }, + .loop_switch_br => { + const switch_br = isel.air.unwrapSwitch(air_inst_index); + + try isel.active_loops.append(gpa, @fromBackingInt(@intCast(isel.loops.count()))); + try isel.loops.putNoClobber(gpa, air_inst_index, .{ + .def_order = @intCast(isel.def_order.count()), + .outer_live = 0, + .repeat_list = undefined, + }); + + var cases_it = switch_br.iterateCases(); + while (cases_it.next()) |case| try isel.analyze(case.body); + if (switch_br.else_body_len > 0) try isel.analyze(cases_it.elseBody()); + + assert(isel.active_loops.pop().?.inst(isel) == air_inst_index); + }, + .switch_dispatch => { + const br = air_data[@backingInt(air_inst_index)].br; + try isel.analyzeUse(br.operand); + }, + .slice_ptr => { + const ty_op = air_data[@backingInt(air_inst_index)].ty_op; + + try isel.analyzeUse(ty_op.operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + + const slice_vi = try isel.use(ty_op.operand); + const ptr_part_vi = try slice_vi.partExact(isel, 0, 8); + try isel.live_values.putNoClobber(gpa, air_inst_index, ptr_part_vi.ref(isel)); + }, + .slice_len => { + const ty_op = air_data[@backingInt(air_inst_index)].ty_op; + + try isel.analyzeUse(ty_op.operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + + const slice_vi = try isel.use(ty_op.operand); + const len_part_vi = try slice_vi.partExact(isel, 8, 8); + try isel.live_values.putNoClobber(gpa, air_inst_index, len_part_vi.ref(isel)); + }, + .reduce, .reduce_optimized => { + const reduce = air_data[@backingInt(air_inst_index)].reduce; + + try isel.analyzeUse(reduce.operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .shuffle_one => { + const extra = isel.air.unwrapShuffleOne(zcu, air_inst_index); + + try isel.analyzeUse(extra.operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .shuffle_two => { + const extra = isel.air.unwrapShuffleTwo(zcu, air_inst_index); + + try isel.analyzeUse(extra.operand_a); + try isel.analyzeUse(extra.operand_b); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .@"try", .try_cold => { + const pl_op = air_data[@backingInt(air_inst_index)].pl_op; + const extra = isel.air.extraData(Air.Try, pl_op.payload); + + try isel.analyzeUse(pl_op.operand); + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .try_ptr, .try_ptr_cold => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.TryPtr, ty_pl.payload); + + try isel.analyzeUse(extra.data.ptr); + try isel.analyze(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .cmpxchg_weak, .cmpxchg_strong => { + const ty_pl = air_data[@backingInt(air_inst_index)].ty_pl; + const extra = isel.air.extraData(Air.Cmpxchg, ty_pl.payload).data; + + try isel.analyzeUse(extra.ptr); + try isel.analyzeUse(extra.expected_value); + try isel.analyzeUse(extra.new_value); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .atomic_load => { + const atomic_load = air_data[@backingInt(air_inst_index)].atomic_load; + + try isel.analyzeUse(atomic_load.ptr); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + .atomic_rmw => { + const pl_op = air_data[@backingInt(air_inst_index)].pl_op; + const extra = isel.air.extraData(Air.AtomicRmw, pl_op.payload).data; + + try isel.analyzeUse(extra.operand); + try isel.def_order.putNoClobber(gpa, air_inst_index, {}); + }, + } + } + isel.def_order.shrinkRetainingCapacity(initial_def_order_len); +} + +fn analyzeUse(isel: *Select, air_ref: Air.Inst.Ref) !void { + const air_inst_index = air_ref.toIndex() orelse return; + const def_order_index = isel.def_order.getIndex(air_inst_index).?; + + // Loop liveness + var active_loop_index = isel.active_loops.items.len; + while (active_loop_index > 0) { + const prev_active_loop_index = active_loop_index - 1; + const active_loop = isel.active_loops.items[prev_active_loop_index]; + if (def_order_index >= active_loop.get(isel).def_order) break; + active_loop_index = prev_active_loop_index; + } + if (active_loop_index < isel.active_loops.items.len) { + const active_loop = isel.active_loops.items[active_loop_index]; + const loop_live_gop = + try isel.loop_outer_live.set.getOrPut(isel.pt.zcu.gpa, .{ active_loop, air_inst_index }); + if (!loop_live_gop.found_existing) active_loop.get(isel).outer_live += 1; + } +} + +pub fn finishAnalysis(isel: *Select) !void { + const gpa = isel.pt.zcu.gpa; + + // Loop liveness + if (isel.loops.count() > 0) { + try isel.loops.ensureUnusedCapacity(gpa, 1); + + const loop_live_len: u32 = @intCast(isel.loop_outer_live.set.count()); + if (loop_live_len > 0) { + try isel.loop_outer_live.list.resize(gpa, loop_live_len); + + // prefix sum + const loops = isel.loops.values(); + for (loops[1..], loops[0 .. loops.len - 1]) |*loop, prev_loop| loop.outer_live += prev_loop.outer_live; + assert(loops[loops.len - 1].outer_live == loop_live_len); + + for (isel.loop_outer_live.set.keys()) |entry| { + const loop, const inst = entry; + const loop_live = &loop.get(isel).outer_live; + loop_live.* -= 1; + isel.loop_outer_live.list.items[loop_live.*] = inst; + } + assert(loops[0].outer_live == 0); + } + + const invalid_gop = isel.loops.getOrPutAssumeCapacity(Loop.invalid); + assert(!invalid_gop.found_existing); + invalid_gop.value_ptr.* = .{ + .def_order = undefined, + .outer_live = loop_live_len, + .repeat_list = undefined, + }; + } + + assert(isel.active_blocks.count() == 1 and isel.active_blocks.keys()[0] == Select.Block.main); + assert(isel.active_loops.items.len == 0); +} + +pub fn verify(isel: *Select, check_values: bool) void { + if (!std.debug.runtime_safety) return; + assert(isel.active_blocks.count() == 1 and isel.active_blocks.keys()[0] == Select.Block.main); + assert(isel.active_loops.items.len == 0); + assert(isel.values.items.len == isel.value_types.items.len); + + // Verify register state + var live_reg_it = isel.live_registers.iterator(); + while (live_reg_it.next()) |live_reg_entry| switch (live_reg_entry.value.*) { + _ => { + tracking_log.err("{f}: still using ${t}", .{ live_reg_entry.value.*, live_reg_entry.key }); + isel.dumpValues(.all); + unreachable; + }, + .allocating, .free => {}, + }; + + // Check values state + if (!check_values) return; + for (isel.values.items, 0..) |value, vi_i| { + const vi: Value.Index = @fromBackingInt(@as(@typeInfo(Value.Index).@"enum".tag_type, @intCast(vi_i))); + if (value.refs != 0) { + tracking_log.err("{f}: still referenced", .{vi}); + isel.dumpValues(.all); + unreachable; + } + if (value.flags.parent_tag == .none and value.offset_from_parent != 0) { + tracking_log.err("{f}: values without none cannot have offset from parent", .{vi}); + isel.dumpValues(.all); + unreachable; + } + // Stack slot locations are allowed because layout values use them + if (vi.register(isel) != null) { + tracking_log.err("{f}: still has a location", .{vi}); + isel.dumpValues(.all); + unreachable; + } + } +} + +pub fn body(isel: *Select, air_body: []const Air.Inst.Index) error{ OutOfMemory, AlreadyReported }!void { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + const gpa = zcu.gpa; + + { + var live_reg_it = isel.live_registers.iterator(); + while (live_reg_it.next()) |live_reg_entry| switch (live_reg_entry.value.*) { + .allocating => { + tracking_log.err("${t} is allocated", .{live_reg_entry.key}); + isel.dumpValues(.all); + unreachable; + }, + _, .free => {}, + }; + } + + var air: struct { + isel: *Select, + tag_items: []const Air.Inst.Tag, + data_items: []const Air.Inst.Data, + body: []const Air.Inst.Index, + body_index: u32, + inst_index: Air.Inst.Index, + + fn tag(it: *@This(), inst_index: Air.Inst.Index) Air.Inst.Tag { + return it.tag_items[@backingInt(inst_index)]; + } + + fn data(it: *@This(), inst_index: Air.Inst.Index) Air.Inst.Data { + return it.data_items[@backingInt(inst_index)]; + } + + fn next(it: *@This()) ?Air.Inst.Tag { + if (it.body_index == 0) { + @branchHint(.unlikely); + return null; + } + it.body_index -= 1; + it.inst_index = it.body[it.body_index]; + wip_mir_log.debug("{f}", .{it.fmtAir(it.inst_index)}); + if (@import("builtin").mode == .debug) { + if (it.isel.live_values.get(it.inst_index)) |def_vi| { + wip_mir_log.debug(" <- {f}", .{it.isel.fmtValue(def_vi)}); + } + } + return it.tag(it.inst_index); + } + + fn fmtAir(it: @This(), inst: Air.Inst.Index) struct { + isel: *Select, + inst: Air.Inst.Index, + pub fn format(fmt_air: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void { + fmt_air.isel.air.writeInst(writer, fmt_air.inst, fmt_air.isel.pt, null); + } + } { + return .{ .isel = it.isel, .inst = inst }; + } + } = .{ + .isel = isel, + .tag_items = isel.air.instructions.items(.tag), + .data_items = isel.air.instructions.items(.data), + .body = air_body, + .body_index = @intCast(air_body.len), + .inst_index = undefined, + }; + while (air.next()) |air_tag| { + switch (air_tag) { + else => if (debug_trap_unimplemented_code) { + if (isel.live_values.fetchRemove(air.inst_index)) |vi| { + vi.value.deref(isel); + isel.wipeLocationDfs(vi.value); + } + try isel.failUnimplemented("unimplemented select for {s}", .{@tagName(air_tag)}); + } else return isel.fail("unimplemented select for {s}", .{@tagName(air_tag)}), + + // Misc + .unreach => {}, + .trap, .breakpoint => try isel.emit(.@"break"(0)), + + // Arguments & return + .arg => { + const arg_vi = isel.live_values.fetchRemove(air.inst_index).?.value; + defer arg_vi.deref(isel); + const layout_vi = isel.arg_layouts[@backingInt(air.inst_index)]; + layout_vi.deref(isel); + switch (layout_vi.parent(isel)) { + .none => try arg_vi.defLiveIn(isel, layout_vi, .{}), + .value, .constant => unreachable, + .address => |layout_addr_vi| { + switch (arg_vi.parent(isel)) { + else => unreachable, + .address => |arg_addr_vi| { + try arg_addr_vi.defLiveIn(isel, layout_addr_vi, .{}); + }, + } + }, + } + }, + .ret, .ret_safe => { + assert(isel.active_blocks.keys()[0] == Block.main); + try isel.active_blocks.values()[0].branch(isel); + if (isel.live_values.get(Block.main)) |ret_vi| { + const un_op = air.data(air.inst_index).un_op; + const src_vi = try isel.use(un_op); + switch (ret_vi.parent(isel)) { + .none => try src_vi.matLiveOut(isel, ret_vi, .{ .mode = .ret }), + .value, .constant => unreachable, + .address => |addr_vi| { + const addr_mat = try addr_vi.matIntRegZeroExt(isel); + try src_vi.matStore(isel, addr_mat.reg(), 0, .{}); + try addr_mat.finish(isel); + }, + } + } + }, + .ret_load => { + const un_op = air.data(air.inst_index).un_op; + const ptr_ty = isel.air.typeOf(un_op, ip); + const ptr_info = ptr_ty.ptrInfo(zcu); + if (ptr_info.packed_offset.host_size > 0) return isel.fail("packed load ret_load", .{}); + + assert(isel.active_blocks.keys()[0] == Block.main); + try isel.active_blocks.values()[0].branch(isel); + if (isel.live_values.get(Block.main)) |layout_vi| switch (layout_vi.parent(isel)) { + .none => { + const ptr_vi = try isel.use(un_op); + const ret_ty = ptr_ty.childType(zcu); + const ret_vi = try isel.initValue(ret_ty); + ret_vi.setParent(isel, .{ .address = ptr_vi }); + try ret_vi.matLiveOut(isel, layout_vi, .{ .mode = .ret }); + }, + .value, .constant => unreachable, + .address => {}, + }; + }, + + // Frame addresses + .ret_addr => if (isel.live_values.fetchRemove(air.inst_index)) |addr_vi| unused: { + defer addr_vi.value.deref(isel); + const addr_reg = try addr_vi.value.defRegMod(isel, .integer) orelse break :unused; + try isel.ldIncoming(addr_reg, .ra); + }, + .frame_addr => if (isel.live_values.fetchRemove(air.inst_index)) |addr_vi| unused: { + defer addr_vi.value.deref(isel); + const addr_reg = try addr_vi.value.defRegMod(isel, .integer) orelse break :unused; + isel.saved_registers.insert(.fp); + try isel.emit(.ori(addr_reg, .fp, 0)); + }, + + // Debugging + .dbg_stmt, .dbg_var_ptr, .dbg_var_val, .dbg_arg_inline => {}, + .dbg_empty_stmt => try isel.emit(.andi(.r0, .r0, 0)), + + // Control-flows + .dbg_inline_block => { + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.DbgInlineBlock, ty_pl.payload); + try isel.block(air.inst_index, ty_pl.ty.toType(), @ptrCast( + isel.air.extra.items[extra.end..][0..extra.data.body_len], + )); + }, + .block => { + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.Block, ty_pl.payload); + try isel.block(air.inst_index, ty_pl.ty.toType(), @ptrCast( + isel.air.extra.items[extra.end..][0..extra.data.body_len], + )); + }, + .loop => { + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.Block, ty_pl.payload); + const loops = isel.loops.values(); + const loop_index = isel.loops.getIndex(air.inst_index).?; + const loop = &loops[loop_index]; + + tracking_log.debug("{f}", .{isel.fmtLoopLive(air.inst_index)}); + loop.snapshot = try isel.takeLocationSnapshot(); + tracking_log.debug("loop snapshot taken:\n{f}", .{loop.snapshot}); + loop.repeat_list = Loop.empty_list; + + try isel.active_loops.append(gpa, @fromBackingInt(@intCast(loop_index))); + try isel.body(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + assert(isel.active_loops.pop().?.inst(isel) == air.inst_index); + + tracking_log.debug("loop %{d}: merge snapshot after loop body", .{@backingInt(air.inst_index)}); + try loop.snapshot.merge(isel); + loop.snapshot.deinit(isel); + loop.snapshot = .empty; + + tracking_log.debug("loop %{d}: kill registers written in loop body", .{@backingInt(air.inst_index)}); + try isel.fillRegsBatch(loop.written_regs, false); + // copy written registers to outer loops + isel.markRegsWritten(loop.written_regs); + + // relocate branches + var repeat_label = loop.repeat_list; + assert(repeat_label != Loop.empty_list); + while (repeat_label != Loop.empty_list) { + const instruction = &isel.instructions.items[repeat_label]; + const next_repeat_label = instruction.*; + instruction.* = .b(0, 0); + try isel.internal_relocs.append(gpa, .{ + .label = repeat_label, + .target = isel.instructions.items.len, + }); + repeat_label = @bitCast(next_repeat_label); + } + }, + .repeat => { + const repeat = air.data(air.inst_index).repeat; + try isel.loops.getPtr(repeat.loop_inst).?.branch(isel); + }, + .br => { + const br = air.data(air.inst_index).br; + try isel.active_blocks.getPtr(br.block_inst).?.branch(isel); + if (isel.live_values.get(br.block_inst)) |dst_vi| try dst_vi.defMove(isel, br.operand); + }, + .cond_br => { + const pl_op = air.data(air.inst_index).pl_op; + const extra = isel.air.extraData(Air.CondBr, pl_op.payload); + + try isel.body(@ptrCast(isel.air.extra.items[extra.end + extra.data.then_body_len ..][0..extra.data.else_body_len])); + const else_label = isel.instructions.items.len; + var else_snapshot = try isel.takeLocationSnapshot(); + defer else_snapshot.deinit(isel); + tracking_log.debug("if-body snapshot taken:\n{f}", .{else_snapshot}); + try isel.body(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.then_body_len])); + try else_snapshot.merge(isel); + + const cond_vi = try isel.use(pl_op.operand); + const cond_mat = try cond_vi.mat(isel, .{ + .pref = .only_reg, + .extension = .zero_ext, + }); + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = else_label, + }); + try isel.emit(.beqz(cond_mat.reg(), 0, 0)); + try cond_mat.finish(isel); + }, + .switch_br, .loop_switch_br => { + // TODO loop switch br and switch dispatch + if (air_tag == .loop_switch_br) try isel.failUnimplemented("TODO loop_switch_br", .{}); + const switch_br = isel.air.unwrapSwitch(air.inst_index); + + var final_case = true; + if (switch_br.else_body_len > 0) { + var cases_it = switch_br.iterateCases(); + while (cases_it.next()) |_| {} + try isel.body(cases_it.elseBody()); + assert(final_case); + final_case = false; + } + var cases_it = switch_br.iterateCases(); + while (cases_it.next()) |case| { + wip_mir_log.debug(" case {d}:", .{case.idx}); + + const next_label = isel.instructions.items.len; + var next_snapshot = try isel.takeLocationSnapshot(); + defer next_snapshot.deinit(isel); + tracking_log.debug("switch case snapshot taken:\n{f}", .{next_snapshot}); + try isel.body(case.body); + try next_snapshot.merge(isel); + if (final_case) { + final_case = false; + continue; + } + + const case_label = isel.instructions.items.len; + + var cond_vi = try isel.use(switch_br.operand); + const cond_mat = try cond_vi.mat(isel, .{ + .pref = .only_reg, + .reg_mod = .integer, + .extension = .zero_ext, + }); + + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = next_label, + }); + try isel.emit(.b(0, 0)); + + var case_range_index = case.ranges.len; + while (case_range_index > 0) { + case_range_index -= 1; + try isel.failUnimplemented("TODO switch_br range", .{}); + } + var case_item_index = case.items.len; + while (case_item_index > 0) { + case_item_index -= 1; + + const item_val: Constant = .fromInterned(case.items[case_item_index].toInterned().?); + var item_bigint_space: Constant.BigIntSpace = undefined; + const item_bigint = item_val.toBigInt(&item_bigint_space, zcu); + const item_int: i64 = if (item_bigint.positive) @bitCast( + item_bigint.toInt(u64) catch + return isel.fail("too big case item: {f}", .{isel.fmtConstant(item_val)}), + ) else item_bigint.toInt(i64) catch + return isel.fail("too big case item: {f}", .{isel.fmtConstant(item_val)}); + + const item_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(item_reg); + + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = case_label, + }); + try isel.emit(.beq(cond_mat.reg(), item_reg, 0)); + try isel.moveIntImm(item_reg, @bitCast(item_int)); + } + + try cond_mat.finish(isel); + } + }, + + // Procedure call + .call => { + const pl_op = air.data(air.inst_index).pl_op; + const extra = isel.air.extraData(Air.Call, pl_op.payload); + const args: []const Air.Inst.Ref = @ptrCast(isel.air.extra.items[extra.end..][0..extra.data.args_len]); + const callee_ty = isel.air.typeOf(pl_op.operand, ip); + const func_info = switch (ip.indexToKey(callee_ty.toIntern())) { + else => unreachable, + .func_type => |func_type| func_type, + .ptr_type => |ptr_type| ip.indexToKey(ptr_type.child).func_type, + }; + + var cc_it: CallAbiIterator = .{ .isel = isel, .cc = &func_info.cc }; + + // return + try call.prepareReturn(isel); + const ret_ty = isel.air.typeOfIndex(air.inst_index, ip); + const maybe_def_ret_vi = isel.live_values.fetchRemove(air.inst_index); + const ret_vi = try cc_it.resolve(ret_ty, true) orelse .free; + defer if (ret_vi != .free) ret_vi.deref(isel); + + var def_ret_stack: Value.Indirect = .unallocated; + if (maybe_def_ret_vi) |def_ret_vi| { + defer def_ret_vi.value.deref(isel); + assert(ret_vi != .free); + switch (ret_vi.parent(isel)) { + else => { + try def_ret_vi.value.defLiveIn(isel, ret_vi, .{}); + }, + .address => { + def_ret_stack = try def_ret_vi.value.defStack(isel) orelse ret_vi.allocStackSlot(isel); + }, + } + } + try call.finishReturn(isel); + + // call + try call.prepareCallee(isel); + if (pl_op.operand.toInterned()) |ct_callee| { + try isel.emit(.jirl(.ra, .ra, 0)); + try isel.nav_relocs.append(gpa, switch (ip.indexToKey(ct_callee)) { + else => unreachable, + inline .@"extern", .func => |func| .{ + .nav = func.owner_nav, + .reloc = .{ .label = @intCast(isel.instructions.items.len) }, + }, + .ptr => |ptr| .{ + .nav = ptr.base_addr.nav, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(ptr.byte_offset), + }, + }, + }); + try isel.emit(.pcaddu18i(.ra, 0)); + } else { + const callee_vi = try isel.use(pl_op.operand); + const callee_mat = try callee_vi.matIntRegZeroExt(isel); + try isel.emit(.jirl(.ra, callee_mat.reg(), 0)); + try callee_mat.finish(isel); + } + try call.finishCallee(isel); + + // params + try call.prepareParams(isel); + if (ret_vi != .free) switch (ret_vi.parent(isel)) { + else => {}, + .address => |addr_vi| try call.paramAddress(isel, def_ret_stack, addr_vi), + }; + for (args) |arg| { + const param_ty = isel.air.typeOf(arg, ip); + const param_vi = try cc_it.resolve(param_ty, false) orelse continue; + defer param_vi.deref(isel); + const arg_vi = try isel.use(arg); + try call.paramLiveOut(isel, arg_vi, param_vi); + } + try call.finishParams(isel); + }, + + // Stack allocation + .alloc, .ret_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |ptr_vi| unused: { + defer ptr_vi.value.deref(isel); + switch (air_tag) { + else => unreachable, + .alloc => {}, + .ret_ptr => if (isel.live_values.get(Block.main)) |ret_vi| switch (ret_vi.parent(isel)) { + .none => {}, + .value, .constant => unreachable, + .address => break :unused, + }, + } + const ptr_reg = try ptr_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const ty = air.data(air.inst_index).ty; + const slot_size = ty.childType(zcu).abiSize(zcu); + const slot_align = ty.ptrAlignment(zcu); + const slot_offset = slot_align.forward(isel.stack_size); + isel.stack_size = @intCast(slot_offset + slot_size); + + try isel.addImm(ptr_reg, .sp, slot_offset); + }, + .inferred_alloc, .inferred_alloc_comptime => unreachable, + + // Assembly + .assembly => { + const unwrapped_asm = isel.air.unwrapAsm(air.inst_index); + const inputs = unwrapped_asm.inputs; + + var as: Assemble = .{ .source = unwrapped_asm.source }; + defer as.deinit(gpa); + + var it = unwrapped_asm.iterateOutputs(); + while (it.next()) |output| { + const constraint = output.constraint; + const name = output.name; + + switch (output.operand) { + else => return isel.fail("invalid constraint: '{s}'", .{constraint}), + .none => { + const output_reg = output_reg: { + if (std.mem.startsWith(u8, constraint, "={") and std.mem.endsWith(u8, constraint, "}")) { + const output_reg = Register.parse(constraint["={".len .. constraint.len - "}".len]) orelse + return isel.fail("invalid constraint: '{s}'", .{constraint}); + assert(try isel.fillReg(output_reg)); + isel.markRegWritten(output_reg); + if (isel.live_values.fetchRemove(air.inst_index)) |output_vi| { + defer output_vi.value.deref(isel); + try output_vi.value.reextendToPcs(isel); + if (try output_vi.value.def(isel)) |output_loc| + try isel.moveLoc( + .{ .register = .{ .mod = .integer, .reg = output_reg } }, + 0, + output_loc, + 0, + output_vi.value.size(isel), + .none, + ); + } + break :output_reg output_reg; + } else if (std.mem.eql(u8, constraint, "=r")) { + if (isel.live_values.fetchRemove(air.inst_index)) |output_vi| { + defer output_vi.value.deref(isel); + try output_vi.value.reextendToPcs(isel); + break :output_reg try output_vi.value.defRegMod(isel, .integer) orelse try isel.allocRegForWrite(.int); + } else break :output_reg try isel.allocRegForWrite(.int); + } else return isel.fail("invalid constraint: '{s}'", .{constraint}); + }; + if (!std.mem.eql(u8, name, "_")) { + const arg_gop = try as.args.getOrPut(gpa, name); + if (arg_gop.found_existing) return isel.fail("duplicate output name: '{s}'", .{name}); + arg_gop.value_ptr.* = .{ .register = output_reg }; + } + }, + } + } + + const clobbers_val: Constant = .fromInterned(unwrapped_asm.clobbers); + const clobbers_ty = clobbers_val.typeOf(zcu); + var clobbers_bigint_buf: Constant.BigIntSpace = undefined; + const clobbers_bigint = clobbers_val.toBigInt(&clobbers_bigint_buf, zcu); + var clobbered_regs: RegisterSet = .empty; + for (0..clobbers_ty.structFieldCount(zcu)) |field_index| { + assert(clobbers_ty.fieldType(field_index, zcu).toIntern() == .bool_type); + const limb_bits = @bitSizeOf(std.math.big.Limb); + if (field_index / limb_bits >= clobbers_bigint.limbs.len) continue; // field is false + switch (@as(u1, @truncate(clobbers_bigint.limbs[field_index / limb_bits] >> @intCast(field_index % limb_bits)))) { + 0 => continue, // field is false + 1 => {}, // field is true + } + + const clobber_name = clobbers_ty.structFieldName(field_index, zcu).toSlice(ip).?; + if (std.mem.eql(u8, clobber_name, "memory")) continue; + if (std.mem.startsWith(u8, clobber_name, "fcsr")) continue; + const clobber_reg = Register.parse(clobber_name) orelse + return isel.fail("unable to parse clobber: '{s}'", .{clobber_name}); + if (clobbered_regs.contains(clobber_reg)) + return isel.fail("clobbered twice: '{t}'", .{clobber_reg}); + clobbered_regs.insert(clobber_reg); + } + try isel.fillRegsBatch(clobbered_regs, true); + isel.markRegsWritten(clobbered_regs); + + const InputMat = union(enum(u1)) { + reg: Register.Alias, + mat: Value.Mat, + }; + const input_mats = try gpa.alloc(InputMat, inputs.len); + defer gpa.free(input_mats); + var index: u32 = 0; + it = unwrapped_asm.iterateInputs(); + while (it.next()) |input| : (index += 1) { + const constraint = input.constraint; + const name = input.name; + const input_mat = &input_mats[index]; + + const input_vi = try isel.use(input.operand); + try input_vi.reextendToPcs(isel); + + // TODO support X constraint + if (std.mem.startsWith(u8, constraint, "{") and std.mem.endsWith(u8, constraint, "}")) { + const input_reg = Register.parse(constraint["{".len .. constraint.len - "}".len]) orelse + return isel.fail("invalid constraint: '{s}'", .{constraint}); + input_mat.* = .{ .reg = .{ .mod = .integer, .reg = input_reg } }; + } else if (std.mem.eql(u8, constraint, "r")) { + const input_value_mat = try input_vi.mat(isel, .{ + .pref = .only_reg, + .reg_mod = .integer, + .extension = if (input_vi.typeOf(isel)) |input_ty| + .pcsMode(isel, input_ty) + else + .zero_ext, + }); + input_mat.* = .{ .mat = input_value_mat }; + } else if (std.mem.eql(u8, name, "_")) { + input_mat.* = .{ .reg = .zero }; + } else return isel.fail("invalid constraint: '{s}'", .{constraint}); + + if (!std.mem.eql(u8, name, "_")) { + const arg_gop = try as.args.getOrPut(gpa, name); + if (arg_gop.found_existing) return isel.fail("duplicate input name: '{s}'", .{name}); + arg_gop.value_ptr.* = .{ .register = switch (input_mat.*) { + .reg => |input_ra| input_ra.reg, + .mat => |input_val_mat| input_val_mat.reg(), + } }; + } + } + + const asm_start = isel.instructions.items.len; + while (instruction: { + const line = as.nextLine(); + break :instruction as.parseLine(line) catch |err| switch (err) { + error.InvalidSyntax => { + if (debug_trap_unimplemented_code) { + wip_mir_log.err("unable to assemble: '{s}'", .{std.mem.trim( + u8, + line, + &std.ascii.whitespace, + )}); + break :instruction Instruction.@"break"(0xaa); + } else return isel.fail("unable to assemble: '{s}'", .{std.mem.trim( + u8, + line, + &std.ascii.whitespace, + )}); + }, + }; + }) |instruction| try isel.emit(instruction); + std.mem.reverse(Instruction, isel.instructions.items[asm_start..]); + + it = unwrapped_asm.iterateInputs(); + index = 0; + while (it.next()) |input| : (index += 1) { + const input_mat = &input_mats[index]; + const input_vi = try isel.use(input.operand); + switch (input_mat.*) { + .reg => |input_ra| { + const input_val_mat = try input_vi.mat(isel, .{ + .pref = .prefer_reg, + .hint_ra = input_ra, + }); + const input_val_loc = input_val_mat.loc(); + const dst_loc: Value.Location = .{ .register = input_ra }; + if (!std.meta.eql(input_val_loc, dst_loc)) { + dst_loc.markRegWritten(isel); + try isel.moveLoc(dst_loc, 0, input_val_loc, 0, input_ra.mod.byteSize(isel.target), .none); + } + try input_val_mat.finish(isel); + }, + .mat => |input_val_mat| try input_val_mat.finish(isel), + } + } + + var clobber_regs_it = clobbered_regs.iterator(); + while (clobber_regs_it.next()) |clobber_reg| isel.freeReg(clobber_reg); + }, + + // Arithmetic + .add, .add_safe, .add_optimized, .add_wrap, .sub, .sub_safe, .sub_optimized, .sub_wrap => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| { + defer res_vi.value.deref(isel); + + const bin_op = air.data(air.inst_index).bin_op; + const ty = isel.air.typeOf(bin_op.lhs, ip); + if (!ty.isRuntimeFloat()) try isel.addOrSubtract(ty, res_vi.value, switch (air_tag) { + else => unreachable, + .add, .add_safe, .add_wrap => .add, + .sub, .sub_safe, .sub_wrap => .sub, + }, try isel.use(bin_op.lhs), try isel.use(bin_op.rhs), .{ + .overflow = switch (air_tag) { + else => unreachable, + .add, .sub => .@"unreachable", + .add_safe, .sub_safe => .{ .panic = .integer_overflow }, + .add_wrap, .sub_wrap => .wrap, + }, + }) else return isel.fail("unimplemented float", .{}); + }, + .not => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| unused: { + defer res_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const src_vi = try isel.use(ty_op.operand); + const ty = ty_op.ty.toType(); + switch (ty.zigTypeTag(zcu)) { + .bool => { + // boolean not + try res_vi.value.reextend(isel, .zero_ext); + const res_reg = try res_vi.value.defRegMod(isel, .integer) orelse break :unused; + // TODO optimize fcc path + const src_mat = try src_vi.matIntRegZeroExt(isel); + const src_reg = src_mat.reg(); + try isel.emit(.xori(res_reg, src_reg, 1)); + try src_mat.finish(isel); + }, + .int => { + // bitwise not + var res_walk = res_vi.value.walk(isel, .{}); + const gpr_size = isel.gprSize(); + while (res_walk.next()) |res_part_vi| { + if (res_part_vi.size(isel) > gpr_size) continue; + res_walk.skipChildren(res_part_vi); + const res_part_ra = try res_part_vi.defReg(isel) orelse continue; + const src_part_mat = try src_vi.mat(isel, .{ + .offset = res_part_vi.offsetIn(isel, res_vi.value), + .size = @intCast(res_part_vi.size(isel)), + .pref = .only_reg, + .reg_mod = res_part_ra.mod, + }); + const src_part_reg = src_part_mat.reg(); + switch (res_part_ra.mod) { + .undef => unreachable, + .integer => try isel.emit(.nor(res_part_ra.reg, src_part_reg, .zero)), + else => return isel.fail("unimplemented not {t}", .{res_part_ra.mod}), + } + try src_part_mat.finish(isel); + } + }, + else => |ty_tag| return isel.fail("unimplemented not on {t}", .{ty_tag}), + } + }, + .trunc => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| { + defer res_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const src_vi = try isel.use(ty_op.operand); + const src_ty = ty_op.ty.toType(); + const src_bits = src_ty.bitSize(zcu); + try res_vi.value.reextendAdvanced( + isel, + src_bits, + src_vi.extension(isel), + res_vi.value.extension(isel), + ); + try res_vi.value.defCopy(isel, src_vi); + }, + .div_trunc, .div_trunc_optimized, .div_floor, .div_floor_optimized, .div_exact, .div_exact_optimized => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| unused: { + defer res_vi.value.deref(isel); + + const bin_op = air.data(air.inst_index).bin_op; + const ty = isel.air.typeOf(bin_op.lhs, ip); + if (!ty.isRuntimeFloat()) { + if (!ty.isAbiInt(zcu)) return isel.fail("bad {t} {f}", .{ air_tag, isel.fmtType(ty) }); + const int_info = ty.intInfo(zcu); + switch (int_info.bits) { + 0 => unreachable, + 1...64 => |bits| { + const res_reg = try res_vi.value.defRegMod(isel, .integer) orelse break :unused; + const lhs_vi = try isel.use(bin_op.lhs); + const rhs_vi = try isel.use(bin_op.rhs); + const mat_opts: Value.Index.MatOptions = .{ + .pref = .only_reg, + .reg_mod = .integer, + .extension = ext_mode: { + if (bits == 32 and isel.hasCpuFeature(.@"64bit") and isel.hasCpuFeature(.div32)) { + break :ext_mode .garbage; + } + break :ext_mode .fromSignedness(int_info.signedness); + }, + }; + const lhs_mat = try lhs_vi.mat(isel, mat_opts); + const rhs_mat = try rhs_vi.mat(isel, mat_opts); + const lhs_reg = lhs_mat.reg(); + const rhs_reg = rhs_mat.reg(); + + switch (bits) { + else => unreachable, + 1...32 => try isel.emit(switch (int_info.signedness) { + .signed => .@"div.w"(res_reg, lhs_reg, rhs_reg), + .unsigned => .@"div.wu"(res_reg, lhs_reg, rhs_reg), + }), + 33...64 => if (isel.hasCpuFeature(.@"64bit")) { + try isel.emit(switch (int_info.signedness) { + .signed => .@"div.d"(res_reg, lhs_reg, rhs_reg), + .unsigned => .@"div.du"(res_reg, lhs_reg, rhs_reg), + }); + } else return isel.fail("unimplemented 64bit division on LA32", .{}), + } + try rhs_mat.finish(isel); + try lhs_mat.finish(isel); + }, + else => try isel.failUnimplemented("too big {t} {f}", .{ air_tag, isel.fmtType(ty) }), + } + } else try isel.failUnimplemented("unimplemented float div", .{}); + }, + .bit_cast, + .ptr_cast, + .ptr_from_int, + .int_from_ptr, + .error_cast, + .error_from_int, + .int_from_error, + .union_from_enum, + => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| unused: { + defer dst_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const dst_ty = ty_op.ty.toType(); + const dst_tag = dst_ty.zigTypeTag(zcu); + const src_ty = isel.air.typeOf(ty_op.operand, ip); + const src_tag = src_ty.zigTypeTag(zcu); + + if ((dst_tag == .bool or dst_ty.isAbiInt(zcu)) and (src_tag == .bool or src_ty.isAbiInt(zcu))) { + const dst_int_info: std.builtin.Type.Int = if (dst_tag == .bool) .{ .signedness = .unsigned, .bits = 1 } else dst_ty.intInfo(zcu); + const src_int_info: std.builtin.Type.Int = if (src_tag == .bool) .{ .signedness = .unsigned, .bits = 1 } else src_ty.intInfo(zcu); + assert(dst_int_info.bits == src_int_info.bits); + if (dst_tag != .@"struct" and src_tag != .@"struct") { + try dst_vi.value.defMove(isel, ty_op.operand); + } else switch (dst_int_info.bits) { + 0 => unreachable, + 1...31, 33...63 => |bits| { + try dst_vi.value.reextendToGarbage(isel); + const dst_reg = try dst_vi.value.defRegMod(isel, .integer) orelse break :unused; + const src_vi = try isel.use(ty_op.operand); + const src_mat = try src_vi.matReg(isel); + try isel.fillUnusedBits( + dst_reg, + src_mat.reg(), + .fromSignedness(dst_int_info.signedness), + .fromSignedness(src_int_info.signedness), + @intCast(bits), + ); + try src_mat.finish(isel); + }, + 32, 64 => try dst_vi.value.defMove(isel, ty_op.operand), + else => return isel.fail("unimplemented {t} {f} {f}", .{ air_tag, isel.fmtType(dst_ty), isel.fmtType(src_ty) }), + } + } else if ((dst_ty.isPtrAtRuntime(zcu) or dst_ty.isAbiInt(zcu)) and (src_ty.isPtrAtRuntime(zcu) or src_ty.isAbiInt(zcu))) { + try dst_vi.value.defMove(isel, ty_op.operand); + } else if (dst_ty.isSliceAtRuntime(zcu) and src_ty.isSliceAtRuntime(zcu)) { + try dst_vi.value.defMove(isel, ty_op.operand); + } else if (dst_tag == .error_union and src_tag == .error_union) { + assert(dst_ty.errorUnionSet(zcu).hasRuntimeBits(zcu) == + src_ty.errorUnionSet(zcu).hasRuntimeBits(zcu)); + if (dst_ty.errorUnionPayload(zcu).toIntern() == src_ty.errorUnionPayload(zcu).toIntern()) { + try dst_vi.value.defMove(isel, ty_op.operand); + } else return isel.fail("bad {t} {f} {f}", .{ air_tag, isel.fmtType(dst_ty), isel.fmtType(src_ty) }); + } else if (dst_tag == .float and src_tag == .float) { + assert(dst_ty.floatBits(isel.target) == src_ty.floatBits(isel.target)); + try dst_vi.value.defMove(isel, ty_op.operand); + } else if (dst_ty.isAbiInt(zcu) and src_tag == .float) { + const dst_int_info = dst_ty.intInfo(zcu); + assert(dst_int_info.bits == src_ty.floatBits(isel.target)); + + try dst_vi.value.reextendToGarbage(isel); + const dst_reg = try dst_vi.value.defRegMod(isel, .fromFloating(dst_int_info.bits)) orelse break :unused; + const src_vi = try isel.use(ty_op.operand); + const src_mat = try src_vi.matReg(isel); + const src_reg = src_mat.reg(); + try isel.emit(switch (dst_int_info.bits) { + else => unreachable, + 32 => .@"movfr2gr.s"(dst_reg, src_reg), + 64 => .@"movfr2gr.d"(dst_reg, src_reg), + }); + try src_mat.finish(isel); + } else if (dst_tag == .float and src_ty.isAbiInt(zcu)) { + const src_int_info = src_ty.intInfo(zcu); + assert(dst_ty.floatBits(isel.target) == src_int_info.bits); + + try dst_vi.value.reextendToGarbage(isel); + const dst_reg = try dst_vi.value.defRegMod(isel, .fromFloating(src_int_info.bits)) orelse break :unused; + const src_vi = try isel.use(ty_op.operand); + const src_mat = try src_vi.matReg(isel); + const src_reg = src_mat.reg(); + try isel.emit(switch (src_int_info.bits) { + else => unreachable, + 32 => .@"movgr2fr.w"(dst_reg, src_reg), + 64 => .@"movfr2gr.d"(dst_reg, src_reg), + }); + try src_mat.finish(isel); + } else if (dst_ty.isAbiInt(zcu) and src_tag == .array and src_ty.childType(zcu).isAbiInt(zcu)) { + const dst_int_info = dst_ty.intInfo(zcu); + const src_child_int_info = src_ty.childType(zcu).intInfo(zcu); + const src_len = src_ty.arrayLenIncludingSentinel(zcu); + assert(dst_int_info.bits == src_child_int_info.bits * src_len); + const src_child_size = src_ty.childType(zcu).abiSize(zcu); + if (8 * src_child_size == src_child_int_info.bits) { + const src_vi = try isel.use(ty_op.operand); + try dst_vi.value.defCopy(isel, src_vi); + } else return isel.fail("bad {t} {f} {f}", .{ air_tag, isel.fmtType(dst_ty), isel.fmtType(src_ty) }); + } else if (dst_tag == .array and dst_ty.childType(zcu).isAbiInt(zcu) and src_ty.isAbiInt(zcu)) { + const dst_child_int_info = dst_ty.childType(zcu).intInfo(zcu); + const src_int_info = src_ty.intInfo(zcu); + const dst_len = dst_ty.arrayLenIncludingSentinel(zcu); + assert(dst_child_int_info.bits * dst_len == src_int_info.bits); + const dst_child_size = dst_ty.childType(zcu).abiSize(zcu); + if (8 * dst_child_size == dst_child_int_info.bits) { + const src_vi = try isel.use(ty_op.operand); + try dst_vi.value.defCopy(isel, src_vi); + } else return isel.fail("bad {t} {f} {f}", .{ air_tag, isel.fmtType(dst_ty), isel.fmtType(src_ty) }); + } else if (dst_tag == .array and dst_ty.childType(zcu).isAbiInt(zcu) and + src_tag == .array and src_ty.childType(zcu).isAbiInt(zcu)) + { + const dst_child_int_info = dst_ty.childType(zcu).intInfo(zcu); + const dst_len = dst_ty.arrayLenIncludingSentinel(zcu); + const src_child_int_info = src_ty.childType(zcu).intInfo(zcu); + const src_len = src_ty.arrayLenIncludingSentinel(zcu); + assert(dst_child_int_info.bits * dst_len == src_child_int_info.bits * src_len); + const dst_child_size = dst_ty.childType(zcu).abiSize(zcu); + const src_child_size = src_ty.childType(zcu).abiSize(zcu); + if (8 * dst_child_size == dst_child_int_info.bits and 8 * src_child_size == src_child_int_info.bits) { + const src_vi = try isel.use(ty_op.operand); + try dst_vi.value.defCopy(isel, src_vi); + } else return isel.fail("bad {t} {f} {f}", .{ air_tag, isel.fmtType(dst_ty), isel.fmtType(src_ty) }); + } else return isel.fail("unimplemented {t} {f} {f}", .{ air_tag, isel.fmtType(dst_ty), isel.fmtType(src_ty) }); + }, + .bit_and, .bit_or, .xor => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| { + defer res_vi.value.deref(isel); + + const bin_op = air.data(air.inst_index).bin_op; + + const lhs_vi = try isel.use(bin_op.lhs); + const rhs_vi = try isel.use(bin_op.rhs); + + const lhs_ext_mode = lhs_vi.extension(isel); + const rhs_ext_mode = rhs_vi.extension(isel); + try res_vi.value.reextend(isel, res_ext_mode: switch (air_tag) { + else => unreachable, + .bit_and => { + if (lhs_ext_mode == rhs_ext_mode) break :res_ext_mode lhs_ext_mode; + if (lhs_ext_mode == .zero_ext or rhs_ext_mode == .zero_ext) break :res_ext_mode .zero_ext; + break :res_ext_mode .garbage; + }, + .bit_or => if (lhs_ext_mode == rhs_ext_mode) lhs_ext_mode else .garbage, + .xor => .garbage, + }); + + var res_walk = res_vi.value.walk(isel, .{}); + const gpr_size = isel.gprSize(); + while (res_walk.next()) |res_part_vi| { + if (res_part_vi.size(isel) > gpr_size) continue; + res_walk.skipChildren(res_part_vi); + const part_offset = res_part_vi.offsetIn(isel, res_vi.value); + const part_size = res_part_vi.size(isel); + // TODO implement vectors + const res_part_ra = try res_part_vi.defReg(isel) orelse continue; + const res_part_reg = res_part_ra.reg; + const lhs_part_mat = try lhs_vi.mat(isel, .{ + .offset = part_offset, + .size = @intCast(part_size), + .pref = .only_reg, + .reg_mod = res_part_ra.mod, + }); + const lhs_part_reg = lhs_part_mat.reg(); + const rhs_part_mat = try lhs_vi.mat(isel, .{ + .offset = part_offset, + .size = @intCast(part_size), + .pref = .only_reg, + .reg_mod = res_part_ra.mod, + }); + const rhs_part_reg = rhs_part_mat.reg(); + + try isel.emit(switch (air_tag) { + else => unreachable, + .bit_and => .@"and"(res_part_reg, lhs_part_reg, rhs_part_reg), + .bit_or => .@"or"(res_part_reg, lhs_part_reg, rhs_part_reg), + .xor => .xor(res_part_reg, lhs_part_reg, rhs_part_reg), + }); + try rhs_part_mat.finish(isel); + try lhs_part_mat.finish(isel); + } + }, + .cmp_lt, .cmp_lte, .cmp_eq, .cmp_gte, .cmp_gt, .cmp_neq => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| unused: { + defer res_vi.value.deref(isel); + + const bin_op = air.data(air.inst_index).bin_op; + const ty = isel.air.typeOf(bin_op.lhs, ip); + const lhs_vi = try isel.use(bin_op.lhs); + const rhs_vi = try isel.use(bin_op.rhs); + + switch (ip.indexToKey(ty.toIntern())) { + else => {}, + .opt_type => |payload_ty| switch (air_tag) { + else => unreachable, + .cmp_eq, .cmp_neq => if (!ty.optionalReprIsPayload(zcu)) { + const payload_size = ZigType.abiSize(.fromInterned(payload_ty), zcu); + try res_vi.value.reextendToGarbage(isel); + const res_reg = try res_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const cmp_label = isel.instructions.items.len; + try isel.cmp( + res_reg, + .fromInterned(payload_ty), + try lhs_vi.partExact(isel, 0, payload_size), + air_tag.toCmpOp().?, + try rhs_vi.partExact(isel, 0, payload_size), + ); + const lhs_tag_mat = try lhs_vi.mat(isel, .{ + .offset = payload_size, + .size = 1, + .pref = .only_reg, + .reg_mod = .integer, + .extension = .zero_ext, + }); + const rhs_tag_mat = try rhs_vi.mat(isel, .{ + .offset = payload_size, + .size = 1, + .pref = .only_reg, + .reg_mod = .integer, + .extension = .zero_ext, + }); + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = cmp_label, + }); + try isel.emit(.beqz(lhs_tag_mat.reg(), 0, 0)); + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = cmp_label, + }); + try isel.emit(.beqz(res_reg, 0, 0)); + + try isel.emit(.xori(res_reg, res_reg, 1)); + try isel.emit(.xor(res_reg, lhs_tag_mat.reg(), rhs_tag_mat.reg())); + try rhs_tag_mat.finish(isel); + try lhs_tag_mat.finish(isel); + break :unused; + }, + }, + } + + // TODO optimize fcc path + try res_vi.value.reextendToPcs(isel); + try isel.cmp( + try res_vi.value.defRegMod(isel, .integer) orelse break :unused, + ty, + lhs_vi, + air_tag.toCmpOp().?, + rhs_vi, + ); + }, + .store, .store_safe, .atomic_store_unordered => unused: { + const bin_op = air.data(air.inst_index).bin_op; + const ptr_ty = isel.air.typeOf(bin_op.lhs, ip); + const ptr_info = ptr_ty.ptrInfo(zcu); + if (ptr_info.packed_offset.host_size > 0) return isel.fail("packed store", .{}); + if (bin_op.rhs.toInterned()) |rhs_val| if (ip.isUndef(rhs_val)) break :unused; + + const src_vi = try isel.use(bin_op.rhs); + const ptr_vi = try isel.use(bin_op.lhs); + const ptr_mat = try ptr_vi.matReg(isel); + try src_vi.matStore(isel, ptr_mat.reg(), 0, .{ + .@"volatile" = ptr_info.flags.is_volatile, + }); + try ptr_mat.finish(isel); + }, + .load => { + const ty_op = air.data(air.inst_index).ty_op; + const ptr_ty = isel.air.typeOf(ty_op.operand, ip); + const ptr_info = ptr_ty.ptrInfo(zcu); + if (ptr_info.packed_offset.host_size > 0) return isel.fail("packed load", .{}); + + if (ptr_info.flags.is_volatile) _ = try isel.use(air.inst_index.toRef()); + if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| { + defer dst_vi.value.deref(isel); + + // TODO unaligned loads + assert(isel.target.cpu.has(.loongarch, .ual)); + const ptr_vi = try isel.use(ty_op.operand); + const ptr_mat = try ptr_vi.matIntRegZeroExt(isel); + _ = try dst_vi.value.defLoad(isel, ptr_mat.reg(), 0, .{ + .@"volatile" = ptr_info.flags.is_volatile, + }); + try ptr_mat.finish(isel); + } + }, + .int_cast => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| { + defer dst_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const dst_ty = ty_op.ty.toType(); + const dst_int_info = dst_ty.intInfo(zcu); + const src_ty = isel.air.typeOf(ty_op.operand, ip); + const src_int_info = src_ty.intInfo(zcu); + + if (dst_int_info.bits == src_int_info.bits) { + try dst_vi.value.defMove(isel, ty_op.operand); + } else { + const src_vi = try isel.use(ty_op.operand); + try dst_vi.value.reextendAdvanced(isel, src_int_info.bits, null, src_vi.extension(isel)); + try dst_vi.value.defCopy(isel, src_vi); + } + }, + .is_null, .is_non_null => if (isel.live_values.fetchRemove(air.inst_index)) |is_vi| unused: { + defer is_vi.value.deref(isel); + const is_reg = try is_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const un_op = air.data(air.inst_index).un_op; + const opt_ty = isel.air.typeOf(un_op, ip); + const payload_ty = opt_ty.optionalChild(zcu); + const payload_size = payload_ty.abiSize(zcu); + const has_value_offset, const has_value_size = if (!opt_ty.optionalReprIsPayload(zcu)) + .{ payload_size, 1 } + else if (payload_ty.isSlice(zcu)) + .{ 0, 8 } + else + .{ 0, @as(u32, @intCast(payload_size)) }; + + const opt_vi = try isel.use(un_op); + const has_value_mat = try opt_vi.mat(isel, .{ + .offset = has_value_offset, + .size = has_value_size, + .pref = .only_reg, + .reg_mod = .integer, + .extension = .zero_ext, + .hint_ra = .{ .reg = is_reg, .mod = .integer }, + }); + const has_value_reg = has_value_mat.reg(); + try isel.emit(switch (air_tag) { + else => unreachable, + .is_null => .sltui(is_reg, has_value_reg, 1), + .is_non_null => .sltu(is_reg, .zero, has_value_reg), + }); + try has_value_mat.finish(isel); + }, + .is_err, .is_non_err => if (isel.live_values.fetchRemove(air.inst_index)) |is_vi| unused: { + defer is_vi.value.deref(isel); + const is_reg = try is_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const un_op = air.data(air.inst_index).un_op; + const error_union_ty = isel.air.typeOf(un_op, ip); + const error_union_info = ip.indexToKey(error_union_ty.toIntern()).error_union_type; + const error_set_ty: ZigType = .fromInterned(error_union_info.error_set_type); + const payload_ty: ZigType = .fromInterned(error_union_info.payload_type); + const error_set_offset = codegen.errUnionErrorOffset(payload_ty, zcu); + const error_set_size = error_set_ty.abiSize(zcu); + + const error_union_vi = try isel.use(un_op); + const error_set_mat = try error_union_vi.mat(isel, .{ + .offset = error_set_offset, + .size = @intCast(error_set_size), + .pref = .only_reg, + .reg_mod = .integer, + .hint_ra = .{ .reg = is_reg, .mod = .integer }, + }); + try isel.emit(switch (air_tag) { + else => unreachable, + .is_err => .sltu(is_reg, .zero, is_reg), + .is_non_err => .sltui(is_reg, is_reg, 1), + }); + try error_set_mat.finish(isel); + }, + .max, .min => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| unused: { + defer res_vi.value.deref(isel); + + const bin_op = air.data(air.inst_index).bin_op; + const ty = isel.air.typeOf(bin_op.lhs, ip); + if (!ty.isRuntimeFloat()) { + if (!ty.isAbiInt(zcu)) return isel.fail("bad {t} {f}", .{ air_tag, isel.fmtType(ty) }); + const int_info = ty.intInfo(zcu); + if (int_info.bits > 64) return isel.fail("too big {t} {f}", .{ air_tag, isel.fmtType(ty) }); + + try res_vi.value.reextendToGarbage(isel); + const res_reg = try res_vi.value.defRegMod(isel, .integer) orelse break :unused; + const lhs_vi = try isel.use(bin_op.lhs); + // TODO: relax LHS and RHS requirements to "not garbage filled" + const lhs_mat = try lhs_vi.matIntRegZeroExt(isel); + const lhs_reg = lhs_mat.reg(); + const rhs_vi = try isel.use(bin_op.rhs); + const rhs_mat = try rhs_vi.matIntRegZeroExt(isel); + const rhs_reg = rhs_mat.reg(); + + const tmp_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(tmp_reg); + const cond_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(cond_reg); + + try isel.emit(.@"or"(res_reg, res_reg, tmp_reg)); + try isel.emit(.maskeqz(res_reg, lhs_reg, cond_reg)); + try isel.emit(.masknez(tmp_reg, rhs_reg, cond_reg)); + switch (air_tag) { + else => unreachable, + .min => try isel.emit(.sltu(cond_reg, lhs_reg, rhs_reg)), + .max => try isel.emit(.sltu(cond_reg, rhs_reg, lhs_reg)), + } + + try rhs_mat.finish(isel); + try lhs_mat.finish(isel); + } else switch (ty.floatBits(isel.target)) { + else => unreachable, + 32, 64 => return isel.fail("TODO float min/max", .{}), + } + }, + .slice => if (isel.live_values.fetchRemove(air.inst_index)) |slice_vi| { + defer slice_vi.value.deref(isel); + const ty_pl = air.data(air.inst_index).ty_pl; + const bin_op = isel.air.extraData(Air.Bin, ty_pl.payload).data; + const gpr_size = isel.gprSize(); + const ptr_part_vi = try slice_vi.value.partExact(isel, 0, gpr_size); + try ptr_part_vi.defMove(isel, bin_op.lhs); + const len_part_vi = try slice_vi.value.partExact(isel, gpr_size, gpr_size); + try len_part_vi.defMove(isel, bin_op.rhs); + }, + .slice_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |ptr_vi| { + defer ptr_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const gpr_size = isel.gprSize(); + const slice_vi = try isel.use(ty_op.operand); + const ptr_part_vi = try slice_vi.partExact(isel, 0, gpr_size); + try ptr_vi.value.defCopy(isel, ptr_part_vi); + }, + .slice_len => if (isel.live_values.fetchRemove(air.inst_index)) |len_vi| { + defer len_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const gpr_size = isel.gprSize(); + const slice_vi = try isel.use(ty_op.operand); + const len_part_vi = try slice_vi.partExact(isel, gpr_size, gpr_size); + try len_vi.value.defCopy(isel, len_part_vi); + }, + .ptr_slice_ptr_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| { + defer dst_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + try dst_vi.value.defMove(isel, ty_op.operand); + }, + .ptr_slice_len_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| unused: { + defer dst_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const dst_reg = try dst_vi.value.defRegMod(isel, .integer) orelse break :unused; + const src_vi = try isel.use(ty_op.operand); + const src_mat = try src_vi.matIntRegZeroExt(isel); + const src_reg = src_mat.reg(); + switch (isel.gprSize()) { + else => unreachable, + 4 => try isel.emit(.@"addi.w"(dst_reg, src_reg, 4)), + 8 => try isel.emit(.@"addi.d"(dst_reg, src_reg, 8)), + } + try src_mat.finish(isel); + }, + .slice_elem_val => if (isel.live_values.fetchRemove(air.inst_index)) |elem_vi| unused: { + defer elem_vi.value.deref(isel); + + const bin_op = air.data(air.inst_index).bin_op; + const slice_ty = isel.air.typeOf(bin_op.lhs, ip); + const ptr_info = slice_ty.ptrInfo(zcu); + const elem_size = elem_vi.value.size(isel); + + const elem_ptr_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(elem_ptr_reg); + + if (!try elem_vi.value.defLoad(isel, elem_ptr_reg, 0, .{ + .@"volatile" = ptr_info.flags.is_volatile, + })) break :unused; + + const slice_vi = try isel.use(bin_op.lhs); + const base_ptr_mat = try slice_vi.mat(isel, .{ + .offset = 0, + .size = isel.gprSize(), + .pref = .only_reg, + .reg_mod = .integer, + }); + const index_vi = try isel.use(bin_op.rhs); + try isel.elemPtr(elem_ptr_reg, base_ptr_mat.reg(), .add, elem_size, index_vi); + try base_ptr_mat.finish(isel); + }, + .slice_elem_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |elem_ptr_vi| unused: { + defer elem_ptr_vi.value.deref(isel); + const elem_ptr_reg = try elem_ptr_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const ty_pl = air.data(air.inst_index).ty_pl; + const bin_op = isel.air.extraData(Air.Bin, ty_pl.payload).data; + const elem_size = ty_pl.ty.toType().childType(zcu).abiSize(zcu); + + const slice_vi = try isel.use(bin_op.lhs); + const base_ptr_mat = try slice_vi.mat(isel, .{ + .offset = 0, + .size = isel.gprSize(), + .pref = .only_reg, + .reg_mod = .integer, + }); + const index_vi = try isel.use(bin_op.rhs); + try isel.elemPtr(elem_ptr_reg, base_ptr_mat.reg(), .add, elem_size, index_vi); + try base_ptr_mat.finish(isel); + }, + .ptr_add, .ptr_sub => if (isel.live_values.fetchRemove(air.inst_index)) |res_vi| unused: { + defer res_vi.value.deref(isel); + const res_reg = try res_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const ty_pl = air.data(air.inst_index).ty_pl; + const bin_op = isel.air.extraData(Air.Bin, ty_pl.payload).data; + const elem_size = ty_pl.ty.toType().childType(zcu).abiSize(zcu); + + const base_vi = try isel.use(bin_op.lhs); + const base_ptr_mat = try base_vi.mat(isel, .{ + .offset = 0, + .size = isel.gprSize(), + .pref = .only_reg, + .reg_mod = .integer, + }); + const index_vi = try isel.use(bin_op.rhs); + try isel.elemPtr(res_reg, base_ptr_mat.reg(), switch (air_tag) { + else => unreachable, + .ptr_add => .add, + .ptr_sub => .sub, + }, elem_size, index_vi); + try base_ptr_mat.finish(isel); + }, + .ptr_elem_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |elem_ptr_vi| unused: { + defer elem_ptr_vi.value.deref(isel); + const elem_ptr_reg = try elem_ptr_vi.value.defRegMod(isel, .integer) orelse break :unused; + + const ty_pl = air.data(air.inst_index).ty_pl; + const bin_op = isel.air.extraData(Air.Bin, ty_pl.payload).data; + const elem_size = ty_pl.ty.toType().childType(zcu).abiSize(zcu); + + const base_vi = try isel.use(bin_op.lhs); + const base_mat = try base_vi.matIntRegZeroExt(isel); + const index_vi = try isel.use(bin_op.rhs); + try isel.elemPtr(elem_ptr_reg, base_mat.reg(), .add, elem_size, index_vi); + try base_mat.finish(isel); + }, + .array_to_slice => if (isel.live_values.fetchRemove(air.inst_index)) |slice_vi| { + defer slice_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const gpr_size = isel.gprSize(); + const array_len = isel.air.typeOf(ty_op.operand, ip).childType(zcu).arrayLen(zcu); + + const len_part_vi = try slice_vi.value.partExact(isel, gpr_size, gpr_size); + if (try len_part_vi.defRegMod(isel, .integer)) |len_reg| + try isel.moveIntImm(len_reg, @bitCast(array_len)); + + const ptr_part_vi = try slice_vi.value.partExact(isel, 0, gpr_size); + try ptr_part_vi.defMove(isel, ty_op.operand); + }, + .@"try", .try_cold => { + const pl_op = air.data(air.inst_index).pl_op; + const extra = isel.air.extraData(Air.Try, pl_op.payload); + const error_union_ty = isel.air.typeOf(pl_op.operand, ip); + const error_union_info = ip.indexToKey(error_union_ty.toIntern()).error_union_type; + const payload_ty: ZigType = .fromInterned(error_union_info.payload_type); + + const error_union_vi = try isel.use(pl_op.operand); + if (isel.live_values.fetchRemove(air.inst_index)) |payload_vi| { + defer payload_vi.value.deref(isel); + + const payload_part_vi = try error_union_vi.partExact( + isel, + codegen.errUnionPayloadOffset(payload_ty, zcu), + payload_vi.value.size(isel), + ); + try payload_vi.value.defCopy(isel, payload_part_vi); + } + + const cont_label = isel.instructions.items.len; + var cont_snapshot = try isel.takeLocationSnapshot(); + defer cont_snapshot.deinit(isel); + tracking_log.debug("try-continue snapshot taken:\n{f}", .{cont_snapshot}); + try isel.body(@ptrCast(isel.air.extra.items[extra.end..][0..extra.data.body_len])); + try cont_snapshot.merge(isel); + + const error_set_part_vi = try error_union_vi.partExact( + isel, + codegen.errUnionErrorOffset(payload_ty, zcu), + ZigType.fromInterned(error_union_info.error_set_type).abiSize(zcu), + ); + const error_set_part_mat = try error_set_part_vi.matIntRegZeroExt(isel); + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = cont_label, + }); + try isel.emit(.beqz(error_set_part_mat.reg(), 0, 0)); + try error_set_part_mat.finish(isel); + }, + .try_ptr, .try_ptr_cold => { + const unwrapped_try = isel.air.unwrapTryPtr(air.inst_index); + const error_union_ty = isel.air.typeOf(unwrapped_try.error_union_ptr, ip).childType(zcu); + const error_union_info = ip.indexToKey(error_union_ty.toIntern()).error_union_type; + const payload_ty: ZigType = .fromInterned(error_union_info.payload_type); + + const error_union_ptr_vi = try isel.use(unwrapped_try.error_union_ptr); + if (isel.live_values.fetchRemove(air.inst_index)) |payload_ptr_vi| unused: { + defer payload_ptr_vi.value.deref(isel); + + const payload_offset = codegen.errUnionPayloadOffset(unwrapped_try.error_union_payload_ptr_ty.toType().childType(zcu), zcu); + if (payload_offset == 0) { + try payload_ptr_vi.value.defMove(isel, unwrapped_try.error_union_ptr); + } else { + const payload_ptr_reg = try payload_ptr_vi.value.defRegMod(isel, .integer) orelse break :unused; + const error_union_ptr_mat = try error_union_ptr_vi.matIntRegZeroExt(isel); + try isel.addImm(payload_ptr_reg, error_union_ptr_mat.reg(), payload_offset); + try error_union_ptr_mat.finish(isel); + } + } + + const cont_label = isel.instructions.items.len; + var cont_snapshot = try isel.takeLocationSnapshot(); + defer cont_snapshot.deinit(isel); + tracking_log.debug("try_ptr-continue snapshot taken:\n{f}", .{cont_snapshot}); + try isel.body(unwrapped_try.else_body); + try cont_snapshot.merge(isel); + + const tmp_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(tmp_reg); + + try isel.internal_relocs.append(gpa, .{ + .label = @intCast(isel.instructions.items.len), + .target = cont_label, + }); + try isel.emit(.beqz(tmp_reg, 0, 0)); + + const error_union_ptr_mat = try error_union_ptr_vi.matIntRegZeroExt(isel); + try isel.loadReg( + tmp_reg, + ZigType.fromInterned(error_union_info.error_set_type).abiSize(zcu), + .unsigned, + error_union_ptr_mat.reg(), + codegen.errUnionErrorOffset(payload_ty, zcu), + ); + try error_union_ptr_mat.finish(isel); + }, + .aggregate_init => if (isel.live_values.fetchRemove(air.inst_index)) |agg_vi| { + defer agg_vi.value.deref(isel); + + const ty_pl = air.data(air.inst_index).ty_pl; + const agg_ty = ty_pl.ty.toType(); + switch (ip.indexToKey(agg_ty.toIntern())) { + .array_type => |array_type| { + const elem_ty = ZigType.fromInterned(array_type.child); + const elem_size = elem_ty.abiSize(zcu); + const elems: []const Air.Inst.Ref = + @ptrCast(isel.air.extra.items[ty_pl.payload..][0..@intCast(array_type.len)]); + var elem_offset: u64 = 0; + + try agg_vi.value.split(isel, false); + for (elems) |elem| { + const agg_part_vi = try agg_vi.value.partExactRecursive(isel, elem_offset, elem_size); + try agg_part_vi.defMove(isel, elem); + elem_offset += elem_size; + } + switch (array_type.sentinel) { + .none => {}, + else => |sentinel| { + const agg_part_vi = try agg_vi.value.partExactRecursive(isel, elem_offset, elem_size); + try agg_part_vi.defMove(isel, .fromIntern(sentinel)); + }, + } + }, + .struct_type => { + const loaded_struct = ip.loadStructType(agg_ty.toIntern()); + const elems: []const Air.Inst.Ref = + @ptrCast(isel.air.extra.items[ty_pl.payload..][0..loaded_struct.field_types.len]); + var field_offset: u64 = 0; + var field_it = loaded_struct.iterateRuntimeOrder(ip); + while (field_it.next()) |field_index| { + const field_ty: ZigType = .fromInterned(loaded_struct.field_types.get(ip)[field_index]); + field_offset = loaded_struct.field_offsets.get(ip)[field_index]; + const field_size = field_ty.abiSize(zcu); + if (field_size == 0) continue; + const agg_part_vi = try agg_vi.value.partExactRecursive(isel, field_offset, field_size); + try agg_part_vi.defMove(isel, elems[field_index]); + field_offset += field_size; + } + assert(loaded_struct.alignment.forward(field_offset) == agg_vi.value.size(isel)); + }, + .tuple_type => |tuple_type| { + const elems: []const Air.Inst.Ref = + @ptrCast(isel.air.extra.items[ty_pl.payload..][0..tuple_type.types.len]); + var tuple_align: InternPool.Alignment = .@"1"; + var field_offset: u64 = 0; + for ( + tuple_type.types.get(ip), + tuple_type.values.get(ip), + elems, + ) |field_ty_index, field_val, elem| { + if (field_val != .none) continue; + const field_ty: ZigType = .fromInterned(field_ty_index); + const field_align = field_ty.abiAlignment(zcu); + tuple_align = tuple_align.maxStrict(field_align); + field_offset = field_align.forward(field_offset); + const field_size = field_ty.abiSize(zcu); + if (field_size == 0) continue; + const agg_part_vi = try agg_vi.value.partExactRecursive(isel, field_offset, field_size); + try agg_part_vi.defMove(isel, elem); + field_offset += field_size; + } + assert(tuple_align.forward(field_offset) == agg_vi.value.size(isel)); + }, + .vector_type => try isel.failUnimplemented("agg init vector", .{}), + else => unreachable, + } + }, + .struct_field_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| unused: { + defer dst_vi.value.deref(isel); + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.StructField, ty_pl.payload).data; + switch (codegen.fieldOffset( + isel.air.typeOf(extra.struct_operand, ip), + ty_pl.ty.toType(), + extra.field_index, + zcu, + )) { + 0 => try dst_vi.value.defMove(isel, extra.struct_operand), + else => |field_offset| { + const dst_reg = try dst_vi.value.defRegMod(isel, .integer) orelse break :unused; + const src_vi = try isel.use(extra.struct_operand); + const src_mat = try src_vi.matIntRegZeroExt(isel); + try isel.addImm(dst_reg, src_mat.reg(), field_offset); + try src_mat.finish(isel); + }, + } + }, + .struct_field_ptr_index_0, + .struct_field_ptr_index_1, + .struct_field_ptr_index_2, + .struct_field_ptr_index_3, + => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| unused: { + defer dst_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + switch (codegen.fieldOffset( + isel.air.typeOf(ty_op.operand, ip), + ty_op.ty.toType(), + switch (air_tag) { + else => unreachable, + .struct_field_ptr_index_0 => 0, + .struct_field_ptr_index_1 => 1, + .struct_field_ptr_index_2 => 2, + .struct_field_ptr_index_3 => 3, + }, + zcu, + )) { + 0 => try dst_vi.value.defMove(isel, ty_op.operand), + else => |field_offset| { + const dst_reg = try dst_vi.value.defRegMod(isel, .integer) orelse break :unused; + const src_vi = try isel.use(ty_op.operand); + const src_mat = try src_vi.matIntRegZeroExt(isel); + try isel.addImm(dst_reg, src_mat.reg(), field_offset); + try src_mat.finish(isel); + }, + } + }, + .agg_field_val => if (isel.live_values.fetchRemove(air.inst_index)) |field_vi| { + defer field_vi.value.deref(isel); + + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.StructField, ty_pl.payload).data; + const agg_ty = isel.air.typeOf(extra.struct_operand, ip); + const field_ty = ty_pl.ty.toType(); + + const field_bit_offset, const field_bit_size, const is_packed = switch (agg_ty.containerLayout(zcu)) { + .auto, .@"extern" => .{ + 8 * agg_ty.structFieldOffset(extra.field_index, zcu), + 8 * field_ty.abiSize(zcu), + false, + }, + .@"packed" => .{ + if (zcu.typeToPackedStruct(agg_ty)) |loaded_struct| + zcu.structPackedFieldBitOffset(loaded_struct, extra.field_index) + else + 0, + field_ty.bitSize(zcu), + true, + }, + }; + if (is_packed) return isel.fail("packed field of {f}", .{ + isel.fmtType(agg_ty), + }); + + const agg_vi = try isel.use(extra.struct_operand); + switch (agg_ty.zigTypeTag(zcu)) { + else => unreachable, + .@"struct" => { + const agg_part_vi = try agg_vi.partExactRecursive( + isel, + @divExact(field_bit_offset, 8), + @divExact(field_bit_size, 8), + ); + try field_vi.value.defCopy(isel, agg_part_vi); + }, + .@"union" => { + const agg_part_vi = try agg_vi.partAtLargerThan( + isel, + @divExact(field_bit_offset, 8), + @divExact(field_bit_size, 8), + ); + try field_vi.value.defCopy(isel, agg_part_vi); + }, + } + }, + .union_init => if (isel.live_values.fetchRemove(air.inst_index)) |union_vi| { + defer union_vi.value.deref(isel); + + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.UnionInit, ty_pl.payload).data; + const union_ty = ty_pl.ty.toType(); + const loaded_union = ip.loadUnionType(union_ty.toIntern()); + const union_layout = ZigType.getUnionLayout(loaded_union, zcu); + + if (union_layout.tag_size > 0) unused_tag: { + const loaded_tag = ip.loadEnumType(loaded_union.enum_tag_type); + const tag_vi = try union_vi.value.partExact( + isel, + union_layout.tagOffset(), + union_layout.tag_size, + ); + if (tag_vi.extension(isel) == .sign_ext) + try tag_vi.reextendToGarbage(isel); + const tag_reg = try tag_vi.defRegMod(isel, .integer) orelse break :unused_tag; + const tag_val: i64 = switch (loaded_tag.field_values.len) { + 0 => extra.field_index, + else => switch (ip.indexToKey(loaded_tag.field_values.get(ip)[extra.field_index]).int.storage) { + .u64 => |imm| @bitCast(imm), + .i64 => |imm| imm, + else => unreachable, + }, + }; + try isel.moveIntImm(tag_reg, tag_val); + } + const payload_vi = try union_vi.value.partExact( + isel, + union_layout.payloadOffset(), + union_layout.payload_size, + ); + try payload_vi.defMove(isel, extra.init); + }, + .set_union_tag => { + const bin_op = air.data(air.inst_index).bin_op; + const union_ty = isel.air.typeOf(bin_op.lhs, ip).childType(zcu); + const union_layout = union_ty.unionGetLayout(zcu); + const tag_vi = try isel.use(bin_op.rhs); + const union_ptr_vi = try isel.use(bin_op.lhs); + const union_ptr_mat = try union_ptr_vi.matIntRegZeroExt(isel); + try tag_vi.matStore(isel, union_ptr_mat.reg(), union_layout.tagOffset(), .{}); + try union_ptr_mat.finish(isel); + }, + .get_union_tag => if (isel.live_values.fetchRemove(air.inst_index)) |tag_vi| { + defer tag_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const union_ty = isel.air.typeOf(ty_op.operand, ip); + const union_layout = union_ty.unionGetLayout(zcu); + const union_vi = try isel.use(ty_op.operand); + const tag_part_vi = try union_vi.partExact(isel, union_layout.tagOffset(), union_layout.tag_size); + try tag_vi.value.defCopy(isel, tag_part_vi); + }, + .optional_payload => if (isel.live_values.fetchRemove(air.inst_index)) |payload_vi| unused: { + defer payload_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const opt_ty = isel.air.typeOf(ty_op.operand, ip); + if (opt_ty.optionalReprIsPayload(zcu)) { + try payload_vi.value.defMove(isel, ty_op.operand); + break :unused; + } + + const opt_vi = try isel.use(ty_op.operand); + const payload_part_vi = try opt_vi.partExact(isel, 0, payload_vi.value.size(isel)); + try payload_vi.value.defCopy(isel, payload_part_vi); + }, + .optional_payload_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |payload_ptr_vi| { + defer payload_ptr_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + try payload_ptr_vi.value.defMove(isel, ty_op.operand); + }, + .wrap_optional => if (isel.live_values.fetchRemove(air.inst_index)) |opt_vi| unused: { + defer opt_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + if (ty_op.ty.toType().optionalReprIsPayload(zcu)) { + try opt_vi.value.defMove(isel, ty_op.operand); + break :unused; + } + + const payload_size = isel.air.typeOf(ty_op.operand, ip).abiSize(zcu); + + const payload_part_vi = try opt_vi.value.partExact(isel, 0, payload_size); + const has_value_part_vi = try opt_vi.value.partExact(isel, payload_size, 1); + try payload_part_vi.defMove(isel, ty_op.operand); + const maybe_has_value_part_reg = try has_value_part_vi.defRegMod(isel, .integer); + if (maybe_has_value_part_reg) |has_value_part_reg| + try isel.emit(.ori(has_value_part_reg, .zero, 0)); + }, + .field_parent_ptr => if (isel.live_values.fetchRemove(air.inst_index)) |dst_vi| unused: { + defer dst_vi.value.deref(isel); + const ty_pl = air.data(air.inst_index).ty_pl; + const extra = isel.air.extraData(Air.FieldParentPtr, ty_pl.payload).data; + switch (codegen.fieldOffset( + ty_pl.ty.toType(), + isel.air.typeOf(extra.field_ptr, ip), + extra.field_index, + zcu, + )) { + 0 => try dst_vi.value.defMove(isel, extra.field_ptr), + else => |field_offset| { + const dst_reg = try dst_vi.value.defRegMod(isel, .integer) orelse break :unused; + const src_vi = try isel.use(extra.field_ptr); + const src_mat = try src_vi.matIntRegZeroExt(isel); + try isel.addImm(dst_reg, src_mat.reg(), -@as(i65, field_offset)); + try src_mat.finish(isel); + }, + } + }, + .unwrap_errunion_payload => if (isel.live_values.fetchRemove(air.inst_index)) |payload_vi| { + defer payload_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const error_union_vi = try isel.use(ty_op.operand); + try payload_vi.value.defCopy( + isel, + try error_union_vi.partExact( + isel, + codegen.errUnionPayloadOffset(ty_op.ty.toType(), zcu), + payload_vi.value.size(isel), + ), + ); + }, + .unwrap_errunion_err => if (isel.live_values.fetchRemove(air.inst_index)) |error_set_vi| { + defer error_set_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const error_union_ty = isel.air.typeOf(ty_op.operand, ip); + const error_union_vi = try isel.use(ty_op.operand); + try error_set_vi.value.defCopy( + isel, + try error_union_vi.partExact( + isel, + codegen.errUnionErrorOffset(error_union_ty.errorUnionPayload(zcu), zcu), + error_set_vi.value.size(isel), + ), + ); + }, + .wrap_errunion_payload => if (isel.live_values.fetchRemove(air.inst_index)) |error_union_vi| { + defer error_union_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const error_union_ty = ty_op.ty.toType(); + const error_union_info = ip.indexToKey(error_union_ty.toIntern()).error_union_type; + const error_set_ty: ZigType = .fromInterned(error_union_info.error_set_type); + const payload_ty: ZigType = .fromInterned(error_union_info.payload_type); + const error_set_offset = codegen.errUnionErrorOffset(payload_ty, zcu); + const payload_offset = codegen.errUnionPayloadOffset(payload_ty, zcu); + const error_set_size = error_set_ty.abiSize(zcu); + const payload_size = payload_ty.abiSize(zcu); + + try error_union_vi.value.collectDefs(isel); + + if (payload_size > 0) { + const payload_part_vi = try error_union_vi.value.partExact(isel, payload_offset, payload_size); + try payload_part_vi.defMove(isel, ty_op.operand); + } + const error_set_part_vi = try error_union_vi.value.partExact(isel, error_set_offset, error_set_size); + if (try error_set_part_vi.defRegMod(isel, .integer)) |error_set_part_reg| + try isel.emit(.ori(error_set_part_reg, .zero, 0)); + }, + .wrap_errunion_err => if (isel.live_values.fetchRemove(air.inst_index)) |error_union_vi| { + defer error_union_vi.value.deref(isel); + + const ty_op = air.data(air.inst_index).ty_op; + const error_union_ty = ty_op.ty.toType(); + const error_union_info = ip.indexToKey(error_union_ty.toIntern()).error_union_type; + const error_set_ty: ZigType = .fromInterned(error_union_info.error_set_type); + const payload_ty: ZigType = .fromInterned(error_union_info.payload_type); + const error_set_offset = codegen.errUnionErrorOffset(payload_ty, zcu); + const payload_offset = codegen.errUnionPayloadOffset(payload_ty, zcu); + const error_set_size = error_set_ty.abiSize(zcu); + const payload_size = payload_ty.abiSize(zcu); + + const error_set_part_vi = try error_union_vi.value.partExact(isel, error_set_offset, error_set_size); + try error_set_part_vi.defMove(isel, ty_op.operand); + if (payload_size > 0) { + const payload_part_vi = try error_union_vi.value.partExact(isel, payload_offset, payload_size); + try payload_part_vi.defUndef(isel); + } + }, + .errunion_payload_ptr_set => if (isel.live_values.fetchRemove(air.inst_index)) |payload_ptr_vi| unused: { + defer payload_ptr_vi.value.deref(isel); + const ty_op = air.data(air.inst_index).ty_op; + const payload_ty = ty_op.ty.toType().childType(zcu); + const eu_ty = isel.air.typeOf(ty_op.operand, ip).childType(zcu); + const error_set_size = eu_ty.errorUnionSet(zcu).abiSize(zcu); + + const eu_ptr_vi = try isel.use(ty_op.operand); + const error_union_ptr_mat = try eu_ptr_vi.matIntRegZeroExt(isel); + if (error_set_size != 0) { + try isel.storeReg( + .zero, + error_set_size, + error_union_ptr_mat.reg(), + codegen.errUnionErrorOffset(payload_ty, zcu), + ); + } + const payload_offset = codegen.errUnionPayloadOffset(payload_ty, zcu); + if (payload_offset == 0) { + try error_union_ptr_mat.finish(isel); + try payload_ptr_vi.value.defMove(isel, ty_op.operand); + } else { + const payload_ptr_reg = try payload_ptr_vi.value.defRegMod(isel, .integer) orelse break :unused; + try isel.addImm(payload_ptr_reg, error_union_ptr_mat.reg(), payload_offset); + try error_union_ptr_mat.finish(isel); + } + }, + } + if (air_tag != .arg) { + var live_reg_it = isel.live_registers.iterator(); + while (live_reg_it.next()) |live_reg_entry| switch (live_reg_entry.value.*) { + .allocating => { + tracking_log.err("${t} is still allocated", .{live_reg_entry.key}); + isel.dumpValues(.all); + unreachable; + }, + _, .free => {}, + }; + } + if (debug_r21_as_air) { + try isel.moveIntImm(.r21, @backingInt(air.inst_index)); + } + } + assert(air.body_index == 0); +} + +/// Generates prologue and epilogue. Returns the length of epilogue. +/// +/// Stack Frame Layout +/// +-+-----------------------------------+ +/// |R| caller frame | +/// +-+-----------------------------------+ +/// |S| incoming stack arguments | +---------------+ +/// +-+-----------------------------------+ <-| align(16) | +/// |L| callee saved FP | | entry/exit SP | +/// +-+-----------------------------------+ | FP | +/// |L| callee saved GPR area | +---------------+ +/// +-+-----------------------------------+ +/// |L| callee saved FPR area | +-----------------+ +/// +-+-----------------------------------+ <-| FP - saves_size | +/// |L| realignment gap | +-----------------+ +/// +-+-----------------------------------+ <-| align(16) | +/// |L| locals | +-----------------+ +/// +-+-----------------------------------+ +/// |S| outgoing stack arguments | +----+ +/// +-+-----------------------------------+ <-| SP | +/// +----+ +/// [S] Size computed by `analyze`, can be used by the body. +/// [L] Size computed by `layout`, can be used by the prologue/epilogue. +/// [R] Size unknown until runtime, can vary from one call to the next. +/// +/// FP saving/restoring is not yet implemented. +pub fn layout(isel: *Select, cc_it: CallAbiIterator, mod: *const Module) !usize { + _ = cc_it; + _ = mod; + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + const nav = ip.getNav(isel.nav_index); + wip_mir_log.debug("{f}:\n", .{nav.fqn.fmt(ip)}); + + const gpr_size = isel.gprSize(); + + var saves_buf: [10 + 2 + 8]struct { + register: Register, + needs_restore: bool, + offset: u11, + size: u5, + } = undefined; + var saved_offset: std.EnumArray(Register, u11) = .initUndefined(); + const saves, const saves_size = saves: { + var saves_len: usize = 0; + var saves_size: u11 = 0; + var save_reg: Register = undefined; + + // callee saved GPR area + save_reg = .r23; + while (true) : (save_reg = @fromBackingInt(@backingInt(save_reg) + 1)) { + if (isel.saved_registers.contains(save_reg)) { + saves_size = std.mem.alignForward(u11, saves_size, gpr_size); + saves_buf[saves_len] = .{ + .register = save_reg, + .needs_restore = true, + .offset = saves_size, + .size = gpr_size, + }; + saved_offset.set(save_reg, saves_size); + saves_len += 1; + saves_size += gpr_size; + } + if (save_reg == .r31) break; + } + inline for (.{ Register.ra, Register.fp }) |reg| { + if (isel.saved_registers.contains(reg)) { + saves_size = std.mem.alignForward(u11, saves_size, gpr_size); + saves_buf[saves_len] = .{ + .register = reg, + .needs_restore = true, + .offset = saves_size, + .size = gpr_size, + }; + saved_offset.set(reg, saves_size); + saves_len += 1; + saves_size += gpr_size; + } + } + + // callee saved FPR area + save_reg = .f24; + while (true) : (save_reg = @fromBackingInt(@backingInt(save_reg) + 1)) { + if (isel.saved_registers.contains(save_reg)) { + saves_size = std.mem.alignForward(u11, saves_size, 8); + saves_buf[saves_len] = .{ + .register = save_reg, + .needs_restore = true, + .offset = saves_size, + .size = 8, + }; + saved_offset.set(save_reg, saves_size); + saves_len += 1; + saves_size += 8; + } + if (save_reg == .f31) break; + } + break :saves .{ saves_buf[0..saves_len], std.mem.Alignment.@"16".forward(saves_size) }; + }; + + const stack_frame_size = isel.stack_align.forward(saves_size + isel.stack_size); + + // apply layout relocs + for (isel.layout_relocs.items) |label| { + const instruction = isel.instructions.items[label]; + const rj: Register = .decode(.int, instruction.DJUk12.rj); + if (isel.saved_registers.contains(rj)) { + const rd: Register = .decode(.int, instruction.DJUk12.rd); + const offset = saved_offset.get(rj); + isel.instructions.items[label] = switch (gpr_size) { + else => unreachable, + 4 => .@"ld.w"(rd, .sp, @intCast(stack_frame_size - 8 - offset)), + 8 => .@"ld.d"(rd, .sp, @intCast(stack_frame_size - 8 - offset)), + }; + } + } + + // prologue + { + // move SP + if (stack_frame_size == 0) {} else if (std.math.cast(i12, stack_frame_size)) |stack_size12| { + switch (gpr_size) { + 4 => try isel.emit(.@"addi.w"(.sp, .sp, -stack_size12)), + 8 => try isel.emit(.@"addi.d"(.sp, .sp, -stack_size12)), + else => unreachable, + } + } else { + switch (gpr_size) { + 4 => try isel.emit(.@"sub.w"(.sp, .sp, .t0)), + 8 => try isel.emit(.@"sub.d"(.sp, .sp, .t0)), + else => unreachable, + } + try isel.moveIntImm(.t0, @intCast(stack_frame_size)); + } + + // set FP + if (isel.saved_registers.contains(.fp)) + try isel.emit(.ori(.fp, .sp, 0)); + + // save registers + for (saves) |save| { + switch (save.register.class()) { + .int => switch (gpr_size) { + 4 => try isel.emit(.@"st.h"(save.register, .sp, -8 - @as(i12, save.offset))), + 8 => try isel.emit(.@"st.d"(save.register, .sp, -8 - @as(i12, save.offset))), + else => unreachable, + }, + .fp => try isel.emit(.@"fst.d"(save.register, .sp, -8 - @as(i12, save.offset))), + .fcc => unreachable, + } + } + wip_mir_log.debug("{f}:", .{nav.fqn.fmt(ip)}); + } + + // epilogue + const epilogue = isel.instructions.items.len; + if (isel.returns) { + // return + try isel.emit(.jirl(.zero, .ra, 0)); + + // restore registers + for (saves) |save| { + if (!save.needs_restore) continue; + switch (save.register.class()) { + .int => switch (gpr_size) { + 4 => try isel.emit(.@"ld.h"(save.register, .sp, -8 - @as(i12, save.offset))), + 8 => try isel.emit(.@"ld.d"(save.register, .sp, -8 - @as(i12, save.offset))), + else => unreachable, + }, + .fp => try isel.emit(.@"fld.d"(save.register, .sp, -8 - @as(i12, save.offset))), + .fcc => unreachable, + } + } + + // restore SP + if (stack_frame_size == 0) {} else if (std.math.cast(i12, stack_frame_size)) |stack_size12| { + switch (gpr_size) { + 4 => try isel.emit(.@"addi.w"(.sp, .sp, stack_size12)), + 8 => try isel.emit(.@"addi.d"(.sp, .sp, stack_size12)), + else => unreachable, + } + } else { + switch (gpr_size) { + 4 => try isel.emit(.@"add.w"(.sp, .sp, .t0)), + 8 => try isel.emit(.@"add.d"(.sp, .sp, .t0)), + else => unreachable, + } + try isel.moveIntImm(.t0, @intCast(stack_frame_size)); + } + + wip_mir_log.debug("{f}:\n", .{nav.fqn.fmt(ip)}); + } + return epilogue; +} + +fn emit(isel: *Select, instruction: Instruction) !void { + wip_mir_log.debug(" | {f}", .{(Disassemble{}).fmtInstruction(instruction)}); + try isel.instructions.append(isel.pt.zcu.gpa, instruction); +} + +pub fn verifyTargetFeatures(isel: *Select) !void { + if (!verify_target_features) return; + + for (isel.instructions.items) |inst| { + if (Disassemble.decodeMnemonic(inst)) |decoded_mnemonic| { + switch (decoded_mnemonic) { + inline else => |mnemonic| { + const expected_features = @field(@import("inst_formats.zon").instructions, @tagName(mnemonic)).features; + inline for (@typeInfo(expected_features).@"struct".fields) |expected_feature_field| { + const expected_feature = @tagName(@field(expected_features, expected_feature_field.name)); + const std_feature = @field(std.Target.loongarch.Feature, expected_feature); + if (!isel.hasCpuFeature(std_feature)) { + wip_mir_log.err("emitted instruction {t} requires feature {t} which is not available", .{ mnemonic, std_feature }); + unreachable; + } + } + }, + } + } else { + wip_mir_log.err("invalid instruction was emitted in Select: {x}", .{inst.word}); + unreachable; + } + } +} + +fn hasCpuFeature(isel: *Select, feature: std.Target.loongarch.Feature) bool { + return std.Target.loongarch.featureSetHas(isel.target.cpu.features, feature); +} + +fn block( + isel: *Select, + air_inst_index: Air.Inst.Index, + res_ty: ZigType, + air_body: []const Air.Inst.Index, +) !void { + if (res_ty.toIntern() != .noreturn_type) { + const snapshot = try isel.takeLocationSnapshot(); + tracking_log.debug("block snapshot taken:\n{f}", .{snapshot}); + isel.active_blocks.putAssumeCapacityNoClobber(air_inst_index, .{ + .snapshot = snapshot, + .target_label = @intCast(isel.instructions.items.len), + }); + } + try isel.body(air_body); + if (res_ty.toIntern() != .noreturn_type) { + var block_entry = isel.active_blocks.pop().?; + assert(block_entry.key == air_inst_index); + block_entry.value.deinit(isel); + if (isel.live_values.fetchRemove(air_inst_index)) |result_vi| { + var res_walk = result_vi.value.walk(isel, .{}); + while (res_walk.next()) |res_part_vi| + _ = res_part_vi.takeLocationMarkWritten(isel); + result_vi.value.deref(isel); + } + } +} + +fn initValue(isel: *Select, ty: ZigType) error{OutOfMemory}!Value.Index { + const zcu = isel.pt.zcu; + try isel.values.ensureUnusedCapacity(zcu.gpa, 1); + try isel.value_types.ensureUnusedCapacity(zcu.gpa, 1); + return isel.initValueAdvanced(ty.abiAlignment(zcu), 0, ty.abiSize(zcu), ty); +} + +fn initValueAssumeCapacity(isel: *Select, ty: ZigType) Value.Index { + const zcu = isel.pt.zcu; + return isel.initValueAdvanced(ty.abiAlignment(zcu), 0, ty.abiSize(zcu), ty); +} + +fn initValueAdvanced( + isel: *Select, + parent_alignment: InternPool.Alignment, + offset_from_parent: u64, + size: u64, + ty: ?ZigType, +) Value.Index { + defer isel.values.addOneAssumeCapacity().* = .{ + .refs = 0, + .flags = .{ + .alignment = .fromLog2Units(@min(parent_alignment.toLog2Units(), @ctz(offset_from_parent))), + .parent_tag = .none, + // TODO size < 32 when vectors are supported + .location_tag = if (size <= 8) + .small + else if (std.math.cast(u32, size) != null) + .large + else + .extreme, + .parts_len_minus_one = 0, + .splitted = false, + }, + .offset_from_parent = offset_from_parent, + .parent_payload = .{ .none = {} }, + // TODO ditto + .location_payload = if (size <= 8) .{ .small = .{ + .flags = .{ + .size = @intCast(size), + .extension = .garbage, + .hint_modifier = .integer, + .hint_register = .zero, + .location_tag = .register, + }, + .location_payload = .{ .register = .zero }, + } } else if (std.math.cast(u32, size)) |size32| .{ .large = .{ + .size = size32, + .stack_slot = .unallocated, + } } else .{ .extreme = .{ .size = size } }, + .parts = undefined, + }; + defer isel.value_types.appendAssumeCapacity(ty orelse .{ .ip_index = .none }); + return @fromBackingInt(@intCast(isel.values.items.len)); +} + +const WhichValues = enum { only_referenced, all }; +pub fn dumpValues(isel: *Select, which: WhichValues) void { + dumpValuesInner(isel, which) catch |err| @panic(@errorName(err)); +} +fn dumpValuesInner(isel: *Select, which: WhichValues) !void { + const zcu = isel.pt.zcu; + const gpa = zcu.gpa; + const ip = &zcu.intern_pool; + const nav = ip.getNav(isel.nav_index); + + const locked_stderr = std.debug.lockStderr(&.{}); + defer std.debug.unlockStderr(); + const stderr = &locked_stderr.file_writer.interface; + + var reverse_live_values: std.AutoArrayHashMapUnmanaged(Value.Index, std.ArrayList(Air.Inst.Index)) = .empty; + defer { + for (reverse_live_values.values()) |*list| list.deinit(gpa); + reverse_live_values.deinit(gpa); + } + { + try reverse_live_values.ensureTotalCapacity(gpa, isel.live_values.count()); + var live_val_it = isel.live_values.iterator(); + while (live_val_it.next()) |live_val_entry| switch (live_val_entry.value_ptr.*) { + _ => { + const gop = reverse_live_values.getOrPutAssumeCapacity(live_val_entry.value_ptr.*); + if (!gop.found_existing) gop.value_ptr.* = .empty; + try gop.value_ptr.append(gpa, live_val_entry.key_ptr.*); + }, + .allocating, .free => unreachable, + }; + } + + var reverse_live_registers: std.AutoHashMapUnmanaged(Value.Index, Register) = .empty; + defer reverse_live_registers.deinit(gpa); + { + try reverse_live_registers.ensureTotalCapacity(gpa, @typeInfo(Register).@"enum".field_names.len); + var live_reg_it = isel.live_registers.iterator(); + while (live_reg_it.next()) |live_reg_entry| switch (live_reg_entry.value.*) { + _ => reverse_live_registers.putAssumeCapacityNoClobber(live_reg_entry.value.*, live_reg_entry.key), + .allocating, .free => {}, + }; + } + + var roots: std.AutoArrayHashMapUnmanaged(Value.Index, u32) = .empty; + defer roots.deinit(gpa); + { + try roots.ensureTotalCapacity(gpa, isel.values.items.len); + var vi: Value.Index = @fromBackingInt(@intCast(isel.values.items.len)); + iter_values: while (@backingInt(vi) > 0) { + vi = @fromBackingInt(@backingInt(vi) - 1); + if (which == .only_referenced and vi.get(isel).refs == 0) continue; + switch (vi.parent(isel)) { + .none, .constant => {}, + .value => continue :iter_values, + .address => |address_vi| roots.putAssumeCapacity(address_vi, 0), + } + roots.putAssumeCapacity(vi, 0); + } + } + + try stderr.print("# Begin LA ISelect Value Dump: {f}:\n", .{nav.fqn.fmt(ip)}); + while (roots.pop()) |root_entry| { + const vi = root_entry.key; + try stderr.splatByteAll(' ', 2 * (@as(usize, 1) + root_entry.value)); + try vi.format(stderr); + { + var first = true; + if (reverse_live_values.get(vi)) |aiis| for (aiis.items) |aii| { + if (aii == Block.main) { + try stderr.print("{s}%main", .{if (first) " <- " else ", "}); + } else { + try stderr.print("{s}%{d}", .{ if (first) " <- " else ", ", @backingInt(aii) }); + } + first = false; + }; + if (reverse_live_registers.get(vi)) |ra| { + try stderr.print("{s}{t}", .{ if (first) " <- " else ", ", ra }); + first = false; + } + } + try stderr.writeByte(':'); + try isel.printValueInfo(stderr, vi); + try stderr.writeByte('\n'); + + const value = vi.get(isel); + var part_index = value.flags.parts_len_minus_one; + if (part_index > 0) while (true) : (part_index -= 1) { + try roots.put( + gpa, + @fromBackingInt(@backingInt(value.parts) + part_index), + root_entry.value + 1, + ); + if (part_index == 0) break; + }; + } + try stderr.print("# End LA ISelect Value Dump: {f}\n", .{nav.fqn.fmt(ip)}); +} + +fn printValueAndParts(isel: *Select, writer: *std.Io.Writer, target_vi: Value.Index) !void { + const zcu = isel.pt.zcu; + const gpa = zcu.gpa; + + var roots: std.AutoArrayHashMapUnmanaged(Value.Index, u32) = .empty; + defer roots.deinit(gpa); + + var root_vi = target_vi; + while (true) switch (root_vi.parent(isel)) { + .none, .constant => break, + .value => |parent_vi| root_vi = parent_vi, + .address => |address_vi| break try roots.put(gpa, address_vi, 0), + }; + try roots.put(gpa, root_vi, 0); + + while (roots.pop()) |root_entry| { + const vi = root_entry.key; + try writer.splatByteAll(' ', 2 * root_entry.value); + try vi.format(writer); + try writer.writeByte(':'); + try isel.printValueInfo(writer, vi); + + const value = vi.get(isel); + var part_index = value.flags.parts_len_minus_one; + if (part_index > 0) while (true) : (part_index -= 1) { + try roots.put( + gpa, + @fromBackingInt(@backingInt(value.parts) + part_index), + root_entry.value + 1, + ); + if (part_index == 0) break; + }; + + if (roots.count() != 0) + try writer.writeByte('\n'); + } +} + +fn printValueInfo(isel: *Select, writer: *std.Io.Writer, vi: Value.Index) !void { + const zcu = isel.pt.zcu; + + const value = vi.get(isel); + switch (value.flags.parent_tag) { + .none => {}, + .value => try writer.print(" {f}+0x{x}", .{ value.parent_payload.value, value.offset_from_parent }), + .address => try writer.print(" {f}[0x{x}]", .{ value.parent_payload.address, value.offset_from_parent }), + .constant => try writer.print(" <{f}, {f}>", .{ + isel.fmtType(value.parent_payload.constant.typeOf(zcu)), + isel.fmtConstant(value.parent_payload.constant), + }), + } + try writer.print(" align({s})", .{@tagName(value.flags.alignment)}); + switch (value.flags.location_tag) { + .small => { + const loc_info = value.location_payload.small; + try writer.print(" {d}B", .{loc_info.flags.size}); + if (loc_info.flags.extension != .garbage) try writer.print(" {t}", .{loc_info.flags.extension}); + + var hints: u8 = 0; + if (loc_info.flags.hint_modifier != .integer) hints += 1; + if (loc_info.flags.hint_register != Register.zero) hints += 1; + if (hints != 0) try writer.writeAll(" hint="); + if (loc_info.flags.hint_modifier != .integer) try writer.print("{t}", .{loc_info.flags.hint_modifier}); + if (loc_info.flags.hint_register != Register.zero) try writer.print("{s}${t}", .{ if (hints != 1) "," else "", loc_info.flags.hint_register }); + + switch (loc_info.flags.location_tag) { + .register => { + if (loc_info.location_payload.register.reg != Register.zero) { + try writer.print(" loc={f}", .{loc_info.location_payload.register}); + } + }, + .stack_slot => try writer.print(" loc={f}", .{loc_info.location_payload.stack_slot}), + } + }, + .large => { + try writer.print(" {d}B large", .{value.location_payload.large.size}); + if (value.location_payload.large.stack_slot != Value.Indirect.unallocated) + try writer.print(" loc={f}", .{value.location_payload.large.stack_slot}); + }, + .extreme => try writer.print(" {d}B extreme", .{value.location_payload.large.size}), + } + if (value.flags.splitted) + try writer.writeAll(" splitted"); + if (value.refs != 0) + try writer.print(" refs={d}", .{value.refs}); + if (vi.typeOf(isel)) |ty| try writer.print(" {f}", .{isel.fmtType(ty)}); +} + +fn fmtValue(isel: *Select, vi: Value.Index) struct { + isel: *Select, + vi: Value.Index, + pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void { + data.isel.printValueAndParts(writer, data.vi) catch |err| switch (err) { + error.OutOfMemory => try writer.writeAll("OOM"), + error.WriteFailed => return error.WriteFailed, + }; + } +} { + return .{ .isel = isel, .vi = vi }; +} + +fn fmtLoopLive(isel: *Select, loop_inst: Air.Inst.Index) struct { + isel: *Select, + inst: Air.Inst.Index, + pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void { + const loops = data.isel.loops.values(); + const loop_index = data.isel.loops.getIndex(data.inst).?; + const live_insts = + data.isel.loop_outer_live.list.items[loops[loop_index].outer_live..loops[loop_index + 1].outer_live]; + + try writer.print("%{d} <- {{", .{@backingInt(data.inst)}); + var first = true; + for (live_insts) |live_inst| { + if (first) first = false else try writer.writeByte(','); + try writer.print(" %{d}", .{@backingInt(live_inst)}); + } + if (!first) try writer.writeByte(' '); + try writer.writeByte('}'); + } +} { + return .{ .isel = isel, .inst = loop_inst }; +} + +fn fmtType(isel: *Select, ty: ZigType) ZigType.Formatter { + return ty.fmt(isel.pt); +} + +fn fmtConstant(isel: *Select, constant: Constant) @typeInfo(@TypeOf(Constant.fmtValue)).@"fn".return_type.? { + return constant.fmtValue(isel.pt); +} + +fn fmtRegisterSet(regs: RegisterSet) struct { + regs: RegisterSet, + pub fn format(data: @This(), writer: *std.Io.Writer) std.Io.Writer.Error!void { + var it = data.regs.iterator(); + var first = true; + while (it.next()) |reg| { + if (first) first = false else try writer.writeAll(", "); + try writer.print("${t}", .{reg}); + } + if (first) try writer.writeAll("(empty)"); + } +} { + return .{ .regs = regs }; +} + +fn use(isel: *Select, air_ref: Air.Inst.Ref) !Value.Index { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + const vi, const ty = if (air_ref.toIndex()) |air_inst_index| vi_ty: { + const live_gop = try isel.live_values.getOrPut(zcu.gpa, air_inst_index); + if (live_gop.found_existing) return live_gop.value_ptr.*; + const ty = isel.air.typeOf(air_ref, ip); + const vi = try isel.initValue(ty); + tracking_log.debug("{f} <- %{d}", .{ vi, @backingInt(air_inst_index) }); + live_gop.value_ptr.* = vi.ref(isel); + break :vi_ty .{ vi, ty }; + } else vi_ty: { + const constant: Constant = .fromInterned(air_ref.toInterned().?); + const ty = constant.typeOf(zcu); + const vi = try isel.initValue(ty); + tracking_log.debug("{f} <- <{f}, {f}>", .{ + vi, + isel.fmtType(ty), + isel.fmtConstant(constant), + }); + vi.setParent(isel, .{ .constant = constant }); + break :vi_ty .{ vi, ty }; + }; + if (ty.isAbiInt(zcu)) { + const int_info = ty.intInfo(zcu); + if (int_info.bits <= 16) vi.setExtension(isel, .fromSignedness(int_info.signedness)); + } + return vi; +} + +// TODO: make r22 allocatable +fn isRegisterAllocatable(rd: Register) bool { + return switch (rd) { + else => true, + Register.zero, Register.tp, Register.sp, Register.fp, .r21 => false, + }; +} + +/// Frees a register by forgetting it. +/// Returns true on success, false on failure (i.e. dst_reg is locked/allocated or unallocatable). +fn forgetReg(isel: *Select, dst_reg: Register) error{ OutOfMemory, AlreadyReported }!bool { + if (!isRegisterAllocatable(dst_reg)) return false; + const dst_live_vi = isel.live_registers.getPtr(dst_reg); + const dst_vi = switch (dst_live_vi.*) { + _ => |dst_vi| dst_vi, + .allocating => return false, + .free => return true, + }; + tracking_log.debug("{f} -> location forgotten", .{dst_vi}); + _ = dst_vi.takeLocation(isel); + assert(dst_live_vi.* == .free); + return true; +} + +/// Frees a register by moving it to another place. +/// Returns true on success, false on failure (i.e. dst_reg is locked/allocated or unallocatable). +fn fillReg(isel: *Select, dst_reg: Register) error{ OutOfMemory, AlreadyReported }!bool { + if (!isRegisterAllocatable(dst_reg)) return false; + const dst_live_vi = isel.live_registers.getPtr(dst_reg); + const dst_vi = switch (dst_live_vi.*) { + _ => |dst_vi| dst_vi, + .allocating => return false, + .free => return true, + }; + const src_loc: Value.Location = src: { + if (dst_vi.hintRegister(isel)) |hint_reg| { + dst_live_vi.* = .allocating; + defer dst_live_vi.* = dst_vi; + if (try isel.fillReg(hint_reg)) { + isel.saved_registers.insert(hint_reg); + break :src .{ .register = .{ .mod = dst_vi.hintModifier(isel), .reg = hint_reg } }; + } + } + if (dst_vi.isSmall(isel)) { + switch (isel.tryAllocReg(dst_vi.hintModifier(isel).class())) { + .allocated => |reg| { + isel.freeReg(reg); + break :src .{ .register = .{ .mod = dst_vi.hintModifier(isel), .reg = reg } }; + }, + .fill_candidate, .out_of_registers => {}, + } + } + break :src .{ .stack_slot = dst_vi.allocStackSlot(isel) }; + }; + try dst_vi.moveTo(isel, src_loc); + assert(dst_live_vi.* == .free); + return true; +} + +/// Frees a set of register. If locked is true, these registers are then locked. +/// Requires all registers to be unlocked. +/// Returns true on success. +fn fillRegsBatch(isel: *Select, regs: RegisterSet, locking: bool) error{ OutOfMemory, AlreadyReported }!void { + tracking_log.debug("batch fill: {f}", .{fmtRegisterSet(regs)}); + // lock free registers + var regs_it = regs.iterator(); + while (regs_it.next()) |reg| { + const live_vi = isel.live_registers.getPtr(reg); + switch (live_vi.*) { + .allocating => unreachable, + .free => live_vi.* = .allocating, + _ => {}, // fill_candidate will be ignored by fillReg so there is no need to protect these values + } + } + + // fill registers + regs_it = regs.iterator(); + while (regs_it.next()) |reg| { + const live_vi = isel.live_registers.getPtr(reg); + switch (live_vi.*) { + .free => unreachable, + .allocating => {}, + _ => { + assert(try isel.fillReg(reg)); + live_vi.* = .allocating; + }, + } + } + + // unlock registers + if (!locking) { + regs_it = regs.iterator(); + while (regs_it.next()) |reg| { + const live_vi = isel.live_registers.getPtr(reg); + assert(live_vi.* == .allocating); + live_vi.* = .free; + } + } + + return; +} + +/// Frees a register by moving it to stack. +/// Returns true on success, false on failure (i.e. dst_reg is locked/allocated or unallocatable). +fn fillRegToMemory(isel: *Select, dst_reg: Register) error{ OutOfMemory, AlreadyReported }!bool { + if (!isRegisterAllocatable(dst_reg)) return false; + const dst_live_vi = isel.live_registers.getPtr(dst_reg); + const dst_vi = switch (dst_live_vi.*) { + _ => |dst_vi| dst_vi, + .allocating => return false, + .free => return true, + }; + try dst_vi.moveTo(isel, .{ .stack_slot = dst_vi.allocStackSlot(isel) }); + assert(dst_live_vi.* == .free); + return true; +} + +const TryAllocRegResult = union(enum) { + allocated: Register, + fill_candidate: Register, + out_of_registers, +}; + +fn tryAllocReg(isel: *Select, class: Register.Class) TryAllocRegResult { + return switch (class) { + .int => isel.tryAllocRegInRanges(&.{ + .{ .r4, .r11 }, // argument registers + .{ .r12, .r20 }, // temporary registers + .{ .r23, .r31 }, // static registers + .{ .r0, .r31 }, + }), + .fp => isel.tryAllocRegInRange(.{ .f0, .f31 }), + .fcc => isel.tryAllocRegInRange(.{ .fcc0, .fcc7 }), + }; +} + +fn tryAllocRegInRanges(isel: *Select, comptime ranges: []const struct { Register, Register }) TryAllocRegResult { + inline for (ranges[0 .. ranges.len - 1]) |range| { + switch (isel.tryAllocRegInRange(range)) { + .allocated => |reg| return .{ .allocated = reg }, + else => {}, + } + } + return isel.tryAllocRegInRange(ranges[ranges.len - 1]); +} + +fn tryAllocRegInRange(isel: *Select, range: struct { Register, Register }) TryAllocRegResult { + var failed_result: TryAllocRegResult = .out_of_registers; + var reg, const last_reg = range; + while (true) : (reg = @fromBackingInt(@backingInt(reg) + 1)) { + if (!isRegisterAllocatable(reg)) continue; + const live_vi = isel.live_registers.getPtr(reg); + switch (live_vi.*) { + _ => switch (failed_result) { + .allocated => unreachable, + .fill_candidate => {}, + .out_of_registers => failed_result = .{ .fill_candidate = reg }, + }, + .allocating => {}, + .free => { + live_vi.* = .allocating; + isel.saved_registers.insert(reg); + return .{ .allocated = reg }; + }, + } + if (reg == last_reg) return failed_result; + } +} + +fn allocReg(isel: *Select, class: Register.Class) !Register { + switch (isel.tryAllocReg(class)) { + .allocated => |reg| return reg, + .fill_candidate => |reg| { + assert(try isel.fillRegToMemory(reg)); + const live_vi = isel.live_registers.getPtr(reg); + assert(live_vi.* == .free); + live_vi.* = .allocating; + return reg; + }, + .out_of_registers => return isel.fail("ran out of {t} registers", .{class}), + } +} + +fn allocRegForWrite(isel: *Select, class: Register.Class) !Register { + const reg = try isel.allocReg(class); + isel.markRegWritten(reg); + return reg; +} + +fn markRegWritten(isel: *Select, reg: Register) void { + if (isel.active_loops.last()) |loop_index| { + const loop = loop_index.get(isel); + tracking_log.debug("${t} <- written", .{reg}); + loop.written_regs.insert(reg); + } +} + +fn markRegsWritten(isel: *Select, regs: RegisterSet) void { + if (isel.active_loops.last()) |loop_index| { + const loop = loop_index.get(isel); + tracking_log.debug("{f} <- written", .{fmtRegisterSet(regs)}); + loop.written_regs.setUnion(regs); + } +} + +const RegLock = struct { + reg: Register, + const empty: RegLock = .{ .reg = .zero }; + fn unlock(lock: RegLock, isel: *Select) void { + switch (lock.reg) { + else => |reg| isel.freeReg(reg), + Register.zero => {}, + } + } +}; + +fn lockReg(isel: *Select, reg: Register) RegLock { + assert(reg != Register.zero); + const live_vi = isel.live_registers.getPtr(reg); + assert(live_vi.* == .free); + live_vi.* = .allocating; + return .{ .reg = reg }; +} + +fn tryLockReg(isel: *Select, reg: Register) RegLock { + assert(reg != Register.zero); + const live_vi = isel.live_registers.getPtr(reg); + switch (live_vi.*) { + _ => { + isel.dumpValues(.all); + unreachable; + }, + .allocating => return .empty, + .free => { + live_vi.* = .allocating; + return .{ .reg = reg }; + }, + } +} + +fn freeReg(isel: *Select, reg: Register) void { + assert(reg != Register.zero); + const live_vi = isel.live_registers.getPtr(reg); + assert(live_vi.* == .allocating); + live_vi.* = .free; +} + +/// A snapshot of unresolved locations. +const LocationSnapshot = struct { + value_locs: std.MultiArrayList(Entry), + + const Entry = union(enum(u2)) { + none, + register: Register.Alias, + stack_slot: Value.Indirect, + }; + + const empty: LocationSnapshot = .{ .value_locs = .empty }; + + fn deinit(snap: *LocationSnapshot, isel: *Select) void { + const gpa = isel.pt.zcu.gpa; + snap.value_locs.deinit(gpa); + snap.* = undefined; + } + + /// Merges the captured locations and current expected locations. + fn merge(snap: *const LocationSnapshot, isel: *Select) !void { + const captured_locs = snap.value_locs.slice(); + for (0..snap.value_locs.len) |i| { + const vi: Value.Index = @fromBackingInt(@intCast(i)); + const captured_loc: Value.Location = switch (captured_locs.get(i)) { + .none => continue, + .register => |captured_ra| .{ .register = captured_ra }, + .stack_slot => |captured_stack| .{ .stack_slot = captured_stack }, + }; + if (vi.location(isel)) |current_loc| { + if (std.meta.eql(captured_loc, current_loc)) continue; + } + tracking_log.debug("{f} <- {f} (snapshot merge)", .{ vi, captured_loc }); + + if (captured_loc.asRegister()) |captured_reg| assert(try isel.fillReg(captured_reg)); + try vi.moveTo(isel, captured_loc); + } + } + + pub fn format(snap: LocationSnapshot, w: *std.Io.Writer) std.Io.Writer.Error!void { + const captured_locs = snap.value_locs.slice(); + var first = true; + for (0..snap.value_locs.len) |i| { + const vi: Value.Index = @fromBackingInt(@intCast(i)); + const captured_loc = captured_locs.get(i); + if (captured_loc == .none) continue; + if (first) first = false else try w.writeAll("\n"); + switch (captured_loc) { + .none => unreachable, + .register => |captured_ra| try w.print(" {f} <- {f}", .{ vi, captured_ra }), + .stack_slot => |captured_stack| try w.print(" {f} <- {f}", .{ vi, captured_stack }), + } + } + if (first) return w.writeAll("(empty)"); + } +}; + +fn takeLocationSnapshot(isel: *Select) !LocationSnapshot { + const gpa = isel.pt.zcu.gpa; + var snapshot: LocationSnapshot = .empty; + try snapshot.value_locs.resize(gpa, isel.values.items.len); + + for (0..isel.values.items.len) |i| { + const vi: Value.Index = @fromBackingInt(@intCast(i)); + if (vi.location(isel)) |vi_loc| { + snapshot.value_locs.set(i, switch (vi_loc) { + .register => |vi_ra| if (vi_ra.reg == Register.zero) .none else .{ .register = vi_ra }, + .stack_slot => |vi_stack| .{ .stack_slot = vi_stack }, + }); + } else { + snapshot.value_locs.set(i, .none); + } + } + + if (std.debug.runtime_safety) { + var live_vi_it = isel.live_registers.iterator(); + while (live_vi_it.next()) |live_vi| { + if (live_vi.value.* == .allocating) { + tracking_log.debug("{t} is still locked when taking snapshot", .{live_vi.key}); + unreachable; + } + } + } + + return snapshot; +} + +/// Ways to treat bits in destination registers that may not be affected by an operation. +const DestProtection = enum { + /// Unrelated bits must be preserved. + preserved, + /// Unrelated bits may be destroyed. + none, + /// Unrelated bits must be filled with 0. + wiped, +}; + +fn fillUnusedBits(isel: *Select, rd: Register, rj: Register, dst_mode: Value.Extension, src_mode: Value.Extension, unused_bits: u9) !void { + const gpr_bits = isel.gprBits(); + const used_bits = gpr_bits - unused_bits; + wip_mir_log.debug(" | # fillUnusedBits {t}, {t}, {d} bits, {t} -> {t}", .{ rd, rj, used_bits, src_mode, dst_mode }); + + if (used_bits == gpr_bits or src_mode == dst_mode) { + if (rd != rj) try isel.emit(.ori(rd, rj, 0)); + return; + } + switch (dst_mode) { + .garbage => {}, + .sign_ext => { + if (used_bits >= gpr_bits) return isel.fail("too many used bits", .{}); + switch (used_bits) { + 8 => try isel.emit(.@"sext.b"(rd, rj)), + 16 => try isel.emit(.@"sext.h"(rd, rj)), + 32 => try isel.emit(.@"addi.w"(rd, rj, 0)), + 0...7, 9...15, 17...31, 33...63 => { + try isel.emit(.@"srai.d"(rd, rd, @intCast(gpr_bits - used_bits))); + try isel.emit(.@"slli.d"(rd, rj, @intCast(gpr_bits - used_bits))); + }, + else => unreachable, + } + }, + .zero_ext => { + if (used_bits >= gpr_bits) return isel.fail("too many used bits", .{}); + switch (used_bits) { + 1...31 => try isel.emit(.@"bstrpick.w"(rd, rj, @intCast(used_bits - 1), 0)), + 32...63 => try isel.emit(.@"bstrpick.d"(rd, rj, @intCast(used_bits - 1), 0)), + else => unreachable, + } + }, + } +} + +/// Loads from memory [base + offset] to register +fn loadReg( + isel: *Select, + dst: Register, + size: u64, + signedness: std.builtin.Signedness, + base: Register, + offset: i65, +) !void { + if (dst.class() != .int) return isel.fail("TODO loadReg {t}", .{dst}); + switch (size) { + 0 => unreachable, + 1 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(switch (signedness) { + .signed => .@"ld.b"(dst, base, small_off), + .unsigned => .@"ld.bu"(dst, base, small_off), + }); + }, + 2 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(switch (signedness) { + .signed => .@"ld.h"(dst, base, small_off), + .unsigned => .@"ld.hu"(dst, base, small_off), + }); + }, + 4 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(switch (signedness) { + .signed => .@"ld.w"(dst, base, small_off), + .unsigned => .@"ld.wu"(dst, base, small_off), + }); + if (signedness == .signed) if (std.math.cast(i16, offset)) |small_off| { + if ((small_off & 0b11) == 0) { + return isel.emit(.@"ldox4.w"(dst, base, @intCast(@divExact(small_off, 4)))); + } + }; + }, + 8 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(.@"ld.d"(dst, base, small_off)); + if (std.math.cast(i16, offset)) |small_off| { + if ((small_off & 0b11) == 0) { + return isel.emit(.@"ldox4.d"(dst, base, @intCast(@divExact(small_off, 4)))); + } + } + }, + else => return try isel.failUnimplemented("bad load size: {d}", .{size}), + } + + const ptr_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(ptr_reg); + switch (size) { + 1 => try isel.emit(switch (signedness) { + .signed => .@"ldx.b"(dst, base, ptr_reg), + .unsigned => .@"ldx.bu"(dst, base, ptr_reg), + }), + 2 => try isel.emit(switch (signedness) { + .signed => .@"ldx.h"(dst, base, ptr_reg), + .unsigned => .@"ldx.hu"(dst, base, ptr_reg), + }), + 4 => try isel.emit(switch (signedness) { + .signed => .@"ldx.w"(dst, base, ptr_reg), + .unsigned => .@"ldx.wu"(dst, base, ptr_reg), + }), + 8 => try isel.emit(.@"ldx.d"(dst, base, ptr_reg)), + else => { + try isel.loadReg(dst, size, signedness, ptr_reg, 0); + try isel.emit(.@"add.d"(ptr_reg, ptr_reg, base)); + }, + } + try isel.moveIntImm(ptr_reg, std.math.cast(i64, offset) orelse return isel.fail("unimplemented load with large offset", .{})); +} + +/// Stores a register to memory [base + offset] +fn storeReg( + isel: *Select, + src: Register, + size: u64, + base: Register, + offset: i65, +) !void { + if (src.class() != .int) return isel.fail("TODO storeReg {t}", .{src}); + switch (size) { + 0 => unreachable, + 1 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(.@"st.b"(src, base, small_off)); + }, + 2 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(.@"st.h"(src, base, small_off)); + }, + 4 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(.@"st.w"(src, base, small_off)); + if (std.math.cast(i16, offset)) |small_off| { + if ((small_off & 0b11) == 0) { + return isel.emit(.@"stox4.w"(src, base, @intCast(@divExact(small_off, 4)))); + } + } + }, + 8 => { + if (std.math.cast(i12, offset)) |small_off| return isel.emit(.@"st.d"(src, base, small_off)); + if (std.math.cast(i16, offset)) |small_off| { + if ((small_off & 0b11) == 0) { + return isel.emit(.@"stox4.d"(src, base, @intCast(@divExact(small_off, 4)))); + } + } + }, + else => return try isel.failUnimplemented("bad store size: {d}", .{size}), + } + + if (std.math.cast(i64, offset)) |offset64| stx: { + const ptr_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(ptr_reg); + switch (size) { + 1 => try isel.emit(.@"stx.b"(src, base, ptr_reg)), + 2 => try isel.emit(.@"stx.h"(src, base, ptr_reg)), + 4 => try isel.emit(.@"stx.w"(src, base, ptr_reg)), + 8 => try isel.emit(.@"stx.d"(src, base, ptr_reg)), + else => break :stx, + } + try isel.moveIntImm(ptr_reg, offset64); + } + + const ptr_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(ptr_reg); + try isel.storeReg(src, size, ptr_reg, 0); + try isel.emit(if (offset > 0) .@"add.d"(ptr_reg, ptr_reg, base) else .@"sub.d"(ptr_reg, ptr_reg, base)); + try isel.moveIntImm(ptr_reg, @intCast(@abs(offset))); +} + +/// Copies a part of a register to another. +fn moveReg( + isel: *Select, + dst_ra: Register.Alias, + dst_bit_off: u9, + src_ra: Register.Alias, + src_bit_off: u9, + bit_size: u16, + init_dst_prot: DestProtection, +) !void { + if (dst_ra.reg == src_ra.reg and dst_bit_off == src_bit_off) return; + if (bit_size == 0) return; + assert(init_dst_prot != .preserved or (isel.live_registers.get(dst_ra.reg) == .allocating)); + assert(isel.live_registers.get(src_ra.reg) == .allocating); + + const dst_ra_bit_size = dst_ra.mod.bitSize(isel.target); + const src_ra_bit_size = src_ra.mod.bitSize(isel.target); + const dst_msb_plus_one = dst_bit_off + bit_size; + const src_msb_plus_one = src_bit_off + bit_size; + assert(dst_msb_plus_one <= dst_ra_bit_size and src_msb_plus_one <= src_ra_bit_size); + + const dst_prot: DestProtection = switch (init_dst_prot) { + .preserved => if (bit_size == dst_ra_bit_size) .none else .preserved, + else => init_dst_prot, + }; + + const dst_lock = isel.tryLockReg(dst_ra.reg); + defer dst_lock.unlock(isel); + const src_lock = isel.tryLockReg(src_ra.reg); + defer src_lock.unlock(isel); + + switch (dst_ra.mod) { + .integer => switch (src_ra.mod) { + .integer => { + if (dst_bit_off == src_bit_off and dst_prot == .none) + return try isel.emit(.ori(dst_ra.reg, src_ra.reg, 0)); + // bstrins + const tmp_reg = tmp_reg: { + if (dst_bit_off == 0 and dst_prot != .none) break :tmp_reg dst_ra.reg; + const tmp_reg = if (src_bit_off == 0) src_ra.reg else try isel.allocRegForWrite(.int); + const dst_msbw = dst_msb_plus_one - 1; + try isel.emit(switch (dst_ra_bit_size) { + 32 => .@"bstrins.w"(dst_ra.reg, tmp_reg, @intCast(dst_msbw), @intCast(dst_bit_off)), + 64 => .@"bstrins.d"(dst_ra.reg, tmp_reg, @intCast(dst_msbw), @intCast(dst_bit_off)), + else => unreachable, + }); + break :tmp_reg tmp_reg; + }; + defer if (tmp_reg != dst_ra.reg and tmp_reg != src_ra.reg) isel.freeReg(tmp_reg); + // bstrpick + const src_msbw = src_msb_plus_one - 1; + try isel.emit(switch (dst_ra_bit_size) { + 32 => .@"bstrpick.w"(tmp_reg, src_ra.reg, @intCast(src_msbw), @intCast(src_bit_off)), + 64 => .@"bstrpick.d"(tmp_reg, src_ra.reg, @intCast(src_msbw), @intCast(src_bit_off)), + else => unreachable, + }); + }, + else => return isel.fail("unimplemented non-integral moveReg", .{}), + }, + else => return isel.fail("unimplemented non-integral moveReg", .{}), + } +} + +/// Moves an immediate to a register. +fn moveIntImm(isel: *Select, rd: Register, si64: i64) !void { + wip_mir_log.debug(" | # moveImm {t} <- 0x{x}", .{ rd, si64 }); + if (std.math.cast(u12, si64)) |imm12| return isel.emit(.ori(rd, .zero, imm12)); + + const ori12: u12 = @truncate(@as(u64, @bitCast(si64))); + const lu12i20: i20 = @truncate(si64 >> 12); + const use_lu12iw = lu12i20 != 0; + const lu32i20: i20 = @truncate(si64 >> 32); + const use_lu32id = lu32i20 != hi: { + if (use_lu12iw) break :hi @as(i20, @intCast(@as(i1, @truncate(si64 >> 31)))); + break :hi 0; + }; + const lu52i12: i12 = @truncate(si64 >> 52); + const use_lu52id = lu52i12 != hi: { + if (use_lu32id) break :hi @as(i12, @intCast(@as(i1, @truncate(si64 >> 51)))); + if (use_lu12iw) break :hi @as(i12, @intCast(@as(i1, @truncate(si64 >> 31)))); + break :hi 0; + }; + const use_ori = (ori12 != 0) or (!use_lu12iw and use_lu32id) or si64 == 0; + const ori_rj = if (use_lu12iw) rd else Register.zero; + const lu52id_rj = if (use_ori or use_lu12iw) rd else Register.zero; + + if (use_lu52id) try isel.emit(.@"cu52i.d"(rd, lu52id_rj, lu52i12)); + if (use_lu32id) try isel.emit(.@"cu32i.d"(rd, lu32i20)); + if (use_ori) try isel.emit(.ori(rd, ori_rj, ori12)); + if (use_lu12iw) try isel.emit(.@"lu12i.w"(rd, lu12i20)); +} + +fn addImm(isel: *Select, rd: Register, rj: Register, si65: i65) !void { + const gpr_size = isel.gprSize(); + if (si65 == 0) { + try isel.emit(.ori(rd, rj, 0)); + } else if (std.math.cast(i12, si65)) |si12| { + switch (gpr_size) { + 4 => try isel.emit(.@"addi.w"(rd, rj, si12)), + 8 => try isel.emit(.@"addi.d"(rd, rj, si12)), + else => unreachable, + } + } else { + if (si65 >= 0) switch (gpr_size) { + 4 => try isel.emit(.@"add.w"(rd, rd, rj)), + 8 => try isel.emit(.@"add.d"(rd, rd, rj)), + else => unreachable, + } else switch (gpr_size) { + 4 => try isel.emit(.@"sub.w"(rd, rd, rj)), + 8 => try isel.emit(.@"sub.d"(rd, rd, rj)), + else => unreachable, + } + try isel.moveIntImm(rd, @bitCast(@as(u64, @truncate(@as(u65, @bitCast(si65)))))); + } +} + +/// Loads the incoming value of a register. +fn ldIncoming(isel: *Select, rd: Register, rj: Register) !void { + wip_mir_log.debug(" | # ldIncoming {t} <- {t}", .{ rd, rj }); + try isel.layout_relocs.append(isel.pt.zcu.gpa, @intCast(isel.instructions.items.len)); + try isel.emit(.ori(rd, rj, 0)); +} + +fn cmp( + isel: *Select, + res_reg: Register, + ty: ZigType, + lhs_vi: Value.Index, + op: std.math.CompareOperator, + rhs_vi: Value.Index, +) !void { + wip_mir_log.debug(" | # cmp {f}, {t}, {f}, {t}, {f}", .{ isel.fmtType(ty), res_reg, lhs_vi, op, rhs_vi }); + if (!ty.isRuntimeFloat() and !ty.isArrayOrVector(isel.pt.zcu)) { + // integeral comparison + const int_info: std.builtin.Type.Int = if (ty.toIntern() == .bool_type) + .{ .signedness = .unsigned, .bits = 1 } + else if (ty.isAbiInt(isel.pt.zcu)) + ty.intInfo(isel.pt.zcu) + else if (ty.isPtrAtRuntime(isel.pt.zcu)) + .{ .signedness = .unsigned, .bits = 64 } + else + return isel.fail("bad cmp_{t} {f}", .{ op, isel.fmtType(ty) }); + + var part_offset = lhs_vi.size(isel); + while (part_offset > 0) { + const part_size = @min(part_offset, isel.gprSize()); + part_offset -= part_size; + // TODO optimize constant cmp + // TODO relax LHS and RHS extension mode requirements to != .garbage + const lhs_part_vi = try lhs_vi.partExact(isel, part_offset, part_size); + const lhs_part_mat = try lhs_part_vi.matIntRegZeroExt(isel); + const lhs_part_reg = lhs_part_mat.reg(); + const rhs_part_vi = try rhs_vi.partExact(isel, part_offset, part_size); + const rhs_part_mat = try rhs_part_vi.matIntRegZeroExt(isel); + const rhs_part_reg = rhs_part_mat.reg(); + + const res_part_reg = if (part_offset == 0) res_reg else res_part_reg: { + const res_part_reg = try isel.allocRegForWrite(.int); + try isel.emit(.@"or"(res_reg, res_reg, res_part_reg)); + break :res_part_reg res_part_reg; + }; + defer if (res_part_reg != res_reg) isel.freeReg(res_part_reg); + + switch (op) { + .eq => { + try isel.emit(.sltui(res_part_reg, res_part_reg, 1)); + try isel.emit(.xor(res_part_reg, lhs_part_reg, rhs_part_reg)); + }, + .neq => { + try isel.emit(.sltu(res_part_reg, .zero, res_part_reg)); + try isel.emit(.xor(res_part_reg, lhs_part_reg, rhs_part_reg)); + }, + .lt, .lte, .gt, .gte => { + var rj = lhs_part_reg; + var rk = rhs_part_reg; + + switch (op) { + .lte, .gt => std.mem.swap(Register, &rj, &rk), + else => {}, + } + switch (op) { + .lte, .gte => try isel.emit(.xori(res_part_reg, res_part_reg, 1)), + else => {}, + } + + try isel.emit(switch (int_info.signedness) { + .signed => .slt(res_part_reg, rj, rk), + .unsigned => .sltu(res_part_reg, rj, rk), + }); + }, + } + try rhs_part_mat.finish(isel); + try lhs_part_mat.finish(isel); + } + } else return isel.fail("bad cmp_{t} {f}", .{ op, isel.fmtType(ty) }); +} + +const AddOrSubtractOptions = struct { + overflow: Overflow, + + const Overflow = union(enum) { + @"unreachable", + panic: Zcu.SimplePanicId, + wrap, + reg: Register, + }; +}; + +// TODO optimize constant add/sub +fn addOrSubtract( + isel: *Select, + ty: ZigType, + res_vi: Value.Index, + op: enum { add, sub }, + lhs_vi: Value.Index, + rhs_vi: Value.Index, + opts: AddOrSubtractOptions, +) !void { + wip_mir_log.debug(" | # {t} ty = {f}, res = {f}, lhs = {f}, rhs = {f}, overflow = {t}", .{ op, isel.fmtType(ty), res_vi, lhs_vi, rhs_vi, opts.overflow }); + // TODO: implement opts.overflow + const zcu = isel.pt.zcu; + assert(ty.isAbiInt(zcu)); + const int_info = ty.intInfo(zcu); + + if (int_info.bits <= 32) { + try res_vi.reextendToGarbage(isel); // TODO optimize + const res_reg = try res_vi.defRegMod(isel, .integer) orelse return; + const lhs_mat = try lhs_vi.matIntRegZeroExt(isel); + const rhs_mat = try rhs_vi.matIntRegZeroExt(isel); + + switch (op) { + .add => try isel.emit(.@"add.w"(res_reg, lhs_mat.reg(), rhs_mat.reg())), + .sub => try isel.emit(.@"sub.w"(res_reg, lhs_mat.reg(), rhs_mat.reg())), + } + + try lhs_mat.finish(isel); + try rhs_mat.finish(isel); + } else if (int_info.bits <= 64) { + try res_vi.reextendToGarbage(isel); // TODO optimize + const res_reg = try res_vi.defRegMod(isel, .integer) orelse return; + const lhs_mat = try lhs_vi.matIntRegZeroExt(isel); + const rhs_mat = try rhs_vi.matIntRegZeroExt(isel); + + switch (op) { + .add => try isel.emit(.@"add.d"(res_reg, lhs_mat.reg(), rhs_mat.reg())), + .sub => try isel.emit(.@"sub.d"(res_reg, lhs_mat.reg(), rhs_mat.reg())), + } + + try lhs_mat.finish(isel); + try rhs_mat.finish(isel); + } else { + if (debug_trap_unimplemented_code) { + isel.wipeLocationDfs(res_vi); + } + return try isel.failUnimplemented("unimplemented {t} {f}", .{ op, isel.fmtType(ty) }); + } +} + +/// elem_ptr = base +- elem_size * index +/// elem_ptr, base, and index may alias. base_reg must be locked. +fn elemPtr( + isel: *Select, + rd: Register, + base_reg: Register, + op: enum { add, sub }, + elem_size: u64, + index_vi: Value.Index, +) !void { + assert(isel.live_registers.get(base_reg) == .allocating); + wip_mir_log.debug(" | # elemPtr {t} = {t} {s} {f} * {d} (= 0b{b})", .{ rd, base_reg, switch (op) { + .add => "+", + .sub => "-", + }, index_vi, elem_size, elem_size }); + switch (@popCount(elem_size)) { + 0 => unreachable, // Sema should optimize this + 1 => { + const shift = @ctz(elem_size); + if (shift == 0) { + const index_mat = try index_vi.matIntRegZeroExt(isel); + const index_reg = index_mat.reg(); + try isel.emit(switch (op) { + .add => switch (isel.gprBits()) { + else => unreachable, + 32 => .@"add.w"(rd, base_reg, index_reg), + 64 => .@"add.d"(rd, base_reg, index_reg), + }, + .sub => switch (isel.gprBits()) { + else => unreachable, + 32 => .@"sub.w"(rd, base_reg, index_reg), + 64 => .@"sub.d"(rd, base_reg, index_reg), + }, + }); + try index_mat.finish(isel); + return; + } else if (std.math.cast(u2, shift - 1)) |sa2| { + switch (op) { + .add => { + const index_mat = try index_vi.matIntRegZeroExt(isel); + const index_reg = index_mat.reg(); + try isel.emit(switch (isel.gprBits()) { + else => unreachable, + 32 => .@"sladd.w"(rd, index_reg, base_reg, sa2), + 64 => .@"sladd.d"(rd, index_reg, base_reg, sa2), + }); + try index_mat.finish(isel); + return; + }, + .sub => { + if (base_reg != rd) { + const index_mat = try index_vi.matIntRegZeroExt(isel); + const index_reg = index_mat.reg(); + switch (isel.gprBits()) { + else => unreachable, + 32 => { + try isel.emit(.@"sladd.w"(rd, rd, base_reg, sa2)); + try isel.emit(.@"sub.w"(rd, .zero, index_reg)); + }, + 64 => { + try isel.emit(.@"sladd.d"(rd, rd, base_reg, sa2)); + try isel.emit(.@"sub.d"(rd, .zero, index_reg)); + }, + } + try index_mat.finish(isel); + return; + } + }, + } + } + }, + 2 => { + const shift1 = @ctz(elem_size); + const mask1 = @as(u64, 1) << @intCast(shift1); + const mask2 = elem_size & ~mask1; + + if ((op == .add or base_reg != rd) and mask1 <= 4 and mask2 <= 4) { + try isel.elemPtr(rd, rd, op, mask2, index_vi); + try isel.elemPtr(rd, base_reg, op, mask1, index_vi); + return; + } + }, + else => {}, + } + + const index_mat = try index_vi.matIntRegZeroExt(isel); + const index_reg = index_mat.reg(); + const offset_reg = if (base_reg != rd) rd else try isel.allocRegForWrite(.int); + defer if (offset_reg != rd) isel.freeReg(offset_reg); + try isel.emit(switch (op) { + .add => switch (isel.gprBits()) { + else => unreachable, + 32 => .@"add.w"(rd, base_reg, offset_reg), + 64 => .@"add.d"(rd, base_reg, offset_reg), + }, + .sub => switch (isel.gprBits()) { + else => unreachable, + 32 => .@"sub.w"(rd, base_reg, offset_reg), + 64 => .@"sub.d"(rd, base_reg, offset_reg), + }, + }); + try isel.emit(switch (isel.gprBits()) { + else => unreachable, + 32 => .@"mul.w"(offset_reg, offset_reg, index_reg), + 64 => .@"mul.d"(offset_reg, offset_reg, index_reg), + }); + try isel.moveIntImm(offset_reg, @bitCast(elem_size)); + try index_mat.finish(isel); +} + +fn moveLoc( + isel: *Select, + dst_loc: Value.Location, + dst_off: u64, + src_loc: Value.Location, + src_off: u64, + size: u64, + dst_prot: DestProtection, +) !void { + if (dst_loc.isUnallocated()) return; + if (std.meta.eql(dst_loc, src_loc) and dst_off == src_off) return; + if (size == 0) return; + assert(!src_loc.isUnallocated()); + wip_mir_log.debug(" | # move {f}[{d}] <- {f}[{d}], {d}B, dst prot={t}", .{ + dst_loc, + dst_off, + src_loc, + src_off, + size, + dst_prot, + }); + + const dst_lock: RegLock = if (dst_prot != .preserved) .empty else dst_loc.tryLock(isel); + defer dst_lock.unlock(isel); + const src_lock = src_loc.tryLock(isel); + defer src_lock.unlock(isel); + + switch (dst_loc) { + .register => |dst_ra| switch (src_loc) { + .register => |src_ra| try isel.moveReg( + dst_ra, + @intCast(dst_off * 8), + src_ra, + @intCast(src_off * 8), + @intCast(size * 8), + dst_prot, + ), + .stack_slot => |src_stack| { + const tmp_reg = if (dst_ra.mod == .integer and dst_off == 0) + dst_ra.reg + else + try isel.allocRegForWrite(.int); + defer if (tmp_reg != dst_ra.reg) isel.freeReg(tmp_reg); + try isel.moveReg( + dst_ra, + @intCast(dst_off * 8), + .{ .reg = tmp_reg, .mod = .integer }, + 0, + @intCast(size * 8), + dst_prot, + ); + try isel.loadReg( + tmp_reg, + memOpSizeFitting(size), + .unsigned, + src_stack.base, + src_stack.offset + @as(i65, src_off), + ); + }, + }, + .stack_slot => |dst_stack| { + if (size > isel.gprSize()) { + // large memory copies, src must be stack_slot + const src_stack = src_loc.stack_slot; + // TODO optimize to memmove call + + const known_direction, const gen_low_to_high, const gen_high_to_low = move_dir: { + if (dst_stack.base == src_stack.base) { + if (dst_stack.offset == src_stack.offset) return; + break :move_dir if (dst_stack.offset < src_stack.offset) + .{ true, false, true } + else + .{ true, true, false }; + } + // cannot determine direction + if (assume_memmove_no_overlap) + break :move_dir .{ true, true, false }; + break :move_dir .{ false, true, true }; + }; + if (!known_direction) { + return isel.failUnimplemented("TODO moveLoc memmove", .{}); + } + + const gpr_size = isel.gprSize(); + const steps = std.math.divCeil(u64, size, gpr_size) catch unreachable; + if (gen_low_to_high) { + var off: u64 = 0; + for (0..@intCast(steps)) |_| { + try isel.moveLoc(dst_loc, dst_off + off, src_loc, src_off + off, gpr_size, dst_prot); + off += gpr_size; + } + } + if (gen_high_to_low) { + var off: u64 = steps * gpr_size; + for (0..@intCast(steps)) |_| { + off -= gpr_size; + try isel.moveLoc(dst_loc, dst_off + off, src_loc, src_off + off, gpr_size, dst_prot); + } + } + + return; + } + + // Move to a temp reg + store + // If size is not direct mem op size and !kill_dst, old values have to + // be loaded first. + const memop_size = memOpSizeFitting(size); + const need_load = memop_size != size; + const tmp_reg, const tmp_allocated = tmp_reg: { + if (src_off == 0 and !need_load) { + switch (src_loc) { + .register => |src_ra| if (src_ra.mod == .integer) + break :tmp_reg .{ src_ra.reg, false }, + else => {}, + } + } + break :tmp_reg .{ try isel.allocRegForWrite(.int), true }; + }; + defer if (tmp_allocated) isel.freeReg(tmp_reg); + + const dst_stack_off = dst_stack.offset + @as(i65, dst_off); + try isel.storeReg(tmp_reg, memop_size, dst_stack.base, dst_stack_off); + if (tmp_allocated) + try isel.moveLoc( + .{ .register = .{ .reg = tmp_reg, .mod = .integer } }, + 0, + src_loc, + src_off, + size, + if (need_load) .preserved else .none, + ); + if (need_load) + try isel.loadReg(tmp_reg, memop_size, .unsigned, dst_stack.base, dst_stack_off); + }, + } +} + +fn moveUndef(isel: *Select, dst_loc: Value.Location, size: u64) !void { + if (isel.opt_mode == .fast or isel.opt_mode == .small) return; + wip_mir_log.debug(" | # move {f} ({d}B) <- undef", .{ dst_loc, size }); + switch (dst_loc) { + .register => |dst_ra| { + assert(dst_ra.mod == .integer); // TODO + try isel.moveIntImm(dst_ra.reg, switch (isel.gprBits()) { + 32 => 0xAAAAAAAA, + 64 => @bitCast(@as(u64, 0xAAAAAAAAAAAAAAAA)), + else => unreachable, + }); + }, + .stack_slot => { + // TODO write undef to memory + }, + } +} + +fn moveConstant(isel: *Select, dst: Value.Location, init_constant: Constant, init_offset: u64, size: u64) !void { + wip_mir_log.debug(" | # move {f} <- {f} [{d}..{d}]", .{ dst, isel.fmtConstant(init_constant), init_offset, init_offset + size - 1 }); + var offset = init_offset; + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + var constant = init_constant.toIntern(); + var constant_key = ip.indexToKey(constant); + while (true) { + // Try to coerce the constant value + // also try better codegen + constant_key: switch (constant_key) { + else => {}, + .undef => return try isel.moveUndef(dst, size), + .simple_value => |simple_value| switch (simple_value) { + .void => {}, + .null, .@"unreachable" => unreachable, + .true => continue :constant_key .{ .int = .{ .ty = .bool_type, .storage = .{ .u64 = 1 } } }, + .false => continue :constant_key .{ .int = .{ .ty = .bool_type, .storage = .{ .u64 = 0 } } }, + }, + .int => |int| if (dst.asRegisterAlias()) |dst_ra| { + if (dst_ra.mod != .integer) break :constant_key; + const dst_reg = dst_ra.reg; + return switch (int.storage) { + .u64 => |imm| try isel.moveIntImm(dst_reg, @bitCast(std.math.shr(u64, imm, 8 * offset))), + .i64 => |imm| switch (size) { + else => unreachable, + 1...4 => try isel.moveIntImm(dst_reg, @as(u32, @bitCast(@as(i32, @truncate(std.math.shr(i64, imm, 8 * offset)))))), + 5...8 => try isel.moveIntImm(dst_reg, @bitCast(std.math.shr(i64, imm, 8 * offset))), + }, + .big_int => |big_int| { + assert(size == isel.gprSize()); + var imm: u64 = 0; + const limb_bits = @bitSizeOf(std.math.big.Limb); + const limbs = @divExact(64, limb_bits); + var limb_index: usize = @intCast(@divExact(offset, @divExact(limb_bits, 8)) + limbs); + for (0..limbs) |_| { + limb_index -= 1; + if (limb_index >= big_int.limbs.len) continue; + if (limb_bits < 64) imm <<= limb_bits; + imm |= big_int.limbs[limb_index]; + } + if (!big_int.positive) { + limb_index = @min(limb_index, big_int.limbs.len); + imm = while (limb_index > 0) { + limb_index -= 1; + if (big_int.limbs[limb_index] != 0) break ~imm; + } else -%imm; + } + try isel.moveIntImm(dst_reg, @bitCast(imm)); + }, + }; + }, + .err => |err| continue :constant_key .{ .int = .{ + .ty = err.ty, + .storage = .{ .u64 = ip.getErrorValueIfExists(err.name).? }, + } }, + .error_union => |error_union| { + const error_union_type = ip.indexToKey(error_union.ty).error_union_type; + const error_set_ty: ZigType = .fromInterned(error_union_type.error_set_type); + const payload_ty: ZigType = .fromInterned(error_union_type.payload_type); + const error_set_offset = codegen.errUnionErrorOffset(payload_ty, zcu); + const error_set_size = error_set_ty.abiSize(zcu); + if (offset >= error_set_offset and offset + size <= error_set_offset + error_set_size) { + offset -= error_set_offset; + continue :constant_key switch (error_union.val) { + .err_name => |err_name| .{ .err = .{ + .ty = error_union_type.error_set_type, + .name = err_name, + } }, + .payload => .{ .int = .{ + .ty = error_union_type.error_set_type, + .storage = .{ .u64 = 0 }, + } }, + }; + } + const payload_offset = codegen.errUnionPayloadOffset(payload_ty, zcu); + const payload_size = payload_ty.abiSize(zcu); + if (offset >= payload_offset and offset + size <= payload_offset + payload_size) { + offset -= payload_offset; + switch (error_union.val) { + .err_name => continue :constant_key .{ .undef = error_union_type.payload_type }, + .payload => |payload| { + constant = payload; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + }, + } + } + }, + .enum_tag => |enum_tag| continue :constant_key .{ .int = ip.indexToKey(enum_tag.int).int }, + .float => return isel.fail("float unimplemented", .{}), + .ptr => |ptr| { + assert(offset == 0 and size == isel.gprSize()); + const dst_ra: Register.Alias, const use_tmp_reg = select_tmp: { + if (dst.asRegisterAlias()) |dst_ra| { + if (dst_ra.mod == .integer) break :select_tmp .{ dst_ra, false }; + } + break :select_tmp .{ .{ .reg = try isel.allocRegForWrite(.int), .mod = .integer }, true }; + }; + const rd = dst_ra.reg; + defer if (use_tmp_reg) isel.freeReg(rd); + + if (use_tmp_reg) try isel.moveLoc(dst, 0, .{ .register = dst_ra }, 0, isel.gprSize(), .none); + return switch (ptr.base_addr) { + .nav => |nav| if (ZigType.fromInterned(ip.getNav(nav).resolved.?.type).isRuntimeFnOrHasRuntimeBits(zcu)) { + // TODO code model + try isel.nav_relocs.append(zcu.gpa, .{ + .nav = nav, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(ptr.byte_offset), + }, + }); + try isel.emit(.@"addi.d"(rd, rd, 0)); + try isel.nav_relocs.append(zcu.gpa, .{ + .nav = nav, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(ptr.byte_offset), + }, + }); + try isel.emit(.pcalau12i(rd, 0)); + } else continue :constant_key .{ .int = .{ + .ty = .usize_type, + .storage = .{ .u64 = isel.pt.zcu.navAlignment(nav).forward(0xaaaaaaaaaaaaaaaa) }, + } }, + .uav => |uav| if (ZigType.fromInterned(ip.typeOf(uav.val)).isRuntimeFnOrHasRuntimeBits(zcu)) { + // TODO code model + try isel.uav_relocs.append(zcu.gpa, .{ + .uav = uav, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(ptr.byte_offset), + }, + }); + try isel.emit(.@"addi.d"(rd, rd, 0)); + try isel.uav_relocs.append(zcu.gpa, .{ + .uav = uav, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = @intCast(ptr.byte_offset), + }, + }); + try isel.emit(.pcalau12i(rd, 0)); + } else continue :constant_key .{ .int = .{ + .ty = .usize_type, + .storage = .{ .u64 = ZigType.fromInterned(uav.orig_ty).ptrAlignment(zcu).forward(0xaaaaaaaaaaaaaaaa) }, + } }, + .int => continue :constant_key .{ .int = .{ + .ty = .usize_type, + .storage = .{ .u64 = ptr.byte_offset }, + } }, + .eu_payload => |base| { + var base_ptr = ip.indexToKey(base).ptr; + const eu_ty = ip.indexToKey(base_ptr.ty).ptr_type.child; + const payload_ty = ip.indexToKey(eu_ty).error_union_type.payload_type; + base_ptr.byte_offset += codegen.errUnionPayloadOffset(.fromInterned(payload_ty), zcu) + ptr.byte_offset; + continue :constant_key .{ .ptr = base_ptr }; + }, + .opt_payload => |base| { + var base_ptr = ip.indexToKey(base).ptr; + base_ptr.byte_offset += ptr.byte_offset; + continue :constant_key .{ .ptr = base_ptr }; + }, + .field => |field_idx| { + var base_ptr = ip.indexToKey(field_idx.base).ptr; + const agg_ty: ZigType = .fromInterned(ip.indexToKey(base_ptr.ty).ptr_type.child); + base_ptr.byte_offset += agg_ty.structFieldOffset(@intCast(field_idx.index), zcu) + ptr.byte_offset; + continue :constant_key .{ .ptr = base_ptr }; + }, + .comptime_alloc, .comptime_field, .arr_elem => unreachable, + }; + }, + .slice => |slice| { + const ptr_size = isel.gprSize(); + if (offset == 0 and size == ptr_size) { + constant = slice.ptr; + continue :constant_key switch (ip.indexToKey(slice.ptr)) { + else => unreachable, + .undef => |undef| .{ .undef = undef }, + .ptr => |ptr| .{ .ptr = ptr }, + }; + } else if (offset == ptr_size) { + offset = 0; + constant = slice.len; + continue :constant_key ip.indexToKey(slice.len); + } else if (offset == 0 and size == (@as(u64, ptr_size) * 2)) { + const dst_stack = dst.asStackSlot().?; + try moveConstant( + isel, + .{ .stack_slot = dst_stack }, + .fromInterned(slice.ptr), + 0, + ptr_size, + ); + try moveConstant( + isel, + .{ .stack_slot = dst_stack.withOffset(ptr_size) }, + .fromInterned(slice.len), + 0, + ptr_size, + ); + return; + } + }, + .opt => |opt| { + const child_ty = ip.indexToKey(opt.ty).opt_type; + const child_size = ZigType.fromInterned(child_ty).abiSize(zcu); + if (offset == child_size and size == 1) { + offset = 0; + continue :constant_key .{ .simple_value = switch (opt.val) { + .none => .false, + else => .true, + } }; + } + const opt_ty: ZigType = .fromInterned(opt.ty); + if (offset + size <= child_size) continue :constant_key switch (opt.val) { + .none => if (opt_ty.optionalReprIsPayload(zcu)) .{ .int = .{ + .ty = opt.ty, + .storage = .{ .u64 = 0 }, + } } else .{ .undef = child_ty }, + else => |child| { + constant = child; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + }, + }; + }, + .aggregate => |aggregate| switch (ip.indexToKey(aggregate.ty)) { + else => unreachable, + .array_type => |array_type| { + const elem_size = ZigType.fromInterned(array_type.child).abiSize(zcu); + const elem_offset = @mod(offset, elem_size); + if (size <= elem_size - elem_offset) { + defer offset = elem_offset; + continue :constant_key switch (aggregate.storage) { + .bytes => |bytes| .{ .int = .{ .ty = .u8_type, .storage = .{ + .u64 = bytes.toSlice(array_type.lenIncludingSentinel(), ip)[@intCast(@divFloor(offset, elem_size))], + } } }, + .elems => |elems| { + constant = elems[@intCast(@divFloor(offset, elem_size))]; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + }, + .repeated_elem => |repeated_elem| { + constant = repeated_elem; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + }, + }; + } + }, + .vector_type => {}, + .struct_type => { + const loaded_struct = ip.loadStructType(aggregate.ty); + switch (loaded_struct.layout) { + .auto => { + var field_it = loaded_struct.iterateRuntimeOrder(ip); + while (field_it.next()) |field_index| { + if (loaded_struct.field_is_comptime_bits.get(ip, field_index)) continue; + const field_ty: ZigType = .fromInterned(loaded_struct.field_types.get(ip)[field_index]); + const field_offset = loaded_struct.field_offsets.get(ip)[field_index]; + const field_size = field_ty.abiSize(zcu); + if (offset >= field_offset and offset + size <= field_offset + field_size) { + offset -= field_offset; + constant = switch (aggregate.storage) { + .bytes => unreachable, + .elems => |elems| elems[field_index], + .repeated_elem => |repeated_elem| repeated_elem, + }; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + } + } + }, + .@"extern", .@"packed" => {}, + } + }, + .tuple_type => |tuple_type| { + var field_offset: u64 = 0; + for (tuple_type.types.get(ip), tuple_type.values.get(ip), 0..) |field_type, field_value, field_index| { + if (field_value != .none) continue; + const field_ty: ZigType = .fromInterned(field_type); + field_offset = field_ty.abiAlignment(zcu).forward(field_offset); + const field_size = field_ty.abiSize(zcu); + if (offset >= field_offset and offset + size <= field_offset + field_size) { + offset -= field_offset; + constant = switch (aggregate.storage) { + .bytes => unreachable, + .elems => |elems| elems[field_index], + .repeated_elem => |repeated_elem| repeated_elem, + }; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + } + field_offset += field_size; + } + }, + }, + .un => |un| { + const loaded_union = ip.loadUnionType(un.ty); + const union_layout = ZigType.getUnionLayout(loaded_union, zcu); + if (loaded_union.has_runtime_tag) { + const tag_offset = union_layout.tagOffset(); + if (offset >= tag_offset and offset + size <= tag_offset + union_layout.tag_size) { + offset -= tag_offset; + continue :constant_key switch (ip.indexToKey(un.tag)) { + else => unreachable, + .int => |int| .{ .int = int }, + .enum_tag => |enum_tag| .{ .enum_tag = enum_tag }, + }; + } + } + const payload_offset = union_layout.payloadOffset(); + if (offset >= payload_offset and offset + size <= payload_offset + union_layout.payload_size) { + offset -= payload_offset; + constant = un.val; + constant_key = ip.indexToKey(constant); + continue :constant_key constant_key; + } + }, + } + const constant_size = ZigType.fromInterned(constant_key.typeOf()).abiSize(zcu); + var buffer: [128]u8 align(8) = @splat(0); + // Large constants should have been coerced to smaller ones, so use a buffer with fixed-size + if (constant_size <= buffer.len and + try isel.writeConstantToMemory(.fromInterned(constant), &buffer)) + { + // TODO lower to literals or lazy symbols and memcpy for larger constants + assert(offset + size <= buffer.len); + const part_buffer = buffer[@intCast(offset)..]; + const gpr_size = isel.gprSize(); + + const tmp_reg, const tmp_lock: RegLock = tmp_reg: { + if (dst.asRegisterAlias()) |dst_ra| { + if (dst_ra.mod == .integer) break :tmp_reg .{ dst_ra.reg, isel.tryLockReg(dst_ra.reg) }; + } + const tmp_reg = try isel.allocRegForWrite(.int); + break :tmp_reg .{ tmp_reg, .{ .reg = tmp_reg } }; + }; + defer tmp_lock.unlock(isel); + const tmp_ra: Register.Alias = .{ .mod = .integer, .reg = tmp_reg }; + + var part_offset = size & (0 -% gpr_size); + while (true) { + const part_size = @min(size - part_offset, gpr_size); + const part_value: u64 = switch (part_size) { + else => unreachable, + 0 => { + part_offset -= gpr_size; + continue; + }, + inline 1...8 => |ct_size| std.mem.readInt( + @Int(.unsigned, 8 * @as(u16, ct_size)), + part_buffer[0..ct_size], + .little, + ), + }; + + try isel.moveLoc(dst, part_offset, .{ .register = tmp_ra }, 0, part_size, .preserved); + try isel.moveIntImm(tmp_reg, @bitCast(part_value)); + + if (part_offset == 0) break else part_offset -= gpr_size; + } + + return; + } + if (ZigType.fromInterned(ip.typeOf(constant)).isRuntimeFnOrHasRuntimeBits(zcu)) { + const ptr_ty = try isel.pt.singleConstPtrType(.fromInterned(ip.typeOf(constant))); + const uav: InternPool.Key.Ptr.BaseAddr.Uav = .{ + .val = constant, + .orig_ty = ptr_ty.ip_index, + }; + + // allocate temporary register for pointers + const tmp_reg, const allocated_tmp_reg = tmp_reg: { + if (dst.asRegisterAlias()) |dst_ra| { + if (dst_ra.mod == .integer) break :tmp_reg .{ dst_ra.reg, false }; + } + break :tmp_reg .{ try isel.allocRegForWrite(.int), true }; + }; + defer if (allocated_tmp_reg) isel.freeReg(tmp_reg); + + // load from the pointer + try isel.moveLoc( + dst, + 0, + .{ .stack_slot = .{ .base = tmp_reg, .offset = 0 } }, + offset, + size, + .none, + ); + + // load constant pointer + try isel.uav_relocs.append(zcu.gpa, .{ + .uav = uav, + .reloc = .{ .label = @intCast(isel.instructions.items.len), .addend = 0 }, + }); + try isel.emit(.@"addi.d"(tmp_reg, tmp_reg, 0)); + try isel.uav_relocs.append(zcu.gpa, .{ + .uav = uav, + .reloc = .{ + .label = @intCast(isel.instructions.items.len), + .addend = 0, + }, + }); + try isel.emit(.pcalau12i(tmp_reg, 0)); + + return; + } + return isel.fail("unsupported value <{f}, {f}>[{d}..{d}] (full size={d}), from <{f}, {f}>[{d}..{d}]", .{ + isel.fmtType(.fromInterned(constant_key.typeOf())), + isel.fmtConstant(.fromInterned(constant)), + offset, + offset + size - 1, + constant_size, + isel.fmtType(init_constant.typeOf(zcu)), + isel.fmtConstant(init_constant), + init_offset, + init_offset + size - 1, + }); + } +} + +/// Returns the minimum legal memory operation size that is equal or greater than the given size. +fn memOpSizeFitting(size: u64) u64 { + return switch (size) { + 0 => unreachable, + 1 => 1, + 2 => 2, + 3...4 => 4, + 5...8 => 8, + 9...16 => 16, + 17...32 => 32, + else => unreachable, + }; +} + +pub const CallAbiIterator = struct { + isel: *Select, + cc: *const std.builtin.CallingConvention, + next_reg: std.EnumArray(RegisterClass, Register) = .init(.{ + .gpr = .r4, + .fpr = .f0, + .ret_byref = .r4, + }), + next_stack: usize = 0, + // TODO optimize, use SP to read incoming arguments when possible + stack_pointer: Register = .sp, + + const RegisterClass = enum { + gpr, + fpr, + /// Virtual register class, for allocating GPRs for by-reference returning. + ret_byref, + }; + + fn allocReg(it: *CallAbiIterator, class: RegisterClass) ?Register { + const last_reg: Register = switch (class) { + .gpr, .ret_byref => .r11, + .fpr => .f7, + }; + const next = it.next_reg.getPtr(class); + if (@backingInt(last_reg) >= @backingInt(next.*)) { + const allocated = next.*; + next.* = @fromBackingInt(@backingInt(allocated) + 1); + return allocated; + } else return null; + } + + /// Trys to allocate some registers, returning amount of allocated registers. + fn allocRegs(it: *CallAbiIterator, class: RegisterClass, result: []Register) usize { + const last_reg: Register = switch (class) { + .gpr, .ret_byref => .r11, + .fpr => .f7, + }; + const next = it.next_reg.getPtr(class); + const remaining = @backingInt(last_reg) - @backingInt(next.*) + 1; + if (remaining >= result.len) { + for (result, @backingInt(next.*)..) |*v, reg| + v.* = @fromBackingInt(@intCast(reg)); + next.* = @fromBackingInt(@intCast(@backingInt(next.*) + result.len)); + return result.len; + } else { + for (@backingInt(next.*)..@backingInt(last_reg) + 1, result[0..remaining]) |reg, *v| + v.* = @fromBackingInt(@intCast(reg)); + next.* = @fromBackingInt(@backingInt(last_reg) + 1); + return remaining; + } + } + + fn assignStack(it: *CallAbiIterator, wip_vi: Value.Index) void { + const isel = it.isel; + assert(wip_vi.stackSlot(isel) == null); + it.next_stack = @intCast(wip_vi.alignment(isel).forward(it.next_stack)); + wip_vi.setStackSlot(isel, .{ + .base = it.stack_pointer, + .offset = @intCast(it.next_stack), + }); + it.next_stack += @intCast(wip_vi.size(isel)); + } + + fn assignUsize(it: *CallAbiIterator, isel: *Select, wip_vi: Value.Index) void { + if (it.allocReg(.gpr)) |reg| { + wip_vi.setHintRegister(isel, reg); + } else it.assignStack(wip_vi); + } + + fn assignGprPair(it: *CallAbiIterator, isel: *Select, wip_vi: Value.Index, part_sizes: [2]u64, part_bit_size: [2]u9) !void { + const grsize: u8 = isel.gprSize(); + var regs: [2]Register = undefined; + const allocated_regs = it.allocRegs(.gpr, ®s); + switch (allocated_regs) { + 0 => it.assignStack(wip_vi), + 1 => { + wip_vi.setParts(isel, 2); + (try wip_vi.addIntPart(isel, 0, part_sizes[0], part_bit_size[0])).setHintRegister(isel, regs[0]); + it.assignStack(try wip_vi.addIntPart(isel, grsize, part_sizes[1], part_bit_size[1])); + }, + 2 => { + wip_vi.setParts(isel, 2); + (try wip_vi.addIntPart(isel, 0, part_sizes[0], part_bit_size[0])).setHintRegister(isel, regs[0]); + (try wip_vi.addIntPart(isel, grsize, part_sizes[1], part_bit_size[1])).setHintRegister(isel, regs[1]); + }, + else => unreachable, + } + } + + fn assignIndirect(it: *CallAbiIterator, isel: *Select, wip_vi: Value.Index, is_return: bool) void { + const wip_address_vi = isel.initValueAssumeCapacity(.usize); + wip_vi.setParent(isel, .{ .address = wip_address_vi }); + + if (it.allocReg(if (is_return) .ret_byref else .gpr)) |reg| { + wip_address_vi.setHintRegister(isel, reg); + } else it.assignStack(wip_address_vi); + } + + pub fn resolve(it: *CallAbiIterator, ty: ZigType, is_return: bool) !?Value.Index { + const isel = it.isel; + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + + if (!ty.hasRuntimeBits(zcu)) return null; + try isel.values.ensureUnusedCapacity(zcu.gpa, Value.max_parts); + try isel.value_types.ensureUnusedCapacity(zcu.gpa, Value.max_parts); + const wip_vi = isel.initValueAssumeCapacity(ty); + wip_vi.setExtension(isel, .pcsMode(isel, ty)); + + const grsize = isel.gprSize(); + const grlen: u8 = isel.gprBits(); + + type_key: switch (ip.indexToKey(ty.toIntern())) { + else => return isel.fail("CallAbiIterator.resolve({f})", .{isel.fmtType(ty)}), + .int_type => |int_ty| { + if (int_ty.bits <= grlen) { + it.assignUsize(isel, wip_vi); + } else if (int_ty.bits <= 2 * grlen) { + try it.assignGprPair(isel, wip_vi, .{ grsize, ty.abiSize(zcu) - grsize }, .{ grlen, @intCast(int_ty.bits - grlen) }); + } else it.assignStack(wip_vi); + }, + .ptr_type => |ptr_type| switch (ptr_type.flags.size) { + .one, .many, .c => it.assignUsize(isel, wip_vi), + .slice => continue :type_key .{ .int_type = .{ + .signedness = .unsigned, + .bits = 2 * grlen, + } }, + }, + .opt_type => |child_type| if (ty.optionalReprIsPayload(zcu)) + continue :type_key ip.indexToKey(child_type) + else switch (ZigType.fromInterned(child_type).abiSize(zcu)) { + 0 => continue :type_key .{ .simple_type = .bool }, + 1...7 => it.assignUsize(isel, wip_vi), + 8...15 => |child_size| { + try it.assignGprPair(isel, wip_vi, .{ child_size, 1 }, .{ @intCast(child_size * 8), 1 }); + }, + else => it.assignIndirect(isel, wip_vi, is_return), + }, + .anyframe_type => unreachable, + .error_union_type => switch (wip_vi.size(isel)) { + 0 => unreachable, + 1...8 => it.assignUsize(isel, wip_vi), + // 9...16 => {}, TODO optimize + else => it.assignIndirect(isel, wip_vi, is_return), + }, + .simple_type => |simple_type| switch (simple_type) { + .f80 => continue :type_key .{ .int_type = .{ .signedness = .unsigned, .bits = 80 } }, + .usize, + .isize, + .c_char, + .c_short, + .c_ushort, + .c_int, + .c_uint, + .c_long, + .c_ulong, + .c_longlong, + .c_ulonglong, + => continue :type_key .{ .int_type = ty.intInfo(zcu) }, + .anyopaque, .bool => it.assignUsize(isel, wip_vi), + .anyerror => continue :type_key .{ .int_type = .{ + .signedness = .unsigned, + .bits = zcu.errorSetBits(), + } }, + .f16, .f32, .f64, .f128, .c_longdouble => return isel.fail("CallAbiIterator.resolve({t})", .{simple_type}), + else => return isel.fail("CallAbiIterator.resolve({t})", .{simple_type}), + }, + .struct_type => { + // TODO: implement floating-point structures rules defined in lapcs + const loaded_struct = ip.loadStructType(ty.toIntern()); + switch (loaded_struct.layout) { + .auto, .@"extern" => {}, + .@"packed" => continue :type_key ip.indexToKey(loaded_struct.packed_backing_int_type), + } + const size = wip_vi.size(isel); + if (size == 0) + unreachable + else if (size <= grsize) + it.assignUsize(isel, wip_vi) + else if (size <= 2 * @as(u64, grsize)) + try it.assignGprPair(isel, wip_vi, .{ grsize, size - grsize }, .{ grlen, @intCast((size * 8) - grlen) }) + else + // TODO flatten single-field structs + it.assignIndirect(isel, wip_vi, is_return); + }, + .union_type => { + const loaded_union = ip.loadUnionType(ty.toIntern()); + switch (loaded_union.layout) { + .auto, .@"extern" => {}, + .@"packed" => continue :type_key .{ .int_type = .{ + .signedness = .unsigned, + .bits = @intCast(ty.bitSize(zcu)), + } }, + } + const size = wip_vi.size(isel); + if (size == 0) + unreachable + else if (size <= grsize) + it.assignUsize(isel, wip_vi) + else if (size <= 2 * @as(u64, grsize)) { + const union_layout = ZigType.getUnionLayout(loaded_union, zcu); + var sizes: [2]u64 = @splat(0); + { + const offset = union_layout.tagOffset(); + const end = offset % grsize + union_layout.tag_size; + const part_index: usize = @intCast(offset / grsize); + sizes[part_index] = @max(sizes[part_index], @min(end, grsize)); + if (end > grsize) sizes[part_index + 1] = @max(sizes[part_index + 1], end - grsize); + } + { + const offset = union_layout.payloadOffset(); + const end = offset % grsize + union_layout.payload_size; + const part_index: usize = @intCast(offset / grsize); + sizes[part_index] = @max(sizes[part_index], @min(end, grsize)); + if (end > grsize) sizes[part_index + 1] = @max(sizes[part_index + 1], end - grsize); + } + try it.assignGprPair(isel, wip_vi, sizes, .{ @intCast(sizes[0] * 8), @intCast(sizes[1] * 8) }); + } else it.assignIndirect(isel, wip_vi, is_return); + }, + .tuple_type => |tuple_ty| { + assert(it.cc.* == .auto); + const size = wip_vi.size(isel); + switch (size) { + 0 => unreachable, + 1...8 => it.assignUsize(isel, wip_vi), + 9...16 => { + var part_offset: u64 = 0; + var part_sizes: [2]u64 = undefined; + var parts_len: Value.PartsLen = 0; + var next_field_end: u64 = 0; + var field_index: usize = 0; + while (part_offset < size) { + const field_end = next_field_end; + const next_field_begin = while (field_index < tuple_ty.types.len) { + defer field_index += 1; + if (tuple_ty.values.get(ip)[field_index] != .none) continue; + const field_ty: ZigType = .fromInterned(tuple_ty.types.get(ip)[field_index]); + const next_field_begin = field_ty.abiAlignment(zcu).forward(field_end); + next_field_end = next_field_begin + field_ty.abiSize(zcu); + break next_field_begin; + } else std.mem.alignForward(u64, size, 8); + while (next_field_begin - part_offset >= 8) { + const part_size = @min(field_end - part_offset, 8); + part_sizes[parts_len] = part_size; + assert(part_offset + part_size <= size); + parts_len += 1; + part_offset += part_size; + if (part_offset >= field_end) part_offset = next_field_begin; + } + } + assert(parts_len == part_sizes.len); + try it.assignGprPair(isel, wip_vi, part_sizes, .{ @intCast(part_sizes[0] * 8), @intCast(part_sizes[1] * 8) }); + }, + else => it.assignIndirect(isel, wip_vi, is_return), + } + }, + // TODO: optimize chance + .array_type => it.assignIndirect(isel, wip_vi, is_return), + .opaque_type, .func_type => continue :type_key .{ .simple_type = .anyopaque }, + .enum_type => continue :type_key ip.indexToKey(ip.loadEnumType(ty.toIntern()).int_tag_type), + .error_set_type, + .inferred_error_set_type, + => continue :type_key .{ .simple_type = .anyerror }, + } + + if (is_return) { + it.next_reg = .init(.{ + .gpr = it.next_reg.get(.ret_byref), // skip registers for by-ref returning + .fpr = .f0, + .ret_byref = .zero, + }); + it.next_stack = 0; + abi_log.debug("| Return: {f} -> {f}", .{ isel.fmtType(ty), isel.fmtValue(wip_vi) }); + } else { + abi_log.debug("| Param: {f} -> {f}", .{ isel.fmtType(ty), isel.fmtValue(wip_vi) }); + } + + return wip_vi.ref(isel); + } +}; + +const call = struct { + const param_reg: Value.Index = @fromBackingInt(@backingInt(Value.Index.allocating) - 2); + const callee_clobbered_reg: Value.Index = @fromBackingInt(@backingInt(Value.Index.allocating) - 1); + const caller_saved_regs: LiveRegisters = .init(.{ + .r0 = .free, + .r1 = callee_clobbered_reg, + .r2 = .free, + .r3 = .free, + .r4 = param_reg, + .r5 = param_reg, + .r6 = param_reg, + .r7 = param_reg, + .r8 = param_reg, + .r9 = param_reg, + .r10 = param_reg, + .r11 = param_reg, + .r12 = callee_clobbered_reg, + .r13 = callee_clobbered_reg, + .r14 = callee_clobbered_reg, + .r15 = callee_clobbered_reg, + .r16 = callee_clobbered_reg, + .r17 = callee_clobbered_reg, + .r18 = callee_clobbered_reg, + .r19 = callee_clobbered_reg, + .r20 = callee_clobbered_reg, + .r21 = .free, + .r22 = .free, + .r23 = .free, + .r24 = .free, + .r25 = .free, + .r26 = .free, + .r27 = .free, + .r28 = .free, + .r29 = .free, + .r30 = .free, + .r31 = .free, + + .f0 = param_reg, + .f1 = param_reg, + .f2 = param_reg, + .f3 = param_reg, + .f4 = param_reg, + .f5 = param_reg, + .f6 = param_reg, + .f7 = param_reg, + .f8 = callee_clobbered_reg, + .f9 = callee_clobbered_reg, + .f10 = callee_clobbered_reg, + .f11 = callee_clobbered_reg, + .f12 = callee_clobbered_reg, + .f13 = callee_clobbered_reg, + .f14 = callee_clobbered_reg, + .f15 = callee_clobbered_reg, + .f16 = callee_clobbered_reg, + .f17 = callee_clobbered_reg, + .f18 = callee_clobbered_reg, + .f19 = callee_clobbered_reg, + .f20 = callee_clobbered_reg, + .f21 = callee_clobbered_reg, + .f22 = callee_clobbered_reg, + .f23 = callee_clobbered_reg, + .f24 = .free, + .f25 = .free, + .f26 = .free, + .f27 = .free, + .f28 = .free, + .f29 = .free, + .f30 = .free, + .f31 = .free, + + .fcc0 = callee_clobbered_reg, + .fcc1 = callee_clobbered_reg, + .fcc2 = callee_clobbered_reg, + .fcc3 = callee_clobbered_reg, + .fcc4 = callee_clobbered_reg, + .fcc5 = callee_clobbered_reg, + .fcc6 = callee_clobbered_reg, + .fcc7 = callee_clobbered_reg, + }); + + fn prepareReturn(_: *Select) !void {} + + fn finishReturn(isel: *Select) !void { + // Lock remaining clobberred registers + const locked_regs = comptime locked_regs: { + var locked_regs: RegisterSet = .empty; + for (std.enums.values(Register)) |reg| switch (caller_saved_regs.get(reg)) { + else => unreachable, + param_reg, callee_clobbered_reg => locked_regs.insert(reg), + .free => {}, + }; + break :locked_regs locked_regs; + }; + try isel.fillRegsBatch(locked_regs, true); + isel.markRegsWritten(locked_regs); + } + + fn prepareCallee(isel: *Select) !void { + // Free clobbered registers + var live_reg_it = isel.live_registers.iterator(); + while (live_reg_it.next()) |live_reg_entry| switch (caller_saved_regs.get(live_reg_entry.key)) { + else => unreachable, + param_reg => assert(live_reg_entry.value.* == .allocating), + callee_clobbered_reg => isel.freeReg(live_reg_entry.key), + .free => {}, + }; + } + fn finishCallee(_: *Select) !void {} + + fn prepareParams(_: *Select) !void {} + fn paramLiveOut(isel: *Select, vi: Value.Index, layout_vi: Value.Index) !void { + switch (layout_vi.parent(isel)) { + else => return vi.matLiveOut(isel, layout_vi, .{ .mode = .param }), + .address => |addr_vi| return call.paramIndirect(isel, vi, addr_vi), + } + } + fn paramIndirect(isel: *Select, vi: Value.Index, addr_vi: Value.Index) !void { + const val_mat = try vi.mat(isel, .{ .pref = .only_stack }); + try paramAddress( + isel, + val_mat.loc().asStackSlot().?, + addr_vi, + ); + try val_mat.finish(isel); + } + fn paramAddress(isel: *Select, stack: Value.Indirect, addr_vi: Value.Index) !void { + if (addr_vi.hintRegister(isel)) |addr_reg| { + assert(isel.live_registers.get(addr_reg) == .allocating); + try isel.addImm(addr_reg, stack.base, stack.offset); + } else if (addr_vi.location(isel)) |addr_loc| { + const tmp_reg = try isel.allocRegForWrite(.int); + defer isel.freeReg(tmp_reg); + try isel.addImm(tmp_reg, stack.base, stack.offset); + try isel.moveLoc( + addr_loc, + 0, + .{ .register = .{ .mod = .integer, .reg = tmp_reg } }, + 0, + isel.gprSize(), + .preserved, + ); + } else unreachable; + } + fn finishParams(isel: *Select) !void { + // Free parameter registers + var live_reg_it = isel.live_registers.iterator(); + while (live_reg_it.next()) |live_reg_entry| switch (caller_saved_regs.get(live_reg_entry.key)) { + else => unreachable, + param_reg => switch (live_reg_entry.value.*) { + _ => {}, + .allocating => live_reg_entry.value.* = .free, + .free => unreachable, + }, + callee_clobbered_reg, .free => {}, + }; + } +}; + +fn gprSize(isel: *Select) u4 { + return switch (isel.target.cpu.arch) { + .loongarch32 => 4, + .loongarch64 => 8, + else => unreachable, + }; +} + +fn gprBits(isel: *Select) u7 { + return switch (isel.target.cpu.arch) { + .loongarch32 => 32, + .loongarch64 => 64, + else => unreachable, + }; +} + +fn gprAlignment(isel: *Select) std.mem.Alignment { + return switch (isel.target.cpu.arch) { + .loongarch32 => .@"4", + .loongarch64 => .@"8", + else => unreachable, + }; +} + +fn typeOfField(isel: *Select, ty: ZigType, offset: u64) ?ZigType { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + type_key: switch (ip.indexToKey(ty.toIntern())) { + else => {}, + // TODO large int splitting + .int_type => { + if (ty.abiSize(zcu) > isel.gprSize() and offset % isel.gprSize() == 0) return .usize; + }, + .ptr_type => |ptr_type| switch (ptr_type.flags.size) { + .one, .many, .c => {}, + .slice => if (offset == 0) + return ty.elemPtrType(null, isel.pt) catch unreachable + else if (offset == isel.gprSize()) + return .usize, + }, + .opt_type => |child_type| if (ty.optionalReprIsPayload(zcu)) + continue :type_key ip.indexToKey(child_type) + else { + const child_ty: ZigType = .fromInterned(child_type); + if (offset == 0) + return child_ty + else if (offset == child_ty.abiSize(zcu)) + return .usize; + }, + .array_type => unreachable, // TODO + .anyframe_type => unreachable, + .error_union_type => |error_union_type| { + const payload_ty: ZigType = .fromInterned(error_union_type.payload_type); + if (offset == codegen.errUnionErrorOffset(payload_ty, zcu)) + return .fromInterned(error_union_type.error_set_type) + else if (offset == codegen.errUnionPayloadOffset(payload_ty, zcu)) + return payload_ty; + }, + .simple_type => |simple_type| switch (simple_type) { + else => {}, + .f80 => continue :type_key .{ .int_type = .{ .signedness = .unsigned, .bits = 80 } }, + .usize, + .isize, + .c_char, + .c_short, + .c_ushort, + .c_int, + .c_uint, + .c_long, + .c_ulong, + .c_longlong, + .c_ulonglong, + => continue :type_key .{ .int_type = ty.intInfo(zcu) }, + .anyerror => continue :type_key .{ .int_type = .{ .signedness = .unsigned, .bits = zcu.errorSetBits() } }, + }, + .struct_type => { + const loaded_struct = ip.loadStructType(ty.toIntern()); + switch (loaded_struct.layout) { + .auto, .@"extern" => {}, + .@"packed" => continue :type_key ip.indexToKey(loaded_struct.backingIntTypeUnordered(ip)).int_type, + } + var field_end: u64 = 0; + var field_it = loaded_struct.iterateRuntimeOrder(ip); + while (field_it.next()) |field_index| { + const field_ty: ZigType = .fromInterned(loaded_struct.field_types.get(ip)[field_index]); + const field_begin = switch (loaded_struct.fieldAlign(ip, field_index)) { + .none => field_ty.abiAlignment(zcu), + else => |field_align| field_align, + }.forward(field_end); + const field_size = field_ty.abiSize(zcu); + field_end = field_begin + field_size; + if (field_begin > offset) break; + if (field_begin == offset) + return field_ty + else if (field_end > offset) + return isel.typeOfField(field_ty, offset - field_begin); + } + }, + .tuple_type => |tuple_type| { + var field_end: u64 = 0; + for (tuple_type.types.get(ip), tuple_type.values.get(ip)) |field_type, field_value| { + if (field_value != .none) continue; + const field_ty: ZigType = .fromInterned(field_type); + const field_begin = field_ty.abiAlignment(zcu).forward(field_end); + const field_size = field_ty.abiSize(zcu); + if (field_size == 0) continue; + field_end = field_begin + field_size; + if (field_begin > offset) break; + if (field_begin == offset) + return field_ty + else if (field_end > offset) + return isel.typeOfField(field_ty, offset - field_begin); + } + }, + .union_type => { + const loaded_union = ip.loadUnionType(ty.toIntern()); + switch (loaded_union.flagsUnordered(ip).layout) { + .auto, .@"extern" => {}, + .@"packed" => continue :type_key .{ .int_type = .{ + .signedness = .unsigned, + .bits = @intCast(ty.bitSize(zcu)), + } }, + } + const union_layout = ZigType.getUnionLayout(loaded_union, zcu); + if (offset == union_layout.tagOffset()) + return .fromInterned(loaded_union.enum_tag_ty); + }, + .opaque_type, .func_type => continue :type_key .{ .simple_type = .anyopaque }, + .enum_type => continue :type_key ip.indexToKey(ip.loadEnumType(ty.toIntern()).tag_ty), + .error_set_type, + .inferred_error_set_type, + => continue :type_key .{ .simple_type = .anyerror }, + } + tracking_log.debug("cannot split {f} at {d}", .{ isel.fmtType(ty), offset }); + return null; +} + +fn hasRepeatedByteRepr(isel: *Select, constant: Constant) error{OutOfMemory}!?u8 { + const zcu = isel.pt.zcu; + const ty = constant.typeOf(zcu); + const abi_size = std.math.cast(usize, ty.abiSize(zcu)) orelse return null; + const byte_buffer = try zcu.gpa.alloc(u8, abi_size); + defer zcu.gpa.free(byte_buffer); + return if (try isel.writeConstantToMemory(constant, byte_buffer) and + std.mem.allEqual(u8, byte_buffer[1..], byte_buffer[0])) byte_buffer[0] else null; +} + +fn writeConstantToMemory(isel: *Select, constant: Constant, buffer: []u8) error{OutOfMemory}!bool { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + if (try isel.writeConstantKeyToMemory(ip.indexToKey(constant.toIntern()), buffer)) return true; + constant.writeToMemory(isel.pt.zcu, buffer) catch |err| switch (err) { + error.OutOfMemory => return error.OutOfMemory, + error.ReinterpretDeclRef, error.IllDefinedMemoryLayout => return false, + }; + return true; +} + +fn writeConstantKeyToMemory(isel: *Select, constant_key: InternPool.Key, buffer: []u8) error{OutOfMemory}!bool { + const zcu = isel.pt.zcu; + const ip = &zcu.intern_pool; + switch (constant_key) { + .int_type, + .ptr_type, + .array_type, + .vector_type, + .opt_type, + .anyframe_type, + .error_union_type, + .simple_type, + .struct_type, + .tuple_type, + .union_type, + .opaque_type, + .enum_type, + .func_type, + .error_set_type, + .inferred_error_set_type, + + .enum_literal, + .memoized_call, + => unreachable, // not a runtime value + .err => |err| { + const error_int = ip.getErrorValueIfExists(err.name).?; + switch (buffer.len) { + else => unreachable, + inline 1...4 => |size| std.mem.writeInt( + @Int(.unsigned, 8 * size), + buffer[0..size], + @intCast(error_int), + isel.target.cpu.arch.endian(), + ), + } + }, + .error_union => |error_union| { + const error_union_type = ip.indexToKey(error_union.ty).error_union_type; + const error_set_ty: ZigType = .fromInterned(error_union_type.error_set_type); + const payload_ty: ZigType = .fromInterned(error_union_type.payload_type); + const error_set = buffer[@intCast(codegen.errUnionErrorOffset(payload_ty, zcu))..][0..@intCast(error_set_ty.abiSize(zcu))]; + switch (error_union.val) { + .err_name => |err_name| if (!try isel.writeConstantKeyToMemory(.{ .err = .{ + .ty = error_set_ty.toIntern(), + .name = err_name, + } }, error_set)) return false, + .payload => |payload| { + if (!try isel.writeConstantToMemory( + .fromInterned(payload), + buffer[@intCast(codegen.errUnionPayloadOffset(payload_ty, zcu))..][0..@intCast(payload_ty.abiSize(zcu))], + )) return false; + @memset(error_set, 0); + }, + } + }, + .opt => |opt| { + const child_size: usize = @intCast(ZigType.fromInterned(ip.indexToKey(opt.ty).opt_type).abiSize(zcu)); + switch (opt.val) { + .none => if (!ZigType.fromInterned(opt.ty).optionalReprIsPayload(zcu)) { + buffer[child_size] = @intFromBool(false); + } else @memset(buffer[0..child_size], 0x00), + else => |child_constant| { + if (!try isel.writeConstantToMemory(.fromInterned(child_constant), buffer[0..child_size])) return false; + if (!ZigType.fromInterned(opt.ty).optionalReprIsPayload(zcu)) buffer[child_size] = @intFromBool(true); + }, + } + }, + .aggregate => |aggregate| switch (ip.indexToKey(aggregate.ty)) { + else => unreachable, + .array_type => |array_type| { + var elem_offset: usize = 0; + const elem_size: usize = @intCast(ZigType.fromInterned(array_type.child).abiSize(zcu)); + const len_including_sentinel: usize = @intCast(array_type.lenIncludingSentinel()); + switch (aggregate.storage) { + .bytes => |bytes| @memcpy(buffer[0..len_including_sentinel], bytes.toSlice(len_including_sentinel, ip)), + .elems => |elems| for (elems) |elem| { + if (!try isel.writeConstantToMemory(.fromInterned(elem), buffer[elem_offset..][0..elem_size])) return false; + elem_offset += elem_size; + }, + .repeated_elem => |repeated_elem| for (0..len_including_sentinel) |_| { + if (!try isel.writeConstantToMemory(.fromInterned(repeated_elem), buffer[elem_offset..][0..elem_size])) return false; + elem_offset += elem_size; + }, + } + }, + .vector_type => return false, + .struct_type => { + const loaded_struct = ip.loadStructType(aggregate.ty); + switch (loaded_struct.layout) { + .auto => { + var field_it = loaded_struct.iterateRuntimeOrder(ip); + while (field_it.next()) |field_index| { + if (loaded_struct.field_is_comptime_bits.get(ip, field_index)) continue; + const field_ty: ZigType = .fromInterned(loaded_struct.field_types.get(ip)[field_index]); + const field_offset = loaded_struct.field_offsets.get(ip)[field_index]; + const field_size = field_ty.abiSize(zcu); + if (!try isel.writeConstantToMemory(.fromInterned(switch (aggregate.storage) { + .bytes => unreachable, + .elems => |elems| elems[field_index], + .repeated_elem => |repeated_elem| repeated_elem, + }), buffer[@intCast(field_offset)..][0..@intCast(field_size)])) return false; + } + }, + .@"extern", .@"packed" => return false, + } + }, + .tuple_type => |tuple_type| { + var field_offset: u64 = 0; + for (tuple_type.types.get(ip), tuple_type.values.get(ip), 0..) |field_type, field_value, field_index| { + if (field_value != .none) continue; + const field_ty: ZigType = .fromInterned(field_type); + field_offset = field_ty.abiAlignment(zcu).forward(field_offset); + const field_size = field_ty.abiSize(zcu); + if (!try isel.writeConstantToMemory(.fromInterned(switch (aggregate.storage) { + .bytes => unreachable, + .elems => |elems| elems[field_index], + .repeated_elem => |repeated_elem| repeated_elem, + }), buffer[@intCast(field_offset)..][0..@intCast(field_size)])) return false; + field_offset += field_size; + } + }, + }, + .un => |union_val| { + const loaded_union = ip.loadUnionType(union_val.ty); + switch (loaded_union.layout) { + .auto => {}, + .@"extern", .@"packed" => return false, + } + const union_layout = ZigType.getUnionLayout(loaded_union, zcu); + if (loaded_union.has_runtime_tag) + if (!try isel.writeConstantToMemory( + .fromInterned(union_val.tag), + buffer[@intCast(union_layout.tagOffset())..][0..@intCast(union_layout.tag_size)], + )) return false; + if (!try isel.writeConstantToMemory( + .fromInterned(union_val.val), + buffer[@intCast(union_layout.payloadOffset())..][0..@intCast(union_layout.payload_size)], + )) return false; + }, + else => return false, + } + return true; +} + +fn wipeLocationDfs(isel: *Select, vi: Value.Index) void { + _ = vi.takeLocationMarkWritten(isel); + var part_it = vi.parts(isel); + while (part_it.next()) |part_vi| { + if (part_vi != vi) isel.wipeLocationDfs(part_vi); + } +} + +const Air = @import("../../Air.zig"); +const assert = std.debug.assert; +const codegen = @import("../../codegen.zig"); +const Constant = @import("../../Value.zig"); +const InternPool = @import("../../InternPool.zig"); +const Module = @import("../../Module.zig"); +const Select = @This(); +const std = @import("std"); +const tracking_log = std.log.scoped(.tracking); +const wip_mir_log = std.log.scoped(.@"wip-mir"); +const abi_log = std.log.scoped(.abi); +const Zcu = @import("../../Zcu.zig"); +const ZigType = @import("../../Type.zig"); diff --git a/src/codegen/loongarch/bits.zig b/src/codegen/loongarch/bits.zig new file mode 100644 index 0000000000000000000000000000000000000000..d60646f4b040ac698f02a24a9e393cb9ee7758cf --- /dev/null +++ b/src/codegen/loongarch/bits.zig @@ -0,0 +1,243 @@ +const std = @import("std"); +const Target = std.Target; +const assert = std.debug.assert; +const expectEqual = std.testing.expectEqual; +const Writer = std.Io.Writer; + +/// Register, one per set of aliasing registers +pub const Register = enum(u7) { + // zig fmt: off + // integer registers + r0, r1, r2, r3, r4, r5, r6, r7, + r8, r9, r10, r11, r12, r13, r14, r15, + r16, r17, r18, r19, r20, r21, r22, r23, + r24, r25, r26, r27, r28, r29, r30, r31, + + // float-point/LSX/LASX registers + f0, f1, f2, f3, f4, f5, f6, f7, + f8, f9, f10, f11, f12, f13, f14, f15, + f16, f17, f18, f19, f20, f21, f22, f23, + f24, f25, f26, f27, f28, f29, f30, f31, + + // float-point condition code registers + fcc0, fcc1, fcc2, fcc3, fcc4, fcc5, fcc6, fcc7, + // zig fmt: on + + pub const zero: Register = .r0; + pub const ra: Register = .r1; + pub const tp: Register = .r2; + pub const sp: Register = .r3; + pub const fp: Register = .r22; + pub const t0: Register = .r12; + + /// Register banks. + pub const Class = enum { int, fp, fcc }; + + /// Register accessing modifier. + pub const Modifier = enum(u3) { + undef, + integer, + floating32, + floating64, + lsx, + lasx, + fcc, + + pub fn class(modifier: Modifier) Class { + return switch (modifier) { + .undef => unreachable, + .integer => .int, + .floating32, .floating64, .lsx, .lasx => .fp, + .fcc => .fcc, + }; + } + + pub fn bitSize(modifier: Modifier, target: *const Target) u16 { + return switch (modifier) { + .undef => 0, + .integer => switch (target.cpu.arch) { + .loongarch32 => 32, + .loongarch64 => 64, + else => unreachable, + }, + .floating32 => 32, + .floating64 => 64, + .lsx => 128, + .lasx => 256, + .fcc => 1, + }; + } + + /// Upper-rounded byte size. + pub fn byteSize(modifier: Modifier, target: *const Target) u16 { + return switch (modifier) { + .undef => 0, + .integer => switch (target.cpu.arch) { + .loongarch32 => 4, + .loongarch64 => 8, + else => unreachable, + }, + .floating32 => 4, + .floating64 => 8, + .lsx => 16, + .lasx => 32, + .fcc => 1, + }; + } + + pub fn fromFloating(bits: u16) Modifier { + return switch (bits) { + else => unreachable, + 32 => .floating32, + 64 => .floating64, + }; + } + }; + + pub const Alias = struct { + reg: Register, + mod: Modifier, + + pub const zero: Alias = .{ .mod = .integer, .reg = .zero }; + + pub fn format(self: Alias, w: *std.Io.Writer) std.Io.Writer.Error!void { + try w.print("${s}{d}", .{ + switch (self.mod) { + .undef => "?", + .integer => "r", + .floating32 => "(s)f", + .floating64 => "(d)f", + .lsx => "v", + .lasx => "x", + .fcc => "fcc", + }, + self.reg.encode(), + }); + } + }; + + pub fn class(reg: Register) Class { + return switch (@backingInt(reg)) { + @backingInt(Register.r0)...@backingInt(Register.r31) => .int, + @backingInt(Register.f0)...@backingInt(Register.f31) => .fp, + @backingInt(Register.fcc0)...@backingInt(Register.fcc7) => .fcc, + else => unreachable, + }; + } + + pub fn encode(reg: Register) u5 { + const base: u7 = switch (@backingInt(reg)) { + @backingInt(Register.r0)...@backingInt(Register.r31) => @backingInt(Register.r0), + @backingInt(Register.f0)...@backingInt(Register.f31) => @backingInt(Register.f0), + @backingInt(Register.fcc0)...@backingInt(Register.fcc7) => @backingInt(Register.fcc0), + else => unreachable, + }; + return @intCast(@backingInt(reg) - base); + } + + pub fn decode(reg_class: Class, reg: u5) Register { + const base: u7 = switch (reg_class) { + .int => @backingInt(Register.r0), + .fp => @backingInt(Register.f0), + .fcc => @backingInt(Register.fcc0), + }; + return @fromBackingInt(base + @as(u7, reg)); + } + + pub fn parse(reg: []const u8) ?Register { + if (reg.len == 0) return null; + if (reg[0] == '$') return parse(reg[1..]); + if (toLowerEqlAssertLower(reg, "zero")) return .zero; + if (toLowerEqlAssertLower(reg, "ra")) return .ra; + if (toLowerEqlAssertLower(reg, "tp")) return .tp; + if (toLowerEqlAssertLower(reg, "sp")) return .sp; + if (toLowerEqlAssertLower(reg, "fp")) return .fp; + return switch (std.ascii.toLower(reg[0])) { + else => null, + 'r' => reg: { + break :reg if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .decode(.int, n) else |_| null; + }, + 'f' => reg: { + if (reg.len == 4 and toLowerEqlAssertLower(reg[0..3], "fcc")) + break :reg if (std.ascii.isDigit(reg[3])) .decode(.fcc, @intCast(reg[3] ^ '0')) else null; + if (reg.len > 2 and toLowerEqlAssertLower(reg[0..2], "fa")) + break :reg if (std.fmt.parseInt(u5, reg[2..], 10)) |n| .decode(.fp, n) else |_| null; + if (reg.len > 2 and toLowerEqlAssertLower(reg[0..2], "ft")) + break :reg if (std.fmt.parseInt(u5, reg[2..], 10)) |n| .decode(.fp, 8 + n) else |_| null; + if (reg.len > 2 and toLowerEqlAssertLower(reg[0..2], "fs")) + break :reg if (std.fmt.parseInt(u5, reg[2..], 10)) |n| .decode(.fp, 24 + n) else |_| null; + + break :reg if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .decode(.fp, n) else |_| null; + }, + 'v', 'x' => reg: { + if (reg.len < 3 or std.ascii.toLower(reg[1]) != 'r') break :reg null; + break :reg if (std.fmt.parseInt(u5, reg[2..], 10)) |n| .decode(.fp, n) else |_| null; + }, + 'a' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .decode(.int, 4 + n) else |_| null, + 't' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| .decode(.int, 12 + n) else |_| null, + 's' => if (std.fmt.parseInt(u5, reg[1..], 10)) |n| reg: { + if (n == 9) break :reg .r22; + break :reg .decode(.int, 23 + n); + } else |_| null, + }; + } + + fn toLowerEqlAssertLower(lhs: []const u8, rhs: []const u8) bool { + if (lhs.len != rhs.len) return false; + for (lhs, rhs) |l, r| { + assert(!std.ascii.isUpper(r)); + if (std.ascii.toLower(l) != r) return false; + } + return true; + } +}; + +test "register classes" { + try expectEqual(.int, Register.r0.class()); + try expectEqual(.int, Register.r31.class()); + try expectEqual(.fp, Register.f0.class()); + try expectEqual(.fp, Register.f31.class()); + try expectEqual(.fcc, Register.fcc0.class()); + try expectEqual(.fcc, Register.fcc7.class()); +} + +test "register encoding" { + try expectEqual(0, Register.r0.encode()); + try expectEqual(31, Register.r31.encode()); + try expectEqual(0, Register.f0.encode()); + try expectEqual(31, Register.f31.encode()); + try expectEqual(0, Register.fcc0.encode()); + try expectEqual(7, Register.fcc7.encode()); +} + +test "register decoding" { + try expectEqual(.r0, Register.decode(.int, 0)); + try expectEqual(.r31, Register.decode(.int, 31)); + try expectEqual(.f0, Register.decode(.fp, 0)); + try expectEqual(.f31, Register.decode(.fp, 31)); + try expectEqual(.fcc0, Register.decode(.fcc, 0)); + try expectEqual(.fcc7, Register.decode(.fcc, 7)); +} + +test "register parsing" { + try expectEqual(.r0, Register.parse("r0").?); + try expectEqual(.r0, Register.parse("ZERO").?); + try expectEqual(.r0, Register.parse("zero").?); + try expectEqual(.r0, Register.parse("$zero").?); + try expectEqual(Register.ra, Register.parse("ra").?); + try expectEqual(Register.tp, Register.parse("tp").?); + try expectEqual(Register.sp, Register.parse("sp").?); + try expectEqual(Register.fp, Register.parse("fp").?); + try expectEqual(.r7, Register.parse("a3").?); + try expectEqual(.r15, Register.parse("t3").?); + try expectEqual(.r26, Register.parse("s3").?); + try expectEqual(.r22, Register.parse("s9").?); + try expectEqual(.fcc0, Register.parse("fcc0").?); + try expectEqual(.fcc7, Register.parse("fcc7").?); + try expectEqual(.f0, Register.parse("f0").?); + try expectEqual(.f3, Register.parse("fa3").?); + try expectEqual(.f11, Register.parse("ft3").?); + try expectEqual(.f27, Register.parse("fs3").?); + try expectEqual(.f0, Register.parse("vr0").?); + try expectEqual(.f0, Register.parse("xr0").?); +} diff --git a/src/target.zig b/src/target.zig index 4bc3853ae75c593ab39cf0ccd276cba2dac0fca1..ed7a854fa796f2ffd188011b7c80aa950674285e 100644 --- a/src/target.zig +++ b/src/target.zig @@ -853,6 +853,7 @@ pub fn supportsThreads(target: *const std.Target, backend: std.lang.CompilerBack _ = target; return switch (backend) { .stage2_aarch64 => false, + .stage2_loongarch => false, else => true, }; } @@ -914,6 +915,7 @@ pub fn zigBackend(target: *const std.Target, use_llvm: bool) std.lang.CompilerBa return switch (target.cpu.arch) { .aarch64, .aarch64_be => .stage2_aarch64, .arm, .armeb, .thumb, .thumbeb => .stage2_arm, + .loongarch32, .loongarch64 => .stage2_loongarch, .powerpc, .powerpcle, .powerpc64, .powerpc64le => .stage2_powerpc, .riscv64 => .stage2_riscv64, .sparc64 => .stage2_sparc64, @@ -950,7 +952,7 @@ pub inline fn backendSupportsFeature(backend: std.lang.CompilerBackend, comptime else => false, }, .field_reordering => switch (backend) { - .stage2_aarch64, .stage2_c, .stage2_llvm, .stage2_x86_64, .stage2_wasm => true, + .stage2_aarch64, .stage2_c, .stage2_llvm, .stage2_loongarch, .stage2_x86_64, .stage2_wasm => true, else => false, }, .separate_thread => switch (backend) { -- 2.54.0 From 4605f7fbbfe44dea013a05b51b4a17e55e9a91ad Mon Sep 17 00:00:00 2001 From: xtex Date: Fri, 7 Aug 2026 15:16:01 +0800 Subject: [PATCH 5/5] std: support loongarch backend --- lib/compiler/test_runner.zig | 1 + lib/std/debug.zig | 1 + lib/std/mem.zig | 1 + lib/std/os/linux.zig | 1 + lib/std/start.zig | 31 ++++++++++++++++++++++++++++++- lib/std/testing.zig | 1 + lib/ubsan_rt.zig | 1 + 7 files changed, 36 insertions(+), 1 deletion(-) diff --git a/lib/compiler/test_runner.zig b/lib/compiler/test_runner.zig index 0fd5afad694b6aa417fb7cdfcf7305614574d883..9ecfa4d03951427c9b091f6e59d50c120d4ee7f1 100644 --- a/lib/compiler/test_runner.zig +++ b/lib/compiler/test_runner.zig @@ -26,6 +26,7 @@ const runner_threaded_io: Io = Io.Threaded.global_single_threaded.io(); /// the test runner will communicate with the build runner via `std.zig.Server`. const need_simple = switch (builtin.zig_backend) { .stage2_aarch64, + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, => true, diff --git a/lib/std/debug.zig b/lib/std/debug.zig index 59a8dcd9eae1cf7ba40a1e5e9c50a683186c322c..ca1bf3f6edf8a79fb2459fe481f311ec7f50c4b1 100644 --- a/lib/std/debug.zig +++ b/lib/std/debug.zig @@ -498,6 +498,7 @@ threadlocal var panic_stage: usize = 0; const use_trap_panic = switch (builtin.zig_backend) { .stage2_aarch64, .stage2_arm, + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, .stage2_spirv, diff --git a/lib/std/mem.zig b/lib/std/mem.zig index 55b9019c4f4d95cfce0f271de52d12a856f9aea8..552dfce320311fb7f672611443de0440a415340b 100644 --- a/lib/std/mem.zig +++ b/lib/std/mem.zig @@ -735,6 +735,7 @@ test lessThan { const use_vectors = switch (builtin.zig_backend) { // These backends don't support vectors yet. .stage2_aarch64, + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, => false, diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig index 8fd3fca48e788610aa574ced6d7c7c56a90c0568..835da881ff859006def9b02fe004fa32df3d2215 100644 --- a/lib/std/os/linux.zig +++ b/lib/std/os/linux.zig @@ -681,6 +681,7 @@ pub var elf_aux_maybe: ?[*]std.elf.Auxv = null; const extern_getauxval = switch (builtin.zig_backend) { // Calling extern functions is not yet supported with these backends .stage2_arm, + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, .stage2_sparc64, diff --git a/lib/std/start.zig b/lib/std/start.zig index 6021da10325aa38a6be00d59ecc1d58634deba77..20cd8548f711901aa61d64d6799d685512df9521 100644 --- a/lib/std/start.zig +++ b/lib/std/start.zig @@ -180,7 +180,10 @@ fn _start() callconv(.naked) noreturn { .csky => ".cfi_undefined lr", .hexagon => ".cfi_undefined r31", .kvx => ".cfi_undefined r14", - .loongarch32, .loongarch64 => ".cfi_undefined 1", + .loongarch32, .loongarch64 => if (builtin.zig_backend == .stage2_loongarch) + "" + else + ".cfi_undefined 1", .m68k => ".cfi_undefined %%pc", .m88k => ".cfi_undefined %%r1", .microblaze, .microblazeel => "", // No CFI support. @@ -215,6 +218,32 @@ fn _start() callconv(.naked) noreturn { // kernel is usually good about upholding the ABI guarantees, the same cannot be said of dynamic // linkers; musl's ldso, for example, opts to not align the stack when invoking the dynamic // linker explicitly. + if (builtin.zig_backend == .stage2_loongarch) { + // TODO: need "X" constraint support + asm volatile (switch (native_arch) { + .loongarch32 => + \\ move $fp, $zero + \\ move $ra, $zero + \\ move $a0, $sp + \\ srli.w $sp, $sp, 4 + \\ slli.w $sp, $sp, 4 + \\ jirl $ra, %[posixCallMainAndExit], 0 + , + .loongarch64 => + \\ move $fp, $zero + \\ move $ra, $zero + \\ move $a0, $sp + \\ bstrins.d $sp, $zero, 3, 0 + \\ jirl $ra, %[posixCallMainAndExit], 0 + , + else => unreachable, + } + : + : [posixCallMainAndExit] "r" (&posixCallMainAndExit), + : .{ .r1 = true, .r4 = true, .r22 = true }); + unreachable; + } + asm volatile (switch (native_arch) { .x86_64 => \\ xorl %%ebp, %%ebp diff --git a/lib/std/testing.zig b/lib/std/testing.zig index eebf3a5195c0d2407c7c51d3b67ef794011f6736..6bef15e8a196bfaf19da01b4eaccff86ee561b15 100644 --- a/lib/std/testing.zig +++ b/lib/std/testing.zig @@ -34,6 +34,7 @@ pub var log_level = std.log.Level.warn; // Disable printing in tests for simple backends. pub const backend_can_print = switch (builtin.zig_backend) { .stage2_aarch64, + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, .stage2_spirv, diff --git a/lib/ubsan_rt.zig b/lib/ubsan_rt.zig index b6fdc5f5aeedc901213ed96c14710904e6ee6336..8fce8a932bc6843c217dd951938a24f4184ccd4c 100644 --- a/lib/ubsan_rt.zig +++ b/lib/ubsan_rt.zig @@ -647,6 +647,7 @@ fn exportHandlerWithAbort( } const can_build_ubsan = switch (builtin.zig_backend) { + .stage2_loongarch, .stage2_powerpc, .stage2_riscv64, => false, -- 2.54.0