Commit 5d019abe4ec70373db7a75c2a8a3e2d76939817c | zig

lib/compiler/aro/aro/Compilation.zig+1-1

...	...	@@ -927,7 +927,7 @@ fn generateVaListType(comp: *Compilation) !Type {
927	927	.ios, .macos, .tvos, .watchos => .char_ptr,
928	928	else => .aarch64_va_list,
929	929	},
930		.sparc, .wasm32, .wasm64, .bpfel, .bpfeb, .riscv32, .riscv64, .avr, .spirv32, .spirv64 => .void_ptr,
	930	.sparc, .wasm32, .wasm64, .bpfel, .bpfeb, .riscv32, .riscv32be, .riscv64, .riscv64be, .avr, .spirv32, .spirv64 => .void_ptr,
931	931	.powerpc => switch (comp.target.os.tag) {
932	932	.ios, .macos, .tvos, .watchos, .aix => @as(Kind, .char_ptr),
933	933	else => return Type{ .specifier = .void }, // unknown

lib/compiler/aro/aro/target.zig+14-1

...	...	@@ -15,6 +15,7 @@ pub fn intMaxType(target: std.Target) Type {
15	15	.bpfeb,
16	16	.loongarch64,
17	17	.riscv64,
	18	.riscv64be,
18	19	.powerpc64,
19	20	.powerpc64le,
20	21	.ve,
...	...	@@ -47,6 +48,7 @@ pub fn intPtrType(target: std.Target) Type {
47	48	.csky,
48	49	.loongarch32,
49	50	.riscv32,
	51	.riscv32be,
50	52	.xcore,
51	53	.hexagon,
52	54	.m68k,
...	...	@@ -109,6 +111,7 @@ pub fn int64Type(target: std.Target) Type {
109	111	.loongarch64,
110	112	.ve,
111	113	.riscv64,
	114	.riscv64be,
112	115	.powerpc64,
113	116	.powerpc64le,
114	117	.bpfel,
...	...	@@ -138,7 +141,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
138	141	.arm, .armeb => 4,
139	142	.aarch64, .aarch64_be => 4,
140	143	.sparc, .sparc64 => 4,
141		.riscv64 => 2,
	144	.riscv64, .riscv64be => 2,
142	145	else => 1,
143	146	};
144	147	}
...	...	@@ -330,7 +333,9 @@ pub const FPSemantics = enum {
330	333	.armeb,
331	334	.hexagon,
332	335	.riscv32,
	336	.riscv32be,
333	337	.riscv64,
	338	.riscv64be,
334	339	.spirv32,
335	340	.spirv64,
336	341	=> return .IEEEHalf,
...	...	@@ -429,7 +434,9 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
429	434	.powerpc64 => "elf64ppc",
430	435	.powerpc64le => "elf64lppc",
431	436	.riscv32 => "elf32lriscv",
	437	.riscv32be => "elf32briscv",
432	438	.riscv64 => "elf64lriscv",
	439	.riscv64be => "elf64briscv",
433	440	.sparc => "elf32_sparc",
434	441	.sparc64 => "elf64_sparc",
435	442	.loongarch32 => "elf32loongarch",
...	...	@@ -477,6 +484,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
477	484	.powerpc,
478	485	.powerpcle,
479	486	.riscv32,
	487	.riscv32be,
480	488	.sparc,
481	489	.thumb,
482	490	.thumbeb,
...	...	@@ -502,6 +510,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
502	510	.powerpc64 => copy.cpu.arch = .powerpc,
503	511	.powerpc64le => copy.cpu.arch = .powerpcle,
504	512	.riscv64 => copy.cpu.arch = .riscv32,
	513	.riscv64be => copy.cpu.arch = .riscv32be,
505	514	.sparc64 => copy.cpu.arch = .sparc,
506	515	.x86_64 => copy.cpu.arch = .x86,
507	516	}
...	...	@@ -537,6 +546,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
537	546	.powerpc64,
538	547	.powerpc64le,
539	548	.riscv64,
	549	.riscv64be,
540	550	.s390x,
541	551	.sparc64,
542	552	.ve,
...	...	@@ -552,6 +562,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
552	562	.powerpc => copy.cpu.arch = .powerpc64,
553	563	.powerpcle => copy.cpu.arch = .powerpc64le,
554	564	.riscv32 => copy.cpu.arch = .riscv64,
	565	.riscv32be => copy.cpu.arch = .riscv64be,
555	566	.sparc => copy.cpu.arch = .sparc64,
556	567	.spirv32 => copy.cpu.arch = .spirv64,
557	568	.thumb => copy.cpu.arch = .aarch64,
...	...	@@ -595,7 +606,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
595	606	.powerpc64le => "powerpc64le",
596	607	.amdgcn => "amdgcn",
597	608	.riscv32 => "riscv32",
	609	.riscv32be => "riscv32be",
598	610	.riscv64 => "riscv64",
	611	.riscv64be => "riscv64be",
599	612	.sparc => "sparc",
600	613	.sparc64 => "sparc64",
601	614	.s390x => "s390x",

lib/compiler_rt/clear_cache.zig+1-4

...	...	@@ -39,10 +39,7 @@ fn clear_cache(start: usize, end: usize) callconv(.c) void {
39	39	.mips, .mipsel, .mips64, .mips64el => true,
40	40	else => false,
41	41	};
42		const riscv = switch (arch) {
43		.riscv32, .riscv64 => true,
44		else => false,
45		};
	42	const riscv = arch.isRISCV();
46	43	const powerpc64 = switch (arch) {
47	44	.powerpc64, .powerpc64le => true,
48	45	else => false,

lib/compiler_rt/common.zig+4

...	...	@@ -87,7 +87,9 @@ pub const gnu_f16_abi = switch (builtin.cpu.arch) {
87	87	.wasm32,
88	88	.wasm64,
89	89	.riscv64,
	90	.riscv64be,
90	91	.riscv32,
	92	.riscv32be,
91	93	=> false,
92	94
93	95	.x86, .x86_64 => true,
...	...	@@ -124,7 +126,9 @@ pub fn F16T(comptime OtherType: type) type {
124	126	.nvptx,
125	127	.nvptx64,
126	128	.riscv32,
	129	.riscv32be,
127	130	.riscv64,
	131	.riscv64be,
128	132	.spirv32,
129	133	.spirv64,
130	134	=> f16,

lib/std/Target.zig+45-11

...	...	@@ -1042,7 +1042,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1042	1042	.powerpc, .powerpcle => .PPC,
1043	1043	.powerpc64, .powerpc64le => .PPC64,
1044	1044	.propeller => .PROPELLER,
1045		.riscv32, .riscv64 => .RISCV,
	1045	.riscv32, .riscv32be, .riscv64, .riscv64be => .RISCV,
1046	1046	.s390x => .S390,
1047	1047	.sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
1048	1048	.sparc64 => .SPARCV9,
...	...	@@ -1099,6 +1099,8 @@ pub fn toCoffMachine(target: *const Target) std.coff.MachineType {
1099	1099	.powerpcle,
1100	1100	.powerpc64,
1101	1101	.powerpc64le,
	1102	.riscv32be,
	1103	.riscv64be,
1102	1104	.s390x,
1103	1105	.sparc,
1104	1106	.sparc64,
...	...	@@ -1310,7 +1312,9 @@ pub const Cpu = struct {
1310	1312	powerpc64le,
1311	1313	propeller,
1312	1314	riscv32,
	1315	riscv32be,
1313	1316	riscv64,
	1317	riscv64be,
1314	1318	s390x,
1315	1319	sparc,
1316	1320	sparc64,
...	...	@@ -1340,6 +1344,7 @@ pub const Cpu = struct {
1340	1344	// - sparcel
1341	1345	// - spir
1342	1346	// - spir64
	1347	// - spirv
1343	1348	// - tce
1344	1349	// - tcele
1345	1350
...	...	@@ -1396,7 +1401,7 @@ pub const Cpu = struct {
1396	1401	.nvptx, .nvptx64 => .nvptx,
1397	1402	.powerpc, .powerpcle, .powerpc64, .powerpc64le => .powerpc,
1398	1403	.propeller => .propeller,
1399		.riscv32, .riscv64 => .riscv,
	1404	.riscv32, .riscv32be, .riscv64, .riscv64be => .riscv,
1400	1405	.s390x => .s390x,
1401	1406	.sparc, .sparc64 => .sparc,
1402	1407	.spirv32, .spirv64 => .spirv,
...	...	@@ -1452,8 +1457,19 @@ pub const Cpu = struct {
1452	1457	}
1453	1458
1454	1459	pub inline fn isRISCV(arch: Arch) bool {
	1460	return arch.isRiscv32() or arch.isRiscv64();
	1461	}
	1462
	1463	pub inline fn isRiscv32(arch: Arch) bool {
	1464	return switch (arch) {
	1465	.riscv32, .riscv32be => true,
	1466	else => false,
	1467	};
	1468	}
	1469
	1470	pub inline fn isRiscv64(arch: Arch) bool {
1455	1471	return switch (arch) {
1456		.riscv32, .riscv64 => true,
	1472	.riscv64, .riscv64be => true,
1457	1473	else => false,
1458	1474	};
1459	1475	}
...	...	@@ -1576,6 +1592,8 @@ pub const Cpu = struct {
1576	1592	.or1k,
1577	1593	.powerpc,
1578	1594	.powerpc64,
	1595	.riscv32be,
	1596	.riscv64be,
1579	1597	.thumbeb,
1580	1598	.sparc,
1581	1599	.sparc64,
...	...	@@ -1688,12 +1706,12 @@ pub const Cpu = struct {
1688	1706	.riscv64_lp64,
1689	1707	.riscv64_lp64_v,
1690	1708	.riscv64_interrupt,
1691		=> &.{.riscv64},
	1709	=> &.{ .riscv64, .riscv64be },
1692	1710
1693	1711	.riscv32_ilp32,
1694	1712	.riscv32_ilp32_v,
1695	1713	.riscv32_interrupt,
1696		=> &.{.riscv32},
	1714	=> &.{ .riscv32, .riscv32be },
1697	1715
1698	1716	.sparc64_sysv,
1699	1717	=> &.{.sparc64},
...	...	@@ -1822,8 +1840,8 @@ pub const Cpu = struct {
1822	1840	.powerpc, .powerpcle => &powerpc.cpu.ppc,
1823	1841	.powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
1824	1842	.propeller => &propeller.cpu.p1,
1825		.riscv32 => &riscv.cpu.generic_rv32,
1826		.riscv64 => &riscv.cpu.generic_rv64,
	1843	.riscv32, .riscv32be => &riscv.cpu.generic_rv32,
	1844	.riscv64, .riscv64be => &riscv.cpu.generic_rv64,
1827	1845	.sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
1828	1846	.wasm32, .wasm64 => &wasm.cpu.mvp,
1829	1847	.x86 => &x86.cpu.i386,
...	...	@@ -1867,8 +1885,8 @@ pub const Cpu = struct {
1867	1885	.msp430 => &msp430.cpu.msp430,
1868	1886	.nvptx, .nvptx64 => &nvptx.cpu.sm_52,
1869	1887	.powerpc64le => &powerpc.cpu.ppc64le,
1870		.riscv32 => &riscv.cpu.baseline_rv32,
1871		.riscv64 => &riscv.cpu.baseline_rv64,
	1888	.riscv32, .riscv32be => &riscv.cpu.baseline_rv32,
	1889	.riscv64, .riscv64be => &riscv.cpu.baseline_rv64,
1872	1890	.s390x => &s390x.cpu.arch8, // gcc/clang do not have a generic s390x model.
1873	1891	.sparc => &sparc.cpu.v9, // glibc does not work with 'plain' v8.
1874	1892	.x86 => &x86.cpu.pentium4,
...	...	@@ -2615,6 +2633,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2615	2633	.powerpc,
2616	2634	.powerpcle,
2617	2635	.riscv32,
	2636	.riscv32be,
2618	2637	.thumb,
2619	2638	.thumbeb,
2620	2639	.x86,
...	...	@@ -2637,6 +2656,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2637	2656	.powerpc64,
2638	2657	.powerpc64le,
2639	2658	.riscv64,
	2659	.riscv64be,
2640	2660	.x86_64,
2641	2661	.nvptx64,
2642	2662	.wasm64,
...	...	@@ -2691,7 +2711,9 @@ pub fn stackAlignment(target: *const Target) u16 {
2691	2711	.powerpc64le,
2692	2712	=> if (target.os.tag == .linux or target.os.tag == .aix) return 16,
2693	2713	.riscv32,
	2714	.riscv32be,
2694	2715	.riscv64,
	2716	.riscv64be,
2695	2717	=> if (!target.cpu.has(.riscv, .e)) return 16,
2696	2718	.x86 => if (target.os.tag != .windows and target.os.tag != .uefi) return 16,
2697	2719	.x86_64 => return 16,
...	...	@@ -2724,7 +2746,9 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
2724	2746	.powerpc64le,
2725	2747	.s390x,
2726	2748	.riscv32,
	2749	.riscv32be,
2727	2750	.riscv64,
	2751	.riscv64be,
2728	2752	.xcore,
2729	2753	.xtensa,
2730	2754	=> .unsigned,
...	...	@@ -2838,7 +2862,9 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
2838	2862	},
2839	2863
2840	2864	.riscv32,
	2865	.riscv32be,
2841	2866	.riscv64,
	2867	.riscv64be,
2842	2868	.aarch64,
2843	2869	.aarch64_be,
2844	2870	.s390x,
...	...	@@ -2957,7 +2983,9 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
2957	2983	},
2958	2984
2959	2985	.riscv32,
	2986	.riscv32be,
2960	2987	.riscv64,
	2988	.riscv64be,
2961	2989	.aarch64,
2962	2990	.aarch64_be,
2963	2991	.s390x,
...	...	@@ -3169,7 +3197,9 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3169	3197	.powerpc64,
3170	3198	.powerpc64le,
3171	3199	.riscv32,
	3200	.riscv32be,
3172	3201	.riscv64,
	3202	.riscv64be,
3173	3203	.sparc64,
3174	3204	.spirv32,
3175	3205	.spirv64,
...	...	@@ -3261,7 +3291,9 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3261	3291	.powerpc64,
3262	3292	.powerpc64le,
3263	3293	.riscv32,
	3294	.riscv32be,
3264	3295	.riscv64,
	3296	.riscv64be,
3265	3297	.sparc64,
3266	3298	.spirv32,
3267	3299	.spirv64,
...	...	@@ -3300,6 +3332,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3300	3332	.powerpc,
3301	3333	.powerpcle,
3302	3334	.riscv32,
	3335	.riscv32be,
3303	3336	.s390x,
3304	3337	=> 8,
3305	3338
...	...	@@ -3315,6 +3348,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3315	3348	.powerpc64,
3316	3349	.powerpc64le,
3317	3350	.riscv64,
	3351	.riscv64be,
3318	3352	.sparc,
3319	3353	.sparc64,
3320	3354	.wasm32,
...	...	@@ -3364,8 +3398,8 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3364	3398	else => .{ .mips64_n64 = .{} },
3365	3399	},
3366	3400	.mips, .mipsel => .{ .mips_o32 = .{} },
3367		.riscv64 => .{ .riscv64_lp64 = .{} },
3368		.riscv32 => .{ .riscv32_ilp32 = .{} },
	3401	.riscv64, .riscv64be => .{ .riscv64_lp64 = .{} },
	3402	.riscv32, .riscv32be => .{ .riscv32_ilp32 = .{} },
3369	3403	.sparc64 => .{ .sparc64_sysv = .{} },
3370	3404	.sparc => .{ .sparc_sysv = .{} },
3371	3405	.powerpc64 => if (target.abi.isMusl())

lib/std/atomic.zig+2

...	...	@@ -386,7 +386,9 @@ pub inline fn spinLoopHint() void {
386	386	=> asm volatile ("pause(#1)"),
387	387
388	388	.riscv32,
	389	.riscv32be,
389	390	.riscv64,
	391	.riscv64be,
390	392	=> if (comptime builtin.cpu.has(.riscv, .zihintpause)) {
391	393	asm volatile ("pause");
392	394	},

lib/std/builtin.zig+1-1

...	...	@@ -909,7 +909,7 @@ pub const VaList = switch (builtin.cpu.arch) {
909	909	.hexagon => if (builtin.target.abi.isMusl()) VaListHexagon else *u8,
910	910	.loongarch32, .loongarch64 => *anyopaque,
911	911	.mips, .mipsel, .mips64, .mips64el => *anyopaque,
912		.riscv32, .riscv64 => *anyopaque,
	912	.riscv32, .riscv32be, .riscv64, .riscv64be => *anyopaque,
913	913	.powerpc, .powerpcle => switch (builtin.os.tag) {
914	914	.ios, .macos, .tvos, .watchos, .visionos, .aix => *u8,
915	915	else => VaListPowerPc,

lib/std/builtin/assembly.zig+1-1

...	...	@@ -641,7 +641,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
641	641	q14: bool = false,
642	642	q15: bool = false,
643	643	},
644		.riscv32, .riscv64 => packed struct {
	644	.riscv32, .riscv32be, .riscv64, .riscv64be => packed struct {
645	645	/// Whether the inline assembly code may perform stores to memory
646	646	/// addresses other than those derived from input pointer provenance.
647	647	memory: bool = false,

lib/std/debug/Dwarf/abi.zig+1-1

...	...	@@ -20,7 +20,7 @@ pub fn supportsUnwinding(target: *const std.Target) bool {
20	20
21	21	// Enabling this causes relocation errors such as:
22	22	// error: invalid relocation type R_RISCV_SUB32 at offset 0x20
23		.riscv64, .riscv32 => false,
	23	.riscv64, .riscv64be, .riscv32, .riscv32be => false,
24	24
25	25	// Conservative guess. Feel free to update this logic with any targets
26	26	// that are known to not support Dwarf unwinding.

lib/std/pie.zig+2-2

...	...	@@ -30,7 +30,7 @@ const R_RELATIVE = switch (builtin.cpu.arch) {
30	30	.m68k => R_68K_RELATIVE,
31	31	.mips, .mipsel, .mips64, .mips64el => R_MIPS_RELATIVE,
32	32	.powerpc, .powerpcle, .powerpc64, .powerpc64le => R_PPC_RELATIVE,
33		.riscv32, .riscv64 => R_RISCV_RELATIVE,
	33	.riscv32, .riscv32be, .riscv64, .riscv64be => R_RISCV_RELATIVE,
34	34	.s390x => R_390_RELATIVE,
35	35	.sparc, .sparc64 => R_SPARC_RELATIVE,
36	36	else => @compileError("Missing R_RELATIVE definition for this target"),
...	...	@@ -163,7 +163,7 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
163	163	: [ret] "=r" (-> [*]const elf.Dyn),
164	164	:
165	165	: .{ .lr = true, .r4 = true }),
166		.riscv32, .riscv64 => asm volatile (
	166	.riscv32, .riscv32be, .riscv64, .riscv64be => asm volatile (
167	167	\\ .weak _DYNAMIC
168	168	\\ .hidden _DYNAMIC
169	169	\\ lla %[ret], _DYNAMIC

lib/std/start.zig+2-2

...	...	@@ -203,7 +203,7 @@ fn _start() callconv(.naked) noreturn {
203	203	.m68k => ".cfi_undefined %%pc",
204	204	.mips, .mipsel, .mips64, .mips64el => ".cfi_undefined $ra",
205	205	.powerpc, .powerpcle, .powerpc64, .powerpc64le => ".cfi_undefined lr",
206		.riscv32, .riscv64 => if (builtin.zig_backend == .stage2_riscv64)
	206	.riscv32, .riscv32be, .riscv64, .riscv64be => if (builtin.zig_backend == .stage2_riscv64)
207	207	""
208	208	else
209	209	".cfi_undefined ra",
...	...	@@ -305,7 +305,7 @@ fn _start() callconv(.naked) noreturn {
305	305	\\ bstrins.d $sp, $zero, 3, 0
306	306	\\ b %[posixCallMainAndExit]
307	307	,
308		.riscv32, .riscv64 =>
	308	.riscv32, .riscv32be, .riscv64, .riscv64be =>
309	309	\\ li fp, 0
310	310	\\ li ra, 0
311	311	\\ mv a0, sp

src/Compilation.zig+1-1

...	...	@@ -7051,7 +7051,7 @@ pub fn addCCArgs(
7051	7051	// compiler frontend does. Therefore we must hard-code the -m flags for
7052	7052	// all CPU features here.
7053	7053	switch (target.cpu.arch) {
7054		.riscv32, .riscv64 => {
	7054	.riscv32, .riscv32be, .riscv64, .riscv64be => {
7055	7055	const RvArchFeat = struct { char: u8, feat: std.Target.riscv.Feature };
7056	7056	const letters = [_]RvArchFeat{
7057	7057	.{ .char = 'm', .feat = .m },

src/Zcu.zig+2

...	...	@@ -3850,6 +3850,7 @@ pub fn atomicPtrAlignment(
3850	3850	.powerpc,
3851	3851	.powerpcle,
3852	3852	.riscv32,
	3853	.riscv32be,
3853	3854	.sparc,
3854	3855	.thumb,
3855	3856	.thumbeb,
...	...	@@ -3874,6 +3875,7 @@ pub fn atomicPtrAlignment(
3874	3875	.powerpc64,
3875	3876	.powerpc64le,
3876	3877	.riscv64,
	3878	.riscv64be,
3877	3879	.sparc64,
3878	3880	.s390x,
3879	3881	.wasm64,

src/codegen/llvm.zig+14-4

...	...	@@ -82,7 +82,9 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
82	82	.powerpc64le => "powerpc64le",
83	83	.amdgcn => "amdgcn",
84	84	.riscv32 => "riscv32",
	85	.riscv32be => "riscv32be",
85	86	.riscv64 => "riscv64",
	87	.riscv64be => "riscv64be",
86	88	.sparc => "sparc",
87	89	.sparc64 => "sparc64",
88	90	.s390x => "s390x",
...	...	@@ -397,10 +399,18 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
397	399	"e-m:e-p:32:32-i64:64-n32-S32"
398	400	else
399	401	"e-m:e-p:32:32-i64:64-n32-S128",
	402	.riscv32be => if (target.cpu.has(.riscv, .e))
	403	"E-m:e-p:32:32-i64:64-n32-S32"
	404	else
	405	"E-m:e-p:32:32-i64:64-n32-S128",
400	406	.riscv64 => if (target.cpu.has(.riscv, .e))
401	407	"e-m:e-p:64:64-i64:64-i128:128-n32:64-S64"
402	408	else
403	409	"e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
	410	.riscv64be => if (target.cpu.has(.riscv, .e))
	411	"E-m:e-p:64:64-i64:64-i128:128-n32:64-S64"
	412	else
	413	"E-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
404	414	.sparc => "E-m:e-p:32:32-i64:64-i128:128-f128:64-n32-S64",
405	415	.sparc64 => "E-m:e-i64:64-i128:128-n32:64-S128",
406	416	.s390x => if (target.os.tag == .zos)
...	...	@@ -12224,8 +12234,8 @@ fn lowerFnRetTy(o: *Object, pt: Zcu.PerThread, fn_info: InternPool.Key.FuncType)
12224	12234	.integer => return o.builder.intType(@intCast(return_type.bitSize(zcu))),
12225	12235	.double_integer => {
12226	12236	const integer: Builder.Type = switch (zcu.getTarget().cpu.arch) {
12227		.riscv64 => .i64,
12228		.riscv32 => .i32,
	12237	.riscv64, .riscv64be => .i64,
	12238	.riscv32, .riscv32be => .i32,
12229	12239	else => unreachable,
12230	12240	};
12231	12241	return o.builder.structType(.normal, &.{ integer, integer });
...	...	@@ -12685,7 +12695,7 @@ fn ccAbiPromoteInt(
12685	12695	else => null,
12686	12696	},
12687	12697	else => switch (target.cpu.arch) {
12688		.loongarch64, .riscv64 => switch (int_info.bits) {
	12698	.loongarch64, .riscv64, .riscv64be => switch (int_info.bits) {
12689	12699	0...16 => int_info.signedness,
12690	12700	32 => .signed, // LLVM always signextends 32 bit ints, unsure if bug.
12691	12701	17...31, 33...63 => int_info.signedness,
...	...	@@ -13079,7 +13089,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13079	13089	llvm.LLVMInitializePowerPCAsmPrinter();
13080	13090	llvm.LLVMInitializePowerPCAsmParser();
13081	13091	},
13082		.riscv32, .riscv64 => {
	13092	.riscv32, .riscv32be, .riscv64, .riscv64be => {
13083	13093	llvm.LLVMInitializeRISCVTarget();
13084	13094	llvm.LLVMInitializeRISCVTargetInfo();
13085	13095	llvm.LLVMInitializeRISCVTargetMC();

src/link/Elf.zig+8-8

...	...	@@ -3722,8 +3722,8 @@ pub fn tpAddress(self: *Elf) i64 {
3722	3722	const phdr = self.phdrs.items[index];
3723	3723	const addr = switch (self.getTarget().cpu.arch) {
3724	3724	.x86_64 => mem.alignForward(u64, phdr.p_vaddr + phdr.p_memsz, phdr.p_align),
3725		.aarch64 => mem.alignBackward(u64, phdr.p_vaddr - 16, phdr.p_align),
3726		.riscv64 => phdr.p_vaddr,
	3725	.aarch64, .aarch64_be => mem.alignBackward(u64, phdr.p_vaddr - 16, phdr.p_align),
	3726	.riscv64, .riscv64be => phdr.p_vaddr,
3727	3727	else => \|arch\| std.debug.panic("TODO implement getTpAddress for {s}", .{@tagName(arch)}),
3728	3728	};
3729	3729	return @intCast(addr);
...	...	@@ -4099,8 +4099,8 @@ pub fn getTarget(self: const Elf) const std.Target {
4099	4099
4100	4100	fn requiresThunks(self: Elf) bool {
4101	4101	return switch (self.getTarget().cpu.arch) {
4102		.aarch64 => true,
4103		.x86_64, .riscv64 => false,
	4102	.aarch64, .aarch64_be => true,
	4103	.x86_64, .riscv64, .riscv64be => false,
4104	4104	else => @panic("TODO unimplemented architecture"),
4105	4105	};
4106	4106	}
...	...	@@ -4345,8 +4345,8 @@ fn createThunks(elf_file: Elf, atom_list: AtomList) !void {
4345	4345	// A branch will need an extender if its target is larger than
4346	4346	// `2^(jump_bits - 1) - margin` where margin is some arbitrary number.
4347	4347	const max_distance = switch (cpu_arch) {
4348		.aarch64 => 0x500_000,
4349		.x86_64, .riscv64 => unreachable,
	4348	.aarch64, .aarch64_be => 0x500_000,
	4349	.x86_64, .riscv64, .riscv64be => unreachable,
4350	4350	else => @panic("unhandled arch"),
4351	4351	};
4352	4352
...	...	@@ -4392,7 +4392,7 @@ fn createThunks(elf_file: Elf, atom_list: AtomList) !void {
4392	4392	log.debug("atom({f}) {s}", .{ ref, atom_ptr.name(elf_file) });
4393	4393	for (atom_ptr.relocs(elf_file)) \|rel\| {
4394	4394	const is_reachable = switch (cpu_arch) {
4395		.aarch64 => r: {
	4395	.aarch64, .aarch64_be => r: {
4396	4396	const r_type: elf.R_AARCH64 = @enumFromInt(rel.r_type());
4397	4397	if (r_type != .CALL26 and r_type != .JUMP26) break :r true;
4398	4398	const target_ref = file_ptr.resolveSymbol(rel.r_sym(), elf_file);
...	...	@@ -4406,7 +4406,7 @@ fn createThunks(elf_file: Elf, atom_list: AtomList) !void {
4406	4406	_ = math.cast(i28, taddr + rel.r_addend - saddr) orelse break :r false;
4407	4407	break :r true;
4408	4408	},
4409		.x86_64, .riscv64 => unreachable,
	4409	.x86_64, .riscv64, .riscv64be => unreachable,
4410	4410	else => @panic("unsupported arch"),
4411	4411	};
4412	4412	if (is_reachable) continue;

src/link/Elf/Atom.zig+6-6

...	...	@@ -346,11 +346,11 @@ pub fn scanRelocs(self: Atom, elf_file: *Elf, code: ?[]const u8, undefs: anytype
346	346	error.RelocFailure => has_reloc_errors = true,
347	347	else => \|e\| return e,
348	348	},
349		.aarch64 => aarch64.scanReloc(self, elf_file, rel, symbol, code, &it) catch \|err\| switch (err) {
	349	.aarch64, .aarch64_be => aarch64.scanReloc(self, elf_file, rel, symbol, code, &it) catch \|err\| switch (err) {
350	350	error.RelocFailure => has_reloc_errors = true,
351	351	else => \|e\| return e,
352	352	},
353		.riscv64 => riscv.scanReloc(self, elf_file, rel, symbol, code, &it) catch \|err\| switch (err) {
	353	.riscv64, .riscv64be => riscv.scanReloc(self, elf_file, rel, symbol, code, &it) catch \|err\| switch (err) {
354	354	error.RelocFailure => has_reloc_errors = true,
355	355	else => \|e\| return e,
356	356	},
...	...	@@ -674,7 +674,7 @@ pub fn resolveRelocsAlloc(self: Atom, elf_file: *Elf, code: []u8) RelocError!voi
674	674	=> has_reloc_errors = true,
675	675	else => \|e\| return e,
676	676	},
677		.aarch64 => aarch64.resolveRelocAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
	677	.aarch64, .aarch64_be => aarch64.resolveRelocAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
678	678	error.RelocFailure,
679	679	error.RelaxFailure,
680	680	error.UnexpectedRemainder,
...	...	@@ -682,7 +682,7 @@ pub fn resolveRelocsAlloc(self: Atom, elf_file: *Elf, code: []u8) RelocError!voi
682	682	=> has_reloc_errors = true,
683	683	else => \|e\| return e,
684	684	},
685		.riscv64 => riscv.resolveRelocAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
	685	.riscv64, .riscv64be => riscv.resolveRelocAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
686	686	error.RelocFailure,
687	687	error.RelaxFailure,
688	688	=> has_reloc_errors = true,
...	...	@@ -870,11 +870,11 @@ pub fn resolveRelocsNonAlloc(self: Atom, elf_file: *Elf, code: []u8, undefs: any
870	870	error.RelocFailure => has_reloc_errors = true,
871	871	else => \|e\| return e,
872	872	},
873		.aarch64 => aarch64.resolveRelocNonAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
	873	.aarch64, .aarch64_be => aarch64.resolveRelocNonAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
874	874	error.RelocFailure => has_reloc_errors = true,
875	875	else => \|e\| return e,
876	876	},
877		.riscv64 => riscv.resolveRelocNonAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
	877	.riscv64, .riscv64be => riscv.resolveRelocNonAlloc(self, elf_file, rel, target, args, &it, code, &stream) catch \|err\| switch (err) {
878	878	error.RelocFailure => has_reloc_errors = true,
879	879	else => \|e\| return e,
880	880	},

src/link/Elf/Object.zig+3-3

...	...	@@ -189,7 +189,7 @@ pub fn validateEFlags(
189	189	e_flags: elf.Word,
190	190	) !void {
191	191	switch (target.cpu.arch) {
192		.riscv64 => {
	192	.riscv64, .riscv64be => {
193	193	const flags: riscv.Eflags = @bitCast(e_flags);
194	194	var any_errors: bool = false;
195	195
...	...	@@ -366,7 +366,7 @@ fn initAtoms(
366	366	const rel_count: u32 = @intCast(relocs.len);
367	367	self.setAtomFields(atom_ptr, .{ .rel_index = rel_index, .rel_count = rel_count });
368	368	try self.relocs.appendUnalignedSlice(gpa, relocs);
369		if (target.cpu.arch == .riscv64) {
	369	if (target.cpu.arch.isRiscv64()) {
370	370	sortRelocs(self.relocs.items[rel_index..][0..rel_count]);
371	371	}
372	372	}
...	...	@@ -445,7 +445,7 @@ fn parseEhFrame(
445	445	// We expect relocations to be sorted by r_offset as per this comment in mold linker:
446	446	// https://github.com/rui314/mold/blob/8e4f7b53832d8af4f48a633a8385cbc932d1944e/src/input-files.cc#L653
447	447	// Except for RISCV and Loongarch which do not seem to be uphold this convention.
448		if (target.cpu.arch == .riscv64) {
	448	if (target.cpu.arch.isRiscv64()) {
449	449	sortRelocs(self.relocs.items[rel_start..][0..relocs.len]);
450	450	}
451	451	const fdes_start = self.fdes.items.len;

src/link/Elf/Thunk.zig+4-4

...	...	@@ -24,8 +24,8 @@ pub fn targetAddress(thunk: Thunk, ref: Elf.Ref, elf_file: *Elf) i64 {
24	24
25	25	pub fn write(thunk: Thunk, elf_file: *Elf, writer: anytype) !void {
26	26	switch (elf_file.getTarget().cpu.arch) {
27		.aarch64 => try aarch64.write(thunk, elf_file, writer),
28		.x86_64, .riscv64 => unreachable,
	27	.aarch64, .aarch64_be => try aarch64.write(thunk, elf_file, writer),
	28	.x86_64, .riscv64, .riscv64be => unreachable,
29	29	else => @panic("unhandled arch"),
30	30	}
31	31	}
...	...	@@ -59,8 +59,8 @@ pub fn writeSymtab(thunk: Thunk, elf_file: *Elf) void {
59	59
60	60	fn trampolineSize(cpu_arch: std.Target.Cpu.Arch) usize {
61	61	return switch (cpu_arch) {
62		.aarch64 => aarch64.trampoline_size,
63		.x86_64, .riscv64 => unreachable,
	62	.aarch64, .aarch64_be => aarch64.trampoline_size,
	63	.x86_64, .riscv64, .riscv64be => unreachable,
64	64	else => @panic("unhandled arch"),
65	65	};
66	66	}

src/link/Elf/eh_frame.zig+2-2

...	...	@@ -286,8 +286,8 @@ fn resolveReloc(rec: anytype, sym: *const Symbol, rel: elf.Elf64_Rela, elf_file:
286	286
287	287	switch (cpu_arch) {
288	288	.x86_64 => try x86_64.resolveReloc(rec, elf_file, rel, P, S + A, contents[offset..]),
289		.aarch64 => try aarch64.resolveReloc(rec, elf_file, rel, P, S + A, contents[offset..]),
290		.riscv64 => try riscv.resolveReloc(rec, elf_file, rel, P, S + A, contents[offset..]),
	289	.aarch64, .aarch64_be => try aarch64.resolveReloc(rec, elf_file, rel, P, S + A, contents[offset..]),
	290	.riscv64, .riscv64be => try riscv.resolveReloc(rec, elf_file, rel, P, S + A, contents[offset..]),
291	291	else => return error.UnsupportedCpuArch,
292	292	}
293	293	}

src/link/Elf/relocation.zig+10-10

...	...	@@ -76,8 +76,8 @@ const riscv64_relocs = Table(11, elf.R_RISCV, .{
76	76	pub fn decode(r_type: u32, cpu_arch: std.Target.Cpu.Arch) ?Kind {
77	77	return switch (cpu_arch) {
78	78	.x86_64 => x86_64_relocs.decode(r_type),
79		.aarch64 => aarch64_relocs.decode(r_type),
80		.riscv64 => riscv64_relocs.decode(r_type),
	79	.aarch64, .aarch64_be => aarch64_relocs.decode(r_type),
	80	.riscv64, .riscv64be => riscv64_relocs.decode(r_type),
81	81	else => @panic("TODO unhandled cpu arch"),
82	82	};
83	83	}
...	...	@@ -85,8 +85,8 @@ pub fn decode(r_type: u32, cpu_arch: std.Target.Cpu.Arch) ?Kind {
85	85	pub fn encode(comptime kind: Kind, cpu_arch: std.Target.Cpu.Arch) u32 {
86	86	return switch (cpu_arch) {
87	87	.x86_64 => x86_64_relocs.encode(kind),
88		.aarch64 => aarch64_relocs.encode(kind),
89		.riscv64 => riscv64_relocs.encode(kind),
	88	.aarch64, .aarch64_be => aarch64_relocs.encode(kind),
	89	.riscv64, .riscv64be => riscv64_relocs.encode(kind),
90	90	else => @panic("TODO unhandled cpu arch"),
91	91	};
92	92	}
...	...	@@ -98,11 +98,11 @@ pub const dwarf = struct {
98	98	.@"32" => .@"32",
99	99	.@"64" => .@"64",
100	100	})),
101		.aarch64 => @intFromEnum(@as(elf.R_AARCH64, switch (format) {
	101	.aarch64, .aarch64_be => @intFromEnum(@as(elf.R_AARCH64, switch (format) {
102	102	.@"32" => .ABS32,
103	103	.@"64" => .ABS64,
104	104	})),
105		.riscv64 => @intFromEnum(@as(elf.R_RISCV, switch (format) {
	105	.riscv64, .riscv64be => @intFromEnum(@as(elf.R_RISCV, switch (format) {
106	106	.@"32" => .@"32",
107	107	.@"64" => .@"64",
108	108	})),
...	...	@@ -125,7 +125,7 @@ pub const dwarf = struct {
125	125	},
126	126	.debug_frame => .PC32,
127	127	})),
128		.aarch64 => @intFromEnum(@as(elf.R_AARCH64, switch (source_section) {
	128	.aarch64, .aarch64_be => @intFromEnum(@as(elf.R_AARCH64, switch (source_section) {
129	129	else => switch (address_size) {
130	130	.@"32" => .ABS32,
131	131	.@"64" => .ABS64,
...	...	@@ -133,7 +133,7 @@ pub const dwarf = struct {
133	133	},
134	134	.debug_frame => .PREL32,
135	135	})),
136		.riscv64 => @intFromEnum(@as(elf.R_RISCV, switch (source_section) {
	136	.riscv64, .riscv64be => @intFromEnum(@as(elf.R_RISCV, switch (source_section) {
137	137	else => switch (address_size) {
138	138	.@"32" => .@"32",
139	139	.@"64" => .@"64",
...	...	@@ -164,8 +164,8 @@ fn formatRelocType(ctx: FormatRelocTypeCtx, writer: *std.io.Writer) std.io.Write
164	164	const r_type = ctx.r_type;
165	165	switch (ctx.cpu_arch) {
166	166	.x86_64 => try writer.print("R_X86_64_{s}", .{@tagName(@as(elf.R_X86_64, @enumFromInt(r_type)))}),
167		.aarch64 => try writer.print("R_AARCH64_{s}", .{@tagName(@as(elf.R_AARCH64, @enumFromInt(r_type)))}),
168		.riscv64 => try writer.print("R_RISCV_{s}", .{@tagName(@as(elf.R_RISCV, @enumFromInt(r_type)))}),
	167	.aarch64, .aarch64_be => try writer.print("R_AARCH64_{s}", .{@tagName(@as(elf.R_AARCH64, @enumFromInt(r_type)))}),
	168	.riscv64, .riscv64be => try writer.print("R_RISCV_{s}", .{@tagName(@as(elf.R_RISCV, @enumFromInt(r_type)))}),
169	169	else => unreachable,
170	170	}
171	171	}

src/link/Lld.zig+2

...	...	@@ -1342,7 +1342,9 @@ fn getLDMOption(target: *const std.Target) ?[]const u8 {
1342	1342	.powerpc64 => "elf64ppc",
1343	1343	.powerpc64le => "elf64lppc",
1344	1344	.riscv32 => "elf32lriscv",
	1345	.riscv32be => "elf32briscv",
1345	1346	.riscv64 => "elf64lriscv",
	1347	.riscv64be => "elf64briscv",
1346	1348	.s390x => "elf64_s390",
1347	1349	.sparc64 => "elf64_sparc",
1348	1350	.x86 => switch (target.os.tag) {

src/target.zig+8-2

...	...	@@ -189,7 +189,9 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
189	189	.powerpc64le,
190	190	.amdgcn,
191	191	.riscv32,
	192	.riscv32be,
192	193	.riscv64,
	194	.riscv64be,
193	195	.sparc,
194	196	.sparc64,
195	197	.spirv32,
...	...	@@ -486,7 +488,9 @@ pub fn clangSupportsNoImplicitFloatArg(target: *const std.Target) bool {
486	488	.thumb,
487	489	.thumbeb,
488	490	.riscv32,
	491	.riscv32be,
489	492	.riscv64,
	493	.riscv64be,
490	494	.x86,
491	495	.x86_64,
492	496	=> true,
...	...	@@ -655,7 +659,7 @@ pub fn llvmMachineAbi(target: *const std.Target) ?[:0]const u8 {
655	659	else => if (target.abi.isMusl()) "elfv2" else "elfv1",
656	660	},
657	661	.powerpc64le => "elfv2",
658		.riscv64 => if (target.cpu.has(.riscv, .e))
	662	.riscv64, .riscv64be => if (target.cpu.has(.riscv, .e))
659	663	"lp64e"
660	664	else if (target.cpu.has(.riscv, .d))
661	665	"lp64d"
...	...	@@ -663,7 +667,7 @@ pub fn llvmMachineAbi(target: *const std.Target) ?[:0]const u8 {
663	667	"lp64f"
664	668	else
665	669	"lp64",
666		.riscv32 => if (target.cpu.has(.riscv, .e))
	670	.riscv32, .riscv32be => if (target.cpu.has(.riscv, .e))
667	671	"ilp32e"
668	672	else if (target.cpu.has(.riscv, .d))
669	673	"ilp32d"
...	...	@@ -707,7 +711,9 @@ pub fn defaultFunctionAlignment(target: *const std.Target) Alignment {
707	711	pub fn minFunctionAlignment(target: *const std.Target) Alignment {
708	712	return switch (target.cpu.arch) {
709	713	.riscv32,
	714	.riscv32be,
710	715	.riscv64,
	716	.riscv64be,
711	717	=> if (target.cpu.hasAny(.riscv, &.{ .c, .zca })) .@"2" else .@"4",
712	718	.thumb,
713	719	.thumbeb,

test/llvm_targets.zig+4

...	...	@@ -217,6 +217,8 @@ const targets = [_]std.Target.Query{
217	217	.{ .cpu_arch = .riscv32, .os_tag = .rtems, .abi = .none },
218	218	// .{ .cpu_arch = .riscv32, .os_tag = .uefi, .abi = .none },
219	219
	220	// .{ .cpu_arch = .riscv32be, .os_tag = .freestanding, .abi = .none },
	221
220	222	.{ .cpu_arch = .riscv64, .os_tag = .freebsd, .abi = .none },
221	223	.{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },
222	224	.{ .cpu_arch = .riscv64, .os_tag = .fuchsia, .abi = .none },
...	...	@@ -231,6 +233,8 @@ const targets = [_]std.Target.Query{
231	233	.{ .cpu_arch = .riscv64, .os_tag = .serenity, .abi = .none },
232	234	// .{ .cpu_arch = .riscv64, .os_tag = .uefi, .abi = .none },
233	235
	236	// .{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },
	237
234	238	.{ .cpu_arch = .s390x, .os_tag = .freestanding, .abi = .none },
235	239	.{ .cpu_arch = .s390x, .os_tag = .linux, .abi = .gnu },
236	240	.{ .cpu_arch = .s390x, .os_tag = .linux, .abi = .none },

author	Alex Rønne Petersen <alex@alexrp.com> 2025-08-24 21:23:45+02:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2025-08-25 16:15:17+02:00
log	5d019abe4ec70373db7a75c2a8a3e2d76939817c
tree	4ca5e04afceab7cc8e363d7adfe0436f54a3e82a
parent	12686d9b7df8fe4c2663cd8e2136991dc3cf661c

start adding big endian RISC-V support