authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-07-16 16:54:12+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-07-16 16:54:12+02:00
log6002514b72cb2a571abc6ac4ac7fbec44d6302b1
treef8e0c714e600cf31350e188c73059f63f02bf2a0
parent89ab6b161d39e0f6338930b2c06dbff891d1f768
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

test: mark riscv soft float targets as extra targets

Soft float is a very rare use case for riscv*-linux. No point wasting CI resources on these targets, especially since our arm and mips soft float coverage is already likely to catch most soft float bugs.

1 files changed, 4 insertions(+), 0 deletions(-)

test/tests.zig+4
......@@ -847,6 +847,7 @@ const test_targets = blk: {
847847 .arch_os_abi = "riscv32-linux-none",
848848 .cpu_features = "baseline-d-f",
849849 }) catch unreachable,
850 .extra_target = true,
850851 },
851852 .{
852853 .target = .{
......@@ -872,6 +873,7 @@ const test_targets = blk: {
872873 .cpu_features = "baseline-d-f",
873874 }) catch unreachable,
874875 .link_libc = true,
876 .extra_target = true,
875877 },
876878 .{
877879 .target = .{
......@@ -904,6 +906,7 @@ const test_targets = blk: {
904906 .arch_os_abi = "riscv64-linux-none",
905907 .cpu_features = "baseline-d-f",
906908 }) catch unreachable,
909 .extra_target = true,
907910 },
908911 .{
909912 .target = .{
......@@ -929,6 +932,7 @@ const test_targets = blk: {
929932 .cpu_features = "baseline-d-f",
930933 }) catch unreachable,
931934 .link_libc = true,
935 .extra_target = true,
932936 },
933937 .{
934938 .target = .{