authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-01-29 13:15:44+01:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2022-01-30 19:41:51-05:00
log66cf011aa91a66fd8b1489d186152522ccd27550
tree64659dd08ae747a56d181b5641d886651bd4f9ab
parent227968d78c4d0c6eaa92ecae4649bfc757af2c28

stage2 ARM: Move to new regalloc freeze API

1 files changed, 87 insertions(+), 32 deletions(-)

src/arch/arm/CodeGen.zig+87-32
......@@ -629,6 +629,9 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
629629 .wrap_errunion_err => try self.airWrapErrUnionErr(inst),
630630 // zig fmt: on
631631 }
632
633 assert(!self.register_manager.frozenRegsExist());
634
632635 if (std.debug.runtime_safety) {
633636 if (self.air_bookkeeping < old_air_bookkeeping + 1) {
634637 std.debug.panic("in codegen.zig, handling of AIR instruction %{d} ('{}') did not do proper bookkeeping. Look for a missing call to finishAir.", .{ inst, air_tags[inst] });
......@@ -1233,18 +1236,21 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12331236 // of two (includes elem_size == 1)
12341237 const offset_mcv = try self.genArmMulConstant(inst, bin_op.rhs, 1, @intCast(u32, elem_size));
12351238 assert(offset_mcv == .register); // result of multiplication should always be register
1239 self.register_manager.freezeRegs(&.{offset_mcv.register});
1240 defer self.register_manager.unfreezeRegs(&.{offset_mcv.register});
12361241
12371242 const base_mcv: MCValue = switch (slice_mcv) {
1238 .stack_offset => |off| blk: {
1239 const reg = try self.register_manager.allocReg(null, &.{offset_mcv.register});
1240 try self.genSetReg(slice_ptr_field_type, reg, MCValue{ .stack_offset = off });
1241 break :blk MCValue{ .register = reg };
1242 },
1243 .stack_offset => .{ .register = try self.copyToTmpRegister(slice_ptr_field_type, slice_mcv) },
12431244 else => return self.fail("TODO slice_elem_val when slice is {}", .{slice_mcv}),
12441245 };
1246 self.register_manager.freezeRegs(&.{base_mcv.register});
1247 defer self.register_manager.unfreezeRegs(&.{base_mcv.register});
12451248
12461249 if (elem_size <= 4) {
1247 const dst_reg = try self.register_manager.allocReg(inst, &.{ base_mcv.register, offset_mcv.register });
1250 const dst_reg = try self.register_manager.allocReg(inst, &.{});
1251 self.register_manager.freezeRegs(&.{dst_reg});
1252 defer self.register_manager.unfreezeRegs(&.{dst_reg});
1253
12481254 switch (elem_size) {
12491255 1, 4 => {
12501256 const tag: Mir.Inst.Tag = switch (elem_size) {
......@@ -1278,9 +1284,20 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12781284 break :result MCValue{ .register = dst_reg };
12791285 } else {
12801286 const dst_mcv = try self.allocRegOrMem(inst, false);
1281 const addr_reg = try self.register_manager.allocReg(null, &.{ base_mcv.register, offset_mcv.register });
1287
1288 const addr_reg = try self.register_manager.allocReg(null, &.{});
1289 self.register_manager.freezeRegs(&.{addr_reg});
1290 defer self.register_manager.unfreezeRegs(&.{addr_reg});
12821291
12831292 try self.genArmBinOpCode(addr_reg, base_mcv, offset_mcv, false, .add, .unsigned);
1293
1294 // I know we will unfreeze these registers at the end of
1295 // the scope of :result. However, at this point in time,
1296 // neither the base register nor the offset register
1297 // contains any valuable data anymore. In order to reduce
1298 // register pressure, unfreeze them prematurely
1299 self.register_manager.unfreezeRegs(&.{ base_mcv.register, offset_mcv.register });
1300
12841301 try self.load(dst_mcv, .{ .register = addr_reg }, slice_ptr_field_type);
12851302
12861303 break :result dst_mcv;
......@@ -1400,6 +1417,9 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14001417 return self.fail("TODO implement loading from MCValue.embedded_in_code", .{});
14011418 },
14021419 .register => |reg| {
1420 self.register_manager.freezeRegs(&.{reg});
1421 defer self.register_manager.unfreezeRegs(&.{reg});
1422
14031423 switch (dst_mcv) {
14041424 .dead => unreachable,
14051425 .undef => unreachable,
......@@ -1417,7 +1437,10 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14171437 },
14181438 .stack_offset => |off| {
14191439 if (elem_ty.abiSize(self.target.*) <= 4) {
1420 const tmp_reg = try self.register_manager.allocReg(null, &.{reg});
1440 const tmp_reg = try self.register_manager.allocReg(null, &.{});
1441 self.register_manager.freezeRegs(&.{tmp_reg});
1442 defer self.register_manager.unfreezeRegs(&.{tmp_reg});
1443
14211444 try self.load(.{ .register = tmp_reg }, ptr, ptr_ty);
14221445 try self.genSetStack(elem_ty, off, MCValue{ .register = tmp_reg });
14231446 } else if (elem_ty.abiSize(self.target.*) == 8) {
......@@ -1428,7 +1451,10 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14281451 // larger
14291452
14301453 const usize_ty = Type.initTag(.usize);
1431 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{reg});
1454 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{});
1455 self.register_manager.freezeRegs(&tmp_regs);
1456 defer self.register_manager.unfreezeRegs(&tmp_regs);
1457
14321458 _ = try self.addInst(.{
14331459 .tag = .ldr,
14341460 .data = .{ .rr_offset = .{
......@@ -1449,7 +1475,10 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14491475 try self.genSetStack(usize_ty, off + 4, MCValue{ .register = tmp_regs[1] });
14501476 } else {
14511477 // TODO optimize the register allocation
1452 const regs = try self.register_manager.allocRegs(4, .{ null, null, null, null }, &.{reg});
1478 const regs = try self.register_manager.allocRegs(4, .{ null, null, null, null }, &.{});
1479 self.register_manager.freezeRegs(&regs);
1480 defer self.register_manager.unfreezeRegs(&regs);
1481
14531482 const src_reg = reg;
14541483 const dst_reg = regs[0];
14551484 const len_reg = regs[1];
......@@ -1496,6 +1525,9 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
14961525 .stack_argument_offset,
14971526 => {
14981527 const reg = try self.register_manager.allocReg(null, &.{});
1528 self.register_manager.freezeRegs(&.{reg});
1529 defer self.register_manager.unfreezeRegs(&.{reg});
1530
14991531 try self.genSetReg(ptr_ty, reg, ptr);
15001532 try self.load(dst_mcv, .{ .register = reg }, ptr_ty);
15011533 },
......@@ -1550,6 +1582,9 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
15501582 return self.fail("TODO implement storing to MCValue.embedded_in_code", .{});
15511583 },
15521584 .register => |addr_reg| {
1585 self.register_manager.freezeRegs(&.{addr_reg});
1586 defer self.register_manager.unfreezeRegs(&.{addr_reg});
1587
15531588 switch (value) {
15541589 .register => |value_reg| {
15551590 _ = try self.addInst(.{
......@@ -1563,9 +1598,11 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
15631598 },
15641599 else => {
15651600 if (value_ty.abiSize(self.target.*) <= 4) {
1566 const tmp_reg = try self.register_manager.allocReg(null, &.{addr_reg});
1567 try self.genSetReg(value_ty, tmp_reg, value);
1601 const tmp_reg = try self.register_manager.allocReg(null, &.{});
1602 self.register_manager.freezeRegs(&.{tmp_reg});
1603 defer self.register_manager.unfreezeRegs(&.{tmp_reg});
15681604
1605 try self.genSetReg(value_ty, tmp_reg, value);
15691606 try self.store(ptr, .{ .register = tmp_reg }, ptr_ty, value_ty);
15701607 } else {
15711608 return self.fail("TODO implement memcpy", .{});
......@@ -1723,6 +1760,11 @@ fn genArmBinIntOp(
17231760 else => true,
17241761 };
17251762
1763 if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
1764 defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
1765 if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
1766 defer if (rhs_is_register) self.register_manager.unfreezeRegs(&.{rhs.register});
1767
17261768 // Destination must be a register
17271769 var dst_mcv: MCValue = undefined;
17281770 var lhs_mcv = lhs;
......@@ -1734,14 +1776,14 @@ fn genArmBinIntOp(
17341776 if (reuse_lhs) {
17351777 // Allocate 0 or 1 registers
17361778 if (!rhs_is_register and rhs_should_be_register) {
1737 rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_rhs).?, &.{lhs.register}) };
1779 rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_rhs).?, &.{}) };
17381780 branch.inst_table.putAssumeCapacity(Air.refToIndex(op_rhs).?, rhs_mcv);
17391781 }
17401782 dst_mcv = lhs;
17411783 } else if (reuse_rhs and can_swap_lhs_and_rhs) {
17421784 // Allocate 0 or 1 registers
17431785 if (!lhs_is_register and lhs_should_be_register) {
1744 lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_lhs).?, &.{rhs.register}) };
1786 lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_lhs).?, &.{}) };
17451787 branch.inst_table.putAssumeCapacity(Air.refToIndex(op_lhs).?, lhs_mcv);
17461788 }
17471789 dst_mcv = rhs;
......@@ -1751,14 +1793,14 @@ fn genArmBinIntOp(
17511793 // Allocate 1 or 2 registers
17521794 if (lhs_should_be_register and rhs_should_be_register) {
17531795 if (lhs_is_register and rhs_is_register) {
1754 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{ lhs.register, rhs.register }) };
1796 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17551797 } else if (lhs_is_register) {
17561798 // Move RHS to register
1757 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{lhs.register}) };
1799 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17581800 rhs_mcv = dst_mcv;
17591801 } else if (rhs_is_register) {
17601802 // Move LHS to register
1761 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{rhs.register}) };
1803 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17621804 lhs_mcv = dst_mcv;
17631805 } else {
17641806 // Move LHS and RHS to register
......@@ -1772,7 +1814,7 @@ fn genArmBinIntOp(
17721814 } else if (lhs_should_be_register) {
17731815 // RHS is immediate
17741816 if (lhs_is_register) {
1775 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{lhs.register}) };
1817 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17761818 } else {
17771819 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17781820 lhs_mcv = dst_mcv;
......@@ -1780,7 +1822,7 @@ fn genArmBinIntOp(
17801822 } else if (rhs_should_be_register and can_swap_lhs_and_rhs) {
17811823 // LHS is immediate
17821824 if (rhs_is_register) {
1783 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{rhs.register}) };
1825 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17841826 } else {
17851827 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
17861828 rhs_mcv = dst_mcv;
......@@ -1926,6 +1968,11 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
19261968 const reuse_lhs = lhs_is_register and self.reuseOperand(inst, op_lhs, 0, lhs);
19271969 const reuse_rhs = !reuse_lhs and rhs_is_register and self.reuseOperand(inst, op_rhs, 1, rhs);
19281970
1971 if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
1972 defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
1973 if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
1974 defer if (rhs_is_register) self.register_manager.unfreezeRegs(&.{rhs.register});
1975
19291976 // Destination must be a register
19301977 // LHS must be a register
19311978 // RHS must be a register
......@@ -1938,28 +1985,28 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
19381985 if (reuse_lhs) {
19391986 // Allocate 0 or 1 registers
19401987 if (!rhs_is_register) {
1941 rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_rhs).?, &.{lhs.register}) };
1988 rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_rhs).?, &.{}) };
19421989 branch.inst_table.putAssumeCapacity(Air.refToIndex(op_rhs).?, rhs_mcv);
19431990 }
19441991 dst_mcv = lhs;
19451992 } else if (reuse_rhs) {
19461993 // Allocate 0 or 1 registers
19471994 if (!lhs_is_register) {
1948 lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_lhs).?, &.{rhs.register}) };
1995 lhs_mcv = MCValue{ .register = try self.register_manager.allocReg(Air.refToIndex(op_lhs).?, &.{}) };
19491996 branch.inst_table.putAssumeCapacity(Air.refToIndex(op_lhs).?, lhs_mcv);
19501997 }
19511998 dst_mcv = rhs;
19521999 } else {
19532000 // Allocate 1 or 2 registers
19542001 if (lhs_is_register and rhs_is_register) {
1955 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{ lhs.register, rhs.register }) };
2002 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
19562003 } else if (lhs_is_register) {
19572004 // Move RHS to register
1958 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{lhs.register}) };
2005 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
19592006 rhs_mcv = dst_mcv;
19602007 } else if (rhs_is_register) {
19612008 // Move LHS to register
1962 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{rhs.register}) };
2009 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(inst, &.{}) };
19632010 lhs_mcv = dst_mcv;
19642011 } else {
19652012 // Move LHS and RHS to register
......@@ -1992,29 +2039,32 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
19922039}
19932040
19942041fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_index: Liveness.OperandInt, imm: u32) !MCValue {
1995 const mcv = try self.resolveInst(op);
2042 const lhs = try self.resolveInst(op);
19962043 const rhs = MCValue{ .immediate = imm };
19972044
1998 const lhs_is_register = mcv == .register;
1999 const reuse_lhs = lhs_is_register and self.reuseOperand(inst, op, op_index, mcv);
2045 const lhs_is_register = lhs == .register;
2046 const reuse_lhs = lhs_is_register and self.reuseOperand(inst, op, op_index, lhs);
2047
2048 if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
2049 defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
20002050
20012051 // Destination must be a register
20022052 // LHS must be a register
20032053 // RHS must be a register
20042054 var dst_mcv: MCValue = undefined;
2005 var lhs_mcv: MCValue = mcv;
2055 var lhs_mcv: MCValue = lhs;
20062056 var rhs_mcv: MCValue = rhs;
20072057
20082058 // Allocate registers for operands and/or destination
20092059 if (reuse_lhs) {
20102060 // Allocate 1 register
2011 rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(null, &.{mcv.register}) };
2012 dst_mcv = mcv;
2061 rhs_mcv = MCValue{ .register = try self.register_manager.allocReg(null, &.{}) };
2062 dst_mcv = lhs;
20132063 } else {
20142064 // Allocate 1 or 2 registers
20152065 if (lhs_is_register) {
20162066 // Move RHS to register
2017 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(null, &.{mcv.register}) };
2067 dst_mcv = MCValue{ .register = try self.register_manager.allocReg(null, &.{}) };
20182068 rhs_mcv = dst_mcv;
20192069 } else {
20202070 // Move LHS and RHS to register
......@@ -2027,7 +2077,7 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind
20272077
20282078 // Move the operands to the newly allocated registers
20292079 if (!lhs_is_register) {
2030 try self.genSetReg(self.air.typeOf(op), lhs_mcv.register, mcv);
2080 try self.genSetReg(self.air.typeOf(op), lhs_mcv.register, lhs);
20312081 }
20322082 try self.genSetReg(Type.initTag(.usize), rhs_mcv.register, rhs);
20332083
......@@ -2375,6 +2425,11 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
23752425 // lhs should always be a register
23762426 const rhs_should_be_register = try self.armOperandShouldBeRegister(rhs);
23772427
2428 if (lhs_is_register) self.register_manager.freezeRegs(&.{lhs.register});
2429 defer if (lhs_is_register) self.register_manager.unfreezeRegs(&.{lhs.register});
2430 if (rhs_is_register) self.register_manager.freezeRegs(&.{rhs.register});
2431 defer if (rhs_is_register) self.register_manager.unfreezeRegs(&.{rhs.register});
2432
23782433 var lhs_mcv = lhs;
23792434 var rhs_mcv = rhs;
23802435