Commit 70206af4829964420d7902488c66ba0edc37ba76 | zig

lib/std/Target.zig+375-151

...	...	@@ -72,6 +72,7 @@ pub const Os = struct {
72	72
73	73	// LLVM tags deliberately omitted:
74	74	// - bridgeos
	75	// - cheriotrtos
75	76	// - darwin
76	77	// - kfreebsd
77	78	// - nacl
...	...	@@ -732,6 +733,7 @@ pub const Os = struct {
732	733	};
733	734
734	735	pub const aarch64 = @import("Target/aarch64.zig");
	736	pub const alpha = @import("Target/generic.zig");
735	737	pub const amdgcn = @import("Target/amdgcn.zig");
736	738	pub const arc = @import("Target/arc.zig");
737	739	pub const arm = @import("Target/arm.zig");
...	...	@@ -739,10 +741,12 @@ pub const avr = @import("Target/avr.zig");
739	741	pub const bpf = @import("Target/bpf.zig");
740	742	pub const csky = @import("Target/csky.zig");
741	743	pub const hexagon = @import("Target/hexagon.zig");
	744	pub const hppa = @import("Target/generic.zig");
742	745	pub const kalimba = @import("Target/generic.zig");
743	746	pub const lanai = @import("Target/lanai.zig");
744	747	pub const loongarch = @import("Target/loongarch.zig");
745	748	pub const m68k = @import("Target/m68k.zig");
	749	pub const microblaze = @import("Target/generic.zig");
746	750	pub const mips = @import("Target/mips.zig");
747	751	pub const msp430 = @import("Target/msp430.zig");
748	752	pub const nvptx = @import("Target/nvptx.zig");
...	...	@@ -751,6 +755,7 @@ pub const powerpc = @import("Target/powerpc.zig");
751	755	pub const propeller = @import("Target/propeller.zig");
752	756	pub const riscv = @import("Target/riscv.zig");
753	757	pub const s390x = @import("Target/s390x.zig");
	758	pub const sh = @import("Target/generic.zig");
754	759	pub const sparc = @import("Target/sparc.zig");
755	760	pub const spirv = @import("Target/spirv.zig");
756	761	pub const ve = @import("Target/ve.zig");
...	...	@@ -800,14 +805,22 @@ pub const Abi = enum {
800	805	// - coreclr
801	806	// - domain
802	807	// - geometry
	808	// - gnueabit64
	809	// - gnueabihft64
803	810	// - gnuf64
	811	// - gnut64
804	812	// - hull
805	813	// - intersection
806	814	// - library
	815	// - llvm
807	816	// - mesh
808	817	// - miss
	818	// - mlibc
	819	// - mtia
	820	// - pauthtest
809	821	// - pixel
810	822	// - raygeneration
	823	// - rootsignature
811	824	// - vertex
812	825
813	826	pub fn default(arch: Cpu.Arch, os_tag: Os.Tag) Abi {
...	...	@@ -816,13 +829,16 @@ pub const Abi = enum {
816	829	// Soft float is usually a sane default for freestanding.
817	830	.arm,
818	831	.armeb,
819		.thumb,
820		.thumbeb,
821	832	.csky,
	833	.hppa,
822	834	.mips,
823	835	.mipsel,
824	836	.powerpc,
825	837	.powerpcle,
	838	.sh,
	839	.sheb,
	840	.thumb,
	841	.thumbeb,
826	842	=> .eabi,
827	843	else => .none,
828	844	},
...	...	@@ -837,20 +853,34 @@ pub const Abi = enum {
837	853	.linux => switch (arch) {
838	854	.arm,
839	855	.armeb,
840		.thumb,
841		.thumbeb,
842	856	.powerpc,
843	857	.powerpcle,
	858	.thumb,
	859	.thumbeb,
844	860	=> .musleabihf,
845		// Soft float tends to be more common for CSKY and MIPS.
846		.csky,
847		=> .gnueabi, // No musl support.
848	861	.mips,
849	862	.mipsel,
850	863	=> .musleabi,
851	864	.mips64,
852	865	.mips64el,
853	866	=> .muslabi64,
	867
	868	// No musl support.
	869	.arc,
	870	.arceb,
	871	=> .gnu,
	872	.csky,
	873	=> .gnueabi,
	874	.hppa,
	875	.sh,
	876	.sheb,
	877	=> .gnueabihf,
	878
	879	// No glibc or musl support.
	880	.xtensa,
	881	.xtensaeb,
	882	=> .none,
	883
854	884	else => .musl,
855	885	},
856	886	.rtems => switch (arch) {
...	...	@@ -1044,18 +1074,21 @@ pub const ObjectFormat = enum {
1044	1074
1045	1075	pub fn toElfMachine(target: *const Target) std.elf.EM {
1046	1076	return switch (target.cpu.arch) {
	1077	.aarch64, .aarch64_be => .AARCH64,
	1078	.alpha => .ALPHA,
1047	1079	.amdgcn => .AMDGPU,
1048		.arc => .ARC_COMPACT,
	1080	.arc, .arceb => .ARC_COMPACT,
1049	1081	.arm, .armeb, .thumb, .thumbeb => .ARM,
1050		.aarch64, .aarch64_be => .AARCH64,
1051	1082	.avr => .AVR,
1052		.bpfel, .bpfeb => .BPF,
	1083	.bpfeb, .bpfel => .BPF,
1053	1084	.csky => .CSKY,
1054	1085	.hexagon => .QDSP6,
	1086	.hppa, .hppa64 => .PARISC,
1055	1087	.kalimba => .CSR_KALIMBA,
1056	1088	.lanai => .LANAI,
1057	1089	.loongarch32, .loongarch64 => .LOONGARCH,
1058	1090	.m68k => .@"68K",
	1091	.microblaze, .microblazeel => .MICROBLAZE,
1059	1092	.mips, .mips64, .mipsel, .mips64el => .MIPS,
1060	1093	.msp430 => .MSP430,
1061	1094	.or1k => .OR1K,
...	...	@@ -1064,13 +1097,14 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1064	1097	.propeller => .PROPELLER,
1065	1098	.riscv32, .riscv32be, .riscv64, .riscv64be => .RISCV,
1066	1099	.s390x => .S390,
	1100	.sh, .sheb => .SH,
1067	1101	.sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
1068	1102	.sparc64 => .SPARCV9,
1069	1103	.ve => .VE,
1070	1104	.x86 => .@"386",
1071	1105	.x86_64 => .X86_64,
1072	1106	.xcore => .XCORE,
1073		.xtensa => .XTENSA,
	1107	.xtensa, .xtensaeb => .XTENSA,
1074	1108
1075	1109	.nvptx,
1076	1110	.nvptx64,
...	...	@@ -1084,54 +1118,63 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
1084	1118
1085	1119	pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
1086	1120	return switch (target.cpu.arch) {
	1121	.alpha => .ALPHA64,
1087	1122	.arm => .ARM,
1088	1123	.thumb => .ARMNT,
1089	1124	.aarch64 => .ARM64,
1090	1125	.loongarch32 => .LOONGARCH32,
1091	1126	.loongarch64 => .LOONGARCH64,
	1127	.mips => .R3000BE,
	1128	.mipsel => .R3000,
	1129	.mips64el => .R4000,
	1130	.powerpcle => .POWERPC,
1092	1131	.riscv32 => .RISCV32,
1093	1132	.riscv64 => .RISCV64,
	1133	.sh => .SH3,
1094	1134	.x86 => .I386,
1095	1135	.x86_64 => .AMD64,
1096	1136
	1137	.aarch64_be,
1097	1138	.amdgcn,
1098	1139	.arc,
	1140	.arceb,
1099	1141	.armeb,
1100		.thumbeb,
1101		.aarch64_be,
1102	1142	.avr,
1103		.bpfel,
1104	1143	.bpfeb,
	1144	.bpfel,
1105	1145	.csky,
1106	1146	.hexagon,
	1147	.hppa,
	1148	.hppa64,
1107	1149	.kalimba,
1108	1150	.lanai,
1109	1151	.m68k,
1110		.mips,
1111		.mipsel,
	1152	.microblaze,
	1153	.microblazeel,
1112	1154	.mips64,
1113		.mips64el,
1114	1155	.msp430,
1115		.or1k,
1116	1156	.nvptx,
1117	1157	.nvptx64,
	1158	.or1k,
1118	1159	.powerpc,
1119		.powerpcle,
1120	1160	.powerpc64,
1121	1161	.powerpc64le,
	1162	.propeller,
1122	1163	.riscv32be,
1123	1164	.riscv64be,
1124	1165	.s390x,
	1166	.sheb,
1125	1167	.sparc,
1126	1168	.sparc64,
1127	1169	.spirv32,
1128	1170	.spirv64,
	1171	.thumbeb,
1129	1172	.ve,
1130	1173	.wasm32,
1131	1174	.wasm64,
1132	1175	.xcore,
1133	1176	.xtensa,
1134		.propeller,
	1177	.xtensaeb,
1135	1178	=> .UNKNOWN,
1136	1179	};
1137	1180	}
...	...	@@ -1300,32 +1343,36 @@ pub const Cpu = struct {
1300	1343	};
1301	1344
1302	1345	pub const Arch = enum {
	1346	aarch64,
	1347	aarch64_be,
	1348	alpha,
1303	1349	amdgcn,
1304	1350	arc,
	1351	arceb,
1305	1352	arm,
1306	1353	armeb,
1307		thumb,
1308		thumbeb,
1309		aarch64,
1310		aarch64_be,
1311	1354	avr,
1312		bpfel,
1313	1355	bpfeb,
	1356	bpfel,
1314	1357	csky,
1315	1358	hexagon,
	1359	hppa,
	1360	hppa64,
1316	1361	kalimba,
1317	1362	lanai,
1318	1363	loongarch32,
1319	1364	loongarch64,
1320	1365	m68k,
	1366	microblaze,
	1367	microblazeel,
1321	1368	mips,
1322	1369	mipsel,
1323	1370	mips64,
1324	1371	mips64el,
1325	1372	msp430,
1326		or1k,
1327	1373	nvptx,
1328	1374	nvptx64,
	1375	or1k,
1329	1376	powerpc,
1330	1377	powerpcle,
1331	1378	powerpc64,
...	...	@@ -1336,10 +1383,14 @@ pub const Cpu = struct {
1336	1383	riscv64,
1337	1384	riscv64be,
1338	1385	s390x,
	1386	sh,
	1387	sheb,
1339	1388	sparc,
1340	1389	sparc64,
1341	1390	spirv32,
1342	1391	spirv64,
	1392	thumb,
	1393	thumbeb,
1343	1394	ve,
1344	1395	wasm32,
1345	1396	wasm64,
...	...	@@ -1347,14 +1398,13 @@ pub const Cpu = struct {
1347	1398	x86_64,
1348	1399	xcore,
1349	1400	xtensa,
	1401	xtensaeb,
1350	1402
1351	1403	// LLVM tags deliberately omitted:
1352	1404	// - aarch64_32
1353	1405	// - amdil
1354	1406	// - amdil64
1355	1407	// - dxil
1356		// - le32
1357		// - le64
1358	1408	// - r600
1359	1409	// - hsail
1360	1410	// - hsail64
...	...	@@ -1372,18 +1422,21 @@ pub const Cpu = struct {
1372	1422	/// For a given family tag, it is guaranteed that an `std.Target.<tag>` namespace exists
1373	1423	/// containing CPU model and feature data.
1374	1424	pub const Family = enum {
	1425	aarch64,
	1426	alpha,
1375	1427	amdgcn,
1376	1428	arc,
1377	1429	arm,
1378		aarch64,
1379	1430	avr,
1380	1431	bpf,
1381	1432	csky,
1382	1433	hexagon,
	1434	hppa,
1383	1435	kalimba,
1384	1436	lanai,
1385	1437	loongarch,
1386	1438	m68k,
	1439	microblaze,
1387	1440	mips,
1388	1441	msp430,
1389	1442	nvptx,
...	...	@@ -1392,6 +1445,7 @@ pub const Cpu = struct {
1392	1445	propeller,
1393	1446	riscv,
1394	1447	s390x,
	1448	sh,
1395	1449	sparc,
1396	1450	spirv,
1397	1451	ve,
...	...	@@ -1403,18 +1457,21 @@ pub const Cpu = struct {
1403	1457
1404	1458	pub inline fn family(arch: Arch) Family {
1405	1459	return switch (arch) {
	1460	.aarch64, .aarch64_be => .aarch64,
	1461	.alpha => .alpha,
1406	1462	.amdgcn => .amdgcn,
1407		.arc => .arc,
	1463	.arc, .arceb => .arc,
1408	1464	.arm, .armeb, .thumb, .thumbeb => .arm,
1409		.aarch64, .aarch64_be => .aarch64,
1410	1465	.avr => .avr,
1411		.bpfel, .bpfeb => .bpf,
	1466	.bpfeb, .bpfel => .bpf,
1412	1467	.csky => .csky,
1413	1468	.hexagon => .hexagon,
	1469	.hppa, .hppa64 => .hppa,
1414	1470	.kalimba => .kalimba,
1415	1471	.lanai => .lanai,
1416	1472	.loongarch32, .loongarch64 => .loongarch,
1417	1473	.m68k => .m68k,
	1474	.microblaze, .microblazeel => .microblaze,
1418	1475	.mips, .mipsel, .mips64, .mips64el => .mips,
1419	1476	.msp430 => .msp430,
1420	1477	.or1k => .or1k,
...	...	@@ -1423,13 +1480,14 @@ pub const Cpu = struct {
1423	1480	.propeller => .propeller,
1424	1481	.riscv32, .riscv32be, .riscv64, .riscv64be => .riscv,
1425	1482	.s390x => .s390x,
	1483	.sh, .sheb => .sh,
1426	1484	.sparc, .sparc64 => .sparc,
1427	1485	.spirv32, .spirv64 => .spirv,
1428	1486	.ve => .ve,
1429	1487	.wasm32, .wasm64 => .wasm,
1430	1488	.x86, .x86_64 => .x86,
1431	1489	.xcore => .xcore,
1432		.xtensa => .xtensa,
	1490	.xtensa, .xtensaeb => .xtensa,
1433	1491	};
1434	1492	}
1435	1493
...	...	@@ -1462,6 +1520,20 @@ pub const Cpu = struct {
1462	1520	};
1463	1521	}
1464	1522
	1523	pub inline fn isArc(arch: Arch) bool {
	1524	return switch (arch) {
	1525	.arc, .arceb => true,
	1526	else => false,
	1527	};
	1528	}
	1529
	1530	pub inline fn isHppa(arch: Arch) bool {
	1531	return switch (arch) {
	1532	.hppa, .hppa64 => true,
	1533	else => false,
	1534	};
	1535	}
	1536
1465	1537	pub inline fn isWasm(arch: Arch) bool {
1466	1538	return switch (arch) {
1467	1539	.wasm32, .wasm64 => true,
...	...	@@ -1494,6 +1566,13 @@ pub const Cpu = struct {
1494	1566	};
1495	1567	}
1496	1568
	1569	pub inline fn isMicroblaze(arch: Arch) bool {
	1570	return switch (arch) {
	1571	.microblaze, .microblazeel => true,
	1572	else => false,
	1573	};
	1574	}
	1575
1497	1576	pub inline fn isMIPS(arch: Arch) bool {
1498	1577	return arch.isMIPS32() or arch.isMIPS64();
1499	1578	}
...	...	@@ -1544,6 +1623,13 @@ pub const Cpu = struct {
1544	1623	};
1545	1624	}
1546	1625
	1626	pub inline fn isSh(arch: Arch) bool {
	1627	return switch (arch) {
	1628	.sh, .sheb => true,
	1629	else => false,
	1630	};
	1631	}
	1632
1547	1633	pub inline fn isBpf(arch: Arch) bool {
1548	1634	return switch (arch) {
1549	1635	.bpfel, .bpfeb => true,
...	...	@@ -1558,6 +1644,13 @@ pub const Cpu = struct {
1558	1644	};
1559	1645	}
1560	1646
	1647	pub inline fn isXtensa(arch: Arch) bool {
	1648	return switch (arch) {
	1649	.xtensa, .xtensaeb => true,
	1650	else => false,
	1651	};
	1652	}
	1653
1561	1654	pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
1562	1655	for (arch.allCpuModels()) \|cpu\| {
1563	1656	if (std.mem.eql(u8, cpu_name, cpu.name)) {
...	...	@@ -1569,44 +1662,46 @@ pub const Cpu = struct {
1569	1662
1570	1663	pub fn endian(arch: Arch) std.builtin.Endian {
1571	1664	return switch (arch) {
1572		.avr,
1573		.arm,
1574	1665	.aarch64,
1575		.amdgcn,
	1666	.alpha,
	1667	.arm,
	1668	.arc,
	1669	.avr,
1576	1670	.bpfel,
1577	1671	.csky,
1578		.xtensa,
1579	1672	.hexagon,
1580	1673	.kalimba,
	1674	.loongarch32,
	1675	.loongarch64,
	1676	.microblazeel,
1581	1677	.mipsel,
1582	1678	.mips64el,
1583	1679	.msp430,
1584		.nvptx,
1585		.nvptx64,
1586	1680	.powerpcle,
1587	1681	.powerpc64le,
	1682	.propeller,
1588	1683	.riscv32,
1589	1684	.riscv64,
1590		.x86,
1591		.x86_64,
	1685	.sh,
	1686	.thumb,
	1687	.ve,
1592	1688	.wasm32,
1593	1689	.wasm64,
	1690	.x86,
	1691	.x86_64,
1594	1692	.xcore,
1595		.thumb,
1596		.ve,
1597		// GPU bitness is opaque. For now, assume little endian.
1598		.spirv32,
1599		.spirv64,
1600		.loongarch32,
1601		.loongarch64,
1602		.arc,
1603		.propeller,
	1693	.xtensa,
1604	1694	=> .little,
1605	1695
1606		.armeb,
1607	1696	.aarch64_be,
	1697	.arceb,
	1698	.armeb,
1608	1699	.bpfeb,
	1700	.hppa,
	1701	.hppa64,
	1702	.lanai,
1609	1703	.m68k,
	1704	.microblaze,
1610	1705	.mips,
1611	1706	.mips64,
1612	1707	.or1k,
...	...	@@ -1614,12 +1709,21 @@ pub const Cpu = struct {
1614	1709	.powerpc64,
1615	1710	.riscv32be,
1616	1711	.riscv64be,
	1712	.s390x,
	1713	.sheb,
1617	1714	.thumbeb,
1618	1715	.sparc,
1619	1716	.sparc64,
1620		.lanai,
1621		.s390x,
	1717	.xtensaeb,
1622	1718	=> .big,
	1719
	1720	// GPU endianness is opaque. For now, assume little endian.
	1721	.amdgcn,
	1722	.nvptx,
	1723	.nvptx64,
	1724	.spirv32,
	1725	.spirv64,
	1726	=> .little,
1623	1727	};
1624	1728	}
1625	1729
...	...	@@ -1683,6 +1787,7 @@ pub const Cpu = struct {
1683	1787	=> unreachable,
1684	1788
1685	1789	.x86_64_sysv,
	1790	.x86_64_x32,
1686	1791	.x86_64_win,
1687	1792	.x86_64_regcall_v3_sysv,
1688	1793	.x86_64_regcall_v4_win,
...	...	@@ -1709,6 +1814,9 @@ pub const Cpu = struct {
1709	1814	.aarch64_vfabi_sve,
1710	1815	=> &.{ .aarch64, .aarch64_be },
1711	1816
	1817	.alpha_osf,
	1818	=> &.{.alpha},
	1819
1712	1820	.arm_aapcs,
1713	1821	.arm_aapcs_vfp,
1714	1822	.arm_interrupt,
...	...	@@ -1755,7 +1863,7 @@ pub const Cpu = struct {
1755	1863
1756	1864	.arc_sysv,
1757	1865	.arc_interrupt,
1758		=> &.{.arc},
	1866	=> &.{ .arc, .arceb },
1759	1867
1760	1868	.avr_gnu,
1761	1869	.avr_builtin,
...	...	@@ -1774,6 +1882,12 @@ pub const Cpu = struct {
1774	1882	.hexagon_sysv_hvx,
1775	1883	=> &.{.hexagon},
1776	1884
	1885	.hppa_elf,
	1886	=> &.{.hppa},
	1887
	1888	.hppa64_elf,
	1889	=> &.{.hppa64},
	1890
1777	1891	.lanai_sysv,
1778	1892	=> &.{.lanai},
1779	1893
...	...	@@ -1789,7 +1903,12 @@ pub const Cpu = struct {
1789	1903	.m68k_interrupt,
1790	1904	=> &.{.m68k},
1791	1905
	1906	.microblaze_std,
	1907	.microblaze_interrupt,
	1908	=> &.{ .microblaze, .microblazeel },
	1909
1792	1910	.msp430_eabi,
	1911	.msp430_interrupt,
1793	1912	=> &.{.msp430},
1794	1913
1795	1914	.or1k_sysv,
...	...	@@ -1802,6 +1921,11 @@ pub const Cpu = struct {
1802	1921	.s390x_sysv_vx,
1803	1922	=> &.{.s390x},
1804	1923
	1924	.sh_gnu,
	1925	.sh_renesas,
	1926	.sh_interrupt,
	1927	=> &.{ .sh, .sheb },
	1928
1805	1929	.ve_sysv,
1806	1930	=> &.{.ve},
1807	1931
...	...	@@ -1811,7 +1935,7 @@ pub const Cpu = struct {
1811	1935
1812	1936	.xtensa_call0,
1813	1937	.xtensa_windowed,
1814		=> &.{.xtensa},
	1938	=> &.{ .xtensa, .xtensaeb },
1815	1939
1816	1940	.amdgcn_device,
1817	1941	.amdgcn_kernel,
...	...	@@ -2104,6 +2228,21 @@ pub fn requiresLibC(target: *const Target) bool {
2104	2228	};
2105	2229	}
2106	2230
	2231	/// The places where a user can specify an address space attribute
	2232	pub const AddressSpaceContext = enum {
	2233	/// A function is specified to be placed in a certain address space.
	2234	function,
	2235	/// A (global) variable is specified to be placed in a certain address space. In contrast to
	2236	/// `.constant`, these values (and thus the address space they will be placed in) are required
	2237	/// to be mutable.
	2238	variable,
	2239	/// A (global) constant value is specified to be placed in a certain address space. In contrast
	2240	/// to `.variable`, values placed in this address space are not required to be mutable.
	2241	constant,
	2242	/// A pointer is ascripted to point into a certain address space.
	2243	pointer,
	2244	};
	2245
2107	2246	/// Returns whether this target supports `address_space`. If `context` is `null`, this
2108	2247	/// function simply answers the general question of whether the target has any concept
2109	2248	/// of `address_space`; if non-`null`, the function additionally checks whether
...	...	@@ -2111,7 +2250,7 @@ pub fn requiresLibC(target: *const Target) bool {
2111	2250	pub fn supportsAddressSpace(
2112	2251	target: Target,
2113	2252	address_space: std.builtin.AddressSpace,
2114		context: ?std.builtin.AddressSpace.Context,
	2253	context: ?AddressSpaceContext,
2115	2254	) bool {
2116	2255	const arch = target.cpu.arch;
2117	2256
...	...	@@ -2343,7 +2482,10 @@ pub const DynamicLinker = struct {
2343	2482
2344	2483	.aarch64,
2345	2484	.aarch64_be,
	2485	.hexagon,
2346	2486	.m68k,
	2487	.microblaze,
	2488	.microblazeel,
2347	2489	.powerpc64,
2348	2490	.powerpc64le,
2349	2491	.s390x,
...	...	@@ -2379,6 +2521,17 @@ pub const DynamicLinker = struct {
2379	2521	else => return none,
2380	2522	}}),
2381	2523
	2524	.sh,
	2525	.sheb,
	2526	=> \|arch\| initFmt("/lib/ld-musl-{t}{s}.so.1", .{
	2527	arch,
	2528	switch (abi) {
	2529	.musleabi => "-nofpu",
	2530	.musleabihf => "",
	2531	else => return none,
	2532	},
	2533	}),
	2534
2382	2535	.riscv32,
2383	2536	.riscv64,
2384	2537	=> \|arch\| if (abi == .musl) initFmt("/lib/ld-musl-{s}{s}.so.1", .{
...	...	@@ -2392,6 +2545,7 @@ pub const DynamicLinker = struct {
2392	2545	}) else none,
2393	2546
2394	2547	.x86 => if (abi == .musl) init("/lib/ld-musl-i386.so.1") else none,
	2548
2395	2549	.x86_64 => initFmt("/lib/ld-musl-{s}.so.1", .{switch (abi) {
2396	2550	.musl => "x86_64",
2397	2551	.muslx32 => "x32",
...	...	@@ -2402,9 +2556,10 @@ pub const DynamicLinker = struct {
2402	2556	}
2403	2557	else if (abi.isGnu())
2404	2558	switch (cpu.arch) {
2405		// TODO: `eb` architecture support.
2406	2559	// TODO: `700` ABI support.
2407		.arc => if (abi == .gnu) init("/lib/ld-linux-arc.so.2") else none,
	2560	.arc,
	2561	.arceb,
	2562	=> \|arch\| if (abi == .gnu) initFmt("/lib/ld-linux-{t}.so.2", .{arch}) else none,
2408	2563
2409	2564	.arm,
2410	2565	.armeb,
...	...	@@ -2434,7 +2589,13 @@ pub const DynamicLinker = struct {
2434	2589	else => return none,
2435	2590	}}),
2436	2591
2437		.m68k => if (abi == .gnu) init("/lib/ld.so.1") else none,
	2592	.hppa,
	2593	.m68k,
	2594	.microblaze,
	2595	.microblazeel,
	2596	.xtensa,
	2597	.xtensaeb,
	2598	=> if (abi == .gnu) init("/lib/ld.so.1") else none,
2438	2599
2439	2600	.mips,
2440	2601	.mipsel,
...	...	@@ -2464,6 +2625,7 @@ pub const DynamicLinker = struct {
2464	2625	=> init("/lib/ld.so.1"),
2465	2626	else => none,
2466	2627	},
	2628
2467	2629	.powerpc64,
2468	2630	.powerpc64le,
2469	2631	=> if (abi == .gnu) init("/lib64/ld64.so.2") else none,
...	...	@@ -2486,18 +2648,28 @@ pub const DynamicLinker = struct {
2486	2648
2487	2649	.s390x => if (abi == .gnu) init("/lib/ld64.so.1") else none,
2488	2650
2489		.sparc => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
	2651	.sh,
	2652	.sheb,
	2653	=> switch (abi) {
	2654	.gnueabi,
	2655	.gnueabihf,
	2656	=> init("/lib/ld-linux.so.2"),
	2657	else => none,
	2658	},
	2659
	2660	.alpha,
	2661	.sparc,
	2662	.x86,
	2663	=> if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
	2664
2490	2665	.sparc64 => if (abi == .gnu) init("/lib64/ld-linux.so.2") else none,
2491	2666
2492		.x86 => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
2493	2667	.x86_64 => switch (abi) {
2494	2668	.gnu => init("/lib64/ld-linux-x86-64.so.2"),
2495	2669	.gnux32 => init("/libx32/ld-linux-x32.so.2"),
2496	2670	else => none,
2497	2671	},
2498	2672
2499		.xtensa => if (abi == .gnu) init("/lib/ld.so.1") else none,
2500
2501	2673	else => none,
2502	2674	}
2503	2675	else
...	...	@@ -2664,52 +2836,61 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
2664	2836	=> 16,
2665	2837
2666	2838	.arc,
	2839	.arceb,
2667	2840	.arm,
2668	2841	.armeb,
2669	2842	.csky,
2670	2843	.hexagon,
	2844	.hppa,
	2845	.kalimba,
	2846	.lanai,
	2847	.loongarch32,
2671	2848	.m68k,
	2849	.microblaze,
	2850	.microblazeel,
2672	2851	.mips,
2673	2852	.mipsel,
	2853	.nvptx,
2674	2854	.or1k,
2675	2855	.powerpc,
2676	2856	.powerpcle,
	2857	.propeller,
2677	2858	.riscv32,
2678	2859	.riscv32be,
	2860	.sh,
	2861	.sheb,
	2862	.sparc,
	2863	.spirv32,
2679	2864	.thumb,
2680	2865	.thumbeb,
	2866	.wasm32,
2681	2867	.x86,
2682	2868	.xcore,
2683		.nvptx,
2684		.kalimba,
2685		.lanai,
2686		.wasm32,
2687		.sparc,
2688		.spirv32,
2689		.loongarch32,
2690	2869	.xtensa,
2691		.propeller,
	2870	.xtensaeb,
2692	2871	=> 32,
2693	2872
2694	2873	.aarch64,
2695	2874	.aarch64_be,
	2875	.alpha,
	2876	.amdgcn,
	2877	.bpfeb,
	2878	.bpfel,
	2879	.hppa64,
	2880	.loongarch64,
2696	2881	.mips64,
2697	2882	.mips64el,
	2883	.nvptx64,
2698	2884	.powerpc64,
2699	2885	.powerpc64le,
2700	2886	.riscv64,
2701	2887	.riscv64be,
2702		.x86_64,
2703		.nvptx64,
2704		.wasm64,
2705		.amdgcn,
2706		.bpfel,
2707		.bpfeb,
2708		.sparc64,
2709	2888	.s390x,
2710		.ve,
	2889	.sparc64,
2711	2890	.spirv64,
2712		.loongarch64,
	2891	.ve,
	2892	.wasm64,
	2893	.x86_64,
2713	2894	=> 64,
2714	2895	};
2715	2896	}
...	...	@@ -2727,17 +2908,20 @@ pub fn stackAlignment(target: *const Target) u16 {
2727	2908	=> return 4,
2728	2909	.arm,
2729	2910	.armeb,
2730		.thumb,
2731		.thumbeb,
	2911	.hppa,
2732	2912	.lanai,
2733	2913	.mips,
2734	2914	.mipsel,
2735	2915	.sparc,
	2916	.thumb,
	2917	.thumbeb,
2736	2918	=> return 8,
2737	2919	.aarch64,
2738	2920	.aarch64_be,
	2921	.alpha,
2739	2922	.bpfeb,
2740	2923	.bpfel,
	2924	.hppa64,
2741	2925	.loongarch32,
2742	2926	.loongarch64,
2743	2927	.mips64,
...	...	@@ -2765,6 +2949,24 @@ pub fn stackAlignment(target: *const Target) u16 {
2765	2949	return @divExact(target.ptrBitWidth(), 8);
2766	2950	}
2767	2951
	2952	pub const StackGrowth = enum {
	2953	down,
	2954	up,
	2955	};
	2956
	2957	pub fn stackGrowth(target: *const Target) StackGrowth {
	2958	// Strictly speaking, most architectures don't inherently define the stack growth direction; you
	2959	// could quite easily argue that it is in fact a property of the ABI. However, that's just not
	2960	// really how it plays out in the real world. And besides, we have no mechanism for indicating
	2961	// a different stack growth ABI, nor a compelling use case for creating such a mechanism.
	2962	return switch (target.cpu.arch) {
	2963	.hppa,
	2964	.hppa64,
	2965	=> .up,
	2966	else => .down,
	2967	};
	2968	}
	2969
2768	2970	/// Default signedness of `char` for the native C compiler for this target
2769	2971	/// Note that char signedness is implementation-defined and many compilers provide
2770	2972	/// an option to override the default signedness e.g. GCC's -funsigned-char / -fsigned-char
...	...	@@ -2772,13 +2974,12 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
2772	2974	if (target.os.tag.isDarwin() or target.os.tag == .windows or target.os.tag == .uefi) return .signed;
2773	2975
2774	2976	return switch (target.cpu.arch) {
2775		.arm,
2776		.armeb,
2777		.thumb,
2778		.thumbeb,
2779	2977	.aarch64,
2780	2978	.aarch64_be,
	2979	.arm,
	2980	.armeb,
2781	2981	.arc,
	2982	.arceb,
2782	2983	.csky,
2783	2984	.hexagon,
2784	2985	.msp430,
...	...	@@ -2791,8 +2992,11 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
2791	2992	.riscv32be,
2792	2993	.riscv64,
2793	2994	.riscv64be,
	2995	.thumb,
	2996	.thumbeb,
2794	2997	.xcore,
2795	2998	.xtensa,
	2999	.xtensaeb,
2796	3000	=> .unsigned,
2797	3001	else => .signed,
2798	3002	};
...	...	@@ -2903,6 +3107,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
2903	3107	else => return 128,
2904	3108	},
2905	3109
	3110	.alpha,
2906	3111	.riscv32,
2907	3112	.riscv32be,
2908	3113	.riscv64,
...	...	@@ -2946,18 +3151,6 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
2946	3151	.wasi,
2947	3152	.emscripten,
2948	3153	=> switch (target.cpu.arch) {
2949		.msp430 => switch (c_type) {
2950		.char => return 8,
2951		.short, .ushort, .int, .uint => return 16,
2952		.long, .ulong, .float => return 32,
2953		.longlong, .ulonglong, .double, .longdouble => return 64,
2954		},
2955		.avr => switch (c_type) {
2956		.char => return 8,
2957		.short, .ushort, .int, .uint => return 16,
2958		.long, .ulong, .float, .double, .longdouble => return 32,
2959		.longlong, .ulonglong => return 64,
2960		},
2961	3154	.mips64, .mips64el => switch (c_type) {
2962	3155	.char => return 8,
2963	3156	.short, .ushort => return 16,
...	...	@@ -3024,6 +3217,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
3024	3217	},
3025	3218	},
3026	3219
	3220	.alpha,
3027	3221	.riscv32,
3028	3222	.riscv32be,
3029	3223	.riscv64,
...	...	@@ -3213,35 +3407,44 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3213	3407	=> 2,
3214	3408
3215	3409	.arc,
	3410	.arceb,
3216	3411	.csky,
	3412	.kalimba,
	3413	.microblaze,
	3414	.microblazeel,
	3415	.or1k,
	3416	.propeller,
	3417	.sh,
	3418	.sheb,
3217	3419	.x86,
3218	3420	.xcore,
3219		.or1k,
3220		.kalimba,
3221	3421	.xtensa,
3222		.propeller,
	3422	.xtensaeb,
3223	3423	=> 4,
3224	3424
	3425	.amdgcn,
3225	3426	.arm,
3226	3427	.armeb,
3227		.thumb,
3228		.thumbeb,
3229		.amdgcn,
3230		.bpfel,
3231	3428	.bpfeb,
	3429	.bpfel,
3232	3430	.hexagon,
	3431	.hppa,
	3432	.lanai,
3233	3433	.m68k,
3234	3434	.mips,
3235	3435	.mipsel,
3236		.sparc,
3237		.lanai,
3238	3436	.nvptx,
3239	3437	.nvptx64,
3240	3438	.s390x,
	3439	.sparc,
	3440	.thumb,
	3441	.thumbeb,
3241	3442	=> 8,
3242	3443
3243	3444	.aarch64,
3244	3445	.aarch64_be,
	3446	.alpha,
	3447	.hppa64,
3245	3448	.loongarch32,
3246	3449	.loongarch64,
3247	3450	.mips64,
...	...	@@ -3257,10 +3460,10 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3257	3460	.sparc64,
3258	3461	.spirv32,
3259	3462	.spirv64,
3260		.x86_64,
3261	3463	.ve,
3262	3464	.wasm32,
3263	3465	.wasm64,
	3466	.x86_64,
3264	3467	=> 16,
3265	3468
3266	3469	.avr,
...	...	@@ -3272,7 +3475,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
3272	3475	pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3273	3476	// Overrides for unusual alignments
3274	3477	switch (target.cpu.arch) {
3275		.arc => switch (c_type) {
	3478	.arc, .arceb => switch (c_type) {
3276	3479	.longdouble => return 4,
3277	3480	else => {},
3278	3481	},
...	...	@@ -3310,36 +3513,45 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3310	3513	@as(u16, switch (target.cpu.arch) {
3311	3514	.msp430 => 2,
3312	3515
	3516	.arc,
	3517	.arceb,
3313	3518	.csky,
3314		.xcore,
3315		.or1k,
3316	3519	.kalimba,
3317		.xtensa,
	3520	.microblaze,
	3521	.microblazeel,
	3522	.or1k,
3318	3523	.propeller,
	3524	.sh,
	3525	.sheb,
	3526	.xcore,
	3527	.xtensa,
	3528	.xtensaeb,
3319	3529	=> 4,
3320	3530
3321		.arc,
	3531	.amdgcn,
3322	3532	.arm,
3323	3533	.armeb,
3324		.thumb,
3325		.thumbeb,
3326		.amdgcn,
3327		.bpfel,
3328	3534	.bpfeb,
	3535	.bpfel,
3329	3536	.hexagon,
3330		.x86,
	3537	.hppa,
	3538	.lanai,
3331	3539	.m68k,
3332	3540	.mips,
3333	3541	.mipsel,
3334		.sparc,
3335		.lanai,
3336	3542	.nvptx,
3337	3543	.nvptx64,
3338	3544	.s390x,
	3545	.sparc,
	3546	.thumb,
	3547	.thumbeb,
	3548	.x86,
3339	3549	=> 8,
3340	3550
3341	3551	.aarch64,
3342	3552	.aarch64_be,
	3553	.alpha,
	3554	.hppa64,
3343	3555	.loongarch32,
3344	3556	.loongarch64,
3345	3557	.mips64,
...	...	@@ -3355,10 +3567,10 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
3355	3567	.sparc64,
3356	3568	.spirv32,
3357	3569	.spirv64,
3358		.x86_64,
3359	3570	.ve,
3360	3571	.wasm32,
3361	3572	.wasm64,
	3573	.x86_64,
3362	3574	=> 16,
3363	3575
3364	3576	.avr,
...	...	@@ -3373,32 +3585,49 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3373	3585
3374	3586	.msp430 => 2,
3375	3587
3376		.xcore,
	3588	.arc,
	3589	.arceb,
	3590	.csky,
	3591	.kalimba,
	3592	.microblaze,
	3593	.microblazeel,
	3594	.or1k,
3377	3595	.propeller,
	3596	.sh,
	3597	.sheb,
	3598	.xcore,
3378	3599	=> 4,
3379	3600
3380		.amdgcn,
3381	3601	.arm,
3382	3602	.armeb,
3383		.thumb,
3384		.thumbeb,
3385		.lanai,
3386	3603	.hexagon,
	3604	.hppa,
	3605	.lanai,
	3606	.loongarch32,
	3607	.m68k,
3387	3608	.mips,
3388	3609	.mipsel,
3389		.or1k,
3390	3610	.powerpc,
3391	3611	.powerpcle,
3392	3612	.riscv32,
3393	3613	.riscv32be,
3394	3614	.s390x,
	3615	.sparc,
	3616	.thumb,
	3617	.thumbeb,
	3618	.x86,
	3619	.xtensa,
	3620	.xtensaeb,
3395	3621	=> 8,
3396	3622
3397		// Even LLVMABIAlignmentOfType(i128) agrees on these targets.
3398	3623	.aarch64,
3399	3624	.aarch64_be,
	3625	.alpha,
	3626	.amdgcn,
3400	3627	.bpfel,
3401	3628	.bpfeb,
	3629	.hppa64,
	3630	.loongarch64,
3402	3631	.mips64,
3403	3632	.mips64el,
3404	3633	.nvptx,
...	...	@@ -3407,26 +3636,13 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
3407	3636	.powerpc64le,
3408	3637	.riscv64,
3409	3638	.riscv64be,
3410		.sparc,
3411	3639	.sparc64,
3412		.wasm32,
3413		.wasm64,
3414		.x86,
3415		.x86_64,
3416		=> 16,
3417
3418		// Below this comment are unverified but based on the fact that C requires
3419		// int128_t to be 16 bytes aligned, it's a safe default.
3420		.arc,
3421		.csky,
3422		.kalimba,
3423		.loongarch32,
3424		.loongarch64,
3425		.m68k,
3426	3640	.spirv32,
3427	3641	.spirv64,
3428	3642	.ve,
3429		.xtensa,
	3643	.wasm32,
	3644	.wasm64,
	3645	.x86_64,
3430	3646	=> 16,
3431	3647	};
3432	3648	}
...	...	@@ -3435,24 +3651,28 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3435	3651	return switch (target.cpu.arch) {
3436	3652	.x86_64 => switch (target.os.tag) {
3437	3653	.windows, .uefi => .{ .x86_64_win = .{} },
3438		else => .{ .x86_64_sysv = .{} },
	3654	else => switch (target.abi) {
	3655	.gnuabin32, .muslabin32 => .{ .x86_64_x32 = .{} },
	3656	else => .{ .x86_64_sysv = .{} },
	3657	},
3439	3658	},
3440	3659	.x86 => switch (target.os.tag) {
3441	3660	.windows, .uefi => .{ .x86_win = .{} },
3442	3661	else => .{ .x86_sysv = .{} },
3443	3662	},
3444		.aarch64, .aarch64_be => if (target.os.tag.isDarwin()) cc: {
3445		break :cc .{ .aarch64_aapcs_darwin = .{} };
3446		} else switch (target.os.tag) {
	3663	.aarch64, .aarch64_be => if (target.os.tag.isDarwin())
	3664	.{ .aarch64_aapcs_darwin = .{} }
	3665	else switch (target.os.tag) {
3447	3666	.windows => .{ .aarch64_aapcs_win = .{} },
3448	3667	else => .{ .aarch64_aapcs = .{} },
3449	3668	},
	3669	.alpha => .{ .alpha_osf = .{} },
3450	3670	.arm, .armeb, .thumb, .thumbeb => switch (target.abi.float()) {
3451	3671	.soft => .{ .arm_aapcs = .{} },
3452	3672	.hard => .{ .arm_aapcs_vfp = .{} },
3453	3673	},
3454	3674	.mips64, .mips64el => switch (target.abi) {
3455		.gnuabin32 => .{ .mips64_n32 = .{} },
	3675	.gnuabin32, .muslabin32 => .{ .mips64_n32 = .{} },
3456	3676	else => .{ .mips64_n64 = .{} },
3457	3677	},
3458	3678	.mips, .mipsel => .{ .mips_o32 = .{} },
...	...	@@ -3470,11 +3690,13 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3470	3690	else => .{ .powerpc_sysv = .{} },
3471	3691	},
3472	3692	.wasm32, .wasm64 => .{ .wasm_mvp = .{} },
3473		.arc => .{ .arc_sysv = .{} },
	3693	.arc, .arceb => .{ .arc_sysv = .{} },
3474	3694	.avr => .avr_gnu,
3475	3695	.bpfel, .bpfeb => .{ .bpf_std = .{} },
3476	3696	.csky => .{ .csky_sysv = .{} },
3477	3697	.hexagon => .{ .hexagon_sysv = .{} },
	3698	.hppa => .{ .hppa_elf = .{} },
	3699	.hppa64 => .{ .hppa64_elf = .{} },
3478	3700	.kalimba => null,
3479	3701	.lanai => .{ .lanai_sysv = .{} },
3480	3702	.loongarch64 => .{ .loongarch64_lp64 = .{} },
...	...	@@ -3483,13 +3705,15 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
3483	3705	.{ .m68k_gnu = .{} }
3484	3706	else
3485	3707	.{ .m68k_sysv = .{} },
	3708	.microblaze, .microblazeel => .{ .microblaze_std = .{} },
3486	3709	.msp430 => .{ .msp430_eabi = .{} },
3487	3710	.or1k => .{ .or1k_sysv = .{} },
3488	3711	.propeller => .{ .propeller_sysv = .{} },
3489	3712	.s390x => .{ .s390x_sysv = .{} },
	3713	.sh, .sheb => .{ .sh_gnu = .{} },
3490	3714	.ve => .{ .ve_sysv = .{} },
3491	3715	.xcore => .{ .xcore_xs1 = .{} },
3492		.xtensa => .{ .xtensa_call0 = .{} },
	3716	.xtensa, .xtensaeb => .{ .xtensa_windowed = .{} },
3493	3717	.amdgcn => .{ .amdgcn_device = .{} },
3494	3718	.nvptx, .nvptx64 => .nvptx_device,
3495	3719	.spirv32, .spirv64 => .spirv_device,

lib/std/Thread.zig+70

...	...	@@ -1235,6 +1235,18 @@ const LinuxThreadImpl = struct {
1235	1235	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
1236	1236	[len] "r" (self.mapped.len),
1237	1237	: .{ .memory = true }),
	1238	.alpha => asm volatile (
	1239	\\ ldi $0, 73 # SYS_munmap
	1240	\\ mov %[ptr], $16
	1241	\\ mov %[len], $17
	1242	\\ callsys
	1243	\\ ldi $0, 1 # SYS_exit
	1244	\\ ldi $16, 0
	1245	\\ callsys
	1246	:
	1247	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
	1248	[len] "r" (self.mapped.len),
	1249	: .{ .memory = true }),
1238	1250	.hexagon => asm volatile (
1239	1251	\\ r6 = #215 // SYS_munmap
1240	1252	\\ r0 = %[ptr]
...	...	@@ -1247,6 +1259,42 @@ const LinuxThreadImpl = struct {
1247	1259	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
1248	1260	[len] "r" (self.mapped.len),
1249	1261	: .{ .memory = true }),
	1262	.hppa => asm volatile (
	1263	\\ ldi 91, %%r20 /* SYS_munmap */
	1264	\\ copy %[ptr], %%r26
	1265	\\ copy %[len], %%r25
	1266	\\ ble 0x100(%%sr2, %%r0)
	1267	\\ ldi 1, %%r20 /* SYS_exit */
	1268	\\ ldi 0, %%r26
	1269	\\ ble 0x100(%%sr2, %%r0)
	1270	:
	1271	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
	1272	[len] "r" (self.mapped.len),
	1273	: .{ .memory = true }),
	1274	.m68k => asm volatile (
	1275	\\ move.l #91, %%d0 // SYS_munmap
	1276	\\ move.l %[ptr], %%d1
	1277	\\ move.l %[len], %%d2
	1278	\\ trap #0
	1279	\\ move.l #1, %%d0 // SYS_exit
	1280	\\ move.l #0, %%d1
	1281	\\ trap #0
	1282	:
	1283	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
	1284	[len] "r" (self.mapped.len),
	1285	: .{ .memory = true }),
	1286	.microblaze, .microblazeel => asm volatile (
	1287	\\ ori r12, r0, 91 # SYS_munmap
	1288	\\ ori r5, %[ptr], 0
	1289	\\ ori r6, %[len], 0
	1290	\\ brki r14, 0x8
	1291	\\ ori r12, r0, 1 # SYS_exit
	1292	\\ or r5, r0, r0
	1293	\\ brki r14, 0x8
	1294	:
	1295	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
	1296	[len] "r" (self.mapped.len),
	1297	: .{ .memory = true }),
1250	1298	// We set `sp` to the address of the current function as a workaround for a Linux
1251	1299	// kernel bug that caused syscalls to return EFAULT if the stack pointer is invalid.
1252	1300	// The bug was introduced in 46e12c07b3b9603c60fc1d421ff18618241cb081 and fixed in
...	...	@@ -1335,6 +1383,28 @@ const LinuxThreadImpl = struct {
1335	1383	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
1336	1384	[len] "r" (self.mapped.len),
1337	1385	: .{ .memory = true }),
	1386	.sh, .sheb => asm volatile (
	1387	\\ mov #91, r3 ! SYS_munmap
	1388	\\ mov %[ptr], r4
	1389	\\ mov %[len], r5
	1390	\\ trapa #31
	1391	\\ or r0, r0
	1392	\\ or r0, r0
	1393	\\ or r0, r0
	1394	\\ or r0, r0
	1395	\\ or r0, r0
	1396	\\ mov #1, r3 ! SYS_exit
	1397	\\ mov #0, r4
	1398	\\ trapa #31
	1399	\\ or r0, r0
	1400	\\ or r0, r0
	1401	\\ or r0, r0
	1402	\\ or r0, r0
	1403	\\ or r0, r0
	1404	:
	1405	: [ptr] "r" (@intFromPtr(self.mapped.ptr)),
	1406	[len] "r" (self.mapped.len),
	1407	: .{ .memory = true }),
1338	1408	.sparc => asm volatile (
1339	1409	\\ # See sparc64 comments below.
1340	1410	\\ 1:

lib/std/atomic.zig+11

...	...	@@ -419,6 +419,7 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
419	419	.aarch64,
420	420	.aarch64_be,
421	421	.arc,
	422	.arceb,
422	423	.powerpc64,
423	424	.powerpc64le,
424	425	=> 128,
...	...	@@ -432,20 +433,29 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
432	433	// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
433	434	// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
434	435	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
	436	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/microblaze/include/asm/cache.h#L15
	437	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sh/include/cpu-sh4/cpu/cache.h#L10
435	438	.arm,
436	439	.armeb,
437	440	.thumb,
438	441	.thumbeb,
	442	.microblaze,
	443	.microblazeel,
439	444	.mips,
440	445	.mipsel,
441	446	.mips64,
442	447	.mips64el,
	448	.sh,
	449	.sheb,
443	450	.sparc,
444	451	.sparc64,
445	452	=> 32,
446	453
447	454	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/m68k/include/asm/cache.h#L10
448	455	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/openrisc/include/asm/cache.h#L24
	456	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/parisc/include/asm/cache.h#L16
	457	.hppa,
	458	.hppa64,
449	459	.m68k,
450	460	.or1k,
451	461	=> 16,
...	...	@@ -468,6 +478,7 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
468	478	// - https://github.com/golang/go/blob/19e923182e590ae6568c2c714f20f32512aeb3e3/src/internal/cpu/cpu_riscv64.go#L7
469	479	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/xtensa/variants/csp/include/variant/core.h#L209
470	480	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/csky/Kconfig#L183
	481	// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/alpha/include/asm/cache.h#L11
471	482	// - https://www.xmos.com/download/The-XMOS-XS3-Architecture.pdf
472	483	else => 64,
473	484	};

lib/std/builtin.zig+85-18

...	...	@@ -204,6 +204,7 @@ pub const CallingConvention = union(enum(u8)) {
204	204
205	205	// Calling conventions for the `x86_64` architecture.
206	206	x86_64_sysv: CommonOptions,
	207	x86_64_x32: CommonOptions,
207	208	x86_64_win: CommonOptions,
208	209	x86_64_regcall_v3_sysv: CommonOptions,
209	210	x86_64_regcall_v4_win: CommonOptions,
...	...	@@ -229,6 +230,9 @@ pub const CallingConvention = union(enum(u8)) {
229	230	aarch64_vfabi: CommonOptions,
230	231	aarch64_vfabi_sve: CommonOptions,
231	232
	233	/// The standard `alpha` calling convention.
	234	alpha_osf: CommonOptions,
	235
232	236	// Calling convetions for the `arm`, `armeb`, `thumb`, and `thumbeb` architectures.
233	237	/// ARM Architecture Procedure Call Standard
234	238	arm_aapcs: CommonOptions,
...	...	@@ -275,7 +279,7 @@ pub const CallingConvention = union(enum(u8)) {
275	279	/// The standard `wasm32` and `wasm64` calling convention, as specified in the WebAssembly Tool Conventions.
276	280	wasm_mvp: CommonOptions,
277	281
278		/// The standard `arc` calling convention.
	282	/// The standard `arc`/`arceb` calling convention.
279	283	arc_sysv: CommonOptions,
280	284	arc_interrupt: ArcInterruptOptions,
281	285
...	...	@@ -296,6 +300,12 @@ pub const CallingConvention = union(enum(u8)) {
296	300	hexagon_sysv: CommonOptions,
297	301	hexagon_sysv_hvx: CommonOptions,
298	302
	303	/// The standard `hppa` calling convention.
	304	hppa_elf: CommonOptions,
	305
	306	/// The standard `hppa64` calling convention.
	307	hppa64_elf: CommonOptions,
	308
299	309	/// The standard `lanai` calling convention.
300	310	lanai_sysv: CommonOptions,
301	311
...	...	@@ -311,8 +321,13 @@ pub const CallingConvention = union(enum(u8)) {
311	321	m68k_rtd: CommonOptions,
312	322	m68k_interrupt: CommonOptions,
313	323
	324	/// The standard `microblaze`/`microblazeel` calling convention.
	325	microblaze_std: CommonOptions,
	326	microblaze_interrupt: MicroblazeInterruptOptions,
	327
314	328	/// The standard `msp430` calling convention.
315	329	msp430_eabi: CommonOptions,
	330	msp430_interrupt: CommonOptions,
316	331
317	332	/// The standard `or1k` calling convention.
318	333	or1k_sysv: CommonOptions,
...	...	@@ -324,6 +339,11 @@ pub const CallingConvention = union(enum(u8)) {
324	339	s390x_sysv: CommonOptions,
325	340	s390x_sysv_vx: CommonOptions,
326	341
	342	// Calling conventions for the `sh`/`sheb` architecture.
	343	sh_gnu: CommonOptions,
	344	sh_renesas: CommonOptions,
	345	sh_interrupt: ShInterruptOptions,
	346
327	347	/// The standard `ve` calling convention.
328	348	ve_sysv: CommonOptions,
329	349
...	...	@@ -331,7 +351,7 @@ pub const CallingConvention = union(enum(u8)) {
331	351	xcore_xs1: CommonOptions,
332	352	xcore_xs2: CommonOptions,
333	353
334		// Calling conventions for the `xtensa` architecture.
	354	// Calling conventions for the `xtensa`/`xtensaeb` architecture.
335	355	xtensa_call0: CommonOptions,
336	356	xtensa_windowed: CommonOptions,
337	357
...	...	@@ -403,6 +423,25 @@ pub const CallingConvention = union(enum(u8)) {
403	423	};
404	424	};
405	425
	426	/// Options for the `microblaze_interrupt` calling convention.
	427	pub const MicroblazeInterruptOptions = struct {
	428	/// The boundary the stack is aligned to when the function is called.
	429	/// `null` means the default for this calling convention.
	430	incoming_stack_alignment: ?u64 = null,
	431	type: InterruptType = .regular,
	432
	433	pub const InterruptType = enum(u2) {
	434	/// User exception; return with `rtsd`.
	435	user,
	436	/// Regular interrupt; return with `rtid`.
	437	regular,
	438	/// Fast interrupt; return with `rtid`.
	439	fast,
	440	/// Software breakpoint; return with `rtbd`.
	441	breakpoint,
	442	};
	443	};
	444
406	445	/// Options for the `mips_interrupt` and `mips64_interrupt` calling conventions.
407	446	pub const MipsInterruptOptions = struct {
408	447	/// The boundary the stack is aligned to when the function is called.
...	...	@@ -438,6 +477,25 @@ pub const CallingConvention = union(enum(u8)) {
438	477	};
439	478	};
440	479
	480	/// Options for the `sh_interrupt` calling convention.
	481	pub const ShInterruptOptions = struct {
	482	/// The boundary the stack is aligned to when the function is called.
	483	/// `null` means the default for this calling convention.
	484	incoming_stack_alignment: ?u64 = null,
	485	save: SaveBehavior = .full,
	486
	487	pub const SaveBehavior = enum(u3) {
	488	/// Save only fpscr (if applicable).
	489	fpscr,
	490	/// Save only high-numbered registers, i.e. r0 through r7 are not saved.
	491	high,
	492	/// Save all registers normally.
	493	full,
	494	/// Save all registers using the CPU's fast register bank.
	495	bank,
	496	};
	497	};
	498
441	499	/// Returns the array of `std.Target.Cpu.Arch` to which this `CallingConvention` applies.
442	500	/// Asserts that `cc` is not `.auto`, `.@"async"`, `.naked`, or `.@"inline"`.
443	501	pub fn archs(cc: CallingConvention) []const std.Target.Cpu.Arch {
...	...	@@ -459,21 +517,6 @@ pub const CallingConvention = union(enum(u8)) {
459	517	/// This data structure is used by the Zig language code generation and
460	518	/// therefore must be kept in sync with the compiler implementation.
461	519	pub const AddressSpace = enum(u5) {
462		/// The places where a user can specify an address space attribute
463		pub const Context = enum {
464		/// A function is specified to be placed in a certain address space.
465		function,
466		/// A (global) variable is specified to be placed in a certain address space.
467		/// In contrast to .constant, these values (and thus the address space they will be
468		/// placed in) are required to be mutable.
469		variable,
470		/// A (global) constant value is specified to be placed in a certain address space.
471		/// In contrast to .variable, values placed in this address space are not required to be mutable.
472		constant,
473		/// A pointer is ascripted to point into a certain address space.
474		pointer,
475		};
476
477	520	// CPU address spaces.
478	521	generic,
479	522	gs,
...	...	@@ -858,6 +901,13 @@ pub const VaListAarch64 = extern struct {
858	901	__vr_offs: c_int,
859	902	};
860	903
	904	/// This data structure is used by the Zig language code generation and
	905	/// therefore must be kept in sync with the compiler implementation.
	906	pub const VaListAlpha = extern struct {
	907	__base: *anyopaque,
	908	__offset: c_int,
	909	};
	910
861	911	/// This data structure is used by the Zig language code generation and
862	912	/// therefore must be kept in sync with the compiler implementation.
863	913	pub const VaListArm = extern struct {
...	...	@@ -891,6 +941,16 @@ pub const VaListS390x = extern struct {
891	941	__overflow_area_pointer: *anyopaque,
892	942	};
893	943
	944	/// This data structure is used by the Zig language code generation and
	945	/// therefore must be kept in sync with the compiler implementation.
	946	pub const VaListSh = extern struct {
	947	__va_next_o: *anyopaque,
	948	__va_next_o_limit: *anyopaque,
	949	__va_next_fp: *anyopaque,
	950	__va_next_fp_limit: *anyopaque,
	951	__va_next_stack: *anyopaque,
	952	};
	953
894	954	/// This data structure is used by the Zig language code generation and
895	955	/// therefore must be kept in sync with the compiler implementation.
896	956	pub const VaListX86_64 = extern struct {
...	...	@@ -920,14 +980,19 @@ pub const VaList = switch (builtin.cpu.arch) {
920	980	.x86,
921	981	=> *u8,
922	982	.arc,
	983	.arceb,
923	984	.avr,
924	985	.bpfel,
925	986	.bpfeb,
926	987	.csky,
	988	.hppa,
	989	.hppa64,
927	990	.lanai,
928	991	.loongarch32,
929	992	.loongarch64,
930	993	.m68k,
	994	.microblaze,
	995	.microblazeel,
931	996	.mips,
932	997	.mipsel,
933	998	.mips64,
...	...	@@ -952,6 +1017,7 @@ pub const VaList = switch (builtin.cpu.arch) {
952	1017	.stage2_llvm => @compileError("disabled due to miscompilations"),
953	1018	},
954	1019	},
	1020	.alpha => VaListAlpha,
955	1021	.arm, .armeb, .thumb, .thumbeb => VaListArm,
956	1022	.hexagon => if (builtin.target.abi.isMusl()) VaListHexagon else *u8,
957	1023	.powerpc, .powerpcle => switch (builtin.os.tag) {
...	...	@@ -959,6 +1025,7 @@ pub const VaList = switch (builtin.cpu.arch) {
959	1025	else => VaListPowerPc,
960	1026	},
961	1027	.s390x => VaListS390x,
	1028	.sh, .sheb => VaListSh, // This is wrong for `sh_renesas`: https://github.com/ziglang/zig/issues/24692#issuecomment-3150779829
962	1029	.x86_64 => switch (builtin.os.tag) {
963	1030	.uefi, .windows => switch (builtin.zig_backend) {
964	1031	else => *u8,
...	...	@@ -966,7 +1033,7 @@ pub const VaList = switch (builtin.cpu.arch) {
966	1033	},
967	1034	else => VaListX86_64,
968	1035	},
969		.xtensa => VaListXtensa,
	1036	.xtensa, .xtensaeb => VaListXtensa,
970	1037	else => @compileError("VaList not supported for this target yet"),
971	1038	};
972	1039

lib/std/builtin/assembly.zig+317-2

...	...	@@ -779,7 +779,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
779	779	lr: bool = false,
780	780	sr: bool = false,
781	781	},
782		.xtensa => packed struct {
	782	.xtensa, .xtensaeb => packed struct {
783	783	/// Whether the inline assembly code may perform stores to memory
784	784	/// addresses other than those derived from input pointer provenance.
785	785	memory: bool = false,
...	...	@@ -1591,7 +1591,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
1591	1591	vr30: bool = false,
1592	1592	vr31: bool = false,
1593	1593	},
1594		.arc => packed struct {
	1594	.arc, .arceb => packed struct {
1595	1595	/// Whether the inline assembly code may perform stores to memory
1596	1596	/// addresses other than those derived from input pointer provenance.
1597	1597	memory: bool = false,
...	...	@@ -2197,6 +2197,321 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
2197	2197	msa_map: bool = false,
2198	2198	msa_unmap: bool = false,
2199	2199	},
	2200	.alpha => packed struct {
	2201	/// Whether the inline assembly code may perform stores to memory
	2202	/// addresses other than those derived from input pointer provenance.
	2203	memory: bool = false,
	2204
	2205	r0: bool = false,
	2206	r1: bool = false,
	2207	r2: bool = false,
	2208	r3: bool = false,
	2209	r4: bool = false,
	2210	r5: bool = false,
	2211	r6: bool = false,
	2212	r7: bool = false,
	2213	r8: bool = false,
	2214	r9: bool = false,
	2215	r10: bool = false,
	2216	r11: bool = false,
	2217	r12: bool = false,
	2218	r13: bool = false,
	2219	r14: bool = false,
	2220	r15: bool = false,
	2221	r16: bool = false,
	2222	r17: bool = false,
	2223	r18: bool = false,
	2224	r19: bool = false,
	2225	r20: bool = false,
	2226	r21: bool = false,
	2227	r22: bool = false,
	2228	r23: bool = false,
	2229	r24: bool = false,
	2230	r25: bool = false,
	2231	r26: bool = false,
	2232	r27: bool = false,
	2233	r28: bool = false,
	2234	r29: bool = false,
	2235	r30: bool = false,
	2236
	2237	f0: bool = false,
	2238	f1: bool = false,
	2239	f2: bool = false,
	2240	f3: bool = false,
	2241	f4: bool = false,
	2242	f5: bool = false,
	2243	f6: bool = false,
	2244	f7: bool = false,
	2245	f8: bool = false,
	2246	f9: bool = false,
	2247	f10: bool = false,
	2248	f11: bool = false,
	2249	f12: bool = false,
	2250	f13: bool = false,
	2251	f14: bool = false,
	2252	f15: bool = false,
	2253	f16: bool = false,
	2254	f17: bool = false,
	2255	f18: bool = false,
	2256	f19: bool = false,
	2257	f20: bool = false,
	2258	f21: bool = false,
	2259	f22: bool = false,
	2260	f23: bool = false,
	2261	f24: bool = false,
	2262	f25: bool = false,
	2263	f26: bool = false,
	2264	f27: bool = false,
	2265	f28: bool = false,
	2266	f29: bool = false,
	2267	f30: bool = false,
	2268	},
	2269	.hppa, .hppa64 => packed struct {
	2270	/// Whether the inline assembly code may perform stores to memory
	2271	/// addresses other than those derived from input pointer provenance.
	2272	memory: bool = false,
	2273
	2274	sar: bool = false,
	2275
	2276	r1: bool = false,
	2277	r2: bool = false,
	2278	r3: bool = false,
	2279	r4: bool = false,
	2280	r5: bool = false,
	2281	r6: bool = false,
	2282	r7: bool = false,
	2283	r8: bool = false,
	2284	r9: bool = false,
	2285	r10: bool = false,
	2286	r11: bool = false,
	2287	r12: bool = false,
	2288	r13: bool = false,
	2289	r14: bool = false,
	2290	r15: bool = false,
	2291	r16: bool = false,
	2292	r17: bool = false,
	2293	r18: bool = false,
	2294	r19: bool = false,
	2295	r20: bool = false,
	2296	r21: bool = false,
	2297	r22: bool = false,
	2298	r23: bool = false,
	2299	r24: bool = false,
	2300	r25: bool = false,
	2301	r26: bool = false,
	2302	r27: bool = false,
	2303	r28: bool = false,
	2304	r29: bool = false,
	2305	r30: bool = false,
	2306	r31: bool = false,
	2307
	2308	fr4: bool = false,
	2309	fr5: bool = false,
	2310	fr6: bool = false,
	2311	fr7: bool = false,
	2312	fr8: bool = false,
	2313	fr9: bool = false,
	2314	fr10: bool = false,
	2315	fr11: bool = false,
	2316	fr12: bool = false,
	2317	fr13: bool = false,
	2318	fr14: bool = false,
	2319	fr15: bool = false,
	2320	fr16: bool = false,
	2321	fr17: bool = false,
	2322	fr18: bool = false,
	2323	fr19: bool = false,
	2324	fr20: bool = false,
	2325	fr21: bool = false,
	2326	fr22: bool = false,
	2327	fr23: bool = false,
	2328	fr24: bool = false,
	2329	fr25: bool = false,
	2330	fr26: bool = false,
	2331	fr27: bool = false,
	2332	fr28: bool = false,
	2333	fr29: bool = false,
	2334	fr30: bool = false,
	2335	fr31: bool = false,
	2336
	2337	fr4r: bool = false,
	2338	fr5r: bool = false,
	2339	fr6r: bool = false,
	2340	fr7r: bool = false,
	2341	fr8r: bool = false,
	2342	fr9r: bool = false,
	2343	fr10r: bool = false,
	2344	fr11r: bool = false,
	2345	fr12r: bool = false,
	2346	fr13r: bool = false,
	2347	fr14r: bool = false,
	2348	fr15r: bool = false,
	2349	fr16r: bool = false,
	2350	fr17r: bool = false,
	2351	fr18r: bool = false,
	2352	fr19r: bool = false,
	2353	fr20r: bool = false,
	2354	fr21r: bool = false,
	2355	fr22r: bool = false,
	2356	fr23r: bool = false,
	2357	fr24r: bool = false,
	2358	fr25r: bool = false,
	2359	fr26r: bool = false,
	2360	fr27r: bool = false,
	2361	fr28r: bool = false,
	2362	fr29r: bool = false,
	2363	fr30r: bool = false,
	2364	fr31r: bool = false,
	2365	},
	2366	.microblaze, .microblazeel => packed struct {
	2367	/// Whether the inline assembly code may perform stores to memory
	2368	/// addresses other than those derived from input pointer provenance.
	2369	memory: bool = false,
	2370
	2371	rmsr: bool = false,
	2372
	2373	r1: bool = false,
	2374	r2: bool = false,
	2375	r3: bool = false,
	2376	r4: bool = false,
	2377	r5: bool = false,
	2378	r6: bool = false,
	2379	r7: bool = false,
	2380	r8: bool = false,
	2381	r9: bool = false,
	2382	r10: bool = false,
	2383	r11: bool = false,
	2384	r12: bool = false,
	2385	r13: bool = false,
	2386	r14: bool = false,
	2387	r15: bool = false,
	2388	r16: bool = false,
	2389	r17: bool = false,
	2390	r18: bool = false,
	2391	r19: bool = false,
	2392	r20: bool = false,
	2393	r21: bool = false,
	2394	r22: bool = false,
	2395	r23: bool = false,
	2396	r24: bool = false,
	2397	r25: bool = false,
	2398	r26: bool = false,
	2399	r27: bool = false,
	2400	r28: bool = false,
	2401	r29: bool = false,
	2402	r30: bool = false,
	2403	r31: bool = false,
	2404	},
	2405	.sh, .sheb => packed struct {
	2406	/// Whether the inline assembly code may perform stores to memory
	2407	/// addresses other than those derived from input pointer provenance.
	2408	memory: bool = false,
	2409
	2410	sr: bool = false,
	2411	gbr: bool = false,
	2412	pr: bool = false,
	2413
	2414	r0: bool = false,
	2415	r1: bool = false,
	2416	r2: bool = false,
	2417	r3: bool = false,
	2418	r4: bool = false,
	2419	r5: bool = false,
	2420	r6: bool = false,
	2421	r7: bool = false,
	2422	r8: bool = false,
	2423	r9: bool = false,
	2424	r10: bool = false,
	2425	r11: bool = false,
	2426	r12: bool = false,
	2427	r13: bool = false,
	2428	r14: bool = false,
	2429	r15: bool = false,
	2430
	2431	mach: bool = false,
	2432	macl: bool = false,
	2433
	2434	fr0: bool = false,
	2435	fr1: bool = false,
	2436	fr2: bool = false,
	2437	fr3: bool = false,
	2438	fr4: bool = false,
	2439	fr5: bool = false,
	2440	fr6: bool = false,
	2441	fr7: bool = false,
	2442	fr8: bool = false,
	2443	fr9: bool = false,
	2444	fr10: bool = false,
	2445	fr11: bool = false,
	2446	fr12: bool = false,
	2447	fr13: bool = false,
	2448	fr14: bool = false,
	2449	fr15: bool = false,
	2450
	2451	dr0: bool = false,
	2452	dr2: bool = false,
	2453	dr4: bool = false,
	2454	dr6: bool = false,
	2455	dr8: bool = false,
	2456	dr10: bool = false,
	2457	dr12: bool = false,
	2458	dr14: bool = false,
	2459
	2460	fv0: bool = false,
	2461	fv4: bool = false,
	2462	fv8: bool = false,
	2463	fv12: bool = false,
	2464
	2465	xf0: bool = false,
	2466	xf1: bool = false,
	2467	xf2: bool = false,
	2468	xf3: bool = false,
	2469	xf4: bool = false,
	2470	xf5: bool = false,
	2471	xf6: bool = false,
	2472	xf7: bool = false,
	2473	xf8: bool = false,
	2474	xf9: bool = false,
	2475	xf10: bool = false,
	2476	xf11: bool = false,
	2477	xf12: bool = false,
	2478	xf13: bool = false,
	2479	xf14: bool = false,
	2480	xf15: bool = false,
	2481
	2482	xd0: bool = false,
	2483	xd2: bool = false,
	2484	xd4: bool = false,
	2485	xd6: bool = false,
	2486	xd8: bool = false,
	2487	xd10: bool = false,
	2488	xd12: bool = false,
	2489	xd14: bool = false,
	2490
	2491	xmtrx: bool = false,
	2492
	2493	fpul: bool = false,
	2494	fpscr: bool = false,
	2495
	2496	ms: bool = false,
	2497	me: bool = false,
	2498
	2499	rs: bool = false,
	2500	re: bool = false,
	2501
	2502	a0: bool = false,
	2503	a0g: bool = false,
	2504	a1: bool = false,
	2505	a1g: bool = false,
	2506	m0: bool = false,
	2507	m1: bool = false,
	2508	x0: bool = false,
	2509	x1: bool = false,
	2510	y0: bool = false,
	2511	y1: bool = false,
	2512
	2513	dsr: bool = false,
	2514	},
2200	2515	else => packed struct {
2201	2516	/// Whether the inline assembly code may perform stores to memory
2202	2517	/// addresses other than those derived from input pointer provenance.

lib/std/debug.zig+22-3

...	...	@@ -872,13 +872,18 @@ const StackIterator = union(enum) {
872	872	};
873	873
874	874	const fp_usability: FpUsability = switch (builtin.target.cpu.arch) {
	875	.alpha,
875	876	.avr,
876	877	.csky,
	878	.microblaze,
	879	.microblazeel,
877	880	.mips,
878	881	.mipsel,
879	882	.mips64,
880	883	.mips64el,
881	884	.msp430,
	885	.sh,
	886	.sheb,
882	887	.xcore,
883	888	=> .useless,
884	889	.hexagon,
...	...	@@ -969,11 +974,15 @@ const StackIterator = union(enum) {
969	974	const ra_ptr: *const usize = @ptrFromInt(ra_addr);
970	975	const bp = applyOffset(bp_ptr.*, stack_bias) orelse return .end;
971	976
972		// The stack grows downards, so `bp > fp` should always hold. If it doesn't, this
973		// frame is invalid, so we'll treat it as though it we reached end of stack. The
	977	// If the stack grows downwards, `bp > fp` should always hold; conversely, if it
	978	// grows upwards, `bp < fp` should always hold. If that is not the case, this
	979	// frame is invalid, so we'll treat it as though we reached end of stack. The
974	980	// exception is address 0, which is a graceful end-of-stack signal, in which case
975	981	// this return address is valid and the next iteration will be the last.
976		if (bp != 0 and bp <= fp) return .end;
	982	if (bp != 0 and switch (comptime builtin.target.stackGrowth()) {
	983	.down => bp <= fp,
	984	.up => bp >= fp,
	985	}) return .end;
977	986
978	987	it.fp = bp;
979	988	const ra = stripInstructionPtrAuthCode(ra_ptr.*);
...	...	@@ -985,6 +994,11 @@ const StackIterator = union(enum) {
985	994
986	995	/// Offset of the saved base pointer (previous frame pointer) wrt the frame pointer.
987	996	const fp_to_bp_offset = off: {
	997	// On 32-bit PA-RISC, the base pointer is the final word of the frame marker.
	998	if (native_arch == .hppa) break :off -1 * @sizeOf(usize);
	999	// On 64-bit PA-RISC, the frame marker was shrunk significantly; now there's just the return
	1000	// address followed by the base pointer.
	1001	if (native_arch == .hppa64) break :off -1 * @sizeOf(usize);
988	1002	// On LoongArch and RISC-V, the frame pointer points to the top of the saved register area,
989	1003	// in which the base pointer is the first word.
990	1004	if (native_arch.isLoongArch() or native_arch.isRISCV()) break :off -2 * @sizeOf(usize);
...	...	@@ -999,6 +1013,11 @@ const StackIterator = union(enum) {
999	1013
1000	1014	/// Offset of the saved return address wrt the frame pointer.
1001	1015	const fp_to_ra_offset = off: {
	1016	// On 32-bit PA-RISC, the return address sits in the middle-ish of the frame marker.
	1017	if (native_arch == .hppa) break :off -5 * @sizeOf(usize);
	1018	// On 64-bit PA-RISC, the frame marker was shrunk significantly; now there's just the return
	1019	// address followed by the base pointer.
	1020	if (native_arch == .hppa64) break :off -2 * @sizeOf(usize);
1002	1021	// On LoongArch and RISC-V, the frame pointer points to the top of the saved register area,
1003	1022	// in which the return address is the second word.
1004	1023	if (native_arch.isLoongArch() or native_arch.isRISCV()) break :off -1 * @sizeOf(usize);

lib/std/debug/Dwarf.zig+3-3

...	...	@@ -1430,7 +1430,7 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
1430	1430	pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1431	1431	return switch (arch) {
1432	1432	.aarch64, .aarch64_be => 32,
1433		.arc => 160,
	1433	.arc, .arceb => 160,
1434	1434	.arm, .armeb, .thumb, .thumbeb => 15,
1435	1435	.csky => 64,
1436	1436	.hexagon => 76,
...	...	@@ -1453,7 +1453,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
1453	1453	pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
1454	1454	return switch (arch) {
1455	1455	.aarch64, .aarch64_be => 29,
1456		.arc => 27,
	1456	.arc, .arceb => 27,
1457	1457	.arm, .armeb, .thumb, .thumbeb => 11,
1458	1458	.csky => 14,
1459	1459	.hexagon => 30,
...	...	@@ -1476,7 +1476,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
1476	1476	pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
1477	1477	return switch (arch) {
1478	1478	.aarch64, .aarch64_be => 31,
1479		.arc => 28,
	1479	.arc, .arceb => 28,
1480	1480	.arm, .armeb, .thumb, .thumbeb => 13,
1481	1481	.csky => 14,
1482	1482	.hexagon => 29,

lib/std/debug/SelfInfo/Elf.zig+1-1

...	...	@@ -102,7 +102,7 @@ pub const can_unwind: bool = s: {
102	102	.x86,
103	103	.x86_64,
104	104	},
105		// Not supported yet: arm/armeb/thumb/thumbeb, xtensa
	105	// Not supported yet: arm/armeb/thumb/thumbeb, xtensa/xtensaeb
106	106	.linux => &.{
107	107	.aarch64,
108	108	.aarch64_be,

lib/std/debug/cpu_context.zig+104-4

...	...	@@ -5,7 +5,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
5	5	root.debug.CpuContext
6	6	else switch (native_arch) {
7	7	.aarch64, .aarch64_be => Aarch64,
8		.arc => Arc,
	8	.arc, .arceb => Arc,
9	9	.arm, .armeb, .thumb, .thumbeb => Arm,
10	10	.csky => Csky,
11	11	.hexagon => Hexagon,
...	...	@@ -36,7 +36,7 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
36	36	const uc: *const signal_ucontext_t = @ptrCast(@alignCast(ctx_ptr));
37	37
38	38	// Deal with some special cases first.
39		if (native_arch == .arc and native_os == .linux) {
	39	if (native_arch.isArc() and native_os == .linux) {
40	40	var native: Native = .{
41	41	.r = [_]u32{ uc.mcontext.r31, uc.mcontext.r30, 0, uc.mcontext.r28 } ++
42	42	uc.mcontext.r27_26 ++
...	...	@@ -1492,6 +1492,21 @@ const X86_64 = struct {
1492	1492	/// as unsigned everywhere even if that's not how they're declared in the C headers.
1493	1493	const signal_ucontext_t = switch (native_os) {
1494	1494	.linux => switch (native_arch) {
	1495	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/alpha/include/asm/ucontext.h
	1496	.alpha => extern struct {
	1497	_flags: u64,
	1498	_link: ?*signal_ucontext_t,
	1499	_osf_sigmask: u64,
	1500	_stack: std.os.linux.stack_t,
	1501	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/alpha/include/uapi/asm/sigcontext.h
	1502	mcontext: extern struct {
	1503	_onstack: i64,
	1504	_mask: i64,
	1505	pc: u64,
	1506	_ps: i64,
	1507	r: [32]u64,
	1508	},
	1509	},
1495	1510	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/arm64/include/uapi/asm/ucontext.h
1496	1511	.aarch64,
1497	1512	.aarch64_be,
...	...	@@ -1553,6 +1568,7 @@ const signal_ucontext_t = switch (native_os) {
1553	1568	},
1554	1569	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/include/uapi/asm-generic/ucontext.h
1555	1570	.arc,
	1571	.arceb,
1556	1572	.csky,
1557	1573	.hexagon,
1558	1574	.m68k,
...	...	@@ -1565,13 +1581,14 @@ const signal_ucontext_t = switch (native_os) {
1565	1581	.x86,
1566	1582	.x86_64,
1567	1583	.xtensa,
	1584	.xtensaeb,
1568	1585	=> extern struct {
1569	1586	_flags: usize,
1570	1587	_link: ?*signal_ucontext_t,
1571	1588	_stack: std.os.linux.stack_t,
1572	1589	mcontext: switch (native_arch) {
1573	1590	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/arc/include/uapi/asm/sigcontext.h
1574		.arc => extern struct {
	1591	.arc, .arceb => extern struct {
1575	1592	_pad1: u32,
1576	1593	_bta: u32,
1577	1594	_lp: extern struct {
...	...	@@ -1616,6 +1633,21 @@ const signal_ucontext_t = switch (native_os) {
1616	1633	_ugp: u32,
1617	1634	pc: u32,
1618	1635	},
	1636	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/parisc/include/uapi/asm/sigcontext.h
	1637	.hppa => extern struct {
	1638	_flags: u32,
	1639	_psw: u32,
	1640	r1_19: [19]u32,
	1641	r20: u32,
	1642	r21: u32,
	1643	r22: u32,
	1644	r23_29: [7]u32,
	1645	r30: u32,
	1646	r31: u32,
	1647	_fr: [32]f64,
	1648	_iasq: [2]u32,
	1649	iaoq: [2]u32,
	1650	},
1619	1651	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/m68k/include/asm/ucontext.h
1620	1652	.m68k => extern struct {
1621	1653	_version: i32,
...	...	@@ -1623,6 +1655,11 @@ const signal_ucontext_t = switch (native_os) {
1623	1655	a: [8]u32,
1624	1656	pc: u32,
1625	1657	},
	1658	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/microblaze/include/uapi/asm/sigcontext.h
	1659	.microblaze, .microblazeel => extern struct {
	1660	r: [32]u32,
	1661	pc: u32,
	1662	},
1626	1663	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/mips/include/uapi/asm/sigcontext.h
1627	1664	.mips, .mipsel => extern struct {
1628	1665	_regmask: u32,
...	...	@@ -1652,6 +1689,13 @@ const signal_ucontext_t = switch (native_os) {
1652	1689	},
1653	1690	r: [16]u64,
1654	1691	},
	1692	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/sh/include/uapi/asm/sigcontext.h
	1693	.sh, .sheb => extern struct {
	1694	_oldmask: u32,
	1695	r: [16]u32,
	1696	pc: u32,
	1697	pr: u32,
	1698	},
1655	1699	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/x86/include/uapi/asm/sigcontext.h
1656	1700	.x86 => extern struct {
1657	1701	_gs: u32,
...	...	@@ -1691,7 +1735,7 @@ const signal_ucontext_t = switch (native_os) {
1691	1735	rip: u64,
1692	1736	},
1693	1737	// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/xtensa/include/uapi/asm/sigcontext.h
1694		.xtensa => extern struct {
	1738	.xtensa, .xtensaeb => extern struct {
1695	1739	pc: u32,
1696	1740	_ps: u32,
1697	1741	_l: extern struct {
...	...	@@ -1948,6 +1992,7 @@ const signal_ucontext_t = switch (native_os) {
1948	1992	_err: i32,
1949	1993	eip: u32,
1950	1994	},
	1995	// https://github.com/illumos/illumos-gate/blob/d4ce137bba3bd16823db6374d9e9a643264ce245/usr/src/uts/intel/sys/mcontext.h
1951	1996	.x86_64 => extern struct {
1952	1997	r15: u64,
1953	1998	r14: u64,
...	...	@@ -1984,6 +2029,14 @@ const signal_ucontext_t = switch (native_os) {
1984	2029	x: [30]u64,
1985	2030	},
1986	2031	},
	2032	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/alpha/include/signal.h
	2033	.alpha => extern struct {
	2034	_cookie: i64,
	2035	_mask: i64,
	2036	pc: u64,
	2037	_ps: i64,
	2038	r: [32]u64,
	2039	},
1987	2040	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/arm/include/signal.h
1988	2041	.arm => extern struct {
1989	2042	_cookie: i32,
...	...	@@ -1995,6 +2048,22 @@ const signal_ucontext_t = switch (native_os) {
1995	2048	pc: u32,
1996	2049	},
1997	2050	},
	2051	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/hppa/include/signal.h
	2052	.hppa => extern struct {
	2053	_unused: u32,
	2054	_mask: i32,
	2055	_fp: u32,
	2056	iaoq: [2]u32,
	2057	_resv: [2]u32,
	2058	r22: u32,
	2059	r21: u32,
	2060	r30: u32,
	2061	r20: u32,
	2062	_sar: u32,
	2063	r1_19: [19]u32,
	2064	r23_29: [7]u32,
	2065	r31: u32,
	2066	},
1998	2067	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/mips64/include/signal.h
1999	2068	.mips64, .mips64el => extern struct {
2000	2069	_cookie: i64,
...	...	@@ -2034,6 +2103,18 @@ const signal_ucontext_t = switch (native_os) {
2034	2103	},
2035	2104	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/sparc64/include/signal.h
2036	2105	.sparc64 => @compileError("sparc64-openbsd ucontext_t missing"),
	2106	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/sh/include/signal.h
	2107	.sh, .sheb => extern struct {
	2108	pc: u32,
	2109	_sr: i32,
	2110	_gbr: i32,
	2111	_macl: i32,
	2112	_mach: i32,
	2113	pr: u32,
	2114	r13_0: [14]u32,
	2115	r15: u32,
	2116	r14: u32,
	2117	},
2037	2118	// https://github.com/openbsd/src/blob/42468faed8369d07ae49ae02dd71ec34f59b66cd/sys/arch/i386/include/signal.h
2038	2119	.x86 => extern struct {
2039	2120	mcontext: extern struct {
...	...	@@ -2100,6 +2181,12 @@ const signal_ucontext_t = switch (native_os) {
2100	2181	sp: u64,
2101	2182	pc: u64,
2102	2183	},
	2184	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/alpha/include/mcontext.h
	2185	.alpha => extern struct {
	2186	r: [32]u64,
	2187	pc: u64,
	2188	},
	2189	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/arm/include/mcontext.h
2103	2190	.arm, .armeb => extern struct {
2104	2191	r: [15]u32 align(8),
2105	2192	pc: u32,
...	...	@@ -2118,6 +2205,7 @@ const signal_ucontext_t = switch (native_os) {
2118	2205	_cause: i32,
2119	2206	pc: u32,
2120	2207	},
	2208	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/mips/include/mcontext.h
2121	2209	.mips64, .mips64el => @compileError("https://github.com/ziglang/zig/issues/23765#issuecomment-2880386178"),
2122	2210	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/powerpc/include/mcontext.h
2123	2211	.powerpc => extern struct {
...	...	@@ -2129,6 +2217,18 @@ const signal_ucontext_t = switch (native_os) {
2129	2217	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/sparc/include/mcontext.h
2130	2218	.sparc => @compileError("sparc-netbsd mcontext_t missing"),
2131	2219	.sparc64 => @compileError("sparc64-netbsd mcontext_t missing"),
	2220	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/sh3/include/mcontext.h
	2221	.sh, .sheb => extern struct {
	2222	_gbr: i32,
	2223	pc: u32,
	2224	_sr: i32,
	2225	_macl: i32,
	2226	_mach: i32,
	2227	pr: u32,
	2228	r14: u32,
	2229	r13_0: [14]u32,
	2230	r15: u32,
	2231	},
2132	2232	// https://github.com/NetBSD/src/blob/861008c62187bf7bc0aac4d81e52ed6eee4d0c74/sys/arch/i386/include/mcontext.h
2133	2233	.x86 => extern struct {
2134	2234	_gs: i32,

lib/std/heap.zig+22-4

...	...	@@ -739,8 +739,10 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
739	739	.x86, .x86_64 => 4 << 10,
740	740	.thumb, .thumbeb, .arm, .armeb => 4 << 10,
741	741	.aarch64, .aarch64_be => 4 << 10,
	742	.hppa => 4 << 10,
742	743	.mips, .mipsel, .mips64, .mips64el => 4 << 10,
743	744	.powerpc, .powerpc64, .powerpc64le, .powerpcle => 4 << 10,
	745	.sh, .sheb => 4 << 10,
744	746	.sparc => 4 << 10,
745	747	.sparc64 => 8 << 10,
746	748	.riscv32, .riscv64 => 4 << 10,
...	...	@@ -754,11 +756,14 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
754	756	},
755	757	.openbsd => switch (builtin.cpu.arch) {
756	758	// OpenBSD/sys/arch/*
	759	.alpha => 8 << 10,
	760	.hppa => 4 << 10,
757	761	.x86, .x86_64 => 4 << 10,
758	762	.thumb, .thumbeb, .arm, .armeb, .aarch64, .aarch64_be => 4 << 10,
759	763	.mips64, .mips64el => 4 << 10,
760	764	.powerpc, .powerpc64, .powerpc64le, .powerpcle => 4 << 10,
761	765	.riscv64 => 4 << 10,
	766	.sh, .sheb => 4 << 10,
762	767	.sparc64 => 8 << 10,
763	768	else => null,
764	769	},
...	...	@@ -824,22 +829,26 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
824	829	.emscripten => 64 << 10,
825	830	.linux => switch (builtin.cpu.arch) {
826	831	// Linux/arch/*/Kconfig
827		.arc => 4 << 10,
	832	.alpha => 8 << 10,
	833	.arc, .arceb => 4 << 10,
828	834	.thumb, .thumbeb, .arm, .armeb => 4 << 10,
829	835	.aarch64, .aarch64_be => 4 << 10,
830	836	.csky => 4 << 10,
831	837	.hexagon => 4 << 10,
	838	.hppa => 4 << 10,
832	839	.loongarch32, .loongarch64 => 4 << 10,
833	840	.m68k => 4 << 10,
	841	.microblaze, .microblazeel => 4 << 10,
834	842	.mips, .mipsel, .mips64, .mips64el => 4 << 10,
835	843	.or1k => 8 << 10,
836	844	.powerpc, .powerpc64, .powerpc64le, .powerpcle => 4 << 10,
837	845	.riscv32, .riscv64 => 4 << 10,
838	846	.s390x => 4 << 10,
	847	.sh, .sheb => 4 << 10,
839	848	.sparc => 4 << 10,
840	849	.sparc64 => 8 << 10,
841	850	.x86, .x86_64 => 4 << 10,
842		.xtensa => 4 << 10,
	851	.xtensa, .xtensaeb => 4 << 10,
843	852	else => null,
844	853	},
845	854	.freestanding, .other => switch (builtin.cpu.arch) {
...	...	@@ -888,8 +897,10 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
888	897	.x86, .x86_64 => 4 << 10,
889	898	.thumb, .thumbeb, .arm, .armeb => 4 << 10,
890	899	.aarch64, .aarch64_be => 64 << 10,
	900	.hppa => 4 << 10,
891	901	.mips, .mipsel, .mips64, .mips64el => 16 << 10,
892	902	.powerpc, .powerpc64, .powerpc64le, .powerpcle => 16 << 10,
	903	.sh, .sheb => 4 << 10,
893	904	.sparc => 8 << 10,
894	905	.sparc64 => 8 << 10,
895	906	.riscv32, .riscv64 => 4 << 10,
...	...	@@ -902,11 +913,14 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
902	913	},
903	914	.openbsd => switch (builtin.cpu.arch) {
904	915	// OpenBSD/sys/arch/*
	916	.alpha => 8 << 10,
	917	.hppa => 4 << 10,
905	918	.x86, .x86_64 => 4 << 10,
906	919	.thumb, .thumbeb, .arm, .armeb, .aarch64, .aarch64_be => 4 << 10,
907	920	.mips64, .mips64el => 16 << 10,
908	921	.powerpc, .powerpc64, .powerpc64le, .powerpcle => 4 << 10,
909	922	.riscv64 => 4 << 10,
	923	.sh, .sheb => 4 << 10,
910	924	.sparc64 => 8 << 10,
911	925	else => null,
912	926	},
...	...	@@ -972,22 +986,26 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
972	986	.emscripten => 64 << 10,
973	987	.linux => switch (builtin.cpu.arch) {
974	988	// Linux/arch/*/Kconfig
975		.arc => 16 << 10,
	989	.alpha => 8 << 10,
	990	.arc, .arceb => 16 << 10,
976	991	.thumb, .thumbeb, .arm, .armeb => 4 << 10,
977	992	.aarch64, .aarch64_be => 64 << 10,
978	993	.csky => 4 << 10,
979	994	.hexagon => 256 << 10,
	995	.hppa => 64 << 10,
980	996	.loongarch32, .loongarch64 => 64 << 10,
981	997	.m68k => 8 << 10,
	998	.microblaze, .microblazeel => 4 << 10,
982	999	.mips, .mipsel, .mips64, .mips64el => 64 << 10,
983	1000	.or1k => 8 << 10,
984	1001	.powerpc, .powerpc64, .powerpc64le, .powerpcle => 256 << 10,
985	1002	.riscv32, .riscv64 => 4 << 10,
986	1003	.s390x => 4 << 10,
	1004	.sh, .sheb => 64 << 10,
987	1005	.sparc => 4 << 10,
988	1006	.sparc64 => 8 << 10,
989	1007	.x86, .x86_64 => 4 << 10,
990		.xtensa => 4 << 10,
	1008	.xtensa, .xtensaeb => 4 << 10,
991	1009	else => null,
992	1010	},
993	1011	.freestanding => switch (builtin.cpu.arch) {

lib/std/os/linux.zig+8-3

...	...	@@ -116,7 +116,7 @@ pub const SECCOMP = @import("linux/seccomp.zig");
116	116
117	117	pub const syscalls = @import("linux/syscalls.zig");
118	118	pub const SYS = switch (native_arch) {
119		.arc => syscalls.Arc,
	119	.arc, .arceb => syscalls.Arc,
120	120	.aarch64, .aarch64_be => syscalls.Arm64,
121	121	.arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
122	122	.csky => syscalls.CSky,
...	...	@@ -141,7 +141,7 @@ pub const SYS = switch (native_arch) {
141	141	.gnux32, .muslx32 => syscalls.X32,
142	142	else => syscalls.X64,
143	143	},
144		.xtensa => syscalls.Xtensa,
	144	.xtensa, .xtensaeb => syscalls.Xtensa,
145	145	else => @compileError("The Zig Standard Library is missing syscall definitions for the target CPU architecture"),
146	146	};
147	147
...	...	@@ -3686,7 +3686,7 @@ pub const PROT = struct {
3686	3686	pub const EXEC = 0x4;
3687	3687	/// page may be used for atomic ops
3688	3688	pub const SEM = switch (native_arch) {
3689		.mips, .mipsel, .mips64, .mips64el, .xtensa => 0x10,
	3689	.mips, .mipsel, .mips64, .mips64el, .xtensa, .xtensaeb => 0x10,
3690	3690	else => 0x8,
3691	3691	};
3692	3692	/// mprotect flag: extend change to start of growsdown vma
...	...	@@ -6161,6 +6161,7 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
6161	6161
6162	6162	pub const MINSIGSTKSZ = switch (native_arch) {
6163	6163	.arc,
	6164	.arceb,
6164	6165	.arm,
6165	6166	.armeb,
6166	6167	.csky,
...	...	@@ -6181,6 +6182,7 @@ pub const MINSIGSTKSZ = switch (native_arch) {
6181	6182	.x86,
6182	6183	.x86_64,
6183	6184	.xtensa,
	6185	.xtensaeb,
6184	6186	=> 2048,
6185	6187	.loongarch64,
6186	6188	.sparc,
...	...	@@ -6196,6 +6198,7 @@ pub const MINSIGSTKSZ = switch (native_arch) {
6196	6198	};
6197	6199	pub const SIGSTKSZ = switch (native_arch) {
6198	6200	.arc,
	6201	.arceb,
6199	6202	.arm,
6200	6203	.armeb,
6201	6204	.csky,
...	...	@@ -6216,6 +6219,7 @@ pub const SIGSTKSZ = switch (native_arch) {
6216	6219	.x86,
6217	6220	.x86_64,
6218	6221	.xtensa,
	6222	.xtensaeb,
6219	6223	=> 8192,
6220	6224	.aarch64,
6221	6225	.aarch64_be,
...	...	@@ -9740,6 +9744,7 @@ pub const AUDIT = struct {
9740	9744	.armeb, .thumbeb => .ARMEB,
9741	9745	.aarch64 => .AARCH64,
9742	9746	.arc => .ARCV2,
	9747	.arceb => .ARCV2BE,
9743	9748	.csky => .CSKY,
9744	9749	.hexagon => .HEXAGON,
9745	9750	.loongarch32 => .LOONGARCH32,

lib/std/os/linux/tls.zig+47-7

...	...	@@ -46,7 +46,7 @@ const Variant = enum {
46	46	/// -------------------------------------^-------------
47	47	/// `-- The TP register points here.
48	48	///
49		/// The offset (which can be zero) is applied to the TP only; there is never physical gap
	49	/// The offset (which can be zero) is applied to the TP only; there is never a physical gap
50	50	/// between the ABI TCB and the TLS blocks. This implies that we only need to align the TP.
51	51	///
52	52	/// The first (and only) word in the ABI TCB points to the DTV.
...	...	@@ -63,12 +63,19 @@ const Variant = enum {
63	63	};
64	64
65	65	const current_variant: Variant = switch (native_arch) {
	66	.aarch64,
	67	.aarch64_be,
	68	.alpha,
66	69	.arc,
	70	.arceb,
67	71	.arm,
68	72	.armeb,
69		.aarch64,
70		.aarch64_be,
71	73	.csky,
	74	.hppa,
	75	.microblaze,
	76	.microblazeel,
	77	.sh,
	78	.sheb,
72	79	.thumb,
73	80	.thumbeb,
74	81	=> .I_original,
...	...	@@ -133,18 +140,22 @@ const current_dtv_offset = switch (native_arch) {
133	140	/// Per-thread storage for the ELF TLS ABI.
134	141	const AbiTcb = switch (current_variant) {
135	142	.I_original, .I_modified => switch (native_arch) {
136		// ARM EABI mandates enough space for two pointers: the first one points to the DTV as
137		// usual, while the second one is unspecified.
138	143	.aarch64,
139	144	.aarch64_be,
	145	.alpha,
140	146	.arm,
141	147	.armeb,
	148	.hppa,
	149	.microblaze,
	150	.microblazeel,
	151	.sh,
	152	.sheb,
142	153	.thumb,
143	154	.thumbeb,
144	155	=> extern struct {
145	156	/// This is offset by `current_dtv_offset`.
146	157	dtv: usize,
147		reserved: ?*anyopaque,
	158	_reserved: ?*anyopaque,
148	159	},
149	160	else => extern struct {
150	161	/// This is offset by `current_dtv_offset`.
...	...	@@ -243,7 +254,15 @@ pub fn setThreadPointer(addr: usize) void {
243	254	: [addr] "r" (addr),
244	255	);
245	256	},
246		.arc => {
	257	.alpha => {
	258	asm volatile (
	259	\\ lda a0, %[addr]
	260	\\ wruniq
	261	:
	262	: [addr] "r" (addr),
	263	);
	264	},
	265	.arc, .arceb => {
247	266	// We apparently need to both set r25 (TP) and inform the kernel...
248	267	asm volatile (
249	268	\\ mov r25, %[addr]
...	...	@@ -268,6 +287,13 @@ pub fn setThreadPointer(addr: usize) void {
268	287	: [addr] "r" (addr),
269	288	);
270	289	},
	290	.hppa => {
	291	asm volatile (
	292	\\ ble 0xe0(%%sr2, %%r0)
	293	:
	294	: [addr] "={r26}" (addr),
	295	: .{ .r29 = true });
	296	},
271	297	.loongarch32, .loongarch64 => {
272	298	asm volatile (
273	299	\\ move $tp, %[addr]
...	...	@@ -286,6 +312,13 @@ pub fn setThreadPointer(addr: usize) void {
286	312	const rc = @call(.always_inline, linux.syscall1, .{ .set_thread_area, addr });
287	313	assert(rc == 0);
288	314	},
	315	.microblaze, .microblazeel => {
	316	asm volatile (
	317	\\ ori r21, %[addr], 0
	318	:
	319	: [addr] "r" (addr),
	320	);
	321	},
289	322	.or1k => {
290	323	asm volatile (
291	324	\\ l.ori r10, %[addr], 0
...	...	@@ -317,6 +350,13 @@ pub fn setThreadPointer(addr: usize) void {
317	350	: [addr] "r" (addr),
318	351	: .{ .r0 = true });
319	352	},
	353	.sh, .sheb => {
	354	asm volatile (
	355	\\ ldc gbr, %[addr]
	356	:
	357	: [addr] "r" (addr),
	358	);
	359	},
320	360	.sparc, .sparc64 => {
321	361	asm volatile (
322	362	\\ mov %[addr], %%g7

lib/std/pie.zig+35-2

...	...	@@ -3,6 +3,7 @@ const builtin = @import("builtin");
3	3	const elf = std.elf;
4	4	const assert = std.debug.assert;
5	5
	6	const R_ALPHA_RELATIVE = 27;
6	7	const R_AMD64_RELATIVE = 8;
7	8	const R_386_RELATIVE = 8;
8	9	const R_ARC_RELATIVE = 56;
...	...	@@ -12,28 +13,33 @@ const R_CSKY_RELATIVE = 9;
12	13	const R_HEXAGON_RELATIVE = 35;
13	14	const R_LARCH_RELATIVE = 3;
14	15	const R_68K_RELATIVE = 22;
	16	const R_MICROBLAZE_REL = 16;
15	17	const R_MIPS_RELATIVE = 128;
16	18	const R_OR1K_RELATIVE = 21;
17	19	const R_PPC_RELATIVE = 22;
18	20	const R_RISCV_RELATIVE = 3;
19	21	const R_390_RELATIVE = 12;
	22	const R_SH_RELATIVE = 165;
20	23	const R_SPARC_RELATIVE = 22;
21	24
22	25	const R_RELATIVE = switch (builtin.cpu.arch) {
23	26	.x86 => R_386_RELATIVE,
24	27	.x86_64 => R_AMD64_RELATIVE,
25		.arc => R_ARC_RELATIVE,
	28	.arc, .arceb => R_ARC_RELATIVE,
26	29	.arm, .armeb, .thumb, .thumbeb => R_ARM_RELATIVE,
27	30	.aarch64, .aarch64_be => R_AARCH64_RELATIVE,
	31	.alpha => R_ALPHA_RELATIVE,
28	32	.csky => R_CSKY_RELATIVE,
29	33	.hexagon => R_HEXAGON_RELATIVE,
30	34	.loongarch32, .loongarch64 => R_LARCH_RELATIVE,
31	35	.m68k => R_68K_RELATIVE,
	36	.microblaze, .microblazeel => R_MICROBLAZE_REL,
32	37	.mips, .mipsel, .mips64, .mips64el => R_MIPS_RELATIVE,
33	38	.or1k => R_OR1K_RELATIVE,
34	39	.powerpc, .powerpcle, .powerpc64, .powerpc64le => R_PPC_RELATIVE,
35	40	.riscv32, .riscv32be, .riscv64, .riscv64be => R_RISCV_RELATIVE,
36	41	.s390x => R_390_RELATIVE,
	42	.sh, .sheb => R_SH_RELATIVE,
37	43	.sparc, .sparc64 => R_SPARC_RELATIVE,
38	44	else => @compileError("Missing R_RELATIVE definition for this target"),
39	45	};
...	...	@@ -58,7 +64,7 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
58	64	\\ lea _DYNAMIC(%%rip), %[ret]
59	65	: [ret] "=r" (-> [*]const elf.Dyn),
60	66	),
61		.arc => asm volatile (
	67	.arc, .arceb => asm volatile (
62	68	\\ .weak _DYNAMIC
63	69	\\ .hidden _DYNAMIC
64	70	\\ add %[ret], pcl, _DYNAMIC@pcl
...	...	@@ -83,6 +89,15 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
83	89	\\ add %[ret], %[ret], #:lo12:_DYNAMIC
84	90	: [ret] "=r" (-> [*]const elf.Dyn),
85	91	),
	92	// The compiler is not required to load the GP register, so do it ourselves.
	93	.alpha => asm volatile (
	94	\\ br $29, 1f
	95	\\1:
	96	\\ ldgp $29, 0($29)
	97	\\ ldq %[ret], -0x8000($29)
	98	: [ret] "=r" (-> [*]const elf.Dyn),
	99	:
	100	: .{ .r26 = true }),
86	101	// The CSKY ABI requires the gb register to point to the GOT. Additionally, the first
87	102	// entry in the GOT is defined to hold the address of _DYNAMIC.
88	103	.csky => asm volatile (
...	...	@@ -118,6 +133,10 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
118	133	\\ lea (%[ret], %%pc), %[ret]
119	134	: [ret] "=r" (-> [*]const elf.Dyn),
120	135	),
	136	.microblaze, .microblazeel => asm volatile (
	137	\\ lwi %[ret], r20, 0
	138	: [ret] "=r" (-> [*]const elf.Dyn),
	139	),
121	140	.mips, .mipsel => asm volatile (
122	141	\\ .weak _DYNAMIC
123	142	\\ .hidden _DYNAMIC
...	...	@@ -206,6 +225,20 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
206	225	\\ 2:
207	226	: [ret] "=a" (-> [*]const elf.Dyn),
208	227	),
	228	.sh, .sheb => asm volatile (
	229	\\ .weak _DYNAMIC
	230	\\ .hidden _DYNAMIC
	231	\\ mova 1f, r0
	232	\\ mov.l 1f, %[ret]
	233	\\ add r0, %[ret]
	234	\\ bra 2f
	235	\\1:
	236	\\ .balign 4
	237	\\ .long DYNAMIC - .
	238	\\2:
	239	: [ret] "=r" (-> [*]const elf.Dyn),
	240	:
	241	: .{ .r0 = true }),
209	242	// The compiler does not necessarily have any obligation to load the `l7` register (pointing
210	243	// to the GOT), so do it ourselves just in case.
211	244	.sparc, .sparc64 => asm volatile (

lib/std/start.zig+43-3

...	...	@@ -195,13 +195,15 @@ fn _start() callconv(.naked) noreturn {
195	195	// This is the first userspace frame. Prevent DWARF-based unwinders from unwinding further. We
196	196	// prevent FP-based unwinders from unwinding further by zeroing the register below.
197	197	if (builtin.unwind_tables != .none or !builtin.strip_debug_info) asm volatile (switch (native_arch) {
198		.arc => ".cfi_undefined blink",
199		.arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891
200	198	.aarch64, .aarch64_be => ".cfi_undefined lr",
	199	.alpha => ".cfi_undefined $26",
	200	.arc, .arceb => ".cfi_undefined blink",
	201	.arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891
201	202	.csky => ".cfi_undefined lr",
202	203	.hexagon => ".cfi_undefined r31",
203	204	.loongarch32, .loongarch64 => ".cfi_undefined 1",
204	205	.m68k => ".cfi_undefined %%pc",
	206	.microblaze, .microblazeel => ".cfi_undefined r15",
205	207	.mips, .mipsel, .mips64, .mips64el => ".cfi_undefined $ra",
206	208	.or1k => ".cfi_undefined r9",
207	209	.powerpc, .powerpcle, .powerpc64, .powerpc64le => ".cfi_undefined lr",
...	...	@@ -210,6 +212,7 @@ fn _start() callconv(.naked) noreturn {
210	212	else
211	213	".cfi_undefined ra",
212	214	.s390x => ".cfi_undefined %%r14",
	215	.sh, .sheb => ".cfi_undefined pr",
213	216	.sparc, .sparc64 => ".cfi_undefined %%i7",
214	217	.x86 => ".cfi_undefined %%eip",
215	218	.x86_64 => ".cfi_undefined %%rip",
...	...	@@ -253,7 +256,19 @@ fn _start() callconv(.naked) noreturn {
253	256	\\ and sp, x0, #-16
254	257	\\ b %[posixCallMainAndExit]
255	258	,
256		.arc =>
	259	.alpha =>
	260	// $15 = FP, $26 = LR, $29 = GP, $30 = SP
	261	\\ br $29, 1f
	262	\\1:
	263	\\ ldgp $29, 0($29)
	264	\\ mov 0, $15
	265	\\ mov 0, $26
	266	\\ mov $30, $16
	267	\\ ldi $1, -16
	268	\\ and $30, $30, $1
	269	\\ jsr $26, %[posixCallMainAndExit]
	270	,
	271	.arc, .arceb =>
257	272	// ARC v1 and v2 had a very low stack alignment requirement of 4; v3 increased it to 16.
258	273	\\ mov fp, 0
259	274	\\ mov blink, 0
...	...	@@ -333,6 +348,16 @@ fn _start() callconv(.naked) noreturn {
333	348	\\ lea %[posixCallMainAndExit] - . - 8, %%a0
334	349	\\ jsr (%%pc, %%a0)
335	350	,
	351	.microblaze, .microblazeel =>
	352	// r1 = SP, r15 = LR, r19 = FP, r20 = GP
	353	\\ ori r15, r0, r0
	354	\\ ori r19, r0, r0
	355	\\ mfs r20, rpc
	356	\\ addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
	357	\\ ori r5, r1, r0
	358	\\ andi r1, r1, -4
	359	\\ brlid r15, %[posixCallMainAndExit]
	360	,
336	361	.mips, .mipsel =>
337	362	\\ move $fp, $zero
338	363	\\ bal 1f
...	...	@@ -431,6 +456,21 @@ fn _start() callconv(.naked) noreturn {
431	456	\\ stg %%r0, 0(%%r15)
432	457	\\ jg %[posixCallMainAndExit]
433	458	,
	459	.sh, .sheb =>
	460	// r14 = FP, r15 = SP, pr = LR
	461	\\ mov #0, r0
	462	\\ lds r0, pr
	463	\\ mov r0, r14
	464	\\ mov r15, r4
	465	\\ mov #-4, r0
	466	\\ and r0, r15
	467	\\ mov.l 2f, r1
	468	\\1:
	469	\\ bsrf r1
	470	\\2:
	471	\\ .balign 4
	472	\\ .long %[posixCallMainAndExit]@PCREL - (1b + 4 - .)
	473	,
434	474	.sparc =>
435	475	// argc is stored after a register window (16 registers * 4 bytes).
436	476	// i7 = LR

lib/std/zig/system.zig+23-11

...	...	@@ -100,10 +100,14 @@ pub fn getExternalExecutor(
100	100	else => bad_result,
101	101	},
102	102	inline .aarch64_be,
	103	.alpha,
103	104	.armeb,
104	105	.hexagon,
	106	.hppa,
105	107	.loongarch64,
106	108	.m68k,
	109	.microblaze,
	110	.microblazeel,
107	111	.mips,
108	112	.mipsel,
109	113	.mips64,
...	...	@@ -114,26 +118,34 @@ pub fn getExternalExecutor(
114	118	.powerpc64le,
115	119	.riscv32,
116	120	.s390x,
	121	.sh,
	122	.sheb,
117	123	.sparc,
118	124	.sparc64,
119	125	.thumb,
120	126	.thumbeb,
121	127	.xtensa,
	128	.xtensaeb,
122	129	=> \|t\| switch (candidate.os.tag) {
123	130	.linux,
124		=> .{ .qemu = switch (t) {
125		.powerpc => "qemu-ppc",
126		.powerpc64 => "qemu-ppc64",
127		.powerpc64le => "qemu-ppc64le",
128		.mips64, .mips64el => switch (candidate.abi) {
129		.gnuabin32, .muslabin32 => if (t == .mips64el) "qemu-mipsn32el" else "qemu-mipsn32",
	131	=> .{
	132	.qemu = switch (t) {
	133	.powerpc => "qemu-ppc",
	134	.powerpc64 => "qemu-ppc64",
	135	.powerpc64le => "qemu-ppc64le",
	136	.mips64, .mips64el => switch (candidate.abi) {
	137	.gnuabin32, .muslabin32 => if (t == .mips64el) "qemu-mipsn32el" else "qemu-mipsn32",
	138	else => "qemu-" ++ @tagName(t),
	139	},
	140	// TODO: Actually check the SuperH version.
	141	.sh => "qemu-sh4",
	142	.sheb => "qemu-sh4eb",
	143	.sparc => if (candidate.cpu.has(.sparc, .v8plus)) "qemu-sparc32plus" else "qemu-sparc",
	144	.thumb => "qemu-arm",
	145	.thumbeb => "qemu-armeb",
130	146	else => "qemu-" ++ @tagName(t),
131	147	},
132		.sparc => if (candidate.cpu.has(.sparc, .v8plus)) "qemu-sparc32plus" else "qemu-sparc",
133		.thumb => "qemu-arm",
134		.thumbeb => "qemu-armeb",
135		else => "qemu-" ++ @tagName(t),
136		} },
	148	},
137	149	else => bad_result,
138	150	},
139	151	else => bad_result,

src/InternPool.zig+18

...	...	@@ -12960,6 +12960,11 @@ const PackedCallingConvention = packed struct(u18) {
12960	12960	.incoming_stack_alignment = .fromByteUnits(pl.incoming_stack_alignment orelse 0),
12961	12961	.extra = @intFromEnum(pl.type),
12962	12962	},
	12963	std.builtin.CallingConvention.MicroblazeInterruptOptions => .{
	12964	.tag = tag,
	12965	.incoming_stack_alignment = .fromByteUnits(pl.incoming_stack_alignment orelse 0),
	12966	.extra = @intFromEnum(pl.type),
	12967	},
12963	12968	std.builtin.CallingConvention.MipsInterruptOptions => .{
12964	12969	.tag = tag,
12965	12970	.incoming_stack_alignment = .fromByteUnits(pl.incoming_stack_alignment orelse 0),
...	...	@@ -12970,6 +12975,11 @@ const PackedCallingConvention = packed struct(u18) {
12970	12975	.incoming_stack_alignment = .fromByteUnits(pl.incoming_stack_alignment orelse 0),
12971	12976	.extra = @intFromEnum(pl.mode),
12972	12977	},
	12978	std.builtin.CallingConvention.ShInterruptOptions => .{
	12979	.tag = tag,
	12980	.incoming_stack_alignment = .fromByteUnits(pl.incoming_stack_alignment orelse 0),
	12981	.extra = @intFromEnum(pl.save),
	12982	},
12973	12983	else => comptime unreachable,
12974	12984	},
12975	12985	};
...	...	@@ -12997,6 +13007,10 @@ const PackedCallingConvention = packed struct(u18) {
12997	13007	.incoming_stack_alignment = cc.incoming_stack_alignment.toByteUnits(),
12998	13008	.type = @enumFromInt(cc.extra),
12999	13009	},
	13010	std.builtin.CallingConvention.MicroblazeInterruptOptions => .{
	13011	.incoming_stack_alignment = cc.incoming_stack_alignment.toByteUnits(),
	13012	.type = @enumFromInt(cc.extra),
	13013	},
13000	13014	std.builtin.CallingConvention.MipsInterruptOptions => .{
13001	13015	.incoming_stack_alignment = cc.incoming_stack_alignment.toByteUnits(),
13002	13016	.mode = @enumFromInt(cc.extra),
...	...	@@ -13005,6 +13019,10 @@ const PackedCallingConvention = packed struct(u18) {
13005	13019	.incoming_stack_alignment = cc.incoming_stack_alignment.toByteUnits(),
13006	13020	.mode = @enumFromInt(cc.extra),
13007	13021	},
	13022	std.builtin.CallingConvention.ShInterruptOptions => .{
	13023	.incoming_stack_alignment = cc.incoming_stack_alignment.toByteUnits(),
	13024	.save = @enumFromInt(cc.extra),
	13025	},
13008	13026	else => comptime unreachable,
13009	13027	},
13010	13028	),

src/Sema.zig+25-3

...	...	@@ -9035,6 +9035,7 @@ pub fn handleExternLibName(
9035	9035	/// functions or there are no more other calling conventions that support variadic functions.
9036	9036	const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{
9037	9037	.x86_64_sysv,
	9038	.x86_64_x32,
9038	9039	.x86_64_win,
9039	9040	.x86_sysv,
9040	9041	.x86_win,
...	...	@@ -9043,8 +9044,10 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9043	9044	.aarch64_aapcs_win,
9044	9045	.aarch64_vfabi,
9045	9046	.aarch64_vfabi_sve,
	9047	.alpha_osf,
9046	9048	.arm_aapcs,
9047	9049	.arm_aapcs_vfp,
	9050	.microblaze_std,
9048	9051	.mips64_n64,
9049	9052	.mips64_n32,
9050	9053	.mips_o32,
...	...	@@ -9068,6 +9071,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9068	9071	.csky_sysv,
9069	9072	.hexagon_sysv,
9070	9073	.hexagon_sysv_hvx,
	9074	.hppa_elf,
	9075	.hppa64_elf,
9071	9076	.lanai_sysv,
9072	9077	.loongarch64_lp64,
9073	9078	.loongarch32_ilp32,
...	...	@@ -9078,6 +9083,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
9078	9083	.or1k_sysv,
9079	9084	.s390x_sysv,
9080	9085	.s390x_sysv_vx,
	9086	.sh_gnu,
	9087	.sh_renesas,
9081	9088	.ve_sysv,
9082	9089	.xcore_xs1,
9083	9090	.xcore_xs2,
...	...	@@ -9128,10 +9135,13 @@ fn callConvIsCallable(cc: std.builtin.CallingConvention.Tag) bool {
9128	9135	.avr_signal,
9129	9136	.csky_interrupt,
9130	9137	.m68k_interrupt,
	9138	.microblaze_interrupt,
9131	9139	.mips_interrupt,
9132	9140	.mips64_interrupt,
	9141	.msp430_interrupt,
9133	9142	.riscv32_interrupt,
9134	9143	.riscv64_interrupt,
	9144	.sh_interrupt,
9135	9145	.x86_interrupt,
9136	9146	.x86_64_interrupt,
9137	9147
...	...	@@ -9287,13 +9297,16 @@ fn funcCommon(
9287	9297	},
9288	9298	.arc_interrupt,
9289	9299	.arm_interrupt,
	9300	.microblaze_interrupt,
9290	9301	.mips64_interrupt,
9291	9302	.mips_interrupt,
9292	9303	.riscv64_interrupt,
9293	9304	.riscv32_interrupt,
	9305	.sh_interrupt,
9294	9306	.avr_interrupt,
9295	9307	.csky_interrupt,
9296	9308	.m68k_interrupt,
	9309	.msp430_interrupt,
9297	9310	.avr_signal,
9298	9311	=> return sema.fail(block, param_src, "parameters are not allowed with '{s}' calling convention", .{@tagName(cc)}),
9299	9312	else => {},
...	...	@@ -9517,10 +9530,13 @@ fn finishFunc(
9517	9530	.mips_interrupt,
9518	9531	.riscv64_interrupt,
9519	9532	.riscv32_interrupt,
	9533	.sh_interrupt,
9520	9534	.arc_interrupt,
9521	9535	.avr_interrupt,
9522	9536	.csky_interrupt,
9523	9537	.m68k_interrupt,
	9538	.microblaze_interrupt,
	9539	.msp430_interrupt,
9524	9540	.avr_signal,
9525	9541	=> if (return_type.zigTypeTag(zcu) != .void and return_type.zigTypeTag(zcu) != .noreturn) {
9526	9542	return sema.fail(block, ret_ty_src, "function with calling convention '{s}' must return 'void' or 'noreturn'", .{@tagName(cc_resolved)});
...	...	@@ -30047,12 +30063,18 @@ fn callconvCoerceAllowed(
30047	30063	std.builtin.CallingConvention.ArmInterruptOptions => {
30048	30064	if (src_data.type != dest_data.type) return false;
30049	30065	},
	30066	std.builtin.CallingConvention.MicroblazeInterruptOptions => {
	30067	if (src_data.type != dest_data.type) return false;
	30068	},
30050	30069	std.builtin.CallingConvention.MipsInterruptOptions => {
30051	30070	if (src_data.mode != dest_data.mode) return false;
30052	30071	},
30053	30072	std.builtin.CallingConvention.RiscvInterruptOptions => {
30054	30073	if (src_data.mode != dest_data.mode) return false;
30055	30074	},
	30075	std.builtin.CallingConvention.ShInterruptOptions => {
	30076	if (src_data.save != dest_data.save) return false;
	30077	},
30056	30078	else => comptime unreachable,
30057	30079	}
30058	30080	},
...	...	@@ -36495,7 +36517,7 @@ fn resolveAddressSpace(
36495	36517	block: *Block,
36496	36518	src: LazySrcLoc,
36497	36519	zir_ref: Zir.Inst.Ref,
36498		ctx: std.builtin.AddressSpace.Context,
	36520	ctx: std.Target.AddressSpaceContext,
36499	36521	) !std.builtin.AddressSpace {
36500	36522	const air_ref = try sema.resolveInst(zir_ref);
36501	36523	return sema.analyzeAsAddressSpace(block, src, air_ref, ctx);
...	...	@@ -36506,7 +36528,7 @@ pub fn analyzeAsAddressSpace(
36506	36528	block: *Block,
36507	36529	src: LazySrcLoc,
36508	36530	air_ref: Air.Inst.Ref,
36509		ctx: std.builtin.AddressSpace.Context,
	36531	ctx: std.Target.AddressSpaceContext,
36510	36532	) !std.builtin.AddressSpace {
36511	36533	const pt = sema.pt;
36512	36534	const addrspace_ty = try sema.getBuiltinType(src, .AddressSpace);
...	...	@@ -37631,7 +37653,7 @@ pub fn resolveNavPtrModifiers(
37631	37653	};
37632	37654
37633	37655	const @"addrspace": std.builtin.AddressSpace = as: {
37634		const addrspace_ctx: std.builtin.AddressSpace.Context = switch (zir_decl.kind) {
	37656	const addrspace_ctx: std.Target.AddressSpaceContext = switch (zir_decl.kind) {
37635	37657	.@"var" => .variable,
37636	37658	else => switch (nav_ty.zigTypeTag(zcu)) {
37637	37659	.@"fn" => .function,

src/Zcu.zig+14-51

...	...	@@ -3836,61 +3836,17 @@ pub fn atomicPtrAlignment(
3836	3836	) AtomicPtrAlignmentError!Alignment {
3837	3837	const target = zcu.getTarget();
3838	3838	const max_atomic_bits: u16 = switch (target.cpu.arch) {
3839		.avr,
3840		.msp430,
3841		=> 16,
3842
3843		.arc,
3844		.arm,
3845		.armeb,
3846		.hexagon,
3847		.m68k,
3848		.mips,
3849		.mipsel,
3850		.nvptx,
3851		.or1k,
3852		.powerpc,
3853		.powerpcle,
3854		.riscv32,
3855		.riscv32be,
3856		.sparc,
3857		.thumb,
3858		.thumbeb,
3859		.x86,
3860		.xcore,
3861		.kalimba,
3862		.lanai,
3863		.wasm32,
3864		.csky,
3865		.spirv32,
3866		.loongarch32,
3867		.xtensa,
3868		.propeller,
3869		=> 32,
3870
3871		.amdgcn,
3872		.bpfel,
3873		.bpfeb,
3874		.mips64,
3875		.mips64el,
3876		.nvptx64,
3877		.powerpc64,
3878		.powerpc64le,
3879		.riscv64,
3880		.riscv64be,
3881		.sparc64,
3882		.s390x,
3883		.wasm64,
3884		.ve,
3885		.spirv64,
3886		.loongarch64,
3887		=> 64,
3888
3889	3839	.aarch64,
3890	3840	.aarch64_be,
3891	3841	=> 128,
3892	3842
3893		.x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64,
	3843	.mips64,
	3844	.mips64el,
	3845	=> 64, // N32 should be 64, not 32.
	3846
	3847	.x86_64 => if (target.cpu.has(.x86, .cx16)) 128 else 64, // x32 should be 64 or 128, not 32.
	3848
	3849	else => target.ptrBitWidth(),
3894	3850	};
3895	3851
3896	3852	if (ty.toIntern() == .bool_type) return .none;
...	...	@@ -4470,6 +4426,7 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
4470	4426	.riscv32_ilp32_v,
4471	4427	.m68k_rtd,
4472	4428	.m68k_interrupt,
	4429	.msp430_interrupt,
4473	4430	=> \|opts\| opts.incoming_stack_alignment == null,
4474	4431
4475	4432	.arm_aapcs_vfp,
...	...	@@ -4481,6 +4438,9 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
4481	4438	.arm_interrupt,
4482	4439	=> \|opts\| opts.incoming_stack_alignment == null,
4483	4440
	4441	.microblaze_interrupt,
	4442	=> \|opts\| opts.incoming_stack_alignment == null,
	4443
4484	4444	.mips_interrupt,
4485	4445	.mips64_interrupt,
4486	4446	=> \|opts\| opts.incoming_stack_alignment == null,
...	...	@@ -4489,6 +4449,9 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
4489	4449	.riscv64_interrupt,
4490	4450	=> \|opts\| opts.incoming_stack_alignment == null,
4491	4451
	4452	.sh_interrupt,
	4453	=> \|opts\| opts.incoming_stack_alignment == null,
	4454
4492	4455	.x86_sysv,
4493	4456	.x86_win,
4494	4457	.x86_stdcall,

src/codegen/c.zig+16

...	...	@@ -8092,6 +8092,13 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8092	8092
8093	8093	.avr_signal => "signal",
8094	8094
	8095	.microblaze_interrupt => \|opts\| switch (opts.type) {
	8096	.user => "save_volatiles",
	8097	.regular => "interrupt_handler",
	8098	.fast => "fast_interrupt",
	8099	.breakpoint => "break_handler",
	8100	},
	8101
8095	8102	.mips_interrupt,
8096	8103	.mips64_interrupt,
8097	8104	=> \|opts\| switch (opts.mode) {
...	...	@@ -8106,11 +8113,20 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
8106	8113	inline else => \|m\| "interrupt(\"" ++ @tagName(m) ++ "\")",
8107	8114	},
8108	8115
	8116	.sh_renesas => "renesas",
	8117	.sh_interrupt => \|opts\| switch (opts.save) {
	8118	.fpscr => "trapa_handler", // Implies `interrupt_handler`.
	8119	.high => "interrupt_handler, nosave_low_regs",
	8120	.full => "interrupt_handler",
	8121	.bank => "interrupt_handler, resbank",
	8122	},
	8123
8109	8124	.m68k_rtd => "m68k_rtd",
8110	8125
8111	8126	.avr_interrupt,
8112	8127	.csky_interrupt,
8113	8128	.m68k_interrupt,
	8129	.msp430_interrupt,
8114	8130	.x86_interrupt,
8115	8131	.x86_64_interrupt,
8116	8132	=> "interrupt",

src/codegen/llvm.zig+39

...	...	@@ -106,9 +106,18 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
106	106	.wasm64 => "wasm64",
107	107	.ve => "ve",
108	108
	109	.alpha,
	110	.arceb,
	111	.hppa,
	112	.hppa64,
109	113	.kalimba,
	114	.microblaze,
	115	.microblazeel,
110	116	.or1k,
111	117	.propeller,
	118	.sh,
	119	.sheb,
	120	.xtensaeb,
112	121	=> unreachable, // Gated by hasLlvmSupport().
113	122	};
114	123
...	...	@@ -473,9 +482,18 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
473	482	.loongarch64 => "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
474	483	.xtensa => "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32",
475	484
	485	.alpha,
	486	.arceb,
	487	.hppa,
	488	.hppa64,
476	489	.kalimba,
	490	.microblaze,
	491	.microblazeel,
477	492	.or1k,
478	493	.propeller,
	494	.sh,
	495	.sheb,
	496	.xtensaeb,
479	497	=> unreachable, // Gated by hasLlvmSupport().
480	498	};
481	499	}
...	...	@@ -11819,6 +11837,8 @@ pub fn toLlvmCallConv(cc: std.builtin.CallingConvention, target: *const std.Targ
11819	11837	std.builtin.CallingConvention.ArcInterruptOptions,
11820	11838	std.builtin.CallingConvention.ArmInterruptOptions,
11821	11839	std.builtin.CallingConvention.RiscvInterruptOptions,
	11840	std.builtin.CallingConvention.ShInterruptOptions,
	11841	std.builtin.CallingConvention.MicroblazeInterruptOptions,
11822	11842	std.builtin.CallingConvention.MipsInterruptOptions,
11823	11843	std.builtin.CallingConvention.CommonOptions,
11824	11844	=> .{ pl.incoming_stack_alignment, 0 },
...	...	@@ -11882,6 +11902,7 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11882	11902	.avr_interrupt => .avr_intrcc,
11883	11903	.m68k_rtd => .m68k_rtdcc,
11884	11904	.m68k_interrupt => .m68k_intrcc,
	11905	.msp430_interrupt => .msp430_intrcc,
11885	11906	.amdgcn_kernel => .amdgpu_kernel,
11886	11907	.amdgcn_cs => .amdgpu_cs,
11887	11908	.nvptx_device => .ptx_device,
...	...	@@ -11901,9 +11922,13 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11901	11922	.x86_sysv,
11902	11923	.x86_win,
11903	11924	.x86_thiscall_mingw,
	11925	.x86_64_x32,
11904	11926	.aarch64_aapcs,
11905	11927	.aarch64_aapcs_darwin,
11906	11928	.aarch64_aapcs_win,
	11929	.alpha_osf,
	11930	.microblaze_std,
	11931	.microblaze_interrupt,
11907	11932	.mips64_n64,
11908	11933	.mips64_n32,
11909	11934	.mips_o32,
...	...	@@ -11926,6 +11951,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11926	11951	.csky_sysv,
11927	11952	.hexagon_sysv,
11928	11953	.hexagon_sysv_hvx,
	11954	.hppa_elf,
	11955	.hppa64_elf,
11929	11956	.lanai_sysv,
11930	11957	.loongarch64_lp64,
11931	11958	.loongarch32_ilp32,
...	...	@@ -11936,6 +11963,9 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
11936	11963	.propeller_sysv,
11937	11964	.s390x_sysv,
11938	11965	.s390x_sysv_vx,
	11966	.sh_gnu,
	11967	.sh_renesas,
	11968	.sh_interrupt,
11939	11969	.ve_sysv,
11940	11970	.xcore_xs1,
11941	11971	.xcore_xs2,
...	...	@@ -13107,9 +13137,18 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
13107	13137	},
13108	13138
13109	13139	// LLVM does does not have a backend for these.
	13140	.alpha,
	13141	.arceb,
	13142	.hppa,
	13143	.hppa64,
13110	13144	.kalimba,
	13145	.microblaze,
	13146	.microblazeel,
13111	13147	.or1k,
13112	13148	.propeller,
	13149	.sh,
	13150	.sheb,
	13151	.xtensaeb,
13113	13152	=> unreachable,
13114	13153	}
13115	13154	}

src/link/Dwarf.zig+5

...	...	@@ -3905,6 +3905,8 @@ fn updateLazyType(
3905	3905
3906	3906	.m68k_rtd => .LLVM_M68kRTD,
3907	3907
	3908	.sh_renesas => .GNU_renesas_sh,
	3909
3908	3910	.amdgcn_kernel => .LLVM_OpenCLKernel,
3909	3911	.nvptx_kernel,
3910	3912	.spirv_kernel,
...	...	@@ -3917,12 +3919,15 @@ fn updateLazyType(
3917	3919	.mips_interrupt,
3918	3920	.riscv64_interrupt,
3919	3921	.riscv32_interrupt,
	3922	.sh_interrupt,
3920	3923	.arc_interrupt,
3921	3924	.avr_builtin,
3922	3925	.avr_signal,
3923	3926	.avr_interrupt,
3924	3927	.csky_interrupt,
3925	3928	.m68k_interrupt,
	3929	.microblaze_interrupt,
	3930	.msp430_interrupt,
3926	3931	=> .normal,
3927	3932
3928	3933	else => .nocall,

src/target.zig+21-3

...	...	@@ -216,9 +216,18 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
216	216	=> false,
217	217
218	218	// No LLVM backend exists.
	219	.alpha,
	220	.arceb,
	221	.hppa,
	222	.hppa64,
219	223	.kalimba,
	224	.microblaze,
	225	.microblazeel,
220	226	.or1k,
221	227	.propeller,
	228	.sh,
	229	.sheb,
	230	.xtensaeb,
222	231	=> false,
223	232	};
224	233	}
...	...	@@ -711,18 +720,26 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
711	720	.csky,
712	721	.m68k,
713	722	.msp430,
	723	.sh,
	724	.sheb,
714	725	.s390x,
715	726	.xcore,
716	727	=> .@"2",
	728	.aarch64,
	729	.aarch64_be,
	730	.alpha,
717	731	.arc,
	732	.arceb,
718	733	.arm,
719	734	.armeb,
720		.aarch64,
721		.aarch64_be,
722	735	.hexagon,
	736	.hppa,
	737	.hppa64,
723	738	.lanai,
724	739	.loongarch32,
725	740	.loongarch64,
	741	.microblaze,
	742	.microblazeel,
726	743	.mips,
727	744	.mipsel,
728	745	.powerpc,
...	...	@@ -732,9 +749,10 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
732	749	.sparc,
733	750	.sparc64,
734	751	.xtensa,
	752	.xtensaeb,
735	753	=> .@"4",
736		.bpfel,
737	754	.bpfeb,
	755	.bpfel,
738	756	.mips64,
739	757	.mips64el,
740	758	=> .@"8",

test/cases/compile_errors/invalid_variadic_function.zig+2-2

...	...	@@ -12,6 +12,6 @@ comptime {
12	12	// target=x86_64-linux
13	13	//
14	14	// :1:8: error: variadic function does not support 'auto' calling convention
15		// :1:8: note: supported calling conventions: 'x86_64_sysv', 'x86_64_win'
	15	// :1:8: note: supported calling conventions: 'x86_64_sysv', 'x86_64_x32', 'x86_64_win'
16	16	// :2:16: error: variadic function does not support 'inline' calling convention
17		// :2:16: note: supported calling conventions: 'x86_64_sysv', 'x86_64_win'
	17	// :2:16: note: supported calling conventions: 'x86_64_sysv', 'x86_64_x32', 'x86_64_win'

test/cases/compile_errors/reify_type.Fn_with_is_var_args_true_and_non-C_callconv.zig+1-1

...	...	@@ -15,4 +15,4 @@ comptime {
15	15	// target=x86_64-linux
16	16	//
17	17	// :1:13: error: variadic function does not support 'auto' calling convention
18		// :1:13: note: supported calling conventions: 'x86_64_sysv', 'x86_64_win'
	18	// :1:13: note: supported calling conventions: 'x86_64_sysv', 'x86_64_x32', 'x86_64_win'

test/tests.zig+11-12

...	...	@@ -40,7 +40,7 @@ const test_targets = blk: {
40	40	// getBaselineCpuFeatures calls populateDependencies which has a O(N ^ 2) algorithm
41	41	// (where N is roughly 160, which technically makes it O(1), but it adds up to a
42	42	// lot of branches)
43		@setEvalBranchQuota(50000);
	43	@setEvalBranchQuota(60000);
44	44	break :blk [_]TestTarget{
45	45	// Native Targets
46	46
...	...	@@ -397,16 +397,15 @@ const test_targets = blk: {
397	397	}) catch unreachable,
398	398	.link_libc = true,
399	399	},
400		// Currently crashes in qemu-hexagon.
401		// .{
402		// .target = std.Target.Query.parse(.{
403		// .arch_os_abi = "hexagon-linux-musl",
404		// .cpu_features = "baseline+long_calls",
405		// }) catch unreachable,
406		// .linkage = .dynamic,
407		// .link_libc = true,
408		// .extra_target = true,
409		// },
	400	.{
	401	.target = std.Target.Query.parse(.{
	402	.arch_os_abi = "hexagon-linux-musl",
	403	.cpu_features = "baseline+long_calls",
	404	}) catch unreachable,
	405	.linkage = .dynamic,
	406	.link_libc = true,
	407	.extra_target = true,
	408	},
410	409
411	410	.{
412	411	.target = .{
...	...	@@ -1551,7 +1550,7 @@ const CAbiTarget = struct {
1551	1550	};
1552	1551
1553	1552	const c_abi_targets = blk: {
1554		@setEvalBranchQuota(20000);
	1553	@setEvalBranchQuota(30000);
1555	1554	break :blk [_]CAbiTarget{
1556	1555	// Native Targets
1557	1556

author	Alex Rønne Petersen <alex@alexrp.com> 2025-10-23 19:35:54+02:00
committer	GitHub <noreply@github.com> 2025-10-23 19:35:54+02:00
log	70206af4829964420d7902488c66ba0edc37ba76
tree	217d18cc05cd69c06e4f9f367a6ca2c3492e5c6d
parent	e5fcc8192da248b890b5f3c8eb65ddec010ba0ef
parent	07d764dc301d4547a6dab131cd6b687fef3278c7
signature	Signed by PGP key B5690EEEBB952194

Merge pull request #25640 from alexrp/std-target-more-arches