diff --git a/src/codegen/loongarch/decode_tree.zon b/src/codegen/loongarch/decode_tree.zon new file mode 100644 index 0000000000000000000000000000000000000000..2dc1a11fee7f9db7cccb6f6d5fba09604bb38b5c --- /dev/null +++ b/src/codegen/loongarch/decode_tree.zon @@ -0,0 +1,2817 @@ +// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. +.{ .mask = 0xfc000000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x03c00000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x003c0000, .cases = .{ + .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"adc.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"adc.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"adc.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"adc.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"sbc.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"sbc.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"sbc.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"sbc.w" } }, + } } }, + .{ .value = 0x00100000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00008000, .then = .{ .instruction = .@"add.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"add.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .maskeqz } }, + .{ .value = 0x00038000, .then = .{ .instruction = .masknez } }, + .{ .value = 0x00020000, .then = .{ .instruction = .slt } }, + .{ .value = 0x00028000, .then = .{ .instruction = .sltu } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"sub.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"sub.w" } }, + } } }, + .{ .value = 0x00280000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00018000, .then = .{ .instruction = .@"addu12i.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"addu12i.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"break" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .dbgcall } }, + .{ .value = 0x00038000, .then = .{ .instruction = .hypcall } }, + .{ .value = 0x00030000, .then = .{ .instruction = .syscall } }, + } } }, + .{ .value = 0x00140000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00008000, .then = .{ .instruction = .@"and" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .andn } }, + .{ .value = 0x00000000, .then = .{ .instruction = .nor } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"or" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .orn } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"sll.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"srl.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .xor } }, + } } }, + .{ .value = 0x00380000, .then = .{ .mask = 0x00038010, .cases = .{ + .{ .value = 0x00000010, .then = .{ .instruction = .@"armadc.w" } }, + .{ .value = 0x00010010, .then = .{ .instruction = .@"armand.w" } }, + .{ .value = 0x00018010, .then = .{ .instruction = .@"armor.w" } }, + .{ .value = 0x00008010, .then = .{ .instruction = .@"armsbc.w" } }, + .{ .value = 0x00028010, .then = .{ .instruction = .@"armsll.w" } }, + .{ .value = 0x00038010, .then = .{ .instruction = .@"armsra.w" } }, + .{ .value = 0x00030010, .then = .{ .instruction = .@"armsrl.w" } }, + .{ .value = 0x00020010, .then = .{ .instruction = .@"armxor.w" } }, + } } }, + .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"armadd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .armmove } }, + .{ .value = 0x00028000, .then = .{ .mask = 0x000043e0, .cases = .{ + .{ .value = 0x00004000, .then = .{ .instruction = .armsetj } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86setj } }, + } } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"armsub.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"rcr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"rcr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"rcr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"rcr.w" } }, + } } }, + .{ .value = 0x003c0000, .then = .{ .mask = 0x00038010, .cases = .{ + .{ .value = 0x00038010, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x0000000e, .then = .{ .instruction = .@"armmov.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"armmov.w" } }, + .{ .value = 0x0000000c, .then = .{ .instruction = .@"armnot.w" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"armrrx.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86and.b" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86and.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86and.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86and.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86or.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86or.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86or.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86or.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86xor.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86xor.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86xor.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86xor.w" } }, + } } }, + .{ .value = 0x00000010, .then = .{ .instruction = .@"armrotr.w" } }, + .{ .value = 0x00020010, .then = .{ .instruction = .@"armrotri.w" } }, + .{ .value = 0x00008010, .then = .{ .instruction = .@"armslli.w" } }, + .{ .value = 0x00018010, .then = .{ .instruction = .@"armsrai.w" } }, + .{ .value = 0x00010010, .then = .{ .instruction = .@"armsrli.w" } }, + .{ .value = 0x00030000, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86adc.b" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86adc.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86adc.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86adc.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86add.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86add.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86add.du" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86add.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86add.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86add.wu" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86sub.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86sub.d" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86sub.du" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86sub.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86sub.w" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86sub.wu" } }, + } } }, + .{ .value = 0x00028000, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86mul.b" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86mul.bu" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86mul.d" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86mul.du" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86mul.h" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86mul.hu" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86mul.w" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86mul.wu" } }, + } } }, + .{ .value = 0x00038000, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86rcl.b" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86rcl.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86rcl.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86rcl.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86rcr.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86rcr.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86rcr.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86rcr.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86rotl.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86rotl.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86rotl.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86rotl.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86rotr.b" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86rotr.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86rotr.h" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86rotr.w" } }, + } } }, + .{ .value = 0x00030010, .then = .{ .mask = 0x0000000f, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86sbc.b" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86sbc.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86sbc.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86sbc.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86sll.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86sll.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86sll.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86sll.w" } }, + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86sra.b" } }, + .{ .value = 0x0000000f, .then = .{ .instruction = .@"x86sra.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86sra.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86sra.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86srl.b" } }, + .{ .value = 0x0000000b, .then = .{ .instruction = .@"x86srl.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86srl.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86srl.w" } }, + } } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00018000, .then = .{ .instruction = .asrtgt } }, + .{ .value = 0x00010000, .then = .{ .instruction = .asrtle } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002000, .then = .{ .instruction = .@"clo.d" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"clo.w" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"clz.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"clz.w" } }, + .{ .value = 0x00006c00, .then = .{ .instruction = .cpucfg } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"cto.d" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"cto.w" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"ctz.d" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"ctz.w" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .movgr2scr } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .movscr2gr } }, + .{ .value = 0x00006800, .then = .{ .instruction = .@"rdtime.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"rdtimeh.w" } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"rdtimel.w" } }, + .{ .value = 0x00003000, .then = .{ .instruction = .@"revb.2h" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"revb.2w" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"revb.4h" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"revb.d" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"revbit.4b" } }, + .{ .value = 0x00004c00, .then = .{ .instruction = .@"revbit.8b" } }, + .{ .value = 0x00005400, .then = .{ .instruction = .@"revbit.d" } }, + .{ .value = 0x00005000, .then = .{ .instruction = .@"revbit.w" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"revh.2w" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"revh.d" } }, + .{ .value = 0x00005c00, .then = .{ .instruction = .@"sext.b" } }, + .{ .value = 0x00005800, .then = .{ .instruction = .@"sext.h" } }, + .{ .value = 0x00007400, .then = .{ .instruction = .x86mftop } }, + .{ .value = 0x00007000, .then = .{ .instruction = .x86mttop } }, + .{ .value = 0x00007800, .then = .{ .instruction = .x86setloope } }, + .{ .value = 0x00007c00, .then = .{ .instruction = .x86setloopne } }, + } } }, + .{ .value = 0x00008000, .then = .{ .mask = 0x00007c1f, .cases = .{ + .{ .value = 0x00000008, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000020, .then = .{ .instruction = .x86clrtm } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86settm } }, + } } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86dec.b" } }, + .{ .value = 0x00000007, .then = .{ .instruction = .@"x86dec.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86dec.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86dec.w" } }, + .{ .value = 0x00000009, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000020, .then = .{ .instruction = .x86dectop } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86inctop } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86inc.b" } }, + .{ .value = 0x00000003, .then = .{ .instruction = .@"x86inc.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86inc.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86inc.w" } }, + } } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"catpick.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"catpick.w" } }, + .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"crc.w.b.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"crc.w.d.w" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"crc.w.h.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"crc.w.w.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"crcc.w.b.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"crcc.w.d.w" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"crcc.w.h.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"crcc.w.w.w" } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"div.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"div.du" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"div.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"div.wu" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"mod.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"mod.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"mod.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"mod.wu" } }, + } } }, + .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00018000, .then = .{ .instruction = .@"mul.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"mul.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"mulh.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"mulh.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"mulh.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"mulh.wu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"mulw.d.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"mulw.d.wu" } }, + } } }, + .{ .value = 0x00180000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"rotr.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"rotr.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"rotr.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"rotr.w" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"sll.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"sra.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"sra.w" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"srl.d" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .instruction = .@"sladd.d" } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"sladd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"sladd.wu" } }, + } } }, + } } }, + .{ .value = 0x02c00000, .then = .{ .instruction = .@"addi.d" } }, + .{ .value = 0x02800000, .then = .{ .instruction = .@"addi.w" } }, + .{ .value = 0x03400000, .then = .{ .instruction = .andi } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x00200000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x001c0000, .cases = .{ + .{ .value = 0x001c0000, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000040, .then = .{ .instruction = .armmfflag } }, + .{ .value = 0x00000060, .then = .{ .instruction = .armmtflag } }, + .{ .value = 0x00000000, .then = .{ .instruction = .x86mfflag } }, + .{ .value = 0x00000020, .then = .{ .instruction = .x86mtflag } }, + } } }, + .{ .value = 0x00100000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"rcri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"rcri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"rcri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"rcri.d" } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"rotri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"rotri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"rotri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"rotri.d" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"slli.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"slli.w" } }, + } } }, + .{ .value = 0x00080000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"srai.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"srai.w" } }, + } } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"srli.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"srli.w" } }, + } } }, + .{ .value = 0x00140000, .then = .{ .mask = 0x0003001f, .cases = .{ + .{ .value = 0x00000018, .then = .{ .instruction = .@"x86rcli.b" } }, + .{ .value = 0x0001001b, .then = .{ .instruction = .@"x86rcli.d" } }, + .{ .value = 0x00000019, .then = .{ .instruction = .@"x86rcli.h" } }, + .{ .value = 0x0000001a, .then = .{ .instruction = .@"x86rcli.w" } }, + .{ .value = 0x00000010, .then = .{ .instruction = .@"x86rcri.b" } }, + .{ .value = 0x00010013, .then = .{ .instruction = .@"x86rcri.d" } }, + .{ .value = 0x00000011, .then = .{ .instruction = .@"x86rcri.h" } }, + .{ .value = 0x00000012, .then = .{ .instruction = .@"x86rcri.w" } }, + .{ .value = 0x00000014, .then = .{ .instruction = .@"x86rotli.b" } }, + .{ .value = 0x00010017, .then = .{ .instruction = .@"x86rotli.d" } }, + .{ .value = 0x00000015, .then = .{ .instruction = .@"x86rotli.h" } }, + .{ .value = 0x00000016, .then = .{ .instruction = .@"x86rotli.w" } }, + .{ .value = 0x0000000c, .then = .{ .instruction = .@"x86rotri.b" } }, + .{ .value = 0x0001000f, .then = .{ .instruction = .@"x86rotri.d" } }, + .{ .value = 0x0000000d, .then = .{ .instruction = .@"x86rotri.h" } }, + .{ .value = 0x0000000e, .then = .{ .instruction = .@"x86rotri.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"x86slli.b" } }, + .{ .value = 0x00010003, .then = .{ .instruction = .@"x86slli.d" } }, + .{ .value = 0x00000001, .then = .{ .instruction = .@"x86slli.h" } }, + .{ .value = 0x00000002, .then = .{ .instruction = .@"x86slli.w" } }, + .{ .value = 0x00000008, .then = .{ .instruction = .@"x86srai.b" } }, + .{ .value = 0x0001000b, .then = .{ .instruction = .@"x86srai.d" } }, + .{ .value = 0x00000009, .then = .{ .instruction = .@"x86srai.h" } }, + .{ .value = 0x0000000a, .then = .{ .instruction = .@"x86srai.w" } }, + .{ .value = 0x00000004, .then = .{ .instruction = .@"x86srli.b" } }, + .{ .value = 0x00010007, .then = .{ .instruction = .@"x86srli.d" } }, + .{ .value = 0x00000005, .then = .{ .instruction = .@"x86srli.h" } }, + .{ .value = 0x00000006, .then = .{ .instruction = .@"x86srli.w" } }, + } } }, + .{ .value = 0x00180000, .then = .{ .instruction = .x86settag } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"bstrins.w" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"bstrpick.w" } }, + } } }, + } } }, + .{ .value = 0x00800000, .then = .{ .instruction = .@"bstrins.d" } }, + .{ .value = 0x00c00000, .then = .{ .instruction = .@"bstrpick.d" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"cu52i.d" } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x003f8000, .cases = .{ + .{ .value = 0x00140000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00000800, .then = .{ .instruction = .@"fabs.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"fabs.s" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"fclass.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"fclass.s" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"flogb.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"flogb.s" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"fneg.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"fneg.s" } }, + .{ .value = 0x00005800, .then = .{ .instruction = .@"frecip.d" } }, + .{ .value = 0x00005400, .then = .{ .instruction = .@"frecip.s" } }, + .{ .value = 0x00007800, .then = .{ .instruction = .@"frecipe.d" } }, + .{ .value = 0x00007400, .then = .{ .instruction = .@"frecipe.s" } }, + .{ .value = 0x00006800, .then = .{ .instruction = .@"frsqrt.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"frsqrt.s" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"fsqrt.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"fsqrt.s" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"fadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"fadd.s" } }, + .{ .value = 0x00130000, .then = .{ .instruction = .@"fcopysign.d" } }, + .{ .value = 0x00128000, .then = .{ .instruction = .@"fcopysign.s" } }, + .{ .value = 0x00148000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00004800, .then = .{ .instruction = .fcsrrd } }, + .{ .value = 0x00004000, .then = .{ .instruction = .fcsrwr } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"fcvt.ld.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"fcvt.ud.d" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"fmov.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"fmov.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"frsqrte.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"frsqrte.s" } }, + .{ .value = 0x00005400, .then = .{ .instruction = .movfcc2fr } }, + .{ .value = 0x00005c00, .then = .{ .instruction = .movfcc2gr } }, + .{ .value = 0x00005000, .then = .{ .instruction = .movfr2fcc } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"movfr2gr.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"movfr2gr.s" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"movfrh2gr.s" } }, + .{ .value = 0x00005800, .then = .{ .instruction = .movgr2fcc } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"movgr2fr.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"movgr2fr.w" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"movgr2frh.w" } }, + } } }, + .{ .value = 0x00150000, .then = .{ .instruction = .@"fcvt.d.ld" } }, + .{ .value = 0x00190000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002400, .then = .{ .instruction = .@"fcvt.d.s" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"fcvt.s.d" } }, + } } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"fdiv.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"fdiv.s" } }, + .{ .value = 0x001d0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002800, .then = .{ .instruction = .@"ffint.d.l" } }, + .{ .value = 0x00002000, .then = .{ .instruction = .@"ffint.d.w" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"ffint.s.l" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"ffint.s.w" } }, + } } }, + .{ .value = 0x00090000, .then = .{ .instruction = .@"fmax.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"fmax.s" } }, + .{ .value = 0x000d0000, .then = .{ .instruction = .@"fmaxa.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"fmaxa.s" } }, + .{ .value = 0x000b0000, .then = .{ .instruction = .@"fmin.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"fmin.s" } }, + .{ .value = 0x000f0000, .then = .{ .instruction = .@"fmina.d" } }, + .{ .value = 0x000e8000, .then = .{ .instruction = .@"fmina.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"fmul.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"fmul.s" } }, + .{ .value = 0x001e0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00004800, .then = .{ .instruction = .@"frint.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"frint.s" } }, + } } }, + .{ .value = 0x00110000, .then = .{ .instruction = .@"fscaleb.d" } }, + .{ .value = 0x00108000, .then = .{ .instruction = .@"fscaleb.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"fsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"fsub.s" } }, + .{ .value = 0x001b0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002800, .then = .{ .instruction = .@"ftint.l.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"ftint.l.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"ftint.w.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"ftint.w.s" } }, + } } }, + .{ .value = 0x001a0000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00002800, .then = .{ .instruction = .@"ftintrm.l.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"ftintrm.l.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"ftintrm.w.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"ftintrm.w.s" } }, + .{ .value = 0x00006800, .then = .{ .instruction = .@"ftintrp.l.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"ftintrp.l.s" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"ftintrp.w.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"ftintrp.w.s" } }, + } } }, + .{ .value = 0x001a8000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00006800, .then = .{ .instruction = .@"ftintrne.l.d" } }, + .{ .value = 0x00006400, .then = .{ .instruction = .@"ftintrne.l.s" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"ftintrne.w.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"ftintrne.w.s" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"ftintrz.l.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"ftintrz.l.s" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"ftintrz.w.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"ftintrz.w.s" } }, + } } }, + } } }, + .{ .value = 0x03800000, .then = .{ .instruction = .ori } }, + .{ .value = 0x02000000, .then = .{ .instruction = .slti } }, + .{ .value = 0x02400000, .then = .{ .instruction = .sltui } }, + .{ .value = 0x03c00000, .then = .{ .instruction = .xori } }, + } } }, + .{ .value = 0x10000000, .then = .{ .instruction = .@"addu16i.d" } }, + .{ .value = 0x38000000, .then = .{ .mask = 0x03ff8000, .cases = .{ + .{ .value = 0x005d0000, .then = .{ .instruction = .@"amadd.b" } }, + .{ .value = 0x00618000, .then = .{ .instruction = .@"amadd.d" } }, + .{ .value = 0x005d8000, .then = .{ .instruction = .@"amadd.h" } }, + .{ .value = 0x00610000, .then = .{ .instruction = .@"amadd.w" } }, + .{ .value = 0x005f0000, .then = .{ .instruction = .@"amadd_db.b" } }, + .{ .value = 0x006a8000, .then = .{ .instruction = .@"amadd_db.d" } }, + .{ .value = 0x005f8000, .then = .{ .instruction = .@"amadd_db.h" } }, + .{ .value = 0x006a0000, .then = .{ .instruction = .@"amadd_db.w" } }, + .{ .value = 0x00628000, .then = .{ .instruction = .@"amand.d" } }, + .{ .value = 0x00620000, .then = .{ .instruction = .@"amand.w" } }, + .{ .value = 0x006b8000, .then = .{ .instruction = .@"amand_db.d" } }, + .{ .value = 0x006b0000, .then = .{ .instruction = .@"amand_db.w" } }, + .{ .value = 0x00580000, .then = .{ .instruction = .@"amcas.b" } }, + .{ .value = 0x00598000, .then = .{ .instruction = .@"amcas.d" } }, + .{ .value = 0x00588000, .then = .{ .instruction = .@"amcas.h" } }, + .{ .value = 0x00590000, .then = .{ .instruction = .@"amcas.w" } }, + .{ .value = 0x005a0000, .then = .{ .instruction = .@"amcas_db.b" } }, + .{ .value = 0x005b8000, .then = .{ .instruction = .@"amcas_db.d" } }, + .{ .value = 0x005a8000, .then = .{ .instruction = .@"amcas_db.h" } }, + .{ .value = 0x005b0000, .then = .{ .instruction = .@"amcas_db.w" } }, + .{ .value = 0x00658000, .then = .{ .instruction = .@"ammax.d" } }, + .{ .value = 0x00678000, .then = .{ .instruction = .@"ammax.du" } }, + .{ .value = 0x00650000, .then = .{ .instruction = .@"ammax.w" } }, + .{ .value = 0x00670000, .then = .{ .instruction = .@"ammax.wu" } }, + .{ .value = 0x006e8000, .then = .{ .instruction = .@"ammax_db.d" } }, + .{ .value = 0x00708000, .then = .{ .instruction = .@"ammax_db.du" } }, + .{ .value = 0x006e0000, .then = .{ .instruction = .@"ammax_db.w" } }, + .{ .value = 0x00700000, .then = .{ .instruction = .@"ammax_db.wu" } }, + .{ .value = 0x00668000, .then = .{ .instruction = .@"ammin.d" } }, + .{ .value = 0x00688000, .then = .{ .instruction = .@"ammin.du" } }, + .{ .value = 0x00660000, .then = .{ .instruction = .@"ammin.w" } }, + .{ .value = 0x00680000, .then = .{ .instruction = .@"ammin.wu" } }, + .{ .value = 0x006f8000, .then = .{ .instruction = .@"ammin_db.d" } }, + .{ .value = 0x00718000, .then = .{ .instruction = .@"ammin_db.du" } }, + .{ .value = 0x006f0000, .then = .{ .instruction = .@"ammin_db.w" } }, + .{ .value = 0x00710000, .then = .{ .instruction = .@"ammin_db.wu" } }, + .{ .value = 0x00638000, .then = .{ .instruction = .@"amor.d" } }, + .{ .value = 0x00630000, .then = .{ .instruction = .@"amor.w" } }, + .{ .value = 0x006c8000, .then = .{ .instruction = .@"amor_db.d" } }, + .{ .value = 0x006c0000, .then = .{ .instruction = .@"amor_db.w" } }, + .{ .value = 0x005c0000, .then = .{ .instruction = .@"amswap.b" } }, + .{ .value = 0x00608000, .then = .{ .instruction = .@"amswap.d" } }, + .{ .value = 0x005c8000, .then = .{ .instruction = .@"amswap.h" } }, + .{ .value = 0x00600000, .then = .{ .instruction = .@"amswap.w" } }, + .{ .value = 0x005e0000, .then = .{ .instruction = .@"amswap_db.b" } }, + .{ .value = 0x00698000, .then = .{ .instruction = .@"amswap_db.d" } }, + .{ .value = 0x005e8000, .then = .{ .instruction = .@"amswap_db.h" } }, + .{ .value = 0x00690000, .then = .{ .instruction = .@"amswap_db.w" } }, + .{ .value = 0x00648000, .then = .{ .instruction = .@"amxor.d" } }, + .{ .value = 0x00640000, .then = .{ .instruction = .@"amxor.w" } }, + .{ .value = 0x006d8000, .then = .{ .instruction = .@"amxor_db.d" } }, + .{ .value = 0x006d0000, .then = .{ .instruction = .@"amxor_db.w" } }, + .{ .value = 0x00720000, .then = .{ .instruction = .dbar } }, + .{ .value = 0x00748000, .then = .{ .instruction = .@"fldgt.d" } }, + .{ .value = 0x00740000, .then = .{ .instruction = .@"fldgt.s" } }, + .{ .value = 0x00758000, .then = .{ .instruction = .@"fldle.d" } }, + .{ .value = 0x00750000, .then = .{ .instruction = .@"fldle.s" } }, + .{ .value = 0x00340000, .then = .{ .instruction = .@"fldx.d" } }, + .{ .value = 0x00300000, .then = .{ .instruction = .@"fldx.s" } }, + .{ .value = 0x00768000, .then = .{ .instruction = .@"fstgt.d" } }, + .{ .value = 0x00760000, .then = .{ .instruction = .@"fstgt.s" } }, + .{ .value = 0x00778000, .then = .{ .instruction = .@"fstle.d" } }, + .{ .value = 0x00770000, .then = .{ .instruction = .@"fstle.s" } }, + .{ .value = 0x003c0000, .then = .{ .instruction = .@"fstx.d" } }, + .{ .value = 0x00380000, .then = .{ .instruction = .@"fstx.s" } }, + .{ .value = 0x00728000, .then = .{ .instruction = .ibar } }, + .{ .value = 0x00780000, .then = .{ .instruction = .@"ldgt.b" } }, + .{ .value = 0x00798000, .then = .{ .instruction = .@"ldgt.d" } }, + .{ .value = 0x00788000, .then = .{ .instruction = .@"ldgt.h" } }, + .{ .value = 0x00790000, .then = .{ .instruction = .@"ldgt.w" } }, + .{ .value = 0x007a0000, .then = .{ .instruction = .@"ldle.b" } }, + .{ .value = 0x007b8000, .then = .{ .instruction = .@"ldle.d" } }, + .{ .value = 0x007a8000, .then = .{ .instruction = .@"ldle.h" } }, + .{ .value = 0x007b0000, .then = .{ .instruction = .@"ldle.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ldx.b" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"ldx.bu" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"ldx.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"ldx.h" } }, + .{ .value = 0x00240000, .then = .{ .instruction = .@"ldx.hu" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"ldx.w" } }, + .{ .value = 0x00280000, .then = .{ .instruction = .@"ldx.wu" } }, + .{ .value = 0x00578000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00000800, .then = .{ .instruction = .@"llacq.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"llacq.w" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"screl.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"screl.w" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .instruction = .preldx } }, + .{ .value = 0x00570000, .then = .{ .instruction = .@"sc.q" } }, + .{ .value = 0x007c0000, .then = .{ .instruction = .@"stgt.b" } }, + .{ .value = 0x007d8000, .then = .{ .instruction = .@"stgt.d" } }, + .{ .value = 0x007c8000, .then = .{ .instruction = .@"stgt.h" } }, + .{ .value = 0x007d0000, .then = .{ .instruction = .@"stgt.w" } }, + .{ .value = 0x007e0000, .then = .{ .instruction = .@"stle.b" } }, + .{ .value = 0x007f8000, .then = .{ .instruction = .@"stle.d" } }, + .{ .value = 0x007e8000, .then = .{ .instruction = .@"stle.h" } }, + .{ .value = 0x007f0000, .then = .{ .instruction = .@"stle.w" } }, + .{ .value = 0x00100000, .then = .{ .instruction = .@"stx.b" } }, + .{ .value = 0x001c0000, .then = .{ .instruction = .@"stx.d" } }, + .{ .value = 0x00140000, .then = .{ .instruction = .@"stx.h" } }, + .{ .value = 0x00180000, .then = .{ .instruction = .@"stx.w" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .vldx } }, + .{ .value = 0x00440000, .then = .{ .instruction = .vstx } }, + .{ .value = 0x00480000, .then = .{ .instruction = .xvldx } }, + .{ .value = 0x004c0000, .then = .{ .instruction = .xvstx } }, + } } }, + .{ .value = 0x50000000, .then = .{ .instruction = .b } }, + .{ .value = 0x48000000, .then = .{ .mask = 0x00000300, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .bceqz } }, + .{ .value = 0x00000100, .then = .{ .instruction = .bcnez } }, + .{ .value = 0x00000200, .then = .{ .instruction = .jiscr0 } }, + .{ .value = 0x00000300, .then = .{ .instruction = .jiscr1 } }, + } } }, + .{ .value = 0x58000000, .then = .{ .instruction = .beq } }, + .{ .value = 0x40000000, .then = .{ .instruction = .beqz } }, + .{ .value = 0x60000000, .then = .{ .instruction = .bgt } }, + .{ .value = 0x68000000, .then = .{ .instruction = .bgtu } }, + .{ .value = 0x54000000, .then = .{ .instruction = .bl } }, + .{ .value = 0x64000000, .then = .{ .instruction = .ble } }, + .{ .value = 0x6c000000, .then = .{ .instruction = .bleu } }, + .{ .value = 0x5c000000, .then = .{ .instruction = .bne } }, + .{ .value = 0x44000000, .then = .{ .instruction = .bnez } }, + .{ .value = 0x04000000, .then = .{ .mask = 0x03000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .mask = 0x00c00000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .cacop } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x003c0000, .cases = .{ + .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00007c00, .cases = .{ + .{ .value = 0x00003800, .then = .{ .instruction = .eret } }, + .{ .value = 0x00002000, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbclr } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbclr } }, + } } }, + .{ .value = 0x00003400, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbfill } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbfill } }, + } } }, + .{ .value = 0x00002400, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbflush } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbflush } }, + } } }, + .{ .value = 0x00002c00, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbrd } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbrd } }, + } } }, + .{ .value = 0x00002800, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbsrch } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbsrch } }, + } } }, + .{ .value = 0x00003000, .then = .{ .mask = 0x000003ff, .cases = .{ + .{ .value = 0x00000001, .then = .{ .instruction = .gtlbwr } }, + .{ .value = 0x00000000, .then = .{ .instruction = .tlbwr } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"iocsrrd.b" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"iocsrrd.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"iocsrrd.h" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"iocsrrd.w" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"iocsrwr.b" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"iocsrwr.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"iocsrwr.h" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"iocsrwr.w" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .idle } }, + .{ .value = 0x00018000, .then = .{ .instruction = .tlbinv } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xxx.unknown.1" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .lddir } }, + .{ .value = 0x00040000, .then = .{ .instruction = .ldpte } }, + } } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .csrrd } }, + .{ .value = 0x00000020, .then = .{ .instruction = .csrwr } }, + .{ .then = .{ .instruction = .csrxchg } }, + } } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x000003e0, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .gcsrrd } }, + .{ .value = 0x00000020, .then = .{ .instruction = .gcsrwr } }, + .{ .then = .{ .instruction = .gcsrxchg } }, + } } }, + } } }, + .{ .value = 0x14000000, .then = .{ .mask = 0x02000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .instruction = .@"cu32i.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"lu12i.w" } }, + } } }, + .{ .value = 0x0c000000, .then = .{ .mask = 0x03f00000, .cases = .{ + .{ .value = 0x00200000, .then = .{ .mask = 0x000f8018, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"fcmp.caf.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"fcmp.ceq.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"fcmp.cle.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"fcmp.clt.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"fcmp.cne.d" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"fcmp.cor.d" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"fcmp.cueq.d" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"fcmp.cule.d" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"fcmp.cult.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"fcmp.cun.d" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"fcmp.cune.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"fcmp.saf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"fcmp.seq.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"fcmp.sle.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"fcmp.slt.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"fcmp.sne.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"fcmp.sor.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"fcmp.sueq.d" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"fcmp.sule.d" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"fcmp.sult.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"fcmp.sun.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"fcmp.sune.d" } }, + } } }, + .{ .value = 0x00100000, .then = .{ .mask = 0x000f8018, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"fcmp.caf.s" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"fcmp.ceq.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"fcmp.cle.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"fcmp.clt.s" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"fcmp.cne.s" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"fcmp.cor.s" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"fcmp.cueq.s" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"fcmp.cule.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"fcmp.cult.s" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"fcmp.cun.s" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"fcmp.cune.s" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"fcmp.saf.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"fcmp.seq.s" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"fcmp.sle.s" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"fcmp.slt.s" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"fcmp.sne.s" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"fcmp.sor.s" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"fcmp.sueq.s" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"fcmp.sule.s" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"fcmp.sult.s" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"fcmp.sun.s" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"fcmp.sune.s" } }, + } } }, + .{ .value = 0x01000000, .then = .{ .instruction = .fsel } }, + .{ .value = 0x01100000, .then = .{ .instruction = .@"vbitsel.v" } }, + .{ .value = 0x00600000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vfcmp.caf.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcmp.ceq.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfcmp.cle.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfcmp.clt.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"vfcmp.cne.d" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"vfcmp.cor.d" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"vfcmp.cueq.d" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"vfcmp.cule.d" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"vfcmp.cult.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"vfcmp.cun.d" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"vfcmp.cune.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfcmp.saf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcmp.seq.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vfcmp.sle.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vfcmp.slt.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"vfcmp.sne.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"vfcmp.sor.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"vfcmp.sueq.d" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"vfcmp.sule.d" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"vfcmp.sult.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"vfcmp.sun.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"vfcmp.sune.d" } }, + } } }, + .{ .value = 0x00500000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vfcmp.caf.s" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcmp.ceq.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfcmp.cle.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfcmp.clt.s" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"vfcmp.cne.s" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"vfcmp.cor.s" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"vfcmp.cueq.s" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"vfcmp.cule.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"vfcmp.cult.s" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"vfcmp.cun.s" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"vfcmp.cune.s" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfcmp.saf.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcmp.seq.s" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vfcmp.sle.s" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vfcmp.slt.s" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"vfcmp.sne.s" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"vfcmp.sor.s" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"vfcmp.sueq.s" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"vfcmp.sule.s" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"vfcmp.sult.s" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"vfcmp.sun.s" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"vfcmp.sune.s" } }, + } } }, + .{ .value = 0x01500000, .then = .{ .instruction = .@"vshuf.b" } }, + .{ .value = 0x01200000, .then = .{ .instruction = .@"xvbitsel.v" } }, + .{ .value = 0x00a00000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvfcmp.caf.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcmp.ceq.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfcmp.cle.d" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfcmp.clt.d" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"xvfcmp.cne.d" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"xvfcmp.cor.d" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"xvfcmp.cueq.d" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"xvfcmp.cule.d" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"xvfcmp.cult.d" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"xvfcmp.cun.d" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"xvfcmp.cune.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfcmp.saf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcmp.seq.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfcmp.sle.d" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvfcmp.slt.d" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"xvfcmp.sne.d" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"xvfcmp.sor.d" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"xvfcmp.sueq.d" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"xvfcmp.sule.d" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"xvfcmp.sult.d" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"xvfcmp.sun.d" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"xvfcmp.sune.d" } }, + } } }, + .{ .value = 0x00900000, .then = .{ .mask = 0x000f8000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvfcmp.caf.s" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcmp.ceq.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfcmp.cle.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfcmp.clt.s" } }, + .{ .value = 0x00080000, .then = .{ .instruction = .@"xvfcmp.cne.s" } }, + .{ .value = 0x000a0000, .then = .{ .instruction = .@"xvfcmp.cor.s" } }, + .{ .value = 0x00060000, .then = .{ .instruction = .@"xvfcmp.cueq.s" } }, + .{ .value = 0x00070000, .then = .{ .instruction = .@"xvfcmp.cule.s" } }, + .{ .value = 0x00050000, .then = .{ .instruction = .@"xvfcmp.cult.s" } }, + .{ .value = 0x00040000, .then = .{ .instruction = .@"xvfcmp.cun.s" } }, + .{ .value = 0x000c0000, .then = .{ .instruction = .@"xvfcmp.cune.s" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfcmp.saf.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcmp.seq.s" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfcmp.sle.s" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvfcmp.slt.s" } }, + .{ .value = 0x00088000, .then = .{ .instruction = .@"xvfcmp.sne.s" } }, + .{ .value = 0x000a8000, .then = .{ .instruction = .@"xvfcmp.sor.s" } }, + .{ .value = 0x00068000, .then = .{ .instruction = .@"xvfcmp.sueq.s" } }, + .{ .value = 0x00078000, .then = .{ .instruction = .@"xvfcmp.sule.s" } }, + .{ .value = 0x00058000, .then = .{ .instruction = .@"xvfcmp.sult.s" } }, + .{ .value = 0x00048000, .then = .{ .instruction = .@"xvfcmp.sun.s" } }, + .{ .value = 0x000c8000, .then = .{ .instruction = .@"xvfcmp.sune.s" } }, + } } }, + .{ .value = 0x01600000, .then = .{ .instruction = .@"xvshuf.b" } }, + } } }, + .{ .value = 0x28000000, .then = .{ .mask = 0x03c00000, .cases = .{ + .{ .value = 0x03800000, .then = .{ .instruction = .@"fld.d" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"fld.s" } }, + .{ .value = 0x03c00000, .then = .{ .instruction = .@"fst.d" } }, + .{ .value = 0x03400000, .then = .{ .instruction = .@"fst.s" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ld.b" } }, + .{ .value = 0x02000000, .then = .{ .instruction = .@"ld.bu" } }, + .{ .value = 0x00c00000, .then = .{ .instruction = .@"ld.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"ld.h" } }, + .{ .value = 0x02400000, .then = .{ .instruction = .@"ld.hu" } }, + .{ .value = 0x00800000, .then = .{ .instruction = .@"ld.w" } }, + .{ .value = 0x02800000, .then = .{ .instruction = .@"ld.wu" } }, + .{ .value = 0x02c00000, .then = .{ .instruction = .preld } }, + .{ .value = 0x01000000, .then = .{ .instruction = .@"st.b" } }, + .{ .value = 0x01c00000, .then = .{ .instruction = .@"st.d" } }, + .{ .value = 0x01400000, .then = .{ .instruction = .@"st.h" } }, + .{ .value = 0x01800000, .then = .{ .instruction = .@"st.w" } }, + } } }, + .{ .value = 0x08000000, .then = .{ .mask = 0x03f00000, .cases = .{ + .{ .value = 0x00200000, .then = .{ .instruction = .@"fmadd.d" } }, + .{ .value = 0x00100000, .then = .{ .instruction = .@"fmadd.s" } }, + .{ .value = 0x00600000, .then = .{ .instruction = .@"fmsub.d" } }, + .{ .value = 0x00500000, .then = .{ .instruction = .@"fmsub.s" } }, + .{ .value = 0x00a00000, .then = .{ .instruction = .@"fnmadd.d" } }, + .{ .value = 0x00900000, .then = .{ .instruction = .@"fnmadd.s" } }, + .{ .value = 0x00e00000, .then = .{ .instruction = .@"fnmsub.d" } }, + .{ .value = 0x00d00000, .then = .{ .instruction = .@"fnmsub.s" } }, + .{ .value = 0x01200000, .then = .{ .instruction = .@"vfmadd.d" } }, + .{ .value = 0x01100000, .then = .{ .instruction = .@"vfmadd.s" } }, + .{ .value = 0x01600000, .then = .{ .instruction = .@"vfmsub.d" } }, + .{ .value = 0x01500000, .then = .{ .instruction = .@"vfmsub.s" } }, + .{ .value = 0x01a00000, .then = .{ .instruction = .@"vfnmadd.d" } }, + .{ .value = 0x01900000, .then = .{ .instruction = .@"vfnmadd.s" } }, + .{ .value = 0x01e00000, .then = .{ .instruction = .@"vfnmsub.d" } }, + .{ .value = 0x01d00000, .then = .{ .instruction = .@"vfnmsub.s" } }, + .{ .value = 0x02200000, .then = .{ .instruction = .@"xvfmadd.d" } }, + .{ .value = 0x02100000, .then = .{ .instruction = .@"xvfmadd.s" } }, + .{ .value = 0x02600000, .then = .{ .instruction = .@"xvfmsub.d" } }, + .{ .value = 0x02500000, .then = .{ .instruction = .@"xvfmsub.s" } }, + .{ .value = 0x02a00000, .then = .{ .instruction = .@"xvfnmadd.d" } }, + .{ .value = 0x02900000, .then = .{ .instruction = .@"xvfnmadd.s" } }, + .{ .value = 0x02e00000, .then = .{ .instruction = .@"xvfnmsub.d" } }, + .{ .value = 0x02d00000, .then = .{ .instruction = .@"xvfnmsub.s" } }, + } } }, + .{ .value = 0x4c000000, .then = .{ .instruction = .jirl } }, + .{ .value = 0x2c000000, .then = .{ .mask = 0x03c00000, .cases = .{ + .{ .value = 0x02800000, .then = .{ .instruction = .@"ldl.d" } }, + .{ .value = 0x02000000, .then = .{ .instruction = .@"ldl.w" } }, + .{ .value = 0x02c00000, .then = .{ .instruction = .@"ldr.d" } }, + .{ .value = 0x02400000, .then = .{ .instruction = .@"ldr.w" } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"stl.d" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"stl.w" } }, + .{ .value = 0x03c00000, .then = .{ .instruction = .@"str.d" } }, + .{ .value = 0x03400000, .then = .{ .instruction = .@"str.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .vld } }, + .{ .value = 0x00400000, .then = .{ .instruction = .vst } }, + .{ .value = 0x00800000, .then = .{ .instruction = .xvld } }, + .{ .value = 0x00c00000, .then = .{ .instruction = .xvst } }, + } } }, + .{ .value = 0x24000000, .then = .{ .mask = 0x03000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .instruction = .@"ldox4.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ldox4.w" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"stox4.d" } }, + .{ .value = 0x01000000, .then = .{ .instruction = .@"stox4.w" } }, + } } }, + .{ .value = 0x20000000, .then = .{ .mask = 0x03000000, .cases = .{ + .{ .value = 0x02000000, .then = .{ .instruction = .@"ll.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"ll.w" } }, + .{ .value = 0x03000000, .then = .{ .instruction = .@"sc.d" } }, + .{ .value = 0x01000000, .then = .{ .instruction = .@"sc.w" } }, + } } }, + .{ .value = 0x1c000000, .then = .{ .mask = 0x02000000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .pcaddu12i } }, + .{ .value = 0x02000000, .then = .{ .instruction = .pcaddu18i } }, + } } }, + .{ .value = 0x18000000, .then = .{ .mask = 0x02000000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .pcaddu2i } }, + .{ .value = 0x02000000, .then = .{ .instruction = .pcalau12i } }, + } } }, + .{ .value = 0x70000000, .then = .{ .mask = 0x03fc0000, .cases = .{ + .{ .value = 0x00600000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vabsd.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vabsd.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vabsd.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vabsd.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vabsd.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vabsd.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vabsd.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vabsd.wu" } }, + } } }, + .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vadd.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslt.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vslt.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslt.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslt.wu" } }, + } } }, + .{ .value = 0x012c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vadd.q" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsigncov.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsigncov.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsigncov.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsigncov.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsub.q" } }, + } } }, + .{ .value = 0x005c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vadda.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vadda.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vadda.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vadda.w" } }, + } } }, + .{ .value = 0x02880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddi.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddi.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddi.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddi.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslti.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vslti.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslti.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslti.wu" } }, + } } }, + .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.h" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.hu" } }, + } } }, + .{ .value = 0x003c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwev.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwev.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwev.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwev.w.hu.h" } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwod.w.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwev.w.h" } }, + } } }, + .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vaddwod.w.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwev.w.hu" } }, + } } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vaddwod.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vaddwod.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vaddwod.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x01240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vand.v" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vnor.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vor.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vxor.v" } }, + } } }, + .{ .value = 0x03d00000, .then = .{ .instruction = .@"vandi.b" } }, + .{ .value = 0x01280000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vandn.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfrstp.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vfrstp.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vorn.v" } }, + } } }, + .{ .value = 0x00640000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vavg.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vavg.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vavg.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vavg.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vavg.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vavg.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vavg.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vavg.wu" } }, + } } }, + .{ .value = 0x00680000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vavgr.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vavgr.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vavgr.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vavgr.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vavgr.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vavgr.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vavgr.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vavgr.wu" } }, + } } }, + .{ .value = 0x010c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitclr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vbitclr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitclr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitclr.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vbitset.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vbitset.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vbitset.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vbitset.w" } }, + } } }, + .{ .value = 0x03100000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitclri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitclri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitclri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitclri.d" } }, + } } }, + .{ .value = 0x01100000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitrev.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vbitrev.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitrev.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitrev.w" } }, + } } }, + .{ .value = 0x03180000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitrevi.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitrevi.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitrevi.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitrevi.d" } }, + } } }, + .{ .value = 0x03c40000, .then = .{ .instruction = .@"vbitseli.b" } }, + .{ .value = 0x03140000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vbitseti.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vbitseti.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vbitseti.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vbitseti.d" } }, + } } }, + .{ .value = 0x028c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vbsll.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vbsrl.v" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubi.wu" } }, + } } }, + .{ .value = 0x029c0000, .then = .{ .mask = 0x0003fc00, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vclo.b" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"vclo.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"vclo.h" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"vclo.w" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"vclz.b" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"vclz.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"vclz.h" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"vclz.w" } }, + .{ .value = 0x0002e800, .then = .{ .instruction = .@"vexth.d.w" } }, + .{ .value = 0x0002f800, .then = .{ .instruction = .@"vexth.du.wu" } }, + .{ .value = 0x0002e000, .then = .{ .instruction = .@"vexth.h.b" } }, + .{ .value = 0x0002f000, .then = .{ .instruction = .@"vexth.hu.bu" } }, + .{ .value = 0x0002ec00, .then = .{ .instruction = .@"vexth.q.d" } }, + .{ .value = 0x0002fc00, .then = .{ .instruction = .@"vexth.qu.du" } }, + .{ .value = 0x0002e400, .then = .{ .instruction = .@"vexth.w.h" } }, + .{ .value = 0x0002f400, .then = .{ .instruction = .@"vexth.wu.hu" } }, + .{ .value = 0x0000d800, .then = .{ .instruction = .@"vfclass.d" } }, + .{ .value = 0x0000d400, .then = .{ .instruction = .@"vfclass.s" } }, + .{ .value = 0x0001f400, .then = .{ .instruction = .@"vfcvth.d.s" } }, + .{ .value = 0x0001ec00, .then = .{ .instruction = .@"vfcvth.s.h" } }, + .{ .value = 0x0001f000, .then = .{ .instruction = .@"vfcvtl.d.s" } }, + .{ .value = 0x0001e800, .then = .{ .instruction = .@"vfcvtl.s.h" } }, + .{ .value = 0x00020800, .then = .{ .instruction = .@"vffint.d.l" } }, + .{ .value = 0x00020c00, .then = .{ .instruction = .@"vffint.d.lu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vffint.s.w" } }, + .{ .value = 0x00020400, .then = .{ .instruction = .@"vffint.s.wu" } }, + .{ .value = 0x00021400, .then = .{ .instruction = .@"vffinth.d.w" } }, + .{ .value = 0x00021000, .then = .{ .instruction = .@"vffintl.d.w" } }, + .{ .value = 0x0000c800, .then = .{ .instruction = .@"vflogb.d" } }, + .{ .value = 0x0000c400, .then = .{ .instruction = .@"vflogb.s" } }, + .{ .value = 0x0000f800, .then = .{ .instruction = .@"vfrecip.d" } }, + .{ .value = 0x0000f400, .then = .{ .instruction = .@"vfrecip.s" } }, + .{ .value = 0x00011800, .then = .{ .instruction = .@"vfrecipe.d" } }, + .{ .value = 0x00011400, .then = .{ .instruction = .@"vfrecipe.s" } }, + .{ .value = 0x00013800, .then = .{ .instruction = .@"vfrint.d" } }, + .{ .value = 0x00013400, .then = .{ .instruction = .@"vfrint.s" } }, + .{ .value = 0x00014800, .then = .{ .instruction = .@"vfrintrm.d" } }, + .{ .value = 0x00014400, .then = .{ .instruction = .@"vfrintrm.s" } }, + .{ .value = 0x00017800, .then = .{ .instruction = .@"vfrintrne.d" } }, + .{ .value = 0x00017400, .then = .{ .instruction = .@"vfrintrne.s" } }, + .{ .value = 0x00015800, .then = .{ .instruction = .@"vfrintrp.d" } }, + .{ .value = 0x00015400, .then = .{ .instruction = .@"vfrintrp.s" } }, + .{ .value = 0x00016800, .then = .{ .instruction = .@"vfrintrz.d" } }, + .{ .value = 0x00016400, .then = .{ .instruction = .@"vfrintrz.s" } }, + .{ .value = 0x00010800, .then = .{ .instruction = .@"vfrsqrt.d" } }, + .{ .value = 0x00010400, .then = .{ .instruction = .@"vfrsqrt.s" } }, + .{ .value = 0x00012800, .then = .{ .instruction = .@"vfrsqrte.d" } }, + .{ .value = 0x00012400, .then = .{ .instruction = .@"vfrsqrte.s" } }, + .{ .value = 0x0000e800, .then = .{ .instruction = .@"vfsqrt.d" } }, + .{ .value = 0x0000e400, .then = .{ .instruction = .@"vfsqrt.s" } }, + .{ .value = 0x00023400, .then = .{ .instruction = .@"vftint.l.d" } }, + .{ .value = 0x00025c00, .then = .{ .instruction = .@"vftint.lu.d" } }, + .{ .value = 0x00023000, .then = .{ .instruction = .@"vftint.w.s" } }, + .{ .value = 0x00025800, .then = .{ .instruction = .@"vftint.wu.s" } }, + .{ .value = 0x00028400, .then = .{ .instruction = .@"vftinth.l.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vftintl.l.s" } }, + .{ .value = 0x00023c00, .then = .{ .instruction = .@"vftintrm.l.d" } }, + .{ .value = 0x00023800, .then = .{ .instruction = .@"vftintrm.w.s" } }, + .{ .value = 0x00028c00, .then = .{ .instruction = .@"vftintrmh.l.s" } }, + .{ .value = 0x00028800, .then = .{ .instruction = .@"vftintrml.l.s" } }, + .{ .value = 0x00025400, .then = .{ .instruction = .@"vftintrne.l.d" } }, + .{ .value = 0x00025000, .then = .{ .instruction = .@"vftintrne.w.s" } }, + .{ .value = 0x0002a400, .then = .{ .instruction = .@"vftintrneh.l.s" } }, + .{ .value = 0x0002a000, .then = .{ .instruction = .@"vftintrnel.l.s" } }, + .{ .value = 0x00024400, .then = .{ .instruction = .@"vftintrp.l.d" } }, + .{ .value = 0x00024000, .then = .{ .instruction = .@"vftintrp.w.s" } }, + .{ .value = 0x00029400, .then = .{ .instruction = .@"vftintrph.l.s" } }, + .{ .value = 0x00029000, .then = .{ .instruction = .@"vftintrpl.l.s" } }, + .{ .value = 0x00024c00, .then = .{ .instruction = .@"vftintrz.l.d" } }, + .{ .value = 0x00027400, .then = .{ .instruction = .@"vftintrz.lu.d" } }, + .{ .value = 0x00024800, .then = .{ .instruction = .@"vftintrz.w.s" } }, + .{ .value = 0x00027000, .then = .{ .instruction = .@"vftintrz.wu.s" } }, + .{ .value = 0x00029c00, .then = .{ .instruction = .@"vftintrzh.l.s" } }, + .{ .value = 0x00029800, .then = .{ .instruction = .@"vftintrzl.l.s" } }, + .{ .value = 0x00005000, .then = .{ .instruction = .@"vmskgez.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vmskltz.b" } }, + .{ .value = 0x00004c00, .then = .{ .instruction = .@"vmskltz.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"vmskltz.h" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"vmskltz.w" } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"vmsknz.b" } }, + .{ .value = 0x00003000, .then = .{ .instruction = .@"vneg.b" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"vneg.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"vneg.h" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"vneg.w" } }, + .{ .value = 0x00002000, .then = .{ .instruction = .@"vpcnt.b" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"vpcnt.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"vpcnt.h" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"vpcnt.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vreplgr2vr.b" } }, + .{ .value = 0x00030c00, .then = .{ .instruction = .@"vreplgr2vr.d" } }, + .{ .value = 0x00030400, .then = .{ .instruction = .@"vreplgr2vr.h" } }, + .{ .value = 0x00030800, .then = .{ .instruction = .@"vreplgr2vr.w" } }, + .{ .value = 0x0000b000, .then = .{ .instruction = .@"vsetallnez.b" } }, + .{ .value = 0x0000bc00, .then = .{ .instruction = .@"vsetallnez.d" } }, + .{ .value = 0x0000b400, .then = .{ .instruction = .@"vsetallnez.h" } }, + .{ .value = 0x0000b800, .then = .{ .instruction = .@"vsetallnez.w" } }, + .{ .value = 0x0000a000, .then = .{ .instruction = .@"vsetanyeqz.b" } }, + .{ .value = 0x0000ac00, .then = .{ .instruction = .@"vsetanyeqz.d" } }, + .{ .value = 0x0000a400, .then = .{ .instruction = .@"vsetanyeqz.h" } }, + .{ .value = 0x0000a800, .then = .{ .instruction = .@"vsetanyeqz.w" } }, + .{ .value = 0x00009800, .then = .{ .instruction = .@"vseteqz.v" } }, + .{ .value = 0x00009c00, .then = .{ .instruction = .@"vsetnez.v" } }, + } } }, + .{ .value = 0x00e00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vdiv.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vdiv.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vdiv.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vdiv.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmod.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmod.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmod.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmod.w" } }, + } } }, + .{ .value = 0x00e40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vdiv.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vdiv.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vdiv.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vdiv.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmod.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmod.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmod.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmod.wu" } }, + } } }, + .{ .value = 0x03080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vextl.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsllwil.d.w" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsllwil.h.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsllwil.w.h" } }, + } } }, + } } }, + .{ .value = 0x030c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vextl.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsllwil.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsllwil.hu.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsllwil.wu.hu" } }, + } } }, + } } }, + .{ .value = 0x038c0000, .then = .{ .instruction = .@"vextrins.b" } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"vextrins.d" } }, + .{ .value = 0x03880000, .then = .{ .instruction = .@"vextrins.h" } }, + .{ .value = 0x03840000, .then = .{ .instruction = .@"vextrins.w" } }, + .{ .value = 0x01300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfadd.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfsub.s" } }, + } } }, + .{ .value = 0x01440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfcvt.h.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfcvt.s.d" } }, + } } }, + .{ .value = 0x01380000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfdiv.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfdiv.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmul.s" } }, + } } }, + .{ .value = 0x01480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vffint.s.l" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vftint.w.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vftintrm.w.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vftintrne.w.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vftintrp.w.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vftintrz.w.d" } }, + } } }, + .{ .value = 0x013c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmax.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfmin.s" } }, + } } }, + .{ .value = 0x01400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vfmaxa.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vfmaxa.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vfmina.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfmina.s" } }, + } } }, + .{ .value = 0x02980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vfrstpi.b" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vfrstpi.h" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmepatmsk.v" } }, + } } }, + .{ .value = 0x00540000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vhaddw.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vhaddw.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vhaddw.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vhaddw.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vhsubw.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vhsubw.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vhsubw.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vhsubw.w.h" } }, + } } }, + .{ .value = 0x00580000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vhaddw.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vhaddw.hu.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vhaddw.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vhaddw.wu.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vhsubw.du.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vhsubw.hu.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vhsubw.qu.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vhsubw.wu.hu" } }, + } } }, + .{ .value = 0x011c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vilvh.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vilvh.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vilvh.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vilvh.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vpickev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vpickev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vpickev.w" } }, + } } }, + .{ .value = 0x01180000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vilvl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vilvl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vilvl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vilvl.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpackod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vpackod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vpackod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vpackod.w" } }, + } } }, + .{ .value = 0x02e80000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vinsgr2vr.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vinsgr2vr.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vinsgr2vr.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vinsgr2vr.h" } }, + } } }, + } } }, + .{ .value = 0x03e00000, .then = .{ .instruction = .vldi } }, + .{ .value = 0x00a80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmadd.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmadd.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmadd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmsub.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmsub.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmsub.w" } }, + } } }, + .{ .value = 0x00ac0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.h" } }, + } } }, + .{ .value = 0x00b40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.hu" } }, + } } }, + .{ .value = 0x00bc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaddwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaddwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaddwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaddwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmaddwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmaddwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmaddwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x00700000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmax.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmax.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmax.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmin.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmin.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmin.w" } }, + } } }, + .{ .value = 0x00740000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmax.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmax.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmax.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmax.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmin.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmin.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmin.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmin.wu" } }, + } } }, + .{ .value = 0x02900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaxi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaxi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaxi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaxi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmini.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmini.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmini.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmini.w" } }, + } } }, + .{ .value = 0x02940000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmaxi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmaxi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmaxi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmaxi.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmini.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmini.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmini.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmini.wu" } }, + } } }, + .{ .value = 0x00840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmuh.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmuh.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmuh.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmuh.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmul.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmul.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmul.w" } }, + } } }, + .{ .value = 0x00880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmuh.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmuh.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmuh.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmuh.wu" } }, + } } }, + .{ .value = 0x00900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.h" } }, + } } }, + .{ .value = 0x00980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.hu" } }, + } } }, + .{ .value = 0x00a00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vmulwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vmulwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vmulwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vmulwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vmulwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vmulwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vmulwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vmulwod.w.hu.h" } }, + } } }, + .{ .value = 0x03dc0000, .then = .{ .instruction = .@"vnori.b" } }, + .{ .value = 0x03d40000, .then = .{ .instruction = .@"vori.b" } }, + .{ .value = 0x01140000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vpackev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpackev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vpackev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vpackev.w" } }, + } } }, + .{ .value = 0x03e40000, .then = .{ .instruction = .@"vpermi.w" } }, + .{ .value = 0x01200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vpickod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vpickod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vpickod.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vreplve.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vreplve.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vreplve.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vreplve.w" } }, + } } }, + .{ .value = 0x02ec0000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickve2gr.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vpickve2gr.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.h" } }, + } } }, + } } }, + .{ .value = 0x02f00000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vpickve2gr.bu" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vpickve2gr.du" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.wu" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vpickve2gr.hu" } }, + } } }, + } } }, + .{ .value = 0x02f40000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vreplvei.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"vreplvei.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vreplvei.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vreplvei.h" } }, + } } }, + } } }, + .{ .value = 0x00ec0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vrotr.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vrotr.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vrotr.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vrotr.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsra.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsra.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsra.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsra.w" } }, + } } }, + .{ .value = 0x02a00000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vrotri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vrotri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vrotri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vrotri.d" } }, + } } }, + .{ .value = 0x00440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsadd.w" } }, + } } }, + .{ .value = 0x00480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsadd.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsadd.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsadd.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsadd.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssub.w" } }, + } } }, + .{ .value = 0x03240000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsat.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsat.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsat.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsat.d" } }, + } } }, + .{ .value = 0x03280000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsat.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsat.hu" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsat.wu" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsat.du" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vseq.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vseq.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vseq.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vseq.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsle.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsle.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsle.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsle.w" } }, + } } }, + .{ .value = 0x02800000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vseqi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vseqi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vseqi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vseqi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vslei.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vslei.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vslei.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vslei.w" } }, + } } }, + .{ .value = 0x01780000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"vshuf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vshuf.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vshuf.w" } }, + } } }, + .{ .value = 0x03900000, .then = .{ .instruction = .@"vshuf4i.b" } }, + .{ .value = 0x039c0000, .then = .{ .instruction = .@"vshuf4i.d" } }, + .{ .value = 0x03940000, .then = .{ .instruction = .@"vshuf4i.h" } }, + .{ .value = 0x03980000, .then = .{ .instruction = .@"vshuf4i.w" } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsle.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsle.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsle.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsle.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vslt.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vslt.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vslt.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vslt.w" } }, + } } }, + .{ .value = 0x02840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslei.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vslei.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslei.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslei.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vslti.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vslti.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vslti.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vslti.w" } }, + } } }, + .{ .value = 0x00e80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsll.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsll.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsll.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsll.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrl.w" } }, + } } }, + .{ .value = 0x032c0000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vslli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vslli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vslli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vslli.d" } }, + } } }, + .{ .value = 0x03340000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrai.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrai.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrai.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrai.d" } }, + } } }, + .{ .value = 0x00f40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrln.w.d" } }, + } } }, + .{ .value = 0x03580000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrani.d.q" } }, + } } }, + .{ .value = 0x00f00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrar.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrar.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrar.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrar.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrlr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlr.w" } }, + } } }, + .{ .value = 0x02a80000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrari.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrari.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrari.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrari.d" } }, + } } }, + .{ .value = 0x00f80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vsrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vsrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vsrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsrlrn.w.d" } }, + } } }, + .{ .value = 0x035c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrarni.d.q" } }, + } } }, + .{ .value = 0x03300000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrli.d" } }, + } } }, + .{ .value = 0x03400000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrlni.d.q" } }, + } } }, + .{ .value = 0x02a40000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"vsrlri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlri.d" } }, + } } }, + .{ .value = 0x03440000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vsrlrni.d.q" } }, + } } }, + .{ .value = 0x00fc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrln.w.d" } }, + } } }, + .{ .value = 0x01040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssran.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssran.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssran.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrln.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrln.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrln.wu.d" } }, + } } }, + .{ .value = 0x03600000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrani.d.q" } }, + } } }, + .{ .value = 0x03640000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrani.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrani.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrani.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrani.du.q" } }, + } } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrlrn.w.d" } }, + } } }, + .{ .value = 0x01080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"vssrarn.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"vssrarn.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"vssrarn.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrn.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrn.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssrlrn.wu.d" } }, + } } }, + .{ .value = 0x03680000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrarni.d.q" } }, + } } }, + .{ .value = 0x036c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrarni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrarni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrarni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrarni.du.q" } }, + } } }, + .{ .value = 0x03480000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlni.d.q" } }, + } } }, + .{ .value = 0x034c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlni.du.q" } }, + } } }, + .{ .value = 0x03500000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlrni.d.q" } }, + } } }, + .{ .value = 0x03540000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssrlrni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssrlrni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssrlrni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"vssrlrni.du.q" } }, + } } }, + .{ .value = 0x004c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vssub.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vssub.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vssub.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vssub.wu" } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsub.w" } }, + } } }, + .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwod.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwod.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwod.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwod.w.h" } }, + } } }, + .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"vsubwod.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"vsubwod.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"vsubwod.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"vsubwod.w.hu" } }, + } } }, + .{ .value = 0x03d80000, .then = .{ .instruction = .@"vxori.b" } }, + } } }, + .{ .value = 0x74000000, .then = .{ .mask = 0x03fc0000, .cases = .{ + .{ .value = 0x029c0000, .then = .{ .mask = 0x0003fc00, .cases = .{ + .{ .value = 0x00031800, .then = .{ .instruction = .@"vext2xv.d.b" } }, + .{ .value = 0x00032000, .then = .{ .instruction = .@"vext2xv.d.h" } }, + .{ .value = 0x00032400, .then = .{ .instruction = .@"vext2xv.d.w" } }, + .{ .value = 0x00033000, .then = .{ .instruction = .@"vext2xv.du.bu" } }, + .{ .value = 0x00033800, .then = .{ .instruction = .@"vext2xv.du.hu" } }, + .{ .value = 0x00033c00, .then = .{ .instruction = .@"vext2xv.du.wu" } }, + .{ .value = 0x00031000, .then = .{ .instruction = .@"vext2xv.h.b" } }, + .{ .value = 0x00032800, .then = .{ .instruction = .@"vext2xv.hu.bu" } }, + .{ .value = 0x00031400, .then = .{ .instruction = .@"vext2xv.w.b" } }, + .{ .value = 0x00031c00, .then = .{ .instruction = .@"vext2xv.w.h" } }, + .{ .value = 0x00032c00, .then = .{ .instruction = .@"vext2xv.wu.bu" } }, + .{ .value = 0x00033400, .then = .{ .instruction = .@"vext2xv.wu.hu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvclo.b" } }, + .{ .value = 0x00000c00, .then = .{ .instruction = .@"xvclo.d" } }, + .{ .value = 0x00000400, .then = .{ .instruction = .@"xvclo.h" } }, + .{ .value = 0x00000800, .then = .{ .instruction = .@"xvclo.w" } }, + .{ .value = 0x00001000, .then = .{ .instruction = .@"xvclz.b" } }, + .{ .value = 0x00001c00, .then = .{ .instruction = .@"xvclz.d" } }, + .{ .value = 0x00001400, .then = .{ .instruction = .@"xvclz.h" } }, + .{ .value = 0x00001800, .then = .{ .instruction = .@"xvclz.w" } }, + .{ .value = 0x0002e800, .then = .{ .instruction = .@"xvexth.d.w" } }, + .{ .value = 0x0002f800, .then = .{ .instruction = .@"xvexth.du.wu" } }, + .{ .value = 0x0002e000, .then = .{ .instruction = .@"xvexth.h.b" } }, + .{ .value = 0x0002f000, .then = .{ .instruction = .@"xvexth.hu.bu" } }, + .{ .value = 0x0002ec00, .then = .{ .instruction = .@"xvexth.q.d" } }, + .{ .value = 0x0002fc00, .then = .{ .instruction = .@"xvexth.qu.du" } }, + .{ .value = 0x0002e400, .then = .{ .instruction = .@"xvexth.w.h" } }, + .{ .value = 0x0002f400, .then = .{ .instruction = .@"xvexth.wu.hu" } }, + .{ .value = 0x0000d800, .then = .{ .instruction = .@"xvfclass.d" } }, + .{ .value = 0x0000d400, .then = .{ .instruction = .@"xvfclass.s" } }, + .{ .value = 0x0001f400, .then = .{ .instruction = .@"xvfcvth.d.s" } }, + .{ .value = 0x0001ec00, .then = .{ .instruction = .@"xvfcvth.s.h" } }, + .{ .value = 0x0001f000, .then = .{ .instruction = .@"xvfcvtl.d.s" } }, + .{ .value = 0x0001e800, .then = .{ .instruction = .@"xvfcvtl.s.h" } }, + .{ .value = 0x00020800, .then = .{ .instruction = .@"xvffint.d.l" } }, + .{ .value = 0x00020c00, .then = .{ .instruction = .@"xvffint.d.lu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvffint.s.w" } }, + .{ .value = 0x00020400, .then = .{ .instruction = .@"xvffint.s.wu" } }, + .{ .value = 0x00021400, .then = .{ .instruction = .@"xvffinth.d.w" } }, + .{ .value = 0x00021000, .then = .{ .instruction = .@"xvffintl.d.w" } }, + .{ .value = 0x0000c800, .then = .{ .instruction = .@"xvflogb.d" } }, + .{ .value = 0x0000c400, .then = .{ .instruction = .@"xvflogb.s" } }, + .{ .value = 0x0000f800, .then = .{ .instruction = .@"xvfrecip.d" } }, + .{ .value = 0x0000f400, .then = .{ .instruction = .@"xvfrecip.s" } }, + .{ .value = 0x00011800, .then = .{ .instruction = .@"xvfrecipe.d" } }, + .{ .value = 0x00011400, .then = .{ .instruction = .@"xvfrecipe.s" } }, + .{ .value = 0x00013800, .then = .{ .instruction = .@"xvfrint.d" } }, + .{ .value = 0x00013400, .then = .{ .instruction = .@"xvfrint.s" } }, + .{ .value = 0x00014800, .then = .{ .instruction = .@"xvfrintrm.d" } }, + .{ .value = 0x00014400, .then = .{ .instruction = .@"xvfrintrm.s" } }, + .{ .value = 0x00017800, .then = .{ .instruction = .@"xvfrintrne.d" } }, + .{ .value = 0x00017400, .then = .{ .instruction = .@"xvfrintrne.s" } }, + .{ .value = 0x00015800, .then = .{ .instruction = .@"xvfrintrp.d" } }, + .{ .value = 0x00015400, .then = .{ .instruction = .@"xvfrintrp.s" } }, + .{ .value = 0x00016800, .then = .{ .instruction = .@"xvfrintrz.d" } }, + .{ .value = 0x00016400, .then = .{ .instruction = .@"xvfrintrz.s" } }, + .{ .value = 0x00010800, .then = .{ .instruction = .@"xvfrsqrt.d" } }, + .{ .value = 0x00010400, .then = .{ .instruction = .@"xvfrsqrt.s" } }, + .{ .value = 0x00012800, .then = .{ .instruction = .@"xvfrsqrte.d" } }, + .{ .value = 0x00012400, .then = .{ .instruction = .@"xvfrsqrte.s" } }, + .{ .value = 0x0000e800, .then = .{ .instruction = .@"xvfsqrt.d" } }, + .{ .value = 0x0000e400, .then = .{ .instruction = .@"xvfsqrt.s" } }, + .{ .value = 0x00023400, .then = .{ .instruction = .@"xvftint.l.d" } }, + .{ .value = 0x00025c00, .then = .{ .instruction = .@"xvftint.lu.d" } }, + .{ .value = 0x00023000, .then = .{ .instruction = .@"xvftint.w.s" } }, + .{ .value = 0x00025800, .then = .{ .instruction = .@"xvftint.wu.s" } }, + .{ .value = 0x00028400, .then = .{ .instruction = .@"xvftinth.l.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvftintl.l.s" } }, + .{ .value = 0x00023c00, .then = .{ .instruction = .@"xvftintrm.l.d" } }, + .{ .value = 0x00023800, .then = .{ .instruction = .@"xvftintrm.w.s" } }, + .{ .value = 0x00028c00, .then = .{ .instruction = .@"xvftintrmh.l.s" } }, + .{ .value = 0x00028800, .then = .{ .instruction = .@"xvftintrml.l.s" } }, + .{ .value = 0x00025400, .then = .{ .instruction = .@"xvftintrne.l.d" } }, + .{ .value = 0x00025000, .then = .{ .instruction = .@"xvftintrne.w.s" } }, + .{ .value = 0x0002a400, .then = .{ .instruction = .@"xvftintrneh.l.s" } }, + .{ .value = 0x0002a000, .then = .{ .instruction = .@"xvftintrnel.l.s" } }, + .{ .value = 0x00024400, .then = .{ .instruction = .@"xvftintrp.l.d" } }, + .{ .value = 0x00024000, .then = .{ .instruction = .@"xvftintrp.w.s" } }, + .{ .value = 0x00029400, .then = .{ .instruction = .@"xvftintrph.l.s" } }, + .{ .value = 0x00029000, .then = .{ .instruction = .@"xvftintrpl.l.s" } }, + .{ .value = 0x00024c00, .then = .{ .instruction = .@"xvftintrz.l.d" } }, + .{ .value = 0x00027400, .then = .{ .instruction = .@"xvftintrz.lu.d" } }, + .{ .value = 0x00024800, .then = .{ .instruction = .@"xvftintrz.w.s" } }, + .{ .value = 0x00027000, .then = .{ .instruction = .@"xvftintrz.wu.s" } }, + .{ .value = 0x00029c00, .then = .{ .instruction = .@"xvftintrzh.l.s" } }, + .{ .value = 0x00029800, .then = .{ .instruction = .@"xvftintrzl.l.s" } }, + .{ .value = 0x00005000, .then = .{ .instruction = .@"xvmskgez.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvmskltz.b" } }, + .{ .value = 0x00004c00, .then = .{ .instruction = .@"xvmskltz.d" } }, + .{ .value = 0x00004400, .then = .{ .instruction = .@"xvmskltz.h" } }, + .{ .value = 0x00004800, .then = .{ .instruction = .@"xvmskltz.w" } }, + .{ .value = 0x00006000, .then = .{ .instruction = .@"xvmsknz.b" } }, + .{ .value = 0x00003000, .then = .{ .instruction = .@"xvneg.b" } }, + .{ .value = 0x00003c00, .then = .{ .instruction = .@"xvneg.d" } }, + .{ .value = 0x00003400, .then = .{ .instruction = .@"xvneg.h" } }, + .{ .value = 0x00003800, .then = .{ .instruction = .@"xvneg.w" } }, + .{ .value = 0x00002000, .then = .{ .instruction = .@"xvpcnt.b" } }, + .{ .value = 0x00002c00, .then = .{ .instruction = .@"xvpcnt.d" } }, + .{ .value = 0x00002400, .then = .{ .instruction = .@"xvpcnt.h" } }, + .{ .value = 0x00002800, .then = .{ .instruction = .@"xvpcnt.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplgr2vr.b" } }, + .{ .value = 0x00030c00, .then = .{ .instruction = .@"xvreplgr2vr.d" } }, + .{ .value = 0x00030400, .then = .{ .instruction = .@"xvreplgr2vr.h" } }, + .{ .value = 0x00030800, .then = .{ .instruction = .@"xvreplgr2vr.w" } }, + .{ .value = 0x0000b000, .then = .{ .instruction = .@"xvsetallnez.b" } }, + .{ .value = 0x0000bc00, .then = .{ .instruction = .@"xvsetallnez.d" } }, + .{ .value = 0x0000b400, .then = .{ .instruction = .@"xvsetallnez.h" } }, + .{ .value = 0x0000b800, .then = .{ .instruction = .@"xvsetallnez.w" } }, + .{ .value = 0x0000a000, .then = .{ .instruction = .@"xvsetanyeqz.b" } }, + .{ .value = 0x0000ac00, .then = .{ .instruction = .@"xvsetanyeqz.d" } }, + .{ .value = 0x0000a400, .then = .{ .instruction = .@"xvsetanyeqz.h" } }, + .{ .value = 0x0000a800, .then = .{ .instruction = .@"xvsetanyeqz.w" } }, + .{ .value = 0x00009800, .then = .{ .instruction = .@"xvseteqz.v" } }, + .{ .value = 0x00009c00, .then = .{ .instruction = .@"xvsetnez.v" } }, + } } }, + .{ .value = 0x00600000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvabsd.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvabsd.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvabsd.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvabsd.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvabsd.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvabsd.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvabsd.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvabsd.wu" } }, + } } }, + .{ .value = 0x00080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvadd.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslt.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslt.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslt.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslt.wu" } }, + } } }, + .{ .value = 0x012c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvadd.q" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsigncov.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsigncov.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsigncov.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsigncov.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsub.q" } }, + } } }, + .{ .value = 0x005c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvadda.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvadda.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvadda.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvadda.w" } }, + } } }, + .{ .value = 0x02880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddi.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddi.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddi.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddi.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslti.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslti.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslti.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslti.wu" } }, + } } }, + .{ .value = 0x001c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.h" } }, + } } }, + .{ .value = 0x002c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.hu" } }, + } } }, + .{ .value = 0x003c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwev.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwev.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwev.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwev.w.hu.h" } }, + } } }, + .{ .value = 0x00200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwod.w.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwev.w.h" } }, + } } }, + .{ .value = 0x00300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvaddwod.w.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwev.w.hu" } }, + } } }, + .{ .value = 0x00400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvaddwod.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvaddwod.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvaddwod.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x01240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvand.v" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvnor.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvor.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvxor.v" } }, + } } }, + .{ .value = 0x03d00000, .then = .{ .instruction = .@"xvandi.b" } }, + .{ .value = 0x01280000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvandn.v" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfrstp.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvfrstp.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvorn.v" } }, + } } }, + .{ .value = 0x00640000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvavg.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvavg.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvavg.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvavg.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvavg.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvavg.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvavg.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvavg.wu" } }, + } } }, + .{ .value = 0x00680000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvavgr.b" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvavgr.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvavgr.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvavgr.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvavgr.h" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvavgr.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvavgr.w" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvavgr.wu" } }, + } } }, + .{ .value = 0x010c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitclr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvbitclr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitclr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitclr.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvbitset.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvbitset.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvbitset.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvbitset.w" } }, + } } }, + .{ .value = 0x03100000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitclri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitclri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitclri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitclri.d" } }, + } } }, + .{ .value = 0x01100000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitrev.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvbitrev.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitrev.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitrev.w" } }, + } } }, + .{ .value = 0x03180000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitrevi.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitrevi.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitrevi.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitrevi.d" } }, + } } }, + .{ .value = 0x03c40000, .then = .{ .instruction = .@"xvbitseli.b" } }, + .{ .value = 0x03140000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvbitseti.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvbitseti.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvbitseti.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvbitseti.d" } }, + } } }, + .{ .value = 0x028c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvbsll.v" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvbsrl.v" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubi.wu" } }, + } } }, + .{ .value = 0x00e00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvdiv.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvdiv.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvdiv.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvdiv.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmod.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmod.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmod.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmod.w" } }, + } } }, + .{ .value = 0x00e40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvdiv.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvdiv.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvdiv.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvdiv.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmod.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmod.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmod.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmod.wu" } }, + } } }, + .{ .value = 0x03080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvextl.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsllwil.d.w" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsllwil.h.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsllwil.w.h" } }, + } } }, + } } }, + .{ .value = 0x030c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvextl.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsllwil.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsllwil.hu.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsllwil.wu.hu" } }, + } } }, + } } }, + .{ .value = 0x038c0000, .then = .{ .instruction = .@"xvextrins.b" } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"xvextrins.d" } }, + .{ .value = 0x03880000, .then = .{ .instruction = .@"xvextrins.h" } }, + .{ .value = 0x03840000, .then = .{ .instruction = .@"xvextrins.w" } }, + .{ .value = 0x01300000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfadd.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfsub.s" } }, + } } }, + .{ .value = 0x01440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfcvt.h.s" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfcvt.s.d" } }, + } } }, + .{ .value = 0x01380000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfdiv.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfdiv.s" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmul.s" } }, + } } }, + .{ .value = 0x01480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvffint.s.l" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvftint.w.d" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvftintrm.w.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvftintrne.w.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvftintrp.w.d" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvftintrz.w.d" } }, + } } }, + .{ .value = 0x013c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmax.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfmin.s" } }, + } } }, + .{ .value = 0x01400000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvfmaxa.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvfmaxa.s" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvfmina.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfmina.s" } }, + } } }, + .{ .value = 0x02980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvfrstpi.b" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvfrstpi.h" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmepatmsk.v" } }, + } } }, + .{ .value = 0x00540000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvhaddw.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvhaddw.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvhaddw.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvhaddw.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvhsubw.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvhsubw.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvhsubw.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvhsubw.w.h" } }, + } } }, + .{ .value = 0x00580000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvhaddw.du.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvhaddw.hu.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvhaddw.qu.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvhaddw.wu.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvhsubw.du.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvhsubw.hu.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvhsubw.qu.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvhsubw.wu.hu" } }, + } } }, + .{ .value = 0x011c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvilvh.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvilvh.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvilvh.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvilvh.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvpickev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvpickev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvpickev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvpickev.w" } }, + } } }, + .{ .value = 0x01180000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvilvl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvilvl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvilvl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvilvl.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvpackod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvpackod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvpackod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvpackod.w" } }, + } } }, + .{ .value = 0x02e80000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvinsgr2vr.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvinsgr2vr.w" } }, + } } }, + .{ .value = 0x02fc0000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvinsve0.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvinsve0.w" } }, + } } }, + .{ .value = 0x03e00000, .then = .{ .instruction = .xvldi } }, + .{ .value = 0x00a80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmadd.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmadd.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmadd.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmadd.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmsub.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmsub.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmsub.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmsub.w" } }, + } } }, + .{ .value = 0x00ac0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.h" } }, + } } }, + .{ .value = 0x00b40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.hu" } }, + } } }, + .{ .value = 0x00bc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaddwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaddwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaddwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaddwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmaddwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmaddwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmaddwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmaddwod.w.hu.h" } }, + } } }, + .{ .value = 0x00700000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmax.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmax.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmax.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmax.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmin.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmin.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmin.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmin.w" } }, + } } }, + .{ .value = 0x00740000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmax.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmax.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmax.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmax.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmin.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmin.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmin.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmin.wu" } }, + } } }, + .{ .value = 0x02900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaxi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaxi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaxi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaxi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmini.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmini.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmini.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmini.w" } }, + } } }, + .{ .value = 0x02940000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmaxi.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmaxi.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmaxi.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmaxi.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmini.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmini.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmini.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmini.wu" } }, + } } }, + .{ .value = 0x00840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmuh.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmuh.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmuh.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmuh.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmul.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmul.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmul.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmul.w" } }, + } } }, + .{ .value = 0x00880000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmuh.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmuh.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmuh.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmuh.wu" } }, + } } }, + .{ .value = 0x00900000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.h" } }, + } } }, + .{ .value = 0x00980000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.hu" } }, + } } }, + .{ .value = 0x00a00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvmulwev.d.wu.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvmulwev.h.bu.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvmulwev.q.du.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvmulwev.w.hu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvmulwod.d.wu.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvmulwod.h.bu.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvmulwod.q.du.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvmulwod.w.hu.h" } }, + } } }, + .{ .value = 0x03dc0000, .then = .{ .instruction = .@"xvnori.b" } }, + .{ .value = 0x03d40000, .then = .{ .instruction = .@"xvori.b" } }, + .{ .value = 0x01140000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvpackev.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvpackev.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvpackev.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvpackev.w" } }, + } } }, + .{ .value = 0x017c0000, .then = .{ .instruction = .@"xvperm.w" } }, + .{ .value = 0x03e80000, .then = .{ .instruction = .@"xvpermi.d" } }, + .{ .value = 0x03ec0000, .then = .{ .instruction = .@"xvpermi.q" } }, + .{ .value = 0x03e40000, .then = .{ .instruction = .@"xvpermi.w" } }, + .{ .value = 0x01200000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvpickod.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvpickod.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvpickod.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvpickod.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvreplve.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvreplve.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvreplve.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplve.w" } }, + } } }, + .{ .value = 0x03000000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve.w" } }, + } } }, + .{ .value = 0x02ec0000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve2gr.d" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve2gr.w" } }, + } } }, + .{ .value = 0x02f00000, .then = .{ .mask = 0x0003e000, .cases = .{ + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvpickve2gr.du" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvpickve2gr.wu" } }, + } } }, + .{ .value = 0x02f40000, .then = .{ .mask = 0x0003c000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvrepl128vei.b" } }, + .{ .value = 0x0003c000, .then = .{ .mask = 0x00002000, .cases = .{ + .{ .value = 0x00002000, .then = .{ .mask = 0x00001000, .cases = .{ + .{ .value = 0x00001000, .then = .{ .instruction = .@"xvrepl128vei.d" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrepl128vei.w" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrepl128vei.h" } }, + } } }, + } } }, + .{ .value = 0x03040000, .then = .{ .mask = 0x0003fc00, .cases = .{ + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvreplve0.b" } }, + .{ .value = 0x0003e000, .then = .{ .instruction = .@"xvreplve0.d" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvreplve0.h" } }, + .{ .value = 0x0003f000, .then = .{ .instruction = .@"xvreplve0.q" } }, + .{ .value = 0x0003c000, .then = .{ .instruction = .@"xvreplve0.w" } }, + } } }, + .{ .value = 0x00ec0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvrotr.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvrotr.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvrotr.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvrotr.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsra.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsra.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsra.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsra.w" } }, + } } }, + .{ .value = 0x02a00000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvrotri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvrotri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvrotri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvrotri.d" } }, + } } }, + .{ .value = 0x00440000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsadd.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsadd.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsadd.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsadd.w" } }, + } } }, + .{ .value = 0x00480000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsadd.bu" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsadd.du" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsadd.hu" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsadd.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssub.w" } }, + } } }, + .{ .value = 0x03240000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsat.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsat.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsat.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsat.d" } }, + } } }, + .{ .value = 0x03280000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsat.bu" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsat.hu" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsat.wu" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsat.du" } }, + } } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvseq.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvseq.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvseq.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvseq.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsle.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsle.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsle.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsle.w" } }, + } } }, + .{ .value = 0x02800000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvseqi.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvseqi.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvseqi.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvseqi.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslei.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslei.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslei.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslei.w" } }, + } } }, + .{ .value = 0x01780000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvshuf.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvshuf.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvshuf.w" } }, + } } }, + .{ .value = 0x03900000, .then = .{ .instruction = .@"xvshuf4i.b" } }, + .{ .value = 0x039c0000, .then = .{ .instruction = .@"xvshuf4i.d" } }, + .{ .value = 0x03940000, .then = .{ .instruction = .@"xvshuf4i.h" } }, + .{ .value = 0x03980000, .then = .{ .instruction = .@"xvshuf4i.w" } }, + .{ .value = 0x00040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsle.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsle.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsle.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsle.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslt.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslt.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslt.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslt.w" } }, + } } }, + .{ .value = 0x02840000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslei.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvslei.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslei.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslei.wu" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvslti.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvslti.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvslti.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvslti.w" } }, + } } }, + .{ .value = 0x00e80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsll.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsll.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsll.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsll.w" } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrl.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrl.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrl.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrl.w" } }, + } } }, + .{ .value = 0x032c0000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvslli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvslli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvslli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvslli.d" } }, + } } }, + .{ .value = 0x03340000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrai.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrai.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrai.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrai.d" } }, + } } }, + .{ .value = 0x00f40000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrln.w.d" } }, + } } }, + .{ .value = 0x03580000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrani.d.q" } }, + } } }, + .{ .value = 0x00f00000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrar.b" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrar.d" } }, + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrar.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrar.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlr.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrlr.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlr.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlr.w" } }, + } } }, + .{ .value = 0x02a80000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrari.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrari.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrari.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrari.d" } }, + } } }, + .{ .value = 0x00f80000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvsrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvsrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvsrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsrlrn.w.d" } }, + } } }, + .{ .value = 0x035c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrarni.d.q" } }, + } } }, + .{ .value = 0x03300000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrli.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrli.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrli.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrli.d" } }, + } } }, + .{ .value = 0x03400000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrlni.d.q" } }, + } } }, + .{ .value = 0x02a40000, .then = .{ .mask = 0x00030000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00004000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlri.b" } }, + .{ .value = 0x00004000, .then = .{ .instruction = .@"xvsrlri.h" } }, + } } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlri.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlri.d" } }, + } } }, + .{ .value = 0x03440000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvsrlrni.d.q" } }, + } } }, + .{ .value = 0x00fc0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssran.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssran.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssran.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrln.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrln.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrln.w.d" } }, + } } }, + .{ .value = 0x01040000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssran.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssran.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssran.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrln.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrln.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrln.wu.d" } }, + } } }, + .{ .value = 0x03600000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrani.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrani.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrani.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrani.d.q" } }, + } } }, + .{ .value = 0x03640000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrani.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrani.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrani.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrani.du.q" } }, + } } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssrarn.b.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssrarn.h.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssrarn.w.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrn.b.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrn.h.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrlrn.w.d" } }, + } } }, + .{ .value = 0x01080000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00028000, .then = .{ .instruction = .@"xvssrarn.bu.h" } }, + .{ .value = 0x00030000, .then = .{ .instruction = .@"xvssrarn.hu.w" } }, + .{ .value = 0x00038000, .then = .{ .instruction = .@"xvssrarn.wu.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrn.bu.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrn.hu.w" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssrlrn.wu.d" } }, + } } }, + .{ .value = 0x03680000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrarni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrarni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrarni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrarni.d.q" } }, + } } }, + .{ .value = 0x036c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrarni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrarni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrarni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrarni.du.q" } }, + } } }, + .{ .value = 0x03480000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlni.d.q" } }, + } } }, + .{ .value = 0x034c0000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlni.du.q" } }, + } } }, + .{ .value = 0x03500000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlrni.b.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrni.h.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrni.w.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlrni.d.q" } }, + } } }, + .{ .value = 0x03540000, .then = .{ .mask = 0x00020000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00010000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00008000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssrlrni.bu.h" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssrlrni.hu.w" } }, + } } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssrlrni.wu.d" } }, + } } }, + .{ .value = 0x00020000, .then = .{ .instruction = .@"xvssrlrni.du.q" } }, + } } }, + .{ .value = 0x004c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvssub.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvssub.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvssub.hu" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvssub.wu" } }, + } } }, + .{ .value = 0x000c0000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsub.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsub.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsub.h" } }, + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsub.w" } }, + } } }, + .{ .value = 0x00240000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwod.d.w" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwod.h.b" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwod.q.d" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwod.w.h" } }, + } } }, + .{ .value = 0x00340000, .then = .{ .mask = 0x00038000, .cases = .{ + .{ .value = 0x00010000, .then = .{ .instruction = .@"xvsubwod.d.wu" } }, + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvsubwod.h.bu" } }, + .{ .value = 0x00018000, .then = .{ .instruction = .@"xvsubwod.q.du" } }, + .{ .value = 0x00008000, .then = .{ .instruction = .@"xvsubwod.w.hu" } }, + } } }, + .{ .value = 0x03d80000, .then = .{ .instruction = .@"xvxori.b" } }, + } } }, + .{ .value = 0x30000000, .then = .{ .mask = 0x03800000, .cases = .{ + .{ .value = 0x00800000, .then = .{ .instruction = .@"vldrepl.b" } }, + .{ .value = 0x00000000, .then = .{ .mask = 0x00600000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vldrepl.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"vldrepl.h" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"vldrepl.w" } }, + } } }, + .{ .value = 0x01800000, .then = .{ .instruction = .@"vstelm.b" } }, + .{ .value = 0x01000000, .then = .{ .mask = 0x00600000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"vstelm.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"vstelm.h" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"vstelm.w" } }, + } } }, + .{ .value = 0x02800000, .then = .{ .instruction = .@"xvldrepl.b" } }, + .{ .value = 0x02000000, .then = .{ .mask = 0x00600000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvldrepl.d" } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"xvldrepl.h" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"xvldrepl.w" } }, + } } }, + .{ .value = 0x03800000, .then = .{ .instruction = .@"xvstelm.b" } }, + .{ .value = 0x03000000, .then = .{ .mask = 0x00400000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .mask = 0x00200000, .cases = .{ + .{ .value = 0x00000000, .then = .{ .instruction = .@"xvstelm.d" } }, + .{ .value = 0x00200000, .then = .{ .instruction = .@"xvstelm.w" } }, + } } }, + .{ .value = 0x00400000, .then = .{ .instruction = .@"xvstelm.h" } }, + } } }, + } } }, +} } diff --git a/src/codegen/loongarch/encoding.zig b/src/codegen/loongarch/encoding.zig new file mode 100644 index 0000000000000000000000000000000000000000..e90b0e2bd75ce2f9a025a2bc3acd450b5d63d4d9 --- /dev/null +++ b/src/codegen/loongarch/encoding.zig @@ -0,0 +1,13695 @@ +// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. +const Register = @import("bits.zig").Register; + +pub const Mnemonic = enum { + @"adc.b", + @"adc.d", + @"adc.h", + @"adc.w", + @"add.d", + @"add.w", + @"addi.d", + @"addi.w", + @"addu12i.d", + @"addu12i.w", + @"addu16i.d", + @"amadd.b", + @"amadd.d", + @"amadd.h", + @"amadd.w", + @"amadd_db.b", + @"amadd_db.d", + @"amadd_db.h", + @"amadd_db.w", + @"amand.d", + @"amand.w", + @"amand_db.d", + @"amand_db.w", + @"amcas.b", + @"amcas.d", + @"amcas.h", + @"amcas.w", + @"amcas_db.b", + @"amcas_db.d", + @"amcas_db.h", + @"amcas_db.w", + @"ammax.d", + @"ammax.du", + @"ammax.w", + @"ammax.wu", + @"ammax_db.d", + @"ammax_db.du", + @"ammax_db.w", + @"ammax_db.wu", + @"ammin.d", + @"ammin.du", + @"ammin.w", + @"ammin.wu", + @"ammin_db.d", + @"ammin_db.du", + @"ammin_db.w", + @"ammin_db.wu", + @"amor.d", + @"amor.w", + @"amor_db.d", + @"amor_db.w", + @"amswap.b", + @"amswap.d", + @"amswap.h", + @"amswap.w", + @"amswap_db.b", + @"amswap_db.d", + @"amswap_db.h", + @"amswap_db.w", + @"amxor.d", + @"amxor.w", + @"amxor_db.d", + @"amxor_db.w", + @"and", + andi, + andn, + @"armadc.w", + @"armadd.w", + @"armand.w", + armmfflag, + @"armmov.d", + @"armmov.w", + armmove, + armmtflag, + @"armnot.w", + @"armor.w", + @"armrotr.w", + @"armrotri.w", + @"armrrx.w", + @"armsbc.w", + armsetj, + @"armsll.w", + @"armslli.w", + @"armsra.w", + @"armsrai.w", + @"armsrl.w", + @"armsrli.w", + @"armsub.w", + @"armxor.w", + asrtgt, + asrtle, + b, + bceqz, + bcnez, + beq, + beqz, + bgt, + bgtu, + bl, + ble, + bleu, + bne, + bnez, + @"break", + @"bstrins.d", + @"bstrins.w", + @"bstrpick.d", + @"bstrpick.w", + cacop, + @"catpick.d", + @"catpick.w", + @"clo.d", + @"clo.w", + @"clz.d", + @"clz.w", + cpucfg, + @"crc.w.b.w", + @"crc.w.d.w", + @"crc.w.h.w", + @"crc.w.w.w", + @"crcc.w.b.w", + @"crcc.w.d.w", + @"crcc.w.h.w", + @"crcc.w.w.w", + csrrd, + csrwr, + csrxchg, + @"cto.d", + @"cto.w", + @"ctz.d", + @"ctz.w", + @"cu32i.d", + @"cu52i.d", + dbar, + dbgcall, + @"div.d", + @"div.du", + @"div.w", + @"div.wu", + eret, + @"fabs.d", + @"fabs.s", + @"fadd.d", + @"fadd.s", + @"fclass.d", + @"fclass.s", + @"fcmp.caf.d", + @"fcmp.caf.s", + @"fcmp.ceq.d", + @"fcmp.ceq.s", + @"fcmp.cle.d", + @"fcmp.cle.s", + @"fcmp.clt.d", + @"fcmp.clt.s", + @"fcmp.cne.d", + @"fcmp.cne.s", + @"fcmp.cor.d", + @"fcmp.cor.s", + @"fcmp.cueq.d", + @"fcmp.cueq.s", + @"fcmp.cule.d", + @"fcmp.cule.s", + @"fcmp.cult.d", + @"fcmp.cult.s", + @"fcmp.cun.d", + @"fcmp.cun.s", + @"fcmp.cune.d", + @"fcmp.cune.s", + @"fcmp.saf.d", + @"fcmp.saf.s", + @"fcmp.seq.d", + @"fcmp.seq.s", + @"fcmp.sle.d", + @"fcmp.sle.s", + @"fcmp.slt.d", + @"fcmp.slt.s", + @"fcmp.sne.d", + @"fcmp.sne.s", + @"fcmp.sor.d", + @"fcmp.sor.s", + @"fcmp.sueq.d", + @"fcmp.sueq.s", + @"fcmp.sule.d", + @"fcmp.sule.s", + @"fcmp.sult.d", + @"fcmp.sult.s", + @"fcmp.sun.d", + @"fcmp.sun.s", + @"fcmp.sune.d", + @"fcmp.sune.s", + @"fcopysign.d", + @"fcopysign.s", + fcsrrd, + fcsrwr, + @"fcvt.d.ld", + @"fcvt.d.s", + @"fcvt.ld.d", + @"fcvt.s.d", + @"fcvt.ud.d", + @"fdiv.d", + @"fdiv.s", + @"ffint.d.l", + @"ffint.d.w", + @"ffint.s.l", + @"ffint.s.w", + @"fld.d", + @"fld.s", + @"fldgt.d", + @"fldgt.s", + @"fldle.d", + @"fldle.s", + @"fldx.d", + @"fldx.s", + @"flogb.d", + @"flogb.s", + @"fmadd.d", + @"fmadd.s", + @"fmax.d", + @"fmax.s", + @"fmaxa.d", + @"fmaxa.s", + @"fmin.d", + @"fmin.s", + @"fmina.d", + @"fmina.s", + @"fmov.d", + @"fmov.s", + @"fmsub.d", + @"fmsub.s", + @"fmul.d", + @"fmul.s", + @"fneg.d", + @"fneg.s", + @"fnmadd.d", + @"fnmadd.s", + @"fnmsub.d", + @"fnmsub.s", + @"frecip.d", + @"frecip.s", + @"frecipe.d", + @"frecipe.s", + @"frint.d", + @"frint.s", + @"frsqrt.d", + @"frsqrt.s", + @"frsqrte.d", + @"frsqrte.s", + @"fscaleb.d", + @"fscaleb.s", + fsel, + @"fsqrt.d", + @"fsqrt.s", + @"fst.d", + @"fst.s", + @"fstgt.d", + @"fstgt.s", + @"fstle.d", + @"fstle.s", + @"fstx.d", + @"fstx.s", + @"fsub.d", + @"fsub.s", + @"ftint.l.d", + @"ftint.l.s", + @"ftint.w.d", + @"ftint.w.s", + @"ftintrm.l.d", + @"ftintrm.l.s", + @"ftintrm.w.d", + @"ftintrm.w.s", + @"ftintrne.l.d", + @"ftintrne.l.s", + @"ftintrne.w.d", + @"ftintrne.w.s", + @"ftintrp.l.d", + @"ftintrp.l.s", + @"ftintrp.w.d", + @"ftintrp.w.s", + @"ftintrz.l.d", + @"ftintrz.l.s", + @"ftintrz.w.d", + @"ftintrz.w.s", + gcsrrd, + gcsrwr, + gcsrxchg, + gtlbclr, + gtlbfill, + gtlbflush, + gtlbrd, + gtlbsrch, + gtlbwr, + hypcall, + ibar, + idle, + @"iocsrrd.b", + @"iocsrrd.d", + @"iocsrrd.h", + @"iocsrrd.w", + @"iocsrwr.b", + @"iocsrwr.d", + @"iocsrwr.h", + @"iocsrwr.w", + jirl, + jiscr0, + jiscr1, + @"ld.b", + @"ld.bu", + @"ld.d", + @"ld.h", + @"ld.hu", + @"ld.w", + @"ld.wu", + lddir, + @"ldgt.b", + @"ldgt.d", + @"ldgt.h", + @"ldgt.w", + @"ldl.d", + @"ldl.w", + @"ldle.b", + @"ldle.d", + @"ldle.h", + @"ldle.w", + @"ldox4.d", + @"ldox4.w", + ldpte, + @"ldr.d", + @"ldr.w", + @"ldx.b", + @"ldx.bu", + @"ldx.d", + @"ldx.h", + @"ldx.hu", + @"ldx.w", + @"ldx.wu", + @"ll.d", + @"ll.w", + @"llacq.d", + @"llacq.w", + @"lu12i.w", + maskeqz, + masknez, + @"mod.d", + @"mod.du", + @"mod.w", + @"mod.wu", + movfcc2fr, + movfcc2gr, + movfr2fcc, + @"movfr2gr.d", + @"movfr2gr.s", + @"movfrh2gr.s", + movgr2fcc, + @"movgr2fr.d", + @"movgr2fr.w", + @"movgr2frh.w", + movgr2scr, + movscr2gr, + @"mul.d", + @"mul.w", + @"mulh.d", + @"mulh.du", + @"mulh.w", + @"mulh.wu", + @"mulw.d.w", + @"mulw.d.wu", + nor, + @"or", + ori, + orn, + pcaddu12i, + pcaddu18i, + pcaddu2i, + pcalau12i, + preld, + preldx, + @"rcr.b", + @"rcr.d", + @"rcr.h", + @"rcr.w", + @"rcri.b", + @"rcri.d", + @"rcri.h", + @"rcri.w", + @"rdtime.d", + @"rdtimeh.w", + @"rdtimel.w", + @"revb.2h", + @"revb.2w", + @"revb.4h", + @"revb.d", + @"revbit.4b", + @"revbit.8b", + @"revbit.d", + @"revbit.w", + @"revh.2w", + @"revh.d", + @"rotr.b", + @"rotr.d", + @"rotr.h", + @"rotr.w", + @"rotri.b", + @"rotri.d", + @"rotri.h", + @"rotri.w", + @"sbc.b", + @"sbc.d", + @"sbc.h", + @"sbc.w", + @"sc.d", + @"sc.q", + @"sc.w", + @"screl.d", + @"screl.w", + @"sext.b", + @"sext.h", + @"sladd.d", + @"sladd.w", + @"sladd.wu", + @"sll.d", + @"sll.w", + @"slli.d", + @"slli.w", + slt, + slti, + sltu, + sltui, + @"sra.d", + @"sra.w", + @"srai.d", + @"srai.w", + @"srl.d", + @"srl.w", + @"srli.d", + @"srli.w", + @"st.b", + @"st.d", + @"st.h", + @"st.w", + @"stgt.b", + @"stgt.d", + @"stgt.h", + @"stgt.w", + @"stl.d", + @"stl.w", + @"stle.b", + @"stle.d", + @"stle.h", + @"stle.w", + @"stox4.d", + @"stox4.w", + @"str.d", + @"str.w", + @"stx.b", + @"stx.d", + @"stx.h", + @"stx.w", + @"sub.d", + @"sub.w", + syscall, + tlbclr, + tlbfill, + tlbflush, + tlbinv, + tlbrd, + tlbsrch, + tlbwr, + @"vabsd.b", + @"vabsd.bu", + @"vabsd.d", + @"vabsd.du", + @"vabsd.h", + @"vabsd.hu", + @"vabsd.w", + @"vabsd.wu", + @"vadd.b", + @"vadd.d", + @"vadd.h", + @"vadd.q", + @"vadd.w", + @"vadda.b", + @"vadda.d", + @"vadda.h", + @"vadda.w", + @"vaddi.bu", + @"vaddi.du", + @"vaddi.hu", + @"vaddi.wu", + @"vaddwev.d.w", + @"vaddwev.d.wu", + @"vaddwev.d.wu.w", + @"vaddwev.h.b", + @"vaddwev.h.bu", + @"vaddwev.h.bu.b", + @"vaddwev.q.d", + @"vaddwev.q.du", + @"vaddwev.q.du.d", + @"vaddwev.w.h", + @"vaddwev.w.hu", + @"vaddwev.w.hu.h", + @"vaddwod.d.w", + @"vaddwod.d.wu", + @"vaddwod.d.wu.w", + @"vaddwod.h.b", + @"vaddwod.h.bu", + @"vaddwod.h.bu.b", + @"vaddwod.q.d", + @"vaddwod.q.du", + @"vaddwod.q.du.d", + @"vaddwod.w.h", + @"vaddwod.w.hu", + @"vaddwod.w.hu.h", + @"vand.v", + @"vandi.b", + @"vandn.v", + @"vavg.b", + @"vavg.bu", + @"vavg.d", + @"vavg.du", + @"vavg.h", + @"vavg.hu", + @"vavg.w", + @"vavg.wu", + @"vavgr.b", + @"vavgr.bu", + @"vavgr.d", + @"vavgr.du", + @"vavgr.h", + @"vavgr.hu", + @"vavgr.w", + @"vavgr.wu", + @"vbitclr.b", + @"vbitclr.d", + @"vbitclr.h", + @"vbitclr.w", + @"vbitclri.b", + @"vbitclri.d", + @"vbitclri.h", + @"vbitclri.w", + @"vbitrev.b", + @"vbitrev.d", + @"vbitrev.h", + @"vbitrev.w", + @"vbitrevi.b", + @"vbitrevi.d", + @"vbitrevi.h", + @"vbitrevi.w", + @"vbitsel.v", + @"vbitseli.b", + @"vbitset.b", + @"vbitset.d", + @"vbitset.h", + @"vbitset.w", + @"vbitseti.b", + @"vbitseti.d", + @"vbitseti.h", + @"vbitseti.w", + @"vbsll.v", + @"vbsrl.v", + @"vclo.b", + @"vclo.d", + @"vclo.h", + @"vclo.w", + @"vclz.b", + @"vclz.d", + @"vclz.h", + @"vclz.w", + @"vdiv.b", + @"vdiv.bu", + @"vdiv.d", + @"vdiv.du", + @"vdiv.h", + @"vdiv.hu", + @"vdiv.w", + @"vdiv.wu", + @"vext2xv.d.b", + @"vext2xv.d.h", + @"vext2xv.d.w", + @"vext2xv.du.bu", + @"vext2xv.du.hu", + @"vext2xv.du.wu", + @"vext2xv.h.b", + @"vext2xv.hu.bu", + @"vext2xv.w.b", + @"vext2xv.w.h", + @"vext2xv.wu.bu", + @"vext2xv.wu.hu", + @"vexth.d.w", + @"vexth.du.wu", + @"vexth.h.b", + @"vexth.hu.bu", + @"vexth.q.d", + @"vexth.qu.du", + @"vexth.w.h", + @"vexth.wu.hu", + @"vextl.q.d", + @"vextl.qu.du", + @"vextrins.b", + @"vextrins.d", + @"vextrins.h", + @"vextrins.w", + @"vfadd.d", + @"vfadd.s", + @"vfclass.d", + @"vfclass.s", + @"vfcmp.caf.d", + @"vfcmp.caf.s", + @"vfcmp.ceq.d", + @"vfcmp.ceq.s", + @"vfcmp.cle.d", + @"vfcmp.cle.s", + @"vfcmp.clt.d", + @"vfcmp.clt.s", + @"vfcmp.cne.d", + @"vfcmp.cne.s", + @"vfcmp.cor.d", + @"vfcmp.cor.s", + @"vfcmp.cueq.d", + @"vfcmp.cueq.s", + @"vfcmp.cule.d", + @"vfcmp.cule.s", + @"vfcmp.cult.d", + @"vfcmp.cult.s", + @"vfcmp.cun.d", + @"vfcmp.cun.s", + @"vfcmp.cune.d", + @"vfcmp.cune.s", + @"vfcmp.saf.d", + @"vfcmp.saf.s", + @"vfcmp.seq.d", + @"vfcmp.seq.s", + @"vfcmp.sle.d", + @"vfcmp.sle.s", + @"vfcmp.slt.d", + @"vfcmp.slt.s", + @"vfcmp.sne.d", + @"vfcmp.sne.s", + @"vfcmp.sor.d", + @"vfcmp.sor.s", + @"vfcmp.sueq.d", + @"vfcmp.sueq.s", + @"vfcmp.sule.d", + @"vfcmp.sule.s", + @"vfcmp.sult.d", + @"vfcmp.sult.s", + @"vfcmp.sun.d", + @"vfcmp.sun.s", + @"vfcmp.sune.d", + @"vfcmp.sune.s", + @"vfcvt.h.s", + @"vfcvt.s.d", + @"vfcvth.d.s", + @"vfcvth.s.h", + @"vfcvtl.d.s", + @"vfcvtl.s.h", + @"vfdiv.d", + @"vfdiv.s", + @"vffint.d.l", + @"vffint.d.lu", + @"vffint.s.l", + @"vffint.s.w", + @"vffint.s.wu", + @"vffinth.d.w", + @"vffintl.d.w", + @"vflogb.d", + @"vflogb.s", + @"vfmadd.d", + @"vfmadd.s", + @"vfmax.d", + @"vfmax.s", + @"vfmaxa.d", + @"vfmaxa.s", + @"vfmin.d", + @"vfmin.s", + @"vfmina.d", + @"vfmina.s", + @"vfmsub.d", + @"vfmsub.s", + @"vfmul.d", + @"vfmul.s", + @"vfnmadd.d", + @"vfnmadd.s", + @"vfnmsub.d", + @"vfnmsub.s", + @"vfrecip.d", + @"vfrecip.s", + @"vfrecipe.d", + @"vfrecipe.s", + @"vfrint.d", + @"vfrint.s", + @"vfrintrm.d", + @"vfrintrm.s", + @"vfrintrne.d", + @"vfrintrne.s", + @"vfrintrp.d", + @"vfrintrp.s", + @"vfrintrz.d", + @"vfrintrz.s", + @"vfrsqrt.d", + @"vfrsqrt.s", + @"vfrsqrte.d", + @"vfrsqrte.s", + @"vfrstp.b", + @"vfrstp.h", + @"vfrstpi.b", + @"vfrstpi.h", + @"vfsqrt.d", + @"vfsqrt.s", + @"vfsub.d", + @"vfsub.s", + @"vftint.l.d", + @"vftint.lu.d", + @"vftint.w.d", + @"vftint.w.s", + @"vftint.wu.s", + @"vftinth.l.s", + @"vftintl.l.s", + @"vftintrm.l.d", + @"vftintrm.w.d", + @"vftintrm.w.s", + @"vftintrmh.l.s", + @"vftintrml.l.s", + @"vftintrne.l.d", + @"vftintrne.w.d", + @"vftintrne.w.s", + @"vftintrneh.l.s", + @"vftintrnel.l.s", + @"vftintrp.l.d", + @"vftintrp.w.d", + @"vftintrp.w.s", + @"vftintrph.l.s", + @"vftintrpl.l.s", + @"vftintrz.l.d", + @"vftintrz.lu.d", + @"vftintrz.w.d", + @"vftintrz.w.s", + @"vftintrz.wu.s", + @"vftintrzh.l.s", + @"vftintrzl.l.s", + @"vhaddw.d.w", + @"vhaddw.du.wu", + @"vhaddw.h.b", + @"vhaddw.hu.bu", + @"vhaddw.q.d", + @"vhaddw.qu.du", + @"vhaddw.w.h", + @"vhaddw.wu.hu", + @"vhsubw.d.w", + @"vhsubw.du.wu", + @"vhsubw.h.b", + @"vhsubw.hu.bu", + @"vhsubw.q.d", + @"vhsubw.qu.du", + @"vhsubw.w.h", + @"vhsubw.wu.hu", + @"vilvh.b", + @"vilvh.d", + @"vilvh.h", + @"vilvh.w", + @"vilvl.b", + @"vilvl.d", + @"vilvl.h", + @"vilvl.w", + @"vinsgr2vr.b", + @"vinsgr2vr.d", + @"vinsgr2vr.h", + @"vinsgr2vr.w", + vld, + vldi, + @"vldrepl.b", + @"vldrepl.d", + @"vldrepl.h", + @"vldrepl.w", + vldx, + @"vmadd.b", + @"vmadd.d", + @"vmadd.h", + @"vmadd.w", + @"vmaddwev.d.w", + @"vmaddwev.d.wu", + @"vmaddwev.d.wu.w", + @"vmaddwev.h.b", + @"vmaddwev.h.bu", + @"vmaddwev.h.bu.b", + @"vmaddwev.q.d", + @"vmaddwev.q.du", + @"vmaddwev.q.du.d", + @"vmaddwev.w.h", + @"vmaddwev.w.hu", + @"vmaddwev.w.hu.h", + @"vmaddwod.d.w", + @"vmaddwod.d.wu", + @"vmaddwod.d.wu.w", + @"vmaddwod.h.b", + @"vmaddwod.h.bu", + @"vmaddwod.h.bu.b", + @"vmaddwod.q.d", + @"vmaddwod.q.du", + @"vmaddwod.q.du.d", + @"vmaddwod.w.h", + @"vmaddwod.w.hu", + @"vmaddwod.w.hu.h", + @"vmax.b", + @"vmax.bu", + @"vmax.d", + @"vmax.du", + @"vmax.h", + @"vmax.hu", + @"vmax.w", + @"vmax.wu", + @"vmaxi.b", + @"vmaxi.bu", + @"vmaxi.d", + @"vmaxi.du", + @"vmaxi.h", + @"vmaxi.hu", + @"vmaxi.w", + @"vmaxi.wu", + @"vmepatmsk.v", + @"vmin.b", + @"vmin.bu", + @"vmin.d", + @"vmin.du", + @"vmin.h", + @"vmin.hu", + @"vmin.w", + @"vmin.wu", + @"vmini.b", + @"vmini.bu", + @"vmini.d", + @"vmini.du", + @"vmini.h", + @"vmini.hu", + @"vmini.w", + @"vmini.wu", + @"vmod.b", + @"vmod.bu", + @"vmod.d", + @"vmod.du", + @"vmod.h", + @"vmod.hu", + @"vmod.w", + @"vmod.wu", + @"vmskgez.b", + @"vmskltz.b", + @"vmskltz.d", + @"vmskltz.h", + @"vmskltz.w", + @"vmsknz.b", + @"vmsub.b", + @"vmsub.d", + @"vmsub.h", + @"vmsub.w", + @"vmuh.b", + @"vmuh.bu", + @"vmuh.d", + @"vmuh.du", + @"vmuh.h", + @"vmuh.hu", + @"vmuh.w", + @"vmuh.wu", + @"vmul.b", + @"vmul.d", + @"vmul.h", + @"vmul.w", + @"vmulwev.d.w", + @"vmulwev.d.wu", + @"vmulwev.d.wu.w", + @"vmulwev.h.b", + @"vmulwev.h.bu", + @"vmulwev.h.bu.b", + @"vmulwev.q.d", + @"vmulwev.q.du", + @"vmulwev.q.du.d", + @"vmulwev.w.h", + @"vmulwev.w.hu", + @"vmulwev.w.hu.h", + @"vmulwod.d.w", + @"vmulwod.d.wu", + @"vmulwod.d.wu.w", + @"vmulwod.h.b", + @"vmulwod.h.bu", + @"vmulwod.h.bu.b", + @"vmulwod.q.d", + @"vmulwod.q.du", + @"vmulwod.q.du.d", + @"vmulwod.w.h", + @"vmulwod.w.hu", + @"vmulwod.w.hu.h", + @"vneg.b", + @"vneg.d", + @"vneg.h", + @"vneg.w", + @"vnor.v", + @"vnori.b", + @"vor.v", + @"vori.b", + @"vorn.v", + @"vpackev.b", + @"vpackev.d", + @"vpackev.h", + @"vpackev.w", + @"vpackod.b", + @"vpackod.d", + @"vpackod.h", + @"vpackod.w", + @"vpcnt.b", + @"vpcnt.d", + @"vpcnt.h", + @"vpcnt.w", + @"vpermi.w", + @"vpickev.b", + @"vpickev.d", + @"vpickev.h", + @"vpickev.w", + @"vpickod.b", + @"vpickod.d", + @"vpickod.h", + @"vpickod.w", + @"vpickve2gr.b", + @"vpickve2gr.bu", + @"vpickve2gr.d", + @"vpickve2gr.du", + @"vpickve2gr.h", + @"vpickve2gr.hu", + @"vpickve2gr.w", + @"vpickve2gr.wu", + @"vreplgr2vr.b", + @"vreplgr2vr.d", + @"vreplgr2vr.h", + @"vreplgr2vr.w", + @"vreplve.b", + @"vreplve.d", + @"vreplve.h", + @"vreplve.w", + @"vreplvei.b", + @"vreplvei.d", + @"vreplvei.h", + @"vreplvei.w", + @"vrotr.b", + @"vrotr.d", + @"vrotr.h", + @"vrotr.w", + @"vrotri.b", + @"vrotri.d", + @"vrotri.h", + @"vrotri.w", + @"vsadd.b", + @"vsadd.bu", + @"vsadd.d", + @"vsadd.du", + @"vsadd.h", + @"vsadd.hu", + @"vsadd.w", + @"vsadd.wu", + @"vsat.b", + @"vsat.bu", + @"vsat.d", + @"vsat.du", + @"vsat.h", + @"vsat.hu", + @"vsat.w", + @"vsat.wu", + @"vseq.b", + @"vseq.d", + @"vseq.h", + @"vseq.w", + @"vseqi.b", + @"vseqi.d", + @"vseqi.h", + @"vseqi.w", + @"vsetallnez.b", + @"vsetallnez.d", + @"vsetallnez.h", + @"vsetallnez.w", + @"vsetanyeqz.b", + @"vsetanyeqz.d", + @"vsetanyeqz.h", + @"vsetanyeqz.w", + @"vseteqz.v", + @"vsetnez.v", + @"vshuf.b", + @"vshuf.d", + @"vshuf.h", + @"vshuf.w", + @"vshuf4i.b", + @"vshuf4i.d", + @"vshuf4i.h", + @"vshuf4i.w", + @"vsigncov.b", + @"vsigncov.d", + @"vsigncov.h", + @"vsigncov.w", + @"vsle.b", + @"vsle.bu", + @"vsle.d", + @"vsle.du", + @"vsle.h", + @"vsle.hu", + @"vsle.w", + @"vsle.wu", + @"vslei.b", + @"vslei.bu", + @"vslei.d", + @"vslei.du", + @"vslei.h", + @"vslei.hu", + @"vslei.w", + @"vslei.wu", + @"vsll.b", + @"vsll.d", + @"vsll.h", + @"vsll.w", + @"vslli.b", + @"vslli.d", + @"vslli.h", + @"vslli.w", + @"vsllwil.d.w", + @"vsllwil.du.wu", + @"vsllwil.h.b", + @"vsllwil.hu.bu", + @"vsllwil.w.h", + @"vsllwil.wu.hu", + @"vslt.b", + @"vslt.bu", + @"vslt.d", + @"vslt.du", + @"vslt.h", + @"vslt.hu", + @"vslt.w", + @"vslt.wu", + @"vslti.b", + @"vslti.bu", + @"vslti.d", + @"vslti.du", + @"vslti.h", + @"vslti.hu", + @"vslti.w", + @"vslti.wu", + @"vsra.b", + @"vsra.d", + @"vsra.h", + @"vsra.w", + @"vsrai.b", + @"vsrai.d", + @"vsrai.h", + @"vsrai.w", + @"vsran.b.h", + @"vsran.h.w", + @"vsran.w.d", + @"vsrani.b.h", + @"vsrani.d.q", + @"vsrani.h.w", + @"vsrani.w.d", + @"vsrar.b", + @"vsrar.d", + @"vsrar.h", + @"vsrar.w", + @"vsrari.b", + @"vsrari.d", + @"vsrari.h", + @"vsrari.w", + @"vsrarn.b.h", + @"vsrarn.h.w", + @"vsrarn.w.d", + @"vsrarni.b.h", + @"vsrarni.d.q", + @"vsrarni.h.w", + @"vsrarni.w.d", + @"vsrl.b", + @"vsrl.d", + @"vsrl.h", + @"vsrl.w", + @"vsrli.b", + @"vsrli.d", + @"vsrli.h", + @"vsrli.w", + @"vsrln.b.h", + @"vsrln.h.w", + @"vsrln.w.d", + @"vsrlni.b.h", + @"vsrlni.d.q", + @"vsrlni.h.w", + @"vsrlni.w.d", + @"vsrlr.b", + @"vsrlr.d", + @"vsrlr.h", + @"vsrlr.w", + @"vsrlri.b", + @"vsrlri.d", + @"vsrlri.h", + @"vsrlri.w", + @"vsrlrn.b.h", + @"vsrlrn.h.w", + @"vsrlrn.w.d", + @"vsrlrni.b.h", + @"vsrlrni.d.q", + @"vsrlrni.h.w", + @"vsrlrni.w.d", + @"vssran.b.h", + @"vssran.bu.h", + @"vssran.h.w", + @"vssran.hu.w", + @"vssran.w.d", + @"vssran.wu.d", + @"vssrani.b.h", + @"vssrani.bu.h", + @"vssrani.d.q", + @"vssrani.du.q", + @"vssrani.h.w", + @"vssrani.hu.w", + @"vssrani.w.d", + @"vssrani.wu.d", + @"vssrarn.b.h", + @"vssrarn.bu.h", + @"vssrarn.h.w", + @"vssrarn.hu.w", + @"vssrarn.w.d", + @"vssrarn.wu.d", + @"vssrarni.b.h", + @"vssrarni.bu.h", + @"vssrarni.d.q", + @"vssrarni.du.q", + @"vssrarni.h.w", + @"vssrarni.hu.w", + @"vssrarni.w.d", + @"vssrarni.wu.d", + @"vssrln.b.h", + @"vssrln.bu.h", + @"vssrln.h.w", + @"vssrln.hu.w", + @"vssrln.w.d", + @"vssrln.wu.d", + @"vssrlni.b.h", + @"vssrlni.bu.h", + @"vssrlni.d.q", + @"vssrlni.du.q", + @"vssrlni.h.w", + @"vssrlni.hu.w", + @"vssrlni.w.d", + @"vssrlni.wu.d", + @"vssrlrn.b.h", + @"vssrlrn.bu.h", + @"vssrlrn.h.w", + @"vssrlrn.hu.w", + @"vssrlrn.w.d", + @"vssrlrn.wu.d", + @"vssrlrni.b.h", + @"vssrlrni.bu.h", + @"vssrlrni.d.q", + @"vssrlrni.du.q", + @"vssrlrni.h.w", + @"vssrlrni.hu.w", + @"vssrlrni.w.d", + @"vssrlrni.wu.d", + @"vssub.b", + @"vssub.bu", + @"vssub.d", + @"vssub.du", + @"vssub.h", + @"vssub.hu", + @"vssub.w", + @"vssub.wu", + vst, + @"vstelm.b", + @"vstelm.d", + @"vstelm.h", + @"vstelm.w", + vstx, + @"vsub.b", + @"vsub.d", + @"vsub.h", + @"vsub.q", + @"vsub.w", + @"vsubi.bu", + @"vsubi.du", + @"vsubi.hu", + @"vsubi.wu", + @"vsubwev.d.w", + @"vsubwev.d.wu", + @"vsubwev.h.b", + @"vsubwev.h.bu", + @"vsubwev.q.d", + @"vsubwev.q.du", + @"vsubwev.w.h", + @"vsubwev.w.hu", + @"vsubwod.d.w", + @"vsubwod.d.wu", + @"vsubwod.h.b", + @"vsubwod.h.bu", + @"vsubwod.q.d", + @"vsubwod.q.du", + @"vsubwod.w.h", + @"vsubwod.w.hu", + @"vxor.v", + @"vxori.b", + @"x86adc.b", + @"x86adc.d", + @"x86adc.h", + @"x86adc.w", + @"x86add.b", + @"x86add.d", + @"x86add.du", + @"x86add.h", + @"x86add.w", + @"x86add.wu", + @"x86and.b", + @"x86and.d", + @"x86and.h", + @"x86and.w", + x86clrtm, + @"x86dec.b", + @"x86dec.d", + @"x86dec.h", + @"x86dec.w", + x86dectop, + @"x86inc.b", + @"x86inc.d", + @"x86inc.h", + @"x86inc.w", + x86inctop, + x86mfflag, + x86mftop, + x86mtflag, + x86mttop, + @"x86mul.b", + @"x86mul.bu", + @"x86mul.d", + @"x86mul.du", + @"x86mul.h", + @"x86mul.hu", + @"x86mul.w", + @"x86mul.wu", + @"x86or.b", + @"x86or.d", + @"x86or.h", + @"x86or.w", + @"x86rcl.b", + @"x86rcl.d", + @"x86rcl.h", + @"x86rcl.w", + @"x86rcli.b", + @"x86rcli.d", + @"x86rcli.h", + @"x86rcli.w", + @"x86rcr.b", + @"x86rcr.d", + @"x86rcr.h", + @"x86rcr.w", + @"x86rcri.b", + @"x86rcri.d", + @"x86rcri.h", + @"x86rcri.w", + @"x86rotl.b", + @"x86rotl.d", + @"x86rotl.h", + @"x86rotl.w", + @"x86rotli.b", + @"x86rotli.d", + @"x86rotli.h", + @"x86rotli.w", + @"x86rotr.b", + @"x86rotr.d", + @"x86rotr.h", + @"x86rotr.w", + @"x86rotri.b", + @"x86rotri.d", + @"x86rotri.h", + @"x86rotri.w", + @"x86sbc.b", + @"x86sbc.d", + @"x86sbc.h", + @"x86sbc.w", + x86setj, + x86setloope, + x86setloopne, + x86settag, + x86settm, + @"x86sll.b", + @"x86sll.d", + @"x86sll.h", + @"x86sll.w", + @"x86slli.b", + @"x86slli.d", + @"x86slli.h", + @"x86slli.w", + @"x86sra.b", + @"x86sra.d", + @"x86sra.h", + @"x86sra.w", + @"x86srai.b", + @"x86srai.d", + @"x86srai.h", + @"x86srai.w", + @"x86srl.b", + @"x86srl.d", + @"x86srl.h", + @"x86srl.w", + @"x86srli.b", + @"x86srli.d", + @"x86srli.h", + @"x86srli.w", + @"x86sub.b", + @"x86sub.d", + @"x86sub.du", + @"x86sub.h", + @"x86sub.w", + @"x86sub.wu", + @"x86xor.b", + @"x86xor.d", + @"x86xor.h", + @"x86xor.w", + xor, + xori, + @"xvabsd.b", + @"xvabsd.bu", + @"xvabsd.d", + @"xvabsd.du", + @"xvabsd.h", + @"xvabsd.hu", + @"xvabsd.w", + @"xvabsd.wu", + @"xvadd.b", + @"xvadd.d", + @"xvadd.h", + @"xvadd.q", + @"xvadd.w", + @"xvadda.b", + @"xvadda.d", + @"xvadda.h", + @"xvadda.w", + @"xvaddi.bu", + @"xvaddi.du", + @"xvaddi.hu", + @"xvaddi.wu", + @"xvaddwev.d.w", + @"xvaddwev.d.wu", + @"xvaddwev.d.wu.w", + @"xvaddwev.h.b", + @"xvaddwev.h.bu", + @"xvaddwev.h.bu.b", + @"xvaddwev.q.d", + @"xvaddwev.q.du", + @"xvaddwev.q.du.d", + @"xvaddwev.w.h", + @"xvaddwev.w.hu", + @"xvaddwev.w.hu.h", + @"xvaddwod.d.w", + @"xvaddwod.d.wu", + @"xvaddwod.d.wu.w", + @"xvaddwod.h.b", + @"xvaddwod.h.bu", + @"xvaddwod.h.bu.b", + @"xvaddwod.q.d", + @"xvaddwod.q.du", + @"xvaddwod.q.du.d", + @"xvaddwod.w.h", + @"xvaddwod.w.hu", + @"xvaddwod.w.hu.h", + @"xvand.v", + @"xvandi.b", + @"xvandn.v", + @"xvavg.b", + @"xvavg.bu", + @"xvavg.d", + @"xvavg.du", + @"xvavg.h", + @"xvavg.hu", + @"xvavg.w", + @"xvavg.wu", + @"xvavgr.b", + @"xvavgr.bu", + @"xvavgr.d", + @"xvavgr.du", + @"xvavgr.h", + @"xvavgr.hu", + @"xvavgr.w", + @"xvavgr.wu", + @"xvbitclr.b", + @"xvbitclr.d", + @"xvbitclr.h", + @"xvbitclr.w", + @"xvbitclri.b", + @"xvbitclri.d", + @"xvbitclri.h", + @"xvbitclri.w", + @"xvbitrev.b", + @"xvbitrev.d", + @"xvbitrev.h", + @"xvbitrev.w", + @"xvbitrevi.b", + @"xvbitrevi.d", + @"xvbitrevi.h", + @"xvbitrevi.w", + @"xvbitsel.v", + @"xvbitseli.b", + @"xvbitset.b", + @"xvbitset.d", + @"xvbitset.h", + @"xvbitset.w", + @"xvbitseti.b", + @"xvbitseti.d", + @"xvbitseti.h", + @"xvbitseti.w", + @"xvbsll.v", + @"xvbsrl.v", + @"xvclo.b", + @"xvclo.d", + @"xvclo.h", + @"xvclo.w", + @"xvclz.b", + @"xvclz.d", + @"xvclz.h", + @"xvclz.w", + @"xvdiv.b", + @"xvdiv.bu", + @"xvdiv.d", + @"xvdiv.du", + @"xvdiv.h", + @"xvdiv.hu", + @"xvdiv.w", + @"xvdiv.wu", + @"xvexth.d.w", + @"xvexth.du.wu", + @"xvexth.h.b", + @"xvexth.hu.bu", + @"xvexth.q.d", + @"xvexth.qu.du", + @"xvexth.w.h", + @"xvexth.wu.hu", + @"xvextl.q.d", + @"xvextl.qu.du", + @"xvextrins.b", + @"xvextrins.d", + @"xvextrins.h", + @"xvextrins.w", + @"xvfadd.d", + @"xvfadd.s", + @"xvfclass.d", + @"xvfclass.s", + @"xvfcmp.caf.d", + @"xvfcmp.caf.s", + @"xvfcmp.ceq.d", + @"xvfcmp.ceq.s", + @"xvfcmp.cle.d", + @"xvfcmp.cle.s", + @"xvfcmp.clt.d", + @"xvfcmp.clt.s", + @"xvfcmp.cne.d", + @"xvfcmp.cne.s", + @"xvfcmp.cor.d", + @"xvfcmp.cor.s", + @"xvfcmp.cueq.d", + @"xvfcmp.cueq.s", + @"xvfcmp.cule.d", + @"xvfcmp.cule.s", + @"xvfcmp.cult.d", + @"xvfcmp.cult.s", + @"xvfcmp.cun.d", + @"xvfcmp.cun.s", + @"xvfcmp.cune.d", + @"xvfcmp.cune.s", + @"xvfcmp.saf.d", + @"xvfcmp.saf.s", + @"xvfcmp.seq.d", + @"xvfcmp.seq.s", + @"xvfcmp.sle.d", + @"xvfcmp.sle.s", + @"xvfcmp.slt.d", + @"xvfcmp.slt.s", + @"xvfcmp.sne.d", + @"xvfcmp.sne.s", + @"xvfcmp.sor.d", + @"xvfcmp.sor.s", + @"xvfcmp.sueq.d", + @"xvfcmp.sueq.s", + @"xvfcmp.sule.d", + @"xvfcmp.sule.s", + @"xvfcmp.sult.d", + @"xvfcmp.sult.s", + @"xvfcmp.sun.d", + @"xvfcmp.sun.s", + @"xvfcmp.sune.d", + @"xvfcmp.sune.s", + @"xvfcvt.h.s", + @"xvfcvt.s.d", + @"xvfcvth.d.s", + @"xvfcvth.s.h", + @"xvfcvtl.d.s", + @"xvfcvtl.s.h", + @"xvfdiv.d", + @"xvfdiv.s", + @"xvffint.d.l", + @"xvffint.d.lu", + @"xvffint.s.l", + @"xvffint.s.w", + @"xvffint.s.wu", + @"xvffinth.d.w", + @"xvffintl.d.w", + @"xvflogb.d", + @"xvflogb.s", + @"xvfmadd.d", + @"xvfmadd.s", + @"xvfmax.d", + @"xvfmax.s", + @"xvfmaxa.d", + @"xvfmaxa.s", + @"xvfmin.d", + @"xvfmin.s", + @"xvfmina.d", + @"xvfmina.s", + @"xvfmsub.d", + @"xvfmsub.s", + @"xvfmul.d", + @"xvfmul.s", + @"xvfnmadd.d", + @"xvfnmadd.s", + @"xvfnmsub.d", + @"xvfnmsub.s", + @"xvfrecip.d", + @"xvfrecip.s", + @"xvfrecipe.d", + @"xvfrecipe.s", + @"xvfrint.d", + @"xvfrint.s", + @"xvfrintrm.d", + @"xvfrintrm.s", + @"xvfrintrne.d", + @"xvfrintrne.s", + @"xvfrintrp.d", + @"xvfrintrp.s", + @"xvfrintrz.d", + @"xvfrintrz.s", + @"xvfrsqrt.d", + @"xvfrsqrt.s", + @"xvfrsqrte.d", + @"xvfrsqrte.s", + @"xvfrstp.b", + @"xvfrstp.h", + @"xvfrstpi.b", + @"xvfrstpi.h", + @"xvfsqrt.d", + @"xvfsqrt.s", + @"xvfsub.d", + @"xvfsub.s", + @"xvftint.l.d", + @"xvftint.lu.d", + @"xvftint.w.d", + @"xvftint.w.s", + @"xvftint.wu.s", + @"xvftinth.l.s", + @"xvftintl.l.s", + @"xvftintrm.l.d", + @"xvftintrm.w.d", + @"xvftintrm.w.s", + @"xvftintrmh.l.s", + @"xvftintrml.l.s", + @"xvftintrne.l.d", + @"xvftintrne.w.d", + @"xvftintrne.w.s", + @"xvftintrneh.l.s", + @"xvftintrnel.l.s", + @"xvftintrp.l.d", + @"xvftintrp.w.d", + @"xvftintrp.w.s", + @"xvftintrph.l.s", + @"xvftintrpl.l.s", + @"xvftintrz.l.d", + @"xvftintrz.lu.d", + @"xvftintrz.w.d", + @"xvftintrz.w.s", + @"xvftintrz.wu.s", + @"xvftintrzh.l.s", + @"xvftintrzl.l.s", + @"xvhaddw.d.w", + @"xvhaddw.du.wu", + @"xvhaddw.h.b", + @"xvhaddw.hu.bu", + @"xvhaddw.q.d", + @"xvhaddw.qu.du", + @"xvhaddw.w.h", + @"xvhaddw.wu.hu", + @"xvhsubw.d.w", + @"xvhsubw.du.wu", + @"xvhsubw.h.b", + @"xvhsubw.hu.bu", + @"xvhsubw.q.d", + @"xvhsubw.qu.du", + @"xvhsubw.w.h", + @"xvhsubw.wu.hu", + @"xvilvh.b", + @"xvilvh.d", + @"xvilvh.h", + @"xvilvh.w", + @"xvilvl.b", + @"xvilvl.d", + @"xvilvl.h", + @"xvilvl.w", + @"xvinsgr2vr.d", + @"xvinsgr2vr.w", + @"xvinsve0.d", + @"xvinsve0.w", + xvld, + xvldi, + @"xvldrepl.b", + @"xvldrepl.d", + @"xvldrepl.h", + @"xvldrepl.w", + xvldx, + @"xvmadd.b", + @"xvmadd.d", + @"xvmadd.h", + @"xvmadd.w", + @"xvmaddwev.d.w", + @"xvmaddwev.d.wu", + @"xvmaddwev.d.wu.w", + @"xvmaddwev.h.b", + @"xvmaddwev.h.bu", + @"xvmaddwev.h.bu.b", + @"xvmaddwev.q.d", + @"xvmaddwev.q.du", + @"xvmaddwev.q.du.d", + @"xvmaddwev.w.h", + @"xvmaddwev.w.hu", + @"xvmaddwev.w.hu.h", + @"xvmaddwod.d.w", + @"xvmaddwod.d.wu", + @"xvmaddwod.d.wu.w", + @"xvmaddwod.h.b", + @"xvmaddwod.h.bu", + @"xvmaddwod.h.bu.b", + @"xvmaddwod.q.d", + @"xvmaddwod.q.du", + @"xvmaddwod.q.du.d", + @"xvmaddwod.w.h", + @"xvmaddwod.w.hu", + @"xvmaddwod.w.hu.h", + @"xvmax.b", + @"xvmax.bu", + @"xvmax.d", + @"xvmax.du", + @"xvmax.h", + @"xvmax.hu", + @"xvmax.w", + @"xvmax.wu", + @"xvmaxi.b", + @"xvmaxi.bu", + @"xvmaxi.d", + @"xvmaxi.du", + @"xvmaxi.h", + @"xvmaxi.hu", + @"xvmaxi.w", + @"xvmaxi.wu", + @"xvmepatmsk.v", + @"xvmin.b", + @"xvmin.bu", + @"xvmin.d", + @"xvmin.du", + @"xvmin.h", + @"xvmin.hu", + @"xvmin.w", + @"xvmin.wu", + @"xvmini.b", + @"xvmini.bu", + @"xvmini.d", + @"xvmini.du", + @"xvmini.h", + @"xvmini.hu", + @"xvmini.w", + @"xvmini.wu", + @"xvmod.b", + @"xvmod.bu", + @"xvmod.d", + @"xvmod.du", + @"xvmod.h", + @"xvmod.hu", + @"xvmod.w", + @"xvmod.wu", + @"xvmskgez.b", + @"xvmskltz.b", + @"xvmskltz.d", + @"xvmskltz.h", + @"xvmskltz.w", + @"xvmsknz.b", + @"xvmsub.b", + @"xvmsub.d", + @"xvmsub.h", + @"xvmsub.w", + @"xvmuh.b", + @"xvmuh.bu", + @"xvmuh.d", + @"xvmuh.du", + @"xvmuh.h", + @"xvmuh.hu", + @"xvmuh.w", + @"xvmuh.wu", + @"xvmul.b", + @"xvmul.d", + @"xvmul.h", + @"xvmul.w", + @"xvmulwev.d.w", + @"xvmulwev.d.wu", + @"xvmulwev.d.wu.w", + @"xvmulwev.h.b", + @"xvmulwev.h.bu", + @"xvmulwev.h.bu.b", + @"xvmulwev.q.d", + @"xvmulwev.q.du", + @"xvmulwev.q.du.d", + @"xvmulwev.w.h", + @"xvmulwev.w.hu", + @"xvmulwev.w.hu.h", + @"xvmulwod.d.w", + @"xvmulwod.d.wu", + @"xvmulwod.d.wu.w", + @"xvmulwod.h.b", + @"xvmulwod.h.bu", + @"xvmulwod.h.bu.b", + @"xvmulwod.q.d", + @"xvmulwod.q.du", + @"xvmulwod.q.du.d", + @"xvmulwod.w.h", + @"xvmulwod.w.hu", + @"xvmulwod.w.hu.h", + @"xvneg.b", + @"xvneg.d", + @"xvneg.h", + @"xvneg.w", + @"xvnor.v", + @"xvnori.b", + @"xvor.v", + @"xvori.b", + @"xvorn.v", + @"xvpackev.b", + @"xvpackev.d", + @"xvpackev.h", + @"xvpackev.w", + @"xvpackod.b", + @"xvpackod.d", + @"xvpackod.h", + @"xvpackod.w", + @"xvpcnt.b", + @"xvpcnt.d", + @"xvpcnt.h", + @"xvpcnt.w", + @"xvperm.w", + @"xvpermi.d", + @"xvpermi.q", + @"xvpermi.w", + @"xvpickev.b", + @"xvpickev.d", + @"xvpickev.h", + @"xvpickev.w", + @"xvpickod.b", + @"xvpickod.d", + @"xvpickod.h", + @"xvpickod.w", + @"xvpickve.d", + @"xvpickve.w", + @"xvpickve2gr.d", + @"xvpickve2gr.du", + @"xvpickve2gr.w", + @"xvpickve2gr.wu", + @"xvrepl128vei.b", + @"xvrepl128vei.d", + @"xvrepl128vei.h", + @"xvrepl128vei.w", + @"xvreplgr2vr.b", + @"xvreplgr2vr.d", + @"xvreplgr2vr.h", + @"xvreplgr2vr.w", + @"xvreplve.b", + @"xvreplve.d", + @"xvreplve.h", + @"xvreplve.w", + @"xvreplve0.b", + @"xvreplve0.d", + @"xvreplve0.h", + @"xvreplve0.q", + @"xvreplve0.w", + @"xvrotr.b", + @"xvrotr.d", + @"xvrotr.h", + @"xvrotr.w", + @"xvrotri.b", + @"xvrotri.d", + @"xvrotri.h", + @"xvrotri.w", + @"xvsadd.b", + @"xvsadd.bu", + @"xvsadd.d", + @"xvsadd.du", + @"xvsadd.h", + @"xvsadd.hu", + @"xvsadd.w", + @"xvsadd.wu", + @"xvsat.b", + @"xvsat.bu", + @"xvsat.d", + @"xvsat.du", + @"xvsat.h", + @"xvsat.hu", + @"xvsat.w", + @"xvsat.wu", + @"xvseq.b", + @"xvseq.d", + @"xvseq.h", + @"xvseq.w", + @"xvseqi.b", + @"xvseqi.d", + @"xvseqi.h", + @"xvseqi.w", + @"xvsetallnez.b", + @"xvsetallnez.d", + @"xvsetallnez.h", + @"xvsetallnez.w", + @"xvsetanyeqz.b", + @"xvsetanyeqz.d", + @"xvsetanyeqz.h", + @"xvsetanyeqz.w", + @"xvseteqz.v", + @"xvsetnez.v", + @"xvshuf.b", + @"xvshuf.d", + @"xvshuf.h", + @"xvshuf.w", + @"xvshuf4i.b", + @"xvshuf4i.d", + @"xvshuf4i.h", + @"xvshuf4i.w", + @"xvsigncov.b", + @"xvsigncov.d", + @"xvsigncov.h", + @"xvsigncov.w", + @"xvsle.b", + @"xvsle.bu", + @"xvsle.d", + @"xvsle.du", + @"xvsle.h", + @"xvsle.hu", + @"xvsle.w", + @"xvsle.wu", + @"xvslei.b", + @"xvslei.bu", + @"xvslei.d", + @"xvslei.du", + @"xvslei.h", + @"xvslei.hu", + @"xvslei.w", + @"xvslei.wu", + @"xvsll.b", + @"xvsll.d", + @"xvsll.h", + @"xvsll.w", + @"xvslli.b", + @"xvslli.d", + @"xvslli.h", + @"xvslli.w", + @"xvsllwil.d.w", + @"xvsllwil.du.wu", + @"xvsllwil.h.b", + @"xvsllwil.hu.bu", + @"xvsllwil.w.h", + @"xvsllwil.wu.hu", + @"xvslt.b", + @"xvslt.bu", + @"xvslt.d", + @"xvslt.du", + @"xvslt.h", + @"xvslt.hu", + @"xvslt.w", + @"xvslt.wu", + @"xvslti.b", + @"xvslti.bu", + @"xvslti.d", + @"xvslti.du", + @"xvslti.h", + @"xvslti.hu", + @"xvslti.w", + @"xvslti.wu", + @"xvsra.b", + @"xvsra.d", + @"xvsra.h", + @"xvsra.w", + @"xvsrai.b", + @"xvsrai.d", + @"xvsrai.h", + @"xvsrai.w", + @"xvsran.b.h", + @"xvsran.h.w", + @"xvsran.w.d", + @"xvsrani.b.h", + @"xvsrani.d.q", + @"xvsrani.h.w", + @"xvsrani.w.d", + @"xvsrar.b", + @"xvsrar.d", + @"xvsrar.h", + @"xvsrar.w", + @"xvsrari.b", + @"xvsrari.d", + @"xvsrari.h", + @"xvsrari.w", + @"xvsrarn.b.h", + @"xvsrarn.h.w", + @"xvsrarn.w.d", + @"xvsrarni.b.h", + @"xvsrarni.d.q", + @"xvsrarni.h.w", + @"xvsrarni.w.d", + @"xvsrl.b", + @"xvsrl.d", + @"xvsrl.h", + @"xvsrl.w", + @"xvsrli.b", + @"xvsrli.d", + @"xvsrli.h", + @"xvsrli.w", + @"xvsrln.b.h", + @"xvsrln.h.w", + @"xvsrln.w.d", + @"xvsrlni.b.h", + @"xvsrlni.d.q", + @"xvsrlni.h.w", + @"xvsrlni.w.d", + @"xvsrlr.b", + @"xvsrlr.d", + @"xvsrlr.h", + @"xvsrlr.w", + @"xvsrlri.b", + @"xvsrlri.d", + @"xvsrlri.h", + @"xvsrlri.w", + @"xvsrlrn.b.h", + @"xvsrlrn.h.w", + @"xvsrlrn.w.d", + @"xvsrlrni.b.h", + @"xvsrlrni.d.q", + @"xvsrlrni.h.w", + @"xvsrlrni.w.d", + @"xvssran.b.h", + @"xvssran.bu.h", + @"xvssran.h.w", + @"xvssran.hu.w", + @"xvssran.w.d", + @"xvssran.wu.d", + @"xvssrani.b.h", + @"xvssrani.bu.h", + @"xvssrani.d.q", + @"xvssrani.du.q", + @"xvssrani.h.w", + @"xvssrani.hu.w", + @"xvssrani.w.d", + @"xvssrani.wu.d", + @"xvssrarn.b.h", + @"xvssrarn.bu.h", + @"xvssrarn.h.w", + @"xvssrarn.hu.w", + @"xvssrarn.w.d", + @"xvssrarn.wu.d", + @"xvssrarni.b.h", + @"xvssrarni.bu.h", + @"xvssrarni.d.q", + @"xvssrarni.du.q", + @"xvssrarni.h.w", + @"xvssrarni.hu.w", + @"xvssrarni.w.d", + @"xvssrarni.wu.d", + @"xvssrln.b.h", + @"xvssrln.bu.h", + @"xvssrln.h.w", + @"xvssrln.hu.w", + @"xvssrln.w.d", + @"xvssrln.wu.d", + @"xvssrlni.b.h", + @"xvssrlni.bu.h", + @"xvssrlni.d.q", + @"xvssrlni.du.q", + @"xvssrlni.h.w", + @"xvssrlni.hu.w", + @"xvssrlni.w.d", + @"xvssrlni.wu.d", + @"xvssrlrn.b.h", + @"xvssrlrn.bu.h", + @"xvssrlrn.h.w", + @"xvssrlrn.hu.w", + @"xvssrlrn.w.d", + @"xvssrlrn.wu.d", + @"xvssrlrni.b.h", + @"xvssrlrni.bu.h", + @"xvssrlrni.d.q", + @"xvssrlrni.du.q", + @"xvssrlrni.h.w", + @"xvssrlrni.hu.w", + @"xvssrlrni.w.d", + @"xvssrlrni.wu.d", + @"xvssub.b", + @"xvssub.bu", + @"xvssub.d", + @"xvssub.du", + @"xvssub.h", + @"xvssub.hu", + @"xvssub.w", + @"xvssub.wu", + xvst, + @"xvstelm.b", + @"xvstelm.d", + @"xvstelm.h", + @"xvstelm.w", + xvstx, + @"xvsub.b", + @"xvsub.d", + @"xvsub.h", + @"xvsub.q", + @"xvsub.w", + @"xvsubi.bu", + @"xvsubi.du", + @"xvsubi.hu", + @"xvsubi.wu", + @"xvsubwev.d.w", + @"xvsubwev.d.wu", + @"xvsubwev.h.b", + @"xvsubwev.h.bu", + @"xvsubwev.q.d", + @"xvsubwev.q.du", + @"xvsubwev.w.h", + @"xvsubwev.w.hu", + @"xvsubwod.d.w", + @"xvsubwod.d.wu", + @"xvsubwod.h.b", + @"xvsubwod.h.bu", + @"xvsubwod.q.d", + @"xvsubwod.q.du", + @"xvsubwod.w.h", + @"xvsubwod.w.hu", + @"xvxor.v", + @"xvxori.b", + @"xxx.unknown.1", +}; + +pub const Instruction = packed union { + word: u32, + /// Fields of a `CdFj` instruction. + CdFj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CdFjFk` instruction. + CdFjFk: packed struct { rd: u3, funct3: u2, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `CdJ` instruction. + CdJ: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CdVj` instruction. + CdVj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CdXj` instruction. + CdXj: packed struct { rd: u3, funct3: u2, rj: u5, funct10: u22 }, + /// Fields of a `CjSd5k16` instruction. + CjSd5k16: packed struct { si5: i5, rj: u3, funct8: u2, si16: i16, funct26: u6 }, + /// Fields of a `CjSd5k16ps2` instruction. + CjSd5k16ps2: packed struct { si5: i5, rj: u3, funct8: u2, si16: i16, funct26: u6 }, + /// Fields of a `D` instruction. + D: packed struct { rd: u5, funct5: u27 }, + /// Fields of a `DCj` instruction. + DCj: packed struct { rd: u5, rj: u3, funct8: u24 }, + /// Fields of a `DFj` instruction. + DFj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `DJ` instruction. + DJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `DJK` instruction. + DJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `DJKUa2` instruction. + DJKUa2: packed struct { rd: u5, rj: u5, rk: u5, ui2: u2, funct17: u15 }, + /// Fields of a `DJKUa2pp1` instruction. + DJKUa2pp1: packed struct { rd: u5, rj: u5, rk: u5, ui2: u2, funct17: u15 }, + /// Fields of a `DJKUa3` instruction. + DJKUa3: packed struct { rd: u5, rj: u5, rk: u5, ui3: u3, funct18: u14 }, + /// Fields of a `DJSk12` instruction. + DJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `DJSk14` instruction. + DJSk14: packed struct { rd: u5, rj: u5, si14: i14, funct24: u8 }, + /// Fields of a `DJSk14ps2` instruction. + DJSk14ps2: packed struct { rd: u5, rj: u5, si14: i14, funct24: u8 }, + /// Fields of a `DJSk16` instruction. + DJSk16: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `DJSk16ps2` instruction. + DJSk16ps2: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `DJSk5` instruction. + DJSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 }, + /// Fields of a `DJUk12` instruction. + DJUk12: packed struct { rd: u5, rj: u5, ui12: u12, funct22: u10 }, + /// Fields of a `DJUk14` instruction. + DJUk14: packed struct { rd: u5, rj: u5, ui14: u14, funct24: u8 }, + /// Fields of a `DJUk3` instruction. + DJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `DJUk4` instruction. + DJUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `DJUk5` instruction. + DJUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `DJUk5Um5` instruction. + DJUk5Um5: packed struct { rd: u5, rj: u5, imm10: u5, funct15: u1, imm16: u5, funct21: u11 }, + /// Fields of a `DJUk6` instruction. + DJUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `DJUk6Um6` instruction. + DJUk6Um6: packed struct { rd: u5, rj: u5, imm10: u6, imm16: u6, funct22: u10 }, + /// Fields of a `DJUk8` instruction. + DJUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `DJUm5Uk5` instruction. + DJUm5Uk5: packed struct { rd: u5, rj: u5, imm10: u5, funct15: u1, imm16: u5, funct21: u11 }, + /// Fields of a `DJUm6Uk6` instruction. + DJUm6Uk6: packed struct { rd: u5, rj: u5, imm10: u6, imm16: u6, funct22: u10 }, + /// Fields of a `DKJ` instruction. + DKJ: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `DSj20` instruction. + DSj20: packed struct { rd: u5, si20: i20, funct25: u7 }, + /// Fields of a `DTj` instruction. + DTj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `DUj5` instruction. + DUj5: packed struct { rd: u5, ui5: u5, funct10: u22 }, + /// Fields of a `DUj5Uk8` instruction. + DUj5Uk8: packed struct { rd: u5, ui5: u5, ui8: u8, funct18: u14 }, + /// Fields of a `DUk14` instruction. + DUk14: packed struct { rd: u5, funct5: u5, ui14: u14, funct24: u8 }, + /// Fields of a `DUk4` instruction. + DUk4: packed struct { rd: u5, funct5: u5, ui4: u4, funct14: u18 }, + /// Fields of a `DUk8` instruction. + DUk8: packed struct { rd: u5, funct5: u5, ui8: u8, funct18: u14 }, + /// Fields of a `DVjUk1` instruction. + DVjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `DVjUk2` instruction. + DVjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `DVjUk3` instruction. + DVjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `DVjUk4` instruction. + DVjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `DXjUk2` instruction. + DXjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `DXjUk3` instruction. + DXjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `FdCj` instruction. + FdCj: packed struct { rd: u5, rj: u3, funct8: u24 }, + /// Fields of a `FdFj` instruction. + FdFj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `FdFjFk` instruction. + FdFjFk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `FdFjFkCa` instruction. + FdFjFkCa: packed struct { rd: u5, rj: u5, rk: u5, ra: u3, funct18: u14 }, + /// Fields of a `FdFjFkFa` instruction. + FdFjFkFa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 }, + /// Fields of a `FdJ` instruction. + FdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `FdJK` instruction. + FdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `FdJSk12` instruction. + FdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `J` instruction. + J: packed struct { funct0: u5, rj: u5, funct10: u22 }, + /// Fields of a `JDSk16ps2` instruction. + JDSk16ps2: packed struct { rd: u5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `JK` instruction. + JK: packed struct { funct0: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `JKUd4` instruction. + JKUd4: packed struct { ui4: u4, funct4: u1, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `JKUd5` instruction. + JKUd5: packed struct { ui5: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `JSd5k16` instruction. + JSd5k16: packed struct { si5: i5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `JSd5k16ps2` instruction. + JSd5k16ps2: packed struct { si5: i5, rj: u5, si16: i16, funct26: u6 }, + /// Fields of a `JUd4Uk5` instruction. + JUd4Uk5: packed struct { ui4: u4, funct4: u1, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `JUd5` instruction. + JUd5: packed struct { ui5: u5, rj: u5, funct10: u22 }, + /// Fields of a `JUd5Sk12` instruction. + JUd5Sk12: packed struct { ui5: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `JUk3` instruction. + JUk3: packed struct { funct0: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `JUk4` instruction. + JUk4: packed struct { funct0: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `JUk5` instruction. + JUk5: packed struct { funct0: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `JUk5Ud4` instruction. + JUk5Ud4: packed struct { ui4: u4, funct4: u1, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `JUk6` instruction. + JUk6: packed struct { funct0: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `JUk8` instruction. + JUk8: packed struct { funct0: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `Sd10k16` instruction. + Sd10k16: packed struct { si10: i10, si16: i16, funct26: u6 }, + /// Fields of a `Sd10k16ps2` instruction. + Sd10k16ps2: packed struct { si10: i10, si16: i16, funct26: u6 }, + /// Fields of a `Sd5k16` instruction. + Sd5k16: packed struct { si5: i5, funct5: u5, si16: i16, funct26: u6 }, + /// Fields of a `Sd5k16ps2` instruction. + Sd5k16ps2: packed struct { si5: i5, funct5: u5, si16: i16, funct26: u6 }, + /// Fields of a `TdJ` instruction. + TdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `Ud15` instruction. + Ud15: packed struct { ui15: u15, funct15: u17 }, + /// Fields of a `Ud5JK` instruction. + Ud5JK: packed struct { ui5: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `Ud5JSk12` instruction. + Ud5JSk12: packed struct { ui5: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `Uj3` instruction. + Uj3: packed struct { funct0: u5, ui3: u3, funct8: u24 }, + /// Fields of a `VdJ` instruction. + VdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `VdJK` instruction. + VdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `VdJSk10` instruction. + VdJSk10: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `VdJSk10ps2` instruction. + VdJSk10ps2: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `VdJSk11` instruction. + VdJSk11: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `VdJSk11ps1` instruction. + VdJSk11ps1: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `VdJSk12` instruction. + VdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `VdJSk8Un1` instruction. + VdJSk8Un1: packed struct { rd: u5, rj: u5, si8: i8, ui1: u1, funct19: u13 }, + /// Fields of a `VdJSk8Un2` instruction. + VdJSk8Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `VdJSk8Un3` instruction. + VdJSk8Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `VdJSk8Un4` instruction. + VdJSk8Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 }, + /// Fields of a `VdJSk8ps1Un3` instruction. + VdJSk8ps1Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `VdJSk8ps2Un2` instruction. + VdJSk8ps2Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `VdJSk8ps3Un1` instruction. + VdJSk8ps3Un1: packed struct { rd: u5, rj: u5, si8: i8, ui1: u1, funct19: u13 }, + /// Fields of a `VdJSk9` instruction. + VdJSk9: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `VdJSk9ps3` instruction. + VdJSk9ps3: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `VdJUk1` instruction. + VdJUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `VdJUk2` instruction. + VdJUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `VdJUk3` instruction. + VdJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `VdJUk4` instruction. + VdJUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `VdSj13` instruction. + VdSj13: packed struct { rd: u5, si13: i13, funct18: u14 }, + /// Fields of a `VdUj5Uk5` instruction. + VdUj5Uk5: packed struct { rd: u5, imm5: u5, imm10: u5, funct15: u17 }, + /// Fields of a `VdVj` instruction. + VdVj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `VdVjK` instruction. + VdVjK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `VdVjSk5` instruction. + VdVjSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 }, + /// Fields of a `VdVjUk1` instruction. + VdVjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `VdVjUk2` instruction. + VdVjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `VdVjUk3` instruction. + VdVjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `VdVjUk4` instruction. + VdVjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `VdVjUk5` instruction. + VdVjUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `VdVjUk6` instruction. + VdVjUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `VdVjUk7` instruction. + VdVjUk7: packed struct { rd: u5, rj: u5, ui7: u7, funct17: u15 }, + /// Fields of a `VdVjUk8` instruction. + VdVjUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `VdVjVk` instruction. + VdVjVk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `VdVjVkVa` instruction. + VdVjVkVa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 }, + /// Fields of a `XdJ` instruction. + XdJ: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `XdJK` instruction. + XdJK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `XdJSk10` instruction. + XdJSk10: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `XdJSk10ps2` instruction. + XdJSk10ps2: packed struct { rd: u5, rj: u5, si10: i10, funct20: u12 }, + /// Fields of a `XdJSk11` instruction. + XdJSk11: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `XdJSk11ps1` instruction. + XdJSk11ps1: packed struct { rd: u5, rj: u5, si11: i11, funct21: u11 }, + /// Fields of a `XdJSk12` instruction. + XdJSk12: packed struct { rd: u5, rj: u5, si12: i12, funct22: u10 }, + /// Fields of a `XdJSk8Un2` instruction. + XdJSk8Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `XdJSk8Un3` instruction. + XdJSk8Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `XdJSk8Un4` instruction. + XdJSk8Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 }, + /// Fields of a `XdJSk8Un5` instruction. + XdJSk8Un5: packed struct { rd: u5, rj: u5, si8: i8, ui5: u5, funct23: u9 }, + /// Fields of a `XdJSk8ps1Un4` instruction. + XdJSk8ps1Un4: packed struct { rd: u5, rj: u5, si8: i8, ui4: u4, funct22: u10 }, + /// Fields of a `XdJSk8ps2Un3` instruction. + XdJSk8ps2Un3: packed struct { rd: u5, rj: u5, si8: i8, ui3: u3, funct21: u11 }, + /// Fields of a `XdJSk8ps3Un2` instruction. + XdJSk8ps3Un2: packed struct { rd: u5, rj: u5, si8: i8, ui2: u2, funct20: u12 }, + /// Fields of a `XdJSk9` instruction. + XdJSk9: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `XdJSk9ps3` instruction. + XdJSk9ps3: packed struct { rd: u5, rj: u5, si9: i9, funct19: u13 }, + /// Fields of a `XdJUk2` instruction. + XdJUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `XdJUk3` instruction. + XdJUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `XdSj13` instruction. + XdSj13: packed struct { rd: u5, si13: i13, funct18: u14 }, + /// Fields of a `XdUj5Uk5` instruction. + XdUj5Uk5: packed struct { rd: u5, imm5: u5, imm10: u5, funct15: u17 }, + /// Fields of a `XdXj` instruction. + XdXj: packed struct { rd: u5, rj: u5, funct10: u22 }, + /// Fields of a `XdXjK` instruction. + XdXjK: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `XdXjSk5` instruction. + XdXjSk5: packed struct { rd: u5, rj: u5, si5: i5, funct15: u17 }, + /// Fields of a `XdXjUk1` instruction. + XdXjUk1: packed struct { rd: u5, rj: u5, ui1: u1, funct11: u21 }, + /// Fields of a `XdXjUk2` instruction. + XdXjUk2: packed struct { rd: u5, rj: u5, ui2: u2, funct12: u20 }, + /// Fields of a `XdXjUk3` instruction. + XdXjUk3: packed struct { rd: u5, rj: u5, ui3: u3, funct13: u19 }, + /// Fields of a `XdXjUk4` instruction. + XdXjUk4: packed struct { rd: u5, rj: u5, ui4: u4, funct14: u18 }, + /// Fields of a `XdXjUk5` instruction. + XdXjUk5: packed struct { rd: u5, rj: u5, ui5: u5, funct15: u17 }, + /// Fields of a `XdXjUk6` instruction. + XdXjUk6: packed struct { rd: u5, rj: u5, ui6: u6, funct16: u16 }, + /// Fields of a `XdXjUk7` instruction. + XdXjUk7: packed struct { rd: u5, rj: u5, ui7: u7, funct17: u15 }, + /// Fields of a `XdXjUk8` instruction. + XdXjUk8: packed struct { rd: u5, rj: u5, ui8: u8, funct18: u14 }, + /// Fields of a `XdXjXk` instruction. + XdXjXk: packed struct { rd: u5, rj: u5, rk: u5, funct15: u17 }, + /// Fields of a `XdXjXkXa` instruction. + XdXjXkXa: packed struct { rd: u5, rj: u5, rk: u5, ra: u5, funct20: u12 }, + + /// Encodes a `CdFj` instruction. + pub inline fn encodeCdFj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CdFjFk` instruction. + pub inline fn encodeCdFjFk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `CdJ` instruction. + pub inline fn encodeCdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CdVj` instruction. + pub inline fn encodeCdVj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CdXj` instruction. + pub inline fn encodeCdXj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `CjSd5k16` instruction. + pub inline fn encodeCjSd5k16(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `CjSd5k16ps2` instruction. + pub inline fn encodeCjSd5k16ps2(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `D` instruction. + pub inline fn encodeD(word: u32, p0: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) }; + } + + /// Encodes a `DCj` instruction. + pub inline fn encodeDCj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DFj` instruction. + pub inline fn encodeDFj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DJ` instruction. + pub inline fn encodeDJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DJK` instruction. + pub inline fn encodeDJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `DJKUa2` instruction. + pub inline fn encodeDJKUa2(word: u32, p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 15) }; + } + + /// Encodes a `DJKUa2pp1` instruction. + pub inline fn encodeDJKUa2pp1(word: u32, p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + ((@as(u32, @as(u2, @bitCast(p3))) - 1) << 15) }; + } + + /// Encodes a `DJKUa3` instruction. + pub inline fn encodeDJKUa3(word: u32, p0: Register, p1: Register, p2: Register, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 15) }; + } + + /// Encodes a `DJSk12` instruction. + pub inline fn encodeDJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJSk14` instruction. + pub inline fn encodeDJSk14(word: u32, p0: Register, p1: Register, p2: i14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u14, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJSk14ps2` instruction. + pub inline fn encodeDJSk14ps2(word: u32, p0: Register, p1: Register, p2: i14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u14, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `DJSk16` instruction. + pub inline fn encodeDJSk16(word: u32, p0: Register, p1: Register, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u16, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJSk16ps2` instruction. + pub inline fn encodeDJSk16ps2(word: u32, p0: Register, p1: Register, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `DJSk5` instruction. + pub inline fn encodeDJSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk12` instruction. + pub inline fn encodeDJUk12(word: u32, p0: Register, p1: Register, p2: u12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk14` instruction. + pub inline fn encodeDJUk14(word: u32, p0: Register, p1: Register, p2: u14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u14, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk3` instruction. + pub inline fn encodeDJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk4` instruction. + pub inline fn encodeDJUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk5` instruction. + pub inline fn encodeDJUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk5Um5` instruction. + pub inline fn encodeDJUk5Um5(word: u32, p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u5, @bitCast(p3)))) << 16) }; + } + + /// Encodes a `DJUk6` instruction. + pub inline fn encodeDJUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUk6Um6` instruction. + pub inline fn encodeDJUk6Um6(word: u32, p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u6, @bitCast(p3)))) << 16) }; + } + + /// Encodes a `DJUk8` instruction. + pub inline fn encodeDJUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DJUm5Uk5` instruction. + pub inline fn encodeDJUm5Uk5(word: u32, p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 16) | + ((@as(u32, @as(u5, @bitCast(p3)))) << 10) }; + } + + /// Encodes a `DJUm6Uk6` instruction. + pub inline fn encodeDJUm6Uk6(word: u32, p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 16) | + ((@as(u32, @as(u6, @bitCast(p3)))) << 10) }; + } + + /// Encodes a `DKJ` instruction. + pub inline fn encodeDKJ(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 10) | + (@as(u32, p2.encode()) << 5) }; + } + + /// Encodes a `DSj20` instruction. + pub inline fn encodeDSj20(word: u32, p0: Register, p1: i20) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u20, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `DTj` instruction. + pub inline fn encodeDTj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `DUj5` instruction. + pub inline fn encodeDUj5(word: u32, p0: Register, p1: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `DUj5Uk8` instruction. + pub inline fn encodeDUj5Uk8(word: u32, p0: Register, p1: u5, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DUk14` instruction. + pub inline fn encodeDUk14(word: u32, p0: Register, p1: u14) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u14, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `DUk4` instruction. + pub inline fn encodeDUk4(word: u32, p0: Register, p1: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u4, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `DUk8` instruction. + pub inline fn encodeDUk8(word: u32, p0: Register, p1: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u8, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `DVjUk1` instruction. + pub inline fn encodeDVjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DVjUk2` instruction. + pub inline fn encodeDVjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DVjUk3` instruction. + pub inline fn encodeDVjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DVjUk4` instruction. + pub inline fn encodeDVjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DXjUk2` instruction. + pub inline fn encodeDXjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `DXjUk3` instruction. + pub inline fn encodeDXjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `EMPTY` instruction. + pub inline fn encodeEMPTY(word: u32) Instruction { + return .{ .word = word }; + } + + /// Encodes a `FdCj` instruction. + pub inline fn encodeFdCj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `FdFj` instruction. + pub inline fn encodeFdFj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `FdFjFk` instruction. + pub inline fn encodeFdFjFk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `FdFjFkCa` instruction. + pub inline fn encodeFdFjFkCa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `FdFjFkFa` instruction. + pub inline fn encodeFdFjFkFa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `FdJ` instruction. + pub inline fn encodeFdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `FdJK` instruction. + pub inline fn encodeFdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `FdJSk12` instruction. + pub inline fn encodeFdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `J` instruction. + pub inline fn encodeJ(word: u32, p0: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) }; + } + + /// Encodes a `JDSk16ps2` instruction. + pub inline fn encodeJDSk16ps2(word: u32, p0: Register, p1: Register, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 0) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `JK` instruction. + pub inline fn encodeJK(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 10) }; + } + + /// Encodes a `JKUd4` instruction. + pub inline fn encodeJKUd4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 10) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 0) }; + } + + /// Encodes a `JKUd5` instruction. + pub inline fn encodeJKUd5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + (@as(u32, p1.encode()) << 10) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 0) }; + } + + /// Encodes a `JSd5k16` instruction. + pub inline fn encodeJSd5k16(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `JSd5k16ps2` instruction. + pub inline fn encodeJSd5k16ps2(word: u32, p0: Register, p1: i5, p2: i16) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `JUd4Uk5` instruction. + pub inline fn encodeJUd4Uk5(word: u32, p0: Register, p1: u4, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `JUd5` instruction. + pub inline fn encodeJUd5(word: u32, p0: Register, p1: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) }; + } + + /// Encodes a `JUd5Sk12` instruction. + pub inline fn encodeJUd5Sk12(word: u32, p0: Register, p1: u5, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 0) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `JUk3` instruction. + pub inline fn encodeJUk3(word: u32, p0: Register, p1: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk4` instruction. + pub inline fn encodeJUk4(word: u32, p0: Register, p1: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk5` instruction. + pub inline fn encodeJUk5(word: u32, p0: Register, p1: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk5Ud4` instruction. + pub inline fn encodeJUk5Ud4(word: u32, p0: Register, p1: u5, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 10) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 0) }; + } + + /// Encodes a `JUk6` instruction. + pub inline fn encodeJUk6(word: u32, p0: Register, p1: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `JUk8` instruction. + pub inline fn encodeJUk8(word: u32, p0: Register, p1: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `Sd10k16` instruction. + pub inline fn encodeSd10k16(word: u32, p0: i10, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u10, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `Sd10k16ps2` instruction. + pub inline fn encodeSd10k16ps2(word: u32, p0: i10, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u10, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1))) >> 2) << 10) }; + } + + /// Encodes a `Sd5k16` instruction. + pub inline fn encodeSd5k16(word: u32, p0: i5, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1)))) << 10) }; + } + + /// Encodes a `Sd5k16ps2` instruction. + pub inline fn encodeSd5k16ps2(word: u32, p0: i5, p1: i16) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + ((@as(u32, @as(u16, @bitCast(p1))) >> 2) << 10) }; + } + + /// Encodes a `TdJ` instruction. + pub inline fn encodeTdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `Ud15` instruction. + pub inline fn encodeUd15(word: u32, p0: u15) Instruction { + return .{ .word = word | + ((@as(u32, @as(u15, @bitCast(p0)))) << 0) }; + } + + /// Encodes a `Ud5JK` instruction. + pub inline fn encodeUd5JK(word: u32, p0: u5, p1: Register, p2: Register) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `Ud5JSk12` instruction. + pub inline fn encodeUd5JSk12(word: u32, p0: u5, p1: Register, p2: i12) Instruction { + return .{ .word = word | + ((@as(u32, @as(u5, @bitCast(p0)))) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `Uj3` instruction. + pub inline fn encodeUj3(word: u32, p0: u3) Instruction { + return .{ .word = word | + ((@as(u32, @as(u3, @bitCast(p0)))) << 5) }; + } + + /// Encodes a `VdJ` instruction. + pub inline fn encodeVdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `VdJK` instruction. + pub inline fn encodeVdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `VdJSk10` instruction. + pub inline fn encodeVdJSk10(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk10ps2` instruction. + pub inline fn encodeVdJSk10ps2(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `VdJSk11` instruction. + pub inline fn encodeVdJSk11(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk11ps1` instruction. + pub inline fn encodeVdJSk11ps1(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2))) >> 1) << 10) }; + } + + /// Encodes a `VdJSk12` instruction. + pub inline fn encodeVdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk8Un1` instruction. + pub inline fn encodeVdJSk8Un1(word: u32, p0: Register, p1: Register, p2: i8, p3: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u1, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8Un2` instruction. + pub inline fn encodeVdJSk8Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8Un3` instruction. + pub inline fn encodeVdJSk8Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8Un4` instruction. + pub inline fn encodeVdJSk8Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u4, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8ps1Un3` instruction. + pub inline fn encodeVdJSk8ps1Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 1) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8ps2Un2` instruction. + pub inline fn encodeVdJSk8ps2Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 2) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk8ps3Un1` instruction. + pub inline fn encodeVdJSk8ps3Un1(word: u32, p0: Register, p1: Register, p2: i8, p3: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 3) << 10) | + ((@as(u32, @as(u1, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `VdJSk9` instruction. + pub inline fn encodeVdJSk9(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJSk9ps3` instruction. + pub inline fn encodeVdJSk9ps3(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2))) >> 3) << 10) }; + } + + /// Encodes a `VdJUk1` instruction. + pub inline fn encodeVdJUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJUk2` instruction. + pub inline fn encodeVdJUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJUk3` instruction. + pub inline fn encodeVdJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdJUk4` instruction. + pub inline fn encodeVdJUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdSj13` instruction. + pub inline fn encodeVdSj13(word: u32, p0: Register, p1: i13) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u13, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `VdUj5Uk5` instruction. + pub inline fn encodeVdUj5Uk5(word: u32, p0: Register, p1: u5, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVj` instruction. + pub inline fn encodeVdVj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `VdVjK` instruction. + pub inline fn encodeVdVjK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `VdVjSk5` instruction. + pub inline fn encodeVdVjSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk1` instruction. + pub inline fn encodeVdVjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk2` instruction. + pub inline fn encodeVdVjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk3` instruction. + pub inline fn encodeVdVjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk4` instruction. + pub inline fn encodeVdVjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk5` instruction. + pub inline fn encodeVdVjUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk6` instruction. + pub inline fn encodeVdVjUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk7` instruction. + pub inline fn encodeVdVjUk7(word: u32, p0: Register, p1: Register, p2: u7) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u7, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjUk8` instruction. + pub inline fn encodeVdVjUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `VdVjVk` instruction. + pub inline fn encodeVdVjVk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `VdVjVkVa` instruction. + pub inline fn encodeVdVjVkVa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `XdJ` instruction. + pub inline fn encodeXdJ(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `XdJK` instruction. + pub inline fn encodeXdJK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `XdJSk10` instruction. + pub inline fn encodeXdJSk10(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk10ps2` instruction. + pub inline fn encodeXdJSk10ps2(word: u32, p0: Register, p1: Register, p2: i10) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u10, @bitCast(p2))) >> 2) << 10) }; + } + + /// Encodes a `XdJSk11` instruction. + pub inline fn encodeXdJSk11(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk11ps1` instruction. + pub inline fn encodeXdJSk11ps1(word: u32, p0: Register, p1: Register, p2: i11) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u11, @bitCast(p2))) >> 1) << 10) }; + } + + /// Encodes a `XdJSk12` instruction. + pub inline fn encodeXdJSk12(word: u32, p0: Register, p1: Register, p2: i12) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u12, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk8Un2` instruction. + pub inline fn encodeXdJSk8Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8Un3` instruction. + pub inline fn encodeXdJSk8Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8Un4` instruction. + pub inline fn encodeXdJSk8Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u4, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8Un5` instruction. + pub inline fn encodeXdJSk8Un5(word: u32, p0: Register, p1: Register, p2: i8, p3: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) | + ((@as(u32, @as(u5, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8ps1Un4` instruction. + pub inline fn encodeXdJSk8ps1Un4(word: u32, p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 1) << 10) | + ((@as(u32, @as(u4, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8ps2Un3` instruction. + pub inline fn encodeXdJSk8ps2Un3(word: u32, p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 2) << 10) | + ((@as(u32, @as(u3, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk8ps3Un2` instruction. + pub inline fn encodeXdJSk8ps3Un2(word: u32, p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2))) >> 3) << 10) | + ((@as(u32, @as(u2, @bitCast(p3)))) << 18) }; + } + + /// Encodes a `XdJSk9` instruction. + pub inline fn encodeXdJSk9(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJSk9ps3` instruction. + pub inline fn encodeXdJSk9ps3(word: u32, p0: Register, p1: Register, p2: i9) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u9, @bitCast(p2))) >> 3) << 10) }; + } + + /// Encodes a `XdJUk2` instruction. + pub inline fn encodeXdJUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdJUk3` instruction. + pub inline fn encodeXdJUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdSj13` instruction. + pub inline fn encodeXdSj13(word: u32, p0: Register, p1: i13) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u13, @bitCast(p1)))) << 5) }; + } + + /// Encodes a `XdUj5Uk5` instruction. + pub inline fn encodeXdUj5Uk5(word: u32, p0: Register, p1: u5, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + ((@as(u32, @as(u5, @bitCast(p1)))) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXj` instruction. + pub inline fn encodeXdXj(word: u32, p0: Register, p1: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) }; + } + + /// Encodes a `XdXjK` instruction. + pub inline fn encodeXdXjK(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `XdXjSk5` instruction. + pub inline fn encodeXdXjSk5(word: u32, p0: Register, p1: Register, p2: i5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk1` instruction. + pub inline fn encodeXdXjUk1(word: u32, p0: Register, p1: Register, p2: u1) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u1, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk2` instruction. + pub inline fn encodeXdXjUk2(word: u32, p0: Register, p1: Register, p2: u2) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u2, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk3` instruction. + pub inline fn encodeXdXjUk3(word: u32, p0: Register, p1: Register, p2: u3) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u3, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk4` instruction. + pub inline fn encodeXdXjUk4(word: u32, p0: Register, p1: Register, p2: u4) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u4, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk5` instruction. + pub inline fn encodeXdXjUk5(word: u32, p0: Register, p1: Register, p2: u5) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u5, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk6` instruction. + pub inline fn encodeXdXjUk6(word: u32, p0: Register, p1: Register, p2: u6) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u6, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk7` instruction. + pub inline fn encodeXdXjUk7(word: u32, p0: Register, p1: Register, p2: u7) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u7, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjUk8` instruction. + pub inline fn encodeXdXjUk8(word: u32, p0: Register, p1: Register, p2: u8) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + ((@as(u32, @as(u8, @bitCast(p2)))) << 10) }; + } + + /// Encodes a `XdXjXk` instruction. + pub inline fn encodeXdXjXk(word: u32, p0: Register, p1: Register, p2: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) }; + } + + /// Encodes a `XdXjXkXa` instruction. + pub inline fn encodeXdXjXkXa(word: u32, p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return .{ .word = word | + (@as(u32, p0.encode()) << 0) | + (@as(u32, p1.encode()) << 5) | + (@as(u32, p2.encode()) << 10) | + (@as(u32, p3.encode()) << 15) }; + } + + /// Encodes a `adc.b` instruction (requires 64bit). + pub inline fn @"adc.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00300000, p0, p1, p2); + } + + /// Encodes a `adc.d` instruction (requires 64bit). + pub inline fn @"adc.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00318000, p0, p1, p2); + } + + /// Encodes a `adc.h` instruction (requires 64bit). + pub inline fn @"adc.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00308000, p0, p1, p2); + } + + /// Encodes a `adc.w` instruction (requires 64bit). + pub inline fn @"adc.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00310000, p0, p1, p2); + } + + /// Encodes a `add.d` instruction (requires 64bit). + pub inline fn @"add.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00108000, p0, p1, p2); + } + + /// Encodes a `add.w` instruction (requires 32bit). + pub inline fn @"add.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00100000, p0, p1, p2); + } + + /// Encodes a `addi.d` instruction (requires 64bit). + pub inline fn @"addi.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02c00000, p0, p1, p2); + } + + /// Encodes a `addi.w` instruction (requires 32bit). + pub inline fn @"addi.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02800000, p0, p1, p2); + } + + /// Encodes a `addu12i.d` instruction (requires 64bit). + pub inline fn @"addu12i.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeDJSk5(0x00298000, p0, p1, p2); + } + + /// Encodes a `addu12i.w` instruction (requires 64bit). + pub inline fn @"addu12i.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeDJSk5(0x00290000, p0, p1, p2); + } + + /// Encodes a `addu16i.d` instruction (requires 64bit). + pub inline fn @"addu16i.d"(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x10000000, p0, p1, p2); + } + + /// Encodes a `amadd.b` instruction (requires 64bit). + pub inline fn @"amadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385d0000, p0, p1, p2); + } + + /// Encodes a `amadd.d` instruction (requires 64bit). + pub inline fn @"amadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38618000, p0, p1, p2); + } + + /// Encodes a `amadd.h` instruction (requires 64bit). + pub inline fn @"amadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385d8000, p0, p1, p2); + } + + /// Encodes a `amadd.w` instruction (requires 64bit). + pub inline fn @"amadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38610000, p0, p1, p2); + } + + /// Encodes a `amadd_db.b` instruction (requires 64bit). + pub inline fn @"amadd_db.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385f0000, p0, p1, p2); + } + + /// Encodes a `amadd_db.d` instruction (requires 64bit). + pub inline fn @"amadd_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386a8000, p0, p1, p2); + } + + /// Encodes a `amadd_db.h` instruction (requires 64bit). + pub inline fn @"amadd_db.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385f8000, p0, p1, p2); + } + + /// Encodes a `amadd_db.w` instruction (requires 64bit). + pub inline fn @"amadd_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386a0000, p0, p1, p2); + } + + /// Encodes a `amand.d` instruction (requires 64bit). + pub inline fn @"amand.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38628000, p0, p1, p2); + } + + /// Encodes a `amand.w` instruction (requires 64bit). + pub inline fn @"amand.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38620000, p0, p1, p2); + } + + /// Encodes a `amand_db.d` instruction (requires 64bit). + pub inline fn @"amand_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386b8000, p0, p1, p2); + } + + /// Encodes a `amand_db.w` instruction (requires 64bit). + pub inline fn @"amand_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386b0000, p0, p1, p2); + } + + /// Encodes a `amcas.b` instruction (requires 64bit). + pub inline fn @"amcas.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38580000, p0, p1, p2); + } + + /// Encodes a `amcas.d` instruction (requires 64bit). + pub inline fn @"amcas.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38598000, p0, p1, p2); + } + + /// Encodes a `amcas.h` instruction (requires 64bit). + pub inline fn @"amcas.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38588000, p0, p1, p2); + } + + /// Encodes a `amcas.w` instruction (requires 64bit). + pub inline fn @"amcas.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38590000, p0, p1, p2); + } + + /// Encodes a `amcas_db.b` instruction (requires 64bit). + pub inline fn @"amcas_db.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385a0000, p0, p1, p2); + } + + /// Encodes a `amcas_db.d` instruction (requires 64bit). + pub inline fn @"amcas_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385b8000, p0, p1, p2); + } + + /// Encodes a `amcas_db.h` instruction (requires 64bit). + pub inline fn @"amcas_db.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385a8000, p0, p1, p2); + } + + /// Encodes a `amcas_db.w` instruction (requires 64bit). + pub inline fn @"amcas_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385b0000, p0, p1, p2); + } + + /// Encodes a `ammax.d` instruction (requires 64bit). + pub inline fn @"ammax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38658000, p0, p1, p2); + } + + /// Encodes a `ammax.du` instruction (requires 64bit). + pub inline fn @"ammax.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38678000, p0, p1, p2); + } + + /// Encodes a `ammax.w` instruction (requires 64bit). + pub inline fn @"ammax.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38650000, p0, p1, p2); + } + + /// Encodes a `ammax.wu` instruction (requires 64bit). + pub inline fn @"ammax.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38670000, p0, p1, p2); + } + + /// Encodes a `ammax_db.d` instruction (requires 64bit). + pub inline fn @"ammax_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386e8000, p0, p1, p2); + } + + /// Encodes a `ammax_db.du` instruction (requires 64bit). + pub inline fn @"ammax_db.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38708000, p0, p1, p2); + } + + /// Encodes a `ammax_db.w` instruction (requires 64bit). + pub inline fn @"ammax_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386e0000, p0, p1, p2); + } + + /// Encodes a `ammax_db.wu` instruction (requires 64bit). + pub inline fn @"ammax_db.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38700000, p0, p1, p2); + } + + /// Encodes a `ammin.d` instruction (requires 64bit). + pub inline fn @"ammin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38668000, p0, p1, p2); + } + + /// Encodes a `ammin.du` instruction (requires 64bit). + pub inline fn @"ammin.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38688000, p0, p1, p2); + } + + /// Encodes a `ammin.w` instruction (requires 64bit). + pub inline fn @"ammin.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38660000, p0, p1, p2); + } + + /// Encodes a `ammin.wu` instruction (requires 64bit). + pub inline fn @"ammin.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38680000, p0, p1, p2); + } + + /// Encodes a `ammin_db.d` instruction (requires 64bit). + pub inline fn @"ammin_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386f8000, p0, p1, p2); + } + + /// Encodes a `ammin_db.du` instruction (requires 64bit). + pub inline fn @"ammin_db.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38718000, p0, p1, p2); + } + + /// Encodes a `ammin_db.w` instruction (requires 64bit). + pub inline fn @"ammin_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386f0000, p0, p1, p2); + } + + /// Encodes a `ammin_db.wu` instruction (requires 64bit). + pub inline fn @"ammin_db.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38710000, p0, p1, p2); + } + + /// Encodes a `amor.d` instruction (requires 64bit). + pub inline fn @"amor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38638000, p0, p1, p2); + } + + /// Encodes a `amor.w` instruction (requires 64bit). + pub inline fn @"amor.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38630000, p0, p1, p2); + } + + /// Encodes a `amor_db.d` instruction (requires 64bit). + pub inline fn @"amor_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386c8000, p0, p1, p2); + } + + /// Encodes a `amor_db.w` instruction (requires 64bit). + pub inline fn @"amor_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386c0000, p0, p1, p2); + } + + /// Encodes a `amswap.b` instruction (requires 64bit). + pub inline fn @"amswap.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385c0000, p0, p1, p2); + } + + /// Encodes a `amswap.d` instruction (requires 64bit). + pub inline fn @"amswap.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38608000, p0, p1, p2); + } + + /// Encodes a `amswap.h` instruction (requires 64bit). + pub inline fn @"amswap.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385c8000, p0, p1, p2); + } + + /// Encodes a `amswap.w` instruction (requires 64bit). + pub inline fn @"amswap.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38600000, p0, p1, p2); + } + + /// Encodes a `amswap_db.b` instruction (requires 64bit). + pub inline fn @"amswap_db.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385e0000, p0, p1, p2); + } + + /// Encodes a `amswap_db.d` instruction (requires 64bit). + pub inline fn @"amswap_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38698000, p0, p1, p2); + } + + /// Encodes a `amswap_db.h` instruction (requires 64bit). + pub inline fn @"amswap_db.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x385e8000, p0, p1, p2); + } + + /// Encodes a `amswap_db.w` instruction (requires 64bit). + pub inline fn @"amswap_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38690000, p0, p1, p2); + } + + /// Encodes a `amxor.d` instruction (requires 64bit). + pub inline fn @"amxor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38648000, p0, p1, p2); + } + + /// Encodes a `amxor.w` instruction (requires 64bit). + pub inline fn @"amxor.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38640000, p0, p1, p2); + } + + /// Encodes a `amxor_db.d` instruction (requires 64bit). + pub inline fn @"amxor_db.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386d8000, p0, p1, p2); + } + + /// Encodes a `amxor_db.w` instruction (requires 64bit). + pub inline fn @"amxor_db.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x386d0000, p0, p1, p2); + } + + /// Encodes a `and` instruction (requires 32bit). + pub inline fn @"and"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00148000, p0, p1, p2); + } + + /// Encodes a `andi` instruction (requires 32bit). + pub inline fn andi(p0: Register, p1: Register, p2: u12) Instruction { + return encodeDJUk12(0x03400000, p0, p1, p2); + } + + /// Encodes a `andn` instruction (requires 32bit). + pub inline fn andn(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00168000, p0, p1, p2); + } + + /// Encodes a `armadc.w` instruction (requires 64bit). + pub inline fn @"armadc.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00380010, p0, p1, p2); + } + + /// Encodes a `armadd.w` instruction (requires 64bit). + pub inline fn @"armadd.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00370010, p0, p1, p2); + } + + /// Encodes a `armand.w` instruction (requires 64bit). + pub inline fn @"armand.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00390010, p0, p1, p2); + } + + /// Encodes a `armmfflag` instruction (requires 64bit). + pub inline fn armmfflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0040, p0, p1); + } + + /// Encodes a `armmov.d` instruction (requires 64bit). + pub inline fn @"armmov.d"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01e, p0, p1); + } + + /// Encodes a `armmov.w` instruction (requires 64bit). + pub inline fn @"armmov.w"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01d, p0, p1); + } + + /// Encodes a `armmove` instruction (requires 64bit). + pub inline fn armmove(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDJUk4(0x00364000, p0, p1, p2); + } + + /// Encodes a `armmtflag` instruction (requires 64bit). + pub inline fn armmtflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0060, p0, p1); + } + + /// Encodes a `armnot.w` instruction (requires 64bit). + pub inline fn @"armnot.w"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01c, p0, p1); + } + + /// Encodes a `armor.w` instruction (requires 64bit). + pub inline fn @"armor.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00398010, p0, p1, p2); + } + + /// Encodes a `armrotr.w` instruction (requires 64bit). + pub inline fn @"armrotr.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003c0010, p0, p1, p2); + } + + /// Encodes a `armrotri.w` instruction (requires 64bit). + pub inline fn @"armrotri.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003e0010, p0, p1, p2); + } + + /// Encodes a `armrrx.w` instruction (requires 64bit). + pub inline fn @"armrrx.w"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x003fc01f, p0, p1); + } + + /// Encodes a `armsbc.w` instruction (requires 64bit). + pub inline fn @"armsbc.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00388010, p0, p1, p2); + } + + /// Encodes a `armsetj` instruction (requires 64bit). + pub inline fn armsetj(p0: Register, p1: u4) Instruction { + return encodeDUk4(0x0036c000, p0, p1); + } + + /// Encodes a `armsll.w` instruction (requires 64bit). + pub inline fn @"armsll.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003a8010, p0, p1, p2); + } + + /// Encodes a `armslli.w` instruction (requires 64bit). + pub inline fn @"armslli.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003c8010, p0, p1, p2); + } + + /// Encodes a `armsra.w` instruction (requires 64bit). + pub inline fn @"armsra.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003b8010, p0, p1, p2); + } + + /// Encodes a `armsrai.w` instruction (requires 64bit). + pub inline fn @"armsrai.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003d8010, p0, p1, p2); + } + + /// Encodes a `armsrl.w` instruction (requires 64bit). + pub inline fn @"armsrl.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003b0010, p0, p1, p2); + } + + /// Encodes a `armsrli.w` instruction (requires 64bit). + pub inline fn @"armsrli.w"(p0: Register, p1: u5, p2: u4) Instruction { + return encodeJUk5Ud4(0x003d0010, p0, p1, p2); + } + + /// Encodes a `armsub.w` instruction (requires 64bit). + pub inline fn @"armsub.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x00378010, p0, p1, p2); + } + + /// Encodes a `armxor.w` instruction (requires 64bit). + pub inline fn @"armxor.w"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeJKUd4(0x003a0010, p0, p1, p2); + } + + /// Encodes a `asrtgt` instruction (requires 64bit). + pub inline fn asrtgt(p0: Register, p1: Register) Instruction { + return encodeJK(0x00018000, p0, p1); + } + + /// Encodes a `asrtle` instruction (requires 64bit). + pub inline fn asrtle(p0: Register, p1: Register) Instruction { + return encodeJK(0x00010000, p0, p1); + } + + /// Encodes a `b` instruction (requires 32bit). + pub inline fn b(p0: i10, p1: i16) Instruction { + return encodeSd10k16ps2(0x50000000, p0, p1); + } + + /// Encodes a `bceqz` instruction (requires f). + pub inline fn bceqz(p0: Register, p1: i5, p2: i16) Instruction { + return encodeCjSd5k16ps2(0x48000000, p0, p1, p2); + } + + /// Encodes a `bcnez` instruction (requires f). + pub inline fn bcnez(p0: Register, p1: i5, p2: i16) Instruction { + return encodeCjSd5k16ps2(0x48000100, p0, p1, p2); + } + + /// Encodes a `beq` instruction (requires 32bit). + pub inline fn beq(p0: Register, p1: Register, p2: i16) Instruction { + return encodeJDSk16ps2(0x58000000, p0, p1, p2); + } + + /// Encodes a `beqz` instruction (requires 32s). + pub inline fn beqz(p0: Register, p1: i5, p2: i16) Instruction { + return encodeJSd5k16ps2(0x40000000, p0, p1, p2); + } + + /// Encodes a `bgt` instruction (requires 32bit). + pub inline fn bgt(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x60000000, p0, p1, p2); + } + + /// Encodes a `bgtu` instruction (requires 32bit). + pub inline fn bgtu(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x68000000, p0, p1, p2); + } + + /// Encodes a `bl` instruction (requires 32bit). + pub inline fn bl(p0: i10, p1: i16) Instruction { + return encodeSd10k16ps2(0x54000000, p0, p1); + } + + /// Encodes a `ble` instruction (requires 32bit). + pub inline fn ble(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x64000000, p0, p1, p2); + } + + /// Encodes a `bleu` instruction (requires 32bit). + pub inline fn bleu(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16(0x6c000000, p0, p1, p2); + } + + /// Encodes a `bne` instruction (requires 32bit). + pub inline fn bne(p0: Register, p1: Register, p2: i16) Instruction { + return encodeJDSk16ps2(0x5c000000, p0, p1, p2); + } + + /// Encodes a `bnez` instruction (requires 32s). + pub inline fn bnez(p0: Register, p1: i5, p2: i16) Instruction { + return encodeJSd5k16ps2(0x44000000, p0, p1, p2); + } + + /// Encodes a `break` instruction (requires 32bit). + pub inline fn @"break"(p0: u15) Instruction { + return encodeUd15(0x002a0000, p0); + } + + /// Encodes a `bstrins.d` instruction (requires 64bit). + pub inline fn @"bstrins.d"(p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return encodeDJUm6Uk6(0x00800000, p0, p1, p2, p3); + } + + /// Encodes a `bstrins.w` instruction (requires 32s). + pub inline fn @"bstrins.w"(p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return encodeDJUm5Uk5(0x00600000, p0, p1, p2, p3); + } + + /// Encodes a `bstrpick.d` instruction (requires 64bit). + pub inline fn @"bstrpick.d"(p0: Register, p1: Register, p2: u6, p3: u6) Instruction { + return encodeDJUm6Uk6(0x00c00000, p0, p1, p2, p3); + } + + /// Encodes a `bstrpick.w` instruction (requires 32s). + pub inline fn @"bstrpick.w"(p0: Register, p1: Register, p2: u5, p3: u5) Instruction { + return encodeDJUm5Uk5(0x00608000, p0, p1, p2, p3); + } + + /// Encodes a `cacop` instruction (requires 32bit). + pub inline fn cacop(p0: u5, p1: Register, p2: i12) Instruction { + return encodeUd5JSk12(0x06000000, p0, p1, p2); + } + + /// Encodes a `catpick.d` instruction (requires 64bit). + pub inline fn @"catpick.d"(p0: Register, p1: Register, p2: Register, p3: u3) Instruction { + return encodeDJKUa3(0x000c0000, p0, p1, p2, p3); + } + + /// Encodes a `catpick.w` instruction (requires 32s). + pub inline fn @"catpick.w"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x00080000, p0, p1, p2, p3); + } + + /// Encodes a `clo.d` instruction (requires 64bit). + pub inline fn @"clo.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002000, p0, p1); + } + + /// Encodes a `clo.w` instruction (requires 32s). + pub inline fn @"clo.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001000, p0, p1); + } + + /// Encodes a `clz.d` instruction (requires 64bit). + pub inline fn @"clz.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002400, p0, p1); + } + + /// Encodes a `clz.w` instruction (requires 32s). + pub inline fn @"clz.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001400, p0, p1); + } + + /// Encodes a `cpucfg` instruction (requires 32s). + pub inline fn cpucfg(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006c00, p0, p1); + } + + /// Encodes a `crc.w.b.w` instruction (requires 64bit). + pub inline fn @"crc.w.b.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00240000, p0, p1, p2); + } + + /// Encodes a `crc.w.d.w` instruction (requires 64bit). + pub inline fn @"crc.w.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00258000, p0, p1, p2); + } + + /// Encodes a `crc.w.h.w` instruction (requires 64bit). + pub inline fn @"crc.w.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00248000, p0, p1, p2); + } + + /// Encodes a `crc.w.w.w` instruction (requires 64bit). + pub inline fn @"crc.w.w.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00250000, p0, p1, p2); + } + + /// Encodes a `crcc.w.b.w` instruction (requires 64bit). + pub inline fn @"crcc.w.b.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00260000, p0, p1, p2); + } + + /// Encodes a `crcc.w.d.w` instruction (requires 64bit). + pub inline fn @"crcc.w.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00278000, p0, p1, p2); + } + + /// Encodes a `crcc.w.h.w` instruction (requires 64bit). + pub inline fn @"crcc.w.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00268000, p0, p1, p2); + } + + /// Encodes a `crcc.w.w.w` instruction (requires 64bit). + pub inline fn @"crcc.w.w.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00270000, p0, p1, p2); + } + + /// Encodes a `csrrd` instruction (requires 32bit). + pub inline fn csrrd(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x04000000, p0, p1); + } + + /// Encodes a `csrwr` instruction (requires 32bit). + pub inline fn csrwr(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x04000032, p0, p1); + } + + /// Encodes a `csrxchg` instruction (requires 32bit). + pub inline fn csrxchg(p0: Register, p1: Register, p2: u14) Instruction { + return encodeDJUk14(0x04000000, p0, p1, p2); + } + + /// Encodes a `cto.d` instruction (requires 64bit). + pub inline fn @"cto.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002800, p0, p1); + } + + /// Encodes a `cto.w` instruction (requires 32s). + pub inline fn @"cto.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001800, p0, p1); + } + + /// Encodes a `ctz.d` instruction (requires 64bit). + pub inline fn @"ctz.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00002c00, p0, p1); + } + + /// Encodes a `ctz.w` instruction (requires 32s). + pub inline fn @"ctz.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00001c00, p0, p1); + } + + /// Encodes a `cu32i.d` instruction (requires 64bit). + pub inline fn @"cu32i.d"(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x16000000, p0, p1); + } + + /// Encodes a `cu52i.d` instruction (requires 64bit). + pub inline fn @"cu52i.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x03000000, p0, p1, p2); + } + + /// Encodes a `dbar` instruction (requires 32bit). + pub inline fn dbar(p0: u15) Instruction { + return encodeUd15(0x38720000, p0); + } + + /// Encodes a `dbgcall` instruction (requires 64bit). + pub inline fn dbgcall(p0: u15) Instruction { + return encodeUd15(0x002a8000, p0); + } + + /// Encodes a `div.d` instruction (requires 64bit). + pub inline fn @"div.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00220000, p0, p1, p2); + } + + /// Encodes a `div.du` instruction (requires 64bit). + pub inline fn @"div.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00230000, p0, p1, p2); + } + + /// Encodes a `div.w` instruction (requires 32bit). + pub inline fn @"div.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00200000, p0, p1, p2); + } + + /// Encodes a `div.wu` instruction (requires 32bit). + pub inline fn @"div.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00210000, p0, p1, p2); + } + + /// Encodes a `eret` instruction (requires 32bit). + pub inline fn eret() Instruction { + return encodeEMPTY(0x06483800); + } + + /// Encodes a `fabs.d` instruction (requires f). + pub inline fn @"fabs.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01140800, p0, p1); + } + + /// Encodes a `fabs.s` instruction (requires f). + pub inline fn @"fabs.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01140400, p0, p1); + } + + /// Encodes a `fadd.d` instruction (requires f). + pub inline fn @"fadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01010000, p0, p1, p2); + } + + /// Encodes a `fadd.s` instruction (requires f). + pub inline fn @"fadd.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01008000, p0, p1, p2); + } + + /// Encodes a `fclass.d` instruction (requires f). + pub inline fn @"fclass.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01143800, p0, p1); + } + + /// Encodes a `fclass.s` instruction (requires f). + pub inline fn @"fclass.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01143400, p0, p1); + } + + /// Encodes a `fcmp.caf.d` instruction (requires f). + pub inline fn @"fcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c200000, p0, p1, p2); + } + + /// Encodes a `fcmp.caf.s` instruction (requires f). + pub inline fn @"fcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c100000, p0, p1, p2); + } + + /// Encodes a `fcmp.ceq.d` instruction (requires f). + pub inline fn @"fcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c220000, p0, p1, p2); + } + + /// Encodes a `fcmp.ceq.s` instruction (requires f). + pub inline fn @"fcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c120000, p0, p1, p2); + } + + /// Encodes a `fcmp.cle.d` instruction (requires f). + pub inline fn @"fcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c230000, p0, p1, p2); + } + + /// Encodes a `fcmp.cle.s` instruction (requires f). + pub inline fn @"fcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c130000, p0, p1, p2); + } + + /// Encodes a `fcmp.clt.d` instruction (requires f). + pub inline fn @"fcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c210000, p0, p1, p2); + } + + /// Encodes a `fcmp.clt.s` instruction (requires f). + pub inline fn @"fcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c110000, p0, p1, p2); + } + + /// Encodes a `fcmp.cne.d` instruction (requires f). + pub inline fn @"fcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c280000, p0, p1, p2); + } + + /// Encodes a `fcmp.cne.s` instruction (requires f). + pub inline fn @"fcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c180000, p0, p1, p2); + } + + /// Encodes a `fcmp.cor.d` instruction (requires f). + pub inline fn @"fcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2a0000, p0, p1, p2); + } + + /// Encodes a `fcmp.cor.s` instruction (requires f). + pub inline fn @"fcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1a0000, p0, p1, p2); + } + + /// Encodes a `fcmp.cueq.d` instruction (requires f). + pub inline fn @"fcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c260000, p0, p1, p2); + } + + /// Encodes a `fcmp.cueq.s` instruction (requires f). + pub inline fn @"fcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c160000, p0, p1, p2); + } + + /// Encodes a `fcmp.cule.d` instruction (requires f). + pub inline fn @"fcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c270000, p0, p1, p2); + } + + /// Encodes a `fcmp.cule.s` instruction (requires f). + pub inline fn @"fcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c170000, p0, p1, p2); + } + + /// Encodes a `fcmp.cult.d` instruction (requires f). + pub inline fn @"fcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c250000, p0, p1, p2); + } + + /// Encodes a `fcmp.cult.s` instruction (requires f). + pub inline fn @"fcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c150000, p0, p1, p2); + } + + /// Encodes a `fcmp.cun.d` instruction (requires f). + pub inline fn @"fcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c240000, p0, p1, p2); + } + + /// Encodes a `fcmp.cun.s` instruction (requires f). + pub inline fn @"fcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c140000, p0, p1, p2); + } + + /// Encodes a `fcmp.cune.d` instruction (requires f). + pub inline fn @"fcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2c0000, p0, p1, p2); + } + + /// Encodes a `fcmp.cune.s` instruction (requires f). + pub inline fn @"fcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1c0000, p0, p1, p2); + } + + /// Encodes a `fcmp.saf.d` instruction (requires f). + pub inline fn @"fcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c208000, p0, p1, p2); + } + + /// Encodes a `fcmp.saf.s` instruction (requires f). + pub inline fn @"fcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c108000, p0, p1, p2); + } + + /// Encodes a `fcmp.seq.d` instruction (requires f). + pub inline fn @"fcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c228000, p0, p1, p2); + } + + /// Encodes a `fcmp.seq.s` instruction (requires f). + pub inline fn @"fcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c128000, p0, p1, p2); + } + + /// Encodes a `fcmp.sle.d` instruction (requires f). + pub inline fn @"fcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c238000, p0, p1, p2); + } + + /// Encodes a `fcmp.sle.s` instruction (requires f). + pub inline fn @"fcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c138000, p0, p1, p2); + } + + /// Encodes a `fcmp.slt.d` instruction (requires f). + pub inline fn @"fcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c218000, p0, p1, p2); + } + + /// Encodes a `fcmp.slt.s` instruction (requires f). + pub inline fn @"fcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c118000, p0, p1, p2); + } + + /// Encodes a `fcmp.sne.d` instruction (requires f). + pub inline fn @"fcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c288000, p0, p1, p2); + } + + /// Encodes a `fcmp.sne.s` instruction (requires f). + pub inline fn @"fcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c188000, p0, p1, p2); + } + + /// Encodes a `fcmp.sor.d` instruction (requires f). + pub inline fn @"fcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2a8000, p0, p1, p2); + } + + /// Encodes a `fcmp.sor.s` instruction (requires f). + pub inline fn @"fcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1a8000, p0, p1, p2); + } + + /// Encodes a `fcmp.sueq.d` instruction (requires f). + pub inline fn @"fcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c268000, p0, p1, p2); + } + + /// Encodes a `fcmp.sueq.s` instruction (requires f). + pub inline fn @"fcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c168000, p0, p1, p2); + } + + /// Encodes a `fcmp.sule.d` instruction (requires f). + pub inline fn @"fcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c278000, p0, p1, p2); + } + + /// Encodes a `fcmp.sule.s` instruction (requires f). + pub inline fn @"fcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c178000, p0, p1, p2); + } + + /// Encodes a `fcmp.sult.d` instruction (requires f). + pub inline fn @"fcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c258000, p0, p1, p2); + } + + /// Encodes a `fcmp.sult.s` instruction (requires f). + pub inline fn @"fcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c158000, p0, p1, p2); + } + + /// Encodes a `fcmp.sun.d` instruction (requires f). + pub inline fn @"fcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c248000, p0, p1, p2); + } + + /// Encodes a `fcmp.sun.s` instruction (requires f). + pub inline fn @"fcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c148000, p0, p1, p2); + } + + /// Encodes a `fcmp.sune.d` instruction (requires f). + pub inline fn @"fcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c2c8000, p0, p1, p2); + } + + /// Encodes a `fcmp.sune.s` instruction (requires f). + pub inline fn @"fcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeCdFjFk(0x0c1c8000, p0, p1, p2); + } + + /// Encodes a `fcopysign.d` instruction (requires f). + pub inline fn @"fcopysign.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01130000, p0, p1, p2); + } + + /// Encodes a `fcopysign.s` instruction (requires f). + pub inline fn @"fcopysign.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01128000, p0, p1, p2); + } + + /// Encodes a `fcsrrd` instruction (requires 64bit). + pub inline fn fcsrrd(p0: Register, p1: u5) Instruction { + return encodeDUj5(0x0114c800, p0, p1); + } + + /// Encodes a `fcsrwr` instruction (requires 64bit). + pub inline fn fcsrwr(p0: Register, p1: u5) Instruction { + return encodeJUd5(0x0114c000, p0, p1); + } + + /// Encodes a `fcvt.d.ld` instruction (requires f). + pub inline fn @"fcvt.d.ld"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01150000, p0, p1, p2); + } + + /// Encodes a `fcvt.d.s` instruction (requires f). + pub inline fn @"fcvt.d.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01192400, p0, p1); + } + + /// Encodes a `fcvt.ld.d` instruction (requires f). + pub inline fn @"fcvt.ld.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x0114e000, p0, p1); + } + + /// Encodes a `fcvt.s.d` instruction (requires f). + pub inline fn @"fcvt.s.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01191800, p0, p1); + } + + /// Encodes a `fcvt.ud.d` instruction (requires f). + pub inline fn @"fcvt.ud.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x0114e400, p0, p1); + } + + /// Encodes a `fdiv.d` instruction (requires f). + pub inline fn @"fdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01070000, p0, p1, p2); + } + + /// Encodes a `fdiv.s` instruction (requires f). + pub inline fn @"fdiv.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01068000, p0, p1, p2); + } + + /// Encodes a `ffint.d.l` instruction (requires f). + pub inline fn @"ffint.d.l"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d2800, p0, p1); + } + + /// Encodes a `ffint.d.w` instruction (requires f). + pub inline fn @"ffint.d.w"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d2000, p0, p1); + } + + /// Encodes a `ffint.s.l` instruction (requires f). + pub inline fn @"ffint.s.l"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d1800, p0, p1); + } + + /// Encodes a `ffint.s.w` instruction (requires f). + pub inline fn @"ffint.s.w"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011d1000, p0, p1); + } + + /// Encodes a `fld.d` instruction (requires f). + pub inline fn @"fld.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2b800000, p0, p1, p2); + } + + /// Encodes a `fld.s` instruction (requires f). + pub inline fn @"fld.s"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2b000000, p0, p1, p2); + } + + /// Encodes a `fldgt.d` instruction (requires f). + pub inline fn @"fldgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38748000, p0, p1, p2); + } + + /// Encodes a `fldgt.s` instruction (requires f). + pub inline fn @"fldgt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38740000, p0, p1, p2); + } + + /// Encodes a `fldle.d` instruction (requires f). + pub inline fn @"fldle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38758000, p0, p1, p2); + } + + /// Encodes a `fldle.s` instruction (requires f). + pub inline fn @"fldle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38750000, p0, p1, p2); + } + + /// Encodes a `fldx.d` instruction (requires f). + pub inline fn @"fldx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38340000, p0, p1, p2); + } + + /// Encodes a `fldx.s` instruction (requires f). + pub inline fn @"fldx.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38300000, p0, p1, p2); + } + + /// Encodes a `flogb.d` instruction (requires f). + pub inline fn @"flogb.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01142800, p0, p1); + } + + /// Encodes a `flogb.s` instruction (requires f). + pub inline fn @"flogb.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01142400, p0, p1); + } + + /// Encodes a `fmadd.d` instruction (requires f). + pub inline fn @"fmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08200000, p0, p1, p2, p3); + } + + /// Encodes a `fmadd.s` instruction (requires f). + pub inline fn @"fmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08100000, p0, p1, p2, p3); + } + + /// Encodes a `fmax.d` instruction (requires f). + pub inline fn @"fmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01090000, p0, p1, p2); + } + + /// Encodes a `fmax.s` instruction (requires f). + pub inline fn @"fmax.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01088000, p0, p1, p2); + } + + /// Encodes a `fmaxa.d` instruction (requires f). + pub inline fn @"fmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010d0000, p0, p1, p2); + } + + /// Encodes a `fmaxa.s` instruction (requires f). + pub inline fn @"fmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010c8000, p0, p1, p2); + } + + /// Encodes a `fmin.d` instruction (requires f). + pub inline fn @"fmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010b0000, p0, p1, p2); + } + + /// Encodes a `fmin.s` instruction (requires f). + pub inline fn @"fmin.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010a8000, p0, p1, p2); + } + + /// Encodes a `fmina.d` instruction (requires f). + pub inline fn @"fmina.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010f0000, p0, p1, p2); + } + + /// Encodes a `fmina.s` instruction (requires f). + pub inline fn @"fmina.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x010e8000, p0, p1, p2); + } + + /// Encodes a `fmov.d` instruction (requires f). + pub inline fn @"fmov.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01149800, p0, p1); + } + + /// Encodes a `fmov.s` instruction (requires f). + pub inline fn @"fmov.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01149400, p0, p1); + } + + /// Encodes a `fmsub.d` instruction (requires f). + pub inline fn @"fmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08600000, p0, p1, p2, p3); + } + + /// Encodes a `fmsub.s` instruction (requires f). + pub inline fn @"fmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08500000, p0, p1, p2, p3); + } + + /// Encodes a `fmul.d` instruction (requires f). + pub inline fn @"fmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01050000, p0, p1, p2); + } + + /// Encodes a `fmul.s` instruction (requires f). + pub inline fn @"fmul.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01048000, p0, p1, p2); + } + + /// Encodes a `fneg.d` instruction (requires f). + pub inline fn @"fneg.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01141800, p0, p1); + } + + /// Encodes a `fneg.s` instruction (requires f). + pub inline fn @"fneg.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01141400, p0, p1); + } + + /// Encodes a `fnmadd.d` instruction (requires f). + pub inline fn @"fnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08a00000, p0, p1, p2, p3); + } + + /// Encodes a `fnmadd.s` instruction (requires f). + pub inline fn @"fnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08900000, p0, p1, p2, p3); + } + + /// Encodes a `fnmsub.d` instruction (requires f). + pub inline fn @"fnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08e00000, p0, p1, p2, p3); + } + + /// Encodes a `fnmsub.s` instruction (requires f). + pub inline fn @"fnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkFa(0x08d00000, p0, p1, p2, p3); + } + + /// Encodes a `frecip.d` instruction (requires f). + pub inline fn @"frecip.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01145800, p0, p1); + } + + /// Encodes a `frecip.s` instruction (requires f). + pub inline fn @"frecip.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01145400, p0, p1); + } + + /// Encodes a `frecipe.d` instruction (requires f). + pub inline fn @"frecipe.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01147800, p0, p1); + } + + /// Encodes a `frecipe.s` instruction (requires f). + pub inline fn @"frecipe.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01147400, p0, p1); + } + + /// Encodes a `frint.d` instruction (requires f). + pub inline fn @"frint.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011e4800, p0, p1); + } + + /// Encodes a `frint.s` instruction (requires f). + pub inline fn @"frint.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011e4400, p0, p1); + } + + /// Encodes a `frsqrt.d` instruction (requires f). + pub inline fn @"frsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01146800, p0, p1); + } + + /// Encodes a `frsqrt.s` instruction (requires f). + pub inline fn @"frsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01146400, p0, p1); + } + + /// Encodes a `frsqrte.d` instruction (requires f). + pub inline fn @"frsqrte.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01148800, p0, p1); + } + + /// Encodes a `frsqrte.s` instruction (requires f). + pub inline fn @"frsqrte.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01148400, p0, p1); + } + + /// Encodes a `fscaleb.d` instruction (requires f). + pub inline fn @"fscaleb.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01110000, p0, p1, p2); + } + + /// Encodes a `fscaleb.s` instruction (requires f). + pub inline fn @"fscaleb.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01108000, p0, p1, p2); + } + + /// Encodes a `fsel` instruction (requires f). + pub inline fn fsel(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeFdFjFkCa(0x0d000000, p0, p1, p2, p3); + } + + /// Encodes a `fsqrt.d` instruction (requires f). + pub inline fn @"fsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01144800, p0, p1); + } + + /// Encodes a `fsqrt.s` instruction (requires f). + pub inline fn @"fsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x01144400, p0, p1); + } + + /// Encodes a `fst.d` instruction (requires f). + pub inline fn @"fst.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2bc00000, p0, p1, p2); + } + + /// Encodes a `fst.s` instruction (requires f). + pub inline fn @"fst.s"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeFdJSk12(0x2b400000, p0, p1, p2); + } + + /// Encodes a `fstgt.d` instruction (requires f). + pub inline fn @"fstgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38768000, p0, p1, p2); + } + + /// Encodes a `fstgt.s` instruction (requires f). + pub inline fn @"fstgt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38760000, p0, p1, p2); + } + + /// Encodes a `fstle.d` instruction (requires f). + pub inline fn @"fstle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38778000, p0, p1, p2); + } + + /// Encodes a `fstle.s` instruction (requires f). + pub inline fn @"fstle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38770000, p0, p1, p2); + } + + /// Encodes a `fstx.d` instruction (requires f). + pub inline fn @"fstx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x383c0000, p0, p1, p2); + } + + /// Encodes a `fstx.s` instruction (requires f). + pub inline fn @"fstx.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdJK(0x38380000, p0, p1, p2); + } + + /// Encodes a `fsub.d` instruction (requires f). + pub inline fn @"fsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01030000, p0, p1, p2); + } + + /// Encodes a `fsub.s` instruction (requires f). + pub inline fn @"fsub.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeFdFjFk(0x01028000, p0, p1, p2); + } + + /// Encodes a `ftint.l.d` instruction (requires f). + pub inline fn @"ftint.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b2800, p0, p1); + } + + /// Encodes a `ftint.l.s` instruction (requires f). + pub inline fn @"ftint.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b2400, p0, p1); + } + + /// Encodes a `ftint.w.d` instruction (requires f). + pub inline fn @"ftint.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b0800, p0, p1); + } + + /// Encodes a `ftint.w.s` instruction (requires f). + pub inline fn @"ftint.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011b0400, p0, p1); + } + + /// Encodes a `ftintrm.l.d` instruction (requires f). + pub inline fn @"ftintrm.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a2800, p0, p1); + } + + /// Encodes a `ftintrm.l.s` instruction (requires f). + pub inline fn @"ftintrm.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a2400, p0, p1); + } + + /// Encodes a `ftintrm.w.d` instruction (requires f). + pub inline fn @"ftintrm.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a0800, p0, p1); + } + + /// Encodes a `ftintrm.w.s` instruction (requires f). + pub inline fn @"ftintrm.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a0400, p0, p1); + } + + /// Encodes a `ftintrne.l.d` instruction (requires f). + pub inline fn @"ftintrne.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ae800, p0, p1); + } + + /// Encodes a `ftintrne.l.s` instruction (requires f). + pub inline fn @"ftintrne.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ae400, p0, p1); + } + + /// Encodes a `ftintrne.w.d` instruction (requires f). + pub inline fn @"ftintrne.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ac800, p0, p1); + } + + /// Encodes a `ftintrne.w.s` instruction (requires f). + pub inline fn @"ftintrne.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011ac400, p0, p1); + } + + /// Encodes a `ftintrp.l.d` instruction (requires f). + pub inline fn @"ftintrp.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a6800, p0, p1); + } + + /// Encodes a `ftintrp.l.s` instruction (requires f). + pub inline fn @"ftintrp.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a6400, p0, p1); + } + + /// Encodes a `ftintrp.w.d` instruction (requires f). + pub inline fn @"ftintrp.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a4800, p0, p1); + } + + /// Encodes a `ftintrp.w.s` instruction (requires f). + pub inline fn @"ftintrp.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a4400, p0, p1); + } + + /// Encodes a `ftintrz.l.d` instruction (requires f). + pub inline fn @"ftintrz.l.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011aa800, p0, p1); + } + + /// Encodes a `ftintrz.l.s` instruction (requires f). + pub inline fn @"ftintrz.l.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011aa400, p0, p1); + } + + /// Encodes a `ftintrz.w.d` instruction (requires f). + pub inline fn @"ftintrz.w.d"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a8800, p0, p1); + } + + /// Encodes a `ftintrz.w.s` instruction (requires f). + pub inline fn @"ftintrz.w.s"(p0: Register, p1: Register) Instruction { + return encodeFdFj(0x011a8400, p0, p1); + } + + /// Encodes a `gcsrrd` instruction (requires 64bit). + pub inline fn gcsrrd(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x05000000, p0, p1); + } + + /// Encodes a `gcsrwr` instruction (requires 64bit). + pub inline fn gcsrwr(p0: Register, p1: u14) Instruction { + return encodeDUk14(0x05000032, p0, p1); + } + + /// Encodes a `gcsrxchg` instruction (requires 64bit). + pub inline fn gcsrxchg(p0: Register, p1: Register, p2: u14) Instruction { + return encodeDJUk14(0x05000000, p0, p1, p2); + } + + /// Encodes a `gtlbclr` instruction (requires 64bit). + pub inline fn gtlbclr() Instruction { + return encodeEMPTY(0x06482001); + } + + /// Encodes a `gtlbfill` instruction (requires 64bit). + pub inline fn gtlbfill() Instruction { + return encodeEMPTY(0x06483401); + } + + /// Encodes a `gtlbflush` instruction (requires 64bit). + pub inline fn gtlbflush() Instruction { + return encodeEMPTY(0x06482401); + } + + /// Encodes a `gtlbrd` instruction (requires 64bit). + pub inline fn gtlbrd() Instruction { + return encodeEMPTY(0x06482c01); + } + + /// Encodes a `gtlbsrch` instruction (requires 64bit). + pub inline fn gtlbsrch() Instruction { + return encodeEMPTY(0x06482801); + } + + /// Encodes a `gtlbwr` instruction (requires 64bit). + pub inline fn gtlbwr() Instruction { + return encodeEMPTY(0x06483001); + } + + /// Encodes a `hypcall` instruction (requires 64bit). + pub inline fn hypcall(p0: u15) Instruction { + return encodeUd15(0x002b8000, p0); + } + + /// Encodes a `ibar` instruction (requires 32bit). + pub inline fn ibar(p0: u15) Instruction { + return encodeUd15(0x38728000, p0); + } + + /// Encodes a `idle` instruction (requires 32bit). + pub inline fn idle(p0: u15) Instruction { + return encodeUd15(0x06488000, p0); + } + + /// Encodes a `iocsrrd.b` instruction (requires 64bit). + pub inline fn @"iocsrrd.b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480000, p0, p1); + } + + /// Encodes a `iocsrrd.d` instruction (requires 64bit). + pub inline fn @"iocsrrd.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480c00, p0, p1); + } + + /// Encodes a `iocsrrd.h` instruction (requires 64bit). + pub inline fn @"iocsrrd.h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480400, p0, p1); + } + + /// Encodes a `iocsrrd.w` instruction (requires 64bit). + pub inline fn @"iocsrrd.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06480800, p0, p1); + } + + /// Encodes a `iocsrwr.b` instruction (requires 64bit). + pub inline fn @"iocsrwr.b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481000, p0, p1); + } + + /// Encodes a `iocsrwr.d` instruction (requires 64bit). + pub inline fn @"iocsrwr.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481c00, p0, p1); + } + + /// Encodes a `iocsrwr.h` instruction (requires 64bit). + pub inline fn @"iocsrwr.h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481400, p0, p1); + } + + /// Encodes a `iocsrwr.w` instruction (requires 64bit). + pub inline fn @"iocsrwr.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x06481800, p0, p1); + } + + /// Encodes a `jirl` instruction (requires 32bit). + pub inline fn jirl(p0: Register, p1: Register, p2: i16) Instruction { + return encodeDJSk16ps2(0x4c000000, p0, p1, p2); + } + + /// Encodes a `jiscr0` instruction (requires 64bit). + pub inline fn jiscr0(p0: i5, p1: i16) Instruction { + return encodeSd5k16ps2(0x48000200, p0, p1); + } + + /// Encodes a `jiscr1` instruction (requires 64bit). + pub inline fn jiscr1(p0: i5, p1: i16) Instruction { + return encodeSd5k16ps2(0x48000300, p0, p1); + } + + /// Encodes a `ld.b` instruction (requires 32bit). + pub inline fn @"ld.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28000000, p0, p1, p2); + } + + /// Encodes a `ld.bu` instruction (requires 32bit). + pub inline fn @"ld.bu"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2a000000, p0, p1, p2); + } + + /// Encodes a `ld.d` instruction (requires 64bit). + pub inline fn @"ld.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28c00000, p0, p1, p2); + } + + /// Encodes a `ld.h` instruction (requires 32bit). + pub inline fn @"ld.h"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28400000, p0, p1, p2); + } + + /// Encodes a `ld.hu` instruction (requires 32bit). + pub inline fn @"ld.hu"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2a400000, p0, p1, p2); + } + + /// Encodes a `ld.w` instruction (requires 32bit). + pub inline fn @"ld.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x28800000, p0, p1, p2); + } + + /// Encodes a `ld.wu` instruction (requires 64bit). + pub inline fn @"ld.wu"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2a800000, p0, p1, p2); + } + + /// Encodes a `lddir` instruction (requires 64bit). + pub inline fn lddir(p0: Register, p1: Register, p2: u8) Instruction { + return encodeDJUk8(0x06400000, p0, p1, p2); + } + + /// Encodes a `ldgt.b` instruction (requires 64bit). + pub inline fn @"ldgt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38780000, p0, p1, p2); + } + + /// Encodes a `ldgt.d` instruction (requires 64bit). + pub inline fn @"ldgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38798000, p0, p1, p2); + } + + /// Encodes a `ldgt.h` instruction (requires 64bit). + pub inline fn @"ldgt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38788000, p0, p1, p2); + } + + /// Encodes a `ldgt.w` instruction (requires 64bit). + pub inline fn @"ldgt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38790000, p0, p1, p2); + } + + /// Encodes a `ldl.d` instruction (requires 64bit). + pub inline fn @"ldl.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2e800000, p0, p1, p2); + } + + /// Encodes a `ldl.w` instruction (requires 64bit). + pub inline fn @"ldl.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2e000000, p0, p1, p2); + } + + /// Encodes a `ldle.b` instruction (requires 64bit). + pub inline fn @"ldle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387a0000, p0, p1, p2); + } + + /// Encodes a `ldle.d` instruction (requires 64bit). + pub inline fn @"ldle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387b8000, p0, p1, p2); + } + + /// Encodes a `ldle.h` instruction (requires 64bit). + pub inline fn @"ldle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387a8000, p0, p1, p2); + } + + /// Encodes a `ldle.w` instruction (requires 64bit). + pub inline fn @"ldle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387b0000, p0, p1, p2); + } + + /// Encodes a `ldox4.d` instruction (requires 64bit). + pub inline fn @"ldox4.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x26000000, p0, p1, p2); + } + + /// Encodes a `ldox4.w` instruction (requires 64bit). + pub inline fn @"ldox4.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x24000000, p0, p1, p2); + } + + /// Encodes a `ldpte` instruction (requires 64bit). + pub inline fn ldpte(p0: Register, p1: u8) Instruction { + return encodeJUk8(0x06440000, p0, p1); + } + + /// Encodes a `ldr.d` instruction (requires 64bit). + pub inline fn @"ldr.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2ec00000, p0, p1, p2); + } + + /// Encodes a `ldr.w` instruction (requires 64bit). + pub inline fn @"ldr.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2e400000, p0, p1, p2); + } + + /// Encodes a `ldx.b` instruction (requires 64bit). + pub inline fn @"ldx.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38000000, p0, p1, p2); + } + + /// Encodes a `ldx.bu` instruction (requires 64bit). + pub inline fn @"ldx.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38200000, p0, p1, p2); + } + + /// Encodes a `ldx.d` instruction (requires 64bit). + pub inline fn @"ldx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x380c0000, p0, p1, p2); + } + + /// Encodes a `ldx.h` instruction (requires 64bit). + pub inline fn @"ldx.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38040000, p0, p1, p2); + } + + /// Encodes a `ldx.hu` instruction (requires 64bit). + pub inline fn @"ldx.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38240000, p0, p1, p2); + } + + /// Encodes a `ldx.w` instruction (requires 64bit). + pub inline fn @"ldx.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38080000, p0, p1, p2); + } + + /// Encodes a `ldx.wu` instruction (requires 64bit). + pub inline fn @"ldx.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38280000, p0, p1, p2); + } + + /// Encodes a `ll.d` instruction (requires 64bit). + pub inline fn @"ll.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x22000000, p0, p1, p2); + } + + /// Encodes a `ll.w` instruction (requires 32bit). + pub inline fn @"ll.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x20000000, p0, p1, p2); + } + + /// Encodes a `llacq.d` instruction (requires 64bit). + pub inline fn @"llacq.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578800, p0, p1); + } + + /// Encodes a `llacq.w` instruction (requires 64bit). + pub inline fn @"llacq.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578000, p0, p1); + } + + /// Encodes a `lu12i.w` instruction (requires 32bit). + pub inline fn @"lu12i.w"(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x14000000, p0, p1); + } + + /// Encodes a `maskeqz` instruction (requires 32s). + pub inline fn maskeqz(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00130000, p0, p1, p2); + } + + /// Encodes a `masknez` instruction (requires 32s). + pub inline fn masknez(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00138000, p0, p1, p2); + } + + /// Encodes a `mod.d` instruction (requires 64bit). + pub inline fn @"mod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00228000, p0, p1, p2); + } + + /// Encodes a `mod.du` instruction (requires 64bit). + pub inline fn @"mod.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00238000, p0, p1, p2); + } + + /// Encodes a `mod.w` instruction (requires 32bit). + pub inline fn @"mod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00208000, p0, p1, p2); + } + + /// Encodes a `mod.wu` instruction (requires 32bit). + pub inline fn @"mod.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00218000, p0, p1, p2); + } + + /// Encodes a `movfcc2fr` instruction (requires f). + pub inline fn movfcc2fr(p0: Register, p1: Register) Instruction { + return encodeFdCj(0x0114d400, p0, p1); + } + + /// Encodes a `movfcc2gr` instruction (requires f). + pub inline fn movfcc2gr(p0: Register, p1: Register) Instruction { + return encodeDCj(0x0114dc00, p0, p1); + } + + /// Encodes a `movfr2fcc` instruction (requires f). + pub inline fn movfr2fcc(p0: Register, p1: Register) Instruction { + return encodeCdFj(0x0114d000, p0, p1); + } + + /// Encodes a `movfr2gr.d` instruction (requires f). + pub inline fn @"movfr2gr.d"(p0: Register, p1: Register) Instruction { + return encodeDFj(0x0114b800, p0, p1); + } + + /// Encodes a `movfr2gr.s` instruction (requires f). + pub inline fn @"movfr2gr.s"(p0: Register, p1: Register) Instruction { + return encodeDFj(0x0114b400, p0, p1); + } + + /// Encodes a `movfrh2gr.s` instruction (requires f). + pub inline fn @"movfrh2gr.s"(p0: Register, p1: Register) Instruction { + return encodeDFj(0x0114bc00, p0, p1); + } + + /// Encodes a `movgr2fcc` instruction (requires f). + pub inline fn movgr2fcc(p0: Register, p1: Register) Instruction { + return encodeCdJ(0x0114d800, p0, p1); + } + + /// Encodes a `movgr2fr.d` instruction (requires f). + pub inline fn @"movgr2fr.d"(p0: Register, p1: Register) Instruction { + return encodeFdJ(0x0114a800, p0, p1); + } + + /// Encodes a `movgr2fr.w` instruction (requires f). + pub inline fn @"movgr2fr.w"(p0: Register, p1: Register) Instruction { + return encodeFdJ(0x0114a400, p0, p1); + } + + /// Encodes a `movgr2frh.w` instruction (requires f). + pub inline fn @"movgr2frh.w"(p0: Register, p1: Register) Instruction { + return encodeFdJ(0x0114ac00, p0, p1); + } + + /// Encodes a `movgr2scr` instruction (requires lbt). + pub inline fn movgr2scr(p0: Register, p1: Register) Instruction { + return encodeTdJ(0x00000800, p0, p1); + } + + /// Encodes a `movscr2gr` instruction (requires lbt). + pub inline fn movscr2gr(p0: Register, p1: Register) Instruction { + return encodeDTj(0x00000c00, p0, p1); + } + + /// Encodes a `mul.d` instruction (requires 64bit). + pub inline fn @"mul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001d8000, p0, p1, p2); + } + + /// Encodes a `mul.w` instruction (requires 32bit). + pub inline fn @"mul.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001c0000, p0, p1, p2); + } + + /// Encodes a `mulh.d` instruction (requires 64bit). + pub inline fn @"mulh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001e0000, p0, p1, p2); + } + + /// Encodes a `mulh.du` instruction (requires 64bit). + pub inline fn @"mulh.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001e8000, p0, p1, p2); + } + + /// Encodes a `mulh.w` instruction (requires 32bit). + pub inline fn @"mulh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001c8000, p0, p1, p2); + } + + /// Encodes a `mulh.wu` instruction (requires 32bit). + pub inline fn @"mulh.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001d0000, p0, p1, p2); + } + + /// Encodes a `mulw.d.w` instruction (requires 64bit). + pub inline fn @"mulw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001f0000, p0, p1, p2); + } + + /// Encodes a `mulw.d.wu` instruction (requires 64bit). + pub inline fn @"mulw.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001f8000, p0, p1, p2); + } + + /// Encodes a `nor` instruction (requires 32bit). + pub inline fn nor(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00140000, p0, p1, p2); + } + + /// Encodes a `or` instruction (requires 32bit). + pub inline fn @"or"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00150000, p0, p1, p2); + } + + /// Encodes a `ori` instruction (requires 32bit). + pub inline fn ori(p0: Register, p1: Register, p2: u12) Instruction { + return encodeDJUk12(0x03800000, p0, p1, p2); + } + + /// Encodes a `orn` instruction (requires 32bit). + pub inline fn orn(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00160000, p0, p1, p2); + } + + /// Encodes a `pcaddu12i` instruction (requires 32bit). + pub inline fn pcaddu12i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x1c000000, p0, p1); + } + + /// Encodes a `pcaddu18i` instruction (requires 64bit). + pub inline fn pcaddu18i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x1e000000, p0, p1); + } + + /// Encodes a `pcaddu2i` instruction (requires 32bit). + pub inline fn pcaddu2i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x18000000, p0, p1); + } + + /// Encodes a `pcalau12i` instruction (requires 32s). + pub inline fn pcalau12i(p0: Register, p1: i20) Instruction { + return encodeDSj20(0x1a000000, p0, p1); + } + + /// Encodes a `preld` instruction (requires 32bit). + pub inline fn preld(p0: u5, p1: Register, p2: i12) Instruction { + return encodeUd5JSk12(0x2ac00000, p0, p1, p2); + } + + /// Encodes a `preldx` instruction (requires 64bit). + pub inline fn preldx(p0: u5, p1: Register, p2: Register) Instruction { + return encodeUd5JK(0x382c0000, p0, p1, p2); + } + + /// Encodes a `rcr.b` instruction (requires 64bit). + pub inline fn @"rcr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00340000, p0, p1, p2); + } + + /// Encodes a `rcr.d` instruction (requires 64bit). + pub inline fn @"rcr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00358000, p0, p1, p2); + } + + /// Encodes a `rcr.h` instruction (requires 64bit). + pub inline fn @"rcr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00348000, p0, p1, p2); + } + + /// Encodes a `rcr.w` instruction (requires 64bit). + pub inline fn @"rcr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00350000, p0, p1, p2); + } + + /// Encodes a `rcri.b` instruction (requires 64bit). + pub inline fn @"rcri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDJUk3(0x00502000, p0, p1, p2); + } + + /// Encodes a `rcri.d` instruction (requires 64bit). + pub inline fn @"rcri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00510000, p0, p1, p2); + } + + /// Encodes a `rcri.h` instruction (requires 64bit). + pub inline fn @"rcri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDJUk4(0x00504000, p0, p1, p2); + } + + /// Encodes a `rcri.w` instruction (requires 64bit). + pub inline fn @"rcri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00508000, p0, p1, p2); + } + + /// Encodes a `rdtime.d` instruction (requires 64bit). + pub inline fn @"rdtime.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006800, p0, p1); + } + + /// Encodes a `rdtimeh.w` instruction (requires 32bit). + pub inline fn @"rdtimeh.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006400, p0, p1); + } + + /// Encodes a `rdtimel.w` instruction (requires 32bit). + pub inline fn @"rdtimel.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00006000, p0, p1); + } + + /// Encodes a `revb.2h` instruction (requires 32s). + pub inline fn @"revb.2h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003000, p0, p1); + } + + /// Encodes a `revb.2w` instruction (requires 64bit). + pub inline fn @"revb.2w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003800, p0, p1); + } + + /// Encodes a `revb.4h` instruction (requires 64bit). + pub inline fn @"revb.4h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003400, p0, p1); + } + + /// Encodes a `revb.d` instruction (requires 64bit). + pub inline fn @"revb.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00003c00, p0, p1); + } + + /// Encodes a `revbit.4b` instruction (requires 32s). + pub inline fn @"revbit.4b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004800, p0, p1); + } + + /// Encodes a `revbit.8b` instruction (requires 64bit). + pub inline fn @"revbit.8b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004c00, p0, p1); + } + + /// Encodes a `revbit.d` instruction (requires 64bit). + pub inline fn @"revbit.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005400, p0, p1); + } + + /// Encodes a `revbit.w` instruction (requires 32s). + pub inline fn @"revbit.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005000, p0, p1); + } + + /// Encodes a `revh.2w` instruction (requires 64bit). + pub inline fn @"revh.2w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004000, p0, p1); + } + + /// Encodes a `revh.d` instruction (requires 64bit). + pub inline fn @"revh.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00004400, p0, p1); + } + + /// Encodes a `rotr.b` instruction (requires 64bit). + pub inline fn @"rotr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001a0000, p0, p1, p2); + } + + /// Encodes a `rotr.d` instruction (requires 64bit). + pub inline fn @"rotr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001b8000, p0, p1, p2); + } + + /// Encodes a `rotr.h` instruction (requires 64bit). + pub inline fn @"rotr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001a8000, p0, p1, p2); + } + + /// Encodes a `rotr.w` instruction (requires 32s). + pub inline fn @"rotr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x001b0000, p0, p1, p2); + } + + /// Encodes a `rotri.b` instruction (requires 64bit). + pub inline fn @"rotri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDJUk3(0x004c2000, p0, p1, p2); + } + + /// Encodes a `rotri.d` instruction (requires 64bit). + pub inline fn @"rotri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x004d0000, p0, p1, p2); + } + + /// Encodes a `rotri.h` instruction (requires 64bit). + pub inline fn @"rotri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDJUk4(0x004c4000, p0, p1, p2); + } + + /// Encodes a `rotri.w` instruction (requires 32s). + pub inline fn @"rotri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x004c8000, p0, p1, p2); + } + + /// Encodes a `sbc.b` instruction (requires 64bit). + pub inline fn @"sbc.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00320000, p0, p1, p2); + } + + /// Encodes a `sbc.d` instruction (requires 64bit). + pub inline fn @"sbc.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00338000, p0, p1, p2); + } + + /// Encodes a `sbc.h` instruction (requires 64bit). + pub inline fn @"sbc.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00328000, p0, p1, p2); + } + + /// Encodes a `sbc.w` instruction (requires 64bit). + pub inline fn @"sbc.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00330000, p0, p1, p2); + } + + /// Encodes a `sc.d` instruction (requires 64bit). + pub inline fn @"sc.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x23000000, p0, p1, p2); + } + + /// Encodes a `sc.q` instruction (requires 64bit). + pub inline fn @"sc.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDKJ(0x38570000, p0, p1, p2); + } + + /// Encodes a `sc.w` instruction (requires 32bit). + pub inline fn @"sc.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14ps2(0x21000000, p0, p1, p2); + } + + /// Encodes a `screl.d` instruction (requires 64bit). + pub inline fn @"screl.d"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578c00, p0, p1); + } + + /// Encodes a `screl.w` instruction (requires 64bit). + pub inline fn @"screl.w"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x38578400, p0, p1); + } + + /// Encodes a `sext.b` instruction (requires 32s). + pub inline fn @"sext.b"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005c00, p0, p1); + } + + /// Encodes a `sext.h` instruction (requires 32s). + pub inline fn @"sext.h"(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00005800, p0, p1); + } + + /// Encodes a `sladd.d` instruction (requires 64bit). + pub inline fn @"sladd.d"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x002c0000, p0, p1, p2, p3); + } + + /// Encodes a `sladd.w` instruction (requires 32s). + pub inline fn @"sladd.w"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x00040000, p0, p1, p2, p3); + } + + /// Encodes a `sladd.wu` instruction (requires 64bit). + pub inline fn @"sladd.wu"(p0: Register, p1: Register, p2: Register, p3: u2) Instruction { + return encodeDJKUa2(0x00060000, p0, p1, p2, p3); + } + + /// Encodes a `sll.d` instruction (requires 64bit). + pub inline fn @"sll.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00188000, p0, p1, p2); + } + + /// Encodes a `sll.w` instruction (requires 32bit). + pub inline fn @"sll.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00170000, p0, p1, p2); + } + + /// Encodes a `slli.d` instruction (requires 64bit). + pub inline fn @"slli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00410000, p0, p1, p2); + } + + /// Encodes a `slli.w` instruction (requires 32bit). + pub inline fn @"slli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00408000, p0, p1, p2); + } + + /// Encodes a `slt` instruction (requires 32bit). + pub inline fn slt(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00120000, p0, p1, p2); + } + + /// Encodes a `slti` instruction (requires 32bit). + pub inline fn slti(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02000000, p0, p1, p2); + } + + /// Encodes a `sltu` instruction (requires 32bit). + pub inline fn sltu(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00128000, p0, p1, p2); + } + + /// Encodes a `sltui` instruction (requires 32bit). + pub inline fn sltui(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x02400000, p0, p1, p2); + } + + /// Encodes a `sra.d` instruction (requires 64bit). + pub inline fn @"sra.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00198000, p0, p1, p2); + } + + /// Encodes a `sra.w` instruction (requires 32bit). + pub inline fn @"sra.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00180000, p0, p1, p2); + } + + /// Encodes a `srai.d` instruction (requires 64bit). + pub inline fn @"srai.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00490000, p0, p1, p2); + } + + /// Encodes a `srai.w` instruction (requires 32bit). + pub inline fn @"srai.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00488000, p0, p1, p2); + } + + /// Encodes a `srl.d` instruction (requires 64bit). + pub inline fn @"srl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00190000, p0, p1, p2); + } + + /// Encodes a `srl.w` instruction (requires 32bit). + pub inline fn @"srl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00178000, p0, p1, p2); + } + + /// Encodes a `srli.d` instruction (requires 64bit). + pub inline fn @"srli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeDJUk6(0x00450000, p0, p1, p2); + } + + /// Encodes a `srli.w` instruction (requires 32bit). + pub inline fn @"srli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeDJUk5(0x00448000, p0, p1, p2); + } + + /// Encodes a `st.b` instruction (requires 32bit). + pub inline fn @"st.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29000000, p0, p1, p2); + } + + /// Encodes a `st.d` instruction (requires 64bit). + pub inline fn @"st.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29c00000, p0, p1, p2); + } + + /// Encodes a `st.h` instruction (requires 32bit). + pub inline fn @"st.h"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29400000, p0, p1, p2); + } + + /// Encodes a `st.w` instruction (requires 32bit). + pub inline fn @"st.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x29800000, p0, p1, p2); + } + + /// Encodes a `stgt.b` instruction (requires 64bit). + pub inline fn @"stgt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387c0000, p0, p1, p2); + } + + /// Encodes a `stgt.d` instruction (requires 64bit). + pub inline fn @"stgt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387d8000, p0, p1, p2); + } + + /// Encodes a `stgt.h` instruction (requires 64bit). + pub inline fn @"stgt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387c8000, p0, p1, p2); + } + + /// Encodes a `stgt.w` instruction (requires 64bit). + pub inline fn @"stgt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387d0000, p0, p1, p2); + } + + /// Encodes a `stl.d` instruction (requires 64bit). + pub inline fn @"stl.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2f800000, p0, p1, p2); + } + + /// Encodes a `stl.w` instruction (requires 64bit). + pub inline fn @"stl.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2f000000, p0, p1, p2); + } + + /// Encodes a `stle.b` instruction (requires 64bit). + pub inline fn @"stle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387e0000, p0, p1, p2); + } + + /// Encodes a `stle.d` instruction (requires 64bit). + pub inline fn @"stle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387f8000, p0, p1, p2); + } + + /// Encodes a `stle.h` instruction (requires 64bit). + pub inline fn @"stle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387e8000, p0, p1, p2); + } + + /// Encodes a `stle.w` instruction (requires 64bit). + pub inline fn @"stle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x387f0000, p0, p1, p2); + } + + /// Encodes a `stox4.d` instruction (requires 64bit). + pub inline fn @"stox4.d"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x27000000, p0, p1, p2); + } + + /// Encodes a `stox4.w` instruction (requires 64bit). + pub inline fn @"stox4.w"(p0: Register, p1: Register, p2: i14) Instruction { + return encodeDJSk14(0x25000000, p0, p1, p2); + } + + /// Encodes a `str.d` instruction (requires 64bit). + pub inline fn @"str.d"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2fc00000, p0, p1, p2); + } + + /// Encodes a `str.w` instruction (requires 64bit). + pub inline fn @"str.w"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeDJSk12(0x2f400000, p0, p1, p2); + } + + /// Encodes a `stx.b` instruction (requires 64bit). + pub inline fn @"stx.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38100000, p0, p1, p2); + } + + /// Encodes a `stx.d` instruction (requires 64bit). + pub inline fn @"stx.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x381c0000, p0, p1, p2); + } + + /// Encodes a `stx.h` instruction (requires 64bit). + pub inline fn @"stx.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38140000, p0, p1, p2); + } + + /// Encodes a `stx.w` instruction (requires 64bit). + pub inline fn @"stx.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x38180000, p0, p1, p2); + } + + /// Encodes a `sub.d` instruction (requires 64bit). + pub inline fn @"sub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00118000, p0, p1, p2); + } + + /// Encodes a `sub.w` instruction (requires 32bit). + pub inline fn @"sub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00110000, p0, p1, p2); + } + + /// Encodes a `syscall` instruction (requires 32bit). + pub inline fn syscall(p0: u15) Instruction { + return encodeUd15(0x002b0000, p0); + } + + /// Encodes a `tlbclr` instruction (requires 64bit). + pub inline fn tlbclr() Instruction { + return encodeEMPTY(0x06482000); + } + + /// Encodes a `tlbfill` instruction (requires 32bit). + pub inline fn tlbfill() Instruction { + return encodeEMPTY(0x06483400); + } + + /// Encodes a `tlbflush` instruction (requires 64bit). + pub inline fn tlbflush() Instruction { + return encodeEMPTY(0x06482400); + } + + /// Encodes a `tlbinv` instruction (requires 32bit). + pub inline fn tlbinv(p0: Register, p1: Register, p2: u5) Instruction { + return encodeJKUd5(0x06498000, p0, p1, p2); + } + + /// Encodes a `tlbrd` instruction (requires 32bit). + pub inline fn tlbrd() Instruction { + return encodeEMPTY(0x06482c00); + } + + /// Encodes a `tlbsrch` instruction (requires 32bit). + pub inline fn tlbsrch() Instruction { + return encodeEMPTY(0x06482800); + } + + /// Encodes a `tlbwr` instruction (requires 32bit). + pub inline fn tlbwr() Instruction { + return encodeEMPTY(0x06483000); + } + + /// Encodes a `vabsd.b` instruction (requires lsx). + pub inline fn @"vabsd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70600000, p0, p1, p2); + } + + /// Encodes a `vabsd.bu` instruction (requires lsx). + pub inline fn @"vabsd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70620000, p0, p1, p2); + } + + /// Encodes a `vabsd.d` instruction (requires lsx). + pub inline fn @"vabsd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70618000, p0, p1, p2); + } + + /// Encodes a `vabsd.du` instruction (requires lsx). + pub inline fn @"vabsd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70638000, p0, p1, p2); + } + + /// Encodes a `vabsd.h` instruction (requires lsx). + pub inline fn @"vabsd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70608000, p0, p1, p2); + } + + /// Encodes a `vabsd.hu` instruction (requires lsx). + pub inline fn @"vabsd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70628000, p0, p1, p2); + } + + /// Encodes a `vabsd.w` instruction (requires lsx). + pub inline fn @"vabsd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70610000, p0, p1, p2); + } + + /// Encodes a `vabsd.wu` instruction (requires lsx). + pub inline fn @"vabsd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70630000, p0, p1, p2); + } + + /// Encodes a `vadd.b` instruction (requires lsx). + pub inline fn @"vadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700a0000, p0, p1, p2); + } + + /// Encodes a `vadd.d` instruction (requires lsx). + pub inline fn @"vadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700b8000, p0, p1, p2); + } + + /// Encodes a `vadd.h` instruction (requires lsx). + pub inline fn @"vadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700a8000, p0, p1, p2); + } + + /// Encodes a `vadd.q` instruction (requires lsx). + pub inline fn @"vadd.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712d0000, p0, p1, p2); + } + + /// Encodes a `vadd.w` instruction (requires lsx). + pub inline fn @"vadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700b0000, p0, p1, p2); + } + + /// Encodes a `vadda.b` instruction (requires lsx). + pub inline fn @"vadda.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705c0000, p0, p1, p2); + } + + /// Encodes a `vadda.d` instruction (requires lsx). + pub inline fn @"vadda.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705d8000, p0, p1, p2); + } + + /// Encodes a `vadda.h` instruction (requires lsx). + pub inline fn @"vadda.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705c8000, p0, p1, p2); + } + + /// Encodes a `vadda.w` instruction (requires lsx). + pub inline fn @"vadda.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705d0000, p0, p1, p2); + } + + /// Encodes a `vaddi.bu` instruction (requires lsx). + pub inline fn @"vaddi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728a0000, p0, p1, p2); + } + + /// Encodes a `vaddi.du` instruction (requires lsx). + pub inline fn @"vaddi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728b8000, p0, p1, p2); + } + + /// Encodes a `vaddi.hu` instruction (requires lsx). + pub inline fn @"vaddi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728a8000, p0, p1, p2); + } + + /// Encodes a `vaddi.wu` instruction (requires lsx). + pub inline fn @"vaddi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728b0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.d.w` instruction (requires lsx). + pub inline fn @"vaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701f0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.d.wu` instruction (requires lsx). + pub inline fn @"vaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702f0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.d.wu.w` instruction (requires lsx). + pub inline fn @"vaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703f0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.h.b` instruction (requires lsx). + pub inline fn @"vaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701e0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.h.bu` instruction (requires lsx). + pub inline fn @"vaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702e0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.h.bu.b` instruction (requires lsx). + pub inline fn @"vaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703e0000, p0, p1, p2); + } + + /// Encodes a `vaddwev.q.d` instruction (requires lsx). + pub inline fn @"vaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701f8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.q.du` instruction (requires lsx). + pub inline fn @"vaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702f8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.q.du.d` instruction (requires lsx). + pub inline fn @"vaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703f8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.w.h` instruction (requires lsx). + pub inline fn @"vaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x701e8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.w.hu` instruction (requires lsx). + pub inline fn @"vaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x702e8000, p0, p1, p2); + } + + /// Encodes a `vaddwev.w.hu.h` instruction (requires lsx). + pub inline fn @"vaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x703e8000, p0, p1, p2); + } + + /// Encodes a `vaddwod.d.w` instruction (requires lsx). + pub inline fn @"vaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70230000, p0, p1, p2); + } + + /// Encodes a `vaddwod.d.wu` instruction (requires lsx). + pub inline fn @"vaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70330000, p0, p1, p2); + } + + /// Encodes a `vaddwod.d.wu.w` instruction (requires lsx). + pub inline fn @"vaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70410000, p0, p1, p2); + } + + /// Encodes a `vaddwod.h.b` instruction (requires lsx). + pub inline fn @"vaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70220000, p0, p1, p2); + } + + /// Encodes a `vaddwod.h.bu` instruction (requires lsx). + pub inline fn @"vaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70320000, p0, p1, p2); + } + + /// Encodes a `vaddwod.h.bu.b` instruction (requires lsx). + pub inline fn @"vaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70400000, p0, p1, p2); + } + + /// Encodes a `vaddwod.q.d` instruction (requires lsx). + pub inline fn @"vaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70238000, p0, p1, p2); + } + + /// Encodes a `vaddwod.q.du` instruction (requires lsx). + pub inline fn @"vaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70338000, p0, p1, p2); + } + + /// Encodes a `vaddwod.q.du.d` instruction (requires lsx). + pub inline fn @"vaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70418000, p0, p1, p2); + } + + /// Encodes a `vaddwod.w.h` instruction (requires lsx). + pub inline fn @"vaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70228000, p0, p1, p2); + } + + /// Encodes a `vaddwod.w.hu` instruction (requires lsx). + pub inline fn @"vaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70328000, p0, p1, p2); + } + + /// Encodes a `vaddwod.w.hu.h` instruction (requires lsx). + pub inline fn @"vaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70408000, p0, p1, p2); + } + + /// Encodes a `vand.v` instruction (requires lsx). + pub inline fn @"vand.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71260000, p0, p1, p2); + } + + /// Encodes a `vandi.b` instruction (requires lsx). + pub inline fn @"vandi.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73d00000, p0, p1, p2); + } + + /// Encodes a `vandn.v` instruction (requires lsx). + pub inline fn @"vandn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71280000, p0, p1, p2); + } + + /// Encodes a `vavg.b` instruction (requires lsx). + pub inline fn @"vavg.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70640000, p0, p1, p2); + } + + /// Encodes a `vavg.bu` instruction (requires lsx). + pub inline fn @"vavg.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70660000, p0, p1, p2); + } + + /// Encodes a `vavg.d` instruction (requires lsx). + pub inline fn @"vavg.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70658000, p0, p1, p2); + } + + /// Encodes a `vavg.du` instruction (requires lsx). + pub inline fn @"vavg.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70678000, p0, p1, p2); + } + + /// Encodes a `vavg.h` instruction (requires lsx). + pub inline fn @"vavg.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70648000, p0, p1, p2); + } + + /// Encodes a `vavg.hu` instruction (requires lsx). + pub inline fn @"vavg.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70668000, p0, p1, p2); + } + + /// Encodes a `vavg.w` instruction (requires lsx). + pub inline fn @"vavg.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70650000, p0, p1, p2); + } + + /// Encodes a `vavg.wu` instruction (requires lsx). + pub inline fn @"vavg.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70670000, p0, p1, p2); + } + + /// Encodes a `vavgr.b` instruction (requires lsx). + pub inline fn @"vavgr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70680000, p0, p1, p2); + } + + /// Encodes a `vavgr.bu` instruction (requires lsx). + pub inline fn @"vavgr.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706a0000, p0, p1, p2); + } + + /// Encodes a `vavgr.d` instruction (requires lsx). + pub inline fn @"vavgr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70698000, p0, p1, p2); + } + + /// Encodes a `vavgr.du` instruction (requires lsx). + pub inline fn @"vavgr.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706b8000, p0, p1, p2); + } + + /// Encodes a `vavgr.h` instruction (requires lsx). + pub inline fn @"vavgr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70688000, p0, p1, p2); + } + + /// Encodes a `vavgr.hu` instruction (requires lsx). + pub inline fn @"vavgr.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706a8000, p0, p1, p2); + } + + /// Encodes a `vavgr.w` instruction (requires lsx). + pub inline fn @"vavgr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70690000, p0, p1, p2); + } + + /// Encodes a `vavgr.wu` instruction (requires lsx). + pub inline fn @"vavgr.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x706b0000, p0, p1, p2); + } + + /// Encodes a `vbitclr.b` instruction (requires lsx). + pub inline fn @"vbitclr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710c0000, p0, p1, p2); + } + + /// Encodes a `vbitclr.d` instruction (requires lsx). + pub inline fn @"vbitclr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710d8000, p0, p1, p2); + } + + /// Encodes a `vbitclr.h` instruction (requires lsx). + pub inline fn @"vbitclr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710c8000, p0, p1, p2); + } + + /// Encodes a `vbitclr.w` instruction (requires lsx). + pub inline fn @"vbitclr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710d0000, p0, p1, p2); + } + + /// Encodes a `vbitclri.b` instruction (requires lsx). + pub inline fn @"vbitclri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73102000, p0, p1, p2); + } + + /// Encodes a `vbitclri.d` instruction (requires lsx). + pub inline fn @"vbitclri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73110000, p0, p1, p2); + } + + /// Encodes a `vbitclri.h` instruction (requires lsx). + pub inline fn @"vbitclri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73104000, p0, p1, p2); + } + + /// Encodes a `vbitclri.w` instruction (requires lsx). + pub inline fn @"vbitclri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73108000, p0, p1, p2); + } + + /// Encodes a `vbitrev.b` instruction (requires lsx). + pub inline fn @"vbitrev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71100000, p0, p1, p2); + } + + /// Encodes a `vbitrev.d` instruction (requires lsx). + pub inline fn @"vbitrev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71118000, p0, p1, p2); + } + + /// Encodes a `vbitrev.h` instruction (requires lsx). + pub inline fn @"vbitrev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71108000, p0, p1, p2); + } + + /// Encodes a `vbitrev.w` instruction (requires lsx). + pub inline fn @"vbitrev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71110000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.b` instruction (requires lsx). + pub inline fn @"vbitrevi.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73182000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.d` instruction (requires lsx). + pub inline fn @"vbitrevi.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73190000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.h` instruction (requires lsx). + pub inline fn @"vbitrevi.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73184000, p0, p1, p2); + } + + /// Encodes a `vbitrevi.w` instruction (requires lsx). + pub inline fn @"vbitrevi.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73188000, p0, p1, p2); + } + + /// Encodes a `vbitsel.v` instruction (requires lsx). + pub inline fn @"vbitsel.v"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x0d100000, p0, p1, p2, p3); + } + + /// Encodes a `vbitseli.b` instruction (requires lsx). + pub inline fn @"vbitseli.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73c40000, p0, p1, p2); + } + + /// Encodes a `vbitset.b` instruction (requires lsx). + pub inline fn @"vbitset.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710e0000, p0, p1, p2); + } + + /// Encodes a `vbitset.d` instruction (requires lsx). + pub inline fn @"vbitset.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710f8000, p0, p1, p2); + } + + /// Encodes a `vbitset.h` instruction (requires lsx). + pub inline fn @"vbitset.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710e8000, p0, p1, p2); + } + + /// Encodes a `vbitset.w` instruction (requires lsx). + pub inline fn @"vbitset.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710f0000, p0, p1, p2); + } + + /// Encodes a `vbitseti.b` instruction (requires lsx). + pub inline fn @"vbitseti.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73142000, p0, p1, p2); + } + + /// Encodes a `vbitseti.d` instruction (requires lsx). + pub inline fn @"vbitseti.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73150000, p0, p1, p2); + } + + /// Encodes a `vbitseti.h` instruction (requires lsx). + pub inline fn @"vbitseti.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73144000, p0, p1, p2); + } + + /// Encodes a `vbitseti.w` instruction (requires lsx). + pub inline fn @"vbitseti.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73148000, p0, p1, p2); + } + + /// Encodes a `vbsll.v` instruction (requires lsx). + pub inline fn @"vbsll.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728e0000, p0, p1, p2); + } + + /// Encodes a `vbsrl.v` instruction (requires lsx). + pub inline fn @"vbsrl.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728e8000, p0, p1, p2); + } + + /// Encodes a `vclo.b` instruction (requires lsx). + pub inline fn @"vclo.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0000, p0, p1); + } + + /// Encodes a `vclo.d` instruction (requires lsx). + pub inline fn @"vclo.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0c00, p0, p1); + } + + /// Encodes a `vclo.h` instruction (requires lsx). + pub inline fn @"vclo.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0400, p0, p1); + } + + /// Encodes a `vclo.w` instruction (requires lsx). + pub inline fn @"vclo.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c0800, p0, p1); + } + + /// Encodes a `vclz.b` instruction (requires lsx). + pub inline fn @"vclz.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1000, p0, p1); + } + + /// Encodes a `vclz.d` instruction (requires lsx). + pub inline fn @"vclz.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1c00, p0, p1); + } + + /// Encodes a `vclz.h` instruction (requires lsx). + pub inline fn @"vclz.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1400, p0, p1); + } + + /// Encodes a `vclz.w` instruction (requires lsx). + pub inline fn @"vclz.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c1800, p0, p1); + } + + /// Encodes a `vdiv.b` instruction (requires lsx). + pub inline fn @"vdiv.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e00000, p0, p1, p2); + } + + /// Encodes a `vdiv.bu` instruction (requires lsx). + pub inline fn @"vdiv.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e40000, p0, p1, p2); + } + + /// Encodes a `vdiv.d` instruction (requires lsx). + pub inline fn @"vdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e18000, p0, p1, p2); + } + + /// Encodes a `vdiv.du` instruction (requires lsx). + pub inline fn @"vdiv.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e58000, p0, p1, p2); + } + + /// Encodes a `vdiv.h` instruction (requires lsx). + pub inline fn @"vdiv.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e08000, p0, p1, p2); + } + + /// Encodes a `vdiv.hu` instruction (requires lsx). + pub inline fn @"vdiv.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e48000, p0, p1, p2); + } + + /// Encodes a `vdiv.w` instruction (requires lsx). + pub inline fn @"vdiv.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e10000, p0, p1, p2); + } + + /// Encodes a `vdiv.wu` instruction (requires lsx). + pub inline fn @"vdiv.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e50000, p0, p1, p2); + } + + /// Encodes a `vext2xv.d.b` instruction (requires lasx). + pub inline fn @"vext2xv.d.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1800, p0, p1); + } + + /// Encodes a `vext2xv.d.h` instruction (requires lasx). + pub inline fn @"vext2xv.d.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2000, p0, p1); + } + + /// Encodes a `vext2xv.d.w` instruction (requires lasx). + pub inline fn @"vext2xv.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2400, p0, p1); + } + + /// Encodes a `vext2xv.du.bu` instruction (requires lasx). + pub inline fn @"vext2xv.du.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3000, p0, p1); + } + + /// Encodes a `vext2xv.du.hu` instruction (requires lasx). + pub inline fn @"vext2xv.du.hu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3800, p0, p1); + } + + /// Encodes a `vext2xv.du.wu` instruction (requires lasx). + pub inline fn @"vext2xv.du.wu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3c00, p0, p1); + } + + /// Encodes a `vext2xv.h.b` instruction (requires lasx). + pub inline fn @"vext2xv.h.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1000, p0, p1); + } + + /// Encodes a `vext2xv.hu.bu` instruction (requires lasx). + pub inline fn @"vext2xv.hu.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2800, p0, p1); + } + + /// Encodes a `vext2xv.w.b` instruction (requires lasx). + pub inline fn @"vext2xv.w.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1400, p0, p1); + } + + /// Encodes a `vext2xv.w.h` instruction (requires lasx). + pub inline fn @"vext2xv.w.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f1c00, p0, p1); + } + + /// Encodes a `vext2xv.wu.bu` instruction (requires lasx). + pub inline fn @"vext2xv.wu.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f2c00, p0, p1); + } + + /// Encodes a `vext2xv.wu.hu` instruction (requires lasx). + pub inline fn @"vext2xv.wu.hu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769f3400, p0, p1); + } + + /// Encodes a `vexth.d.w` instruction (requires lsx). + pub inline fn @"vexth.d.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ee800, p0, p1); + } + + /// Encodes a `vexth.du.wu` instruction (requires lsx). + pub inline fn @"vexth.du.wu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ef800, p0, p1); + } + + /// Encodes a `vexth.h.b` instruction (requires lsx). + pub inline fn @"vexth.h.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ee000, p0, p1); + } + + /// Encodes a `vexth.hu.bu` instruction (requires lsx). + pub inline fn @"vexth.hu.bu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ef000, p0, p1); + } + + /// Encodes a `vexth.q.d` instruction (requires lsx). + pub inline fn @"vexth.q.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729eec00, p0, p1); + } + + /// Encodes a `vexth.qu.du` instruction (requires lsx). + pub inline fn @"vexth.qu.du"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729efc00, p0, p1); + } + + /// Encodes a `vexth.w.h` instruction (requires lsx). + pub inline fn @"vexth.w.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ee400, p0, p1); + } + + /// Encodes a `vexth.wu.hu` instruction (requires lsx). + pub inline fn @"vexth.wu.hu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ef400, p0, p1); + } + + /// Encodes a `vextl.q.d` instruction (requires lsx). + pub inline fn @"vextl.q.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x73090000, p0, p1); + } + + /// Encodes a `vextl.qu.du` instruction (requires lsx). + pub inline fn @"vextl.qu.du"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x730d0000, p0, p1); + } + + /// Encodes a `vextrins.b` instruction (requires lsx). + pub inline fn @"vextrins.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x738c0000, p0, p1, p2); + } + + /// Encodes a `vextrins.d` instruction (requires lsx). + pub inline fn @"vextrins.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73800000, p0, p1, p2); + } + + /// Encodes a `vextrins.h` instruction (requires lsx). + pub inline fn @"vextrins.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73880000, p0, p1, p2); + } + + /// Encodes a `vextrins.w` instruction (requires lsx). + pub inline fn @"vextrins.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73840000, p0, p1, p2); + } + + /// Encodes a `vfadd.d` instruction (requires lsx). + pub inline fn @"vfadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71310000, p0, p1, p2); + } + + /// Encodes a `vfadd.s` instruction (requires lsx). + pub inline fn @"vfadd.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71308000, p0, p1, p2); + } + + /// Encodes a `vfclass.d` instruction (requires lsx). + pub inline fn @"vfclass.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cd800, p0, p1); + } + + /// Encodes a `vfclass.s` instruction (requires lsx). + pub inline fn @"vfclass.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cd400, p0, p1); + } + + /// Encodes a `vfcmp.caf.d` instruction (requires lsx). + pub inline fn @"vfcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c600000, p0, p1, p2); + } + + /// Encodes a `vfcmp.caf.s` instruction (requires lsx). + pub inline fn @"vfcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c500000, p0, p1, p2); + } + + /// Encodes a `vfcmp.ceq.d` instruction (requires lsx). + pub inline fn @"vfcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c620000, p0, p1, p2); + } + + /// Encodes a `vfcmp.ceq.s` instruction (requires lsx). + pub inline fn @"vfcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c520000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cle.d` instruction (requires lsx). + pub inline fn @"vfcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c630000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cle.s` instruction (requires lsx). + pub inline fn @"vfcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c530000, p0, p1, p2); + } + + /// Encodes a `vfcmp.clt.d` instruction (requires lsx). + pub inline fn @"vfcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c610000, p0, p1, p2); + } + + /// Encodes a `vfcmp.clt.s` instruction (requires lsx). + pub inline fn @"vfcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c510000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cne.d` instruction (requires lsx). + pub inline fn @"vfcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c680000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cne.s` instruction (requires lsx). + pub inline fn @"vfcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c580000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cor.d` instruction (requires lsx). + pub inline fn @"vfcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6a0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cor.s` instruction (requires lsx). + pub inline fn @"vfcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5a0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cueq.d` instruction (requires lsx). + pub inline fn @"vfcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c660000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cueq.s` instruction (requires lsx). + pub inline fn @"vfcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c560000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cule.d` instruction (requires lsx). + pub inline fn @"vfcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c670000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cule.s` instruction (requires lsx). + pub inline fn @"vfcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c570000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cult.d` instruction (requires lsx). + pub inline fn @"vfcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c650000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cult.s` instruction (requires lsx). + pub inline fn @"vfcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c550000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cun.d` instruction (requires lsx). + pub inline fn @"vfcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c640000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cun.s` instruction (requires lsx). + pub inline fn @"vfcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c540000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cune.d` instruction (requires lsx). + pub inline fn @"vfcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6c0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.cune.s` instruction (requires lsx). + pub inline fn @"vfcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5c0000, p0, p1, p2); + } + + /// Encodes a `vfcmp.saf.d` instruction (requires lsx). + pub inline fn @"vfcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c608000, p0, p1, p2); + } + + /// Encodes a `vfcmp.saf.s` instruction (requires lsx). + pub inline fn @"vfcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c508000, p0, p1, p2); + } + + /// Encodes a `vfcmp.seq.d` instruction (requires lsx). + pub inline fn @"vfcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c628000, p0, p1, p2); + } + + /// Encodes a `vfcmp.seq.s` instruction (requires lsx). + pub inline fn @"vfcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c528000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sle.d` instruction (requires lsx). + pub inline fn @"vfcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c638000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sle.s` instruction (requires lsx). + pub inline fn @"vfcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c538000, p0, p1, p2); + } + + /// Encodes a `vfcmp.slt.d` instruction (requires lsx). + pub inline fn @"vfcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c618000, p0, p1, p2); + } + + /// Encodes a `vfcmp.slt.s` instruction (requires lsx). + pub inline fn @"vfcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c518000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sne.d` instruction (requires lsx). + pub inline fn @"vfcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c688000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sne.s` instruction (requires lsx). + pub inline fn @"vfcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c588000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sor.d` instruction (requires lsx). + pub inline fn @"vfcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6a8000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sor.s` instruction (requires lsx). + pub inline fn @"vfcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5a8000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sueq.d` instruction (requires lsx). + pub inline fn @"vfcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c668000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sueq.s` instruction (requires lsx). + pub inline fn @"vfcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c568000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sule.d` instruction (requires lsx). + pub inline fn @"vfcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c678000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sule.s` instruction (requires lsx). + pub inline fn @"vfcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c578000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sult.d` instruction (requires lsx). + pub inline fn @"vfcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c658000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sult.s` instruction (requires lsx). + pub inline fn @"vfcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c558000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sun.d` instruction (requires lsx). + pub inline fn @"vfcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c648000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sun.s` instruction (requires lsx). + pub inline fn @"vfcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c548000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sune.d` instruction (requires lsx). + pub inline fn @"vfcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c6c8000, p0, p1, p2); + } + + /// Encodes a `vfcmp.sune.s` instruction (requires lsx). + pub inline fn @"vfcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x0c5c8000, p0, p1, p2); + } + + /// Encodes a `vfcvt.h.s` instruction (requires lsx). + pub inline fn @"vfcvt.h.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71460000, p0, p1, p2); + } + + /// Encodes a `vfcvt.s.d` instruction (requires lsx). + pub inline fn @"vfcvt.s.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71468000, p0, p1, p2); + } + + /// Encodes a `vfcvth.d.s` instruction (requires lsx). + pub inline fn @"vfcvth.d.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729df400, p0, p1); + } + + /// Encodes a `vfcvth.s.h` instruction (requires lsx). + pub inline fn @"vfcvth.s.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729dec00, p0, p1); + } + + /// Encodes a `vfcvtl.d.s` instruction (requires lsx). + pub inline fn @"vfcvtl.d.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729df000, p0, p1); + } + + /// Encodes a `vfcvtl.s.h` instruction (requires lsx). + pub inline fn @"vfcvtl.s.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729de800, p0, p1); + } + + /// Encodes a `vfdiv.d` instruction (requires lsx). + pub inline fn @"vfdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713b0000, p0, p1, p2); + } + + /// Encodes a `vfdiv.s` instruction (requires lsx). + pub inline fn @"vfdiv.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713a8000, p0, p1, p2); + } + + /// Encodes a `vffint.d.l` instruction (requires lsx). + pub inline fn @"vffint.d.l"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0800, p0, p1); + } + + /// Encodes a `vffint.d.lu` instruction (requires lsx). + pub inline fn @"vffint.d.lu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0c00, p0, p1); + } + + /// Encodes a `vffint.s.l` instruction (requires lsx). + pub inline fn @"vffint.s.l"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71480000, p0, p1, p2); + } + + /// Encodes a `vffint.s.w` instruction (requires lsx). + pub inline fn @"vffint.s.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0000, p0, p1); + } + + /// Encodes a `vffint.s.wu` instruction (requires lsx). + pub inline fn @"vffint.s.wu"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e0400, p0, p1); + } + + /// Encodes a `vffinth.d.w` instruction (requires lsx). + pub inline fn @"vffinth.d.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e1400, p0, p1); + } + + /// Encodes a `vffintl.d.w` instruction (requires lsx). + pub inline fn @"vffintl.d.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e1000, p0, p1); + } + + /// Encodes a `vflogb.d` instruction (requires lsx). + pub inline fn @"vflogb.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cc800, p0, p1); + } + + /// Encodes a `vflogb.s` instruction (requires lsx). + pub inline fn @"vflogb.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cc400, p0, p1); + } + + /// Encodes a `vfmadd.d` instruction (requires lsx). + pub inline fn @"vfmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09200000, p0, p1, p2, p3); + } + + /// Encodes a `vfmadd.s` instruction (requires lsx). + pub inline fn @"vfmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09100000, p0, p1, p2, p3); + } + + /// Encodes a `vfmax.d` instruction (requires lsx). + pub inline fn @"vfmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713d0000, p0, p1, p2); + } + + /// Encodes a `vfmax.s` instruction (requires lsx). + pub inline fn @"vfmax.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713c8000, p0, p1, p2); + } + + /// Encodes a `vfmaxa.d` instruction (requires lsx). + pub inline fn @"vfmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71410000, p0, p1, p2); + } + + /// Encodes a `vfmaxa.s` instruction (requires lsx). + pub inline fn @"vfmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71408000, p0, p1, p2); + } + + /// Encodes a `vfmin.d` instruction (requires lsx). + pub inline fn @"vfmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713f0000, p0, p1, p2); + } + + /// Encodes a `vfmin.s` instruction (requires lsx). + pub inline fn @"vfmin.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x713e8000, p0, p1, p2); + } + + /// Encodes a `vfmina.d` instruction (requires lsx). + pub inline fn @"vfmina.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71430000, p0, p1, p2); + } + + /// Encodes a `vfmina.s` instruction (requires lsx). + pub inline fn @"vfmina.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71428000, p0, p1, p2); + } + + /// Encodes a `vfmsub.d` instruction (requires lsx). + pub inline fn @"vfmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09600000, p0, p1, p2, p3); + } + + /// Encodes a `vfmsub.s` instruction (requires lsx). + pub inline fn @"vfmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09500000, p0, p1, p2, p3); + } + + /// Encodes a `vfmul.d` instruction (requires lsx). + pub inline fn @"vfmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71390000, p0, p1, p2); + } + + /// Encodes a `vfmul.s` instruction (requires lsx). + pub inline fn @"vfmul.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71388000, p0, p1, p2); + } + + /// Encodes a `vfnmadd.d` instruction (requires lsx). + pub inline fn @"vfnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09a00000, p0, p1, p2, p3); + } + + /// Encodes a `vfnmadd.s` instruction (requires lsx). + pub inline fn @"vfnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09900000, p0, p1, p2, p3); + } + + /// Encodes a `vfnmsub.d` instruction (requires lsx). + pub inline fn @"vfnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09e00000, p0, p1, p2, p3); + } + + /// Encodes a `vfnmsub.s` instruction (requires lsx). + pub inline fn @"vfnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x09d00000, p0, p1, p2, p3); + } + + /// Encodes a `vfrecip.d` instruction (requires lsx). + pub inline fn @"vfrecip.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cf800, p0, p1); + } + + /// Encodes a `vfrecip.s` instruction (requires lsx). + pub inline fn @"vfrecip.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729cf400, p0, p1); + } + + /// Encodes a `vfrecipe.d` instruction (requires lsx). + pub inline fn @"vfrecipe.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d1800, p0, p1); + } + + /// Encodes a `vfrecipe.s` instruction (requires lsx). + pub inline fn @"vfrecipe.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d1400, p0, p1); + } + + /// Encodes a `vfrint.d` instruction (requires lsx). + pub inline fn @"vfrint.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d3800, p0, p1); + } + + /// Encodes a `vfrint.s` instruction (requires lsx). + pub inline fn @"vfrint.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d3400, p0, p1); + } + + /// Encodes a `vfrintrm.d` instruction (requires lsx). + pub inline fn @"vfrintrm.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d4800, p0, p1); + } + + /// Encodes a `vfrintrm.s` instruction (requires lsx). + pub inline fn @"vfrintrm.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d4400, p0, p1); + } + + /// Encodes a `vfrintrne.d` instruction (requires lsx). + pub inline fn @"vfrintrne.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d7800, p0, p1); + } + + /// Encodes a `vfrintrne.s` instruction (requires lsx). + pub inline fn @"vfrintrne.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d7400, p0, p1); + } + + /// Encodes a `vfrintrp.d` instruction (requires lsx). + pub inline fn @"vfrintrp.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d5800, p0, p1); + } + + /// Encodes a `vfrintrp.s` instruction (requires lsx). + pub inline fn @"vfrintrp.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d5400, p0, p1); + } + + /// Encodes a `vfrintrz.d` instruction (requires lsx). + pub inline fn @"vfrintrz.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d6800, p0, p1); + } + + /// Encodes a `vfrintrz.s` instruction (requires lsx). + pub inline fn @"vfrintrz.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d6400, p0, p1); + } + + /// Encodes a `vfrsqrt.d` instruction (requires lsx). + pub inline fn @"vfrsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d0800, p0, p1); + } + + /// Encodes a `vfrsqrt.s` instruction (requires lsx). + pub inline fn @"vfrsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d0400, p0, p1); + } + + /// Encodes a `vfrsqrte.d` instruction (requires lsx). + pub inline fn @"vfrsqrte.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d2800, p0, p1); + } + + /// Encodes a `vfrsqrte.s` instruction (requires lsx). + pub inline fn @"vfrsqrte.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729d2400, p0, p1); + } + + /// Encodes a `vfrstp.b` instruction (requires lsx). + pub inline fn @"vfrstp.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712b0000, p0, p1, p2); + } + + /// Encodes a `vfrstp.h` instruction (requires lsx). + pub inline fn @"vfrstp.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712b8000, p0, p1, p2); + } + + /// Encodes a `vfrstpi.b` instruction (requires lsx). + pub inline fn @"vfrstpi.b"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x729a0000, p0, p1, p2); + } + + /// Encodes a `vfrstpi.h` instruction (requires lsx). + pub inline fn @"vfrstpi.h"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x729a8000, p0, p1, p2); + } + + /// Encodes a `vfsqrt.d` instruction (requires lsx). + pub inline fn @"vfsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ce800, p0, p1); + } + + /// Encodes a `vfsqrt.s` instruction (requires lsx). + pub inline fn @"vfsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ce400, p0, p1); + } + + /// Encodes a `vfsub.d` instruction (requires lsx). + pub inline fn @"vfsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71330000, p0, p1, p2); + } + + /// Encodes a `vfsub.s` instruction (requires lsx). + pub inline fn @"vfsub.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71328000, p0, p1, p2); + } + + /// Encodes a `vftint.l.d` instruction (requires lsx). + pub inline fn @"vftint.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3400, p0, p1); + } + + /// Encodes a `vftint.lu.d` instruction (requires lsx). + pub inline fn @"vftint.lu.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5c00, p0, p1); + } + + /// Encodes a `vftint.w.d` instruction (requires lsx). + pub inline fn @"vftint.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71498000, p0, p1, p2); + } + + /// Encodes a `vftint.w.s` instruction (requires lsx). + pub inline fn @"vftint.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3000, p0, p1); + } + + /// Encodes a `vftint.wu.s` instruction (requires lsx). + pub inline fn @"vftint.wu.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5800, p0, p1); + } + + /// Encodes a `vftinth.l.s` instruction (requires lsx). + pub inline fn @"vftinth.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8400, p0, p1); + } + + /// Encodes a `vftintl.l.s` instruction (requires lsx). + pub inline fn @"vftintl.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8000, p0, p1); + } + + /// Encodes a `vftintrm.l.d` instruction (requires lsx). + pub inline fn @"vftintrm.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3c00, p0, p1); + } + + /// Encodes a `vftintrm.w.d` instruction (requires lsx). + pub inline fn @"vftintrm.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714a0000, p0, p1, p2); + } + + /// Encodes a `vftintrm.w.s` instruction (requires lsx). + pub inline fn @"vftintrm.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e3800, p0, p1); + } + + /// Encodes a `vftintrmh.l.s` instruction (requires lsx). + pub inline fn @"vftintrmh.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8c00, p0, p1); + } + + /// Encodes a `vftintrml.l.s` instruction (requires lsx). + pub inline fn @"vftintrml.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e8800, p0, p1); + } + + /// Encodes a `vftintrne.l.d` instruction (requires lsx). + pub inline fn @"vftintrne.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5400, p0, p1); + } + + /// Encodes a `vftintrne.w.d` instruction (requires lsx). + pub inline fn @"vftintrne.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714b8000, p0, p1, p2); + } + + /// Encodes a `vftintrne.w.s` instruction (requires lsx). + pub inline fn @"vftintrne.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e5000, p0, p1); + } + + /// Encodes a `vftintrneh.l.s` instruction (requires lsx). + pub inline fn @"vftintrneh.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ea400, p0, p1); + } + + /// Encodes a `vftintrnel.l.s` instruction (requires lsx). + pub inline fn @"vftintrnel.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729ea000, p0, p1); + } + + /// Encodes a `vftintrp.l.d` instruction (requires lsx). + pub inline fn @"vftintrp.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4400, p0, p1); + } + + /// Encodes a `vftintrp.w.d` instruction (requires lsx). + pub inline fn @"vftintrp.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714a8000, p0, p1, p2); + } + + /// Encodes a `vftintrp.w.s` instruction (requires lsx). + pub inline fn @"vftintrp.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4000, p0, p1); + } + + /// Encodes a `vftintrph.l.s` instruction (requires lsx). + pub inline fn @"vftintrph.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9400, p0, p1); + } + + /// Encodes a `vftintrpl.l.s` instruction (requires lsx). + pub inline fn @"vftintrpl.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9000, p0, p1); + } + + /// Encodes a `vftintrz.l.d` instruction (requires lsx). + pub inline fn @"vftintrz.l.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4c00, p0, p1); + } + + /// Encodes a `vftintrz.lu.d` instruction (requires lsx). + pub inline fn @"vftintrz.lu.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e7400, p0, p1); + } + + /// Encodes a `vftintrz.w.d` instruction (requires lsx). + pub inline fn @"vftintrz.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x714b0000, p0, p1, p2); + } + + /// Encodes a `vftintrz.w.s` instruction (requires lsx). + pub inline fn @"vftintrz.w.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e4800, p0, p1); + } + + /// Encodes a `vftintrz.wu.s` instruction (requires lsx). + pub inline fn @"vftintrz.wu.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e7000, p0, p1); + } + + /// Encodes a `vftintrzh.l.s` instruction (requires lsx). + pub inline fn @"vftintrzh.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9c00, p0, p1); + } + + /// Encodes a `vftintrzl.l.s` instruction (requires lsx). + pub inline fn @"vftintrzl.l.s"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729e9800, p0, p1); + } + + /// Encodes a `vhaddw.d.w` instruction (requires lsx). + pub inline fn @"vhaddw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70550000, p0, p1, p2); + } + + /// Encodes a `vhaddw.du.wu` instruction (requires lsx). + pub inline fn @"vhaddw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70590000, p0, p1, p2); + } + + /// Encodes a `vhaddw.h.b` instruction (requires lsx). + pub inline fn @"vhaddw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70540000, p0, p1, p2); + } + + /// Encodes a `vhaddw.hu.bu` instruction (requires lsx). + pub inline fn @"vhaddw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70580000, p0, p1, p2); + } + + /// Encodes a `vhaddw.q.d` instruction (requires lsx). + pub inline fn @"vhaddw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70558000, p0, p1, p2); + } + + /// Encodes a `vhaddw.qu.du` instruction (requires lsx). + pub inline fn @"vhaddw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70598000, p0, p1, p2); + } + + /// Encodes a `vhaddw.w.h` instruction (requires lsx). + pub inline fn @"vhaddw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70548000, p0, p1, p2); + } + + /// Encodes a `vhaddw.wu.hu` instruction (requires lsx). + pub inline fn @"vhaddw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70588000, p0, p1, p2); + } + + /// Encodes a `vhsubw.d.w` instruction (requires lsx). + pub inline fn @"vhsubw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70570000, p0, p1, p2); + } + + /// Encodes a `vhsubw.du.wu` instruction (requires lsx). + pub inline fn @"vhsubw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705b0000, p0, p1, p2); + } + + /// Encodes a `vhsubw.h.b` instruction (requires lsx). + pub inline fn @"vhsubw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70560000, p0, p1, p2); + } + + /// Encodes a `vhsubw.hu.bu` instruction (requires lsx). + pub inline fn @"vhsubw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705a0000, p0, p1, p2); + } + + /// Encodes a `vhsubw.q.d` instruction (requires lsx). + pub inline fn @"vhsubw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70578000, p0, p1, p2); + } + + /// Encodes a `vhsubw.qu.du` instruction (requires lsx). + pub inline fn @"vhsubw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705b8000, p0, p1, p2); + } + + /// Encodes a `vhsubw.w.h` instruction (requires lsx). + pub inline fn @"vhsubw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70568000, p0, p1, p2); + } + + /// Encodes a `vhsubw.wu.hu` instruction (requires lsx). + pub inline fn @"vhsubw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x705a8000, p0, p1, p2); + } + + /// Encodes a `vilvh.b` instruction (requires lsx). + pub inline fn @"vilvh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711c0000, p0, p1, p2); + } + + /// Encodes a `vilvh.d` instruction (requires lsx). + pub inline fn @"vilvh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711d8000, p0, p1, p2); + } + + /// Encodes a `vilvh.h` instruction (requires lsx). + pub inline fn @"vilvh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711c8000, p0, p1, p2); + } + + /// Encodes a `vilvh.w` instruction (requires lsx). + pub inline fn @"vilvh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711d0000, p0, p1, p2); + } + + /// Encodes a `vilvl.b` instruction (requires lsx). + pub inline fn @"vilvl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711a0000, p0, p1, p2); + } + + /// Encodes a `vilvl.d` instruction (requires lsx). + pub inline fn @"vilvl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711b8000, p0, p1, p2); + } + + /// Encodes a `vilvl.h` instruction (requires lsx). + pub inline fn @"vilvl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711a8000, p0, p1, p2); + } + + /// Encodes a `vilvl.w` instruction (requires lsx). + pub inline fn @"vilvl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711b0000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.b` instruction (requires lsx). + pub inline fn @"vinsgr2vr.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdJUk4(0x72eb8000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.d` instruction (requires lsx). + pub inline fn @"vinsgr2vr.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeVdJUk1(0x72ebf000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.h` instruction (requires lsx). + pub inline fn @"vinsgr2vr.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdJUk3(0x72ebc000, p0, p1, p2); + } + + /// Encodes a `vinsgr2vr.w` instruction (requires lsx). + pub inline fn @"vinsgr2vr.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeVdJUk2(0x72ebe000, p0, p1, p2); + } + + /// Encodes a `vld` instruction (requires lsx). + pub inline fn vld(p0: Register, p1: Register, p2: i12) Instruction { + return encodeVdJSk12(0x2c000000, p0, p1, p2); + } + + /// Encodes a `vldi` instruction (requires lsx). + pub inline fn vldi(p0: Register, p1: i13) Instruction { + return encodeVdSj13(0x73e00000, p0, p1); + } + + /// Encodes a `vldrepl.b` instruction (requires lsx). + pub inline fn @"vldrepl.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeVdJSk12(0x30800000, p0, p1, p2); + } + + /// Encodes a `vldrepl.d` instruction (requires lsx). + pub inline fn @"vldrepl.d"(p0: Register, p1: Register, p2: i9) Instruction { + return encodeVdJSk9ps3(0x30100000, p0, p1, p2); + } + + /// Encodes a `vldrepl.h` instruction (requires lsx). + pub inline fn @"vldrepl.h"(p0: Register, p1: Register, p2: i11) Instruction { + return encodeVdJSk11ps1(0x30400000, p0, p1, p2); + } + + /// Encodes a `vldrepl.w` instruction (requires lsx). + pub inline fn @"vldrepl.w"(p0: Register, p1: Register, p2: i10) Instruction { + return encodeVdJSk10ps2(0x30200000, p0, p1, p2); + } + + /// Encodes a `vldx` instruction (requires lsx). + pub inline fn vldx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdJK(0x38400000, p0, p1, p2); + } + + /// Encodes a `vmadd.b` instruction (requires lsx). + pub inline fn @"vmadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a80000, p0, p1, p2); + } + + /// Encodes a `vmadd.d` instruction (requires lsx). + pub inline fn @"vmadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a98000, p0, p1, p2); + } + + /// Encodes a `vmadd.h` instruction (requires lsx). + pub inline fn @"vmadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a88000, p0, p1, p2); + } + + /// Encodes a `vmadd.w` instruction (requires lsx). + pub inline fn @"vmadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a90000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.d.w` instruction (requires lsx). + pub inline fn @"vmaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ad0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.d.wu` instruction (requires lsx). + pub inline fn @"vmaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b50000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.d.wu.w` instruction (requires lsx). + pub inline fn @"vmaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bd0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.h.b` instruction (requires lsx). + pub inline fn @"vmaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ac0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.h.bu` instruction (requires lsx). + pub inline fn @"vmaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b40000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.h.bu.b` instruction (requires lsx). + pub inline fn @"vmaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bc0000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.q.d` instruction (requires lsx). + pub inline fn @"vmaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ad8000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.q.du` instruction (requires lsx). + pub inline fn @"vmaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b58000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.q.du.d` instruction (requires lsx). + pub inline fn @"vmaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bd8000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.w.h` instruction (requires lsx). + pub inline fn @"vmaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ac8000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.w.hu` instruction (requires lsx). + pub inline fn @"vmaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b48000, p0, p1, p2); + } + + /// Encodes a `vmaddwev.w.hu.h` instruction (requires lsx). + pub inline fn @"vmaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bc8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.d.w` instruction (requires lsx). + pub inline fn @"vmaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70af0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.d.wu` instruction (requires lsx). + pub inline fn @"vmaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b70000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.d.wu.w` instruction (requires lsx). + pub inline fn @"vmaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bf0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.h.b` instruction (requires lsx). + pub inline fn @"vmaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ae0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.h.bu` instruction (requires lsx). + pub inline fn @"vmaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b60000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.h.bu.b` instruction (requires lsx). + pub inline fn @"vmaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70be0000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.q.d` instruction (requires lsx). + pub inline fn @"vmaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70af8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.q.du` instruction (requires lsx). + pub inline fn @"vmaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b78000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.q.du.d` instruction (requires lsx). + pub inline fn @"vmaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70bf8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.w.h` instruction (requires lsx). + pub inline fn @"vmaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ae8000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.w.hu` instruction (requires lsx). + pub inline fn @"vmaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70b68000, p0, p1, p2); + } + + /// Encodes a `vmaddwod.w.hu.h` instruction (requires lsx). + pub inline fn @"vmaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70be8000, p0, p1, p2); + } + + /// Encodes a `vmax.b` instruction (requires lsx). + pub inline fn @"vmax.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70700000, p0, p1, p2); + } + + /// Encodes a `vmax.bu` instruction (requires lsx). + pub inline fn @"vmax.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70740000, p0, p1, p2); + } + + /// Encodes a `vmax.d` instruction (requires lsx). + pub inline fn @"vmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70718000, p0, p1, p2); + } + + /// Encodes a `vmax.du` instruction (requires lsx). + pub inline fn @"vmax.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70758000, p0, p1, p2); + } + + /// Encodes a `vmax.h` instruction (requires lsx). + pub inline fn @"vmax.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70708000, p0, p1, p2); + } + + /// Encodes a `vmax.hu` instruction (requires lsx). + pub inline fn @"vmax.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70748000, p0, p1, p2); + } + + /// Encodes a `vmax.w` instruction (requires lsx). + pub inline fn @"vmax.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70710000, p0, p1, p2); + } + + /// Encodes a `vmax.wu` instruction (requires lsx). + pub inline fn @"vmax.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70750000, p0, p1, p2); + } + + /// Encodes a `vmaxi.b` instruction (requires lsx). + pub inline fn @"vmaxi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72900000, p0, p1, p2); + } + + /// Encodes a `vmaxi.bu` instruction (requires lsx). + pub inline fn @"vmaxi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72940000, p0, p1, p2); + } + + /// Encodes a `vmaxi.d` instruction (requires lsx). + pub inline fn @"vmaxi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72918000, p0, p1, p2); + } + + /// Encodes a `vmaxi.du` instruction (requires lsx). + pub inline fn @"vmaxi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72958000, p0, p1, p2); + } + + /// Encodes a `vmaxi.h` instruction (requires lsx). + pub inline fn @"vmaxi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72908000, p0, p1, p2); + } + + /// Encodes a `vmaxi.hu` instruction (requires lsx). + pub inline fn @"vmaxi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72948000, p0, p1, p2); + } + + /// Encodes a `vmaxi.w` instruction (requires lsx). + pub inline fn @"vmaxi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72910000, p0, p1, p2); + } + + /// Encodes a `vmaxi.wu` instruction (requires lsx). + pub inline fn @"vmaxi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72950000, p0, p1, p2); + } + + /// Encodes a `vmepatmsk.v` instruction (requires lsx). + pub inline fn @"vmepatmsk.v"(p0: Register, p1: u5, p2: u5) Instruction { + return encodeVdUj5Uk5(0x729b8000, p0, p1, p2); + } + + /// Encodes a `vmin.b` instruction (requires lsx). + pub inline fn @"vmin.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70720000, p0, p1, p2); + } + + /// Encodes a `vmin.bu` instruction (requires lsx). + pub inline fn @"vmin.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70760000, p0, p1, p2); + } + + /// Encodes a `vmin.d` instruction (requires lsx). + pub inline fn @"vmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70738000, p0, p1, p2); + } + + /// Encodes a `vmin.du` instruction (requires lsx). + pub inline fn @"vmin.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70778000, p0, p1, p2); + } + + /// Encodes a `vmin.h` instruction (requires lsx). + pub inline fn @"vmin.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70728000, p0, p1, p2); + } + + /// Encodes a `vmin.hu` instruction (requires lsx). + pub inline fn @"vmin.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70768000, p0, p1, p2); + } + + /// Encodes a `vmin.w` instruction (requires lsx). + pub inline fn @"vmin.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70730000, p0, p1, p2); + } + + /// Encodes a `vmin.wu` instruction (requires lsx). + pub inline fn @"vmin.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70770000, p0, p1, p2); + } + + /// Encodes a `vmini.b` instruction (requires lsx). + pub inline fn @"vmini.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72920000, p0, p1, p2); + } + + /// Encodes a `vmini.bu` instruction (requires lsx). + pub inline fn @"vmini.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72960000, p0, p1, p2); + } + + /// Encodes a `vmini.d` instruction (requires lsx). + pub inline fn @"vmini.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72938000, p0, p1, p2); + } + + /// Encodes a `vmini.du` instruction (requires lsx). + pub inline fn @"vmini.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72978000, p0, p1, p2); + } + + /// Encodes a `vmini.h` instruction (requires lsx). + pub inline fn @"vmini.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72928000, p0, p1, p2); + } + + /// Encodes a `vmini.hu` instruction (requires lsx). + pub inline fn @"vmini.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72968000, p0, p1, p2); + } + + /// Encodes a `vmini.w` instruction (requires lsx). + pub inline fn @"vmini.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72930000, p0, p1, p2); + } + + /// Encodes a `vmini.wu` instruction (requires lsx). + pub inline fn @"vmini.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72970000, p0, p1, p2); + } + + /// Encodes a `vmod.b` instruction (requires lsx). + pub inline fn @"vmod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e20000, p0, p1, p2); + } + + /// Encodes a `vmod.bu` instruction (requires lsx). + pub inline fn @"vmod.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e60000, p0, p1, p2); + } + + /// Encodes a `vmod.d` instruction (requires lsx). + pub inline fn @"vmod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e38000, p0, p1, p2); + } + + /// Encodes a `vmod.du` instruction (requires lsx). + pub inline fn @"vmod.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e78000, p0, p1, p2); + } + + /// Encodes a `vmod.h` instruction (requires lsx). + pub inline fn @"vmod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e28000, p0, p1, p2); + } + + /// Encodes a `vmod.hu` instruction (requires lsx). + pub inline fn @"vmod.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e68000, p0, p1, p2); + } + + /// Encodes a `vmod.w` instruction (requires lsx). + pub inline fn @"vmod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e30000, p0, p1, p2); + } + + /// Encodes a `vmod.wu` instruction (requires lsx). + pub inline fn @"vmod.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e70000, p0, p1, p2); + } + + /// Encodes a `vmskgez.b` instruction (requires lsx). + pub inline fn @"vmskgez.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c5000, p0, p1); + } + + /// Encodes a `vmskltz.b` instruction (requires lsx). + pub inline fn @"vmskltz.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4000, p0, p1); + } + + /// Encodes a `vmskltz.d` instruction (requires lsx). + pub inline fn @"vmskltz.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4c00, p0, p1); + } + + /// Encodes a `vmskltz.h` instruction (requires lsx). + pub inline fn @"vmskltz.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4400, p0, p1); + } + + /// Encodes a `vmskltz.w` instruction (requires lsx). + pub inline fn @"vmskltz.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c4800, p0, p1); + } + + /// Encodes a `vmsknz.b` instruction (requires lsx). + pub inline fn @"vmsknz.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c6000, p0, p1); + } + + /// Encodes a `vmsub.b` instruction (requires lsx). + pub inline fn @"vmsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70aa0000, p0, p1, p2); + } + + /// Encodes a `vmsub.d` instruction (requires lsx). + pub inline fn @"vmsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ab8000, p0, p1, p2); + } + + /// Encodes a `vmsub.h` instruction (requires lsx). + pub inline fn @"vmsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70aa8000, p0, p1, p2); + } + + /// Encodes a `vmsub.w` instruction (requires lsx). + pub inline fn @"vmsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ab0000, p0, p1, p2); + } + + /// Encodes a `vmuh.b` instruction (requires lsx). + pub inline fn @"vmuh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70860000, p0, p1, p2); + } + + /// Encodes a `vmuh.bu` instruction (requires lsx). + pub inline fn @"vmuh.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70880000, p0, p1, p2); + } + + /// Encodes a `vmuh.d` instruction (requires lsx). + pub inline fn @"vmuh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70878000, p0, p1, p2); + } + + /// Encodes a `vmuh.du` instruction (requires lsx). + pub inline fn @"vmuh.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70898000, p0, p1, p2); + } + + /// Encodes a `vmuh.h` instruction (requires lsx). + pub inline fn @"vmuh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70868000, p0, p1, p2); + } + + /// Encodes a `vmuh.hu` instruction (requires lsx). + pub inline fn @"vmuh.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70888000, p0, p1, p2); + } + + /// Encodes a `vmuh.w` instruction (requires lsx). + pub inline fn @"vmuh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70870000, p0, p1, p2); + } + + /// Encodes a `vmuh.wu` instruction (requires lsx). + pub inline fn @"vmuh.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70890000, p0, p1, p2); + } + + /// Encodes a `vmul.b` instruction (requires lsx). + pub inline fn @"vmul.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70840000, p0, p1, p2); + } + + /// Encodes a `vmul.d` instruction (requires lsx). + pub inline fn @"vmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70858000, p0, p1, p2); + } + + /// Encodes a `vmul.h` instruction (requires lsx). + pub inline fn @"vmul.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70848000, p0, p1, p2); + } + + /// Encodes a `vmul.w` instruction (requires lsx). + pub inline fn @"vmul.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70850000, p0, p1, p2); + } + + /// Encodes a `vmulwev.d.w` instruction (requires lsx). + pub inline fn @"vmulwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70910000, p0, p1, p2); + } + + /// Encodes a `vmulwev.d.wu` instruction (requires lsx). + pub inline fn @"vmulwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70990000, p0, p1, p2); + } + + /// Encodes a `vmulwev.d.wu.w` instruction (requires lsx). + pub inline fn @"vmulwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a10000, p0, p1, p2); + } + + /// Encodes a `vmulwev.h.b` instruction (requires lsx). + pub inline fn @"vmulwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70900000, p0, p1, p2); + } + + /// Encodes a `vmulwev.h.bu` instruction (requires lsx). + pub inline fn @"vmulwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70980000, p0, p1, p2); + } + + /// Encodes a `vmulwev.h.bu.b` instruction (requires lsx). + pub inline fn @"vmulwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a00000, p0, p1, p2); + } + + /// Encodes a `vmulwev.q.d` instruction (requires lsx). + pub inline fn @"vmulwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70918000, p0, p1, p2); + } + + /// Encodes a `vmulwev.q.du` instruction (requires lsx). + pub inline fn @"vmulwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70998000, p0, p1, p2); + } + + /// Encodes a `vmulwev.q.du.d` instruction (requires lsx). + pub inline fn @"vmulwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a18000, p0, p1, p2); + } + + /// Encodes a `vmulwev.w.h` instruction (requires lsx). + pub inline fn @"vmulwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70908000, p0, p1, p2); + } + + /// Encodes a `vmulwev.w.hu` instruction (requires lsx). + pub inline fn @"vmulwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70988000, p0, p1, p2); + } + + /// Encodes a `vmulwev.w.hu.h` instruction (requires lsx). + pub inline fn @"vmulwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a08000, p0, p1, p2); + } + + /// Encodes a `vmulwod.d.w` instruction (requires lsx). + pub inline fn @"vmulwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70930000, p0, p1, p2); + } + + /// Encodes a `vmulwod.d.wu` instruction (requires lsx). + pub inline fn @"vmulwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709b0000, p0, p1, p2); + } + + /// Encodes a `vmulwod.d.wu.w` instruction (requires lsx). + pub inline fn @"vmulwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a30000, p0, p1, p2); + } + + /// Encodes a `vmulwod.h.b` instruction (requires lsx). + pub inline fn @"vmulwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70920000, p0, p1, p2); + } + + /// Encodes a `vmulwod.h.bu` instruction (requires lsx). + pub inline fn @"vmulwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709a0000, p0, p1, p2); + } + + /// Encodes a `vmulwod.h.bu.b` instruction (requires lsx). + pub inline fn @"vmulwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a20000, p0, p1, p2); + } + + /// Encodes a `vmulwod.q.d` instruction (requires lsx). + pub inline fn @"vmulwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70938000, p0, p1, p2); + } + + /// Encodes a `vmulwod.q.du` instruction (requires lsx). + pub inline fn @"vmulwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709b8000, p0, p1, p2); + } + + /// Encodes a `vmulwod.q.du.d` instruction (requires lsx). + pub inline fn @"vmulwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a38000, p0, p1, p2); + } + + /// Encodes a `vmulwod.w.h` instruction (requires lsx). + pub inline fn @"vmulwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70928000, p0, p1, p2); + } + + /// Encodes a `vmulwod.w.hu` instruction (requires lsx). + pub inline fn @"vmulwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x709a8000, p0, p1, p2); + } + + /// Encodes a `vmulwod.w.hu.h` instruction (requires lsx). + pub inline fn @"vmulwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70a28000, p0, p1, p2); + } + + /// Encodes a `vneg.b` instruction (requires lsx). + pub inline fn @"vneg.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3000, p0, p1); + } + + /// Encodes a `vneg.d` instruction (requires lsx). + pub inline fn @"vneg.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3c00, p0, p1); + } + + /// Encodes a `vneg.h` instruction (requires lsx). + pub inline fn @"vneg.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3400, p0, p1); + } + + /// Encodes a `vneg.w` instruction (requires lsx). + pub inline fn @"vneg.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c3800, p0, p1); + } + + /// Encodes a `vnor.v` instruction (requires lsx). + pub inline fn @"vnor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71278000, p0, p1, p2); + } + + /// Encodes a `vnori.b` instruction (requires lsx). + pub inline fn @"vnori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73dc0000, p0, p1, p2); + } + + /// Encodes a `vor.v` instruction (requires lsx). + pub inline fn @"vor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71268000, p0, p1, p2); + } + + /// Encodes a `vori.b` instruction (requires lsx). + pub inline fn @"vori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73d40000, p0, p1, p2); + } + + /// Encodes a `vorn.v` instruction (requires lsx). + pub inline fn @"vorn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71288000, p0, p1, p2); + } + + /// Encodes a `vpackev.b` instruction (requires lsx). + pub inline fn @"vpackev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71160000, p0, p1, p2); + } + + /// Encodes a `vpackev.d` instruction (requires lsx). + pub inline fn @"vpackev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71178000, p0, p1, p2); + } + + /// Encodes a `vpackev.h` instruction (requires lsx). + pub inline fn @"vpackev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71168000, p0, p1, p2); + } + + /// Encodes a `vpackev.w` instruction (requires lsx). + pub inline fn @"vpackev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71170000, p0, p1, p2); + } + + /// Encodes a `vpackod.b` instruction (requires lsx). + pub inline fn @"vpackod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71180000, p0, p1, p2); + } + + /// Encodes a `vpackod.d` instruction (requires lsx). + pub inline fn @"vpackod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71198000, p0, p1, p2); + } + + /// Encodes a `vpackod.h` instruction (requires lsx). + pub inline fn @"vpackod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71188000, p0, p1, p2); + } + + /// Encodes a `vpackod.w` instruction (requires lsx). + pub inline fn @"vpackod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71190000, p0, p1, p2); + } + + /// Encodes a `vpcnt.b` instruction (requires lsx). + pub inline fn @"vpcnt.b"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2000, p0, p1); + } + + /// Encodes a `vpcnt.d` instruction (requires lsx). + pub inline fn @"vpcnt.d"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2c00, p0, p1); + } + + /// Encodes a `vpcnt.h` instruction (requires lsx). + pub inline fn @"vpcnt.h"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2400, p0, p1); + } + + /// Encodes a `vpcnt.w` instruction (requires lsx). + pub inline fn @"vpcnt.w"(p0: Register, p1: Register) Instruction { + return encodeVdVj(0x729c2800, p0, p1); + } + + /// Encodes a `vpermi.w` instruction (requires lsx). + pub inline fn @"vpermi.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73e40000, p0, p1, p2); + } + + /// Encodes a `vpickev.b` instruction (requires lsx). + pub inline fn @"vpickev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711e0000, p0, p1, p2); + } + + /// Encodes a `vpickev.d` instruction (requires lsx). + pub inline fn @"vpickev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711f8000, p0, p1, p2); + } + + /// Encodes a `vpickev.h` instruction (requires lsx). + pub inline fn @"vpickev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711e8000, p0, p1, p2); + } + + /// Encodes a `vpickev.w` instruction (requires lsx). + pub inline fn @"vpickev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x711f0000, p0, p1, p2); + } + + /// Encodes a `vpickod.b` instruction (requires lsx). + pub inline fn @"vpickod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71200000, p0, p1, p2); + } + + /// Encodes a `vpickod.d` instruction (requires lsx). + pub inline fn @"vpickod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71218000, p0, p1, p2); + } + + /// Encodes a `vpickod.h` instruction (requires lsx). + pub inline fn @"vpickod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71208000, p0, p1, p2); + } + + /// Encodes a `vpickod.w` instruction (requires lsx). + pub inline fn @"vpickod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71210000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.b` instruction (requires lsx). + pub inline fn @"vpickve2gr.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDVjUk4(0x72ef8000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.bu` instruction (requires lsx). + pub inline fn @"vpickve2gr.bu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeDVjUk4(0x72f38000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.d` instruction (requires lsx). + pub inline fn @"vpickve2gr.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeDVjUk1(0x72eff000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.du` instruction (requires lsx). + pub inline fn @"vpickve2gr.du"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeDVjUk1(0x72f3f000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.h` instruction (requires lsx). + pub inline fn @"vpickve2gr.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDVjUk3(0x72efc000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.hu` instruction (requires lsx). + pub inline fn @"vpickve2gr.hu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDVjUk3(0x72f3c000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.w` instruction (requires lsx). + pub inline fn @"vpickve2gr.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDVjUk2(0x72efe000, p0, p1, p2); + } + + /// Encodes a `vpickve2gr.wu` instruction (requires lsx). + pub inline fn @"vpickve2gr.wu"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDVjUk2(0x72f3e000, p0, p1, p2); + } + + /// Encodes a `vreplgr2vr.b` instruction (requires lsx). + pub inline fn @"vreplgr2vr.b"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0000, p0, p1); + } + + /// Encodes a `vreplgr2vr.d` instruction (requires lsx). + pub inline fn @"vreplgr2vr.d"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0c00, p0, p1); + } + + /// Encodes a `vreplgr2vr.h` instruction (requires lsx). + pub inline fn @"vreplgr2vr.h"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0400, p0, p1); + } + + /// Encodes a `vreplgr2vr.w` instruction (requires lsx). + pub inline fn @"vreplgr2vr.w"(p0: Register, p1: Register) Instruction { + return encodeVdJ(0x729f0800, p0, p1); + } + + /// Encodes a `vreplve.b` instruction (requires lsx). + pub inline fn @"vreplve.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71220000, p0, p1, p2); + } + + /// Encodes a `vreplve.d` instruction (requires lsx). + pub inline fn @"vreplve.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71238000, p0, p1, p2); + } + + /// Encodes a `vreplve.h` instruction (requires lsx). + pub inline fn @"vreplve.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71228000, p0, p1, p2); + } + + /// Encodes a `vreplve.w` instruction (requires lsx). + pub inline fn @"vreplve.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjK(0x71230000, p0, p1, p2); + } + + /// Encodes a `vreplvei.b` instruction (requires lsx). + pub inline fn @"vreplvei.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72f78000, p0, p1, p2); + } + + /// Encodes a `vreplvei.d` instruction (requires lsx). + pub inline fn @"vreplvei.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeVdVjUk1(0x72f7f000, p0, p1, p2); + } + + /// Encodes a `vreplvei.h` instruction (requires lsx). + pub inline fn @"vreplvei.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72f7c000, p0, p1, p2); + } + + /// Encodes a `vreplvei.w` instruction (requires lsx). + pub inline fn @"vreplvei.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeVdVjUk2(0x72f7e000, p0, p1, p2); + } + + /// Encodes a `vrotr.b` instruction (requires lsx). + pub inline fn @"vrotr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ee0000, p0, p1, p2); + } + + /// Encodes a `vrotr.d` instruction (requires lsx). + pub inline fn @"vrotr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ef8000, p0, p1, p2); + } + + /// Encodes a `vrotr.h` instruction (requires lsx). + pub inline fn @"vrotr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ee8000, p0, p1, p2); + } + + /// Encodes a `vrotr.w` instruction (requires lsx). + pub inline fn @"vrotr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ef0000, p0, p1, p2); + } + + /// Encodes a `vrotri.b` instruction (requires lsx). + pub inline fn @"vrotri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72a02000, p0, p1, p2); + } + + /// Encodes a `vrotri.d` instruction (requires lsx). + pub inline fn @"vrotri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x72a10000, p0, p1, p2); + } + + /// Encodes a `vrotri.h` instruction (requires lsx). + pub inline fn @"vrotri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72a04000, p0, p1, p2); + } + + /// Encodes a `vrotri.w` instruction (requires lsx). + pub inline fn @"vrotri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72a08000, p0, p1, p2); + } + + /// Encodes a `vsadd.b` instruction (requires lsx). + pub inline fn @"vsadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70460000, p0, p1, p2); + } + + /// Encodes a `vsadd.bu` instruction (requires lsx). + pub inline fn @"vsadd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704a0000, p0, p1, p2); + } + + /// Encodes a `vsadd.d` instruction (requires lsx). + pub inline fn @"vsadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70478000, p0, p1, p2); + } + + /// Encodes a `vsadd.du` instruction (requires lsx). + pub inline fn @"vsadd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704b8000, p0, p1, p2); + } + + /// Encodes a `vsadd.h` instruction (requires lsx). + pub inline fn @"vsadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70468000, p0, p1, p2); + } + + /// Encodes a `vsadd.hu` instruction (requires lsx). + pub inline fn @"vsadd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704a8000, p0, p1, p2); + } + + /// Encodes a `vsadd.w` instruction (requires lsx). + pub inline fn @"vsadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70470000, p0, p1, p2); + } + + /// Encodes a `vsadd.wu` instruction (requires lsx). + pub inline fn @"vsadd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704b0000, p0, p1, p2); + } + + /// Encodes a `vsat.b` instruction (requires lsx). + pub inline fn @"vsat.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73242000, p0, p1, p2); + } + + /// Encodes a `vsat.bu` instruction (requires lsx). + pub inline fn @"vsat.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73282000, p0, p1, p2); + } + + /// Encodes a `vsat.d` instruction (requires lsx). + pub inline fn @"vsat.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73250000, p0, p1, p2); + } + + /// Encodes a `vsat.du` instruction (requires lsx). + pub inline fn @"vsat.du"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73290000, p0, p1, p2); + } + + /// Encodes a `vsat.h` instruction (requires lsx). + pub inline fn @"vsat.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73244000, p0, p1, p2); + } + + /// Encodes a `vsat.hu` instruction (requires lsx). + pub inline fn @"vsat.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73284000, p0, p1, p2); + } + + /// Encodes a `vsat.w` instruction (requires lsx). + pub inline fn @"vsat.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73248000, p0, p1, p2); + } + + /// Encodes a `vsat.wu` instruction (requires lsx). + pub inline fn @"vsat.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73288000, p0, p1, p2); + } + + /// Encodes a `vseq.b` instruction (requires lsx). + pub inline fn @"vseq.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70000000, p0, p1, p2); + } + + /// Encodes a `vseq.d` instruction (requires lsx). + pub inline fn @"vseq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70018000, p0, p1, p2); + } + + /// Encodes a `vseq.h` instruction (requires lsx). + pub inline fn @"vseq.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70008000, p0, p1, p2); + } + + /// Encodes a `vseq.w` instruction (requires lsx). + pub inline fn @"vseq.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70010000, p0, p1, p2); + } + + /// Encodes a `vseqi.b` instruction (requires lsx). + pub inline fn @"vseqi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72800000, p0, p1, p2); + } + + /// Encodes a `vseqi.d` instruction (requires lsx). + pub inline fn @"vseqi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72818000, p0, p1, p2); + } + + /// Encodes a `vseqi.h` instruction (requires lsx). + pub inline fn @"vseqi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72808000, p0, p1, p2); + } + + /// Encodes a `vseqi.w` instruction (requires lsx). + pub inline fn @"vseqi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72810000, p0, p1, p2); + } + + /// Encodes a `vsetallnez.b` instruction (requires f & lsx). + pub inline fn @"vsetallnez.b"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cb000, p0, p1); + } + + /// Encodes a `vsetallnez.d` instruction (requires f & lsx). + pub inline fn @"vsetallnez.d"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cbc00, p0, p1); + } + + /// Encodes a `vsetallnez.h` instruction (requires f & lsx). + pub inline fn @"vsetallnez.h"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cb400, p0, p1); + } + + /// Encodes a `vsetallnez.w` instruction (requires f & lsx). + pub inline fn @"vsetallnez.w"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cb800, p0, p1); + } + + /// Encodes a `vsetanyeqz.b` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.b"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729ca000, p0, p1); + } + + /// Encodes a `vsetanyeqz.d` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.d"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729cac00, p0, p1); + } + + /// Encodes a `vsetanyeqz.h` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.h"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729ca400, p0, p1); + } + + /// Encodes a `vsetanyeqz.w` instruction (requires f & lsx). + pub inline fn @"vsetanyeqz.w"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729ca800, p0, p1); + } + + /// Encodes a `vseteqz.v` instruction (requires f & lsx). + pub inline fn @"vseteqz.v"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729c9800, p0, p1); + } + + /// Encodes a `vsetnez.v` instruction (requires f & lsx). + pub inline fn @"vsetnez.v"(p0: Register, p1: Register) Instruction { + return encodeCdVj(0x729c9c00, p0, p1); + } + + /// Encodes a `vshuf.b` instruction (requires lsx). + pub inline fn @"vshuf.b"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeVdVjVkVa(0x0d500000, p0, p1, p2, p3); + } + + /// Encodes a `vshuf.d` instruction (requires lsx). + pub inline fn @"vshuf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x717b8000, p0, p1, p2); + } + + /// Encodes a `vshuf.h` instruction (requires lsx). + pub inline fn @"vshuf.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x717a8000, p0, p1, p2); + } + + /// Encodes a `vshuf.w` instruction (requires lsx). + pub inline fn @"vshuf.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x717b0000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.b` instruction (requires lsx). + pub inline fn @"vshuf4i.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73900000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.d` instruction (requires lsx). + pub inline fn @"vshuf4i.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x739c0000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.h` instruction (requires lsx). + pub inline fn @"vshuf4i.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73940000, p0, p1, p2); + } + + /// Encodes a `vshuf4i.w` instruction (requires lsx). + pub inline fn @"vshuf4i.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73980000, p0, p1, p2); + } + + /// Encodes a `vsigncov.b` instruction (requires lsx). + pub inline fn @"vsigncov.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712e0000, p0, p1, p2); + } + + /// Encodes a `vsigncov.d` instruction (requires lsx). + pub inline fn @"vsigncov.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712f8000, p0, p1, p2); + } + + /// Encodes a `vsigncov.h` instruction (requires lsx). + pub inline fn @"vsigncov.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712e8000, p0, p1, p2); + } + + /// Encodes a `vsigncov.w` instruction (requires lsx). + pub inline fn @"vsigncov.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712f0000, p0, p1, p2); + } + + /// Encodes a `vsle.b` instruction (requires lsx). + pub inline fn @"vsle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70020000, p0, p1, p2); + } + + /// Encodes a `vsle.bu` instruction (requires lsx). + pub inline fn @"vsle.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70040000, p0, p1, p2); + } + + /// Encodes a `vsle.d` instruction (requires lsx). + pub inline fn @"vsle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70038000, p0, p1, p2); + } + + /// Encodes a `vsle.du` instruction (requires lsx). + pub inline fn @"vsle.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70058000, p0, p1, p2); + } + + /// Encodes a `vsle.h` instruction (requires lsx). + pub inline fn @"vsle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70028000, p0, p1, p2); + } + + /// Encodes a `vsle.hu` instruction (requires lsx). + pub inline fn @"vsle.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70048000, p0, p1, p2); + } + + /// Encodes a `vsle.w` instruction (requires lsx). + pub inline fn @"vsle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70030000, p0, p1, p2); + } + + /// Encodes a `vsle.wu` instruction (requires lsx). + pub inline fn @"vsle.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70050000, p0, p1, p2); + } + + /// Encodes a `vslei.b` instruction (requires lsx). + pub inline fn @"vslei.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72820000, p0, p1, p2); + } + + /// Encodes a `vslei.bu` instruction (requires lsx). + pub inline fn @"vslei.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72840000, p0, p1, p2); + } + + /// Encodes a `vslei.d` instruction (requires lsx). + pub inline fn @"vslei.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72838000, p0, p1, p2); + } + + /// Encodes a `vslei.du` instruction (requires lsx). + pub inline fn @"vslei.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72858000, p0, p1, p2); + } + + /// Encodes a `vslei.h` instruction (requires lsx). + pub inline fn @"vslei.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72828000, p0, p1, p2); + } + + /// Encodes a `vslei.hu` instruction (requires lsx). + pub inline fn @"vslei.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72848000, p0, p1, p2); + } + + /// Encodes a `vslei.w` instruction (requires lsx). + pub inline fn @"vslei.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72830000, p0, p1, p2); + } + + /// Encodes a `vslei.wu` instruction (requires lsx). + pub inline fn @"vslei.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72850000, p0, p1, p2); + } + + /// Encodes a `vsll.b` instruction (requires lsx). + pub inline fn @"vsll.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e80000, p0, p1, p2); + } + + /// Encodes a `vsll.d` instruction (requires lsx). + pub inline fn @"vsll.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e98000, p0, p1, p2); + } + + /// Encodes a `vsll.h` instruction (requires lsx). + pub inline fn @"vsll.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e88000, p0, p1, p2); + } + + /// Encodes a `vsll.w` instruction (requires lsx). + pub inline fn @"vsll.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70e90000, p0, p1, p2); + } + + /// Encodes a `vslli.b` instruction (requires lsx). + pub inline fn @"vslli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x732c2000, p0, p1, p2); + } + + /// Encodes a `vslli.d` instruction (requires lsx). + pub inline fn @"vslli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x732d0000, p0, p1, p2); + } + + /// Encodes a `vslli.h` instruction (requires lsx). + pub inline fn @"vslli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x732c4000, p0, p1, p2); + } + + /// Encodes a `vslli.w` instruction (requires lsx). + pub inline fn @"vslli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x732c8000, p0, p1, p2); + } + + /// Encodes a `vsllwil.d.w` instruction (requires lsx). + pub inline fn @"vsllwil.d.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73088000, p0, p1, p2); + } + + /// Encodes a `vsllwil.du.wu` instruction (requires lsx). + pub inline fn @"vsllwil.du.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x730c8000, p0, p1, p2); + } + + /// Encodes a `vsllwil.h.b` instruction (requires lsx). + pub inline fn @"vsllwil.h.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73082000, p0, p1, p2); + } + + /// Encodes a `vsllwil.hu.bu` instruction (requires lsx). + pub inline fn @"vsllwil.hu.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x730c2000, p0, p1, p2); + } + + /// Encodes a `vsllwil.w.h` instruction (requires lsx). + pub inline fn @"vsllwil.w.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73084000, p0, p1, p2); + } + + /// Encodes a `vsllwil.wu.hu` instruction (requires lsx). + pub inline fn @"vsllwil.wu.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x730c4000, p0, p1, p2); + } + + /// Encodes a `vslt.b` instruction (requires lsx). + pub inline fn @"vslt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70060000, p0, p1, p2); + } + + /// Encodes a `vslt.bu` instruction (requires lsx). + pub inline fn @"vslt.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70080000, p0, p1, p2); + } + + /// Encodes a `vslt.d` instruction (requires lsx). + pub inline fn @"vslt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70078000, p0, p1, p2); + } + + /// Encodes a `vslt.du` instruction (requires lsx). + pub inline fn @"vslt.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70098000, p0, p1, p2); + } + + /// Encodes a `vslt.h` instruction (requires lsx). + pub inline fn @"vslt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70068000, p0, p1, p2); + } + + /// Encodes a `vslt.hu` instruction (requires lsx). + pub inline fn @"vslt.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70088000, p0, p1, p2); + } + + /// Encodes a `vslt.w` instruction (requires lsx). + pub inline fn @"vslt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70070000, p0, p1, p2); + } + + /// Encodes a `vslt.wu` instruction (requires lsx). + pub inline fn @"vslt.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70090000, p0, p1, p2); + } + + /// Encodes a `vslti.b` instruction (requires lsx). + pub inline fn @"vslti.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72860000, p0, p1, p2); + } + + /// Encodes a `vslti.bu` instruction (requires lsx). + pub inline fn @"vslti.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72880000, p0, p1, p2); + } + + /// Encodes a `vslti.d` instruction (requires lsx). + pub inline fn @"vslti.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72878000, p0, p1, p2); + } + + /// Encodes a `vslti.du` instruction (requires lsx). + pub inline fn @"vslti.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72898000, p0, p1, p2); + } + + /// Encodes a `vslti.h` instruction (requires lsx). + pub inline fn @"vslti.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72868000, p0, p1, p2); + } + + /// Encodes a `vslti.hu` instruction (requires lsx). + pub inline fn @"vslti.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72888000, p0, p1, p2); + } + + /// Encodes a `vslti.w` instruction (requires lsx). + pub inline fn @"vslti.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeVdVjSk5(0x72870000, p0, p1, p2); + } + + /// Encodes a `vslti.wu` instruction (requires lsx). + pub inline fn @"vslti.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72890000, p0, p1, p2); + } + + /// Encodes a `vsra.b` instruction (requires lsx). + pub inline fn @"vsra.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ec0000, p0, p1, p2); + } + + /// Encodes a `vsra.d` instruction (requires lsx). + pub inline fn @"vsra.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ed8000, p0, p1, p2); + } + + /// Encodes a `vsra.h` instruction (requires lsx). + pub inline fn @"vsra.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ec8000, p0, p1, p2); + } + + /// Encodes a `vsra.w` instruction (requires lsx). + pub inline fn @"vsra.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ed0000, p0, p1, p2); + } + + /// Encodes a `vsrai.b` instruction (requires lsx). + pub inline fn @"vsrai.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73342000, p0, p1, p2); + } + + /// Encodes a `vsrai.d` instruction (requires lsx). + pub inline fn @"vsrai.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73350000, p0, p1, p2); + } + + /// Encodes a `vsrai.h` instruction (requires lsx). + pub inline fn @"vsrai.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73344000, p0, p1, p2); + } + + /// Encodes a `vsrai.w` instruction (requires lsx). + pub inline fn @"vsrai.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73348000, p0, p1, p2); + } + + /// Encodes a `vsran.b.h` instruction (requires lsx). + pub inline fn @"vsran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f68000, p0, p1, p2); + } + + /// Encodes a `vsran.h.w` instruction (requires lsx). + pub inline fn @"vsran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f70000, p0, p1, p2); + } + + /// Encodes a `vsran.w.d` instruction (requires lsx). + pub inline fn @"vsran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f78000, p0, p1, p2); + } + + /// Encodes a `vsrani.b.h` instruction (requires lsx). + pub inline fn @"vsrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73584000, p0, p1, p2); + } + + /// Encodes a `vsrani.d.q` instruction (requires lsx). + pub inline fn @"vsrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x735a0000, p0, p1, p2); + } + + /// Encodes a `vsrani.h.w` instruction (requires lsx). + pub inline fn @"vsrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73588000, p0, p1, p2); + } + + /// Encodes a `vsrani.w.d` instruction (requires lsx). + pub inline fn @"vsrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73590000, p0, p1, p2); + } + + /// Encodes a `vsrar.b` instruction (requires lsx). + pub inline fn @"vsrar.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f20000, p0, p1, p2); + } + + /// Encodes a `vsrar.d` instruction (requires lsx). + pub inline fn @"vsrar.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f38000, p0, p1, p2); + } + + /// Encodes a `vsrar.h` instruction (requires lsx). + pub inline fn @"vsrar.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f28000, p0, p1, p2); + } + + /// Encodes a `vsrar.w` instruction (requires lsx). + pub inline fn @"vsrar.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f30000, p0, p1, p2); + } + + /// Encodes a `vsrari.b` instruction (requires lsx). + pub inline fn @"vsrari.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72a82000, p0, p1, p2); + } + + /// Encodes a `vsrari.d` instruction (requires lsx). + pub inline fn @"vsrari.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x72a90000, p0, p1, p2); + } + + /// Encodes a `vsrari.h` instruction (requires lsx). + pub inline fn @"vsrari.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72a84000, p0, p1, p2); + } + + /// Encodes a `vsrari.w` instruction (requires lsx). + pub inline fn @"vsrari.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72a88000, p0, p1, p2); + } + + /// Encodes a `vsrarn.b.h` instruction (requires lsx). + pub inline fn @"vsrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fa8000, p0, p1, p2); + } + + /// Encodes a `vsrarn.h.w` instruction (requires lsx). + pub inline fn @"vsrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fb0000, p0, p1, p2); + } + + /// Encodes a `vsrarn.w.d` instruction (requires lsx). + pub inline fn @"vsrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fb8000, p0, p1, p2); + } + + /// Encodes a `vsrarni.b.h` instruction (requires lsx). + pub inline fn @"vsrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x735c4000, p0, p1, p2); + } + + /// Encodes a `vsrarni.d.q` instruction (requires lsx). + pub inline fn @"vsrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x735e0000, p0, p1, p2); + } + + /// Encodes a `vsrarni.h.w` instruction (requires lsx). + pub inline fn @"vsrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x735c8000, p0, p1, p2); + } + + /// Encodes a `vsrarni.w.d` instruction (requires lsx). + pub inline fn @"vsrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x735d0000, p0, p1, p2); + } + + /// Encodes a `vsrl.b` instruction (requires lsx). + pub inline fn @"vsrl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ea0000, p0, p1, p2); + } + + /// Encodes a `vsrl.d` instruction (requires lsx). + pub inline fn @"vsrl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70eb8000, p0, p1, p2); + } + + /// Encodes a `vsrl.h` instruction (requires lsx). + pub inline fn @"vsrl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ea8000, p0, p1, p2); + } + + /// Encodes a `vsrl.w` instruction (requires lsx). + pub inline fn @"vsrl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70eb0000, p0, p1, p2); + } + + /// Encodes a `vsrli.b` instruction (requires lsx). + pub inline fn @"vsrli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x73302000, p0, p1, p2); + } + + /// Encodes a `vsrli.d` instruction (requires lsx). + pub inline fn @"vsrli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73310000, p0, p1, p2); + } + + /// Encodes a `vsrli.h` instruction (requires lsx). + pub inline fn @"vsrli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73304000, p0, p1, p2); + } + + /// Encodes a `vsrli.w` instruction (requires lsx). + pub inline fn @"vsrli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73308000, p0, p1, p2); + } + + /// Encodes a `vsrln.b.h` instruction (requires lsx). + pub inline fn @"vsrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f48000, p0, p1, p2); + } + + /// Encodes a `vsrln.h.w` instruction (requires lsx). + pub inline fn @"vsrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f50000, p0, p1, p2); + } + + /// Encodes a `vsrln.w.d` instruction (requires lsx). + pub inline fn @"vsrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f58000, p0, p1, p2); + } + + /// Encodes a `vsrlni.b.h` instruction (requires lsx). + pub inline fn @"vsrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73404000, p0, p1, p2); + } + + /// Encodes a `vsrlni.d.q` instruction (requires lsx). + pub inline fn @"vsrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73420000, p0, p1, p2); + } + + /// Encodes a `vsrlni.h.w` instruction (requires lsx). + pub inline fn @"vsrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73408000, p0, p1, p2); + } + + /// Encodes a `vsrlni.w.d` instruction (requires lsx). + pub inline fn @"vsrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73410000, p0, p1, p2); + } + + /// Encodes a `vsrlr.b` instruction (requires lsx). + pub inline fn @"vsrlr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f00000, p0, p1, p2); + } + + /// Encodes a `vsrlr.d` instruction (requires lsx). + pub inline fn @"vsrlr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f18000, p0, p1, p2); + } + + /// Encodes a `vsrlr.h` instruction (requires lsx). + pub inline fn @"vsrlr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f08000, p0, p1, p2); + } + + /// Encodes a `vsrlr.w` instruction (requires lsx). + pub inline fn @"vsrlr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f10000, p0, p1, p2); + } + + /// Encodes a `vsrlri.b` instruction (requires lsx). + pub inline fn @"vsrlri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeVdVjUk3(0x72a42000, p0, p1, p2); + } + + /// Encodes a `vsrlri.d` instruction (requires lsx). + pub inline fn @"vsrlri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x72a50000, p0, p1, p2); + } + + /// Encodes a `vsrlri.h` instruction (requires lsx). + pub inline fn @"vsrlri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x72a44000, p0, p1, p2); + } + + /// Encodes a `vsrlri.w` instruction (requires lsx). + pub inline fn @"vsrlri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x72a48000, p0, p1, p2); + } + + /// Encodes a `vsrlrn.b.h` instruction (requires lsx). + pub inline fn @"vsrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f88000, p0, p1, p2); + } + + /// Encodes a `vsrlrn.h.w` instruction (requires lsx). + pub inline fn @"vsrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f90000, p0, p1, p2); + } + + /// Encodes a `vsrlrn.w.d` instruction (requires lsx). + pub inline fn @"vsrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70f98000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.b.h` instruction (requires lsx). + pub inline fn @"vsrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73444000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.d.q` instruction (requires lsx). + pub inline fn @"vsrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73460000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.h.w` instruction (requires lsx). + pub inline fn @"vsrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73448000, p0, p1, p2); + } + + /// Encodes a `vsrlrni.w.d` instruction (requires lsx). + pub inline fn @"vsrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73450000, p0, p1, p2); + } + + /// Encodes a `vssran.b.h` instruction (requires lsx). + pub inline fn @"vssran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fe8000, p0, p1, p2); + } + + /// Encodes a `vssran.bu.h` instruction (requires lsx). + pub inline fn @"vssran.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71068000, p0, p1, p2); + } + + /// Encodes a `vssran.h.w` instruction (requires lsx). + pub inline fn @"vssran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ff0000, p0, p1, p2); + } + + /// Encodes a `vssran.hu.w` instruction (requires lsx). + pub inline fn @"vssran.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71070000, p0, p1, p2); + } + + /// Encodes a `vssran.w.d` instruction (requires lsx). + pub inline fn @"vssran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70ff8000, p0, p1, p2); + } + + /// Encodes a `vssran.wu.d` instruction (requires lsx). + pub inline fn @"vssran.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71078000, p0, p1, p2); + } + + /// Encodes a `vssrani.b.h` instruction (requires lsx). + pub inline fn @"vssrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73604000, p0, p1, p2); + } + + /// Encodes a `vssrani.bu.h` instruction (requires lsx). + pub inline fn @"vssrani.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73644000, p0, p1, p2); + } + + /// Encodes a `vssrani.d.q` instruction (requires lsx). + pub inline fn @"vssrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73620000, p0, p1, p2); + } + + /// Encodes a `vssrani.du.q` instruction (requires lsx). + pub inline fn @"vssrani.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73660000, p0, p1, p2); + } + + /// Encodes a `vssrani.h.w` instruction (requires lsx). + pub inline fn @"vssrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73608000, p0, p1, p2); + } + + /// Encodes a `vssrani.hu.w` instruction (requires lsx). + pub inline fn @"vssrani.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73648000, p0, p1, p2); + } + + /// Encodes a `vssrani.w.d` instruction (requires lsx). + pub inline fn @"vssrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73610000, p0, p1, p2); + } + + /// Encodes a `vssrani.wu.d` instruction (requires lsx). + pub inline fn @"vssrani.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73650000, p0, p1, p2); + } + + /// Encodes a `vssrarn.b.h` instruction (requires lsx). + pub inline fn @"vssrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71028000, p0, p1, p2); + } + + /// Encodes a `vssrarn.bu.h` instruction (requires lsx). + pub inline fn @"vssrarn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710a8000, p0, p1, p2); + } + + /// Encodes a `vssrarn.h.w` instruction (requires lsx). + pub inline fn @"vssrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71030000, p0, p1, p2); + } + + /// Encodes a `vssrarn.hu.w` instruction (requires lsx). + pub inline fn @"vssrarn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710b0000, p0, p1, p2); + } + + /// Encodes a `vssrarn.w.d` instruction (requires lsx). + pub inline fn @"vssrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71038000, p0, p1, p2); + } + + /// Encodes a `vssrarn.wu.d` instruction (requires lsx). + pub inline fn @"vssrarn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x710b8000, p0, p1, p2); + } + + /// Encodes a `vssrarni.b.h` instruction (requires lsx). + pub inline fn @"vssrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73684000, p0, p1, p2); + } + + /// Encodes a `vssrarni.bu.h` instruction (requires lsx). + pub inline fn @"vssrarni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x736c4000, p0, p1, p2); + } + + /// Encodes a `vssrarni.d.q` instruction (requires lsx). + pub inline fn @"vssrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x736a0000, p0, p1, p2); + } + + /// Encodes a `vssrarni.du.q` instruction (requires lsx). + pub inline fn @"vssrarni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x736e0000, p0, p1, p2); + } + + /// Encodes a `vssrarni.h.w` instruction (requires lsx). + pub inline fn @"vssrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73688000, p0, p1, p2); + } + + /// Encodes a `vssrarni.hu.w` instruction (requires lsx). + pub inline fn @"vssrarni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x736c8000, p0, p1, p2); + } + + /// Encodes a `vssrarni.w.d` instruction (requires lsx). + pub inline fn @"vssrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73690000, p0, p1, p2); + } + + /// Encodes a `vssrarni.wu.d` instruction (requires lsx). + pub inline fn @"vssrarni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x736d0000, p0, p1, p2); + } + + /// Encodes a `vssrln.b.h` instruction (requires lsx). + pub inline fn @"vssrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fc8000, p0, p1, p2); + } + + /// Encodes a `vssrln.bu.h` instruction (requires lsx). + pub inline fn @"vssrln.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71048000, p0, p1, p2); + } + + /// Encodes a `vssrln.h.w` instruction (requires lsx). + pub inline fn @"vssrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fd0000, p0, p1, p2); + } + + /// Encodes a `vssrln.hu.w` instruction (requires lsx). + pub inline fn @"vssrln.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71050000, p0, p1, p2); + } + + /// Encodes a `vssrln.w.d` instruction (requires lsx). + pub inline fn @"vssrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70fd8000, p0, p1, p2); + } + + /// Encodes a `vssrln.wu.d` instruction (requires lsx). + pub inline fn @"vssrln.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71058000, p0, p1, p2); + } + + /// Encodes a `vssrlni.b.h` instruction (requires lsx). + pub inline fn @"vssrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73484000, p0, p1, p2); + } + + /// Encodes a `vssrlni.bu.h` instruction (requires lsx). + pub inline fn @"vssrlni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x734c4000, p0, p1, p2); + } + + /// Encodes a `vssrlni.d.q` instruction (requires lsx). + pub inline fn @"vssrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x734a0000, p0, p1, p2); + } + + /// Encodes a `vssrlni.du.q` instruction (requires lsx). + pub inline fn @"vssrlni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x734e0000, p0, p1, p2); + } + + /// Encodes a `vssrlni.h.w` instruction (requires lsx). + pub inline fn @"vssrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73488000, p0, p1, p2); + } + + /// Encodes a `vssrlni.hu.w` instruction (requires lsx). + pub inline fn @"vssrlni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x734c8000, p0, p1, p2); + } + + /// Encodes a `vssrlni.w.d` instruction (requires lsx). + pub inline fn @"vssrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73490000, p0, p1, p2); + } + + /// Encodes a `vssrlni.wu.d` instruction (requires lsx). + pub inline fn @"vssrlni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x734d0000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.b.h` instruction (requires lsx). + pub inline fn @"vssrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71008000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.bu.h` instruction (requires lsx). + pub inline fn @"vssrlrn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71088000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.h.w` instruction (requires lsx). + pub inline fn @"vssrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71010000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.hu.w` instruction (requires lsx). + pub inline fn @"vssrlrn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71090000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.w.d` instruction (requires lsx). + pub inline fn @"vssrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71018000, p0, p1, p2); + } + + /// Encodes a `vssrlrn.wu.d` instruction (requires lsx). + pub inline fn @"vssrlrn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71098000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.b.h` instruction (requires lsx). + pub inline fn @"vssrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73504000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.bu.h` instruction (requires lsx). + pub inline fn @"vssrlrni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeVdVjUk4(0x73544000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.d.q` instruction (requires lsx). + pub inline fn @"vssrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73520000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.du.q` instruction (requires lsx). + pub inline fn @"vssrlrni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeVdVjUk7(0x73560000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.h.w` instruction (requires lsx). + pub inline fn @"vssrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73508000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.hu.w` instruction (requires lsx). + pub inline fn @"vssrlrni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x73548000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.w.d` instruction (requires lsx). + pub inline fn @"vssrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73510000, p0, p1, p2); + } + + /// Encodes a `vssrlrni.wu.d` instruction (requires lsx). + pub inline fn @"vssrlrni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeVdVjUk6(0x73550000, p0, p1, p2); + } + + /// Encodes a `vssub.b` instruction (requires lsx). + pub inline fn @"vssub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70480000, p0, p1, p2); + } + + /// Encodes a `vssub.bu` instruction (requires lsx). + pub inline fn @"vssub.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704c0000, p0, p1, p2); + } + + /// Encodes a `vssub.d` instruction (requires lsx). + pub inline fn @"vssub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70498000, p0, p1, p2); + } + + /// Encodes a `vssub.du` instruction (requires lsx). + pub inline fn @"vssub.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704d8000, p0, p1, p2); + } + + /// Encodes a `vssub.h` instruction (requires lsx). + pub inline fn @"vssub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70488000, p0, p1, p2); + } + + /// Encodes a `vssub.hu` instruction (requires lsx). + pub inline fn @"vssub.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704c8000, p0, p1, p2); + } + + /// Encodes a `vssub.w` instruction (requires lsx). + pub inline fn @"vssub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70490000, p0, p1, p2); + } + + /// Encodes a `vssub.wu` instruction (requires lsx). + pub inline fn @"vssub.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x704d0000, p0, p1, p2); + } + + /// Encodes a `vst` instruction (requires lsx). + pub inline fn vst(p0: Register, p1: Register, p2: i12) Instruction { + return encodeVdJSk12(0x2c400000, p0, p1, p2); + } + + /// Encodes a `vstelm.b` instruction (requires lsx). + pub inline fn @"vstelm.b"(p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return encodeVdJSk8Un4(0x31800000, p0, p1, p2, p3); + } + + /// Encodes a `vstelm.d` instruction (requires lsx). + pub inline fn @"vstelm.d"(p0: Register, p1: Register, p2: i8, p3: u1) Instruction { + return encodeVdJSk8ps3Un1(0x31100000, p0, p1, p2, p3); + } + + /// Encodes a `vstelm.h` instruction (requires lsx). + pub inline fn @"vstelm.h"(p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return encodeVdJSk8ps1Un3(0x31400000, p0, p1, p2, p3); + } + + /// Encodes a `vstelm.w` instruction (requires lsx). + pub inline fn @"vstelm.w"(p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return encodeVdJSk8ps2Un2(0x31200000, p0, p1, p2, p3); + } + + /// Encodes a `vstx` instruction (requires lsx). + pub inline fn vstx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdJK(0x38440000, p0, p1, p2); + } + + /// Encodes a `vsub.b` instruction (requires lsx). + pub inline fn @"vsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700c0000, p0, p1, p2); + } + + /// Encodes a `vsub.d` instruction (requires lsx). + pub inline fn @"vsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700d8000, p0, p1, p2); + } + + /// Encodes a `vsub.h` instruction (requires lsx). + pub inline fn @"vsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700c8000, p0, p1, p2); + } + + /// Encodes a `vsub.q` instruction (requires lsx). + pub inline fn @"vsub.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x712d8000, p0, p1, p2); + } + + /// Encodes a `vsub.w` instruction (requires lsx). + pub inline fn @"vsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x700d0000, p0, p1, p2); + } + + /// Encodes a `vsubi.bu` instruction (requires lsx). + pub inline fn @"vsubi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728c0000, p0, p1, p2); + } + + /// Encodes a `vsubi.du` instruction (requires lsx). + pub inline fn @"vsubi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728d8000, p0, p1, p2); + } + + /// Encodes a `vsubi.hu` instruction (requires lsx). + pub inline fn @"vsubi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728c8000, p0, p1, p2); + } + + /// Encodes a `vsubi.wu` instruction (requires lsx). + pub inline fn @"vsubi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeVdVjUk5(0x728d0000, p0, p1, p2); + } + + /// Encodes a `vsubwev.d.w` instruction (requires lsx). + pub inline fn @"vsubwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70210000, p0, p1, p2); + } + + /// Encodes a `vsubwev.d.wu` instruction (requires lsx). + pub inline fn @"vsubwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70310000, p0, p1, p2); + } + + /// Encodes a `vsubwev.h.b` instruction (requires lsx). + pub inline fn @"vsubwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70200000, p0, p1, p2); + } + + /// Encodes a `vsubwev.h.bu` instruction (requires lsx). + pub inline fn @"vsubwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70300000, p0, p1, p2); + } + + /// Encodes a `vsubwev.q.d` instruction (requires lsx). + pub inline fn @"vsubwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70218000, p0, p1, p2); + } + + /// Encodes a `vsubwev.q.du` instruction (requires lsx). + pub inline fn @"vsubwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70318000, p0, p1, p2); + } + + /// Encodes a `vsubwev.w.h` instruction (requires lsx). + pub inline fn @"vsubwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70208000, p0, p1, p2); + } + + /// Encodes a `vsubwev.w.hu` instruction (requires lsx). + pub inline fn @"vsubwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70308000, p0, p1, p2); + } + + /// Encodes a `vsubwod.d.w` instruction (requires lsx). + pub inline fn @"vsubwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70250000, p0, p1, p2); + } + + /// Encodes a `vsubwod.d.wu` instruction (requires lsx). + pub inline fn @"vsubwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70350000, p0, p1, p2); + } + + /// Encodes a `vsubwod.h.b` instruction (requires lsx). + pub inline fn @"vsubwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70240000, p0, p1, p2); + } + + /// Encodes a `vsubwod.h.bu` instruction (requires lsx). + pub inline fn @"vsubwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70340000, p0, p1, p2); + } + + /// Encodes a `vsubwod.q.d` instruction (requires lsx). + pub inline fn @"vsubwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70258000, p0, p1, p2); + } + + /// Encodes a `vsubwod.q.du` instruction (requires lsx). + pub inline fn @"vsubwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70358000, p0, p1, p2); + } + + /// Encodes a `vsubwod.w.h` instruction (requires lsx). + pub inline fn @"vsubwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70248000, p0, p1, p2); + } + + /// Encodes a `vsubwod.w.hu` instruction (requires lsx). + pub inline fn @"vsubwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x70348000, p0, p1, p2); + } + + /// Encodes a `vxor.v` instruction (requires lsx). + pub inline fn @"vxor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeVdVjVk(0x71270000, p0, p1, p2); + } + + /// Encodes a `vxori.b` instruction (requires lsx). + pub inline fn @"vxori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeVdVjUk8(0x73d80000, p0, p1, p2); + } + + /// Encodes a `x86adc.b` instruction (requires 64bit). + pub inline fn @"x86adc.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000c, p0, p1); + } + + /// Encodes a `x86adc.d` instruction (requires 64bit). + pub inline fn @"x86adc.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000f, p0, p1); + } + + /// Encodes a `x86adc.h` instruction (requires 64bit). + pub inline fn @"x86adc.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000d, p0, p1); + } + + /// Encodes a `x86adc.w` instruction (requires 64bit). + pub inline fn @"x86adc.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000e, p0, p1); + } + + /// Encodes a `x86add.b` instruction (requires 64bit). + pub inline fn @"x86add.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0004, p0, p1); + } + + /// Encodes a `x86add.d` instruction (requires 64bit). + pub inline fn @"x86add.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0007, p0, p1); + } + + /// Encodes a `x86add.du` instruction (requires 64bit). + pub inline fn @"x86add.du"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0001, p0, p1); + } + + /// Encodes a `x86add.h` instruction (requires 64bit). + pub inline fn @"x86add.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0005, p0, p1); + } + + /// Encodes a `x86add.w` instruction (requires 64bit). + pub inline fn @"x86add.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0006, p0, p1); + } + + /// Encodes a `x86add.wu` instruction (requires 64bit). + pub inline fn @"x86add.wu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0000, p0, p1); + } + + /// Encodes a `x86and.b` instruction (requires 64bit). + pub inline fn @"x86and.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8010, p0, p1); + } + + /// Encodes a `x86and.d` instruction (requires 64bit). + pub inline fn @"x86and.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8013, p0, p1); + } + + /// Encodes a `x86and.h` instruction (requires 64bit). + pub inline fn @"x86and.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8011, p0, p1); + } + + /// Encodes a `x86and.w` instruction (requires 64bit). + pub inline fn @"x86and.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8012, p0, p1); + } + + /// Encodes a `x86clrtm` instruction (requires 64bit). + pub inline fn x86clrtm() Instruction { + return encodeEMPTY(0x00008028); + } + + /// Encodes a `x86dec.b` instruction (requires 64bit). + pub inline fn @"x86dec.b"(p0: Register) Instruction { + return encodeJ(0x00008004, p0); + } + + /// Encodes a `x86dec.d` instruction (requires 64bit). + pub inline fn @"x86dec.d"(p0: Register) Instruction { + return encodeJ(0x00008007, p0); + } + + /// Encodes a `x86dec.h` instruction (requires 64bit). + pub inline fn @"x86dec.h"(p0: Register) Instruction { + return encodeJ(0x00008005, p0); + } + + /// Encodes a `x86dec.w` instruction (requires 64bit). + pub inline fn @"x86dec.w"(p0: Register) Instruction { + return encodeJ(0x00008006, p0); + } + + /// Encodes a `x86dectop` instruction (requires 64bit). + pub inline fn x86dectop() Instruction { + return encodeEMPTY(0x00008029); + } + + /// Encodes a `x86inc.b` instruction (requires 64bit). + pub inline fn @"x86inc.b"(p0: Register) Instruction { + return encodeJ(0x00008000, p0); + } + + /// Encodes a `x86inc.d` instruction (requires 64bit). + pub inline fn @"x86inc.d"(p0: Register) Instruction { + return encodeJ(0x00008003, p0); + } + + /// Encodes a `x86inc.h` instruction (requires 64bit). + pub inline fn @"x86inc.h"(p0: Register) Instruction { + return encodeJ(0x00008001, p0); + } + + /// Encodes a `x86inc.w` instruction (requires 64bit). + pub inline fn @"x86inc.w"(p0: Register) Instruction { + return encodeJ(0x00008002, p0); + } + + /// Encodes a `x86inctop` instruction (requires 64bit). + pub inline fn x86inctop() Instruction { + return encodeEMPTY(0x00008009); + } + + /// Encodes a `x86mfflag` instruction (requires 64bit). + pub inline fn x86mfflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0000, p0, p1); + } + + /// Encodes a `x86mftop` instruction (requires 64bit). + pub inline fn x86mftop(p0: Register) Instruction { + return encodeD(0x00007400, p0); + } + + /// Encodes a `x86mtflag` instruction (requires 64bit). + pub inline fn x86mtflag(p0: Register, p1: u8) Instruction { + return encodeDUk8(0x005c0020, p0, p1); + } + + /// Encodes a `x86mttop` instruction (requires 64bit). + pub inline fn x86mttop(p0: u3) Instruction { + return encodeUj3(0x00007000, p0); + } + + /// Encodes a `x86mul.b` instruction (requires 64bit). + pub inline fn @"x86mul.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8000, p0, p1); + } + + /// Encodes a `x86mul.bu` instruction (requires 64bit). + pub inline fn @"x86mul.bu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8004, p0, p1); + } + + /// Encodes a `x86mul.d` instruction (requires 64bit). + pub inline fn @"x86mul.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8003, p0, p1); + } + + /// Encodes a `x86mul.du` instruction (requires 64bit). + pub inline fn @"x86mul.du"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8007, p0, p1); + } + + /// Encodes a `x86mul.h` instruction (requires 64bit). + pub inline fn @"x86mul.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8001, p0, p1); + } + + /// Encodes a `x86mul.hu` instruction (requires 64bit). + pub inline fn @"x86mul.hu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8005, p0, p1); + } + + /// Encodes a `x86mul.w` instruction (requires 64bit). + pub inline fn @"x86mul.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8002, p0, p1); + } + + /// Encodes a `x86mul.wu` instruction (requires 64bit). + pub inline fn @"x86mul.wu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003e8006, p0, p1); + } + + /// Encodes a `x86or.b` instruction (requires 64bit). + pub inline fn @"x86or.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8014, p0, p1); + } + + /// Encodes a `x86or.d` instruction (requires 64bit). + pub inline fn @"x86or.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8017, p0, p1); + } + + /// Encodes a `x86or.h` instruction (requires 64bit). + pub inline fn @"x86or.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8015, p0, p1); + } + + /// Encodes a `x86or.w` instruction (requires 64bit). + pub inline fn @"x86or.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8016, p0, p1); + } + + /// Encodes a `x86rcl.b` instruction (requires 64bit). + pub inline fn @"x86rcl.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800c, p0, p1); + } + + /// Encodes a `x86rcl.d` instruction (requires 64bit). + pub inline fn @"x86rcl.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800f, p0, p1); + } + + /// Encodes a `x86rcl.h` instruction (requires 64bit). + pub inline fn @"x86rcl.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800d, p0, p1); + } + + /// Encodes a `x86rcl.w` instruction (requires 64bit). + pub inline fn @"x86rcl.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800e, p0, p1); + } + + /// Encodes a `x86rcli.b` instruction (requires 64bit). + pub inline fn @"x86rcli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542018, p0, p1); + } + + /// Encodes a `x86rcli.d` instruction (requires 64bit). + pub inline fn @"x86rcli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x0055001b, p0, p1); + } + + /// Encodes a `x86rcli.h` instruction (requires 64bit). + pub inline fn @"x86rcli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544019, p0, p1); + } + + /// Encodes a `x86rcli.w` instruction (requires 64bit). + pub inline fn @"x86rcli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x0054801a, p0, p1); + } + + /// Encodes a `x86rcr.b` instruction (requires 64bit). + pub inline fn @"x86rcr.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8008, p0, p1); + } + + /// Encodes a `x86rcr.d` instruction (requires 64bit). + pub inline fn @"x86rcr.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800b, p0, p1); + } + + /// Encodes a `x86rcr.h` instruction (requires 64bit). + pub inline fn @"x86rcr.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8009, p0, p1); + } + + /// Encodes a `x86rcr.w` instruction (requires 64bit). + pub inline fn @"x86rcr.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f800a, p0, p1); + } + + /// Encodes a `x86rcri.b` instruction (requires 64bit). + pub inline fn @"x86rcri.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542010, p0, p1); + } + + /// Encodes a `x86rcri.d` instruction (requires 64bit). + pub inline fn @"x86rcri.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550013, p0, p1); + } + + /// Encodes a `x86rcri.h` instruction (requires 64bit). + pub inline fn @"x86rcri.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544011, p0, p1); + } + + /// Encodes a `x86rcri.w` instruction (requires 64bit). + pub inline fn @"x86rcri.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548012, p0, p1); + } + + /// Encodes a `x86rotl.b` instruction (requires 64bit). + pub inline fn @"x86rotl.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8004, p0, p1); + } + + /// Encodes a `x86rotl.d` instruction (requires 64bit). + pub inline fn @"x86rotl.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8007, p0, p1); + } + + /// Encodes a `x86rotl.h` instruction (requires 64bit). + pub inline fn @"x86rotl.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8005, p0, p1); + } + + /// Encodes a `x86rotl.w` instruction (requires 64bit). + pub inline fn @"x86rotl.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8006, p0, p1); + } + + /// Encodes a `x86rotli.b` instruction (requires 64bit). + pub inline fn @"x86rotli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542014, p0, p1); + } + + /// Encodes a `x86rotli.d` instruction (requires 64bit). + pub inline fn @"x86rotli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550017, p0, p1); + } + + /// Encodes a `x86rotli.h` instruction (requires 64bit). + pub inline fn @"x86rotli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544015, p0, p1); + } + + /// Encodes a `x86rotli.w` instruction (requires 64bit). + pub inline fn @"x86rotli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548016, p0, p1); + } + + /// Encodes a `x86rotr.b` instruction (requires 64bit). + pub inline fn @"x86rotr.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8000, p0, p1); + } + + /// Encodes a `x86rotr.d` instruction (requires 64bit). + pub inline fn @"x86rotr.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8002, p0, p1); + } + + /// Encodes a `x86rotr.h` instruction (requires 64bit). + pub inline fn @"x86rotr.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8001, p0, p1); + } + + /// Encodes a `x86rotr.w` instruction (requires 64bit). + pub inline fn @"x86rotr.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8003, p0, p1); + } + + /// Encodes a `x86rotri.b` instruction (requires 64bit). + pub inline fn @"x86rotri.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x0054200c, p0, p1); + } + + /// Encodes a `x86rotri.d` instruction (requires 64bit). + pub inline fn @"x86rotri.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x0055000f, p0, p1); + } + + /// Encodes a `x86rotri.h` instruction (requires 64bit). + pub inline fn @"x86rotri.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x0054400d, p0, p1); + } + + /// Encodes a `x86rotri.w` instruction (requires 64bit). + pub inline fn @"x86rotri.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x0054800e, p0, p1); + } + + /// Encodes a `x86sbc.b` instruction (requires 64bit). + pub inline fn @"x86sbc.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0010, p0, p1); + } + + /// Encodes a `x86sbc.d` instruction (requires 64bit). + pub inline fn @"x86sbc.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0013, p0, p1); + } + + /// Encodes a `x86sbc.h` instruction (requires 64bit). + pub inline fn @"x86sbc.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0011, p0, p1); + } + + /// Encodes a `x86sbc.w` instruction (requires 64bit). + pub inline fn @"x86sbc.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0012, p0, p1); + } + + /// Encodes a `x86setj` instruction (requires 64bit). + pub inline fn x86setj(p0: Register, p1: u4) Instruction { + return encodeDUk4(0x00368000, p0, p1); + } + + /// Encodes a `x86setloope` instruction (requires 64bit). + pub inline fn x86setloope(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00007800, p0, p1); + } + + /// Encodes a `x86setloopne` instruction (requires 64bit). + pub inline fn x86setloopne(p0: Register, p1: Register) Instruction { + return encodeDJ(0x00007c00, p0, p1); + } + + /// Encodes a `x86settag` instruction (requires 64bit). + pub inline fn x86settag(p0: Register, p1: u5, p2: u8) Instruction { + return encodeDUj5Uk8(0x00580000, p0, p1, p2); + } + + /// Encodes a `x86settm` instruction (requires 64bit). + pub inline fn x86settm() Instruction { + return encodeEMPTY(0x00008008); + } + + /// Encodes a `x86sll.b` instruction (requires 64bit). + pub inline fn @"x86sll.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0014, p0, p1); + } + + /// Encodes a `x86sll.d` instruction (requires 64bit). + pub inline fn @"x86sll.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0017, p0, p1); + } + + /// Encodes a `x86sll.h` instruction (requires 64bit). + pub inline fn @"x86sll.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0015, p0, p1); + } + + /// Encodes a `x86sll.w` instruction (requires 64bit). + pub inline fn @"x86sll.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0016, p0, p1); + } + + /// Encodes a `x86slli.b` instruction (requires 64bit). + pub inline fn @"x86slli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542000, p0, p1); + } + + /// Encodes a `x86slli.d` instruction (requires 64bit). + pub inline fn @"x86slli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550003, p0, p1); + } + + /// Encodes a `x86slli.h` instruction (requires 64bit). + pub inline fn @"x86slli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544001, p0, p1); + } + + /// Encodes a `x86slli.w` instruction (requires 64bit). + pub inline fn @"x86slli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548002, p0, p1); + } + + /// Encodes a `x86sra.b` instruction (requires 64bit). + pub inline fn @"x86sra.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001c, p0, p1); + } + + /// Encodes a `x86sra.d` instruction (requires 64bit). + pub inline fn @"x86sra.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001f, p0, p1); + } + + /// Encodes a `x86sra.h` instruction (requires 64bit). + pub inline fn @"x86sra.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001d, p0, p1); + } + + /// Encodes a `x86sra.w` instruction (requires 64bit). + pub inline fn @"x86sra.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001e, p0, p1); + } + + /// Encodes a `x86srai.b` instruction (requires 64bit). + pub inline fn @"x86srai.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542008, p0, p1); + } + + /// Encodes a `x86srai.d` instruction (requires 64bit). + pub inline fn @"x86srai.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x0055000b, p0, p1); + } + + /// Encodes a `x86srai.h` instruction (requires 64bit). + pub inline fn @"x86srai.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544009, p0, p1); + } + + /// Encodes a `x86srai.w` instruction (requires 64bit). + pub inline fn @"x86srai.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x0054800a, p0, p1); + } + + /// Encodes a `x86srl.b` instruction (requires 64bit). + pub inline fn @"x86srl.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0018, p0, p1); + } + + /// Encodes a `x86srl.d` instruction (requires 64bit). + pub inline fn @"x86srl.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001b, p0, p1); + } + + /// Encodes a `x86srl.h` instruction (requires 64bit). + pub inline fn @"x86srl.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0019, p0, p1); + } + + /// Encodes a `x86srl.w` instruction (requires 64bit). + pub inline fn @"x86srl.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f001a, p0, p1); + } + + /// Encodes a `x86srli.b` instruction (requires 64bit). + pub inline fn @"x86srli.b"(p0: Register, p1: u3) Instruction { + return encodeJUk3(0x00542004, p0, p1); + } + + /// Encodes a `x86srli.d` instruction (requires 64bit). + pub inline fn @"x86srli.d"(p0: Register, p1: u6) Instruction { + return encodeJUk6(0x00550007, p0, p1); + } + + /// Encodes a `x86srli.h` instruction (requires 64bit). + pub inline fn @"x86srli.h"(p0: Register, p1: u4) Instruction { + return encodeJUk4(0x00544005, p0, p1); + } + + /// Encodes a `x86srli.w` instruction (requires 64bit). + pub inline fn @"x86srli.w"(p0: Register, p1: u5) Instruction { + return encodeJUk5(0x00548006, p0, p1); + } + + /// Encodes a `x86sub.b` instruction (requires 64bit). + pub inline fn @"x86sub.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0008, p0, p1); + } + + /// Encodes a `x86sub.d` instruction (requires 64bit). + pub inline fn @"x86sub.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000b, p0, p1); + } + + /// Encodes a `x86sub.du` instruction (requires 64bit). + pub inline fn @"x86sub.du"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0003, p0, p1); + } + + /// Encodes a `x86sub.h` instruction (requires 64bit). + pub inline fn @"x86sub.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0009, p0, p1); + } + + /// Encodes a `x86sub.w` instruction (requires 64bit). + pub inline fn @"x86sub.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f000a, p0, p1); + } + + /// Encodes a `x86sub.wu` instruction (requires 64bit). + pub inline fn @"x86sub.wu"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f0002, p0, p1); + } + + /// Encodes a `x86xor.b` instruction (requires 64bit). + pub inline fn @"x86xor.b"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8018, p0, p1); + } + + /// Encodes a `x86xor.d` instruction (requires 64bit). + pub inline fn @"x86xor.d"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f801b, p0, p1); + } + + /// Encodes a `x86xor.h` instruction (requires 64bit). + pub inline fn @"x86xor.h"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f8019, p0, p1); + } + + /// Encodes a `x86xor.w` instruction (requires 64bit). + pub inline fn @"x86xor.w"(p0: Register, p1: Register) Instruction { + return encodeJK(0x003f801a, p0, p1); + } + + /// Encodes a `xor` instruction (requires 32bit). + pub inline fn xor(p0: Register, p1: Register, p2: Register) Instruction { + return encodeDJK(0x00158000, p0, p1, p2); + } + + /// Encodes a `xori` instruction (requires 32bit). + pub inline fn xori(p0: Register, p1: Register, p2: u12) Instruction { + return encodeDJUk12(0x03c00000, p0, p1, p2); + } + + /// Encodes a `xvabsd.b` instruction (requires lasx). + pub inline fn @"xvabsd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74600000, p0, p1, p2); + } + + /// Encodes a `xvabsd.bu` instruction (requires lasx). + pub inline fn @"xvabsd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74620000, p0, p1, p2); + } + + /// Encodes a `xvabsd.d` instruction (requires lasx). + pub inline fn @"xvabsd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74618000, p0, p1, p2); + } + + /// Encodes a `xvabsd.du` instruction (requires lasx). + pub inline fn @"xvabsd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74638000, p0, p1, p2); + } + + /// Encodes a `xvabsd.h` instruction (requires lasx). + pub inline fn @"xvabsd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74608000, p0, p1, p2); + } + + /// Encodes a `xvabsd.hu` instruction (requires lasx). + pub inline fn @"xvabsd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74628000, p0, p1, p2); + } + + /// Encodes a `xvabsd.w` instruction (requires lasx). + pub inline fn @"xvabsd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74610000, p0, p1, p2); + } + + /// Encodes a `xvabsd.wu` instruction (requires lasx). + pub inline fn @"xvabsd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74630000, p0, p1, p2); + } + + /// Encodes a `xvadd.b` instruction (requires lasx). + pub inline fn @"xvadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740a0000, p0, p1, p2); + } + + /// Encodes a `xvadd.d` instruction (requires lasx). + pub inline fn @"xvadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740b8000, p0, p1, p2); + } + + /// Encodes a `xvadd.h` instruction (requires lasx). + pub inline fn @"xvadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740a8000, p0, p1, p2); + } + + /// Encodes a `xvadd.q` instruction (requires lasx). + pub inline fn @"xvadd.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752d0000, p0, p1, p2); + } + + /// Encodes a `xvadd.w` instruction (requires lasx). + pub inline fn @"xvadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740b0000, p0, p1, p2); + } + + /// Encodes a `xvadda.b` instruction (requires lasx). + pub inline fn @"xvadda.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745c0000, p0, p1, p2); + } + + /// Encodes a `xvadda.d` instruction (requires lasx). + pub inline fn @"xvadda.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745d8000, p0, p1, p2); + } + + /// Encodes a `xvadda.h` instruction (requires lasx). + pub inline fn @"xvadda.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745c8000, p0, p1, p2); + } + + /// Encodes a `xvadda.w` instruction (requires lasx). + pub inline fn @"xvadda.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745d0000, p0, p1, p2); + } + + /// Encodes a `xvaddi.bu` instruction (requires lasx). + pub inline fn @"xvaddi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768a0000, p0, p1, p2); + } + + /// Encodes a `xvaddi.du` instruction (requires lasx). + pub inline fn @"xvaddi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768b8000, p0, p1, p2); + } + + /// Encodes a `xvaddi.hu` instruction (requires lasx). + pub inline fn @"xvaddi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768a8000, p0, p1, p2); + } + + /// Encodes a `xvaddi.wu` instruction (requires lasx). + pub inline fn @"xvaddi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768b0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.d.w` instruction (requires lasx). + pub inline fn @"xvaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741f0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.d.wu` instruction (requires lasx). + pub inline fn @"xvaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742f0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.d.wu.w` instruction (requires lasx). + pub inline fn @"xvaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743f0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.h.b` instruction (requires lasx). + pub inline fn @"xvaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741e0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.h.bu` instruction (requires lasx). + pub inline fn @"xvaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742e0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.h.bu.b` instruction (requires lasx). + pub inline fn @"xvaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743e0000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.q.d` instruction (requires lasx). + pub inline fn @"xvaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741f8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.q.du` instruction (requires lasx). + pub inline fn @"xvaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742f8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.q.du.d` instruction (requires lasx). + pub inline fn @"xvaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743f8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.w.h` instruction (requires lasx). + pub inline fn @"xvaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x741e8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.w.hu` instruction (requires lasx). + pub inline fn @"xvaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x742e8000, p0, p1, p2); + } + + /// Encodes a `xvaddwev.w.hu.h` instruction (requires lasx). + pub inline fn @"xvaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x743e8000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.d.w` instruction (requires lasx). + pub inline fn @"xvaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74230000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.d.wu` instruction (requires lasx). + pub inline fn @"xvaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74330000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.d.wu.w` instruction (requires lasx). + pub inline fn @"xvaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74410000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.h.b` instruction (requires lasx). + pub inline fn @"xvaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74220000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.h.bu` instruction (requires lasx). + pub inline fn @"xvaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74320000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.h.bu.b` instruction (requires lasx). + pub inline fn @"xvaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74400000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.q.d` instruction (requires lasx). + pub inline fn @"xvaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74238000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.q.du` instruction (requires lasx). + pub inline fn @"xvaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74338000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.q.du.d` instruction (requires lasx). + pub inline fn @"xvaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74418000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.w.h` instruction (requires lasx). + pub inline fn @"xvaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74228000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.w.hu` instruction (requires lasx). + pub inline fn @"xvaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74328000, p0, p1, p2); + } + + /// Encodes a `xvaddwod.w.hu.h` instruction (requires lasx). + pub inline fn @"xvaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74408000, p0, p1, p2); + } + + /// Encodes a `xvand.v` instruction (requires lasx). + pub inline fn @"xvand.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75260000, p0, p1, p2); + } + + /// Encodes a `xvandi.b` instruction (requires lasx). + pub inline fn @"xvandi.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77d00000, p0, p1, p2); + } + + /// Encodes a `xvandn.v` instruction (requires lasx). + pub inline fn @"xvandn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75280000, p0, p1, p2); + } + + /// Encodes a `xvavg.b` instruction (requires lasx). + pub inline fn @"xvavg.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74640000, p0, p1, p2); + } + + /// Encodes a `xvavg.bu` instruction (requires lasx). + pub inline fn @"xvavg.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74660000, p0, p1, p2); + } + + /// Encodes a `xvavg.d` instruction (requires lasx). + pub inline fn @"xvavg.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74658000, p0, p1, p2); + } + + /// Encodes a `xvavg.du` instruction (requires lasx). + pub inline fn @"xvavg.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74678000, p0, p1, p2); + } + + /// Encodes a `xvavg.h` instruction (requires lasx). + pub inline fn @"xvavg.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74648000, p0, p1, p2); + } + + /// Encodes a `xvavg.hu` instruction (requires lasx). + pub inline fn @"xvavg.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74668000, p0, p1, p2); + } + + /// Encodes a `xvavg.w` instruction (requires lasx). + pub inline fn @"xvavg.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74650000, p0, p1, p2); + } + + /// Encodes a `xvavg.wu` instruction (requires lasx). + pub inline fn @"xvavg.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74670000, p0, p1, p2); + } + + /// Encodes a `xvavgr.b` instruction (requires lasx). + pub inline fn @"xvavgr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74680000, p0, p1, p2); + } + + /// Encodes a `xvavgr.bu` instruction (requires lasx). + pub inline fn @"xvavgr.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746a0000, p0, p1, p2); + } + + /// Encodes a `xvavgr.d` instruction (requires lasx). + pub inline fn @"xvavgr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74698000, p0, p1, p2); + } + + /// Encodes a `xvavgr.du` instruction (requires lasx). + pub inline fn @"xvavgr.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746b8000, p0, p1, p2); + } + + /// Encodes a `xvavgr.h` instruction (requires lasx). + pub inline fn @"xvavgr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74688000, p0, p1, p2); + } + + /// Encodes a `xvavgr.hu` instruction (requires lasx). + pub inline fn @"xvavgr.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746a8000, p0, p1, p2); + } + + /// Encodes a `xvavgr.w` instruction (requires lasx). + pub inline fn @"xvavgr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74690000, p0, p1, p2); + } + + /// Encodes a `xvavgr.wu` instruction (requires lasx). + pub inline fn @"xvavgr.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x746b0000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.b` instruction (requires lasx). + pub inline fn @"xvbitclr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750c0000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.d` instruction (requires lasx). + pub inline fn @"xvbitclr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750d8000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.h` instruction (requires lasx). + pub inline fn @"xvbitclr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750c8000, p0, p1, p2); + } + + /// Encodes a `xvbitclr.w` instruction (requires lasx). + pub inline fn @"xvbitclr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750d0000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.b` instruction (requires lasx). + pub inline fn @"xvbitclri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77102000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.d` instruction (requires lasx). + pub inline fn @"xvbitclri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77110000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.h` instruction (requires lasx). + pub inline fn @"xvbitclri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77104000, p0, p1, p2); + } + + /// Encodes a `xvbitclri.w` instruction (requires lasx). + pub inline fn @"xvbitclri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77108000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.b` instruction (requires lasx). + pub inline fn @"xvbitrev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75100000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.d` instruction (requires lasx). + pub inline fn @"xvbitrev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75118000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.h` instruction (requires lasx). + pub inline fn @"xvbitrev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75108000, p0, p1, p2); + } + + /// Encodes a `xvbitrev.w` instruction (requires lasx). + pub inline fn @"xvbitrev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75110000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.b` instruction (requires lasx). + pub inline fn @"xvbitrevi.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77182000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.d` instruction (requires lasx). + pub inline fn @"xvbitrevi.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77190000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.h` instruction (requires lasx). + pub inline fn @"xvbitrevi.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77184000, p0, p1, p2); + } + + /// Encodes a `xvbitrevi.w` instruction (requires lasx). + pub inline fn @"xvbitrevi.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77188000, p0, p1, p2); + } + + /// Encodes a `xvbitsel.v` instruction (requires lasx). + pub inline fn @"xvbitsel.v"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0d200000, p0, p1, p2, p3); + } + + /// Encodes a `xvbitseli.b` instruction (requires lasx). + pub inline fn @"xvbitseli.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77c40000, p0, p1, p2); + } + + /// Encodes a `xvbitset.b` instruction (requires lasx). + pub inline fn @"xvbitset.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750e0000, p0, p1, p2); + } + + /// Encodes a `xvbitset.d` instruction (requires lasx). + pub inline fn @"xvbitset.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750f8000, p0, p1, p2); + } + + /// Encodes a `xvbitset.h` instruction (requires lasx). + pub inline fn @"xvbitset.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750e8000, p0, p1, p2); + } + + /// Encodes a `xvbitset.w` instruction (requires lasx). + pub inline fn @"xvbitset.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750f0000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.b` instruction (requires lasx). + pub inline fn @"xvbitseti.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77142000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.d` instruction (requires lasx). + pub inline fn @"xvbitseti.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77150000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.h` instruction (requires lasx). + pub inline fn @"xvbitseti.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77144000, p0, p1, p2); + } + + /// Encodes a `xvbitseti.w` instruction (requires lasx). + pub inline fn @"xvbitseti.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77148000, p0, p1, p2); + } + + /// Encodes a `xvbsll.v` instruction (requires lasx). + pub inline fn @"xvbsll.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768e0000, p0, p1, p2); + } + + /// Encodes a `xvbsrl.v` instruction (requires lasx). + pub inline fn @"xvbsrl.v"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768e8000, p0, p1, p2); + } + + /// Encodes a `xvclo.b` instruction (requires lasx). + pub inline fn @"xvclo.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0000, p0, p1); + } + + /// Encodes a `xvclo.d` instruction (requires lasx). + pub inline fn @"xvclo.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0c00, p0, p1); + } + + /// Encodes a `xvclo.h` instruction (requires lasx). + pub inline fn @"xvclo.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0400, p0, p1); + } + + /// Encodes a `xvclo.w` instruction (requires lasx). + pub inline fn @"xvclo.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c0800, p0, p1); + } + + /// Encodes a `xvclz.b` instruction (requires lasx). + pub inline fn @"xvclz.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1000, p0, p1); + } + + /// Encodes a `xvclz.d` instruction (requires lasx). + pub inline fn @"xvclz.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1c00, p0, p1); + } + + /// Encodes a `xvclz.h` instruction (requires lasx). + pub inline fn @"xvclz.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1400, p0, p1); + } + + /// Encodes a `xvclz.w` instruction (requires lasx). + pub inline fn @"xvclz.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c1800, p0, p1); + } + + /// Encodes a `xvdiv.b` instruction (requires lasx). + pub inline fn @"xvdiv.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e00000, p0, p1, p2); + } + + /// Encodes a `xvdiv.bu` instruction (requires lasx). + pub inline fn @"xvdiv.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e40000, p0, p1, p2); + } + + /// Encodes a `xvdiv.d` instruction (requires lasx). + pub inline fn @"xvdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e18000, p0, p1, p2); + } + + /// Encodes a `xvdiv.du` instruction (requires lasx). + pub inline fn @"xvdiv.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e58000, p0, p1, p2); + } + + /// Encodes a `xvdiv.h` instruction (requires lasx). + pub inline fn @"xvdiv.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e08000, p0, p1, p2); + } + + /// Encodes a `xvdiv.hu` instruction (requires lasx). + pub inline fn @"xvdiv.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e48000, p0, p1, p2); + } + + /// Encodes a `xvdiv.w` instruction (requires lasx). + pub inline fn @"xvdiv.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e10000, p0, p1, p2); + } + + /// Encodes a `xvdiv.wu` instruction (requires lasx). + pub inline fn @"xvdiv.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e50000, p0, p1, p2); + } + + /// Encodes a `xvexth.d.w` instruction (requires lasx). + pub inline fn @"xvexth.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ee800, p0, p1); + } + + /// Encodes a `xvexth.du.wu` instruction (requires lasx). + pub inline fn @"xvexth.du.wu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ef800, p0, p1); + } + + /// Encodes a `xvexth.h.b` instruction (requires lasx). + pub inline fn @"xvexth.h.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ee000, p0, p1); + } + + /// Encodes a `xvexth.hu.bu` instruction (requires lasx). + pub inline fn @"xvexth.hu.bu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ef000, p0, p1); + } + + /// Encodes a `xvexth.q.d` instruction (requires lasx). + pub inline fn @"xvexth.q.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769eec00, p0, p1); + } + + /// Encodes a `xvexth.qu.du` instruction (requires lasx). + pub inline fn @"xvexth.qu.du"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769efc00, p0, p1); + } + + /// Encodes a `xvexth.w.h` instruction (requires lasx). + pub inline fn @"xvexth.w.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ee400, p0, p1); + } + + /// Encodes a `xvexth.wu.hu` instruction (requires lasx). + pub inline fn @"xvexth.wu.hu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ef400, p0, p1); + } + + /// Encodes a `xvextl.q.d` instruction (requires lasx). + pub inline fn @"xvextl.q.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x77090000, p0, p1); + } + + /// Encodes a `xvextl.qu.du` instruction (requires lasx). + pub inline fn @"xvextl.qu.du"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x770d0000, p0, p1); + } + + /// Encodes a `xvextrins.b` instruction (requires lasx). + pub inline fn @"xvextrins.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x778c0000, p0, p1, p2); + } + + /// Encodes a `xvextrins.d` instruction (requires lasx). + pub inline fn @"xvextrins.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77800000, p0, p1, p2); + } + + /// Encodes a `xvextrins.h` instruction (requires lasx). + pub inline fn @"xvextrins.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77880000, p0, p1, p2); + } + + /// Encodes a `xvextrins.w` instruction (requires lasx). + pub inline fn @"xvextrins.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77840000, p0, p1, p2); + } + + /// Encodes a `xvfadd.d` instruction (requires lasx). + pub inline fn @"xvfadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75310000, p0, p1, p2); + } + + /// Encodes a `xvfadd.s` instruction (requires lasx). + pub inline fn @"xvfadd.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75308000, p0, p1, p2); + } + + /// Encodes a `xvfclass.d` instruction (requires lasx). + pub inline fn @"xvfclass.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cd800, p0, p1); + } + + /// Encodes a `xvfclass.s` instruction (requires lasx). + pub inline fn @"xvfclass.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cd400, p0, p1); + } + + /// Encodes a `xvfcmp.caf.d` instruction (requires lasx). + pub inline fn @"xvfcmp.caf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca00000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.caf.s` instruction (requires lasx). + pub inline fn @"xvfcmp.caf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c900000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.ceq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.ceq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca20000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.ceq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.ceq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c920000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cle.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca30000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cle.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c930000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.clt.d` instruction (requires lasx). + pub inline fn @"xvfcmp.clt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca10000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.clt.s` instruction (requires lasx). + pub inline fn @"xvfcmp.clt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c910000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cne.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca80000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cne.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c980000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cor.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0caa0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cor.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9a0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cueq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca60000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cueq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c960000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cule.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca70000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cule.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c970000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cult.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca50000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cult.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c950000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cun.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca40000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cun.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c940000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cune.d` instruction (requires lasx). + pub inline fn @"xvfcmp.cune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0cac0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.cune.s` instruction (requires lasx). + pub inline fn @"xvfcmp.cune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9c0000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.saf.d` instruction (requires lasx). + pub inline fn @"xvfcmp.saf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca08000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.saf.s` instruction (requires lasx). + pub inline fn @"xvfcmp.saf.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c908000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.seq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.seq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca28000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.seq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.seq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c928000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sle.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca38000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sle.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sle.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c938000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.slt.d` instruction (requires lasx). + pub inline fn @"xvfcmp.slt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca18000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.slt.s` instruction (requires lasx). + pub inline fn @"xvfcmp.slt.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c918000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sne.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sne.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca88000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sne.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sne.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c988000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sor.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sor.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0caa8000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sor.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sor.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9a8000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sueq.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sueq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca68000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sueq.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sueq.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c968000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sule.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sule.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca78000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sule.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sule.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c978000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sult.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sult.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca58000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sult.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sult.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c958000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sun.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sun.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0ca48000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sun.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sun.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c948000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sune.d` instruction (requires lasx). + pub inline fn @"xvfcmp.sune.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0cac8000, p0, p1, p2); + } + + /// Encodes a `xvfcmp.sune.s` instruction (requires lasx). + pub inline fn @"xvfcmp.sune.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x0c9c8000, p0, p1, p2); + } + + /// Encodes a `xvfcvt.h.s` instruction (requires lasx). + pub inline fn @"xvfcvt.h.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75460000, p0, p1, p2); + } + + /// Encodes a `xvfcvt.s.d` instruction (requires lasx). + pub inline fn @"xvfcvt.s.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75468000, p0, p1, p2); + } + + /// Encodes a `xvfcvth.d.s` instruction (requires lasx). + pub inline fn @"xvfcvth.d.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769df400, p0, p1); + } + + /// Encodes a `xvfcvth.s.h` instruction (requires lasx). + pub inline fn @"xvfcvth.s.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769dec00, p0, p1); + } + + /// Encodes a `xvfcvtl.d.s` instruction (requires lasx). + pub inline fn @"xvfcvtl.d.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769df000, p0, p1); + } + + /// Encodes a `xvfcvtl.s.h` instruction (requires lasx). + pub inline fn @"xvfcvtl.s.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769de800, p0, p1); + } + + /// Encodes a `xvfdiv.d` instruction (requires lasx). + pub inline fn @"xvfdiv.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753b0000, p0, p1, p2); + } + + /// Encodes a `xvfdiv.s` instruction (requires lasx). + pub inline fn @"xvfdiv.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753a8000, p0, p1, p2); + } + + /// Encodes a `xvffint.d.l` instruction (requires lasx). + pub inline fn @"xvffint.d.l"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0800, p0, p1); + } + + /// Encodes a `xvffint.d.lu` instruction (requires lasx). + pub inline fn @"xvffint.d.lu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0c00, p0, p1); + } + + /// Encodes a `xvffint.s.l` instruction (requires lasx). + pub inline fn @"xvffint.s.l"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75480000, p0, p1, p2); + } + + /// Encodes a `xvffint.s.w` instruction (requires lasx). + pub inline fn @"xvffint.s.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0000, p0, p1); + } + + /// Encodes a `xvffint.s.wu` instruction (requires lasx). + pub inline fn @"xvffint.s.wu"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e0400, p0, p1); + } + + /// Encodes a `xvffinth.d.w` instruction (requires lasx). + pub inline fn @"xvffinth.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e1400, p0, p1); + } + + /// Encodes a `xvffintl.d.w` instruction (requires lasx). + pub inline fn @"xvffintl.d.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e1000, p0, p1); + } + + /// Encodes a `xvflogb.d` instruction (requires lasx). + pub inline fn @"xvflogb.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cc800, p0, p1); + } + + /// Encodes a `xvflogb.s` instruction (requires lasx). + pub inline fn @"xvflogb.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cc400, p0, p1); + } + + /// Encodes a `xvfmadd.d` instruction (requires lasx). + pub inline fn @"xvfmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a200000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmadd.s` instruction (requires lasx). + pub inline fn @"xvfmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a100000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmax.d` instruction (requires lasx). + pub inline fn @"xvfmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753d0000, p0, p1, p2); + } + + /// Encodes a `xvfmax.s` instruction (requires lasx). + pub inline fn @"xvfmax.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753c8000, p0, p1, p2); + } + + /// Encodes a `xvfmaxa.d` instruction (requires lasx). + pub inline fn @"xvfmaxa.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75410000, p0, p1, p2); + } + + /// Encodes a `xvfmaxa.s` instruction (requires lasx). + pub inline fn @"xvfmaxa.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75408000, p0, p1, p2); + } + + /// Encodes a `xvfmin.d` instruction (requires lasx). + pub inline fn @"xvfmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753f0000, p0, p1, p2); + } + + /// Encodes a `xvfmin.s` instruction (requires lasx). + pub inline fn @"xvfmin.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x753e8000, p0, p1, p2); + } + + /// Encodes a `xvfmina.d` instruction (requires lasx). + pub inline fn @"xvfmina.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75430000, p0, p1, p2); + } + + /// Encodes a `xvfmina.s` instruction (requires lasx). + pub inline fn @"xvfmina.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75428000, p0, p1, p2); + } + + /// Encodes a `xvfmsub.d` instruction (requires lasx). + pub inline fn @"xvfmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a600000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmsub.s` instruction (requires lasx). + pub inline fn @"xvfmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a500000, p0, p1, p2, p3); + } + + /// Encodes a `xvfmul.d` instruction (requires lasx). + pub inline fn @"xvfmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75390000, p0, p1, p2); + } + + /// Encodes a `xvfmul.s` instruction (requires lasx). + pub inline fn @"xvfmul.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75388000, p0, p1, p2); + } + + /// Encodes a `xvfnmadd.d` instruction (requires lasx). + pub inline fn @"xvfnmadd.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0aa00000, p0, p1, p2, p3); + } + + /// Encodes a `xvfnmadd.s` instruction (requires lasx). + pub inline fn @"xvfnmadd.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0a900000, p0, p1, p2, p3); + } + + /// Encodes a `xvfnmsub.d` instruction (requires lasx). + pub inline fn @"xvfnmsub.d"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0ae00000, p0, p1, p2, p3); + } + + /// Encodes a `xvfnmsub.s` instruction (requires lasx). + pub inline fn @"xvfnmsub.s"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0ad00000, p0, p1, p2, p3); + } + + /// Encodes a `xvfrecip.d` instruction (requires lasx). + pub inline fn @"xvfrecip.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cf800, p0, p1); + } + + /// Encodes a `xvfrecip.s` instruction (requires lasx). + pub inline fn @"xvfrecip.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769cf400, p0, p1); + } + + /// Encodes a `xvfrecipe.d` instruction (requires lasx). + pub inline fn @"xvfrecipe.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d1800, p0, p1); + } + + /// Encodes a `xvfrecipe.s` instruction (requires lasx). + pub inline fn @"xvfrecipe.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d1400, p0, p1); + } + + /// Encodes a `xvfrint.d` instruction (requires lasx). + pub inline fn @"xvfrint.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d3800, p0, p1); + } + + /// Encodes a `xvfrint.s` instruction (requires lasx). + pub inline fn @"xvfrint.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d3400, p0, p1); + } + + /// Encodes a `xvfrintrm.d` instruction (requires lasx). + pub inline fn @"xvfrintrm.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d4800, p0, p1); + } + + /// Encodes a `xvfrintrm.s` instruction (requires lasx). + pub inline fn @"xvfrintrm.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d4400, p0, p1); + } + + /// Encodes a `xvfrintrne.d` instruction (requires lasx). + pub inline fn @"xvfrintrne.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d7800, p0, p1); + } + + /// Encodes a `xvfrintrne.s` instruction (requires lasx). + pub inline fn @"xvfrintrne.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d7400, p0, p1); + } + + /// Encodes a `xvfrintrp.d` instruction (requires lasx). + pub inline fn @"xvfrintrp.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d5800, p0, p1); + } + + /// Encodes a `xvfrintrp.s` instruction (requires lasx). + pub inline fn @"xvfrintrp.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d5400, p0, p1); + } + + /// Encodes a `xvfrintrz.d` instruction (requires lasx). + pub inline fn @"xvfrintrz.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d6800, p0, p1); + } + + /// Encodes a `xvfrintrz.s` instruction (requires lasx). + pub inline fn @"xvfrintrz.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d6400, p0, p1); + } + + /// Encodes a `xvfrsqrt.d` instruction (requires lasx). + pub inline fn @"xvfrsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d0800, p0, p1); + } + + /// Encodes a `xvfrsqrt.s` instruction (requires lasx). + pub inline fn @"xvfrsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d0400, p0, p1); + } + + /// Encodes a `xvfrsqrte.d` instruction (requires lasx). + pub inline fn @"xvfrsqrte.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d2800, p0, p1); + } + + /// Encodes a `xvfrsqrte.s` instruction (requires lasx). + pub inline fn @"xvfrsqrte.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769d2400, p0, p1); + } + + /// Encodes a `xvfrstp.b` instruction (requires lasx). + pub inline fn @"xvfrstp.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752b0000, p0, p1, p2); + } + + /// Encodes a `xvfrstp.h` instruction (requires lasx). + pub inline fn @"xvfrstp.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752b8000, p0, p1, p2); + } + + /// Encodes a `xvfrstpi.b` instruction (requires lasx). + pub inline fn @"xvfrstpi.b"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x769a0000, p0, p1, p2); + } + + /// Encodes a `xvfrstpi.h` instruction (requires lasx). + pub inline fn @"xvfrstpi.h"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x769a8000, p0, p1, p2); + } + + /// Encodes a `xvfsqrt.d` instruction (requires lasx). + pub inline fn @"xvfsqrt.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ce800, p0, p1); + } + + /// Encodes a `xvfsqrt.s` instruction (requires lasx). + pub inline fn @"xvfsqrt.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ce400, p0, p1); + } + + /// Encodes a `xvfsub.d` instruction (requires lasx). + pub inline fn @"xvfsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75330000, p0, p1, p2); + } + + /// Encodes a `xvfsub.s` instruction (requires lasx). + pub inline fn @"xvfsub.s"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75328000, p0, p1, p2); + } + + /// Encodes a `xvftint.l.d` instruction (requires lasx). + pub inline fn @"xvftint.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3400, p0, p1); + } + + /// Encodes a `xvftint.lu.d` instruction (requires lasx). + pub inline fn @"xvftint.lu.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5c00, p0, p1); + } + + /// Encodes a `xvftint.w.d` instruction (requires lasx). + pub inline fn @"xvftint.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75498000, p0, p1, p2); + } + + /// Encodes a `xvftint.w.s` instruction (requires lasx). + pub inline fn @"xvftint.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3000, p0, p1); + } + + /// Encodes a `xvftint.wu.s` instruction (requires lasx). + pub inline fn @"xvftint.wu.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5800, p0, p1); + } + + /// Encodes a `xvftinth.l.s` instruction (requires lasx). + pub inline fn @"xvftinth.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8400, p0, p1); + } + + /// Encodes a `xvftintl.l.s` instruction (requires lasx). + pub inline fn @"xvftintl.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8000, p0, p1); + } + + /// Encodes a `xvftintrm.l.d` instruction (requires lasx). + pub inline fn @"xvftintrm.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3c00, p0, p1); + } + + /// Encodes a `xvftintrm.w.d` instruction (requires lasx). + pub inline fn @"xvftintrm.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754a0000, p0, p1, p2); + } + + /// Encodes a `xvftintrm.w.s` instruction (requires lasx). + pub inline fn @"xvftintrm.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e3800, p0, p1); + } + + /// Encodes a `xvftintrmh.l.s` instruction (requires lasx). + pub inline fn @"xvftintrmh.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8c00, p0, p1); + } + + /// Encodes a `xvftintrml.l.s` instruction (requires lasx). + pub inline fn @"xvftintrml.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e8800, p0, p1); + } + + /// Encodes a `xvftintrne.l.d` instruction (requires lasx). + pub inline fn @"xvftintrne.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5400, p0, p1); + } + + /// Encodes a `xvftintrne.w.d` instruction (requires lasx). + pub inline fn @"xvftintrne.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754b8000, p0, p1, p2); + } + + /// Encodes a `xvftintrne.w.s` instruction (requires lasx). + pub inline fn @"xvftintrne.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e5000, p0, p1); + } + + /// Encodes a `xvftintrneh.l.s` instruction (requires lasx). + pub inline fn @"xvftintrneh.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ea400, p0, p1); + } + + /// Encodes a `xvftintrnel.l.s` instruction (requires lasx). + pub inline fn @"xvftintrnel.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769ea000, p0, p1); + } + + /// Encodes a `xvftintrp.l.d` instruction (requires lasx). + pub inline fn @"xvftintrp.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4400, p0, p1); + } + + /// Encodes a `xvftintrp.w.d` instruction (requires lasx). + pub inline fn @"xvftintrp.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754a8000, p0, p1, p2); + } + + /// Encodes a `xvftintrp.w.s` instruction (requires lasx). + pub inline fn @"xvftintrp.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4000, p0, p1); + } + + /// Encodes a `xvftintrph.l.s` instruction (requires lasx). + pub inline fn @"xvftintrph.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9400, p0, p1); + } + + /// Encodes a `xvftintrpl.l.s` instruction (requires lasx). + pub inline fn @"xvftintrpl.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9000, p0, p1); + } + + /// Encodes a `xvftintrz.l.d` instruction (requires lasx). + pub inline fn @"xvftintrz.l.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4c00, p0, p1); + } + + /// Encodes a `xvftintrz.lu.d` instruction (requires lasx). + pub inline fn @"xvftintrz.lu.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e7400, p0, p1); + } + + /// Encodes a `xvftintrz.w.d` instruction (requires lasx). + pub inline fn @"xvftintrz.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x754b0000, p0, p1, p2); + } + + /// Encodes a `xvftintrz.w.s` instruction (requires lasx). + pub inline fn @"xvftintrz.w.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e4800, p0, p1); + } + + /// Encodes a `xvftintrz.wu.s` instruction (requires lasx). + pub inline fn @"xvftintrz.wu.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e7000, p0, p1); + } + + /// Encodes a `xvftintrzh.l.s` instruction (requires lasx). + pub inline fn @"xvftintrzh.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9c00, p0, p1); + } + + /// Encodes a `xvftintrzl.l.s` instruction (requires lasx). + pub inline fn @"xvftintrzl.l.s"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769e9800, p0, p1); + } + + /// Encodes a `xvhaddw.d.w` instruction (requires lasx). + pub inline fn @"xvhaddw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74550000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.du.wu` instruction (requires lasx). + pub inline fn @"xvhaddw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74590000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.h.b` instruction (requires lasx). + pub inline fn @"xvhaddw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74540000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.hu.bu` instruction (requires lasx). + pub inline fn @"xvhaddw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74580000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.q.d` instruction (requires lasx). + pub inline fn @"xvhaddw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74558000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.qu.du` instruction (requires lasx). + pub inline fn @"xvhaddw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74598000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.w.h` instruction (requires lasx). + pub inline fn @"xvhaddw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74548000, p0, p1, p2); + } + + /// Encodes a `xvhaddw.wu.hu` instruction (requires lasx). + pub inline fn @"xvhaddw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74588000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.d.w` instruction (requires lasx). + pub inline fn @"xvhsubw.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74570000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.du.wu` instruction (requires lasx). + pub inline fn @"xvhsubw.du.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745b0000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.h.b` instruction (requires lasx). + pub inline fn @"xvhsubw.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74560000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.hu.bu` instruction (requires lasx). + pub inline fn @"xvhsubw.hu.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745a0000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.q.d` instruction (requires lasx). + pub inline fn @"xvhsubw.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74578000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.qu.du` instruction (requires lasx). + pub inline fn @"xvhsubw.qu.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745b8000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.w.h` instruction (requires lasx). + pub inline fn @"xvhsubw.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74568000, p0, p1, p2); + } + + /// Encodes a `xvhsubw.wu.hu` instruction (requires lasx). + pub inline fn @"xvhsubw.wu.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x745a8000, p0, p1, p2); + } + + /// Encodes a `xvilvh.b` instruction (requires lasx). + pub inline fn @"xvilvh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751c0000, p0, p1, p2); + } + + /// Encodes a `xvilvh.d` instruction (requires lasx). + pub inline fn @"xvilvh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751d8000, p0, p1, p2); + } + + /// Encodes a `xvilvh.h` instruction (requires lasx). + pub inline fn @"xvilvh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751c8000, p0, p1, p2); + } + + /// Encodes a `xvilvh.w` instruction (requires lasx). + pub inline fn @"xvilvh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751d0000, p0, p1, p2); + } + + /// Encodes a `xvilvl.b` instruction (requires lasx). + pub inline fn @"xvilvl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751a0000, p0, p1, p2); + } + + /// Encodes a `xvilvl.d` instruction (requires lasx). + pub inline fn @"xvilvl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751b8000, p0, p1, p2); + } + + /// Encodes a `xvilvl.h` instruction (requires lasx). + pub inline fn @"xvilvl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751a8000, p0, p1, p2); + } + + /// Encodes a `xvilvl.w` instruction (requires lasx). + pub inline fn @"xvilvl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751b0000, p0, p1, p2); + } + + /// Encodes a `xvinsgr2vr.d` instruction (requires lasx). + pub inline fn @"xvinsgr2vr.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdJUk2(0x76ebe000, p0, p1, p2); + } + + /// Encodes a `xvinsgr2vr.w` instruction (requires lasx). + pub inline fn @"xvinsgr2vr.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdJUk3(0x76ebc000, p0, p1, p2); + } + + /// Encodes a `xvinsve0.d` instruction (requires lasx). + pub inline fn @"xvinsve0.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdXjUk2(0x76ffe000, p0, p1, p2); + } + + /// Encodes a `xvinsve0.w` instruction (requires lasx). + pub inline fn @"xvinsve0.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76ffc000, p0, p1, p2); + } + + /// Encodes a `xvld` instruction (requires lasx). + pub inline fn xvld(p0: Register, p1: Register, p2: i12) Instruction { + return encodeXdJSk12(0x2c800000, p0, p1, p2); + } + + /// Encodes a `xvldi` instruction (requires lasx). + pub inline fn xvldi(p0: Register, p1: i13) Instruction { + return encodeXdSj13(0x77e00000, p0, p1); + } + + /// Encodes a `xvldrepl.b` instruction (requires lasx). + pub inline fn @"xvldrepl.b"(p0: Register, p1: Register, p2: i12) Instruction { + return encodeXdJSk12(0x32800000, p0, p1, p2); + } + + /// Encodes a `xvldrepl.d` instruction (requires lasx). + pub inline fn @"xvldrepl.d"(p0: Register, p1: Register, p2: i9) Instruction { + return encodeXdJSk9ps3(0x32100000, p0, p1, p2); + } + + /// Encodes a `xvldrepl.h` instruction (requires lasx). + pub inline fn @"xvldrepl.h"(p0: Register, p1: Register, p2: i11) Instruction { + return encodeXdJSk11ps1(0x32400000, p0, p1, p2); + } + + /// Encodes a `xvldrepl.w` instruction (requires lasx). + pub inline fn @"xvldrepl.w"(p0: Register, p1: Register, p2: i10) Instruction { + return encodeXdJSk10ps2(0x32200000, p0, p1, p2); + } + + /// Encodes a `xvldx` instruction (requires lasx). + pub inline fn xvldx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdJK(0x38480000, p0, p1, p2); + } + + /// Encodes a `xvmadd.b` instruction (requires lasx). + pub inline fn @"xvmadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a80000, p0, p1, p2); + } + + /// Encodes a `xvmadd.d` instruction (requires lasx). + pub inline fn @"xvmadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a98000, p0, p1, p2); + } + + /// Encodes a `xvmadd.h` instruction (requires lasx). + pub inline fn @"xvmadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a88000, p0, p1, p2); + } + + /// Encodes a `xvmadd.w` instruction (requires lasx). + pub inline fn @"xvmadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a90000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.d.w` instruction (requires lasx). + pub inline fn @"xvmaddwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ad0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.d.wu` instruction (requires lasx). + pub inline fn @"xvmaddwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b50000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmaddwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bd0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.h.b` instruction (requires lasx). + pub inline fn @"xvmaddwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ac0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.h.bu` instruction (requires lasx). + pub inline fn @"xvmaddwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b40000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmaddwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bc0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.q.d` instruction (requires lasx). + pub inline fn @"xvmaddwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ad8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.q.du` instruction (requires lasx). + pub inline fn @"xvmaddwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b58000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.q.du.d` instruction (requires lasx). + pub inline fn @"xvmaddwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bd8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.w.h` instruction (requires lasx). + pub inline fn @"xvmaddwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ac8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.w.hu` instruction (requires lasx). + pub inline fn @"xvmaddwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b48000, p0, p1, p2); + } + + /// Encodes a `xvmaddwev.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmaddwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bc8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.d.w` instruction (requires lasx). + pub inline fn @"xvmaddwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74af0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.d.wu` instruction (requires lasx). + pub inline fn @"xvmaddwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b70000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmaddwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bf0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.h.b` instruction (requires lasx). + pub inline fn @"xvmaddwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ae0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.h.bu` instruction (requires lasx). + pub inline fn @"xvmaddwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b60000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmaddwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74be0000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.q.d` instruction (requires lasx). + pub inline fn @"xvmaddwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74af8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.q.du` instruction (requires lasx). + pub inline fn @"xvmaddwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b78000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.q.du.d` instruction (requires lasx). + pub inline fn @"xvmaddwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74bf8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.w.h` instruction (requires lasx). + pub inline fn @"xvmaddwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ae8000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.w.hu` instruction (requires lasx). + pub inline fn @"xvmaddwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74b68000, p0, p1, p2); + } + + /// Encodes a `xvmaddwod.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmaddwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74be8000, p0, p1, p2); + } + + /// Encodes a `xvmax.b` instruction (requires lasx). + pub inline fn @"xvmax.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74700000, p0, p1, p2); + } + + /// Encodes a `xvmax.bu` instruction (requires lasx). + pub inline fn @"xvmax.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74740000, p0, p1, p2); + } + + /// Encodes a `xvmax.d` instruction (requires lasx). + pub inline fn @"xvmax.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74718000, p0, p1, p2); + } + + /// Encodes a `xvmax.du` instruction (requires lasx). + pub inline fn @"xvmax.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74758000, p0, p1, p2); + } + + /// Encodes a `xvmax.h` instruction (requires lasx). + pub inline fn @"xvmax.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74708000, p0, p1, p2); + } + + /// Encodes a `xvmax.hu` instruction (requires lasx). + pub inline fn @"xvmax.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74748000, p0, p1, p2); + } + + /// Encodes a `xvmax.w` instruction (requires lasx). + pub inline fn @"xvmax.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74710000, p0, p1, p2); + } + + /// Encodes a `xvmax.wu` instruction (requires lasx). + pub inline fn @"xvmax.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74750000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.b` instruction (requires lasx). + pub inline fn @"xvmaxi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76900000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.bu` instruction (requires lasx). + pub inline fn @"xvmaxi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76940000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.d` instruction (requires lasx). + pub inline fn @"xvmaxi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76918000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.du` instruction (requires lasx). + pub inline fn @"xvmaxi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76958000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.h` instruction (requires lasx). + pub inline fn @"xvmaxi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76908000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.hu` instruction (requires lasx). + pub inline fn @"xvmaxi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76948000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.w` instruction (requires lasx). + pub inline fn @"xvmaxi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76910000, p0, p1, p2); + } + + /// Encodes a `xvmaxi.wu` instruction (requires lasx). + pub inline fn @"xvmaxi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76950000, p0, p1, p2); + } + + /// Encodes a `xvmepatmsk.v` instruction (requires lasx). + pub inline fn @"xvmepatmsk.v"(p0: Register, p1: u5, p2: u5) Instruction { + return encodeXdUj5Uk5(0x769b8000, p0, p1, p2); + } + + /// Encodes a `xvmin.b` instruction (requires lasx). + pub inline fn @"xvmin.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74720000, p0, p1, p2); + } + + /// Encodes a `xvmin.bu` instruction (requires lasx). + pub inline fn @"xvmin.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74760000, p0, p1, p2); + } + + /// Encodes a `xvmin.d` instruction (requires lasx). + pub inline fn @"xvmin.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74738000, p0, p1, p2); + } + + /// Encodes a `xvmin.du` instruction (requires lasx). + pub inline fn @"xvmin.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74778000, p0, p1, p2); + } + + /// Encodes a `xvmin.h` instruction (requires lasx). + pub inline fn @"xvmin.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74728000, p0, p1, p2); + } + + /// Encodes a `xvmin.hu` instruction (requires lasx). + pub inline fn @"xvmin.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74768000, p0, p1, p2); + } + + /// Encodes a `xvmin.w` instruction (requires lasx). + pub inline fn @"xvmin.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74730000, p0, p1, p2); + } + + /// Encodes a `xvmin.wu` instruction (requires lasx). + pub inline fn @"xvmin.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74770000, p0, p1, p2); + } + + /// Encodes a `xvmini.b` instruction (requires lasx). + pub inline fn @"xvmini.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76920000, p0, p1, p2); + } + + /// Encodes a `xvmini.bu` instruction (requires lasx). + pub inline fn @"xvmini.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76960000, p0, p1, p2); + } + + /// Encodes a `xvmini.d` instruction (requires lasx). + pub inline fn @"xvmini.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76938000, p0, p1, p2); + } + + /// Encodes a `xvmini.du` instruction (requires lasx). + pub inline fn @"xvmini.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76978000, p0, p1, p2); + } + + /// Encodes a `xvmini.h` instruction (requires lasx). + pub inline fn @"xvmini.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76928000, p0, p1, p2); + } + + /// Encodes a `xvmini.hu` instruction (requires lasx). + pub inline fn @"xvmini.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76968000, p0, p1, p2); + } + + /// Encodes a `xvmini.w` instruction (requires lasx). + pub inline fn @"xvmini.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76930000, p0, p1, p2); + } + + /// Encodes a `xvmini.wu` instruction (requires lasx). + pub inline fn @"xvmini.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76970000, p0, p1, p2); + } + + /// Encodes a `xvmod.b` instruction (requires lasx). + pub inline fn @"xvmod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e20000, p0, p1, p2); + } + + /// Encodes a `xvmod.bu` instruction (requires lasx). + pub inline fn @"xvmod.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e60000, p0, p1, p2); + } + + /// Encodes a `xvmod.d` instruction (requires lasx). + pub inline fn @"xvmod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e38000, p0, p1, p2); + } + + /// Encodes a `xvmod.du` instruction (requires lasx). + pub inline fn @"xvmod.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e78000, p0, p1, p2); + } + + /// Encodes a `xvmod.h` instruction (requires lasx). + pub inline fn @"xvmod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e28000, p0, p1, p2); + } + + /// Encodes a `xvmod.hu` instruction (requires lasx). + pub inline fn @"xvmod.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e68000, p0, p1, p2); + } + + /// Encodes a `xvmod.w` instruction (requires lasx). + pub inline fn @"xvmod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e30000, p0, p1, p2); + } + + /// Encodes a `xvmod.wu` instruction (requires lasx). + pub inline fn @"xvmod.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e70000, p0, p1, p2); + } + + /// Encodes a `xvmskgez.b` instruction (requires lasx). + pub inline fn @"xvmskgez.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c5000, p0, p1); + } + + /// Encodes a `xvmskltz.b` instruction (requires lasx). + pub inline fn @"xvmskltz.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4000, p0, p1); + } + + /// Encodes a `xvmskltz.d` instruction (requires lasx). + pub inline fn @"xvmskltz.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4c00, p0, p1); + } + + /// Encodes a `xvmskltz.h` instruction (requires lasx). + pub inline fn @"xvmskltz.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4400, p0, p1); + } + + /// Encodes a `xvmskltz.w` instruction (requires lasx). + pub inline fn @"xvmskltz.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c4800, p0, p1); + } + + /// Encodes a `xvmsknz.b` instruction (requires lasx). + pub inline fn @"xvmsknz.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c6000, p0, p1); + } + + /// Encodes a `xvmsub.b` instruction (requires lasx). + pub inline fn @"xvmsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74aa0000, p0, p1, p2); + } + + /// Encodes a `xvmsub.d` instruction (requires lasx). + pub inline fn @"xvmsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ab8000, p0, p1, p2); + } + + /// Encodes a `xvmsub.h` instruction (requires lasx). + pub inline fn @"xvmsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74aa8000, p0, p1, p2); + } + + /// Encodes a `xvmsub.w` instruction (requires lasx). + pub inline fn @"xvmsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ab0000, p0, p1, p2); + } + + /// Encodes a `xvmuh.b` instruction (requires lasx). + pub inline fn @"xvmuh.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74860000, p0, p1, p2); + } + + /// Encodes a `xvmuh.bu` instruction (requires lasx). + pub inline fn @"xvmuh.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74880000, p0, p1, p2); + } + + /// Encodes a `xvmuh.d` instruction (requires lasx). + pub inline fn @"xvmuh.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74878000, p0, p1, p2); + } + + /// Encodes a `xvmuh.du` instruction (requires lasx). + pub inline fn @"xvmuh.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74898000, p0, p1, p2); + } + + /// Encodes a `xvmuh.h` instruction (requires lasx). + pub inline fn @"xvmuh.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74868000, p0, p1, p2); + } + + /// Encodes a `xvmuh.hu` instruction (requires lasx). + pub inline fn @"xvmuh.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74888000, p0, p1, p2); + } + + /// Encodes a `xvmuh.w` instruction (requires lasx). + pub inline fn @"xvmuh.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74870000, p0, p1, p2); + } + + /// Encodes a `xvmuh.wu` instruction (requires lasx). + pub inline fn @"xvmuh.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74890000, p0, p1, p2); + } + + /// Encodes a `xvmul.b` instruction (requires lasx). + pub inline fn @"xvmul.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74840000, p0, p1, p2); + } + + /// Encodes a `xvmul.d` instruction (requires lasx). + pub inline fn @"xvmul.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74858000, p0, p1, p2); + } + + /// Encodes a `xvmul.h` instruction (requires lasx). + pub inline fn @"xvmul.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74848000, p0, p1, p2); + } + + /// Encodes a `xvmul.w` instruction (requires lasx). + pub inline fn @"xvmul.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74850000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.d.w` instruction (requires lasx). + pub inline fn @"xvmulwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74910000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.d.wu` instruction (requires lasx). + pub inline fn @"xvmulwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74990000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmulwev.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a10000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.h.b` instruction (requires lasx). + pub inline fn @"xvmulwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74900000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.h.bu` instruction (requires lasx). + pub inline fn @"xvmulwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74980000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmulwev.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a00000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.q.d` instruction (requires lasx). + pub inline fn @"xvmulwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74918000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.q.du` instruction (requires lasx). + pub inline fn @"xvmulwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74998000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.q.du.d` instruction (requires lasx). + pub inline fn @"xvmulwev.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a18000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.w.h` instruction (requires lasx). + pub inline fn @"xvmulwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74908000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.w.hu` instruction (requires lasx). + pub inline fn @"xvmulwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74988000, p0, p1, p2); + } + + /// Encodes a `xvmulwev.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmulwev.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a08000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.d.w` instruction (requires lasx). + pub inline fn @"xvmulwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74930000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.d.wu` instruction (requires lasx). + pub inline fn @"xvmulwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749b0000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.d.wu.w` instruction (requires lasx). + pub inline fn @"xvmulwod.d.wu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a30000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.h.b` instruction (requires lasx). + pub inline fn @"xvmulwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74920000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.h.bu` instruction (requires lasx). + pub inline fn @"xvmulwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749a0000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.h.bu.b` instruction (requires lasx). + pub inline fn @"xvmulwod.h.bu.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a20000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.q.d` instruction (requires lasx). + pub inline fn @"xvmulwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74938000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.q.du` instruction (requires lasx). + pub inline fn @"xvmulwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749b8000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.q.du.d` instruction (requires lasx). + pub inline fn @"xvmulwod.q.du.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a38000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.w.h` instruction (requires lasx). + pub inline fn @"xvmulwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74928000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.w.hu` instruction (requires lasx). + pub inline fn @"xvmulwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x749a8000, p0, p1, p2); + } + + /// Encodes a `xvmulwod.w.hu.h` instruction (requires lasx). + pub inline fn @"xvmulwod.w.hu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74a28000, p0, p1, p2); + } + + /// Encodes a `xvneg.b` instruction (requires lasx). + pub inline fn @"xvneg.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3000, p0, p1); + } + + /// Encodes a `xvneg.d` instruction (requires lasx). + pub inline fn @"xvneg.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3c00, p0, p1); + } + + /// Encodes a `xvneg.h` instruction (requires lasx). + pub inline fn @"xvneg.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3400, p0, p1); + } + + /// Encodes a `xvneg.w` instruction (requires lasx). + pub inline fn @"xvneg.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c3800, p0, p1); + } + + /// Encodes a `xvnor.v` instruction (requires lasx). + pub inline fn @"xvnor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75278000, p0, p1, p2); + } + + /// Encodes a `xvnori.b` instruction (requires lasx). + pub inline fn @"xvnori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77dc0000, p0, p1, p2); + } + + /// Encodes a `xvor.v` instruction (requires lasx). + pub inline fn @"xvor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75268000, p0, p1, p2); + } + + /// Encodes a `xvori.b` instruction (requires lasx). + pub inline fn @"xvori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77d40000, p0, p1, p2); + } + + /// Encodes a `xvorn.v` instruction (requires lasx). + pub inline fn @"xvorn.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75288000, p0, p1, p2); + } + + /// Encodes a `xvpackev.b` instruction (requires lasx). + pub inline fn @"xvpackev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75160000, p0, p1, p2); + } + + /// Encodes a `xvpackev.d` instruction (requires lasx). + pub inline fn @"xvpackev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75178000, p0, p1, p2); + } + + /// Encodes a `xvpackev.h` instruction (requires lasx). + pub inline fn @"xvpackev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75168000, p0, p1, p2); + } + + /// Encodes a `xvpackev.w` instruction (requires lasx). + pub inline fn @"xvpackev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75170000, p0, p1, p2); + } + + /// Encodes a `xvpackod.b` instruction (requires lasx). + pub inline fn @"xvpackod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75180000, p0, p1, p2); + } + + /// Encodes a `xvpackod.d` instruction (requires lasx). + pub inline fn @"xvpackod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75198000, p0, p1, p2); + } + + /// Encodes a `xvpackod.h` instruction (requires lasx). + pub inline fn @"xvpackod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75188000, p0, p1, p2); + } + + /// Encodes a `xvpackod.w` instruction (requires lasx). + pub inline fn @"xvpackod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75190000, p0, p1, p2); + } + + /// Encodes a `xvpcnt.b` instruction (requires lasx). + pub inline fn @"xvpcnt.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2000, p0, p1); + } + + /// Encodes a `xvpcnt.d` instruction (requires lasx). + pub inline fn @"xvpcnt.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2c00, p0, p1); + } + + /// Encodes a `xvpcnt.h` instruction (requires lasx). + pub inline fn @"xvpcnt.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2400, p0, p1); + } + + /// Encodes a `xvpcnt.w` instruction (requires lasx). + pub inline fn @"xvpcnt.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x769c2800, p0, p1); + } + + /// Encodes a `xvperm.w` instruction (requires lasx). + pub inline fn @"xvperm.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757d0000, p0, p1, p2); + } + + /// Encodes a `xvpermi.d` instruction (requires lasx). + pub inline fn @"xvpermi.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77e80000, p0, p1, p2); + } + + /// Encodes a `xvpermi.q` instruction (requires lasx). + pub inline fn @"xvpermi.q"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77ec0000, p0, p1, p2); + } + + /// Encodes a `xvpermi.w` instruction (requires lasx). + pub inline fn @"xvpermi.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77e40000, p0, p1, p2); + } + + /// Encodes a `xvpickev.b` instruction (requires lasx). + pub inline fn @"xvpickev.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751e0000, p0, p1, p2); + } + + /// Encodes a `xvpickev.d` instruction (requires lasx). + pub inline fn @"xvpickev.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751f8000, p0, p1, p2); + } + + /// Encodes a `xvpickev.h` instruction (requires lasx). + pub inline fn @"xvpickev.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751e8000, p0, p1, p2); + } + + /// Encodes a `xvpickev.w` instruction (requires lasx). + pub inline fn @"xvpickev.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x751f0000, p0, p1, p2); + } + + /// Encodes a `xvpickod.b` instruction (requires lasx). + pub inline fn @"xvpickod.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75200000, p0, p1, p2); + } + + /// Encodes a `xvpickod.d` instruction (requires lasx). + pub inline fn @"xvpickod.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75218000, p0, p1, p2); + } + + /// Encodes a `xvpickod.h` instruction (requires lasx). + pub inline fn @"xvpickod.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75208000, p0, p1, p2); + } + + /// Encodes a `xvpickod.w` instruction (requires lasx). + pub inline fn @"xvpickod.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75210000, p0, p1, p2); + } + + /// Encodes a `xvpickve.d` instruction (requires lasx). + pub inline fn @"xvpickve.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdXjUk2(0x7703e000, p0, p1, p2); + } + + /// Encodes a `xvpickve.w` instruction (requires lasx). + pub inline fn @"xvpickve.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x7703c000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.d` instruction (requires lasx). + pub inline fn @"xvpickve2gr.d"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDXjUk2(0x76efe000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.du` instruction (requires lasx). + pub inline fn @"xvpickve2gr.du"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeDXjUk2(0x76f3e000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.w` instruction (requires lasx). + pub inline fn @"xvpickve2gr.w"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDXjUk3(0x76efc000, p0, p1, p2); + } + + /// Encodes a `xvpickve2gr.wu` instruction (requires lasx). + pub inline fn @"xvpickve2gr.wu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeDXjUk3(0x76f3c000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.b` instruction (requires lasx). + pub inline fn @"xvrepl128vei.b"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76f78000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.d` instruction (requires lasx). + pub inline fn @"xvrepl128vei.d"(p0: Register, p1: Register, p2: u1) Instruction { + return encodeXdXjUk1(0x76f7f000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.h` instruction (requires lasx). + pub inline fn @"xvrepl128vei.h"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76f7c000, p0, p1, p2); + } + + /// Encodes a `xvrepl128vei.w` instruction (requires lasx). + pub inline fn @"xvrepl128vei.w"(p0: Register, p1: Register, p2: u2) Instruction { + return encodeXdXjUk2(0x76f7e000, p0, p1, p2); + } + + /// Encodes a `xvreplgr2vr.b` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.b"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0000, p0, p1); + } + + /// Encodes a `xvreplgr2vr.d` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.d"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0c00, p0, p1); + } + + /// Encodes a `xvreplgr2vr.h` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.h"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0400, p0, p1); + } + + /// Encodes a `xvreplgr2vr.w` instruction (requires lasx). + pub inline fn @"xvreplgr2vr.w"(p0: Register, p1: Register) Instruction { + return encodeXdJ(0x769f0800, p0, p1); + } + + /// Encodes a `xvreplve.b` instruction (requires lasx). + pub inline fn @"xvreplve.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75220000, p0, p1, p2); + } + + /// Encodes a `xvreplve.d` instruction (requires lasx). + pub inline fn @"xvreplve.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75238000, p0, p1, p2); + } + + /// Encodes a `xvreplve.h` instruction (requires lasx). + pub inline fn @"xvreplve.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75228000, p0, p1, p2); + } + + /// Encodes a `xvreplve.w` instruction (requires lasx). + pub inline fn @"xvreplve.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjK(0x75230000, p0, p1, p2); + } + + /// Encodes a `xvreplve0.b` instruction (requires lasx). + pub inline fn @"xvreplve0.b"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x77070000, p0, p1); + } + + /// Encodes a `xvreplve0.d` instruction (requires lasx). + pub inline fn @"xvreplve0.d"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x7707e000, p0, p1); + } + + /// Encodes a `xvreplve0.h` instruction (requires lasx). + pub inline fn @"xvreplve0.h"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x77078000, p0, p1); + } + + /// Encodes a `xvreplve0.q` instruction (requires lasx). + pub inline fn @"xvreplve0.q"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x7707f000, p0, p1); + } + + /// Encodes a `xvreplve0.w` instruction (requires lasx). + pub inline fn @"xvreplve0.w"(p0: Register, p1: Register) Instruction { + return encodeXdXj(0x7707c000, p0, p1); + } + + /// Encodes a `xvrotr.b` instruction (requires lasx). + pub inline fn @"xvrotr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ee0000, p0, p1, p2); + } + + /// Encodes a `xvrotr.d` instruction (requires lasx). + pub inline fn @"xvrotr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ef8000, p0, p1, p2); + } + + /// Encodes a `xvrotr.h` instruction (requires lasx). + pub inline fn @"xvrotr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ee8000, p0, p1, p2); + } + + /// Encodes a `xvrotr.w` instruction (requires lasx). + pub inline fn @"xvrotr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ef0000, p0, p1, p2); + } + + /// Encodes a `xvrotri.b` instruction (requires lasx). + pub inline fn @"xvrotri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76a02000, p0, p1, p2); + } + + /// Encodes a `xvrotri.d` instruction (requires lasx). + pub inline fn @"xvrotri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x76a10000, p0, p1, p2); + } + + /// Encodes a `xvrotri.h` instruction (requires lasx). + pub inline fn @"xvrotri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76a04000, p0, p1, p2); + } + + /// Encodes a `xvrotri.w` instruction (requires lasx). + pub inline fn @"xvrotri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76a08000, p0, p1, p2); + } + + /// Encodes a `xvsadd.b` instruction (requires lasx). + pub inline fn @"xvsadd.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74460000, p0, p1, p2); + } + + /// Encodes a `xvsadd.bu` instruction (requires lasx). + pub inline fn @"xvsadd.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744a0000, p0, p1, p2); + } + + /// Encodes a `xvsadd.d` instruction (requires lasx). + pub inline fn @"xvsadd.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74478000, p0, p1, p2); + } + + /// Encodes a `xvsadd.du` instruction (requires lasx). + pub inline fn @"xvsadd.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744b8000, p0, p1, p2); + } + + /// Encodes a `xvsadd.h` instruction (requires lasx). + pub inline fn @"xvsadd.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74468000, p0, p1, p2); + } + + /// Encodes a `xvsadd.hu` instruction (requires lasx). + pub inline fn @"xvsadd.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744a8000, p0, p1, p2); + } + + /// Encodes a `xvsadd.w` instruction (requires lasx). + pub inline fn @"xvsadd.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74470000, p0, p1, p2); + } + + /// Encodes a `xvsadd.wu` instruction (requires lasx). + pub inline fn @"xvsadd.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744b0000, p0, p1, p2); + } + + /// Encodes a `xvsat.b` instruction (requires lasx). + pub inline fn @"xvsat.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77242000, p0, p1, p2); + } + + /// Encodes a `xvsat.bu` instruction (requires lasx). + pub inline fn @"xvsat.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77282000, p0, p1, p2); + } + + /// Encodes a `xvsat.d` instruction (requires lasx). + pub inline fn @"xvsat.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77250000, p0, p1, p2); + } + + /// Encodes a `xvsat.du` instruction (requires lasx). + pub inline fn @"xvsat.du"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77290000, p0, p1, p2); + } + + /// Encodes a `xvsat.h` instruction (requires lasx). + pub inline fn @"xvsat.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77244000, p0, p1, p2); + } + + /// Encodes a `xvsat.hu` instruction (requires lasx). + pub inline fn @"xvsat.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77284000, p0, p1, p2); + } + + /// Encodes a `xvsat.w` instruction (requires lasx). + pub inline fn @"xvsat.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77248000, p0, p1, p2); + } + + /// Encodes a `xvsat.wu` instruction (requires lasx). + pub inline fn @"xvsat.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77288000, p0, p1, p2); + } + + /// Encodes a `xvseq.b` instruction (requires lasx). + pub inline fn @"xvseq.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74000000, p0, p1, p2); + } + + /// Encodes a `xvseq.d` instruction (requires lasx). + pub inline fn @"xvseq.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74018000, p0, p1, p2); + } + + /// Encodes a `xvseq.h` instruction (requires lasx). + pub inline fn @"xvseq.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74008000, p0, p1, p2); + } + + /// Encodes a `xvseq.w` instruction (requires lasx). + pub inline fn @"xvseq.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74010000, p0, p1, p2); + } + + /// Encodes a `xvseqi.b` instruction (requires lasx). + pub inline fn @"xvseqi.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76800000, p0, p1, p2); + } + + /// Encodes a `xvseqi.d` instruction (requires lasx). + pub inline fn @"xvseqi.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76818000, p0, p1, p2); + } + + /// Encodes a `xvseqi.h` instruction (requires lasx). + pub inline fn @"xvseqi.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76808000, p0, p1, p2); + } + + /// Encodes a `xvseqi.w` instruction (requires lasx). + pub inline fn @"xvseqi.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76810000, p0, p1, p2); + } + + /// Encodes a `xvsetallnez.b` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.b"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cb000, p0, p1); + } + + /// Encodes a `xvsetallnez.d` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.d"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cbc00, p0, p1); + } + + /// Encodes a `xvsetallnez.h` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.h"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cb400, p0, p1); + } + + /// Encodes a `xvsetallnez.w` instruction (requires f & lasx). + pub inline fn @"xvsetallnez.w"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cb800, p0, p1); + } + + /// Encodes a `xvsetanyeqz.b` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.b"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769ca000, p0, p1); + } + + /// Encodes a `xvsetanyeqz.d` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.d"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769cac00, p0, p1); + } + + /// Encodes a `xvsetanyeqz.h` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.h"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769ca400, p0, p1); + } + + /// Encodes a `xvsetanyeqz.w` instruction (requires f & lasx). + pub inline fn @"xvsetanyeqz.w"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769ca800, p0, p1); + } + + /// Encodes a `xvseteqz.v` instruction (requires f & lasx). + pub inline fn @"xvseteqz.v"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769c9800, p0, p1); + } + + /// Encodes a `xvsetnez.v` instruction (requires f & lasx). + pub inline fn @"xvsetnez.v"(p0: Register, p1: Register) Instruction { + return encodeCdXj(0x769c9c00, p0, p1); + } + + /// Encodes a `xvshuf.b` instruction (requires lasx). + pub inline fn @"xvshuf.b"(p0: Register, p1: Register, p2: Register, p3: Register) Instruction { + return encodeXdXjXkXa(0x0d600000, p0, p1, p2, p3); + } + + /// Encodes a `xvshuf.d` instruction (requires lasx). + pub inline fn @"xvshuf.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757b8000, p0, p1, p2); + } + + /// Encodes a `xvshuf.h` instruction (requires lasx). + pub inline fn @"xvshuf.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757a8000, p0, p1, p2); + } + + /// Encodes a `xvshuf.w` instruction (requires lasx). + pub inline fn @"xvshuf.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x757b0000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.b` instruction (requires lasx). + pub inline fn @"xvshuf4i.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77900000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.d` instruction (requires lasx). + pub inline fn @"xvshuf4i.d"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x779c0000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.h` instruction (requires lasx). + pub inline fn @"xvshuf4i.h"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77940000, p0, p1, p2); + } + + /// Encodes a `xvshuf4i.w` instruction (requires lasx). + pub inline fn @"xvshuf4i.w"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77980000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.b` instruction (requires lasx). + pub inline fn @"xvsigncov.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752e0000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.d` instruction (requires lasx). + pub inline fn @"xvsigncov.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752f8000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.h` instruction (requires lasx). + pub inline fn @"xvsigncov.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752e8000, p0, p1, p2); + } + + /// Encodes a `xvsigncov.w` instruction (requires lasx). + pub inline fn @"xvsigncov.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752f0000, p0, p1, p2); + } + + /// Encodes a `xvsle.b` instruction (requires lasx). + pub inline fn @"xvsle.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74020000, p0, p1, p2); + } + + /// Encodes a `xvsle.bu` instruction (requires lasx). + pub inline fn @"xvsle.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74040000, p0, p1, p2); + } + + /// Encodes a `xvsle.d` instruction (requires lasx). + pub inline fn @"xvsle.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74038000, p0, p1, p2); + } + + /// Encodes a `xvsle.du` instruction (requires lasx). + pub inline fn @"xvsle.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74058000, p0, p1, p2); + } + + /// Encodes a `xvsle.h` instruction (requires lasx). + pub inline fn @"xvsle.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74028000, p0, p1, p2); + } + + /// Encodes a `xvsle.hu` instruction (requires lasx). + pub inline fn @"xvsle.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74048000, p0, p1, p2); + } + + /// Encodes a `xvsle.w` instruction (requires lasx). + pub inline fn @"xvsle.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74030000, p0, p1, p2); + } + + /// Encodes a `xvsle.wu` instruction (requires lasx). + pub inline fn @"xvsle.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74050000, p0, p1, p2); + } + + /// Encodes a `xvslei.b` instruction (requires lasx). + pub inline fn @"xvslei.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76820000, p0, p1, p2); + } + + /// Encodes a `xvslei.bu` instruction (requires lasx). + pub inline fn @"xvslei.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76840000, p0, p1, p2); + } + + /// Encodes a `xvslei.d` instruction (requires lasx). + pub inline fn @"xvslei.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76838000, p0, p1, p2); + } + + /// Encodes a `xvslei.du` instruction (requires lasx). + pub inline fn @"xvslei.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76858000, p0, p1, p2); + } + + /// Encodes a `xvslei.h` instruction (requires lasx). + pub inline fn @"xvslei.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76828000, p0, p1, p2); + } + + /// Encodes a `xvslei.hu` instruction (requires lasx). + pub inline fn @"xvslei.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76848000, p0, p1, p2); + } + + /// Encodes a `xvslei.w` instruction (requires lasx). + pub inline fn @"xvslei.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76830000, p0, p1, p2); + } + + /// Encodes a `xvslei.wu` instruction (requires lasx). + pub inline fn @"xvslei.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76850000, p0, p1, p2); + } + + /// Encodes a `xvsll.b` instruction (requires lasx). + pub inline fn @"xvsll.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e80000, p0, p1, p2); + } + + /// Encodes a `xvsll.d` instruction (requires lasx). + pub inline fn @"xvsll.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e98000, p0, p1, p2); + } + + /// Encodes a `xvsll.h` instruction (requires lasx). + pub inline fn @"xvsll.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e88000, p0, p1, p2); + } + + /// Encodes a `xvsll.w` instruction (requires lasx). + pub inline fn @"xvsll.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74e90000, p0, p1, p2); + } + + /// Encodes a `xvslli.b` instruction (requires lasx). + pub inline fn @"xvslli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x772c2000, p0, p1, p2); + } + + /// Encodes a `xvslli.d` instruction (requires lasx). + pub inline fn @"xvslli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x772d0000, p0, p1, p2); + } + + /// Encodes a `xvslli.h` instruction (requires lasx). + pub inline fn @"xvslli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x772c4000, p0, p1, p2); + } + + /// Encodes a `xvslli.w` instruction (requires lasx). + pub inline fn @"xvslli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x772c8000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.d.w` instruction (requires lasx). + pub inline fn @"xvsllwil.d.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77088000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.du.wu` instruction (requires lasx). + pub inline fn @"xvsllwil.du.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x770c8000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.h.b` instruction (requires lasx). + pub inline fn @"xvsllwil.h.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77082000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.hu.bu` instruction (requires lasx). + pub inline fn @"xvsllwil.hu.bu"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x770c2000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.w.h` instruction (requires lasx). + pub inline fn @"xvsllwil.w.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77084000, p0, p1, p2); + } + + /// Encodes a `xvsllwil.wu.hu` instruction (requires lasx). + pub inline fn @"xvsllwil.wu.hu"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x770c4000, p0, p1, p2); + } + + /// Encodes a `xvslt.b` instruction (requires lasx). + pub inline fn @"xvslt.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74060000, p0, p1, p2); + } + + /// Encodes a `xvslt.bu` instruction (requires lasx). + pub inline fn @"xvslt.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74080000, p0, p1, p2); + } + + /// Encodes a `xvslt.d` instruction (requires lasx). + pub inline fn @"xvslt.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74078000, p0, p1, p2); + } + + /// Encodes a `xvslt.du` instruction (requires lasx). + pub inline fn @"xvslt.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74098000, p0, p1, p2); + } + + /// Encodes a `xvslt.h` instruction (requires lasx). + pub inline fn @"xvslt.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74068000, p0, p1, p2); + } + + /// Encodes a `xvslt.hu` instruction (requires lasx). + pub inline fn @"xvslt.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74088000, p0, p1, p2); + } + + /// Encodes a `xvslt.w` instruction (requires lasx). + pub inline fn @"xvslt.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74070000, p0, p1, p2); + } + + /// Encodes a `xvslt.wu` instruction (requires lasx). + pub inline fn @"xvslt.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74090000, p0, p1, p2); + } + + /// Encodes a `xvslti.b` instruction (requires lasx). + pub inline fn @"xvslti.b"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76860000, p0, p1, p2); + } + + /// Encodes a `xvslti.bu` instruction (requires lasx). + pub inline fn @"xvslti.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76880000, p0, p1, p2); + } + + /// Encodes a `xvslti.d` instruction (requires lasx). + pub inline fn @"xvslti.d"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76878000, p0, p1, p2); + } + + /// Encodes a `xvslti.du` instruction (requires lasx). + pub inline fn @"xvslti.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76898000, p0, p1, p2); + } + + /// Encodes a `xvslti.h` instruction (requires lasx). + pub inline fn @"xvslti.h"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76868000, p0, p1, p2); + } + + /// Encodes a `xvslti.hu` instruction (requires lasx). + pub inline fn @"xvslti.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76888000, p0, p1, p2); + } + + /// Encodes a `xvslti.w` instruction (requires lasx). + pub inline fn @"xvslti.w"(p0: Register, p1: Register, p2: i5) Instruction { + return encodeXdXjSk5(0x76870000, p0, p1, p2); + } + + /// Encodes a `xvslti.wu` instruction (requires lasx). + pub inline fn @"xvslti.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76890000, p0, p1, p2); + } + + /// Encodes a `xvsra.b` instruction (requires lasx). + pub inline fn @"xvsra.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ec0000, p0, p1, p2); + } + + /// Encodes a `xvsra.d` instruction (requires lasx). + pub inline fn @"xvsra.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ed8000, p0, p1, p2); + } + + /// Encodes a `xvsra.h` instruction (requires lasx). + pub inline fn @"xvsra.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ec8000, p0, p1, p2); + } + + /// Encodes a `xvsra.w` instruction (requires lasx). + pub inline fn @"xvsra.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ed0000, p0, p1, p2); + } + + /// Encodes a `xvsrai.b` instruction (requires lasx). + pub inline fn @"xvsrai.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77342000, p0, p1, p2); + } + + /// Encodes a `xvsrai.d` instruction (requires lasx). + pub inline fn @"xvsrai.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77350000, p0, p1, p2); + } + + /// Encodes a `xvsrai.h` instruction (requires lasx). + pub inline fn @"xvsrai.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77344000, p0, p1, p2); + } + + /// Encodes a `xvsrai.w` instruction (requires lasx). + pub inline fn @"xvsrai.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77348000, p0, p1, p2); + } + + /// Encodes a `xvsran.b.h` instruction (requires lasx). + pub inline fn @"xvsran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f68000, p0, p1, p2); + } + + /// Encodes a `xvsran.h.w` instruction (requires lasx). + pub inline fn @"xvsran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f70000, p0, p1, p2); + } + + /// Encodes a `xvsran.w.d` instruction (requires lasx). + pub inline fn @"xvsran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f78000, p0, p1, p2); + } + + /// Encodes a `xvsrani.b.h` instruction (requires lasx). + pub inline fn @"xvsrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77584000, p0, p1, p2); + } + + /// Encodes a `xvsrani.d.q` instruction (requires lasx). + pub inline fn @"xvsrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x775a0000, p0, p1, p2); + } + + /// Encodes a `xvsrani.h.w` instruction (requires lasx). + pub inline fn @"xvsrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77588000, p0, p1, p2); + } + + /// Encodes a `xvsrani.w.d` instruction (requires lasx). + pub inline fn @"xvsrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77590000, p0, p1, p2); + } + + /// Encodes a `xvsrar.b` instruction (requires lasx). + pub inline fn @"xvsrar.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f20000, p0, p1, p2); + } + + /// Encodes a `xvsrar.d` instruction (requires lasx). + pub inline fn @"xvsrar.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f38000, p0, p1, p2); + } + + /// Encodes a `xvsrar.h` instruction (requires lasx). + pub inline fn @"xvsrar.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f28000, p0, p1, p2); + } + + /// Encodes a `xvsrar.w` instruction (requires lasx). + pub inline fn @"xvsrar.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f30000, p0, p1, p2); + } + + /// Encodes a `xvsrari.b` instruction (requires lasx). + pub inline fn @"xvsrari.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76a82000, p0, p1, p2); + } + + /// Encodes a `xvsrari.d` instruction (requires lasx). + pub inline fn @"xvsrari.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x76a90000, p0, p1, p2); + } + + /// Encodes a `xvsrari.h` instruction (requires lasx). + pub inline fn @"xvsrari.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76a84000, p0, p1, p2); + } + + /// Encodes a `xvsrari.w` instruction (requires lasx). + pub inline fn @"xvsrari.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76a88000, p0, p1, p2); + } + + /// Encodes a `xvsrarn.b.h` instruction (requires lasx). + pub inline fn @"xvsrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fa8000, p0, p1, p2); + } + + /// Encodes a `xvsrarn.h.w` instruction (requires lasx). + pub inline fn @"xvsrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fb0000, p0, p1, p2); + } + + /// Encodes a `xvsrarn.w.d` instruction (requires lasx). + pub inline fn @"xvsrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fb8000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.b.h` instruction (requires lasx). + pub inline fn @"xvsrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x775c4000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.d.q` instruction (requires lasx). + pub inline fn @"xvsrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x775e0000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.h.w` instruction (requires lasx). + pub inline fn @"xvsrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x775c8000, p0, p1, p2); + } + + /// Encodes a `xvsrarni.w.d` instruction (requires lasx). + pub inline fn @"xvsrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x775d0000, p0, p1, p2); + } + + /// Encodes a `xvsrl.b` instruction (requires lasx). + pub inline fn @"xvsrl.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ea0000, p0, p1, p2); + } + + /// Encodes a `xvsrl.d` instruction (requires lasx). + pub inline fn @"xvsrl.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74eb8000, p0, p1, p2); + } + + /// Encodes a `xvsrl.h` instruction (requires lasx). + pub inline fn @"xvsrl.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ea8000, p0, p1, p2); + } + + /// Encodes a `xvsrl.w` instruction (requires lasx). + pub inline fn @"xvsrl.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74eb0000, p0, p1, p2); + } + + /// Encodes a `xvsrli.b` instruction (requires lasx). + pub inline fn @"xvsrli.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x77302000, p0, p1, p2); + } + + /// Encodes a `xvsrli.d` instruction (requires lasx). + pub inline fn @"xvsrli.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77310000, p0, p1, p2); + } + + /// Encodes a `xvsrli.h` instruction (requires lasx). + pub inline fn @"xvsrli.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77304000, p0, p1, p2); + } + + /// Encodes a `xvsrli.w` instruction (requires lasx). + pub inline fn @"xvsrli.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77308000, p0, p1, p2); + } + + /// Encodes a `xvsrln.b.h` instruction (requires lasx). + pub inline fn @"xvsrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f48000, p0, p1, p2); + } + + /// Encodes a `xvsrln.h.w` instruction (requires lasx). + pub inline fn @"xvsrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f50000, p0, p1, p2); + } + + /// Encodes a `xvsrln.w.d` instruction (requires lasx). + pub inline fn @"xvsrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f58000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.b.h` instruction (requires lasx). + pub inline fn @"xvsrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77404000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.d.q` instruction (requires lasx). + pub inline fn @"xvsrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77420000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.h.w` instruction (requires lasx). + pub inline fn @"xvsrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77408000, p0, p1, p2); + } + + /// Encodes a `xvsrlni.w.d` instruction (requires lasx). + pub inline fn @"xvsrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77410000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.b` instruction (requires lasx). + pub inline fn @"xvsrlr.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f00000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.d` instruction (requires lasx). + pub inline fn @"xvsrlr.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f18000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.h` instruction (requires lasx). + pub inline fn @"xvsrlr.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f08000, p0, p1, p2); + } + + /// Encodes a `xvsrlr.w` instruction (requires lasx). + pub inline fn @"xvsrlr.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f10000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.b` instruction (requires lasx). + pub inline fn @"xvsrlri.b"(p0: Register, p1: Register, p2: u3) Instruction { + return encodeXdXjUk3(0x76a42000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.d` instruction (requires lasx). + pub inline fn @"xvsrlri.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x76a50000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.h` instruction (requires lasx). + pub inline fn @"xvsrlri.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x76a44000, p0, p1, p2); + } + + /// Encodes a `xvsrlri.w` instruction (requires lasx). + pub inline fn @"xvsrlri.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x76a48000, p0, p1, p2); + } + + /// Encodes a `xvsrlrn.b.h` instruction (requires lasx). + pub inline fn @"xvsrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f88000, p0, p1, p2); + } + + /// Encodes a `xvsrlrn.h.w` instruction (requires lasx). + pub inline fn @"xvsrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f90000, p0, p1, p2); + } + + /// Encodes a `xvsrlrn.w.d` instruction (requires lasx). + pub inline fn @"xvsrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74f98000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.b.h` instruction (requires lasx). + pub inline fn @"xvsrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77444000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.d.q` instruction (requires lasx). + pub inline fn @"xvsrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77460000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.h.w` instruction (requires lasx). + pub inline fn @"xvsrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77448000, p0, p1, p2); + } + + /// Encodes a `xvsrlrni.w.d` instruction (requires lasx). + pub inline fn @"xvsrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77450000, p0, p1, p2); + } + + /// Encodes a `xvssran.b.h` instruction (requires lasx). + pub inline fn @"xvssran.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fe8000, p0, p1, p2); + } + + /// Encodes a `xvssran.bu.h` instruction (requires lasx). + pub inline fn @"xvssran.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75068000, p0, p1, p2); + } + + /// Encodes a `xvssran.h.w` instruction (requires lasx). + pub inline fn @"xvssran.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ff0000, p0, p1, p2); + } + + /// Encodes a `xvssran.hu.w` instruction (requires lasx). + pub inline fn @"xvssran.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75070000, p0, p1, p2); + } + + /// Encodes a `xvssran.w.d` instruction (requires lasx). + pub inline fn @"xvssran.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74ff8000, p0, p1, p2); + } + + /// Encodes a `xvssran.wu.d` instruction (requires lasx). + pub inline fn @"xvssran.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75078000, p0, p1, p2); + } + + /// Encodes a `xvssrani.b.h` instruction (requires lasx). + pub inline fn @"xvssrani.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77604000, p0, p1, p2); + } + + /// Encodes a `xvssrani.bu.h` instruction (requires lasx). + pub inline fn @"xvssrani.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77644000, p0, p1, p2); + } + + /// Encodes a `xvssrani.d.q` instruction (requires lasx). + pub inline fn @"xvssrani.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77620000, p0, p1, p2); + } + + /// Encodes a `xvssrani.du.q` instruction (requires lasx). + pub inline fn @"xvssrani.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77660000, p0, p1, p2); + } + + /// Encodes a `xvssrani.h.w` instruction (requires lasx). + pub inline fn @"xvssrani.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77608000, p0, p1, p2); + } + + /// Encodes a `xvssrani.hu.w` instruction (requires lasx). + pub inline fn @"xvssrani.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77648000, p0, p1, p2); + } + + /// Encodes a `xvssrani.w.d` instruction (requires lasx). + pub inline fn @"xvssrani.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77610000, p0, p1, p2); + } + + /// Encodes a `xvssrani.wu.d` instruction (requires lasx). + pub inline fn @"xvssrani.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77650000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.b.h` instruction (requires lasx). + pub inline fn @"xvssrarn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75028000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.bu.h` instruction (requires lasx). + pub inline fn @"xvssrarn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750a8000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.h.w` instruction (requires lasx). + pub inline fn @"xvssrarn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75030000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.hu.w` instruction (requires lasx). + pub inline fn @"xvssrarn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750b0000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.w.d` instruction (requires lasx). + pub inline fn @"xvssrarn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75038000, p0, p1, p2); + } + + /// Encodes a `xvssrarn.wu.d` instruction (requires lasx). + pub inline fn @"xvssrarn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x750b8000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.b.h` instruction (requires lasx). + pub inline fn @"xvssrarni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77684000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.bu.h` instruction (requires lasx). + pub inline fn @"xvssrarni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x776c4000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.d.q` instruction (requires lasx). + pub inline fn @"xvssrarni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x776a0000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.du.q` instruction (requires lasx). + pub inline fn @"xvssrarni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x776e0000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.h.w` instruction (requires lasx). + pub inline fn @"xvssrarni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77688000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.hu.w` instruction (requires lasx). + pub inline fn @"xvssrarni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x776c8000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.w.d` instruction (requires lasx). + pub inline fn @"xvssrarni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77690000, p0, p1, p2); + } + + /// Encodes a `xvssrarni.wu.d` instruction (requires lasx). + pub inline fn @"xvssrarni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x776d0000, p0, p1, p2); + } + + /// Encodes a `xvssrln.b.h` instruction (requires lasx). + pub inline fn @"xvssrln.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fc8000, p0, p1, p2); + } + + /// Encodes a `xvssrln.bu.h` instruction (requires lasx). + pub inline fn @"xvssrln.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75048000, p0, p1, p2); + } + + /// Encodes a `xvssrln.h.w` instruction (requires lasx). + pub inline fn @"xvssrln.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fd0000, p0, p1, p2); + } + + /// Encodes a `xvssrln.hu.w` instruction (requires lasx). + pub inline fn @"xvssrln.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75050000, p0, p1, p2); + } + + /// Encodes a `xvssrln.w.d` instruction (requires lasx). + pub inline fn @"xvssrln.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74fd8000, p0, p1, p2); + } + + /// Encodes a `xvssrln.wu.d` instruction (requires lasx). + pub inline fn @"xvssrln.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75058000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.b.h` instruction (requires lasx). + pub inline fn @"xvssrlni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77484000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.bu.h` instruction (requires lasx). + pub inline fn @"xvssrlni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x774c4000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.d.q` instruction (requires lasx). + pub inline fn @"xvssrlni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x774a0000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.du.q` instruction (requires lasx). + pub inline fn @"xvssrlni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x774e0000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.h.w` instruction (requires lasx). + pub inline fn @"xvssrlni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77488000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.hu.w` instruction (requires lasx). + pub inline fn @"xvssrlni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x774c8000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.w.d` instruction (requires lasx). + pub inline fn @"xvssrlni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77490000, p0, p1, p2); + } + + /// Encodes a `xvssrlni.wu.d` instruction (requires lasx). + pub inline fn @"xvssrlni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x774d0000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.b.h` instruction (requires lasx). + pub inline fn @"xvssrlrn.b.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75008000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.bu.h` instruction (requires lasx). + pub inline fn @"xvssrlrn.bu.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75088000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.h.w` instruction (requires lasx). + pub inline fn @"xvssrlrn.h.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75010000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.hu.w` instruction (requires lasx). + pub inline fn @"xvssrlrn.hu.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75090000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.w.d` instruction (requires lasx). + pub inline fn @"xvssrlrn.w.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75018000, p0, p1, p2); + } + + /// Encodes a `xvssrlrn.wu.d` instruction (requires lasx). + pub inline fn @"xvssrlrn.wu.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75098000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.b.h` instruction (requires lasx). + pub inline fn @"xvssrlrni.b.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77504000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.bu.h` instruction (requires lasx). + pub inline fn @"xvssrlrni.bu.h"(p0: Register, p1: Register, p2: u4) Instruction { + return encodeXdXjUk4(0x77544000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.d.q` instruction (requires lasx). + pub inline fn @"xvssrlrni.d.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77520000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.du.q` instruction (requires lasx). + pub inline fn @"xvssrlrni.du.q"(p0: Register, p1: Register, p2: u7) Instruction { + return encodeXdXjUk7(0x77560000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.h.w` instruction (requires lasx). + pub inline fn @"xvssrlrni.h.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77508000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.hu.w` instruction (requires lasx). + pub inline fn @"xvssrlrni.hu.w"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x77548000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.w.d` instruction (requires lasx). + pub inline fn @"xvssrlrni.w.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77510000, p0, p1, p2); + } + + /// Encodes a `xvssrlrni.wu.d` instruction (requires lasx). + pub inline fn @"xvssrlrni.wu.d"(p0: Register, p1: Register, p2: u6) Instruction { + return encodeXdXjUk6(0x77550000, p0, p1, p2); + } + + /// Encodes a `xvssub.b` instruction (requires lasx). + pub inline fn @"xvssub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74480000, p0, p1, p2); + } + + /// Encodes a `xvssub.bu` instruction (requires lasx). + pub inline fn @"xvssub.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744c0000, p0, p1, p2); + } + + /// Encodes a `xvssub.d` instruction (requires lasx). + pub inline fn @"xvssub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74498000, p0, p1, p2); + } + + /// Encodes a `xvssub.du` instruction (requires lasx). + pub inline fn @"xvssub.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744d8000, p0, p1, p2); + } + + /// Encodes a `xvssub.h` instruction (requires lasx). + pub inline fn @"xvssub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74488000, p0, p1, p2); + } + + /// Encodes a `xvssub.hu` instruction (requires lasx). + pub inline fn @"xvssub.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744c8000, p0, p1, p2); + } + + /// Encodes a `xvssub.w` instruction (requires lasx). + pub inline fn @"xvssub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74490000, p0, p1, p2); + } + + /// Encodes a `xvssub.wu` instruction (requires lasx). + pub inline fn @"xvssub.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x744d0000, p0, p1, p2); + } + + /// Encodes a `xvst` instruction (requires lasx). + pub inline fn xvst(p0: Register, p1: Register, p2: i12) Instruction { + return encodeXdJSk12(0x2cc00000, p0, p1, p2); + } + + /// Encodes a `xvstelm.b` instruction (requires lasx). + pub inline fn @"xvstelm.b"(p0: Register, p1: Register, p2: i8, p3: u5) Instruction { + return encodeXdJSk8Un5(0x33800000, p0, p1, p2, p3); + } + + /// Encodes a `xvstelm.d` instruction (requires lasx). + pub inline fn @"xvstelm.d"(p0: Register, p1: Register, p2: i8, p3: u2) Instruction { + return encodeXdJSk8ps3Un2(0x33100000, p0, p1, p2, p3); + } + + /// Encodes a `xvstelm.h` instruction (requires lasx). + pub inline fn @"xvstelm.h"(p0: Register, p1: Register, p2: i8, p3: u4) Instruction { + return encodeXdJSk8ps1Un4(0x33400000, p0, p1, p2, p3); + } + + /// Encodes a `xvstelm.w` instruction (requires lasx). + pub inline fn @"xvstelm.w"(p0: Register, p1: Register, p2: i8, p3: u3) Instruction { + return encodeXdJSk8ps2Un3(0x33200000, p0, p1, p2, p3); + } + + /// Encodes a `xvstx` instruction (requires lasx). + pub inline fn xvstx(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdJK(0x384c0000, p0, p1, p2); + } + + /// Encodes a `xvsub.b` instruction (requires lasx). + pub inline fn @"xvsub.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740c0000, p0, p1, p2); + } + + /// Encodes a `xvsub.d` instruction (requires lasx). + pub inline fn @"xvsub.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740d8000, p0, p1, p2); + } + + /// Encodes a `xvsub.h` instruction (requires lasx). + pub inline fn @"xvsub.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740c8000, p0, p1, p2); + } + + /// Encodes a `xvsub.q` instruction (requires lasx). + pub inline fn @"xvsub.q"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x752d8000, p0, p1, p2); + } + + /// Encodes a `xvsub.w` instruction (requires lasx). + pub inline fn @"xvsub.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x740d0000, p0, p1, p2); + } + + /// Encodes a `xvsubi.bu` instruction (requires lasx). + pub inline fn @"xvsubi.bu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768c0000, p0, p1, p2); + } + + /// Encodes a `xvsubi.du` instruction (requires lasx). + pub inline fn @"xvsubi.du"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768d8000, p0, p1, p2); + } + + /// Encodes a `xvsubi.hu` instruction (requires lasx). + pub inline fn @"xvsubi.hu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768c8000, p0, p1, p2); + } + + /// Encodes a `xvsubi.wu` instruction (requires lasx). + pub inline fn @"xvsubi.wu"(p0: Register, p1: Register, p2: u5) Instruction { + return encodeXdXjUk5(0x768d0000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.d.w` instruction (requires lasx). + pub inline fn @"xvsubwev.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74210000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.d.wu` instruction (requires lasx). + pub inline fn @"xvsubwev.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74310000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.h.b` instruction (requires lasx). + pub inline fn @"xvsubwev.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74200000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.h.bu` instruction (requires lasx). + pub inline fn @"xvsubwev.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74300000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.q.d` instruction (requires lasx). + pub inline fn @"xvsubwev.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74218000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.q.du` instruction (requires lasx). + pub inline fn @"xvsubwev.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74318000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.w.h` instruction (requires lasx). + pub inline fn @"xvsubwev.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74208000, p0, p1, p2); + } + + /// Encodes a `xvsubwev.w.hu` instruction (requires lasx). + pub inline fn @"xvsubwev.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74308000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.d.w` instruction (requires lasx). + pub inline fn @"xvsubwod.d.w"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74250000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.d.wu` instruction (requires lasx). + pub inline fn @"xvsubwod.d.wu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74350000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.h.b` instruction (requires lasx). + pub inline fn @"xvsubwod.h.b"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74240000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.h.bu` instruction (requires lasx). + pub inline fn @"xvsubwod.h.bu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74340000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.q.d` instruction (requires lasx). + pub inline fn @"xvsubwod.q.d"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74258000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.q.du` instruction (requires lasx). + pub inline fn @"xvsubwod.q.du"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74358000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.w.h` instruction (requires lasx). + pub inline fn @"xvsubwod.w.h"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74248000, p0, p1, p2); + } + + /// Encodes a `xvsubwod.w.hu` instruction (requires lasx). + pub inline fn @"xvsubwod.w.hu"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x74348000, p0, p1, p2); + } + + /// Encodes a `xvxor.v` instruction (requires lasx). + pub inline fn @"xvxor.v"(p0: Register, p1: Register, p2: Register) Instruction { + return encodeXdXjXk(0x75270000, p0, p1, p2); + } + + /// Encodes a `xvxori.b` instruction (requires lasx). + pub inline fn @"xvxori.b"(p0: Register, p1: Register, p2: u8) Instruction { + return encodeXdXjUk8(0x77d80000, p0, p1, p2); + } + + /// Encodes a `xxx.unknown.1` instruction (requires 64bit). + pub inline fn @"xxx.unknown.1"() Instruction { + return encodeEMPTY(0x06493000); + } +}; diff --git a/src/codegen/loongarch/inst_formats.zon b/src/codegen/loongarch/inst_formats.zon new file mode 100644 index 0000000000000000000000000000000000000000..78ba4dd6ad38c6fc7b800082fd3f91230f7c3f7b --- /dev/null +++ b/src/codegen/loongarch/inst_formats.zon @@ -0,0 +1,11059 @@ +// DO NOT MODIFY. This file is generated by tools/gen_loongarch_encoding.zig. +.{ + .instructions = .{ + .@"adc.b" = .{ + .word = 0x00300000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"adc.d" = .{ + .word = 0x00318000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"adc.h" = .{ + .word = 0x00308000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"adc.w" = .{ + .word = 0x00310000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"add.d" = .{ + .word = 0x00108000, + .format = .DJK, + .features = .{.@"64bit"}, + }, + .@"add.w" = .{ + .word = 0x00100000, + .format = .DJK, + .features = .{.@"32bit"}, + }, + .@"addi.d" = .{ + .word = 0x02c00000, + .format = .DJSk12, + .features = .{.@"64bit"}, + }, + .@"addi.w" = .{ + .word = 0x02800000, + .format = .DJSk12, + .features = .{.@"32bit"}, + }, + .@"addu12i.d" = .{ + .word = 0x00298000, + .format = .DJSk5, + .features = .{.@"64bit"}, + }, + .@"addu12i.w" = .{ + .word = 0x00290000, + .format = .DJSk5, + .features = .{.@"64bit"}, + }, + .@"addu16i.d" = .{ + .word = 0x10000000, + .format = .DJSk16, + .features = .{.@"64bit"}, + }, + .@"amadd.b" = .{ + .word = 0x385d0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd.d" = .{ + .word = 0x38618000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd.h" = .{ + .word = 0x385d8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd.w" = .{ + .word = 0x38610000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.b" = .{ + .word = 0x385f0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.d" = .{ + .word = 0x386a8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.h" = .{ + .word = 0x385f8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amadd_db.w" = .{ + .word = 0x386a0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand.d" = .{ + .word = 0x38628000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand.w" = .{ + .word = 0x38620000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand_db.d" = .{ + .word = 0x386b8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amand_db.w" = .{ + .word = 0x386b0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.b" = .{ + .word = 0x38580000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.d" = .{ + .word = 0x38598000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.h" = .{ + .word = 0x38588000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas.w" = .{ + .word = 0x38590000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.b" = .{ + .word = 0x385a0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.d" = .{ + .word = 0x385b8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.h" = .{ + .word = 0x385a8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amcas_db.w" = .{ + .word = 0x385b0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.d" = .{ + .word = 0x38658000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.du" = .{ + .word = 0x38678000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.w" = .{ + .word = 0x38650000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax.wu" = .{ + .word = 0x38670000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.d" = .{ + .word = 0x386e8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.du" = .{ + .word = 0x38708000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.w" = .{ + .word = 0x386e0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammax_db.wu" = .{ + .word = 0x38700000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.d" = .{ + .word = 0x38668000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.du" = .{ + .word = 0x38688000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.w" = .{ + .word = 0x38660000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin.wu" = .{ + .word = 0x38680000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.d" = .{ + .word = 0x386f8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.du" = .{ + .word = 0x38718000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.w" = .{ + .word = 0x386f0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"ammin_db.wu" = .{ + .word = 0x38710000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor.d" = .{ + .word = 0x38638000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor.w" = .{ + .word = 0x38630000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor_db.d" = .{ + .word = 0x386c8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amor_db.w" = .{ + .word = 0x386c0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.b" = .{ + .word = 0x385c0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.d" = .{ + .word = 0x38608000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.h" = .{ + .word = 0x385c8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap.w" = .{ + .word = 0x38600000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.b" = .{ + .word = 0x385e0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.d" = .{ + .word = 0x38698000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.h" = .{ + .word = 0x385e8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amswap_db.w" = .{ + .word = 0x38690000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor.d" = .{ + .word = 0x38648000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor.w" = .{ + .word = 0x38640000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor_db.d" = .{ + .word = 0x386d8000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"amxor_db.w" = .{ + .word = 0x386d0000, + .format = .DJK, + .orig_format = .DKJ, + .features = .{.@"64bit"}, + }, + .@"and" = .{ + .word = 0x00148000, + .format = .DJK, + .features = .{.@"32bit"}, + }, + .andi = .{ + .word = 0x03400000, + .format = .DJUk12, + .features = .{.@"32bit"}, + }, + .andn = .{ + .word = 0x00168000, + .format = .DJK, + .features = .{.@"32bit"}, + }, + .@"armadc.w" = .{ + .word = 0x00380010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armadd.w" = .{ + .word = 0x00370010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armand.w" = .{ + .word = 0x00390010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .armmfflag = .{ + .word = 0x005c0040, + .format = .DUk8, + .features = .{.@"64bit"}, + }, + .@"armmov.d" = .{ + .word = 0x003fc01e, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .@"armmov.w" = .{ + .word = 0x003fc01d, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .armmove = .{ + .word = 0x00364000, + .format = .DJUk4, + .features = .{.@"64bit"}, + }, + .armmtflag = .{ + .word = 0x005c0060, + .format = .DUk8, + .features = .{.@"64bit"}, + }, + .@"armnot.w" = .{ + .word = 0x003fc01c, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .@"armor.w" = .{ + .word = 0x00398010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armrotr.w" = .{ + .word = 0x003c0010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .@"armrotri.w" = .{ + .word = 0x003e0010, + .format = .JUd4Uk5, + .orig_format = .JUk5Ud4, + .features = .{.@"64bit"}, + }, + .@"armrrx.w" = .{ + .word = 0x003fc01f, + .format = .JUk4, + .features = .{.@"64bit"}, + }, + .@"armsbc.w" = .{ + .word = 0x00388010, + .format = .JKUd4, + .features = .{.@"64bit"}, + }, + .armsetj = .{ + .word = 0x0036c000, + .format = .DUk4, + .orig_name = "setarmj", + .features = .{.@"64bit"}, + }, + .@"armsll.w" = .{ + .word = 0x003a8010, + .format = .JKUd4, + .features = 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.{.lasx}, + }, + .@"xvxor.v" = .{ + .word = 0x75270000, + .format = .XdXjXk, + .features = .{.lasx}, + }, + .@"xvxori.b" = .{ + .word = 0x77d80000, + .format = .XdXjUk8, + .features = .{.lasx}, + }, + .@"xxx.unknown.1" = .{ + .word = 0x06493000, + .format = .EMPTY, + .features = .{.@"64bit"}, + }, + }, + .formats = .{ + .CdFj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fcc } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + } }, + .CdFjFk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fcc } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + } }, + .CdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fcc } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .CdVj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fcc } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + } }, + .CdXj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fcc } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + } }, + .CjSd5k16 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .fcc } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .CjSd5k16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .fcc } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .D = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + } }, + .DCj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .fcc } }, + } }, + .DFj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + } }, + .DJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .DJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .DJKUa2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 15, .length = 2, .signedness = .unsigned } }, + } }, + .DJKUa2pp1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 15, .length = 2, .signedness = .unsigned, .post_proc = .{ .add = 1 } } }, + } }, + .DJKUa3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 15, .length = 3, .signedness = .unsigned } }, + } }, + .DJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .DJSk14 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .signed } }, + } }, + .DJSk14ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .DJSk16 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .DJSk16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .DJSk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } }, + } }, + .DJUk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .unsigned } }, + } }, + .DJUk14 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .unsigned } }, + } }, + .DJUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .DJUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .DJUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .DJUk5Um5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 16, .length = 5, .signedness = .unsigned } }, + } }, + .DJUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .DJUk6Um6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + .{ .imm = .{ .location = 16, .length = 6, .signedness = .unsigned } }, + } }, + .DJUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .DJUm5Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 16, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .DJUm6Uk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 16, .length = 6, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .DKJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .DSj20 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 5, .length = 20, .signedness = .signed } }, + } }, + .DTj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lbt_scratch } }, + } }, + .DUj5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + } }, + .DUj5Uk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .DUk14 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 14, .signedness = .unsigned } }, + } }, + .DUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .DUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .DVjUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .DVjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .DVjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .DVjUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .DXjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .DXjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .EMPTY = .{ .slots = .{} }, + .FdCj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fcc } }, + } }, + .FdFj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + } }, + .FdFjFk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + } }, + .FdFjFkCa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + .{ .reg = .{ .location = 15, .class = .fcc } }, + } }, + .FdFjFkFa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .fp } }, + .{ .reg = .{ .location = 10, .class = .fp } }, + .{ .reg = .{ .location = 15, .class = .fp } }, + } }, + .FdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .FdJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .FdJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .fp } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .J = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .JDSk16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 0, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .JK = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .JKUd4 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } }, + } }, + .JKUd5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + } }, + .JSd5k16 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .JSd5k16ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .JUd4Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .JUd5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + } }, + .JUd5Sk12 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .JUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .JUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .JUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .JUk5Ud4 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 0, .length = 4, .signedness = .unsigned } }, + } }, + .JUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .JUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .Sd10k16 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 10, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .Sd10k16ps2 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 10, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .Sd5k16 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed } }, + } }, + .Sd5k16ps2 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .signed } }, + .{ .imm = .{ .location = 10, .length = 16, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .TdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lbt_scratch } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .Ud15 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 15, .signedness = .unsigned } }, + } }, + .Ud5JK = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .Ud5JSk12 = .{ .slots = .{ + .{ .imm = .{ .location = 0, .length = 5, .signedness = .unsigned } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .Uj3 = .{ .slots = .{ + .{ .imm = .{ .location = 5, .length = 3, .signedness = .unsigned } }, + } }, + .VdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .VdJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .VdJSk10 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed } }, + } }, + .VdJSk10ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .VdJSk11 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed } }, + } }, + .VdJSk11ps1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + } }, + .VdJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .VdJSk8Un1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 1, .signedness = .unsigned } }, + } }, + .VdJSk8Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .VdJSk8Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .VdJSk8Un4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } }, + } }, + .VdJSk8ps1Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .VdJSk8ps2Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .VdJSk8ps3Un1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + .{ .imm = .{ .location = 18, .length = 1, .signedness = .unsigned } }, + } }, + .VdJSk9 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed } }, + } }, + .VdJSk9ps3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + } }, + .VdJUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .VdJUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .VdJUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .VdJUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .VdSj13 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .imm = .{ .location = 5, .length = 13, .signedness = .signed } }, + } }, + .VdUj5Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .VdVj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + } }, + .VdVjK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .VdVjSk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } }, + } }, + .VdVjUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .VdVjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .VdVjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .VdVjUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .VdVjUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .VdVjUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .VdVjUk7 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 7, .signedness = .unsigned } }, + } }, + .VdVjUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .VdVjVk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .reg = .{ .location = 10, .class = .lsx } }, + } }, + .VdVjVkVa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lsx } }, + .{ .reg = .{ .location = 5, .class = .lsx } }, + .{ .reg = .{ .location = 10, .class = .lsx } }, + .{ .reg = .{ .location = 15, .class = .lsx } }, + } }, + .XdJ = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + } }, + .XdJK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .XdJSk10 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed } }, + } }, + .XdJSk10ps2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 10, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + } }, + .XdJSk11 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed } }, + } }, + .XdJSk11ps1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 11, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + } }, + .XdJSk12 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 12, .signedness = .signed } }, + } }, + .XdJSk8Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .XdJSk8Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .XdJSk8Un4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } }, + } }, + .XdJSk8Un5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed } }, + .{ .imm = .{ .location = 18, .length = 5, .signedness = .unsigned } }, + } }, + .XdJSk8ps1Un4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 1 } } }, + .{ .imm = .{ .location = 18, .length = 4, .signedness = .unsigned } }, + } }, + .XdJSk8ps2Un3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 2 } } }, + .{ .imm = .{ .location = 18, .length = 3, .signedness = .unsigned } }, + } }, + .XdJSk8ps3Un2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + .{ .imm = .{ .location = 18, .length = 2, .signedness = .unsigned } }, + } }, + .XdJSk9 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed } }, + } }, + .XdJSk9ps3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 9, .signedness = .signed, .post_proc = .{ .shl = 3 } } }, + } }, + .XdJUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .XdJUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .int } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .XdSj13 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .imm = .{ .location = 5, .length = 13, .signedness = .signed } }, + } }, + .XdUj5Uk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .imm = .{ .location = 5, .length = 5, .signedness = .unsigned } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .XdXj = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + } }, + .XdXjK = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .reg = .{ .location = 10, .class = .int } }, + } }, + .XdXjSk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .signed } }, + } }, + .XdXjUk1 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 1, .signedness = .unsigned } }, + } }, + .XdXjUk2 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 2, .signedness = .unsigned } }, + } }, + .XdXjUk3 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 3, .signedness = .unsigned } }, + } }, + .XdXjUk4 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 4, .signedness = .unsigned } }, + } }, + .XdXjUk5 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 5, .signedness = .unsigned } }, + } }, + .XdXjUk6 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 6, .signedness = .unsigned } }, + } }, + .XdXjUk7 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 7, .signedness = .unsigned } }, + } }, + .XdXjUk8 = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .imm = .{ .location = 10, .length = 8, .signedness = .unsigned } }, + } }, + .XdXjXk = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .reg = .{ .location = 10, .class = .lasx } }, + } }, + .XdXjXkXa = .{ .slots = .{ + .{ .reg = .{ .location = 0, .class = .lasx } }, + .{ .reg = .{ .location = 5, .class = .lasx } }, + .{ .reg = .{ .location = 10, .class = .lasx } }, + .{ .reg = .{ .location = 15, .class = .lasx } }, + } }, + }, +}