diff --git a/lib/compiler/aro/aro/Compilation.zig b/lib/compiler/aro/aro/Compilation.zig index 932b09a088a70e91a7838d5e75ad3be0ba174833..507157d05b14652c68a6f94ff2c38662e852c01e 100644 --- a/lib/compiler/aro/aro/Compilation.zig +++ b/lib/compiler/aro/aro/Compilation.zig @@ -560,7 +560,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { .{ .amx_fp8, "__AMX_FP8__" }, .{ .amx_movrs, "__AMX_MOVRS__" }, .{ .amx_avx512, "__AMX_AVX512__" }, - .{ .amx_tf32, "__AMX_TF32__" }, .{ .cmpccxadd, "__CMPCCXADD__" }, .{ .raoint, "__RAOINT__" }, .{ .avxifma, "__AVXIFMA__" }, diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 62a6a61edafb4339db2e67ab5c62650f8ce26a27..d8cdb78494409d5e810a62485c887b0f056217cb 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1238,7 +1238,7 @@ pub const Cpu = struct { pub const Set = struct { ints: [usize_count]usize, - pub const needed_bit_count = 347; + pub const needed_bit_count = 378; pub const byte_count = @divCeil(needed_bit_count, 8); pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize); pub const Index = std.math.Log2Int(@Int(.unsigned, usize_count * @bitSizeOf(usize))); diff --git a/lib/std/Target/aarch64.zig b/lib/std/Target/aarch64.zig index eb02c7d17ab450361a359d99bc146c1e1d0ae4d5..6cf169bd76b7efc3378899b125603930dbef8f10 100644 --- a/lib/std/Target/aarch64.zig +++ b/lib/std/Target/aarch64.zig @@ -10,6 +10,7 @@ pub const Feature = enum { aes, aggressive_fma, aggressive_interleaving, + align_cmp_csel_pairs, alternate_sextload_cvt_f32_pattern, altnzcv, alu_lsl_fast, @@ -38,7 +39,6 @@ pub const Feature = enum { ccpp, chk, clrbhb, - cmh, cmp_bcc_fusion, cmpbr, complxnum, @@ -48,6 +48,7 @@ pub const Feature = enum { crypto, cssc, d128, + disable_distinct_predicate_dst_reg, disable_fast_inc_vl, disable_latency_sched_heuristic, disable_ldp, @@ -71,8 +72,10 @@ pub const Feature = enum { f8f16mm, f8f32mm, faminmax, + fast_ld1_single, fgt, fix_cortex_a53_835769, + fixed_load_latency_4, flagm, fmv, force_32bit_jump_tables, @@ -95,14 +98,16 @@ pub const Feature = enum { fuse_crypto_eor, fuse_csel, fuse_cset, + fuse_fcsel, fuse_literals, gcie, gcs, harden_sls_blr, harden_sls_nocomdat, harden_sls_retbr, + has_limited_64bit_vector_mul_bandwidth, hbc, - hcx, + hinte, i8mm, ite, jsconv, @@ -121,12 +126,13 @@ pub const Feature = enum { mops, mops_go, mpam, - mpamv2, mte, mtetc, neon, nmi, no_bti_at_return_twice, + no_lfi_loads, + no_lfi_stores, no_neg_immediates, no_sve_fp_ld1r, no_zcz_fpr64, @@ -138,7 +144,6 @@ pub const Feature = enum { pan_rwv, pauth, pauth_lr, - pcdphint, perfmon, poe2, pops, @@ -328,6 +333,11 @@ pub const all_features = blk: { .description = "Make use of aggressive interleaving during vectorization", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.align_cmp_csel_pairs)] = .{ + .llvm_name = "align-cmp-csel-pairs", + .description = "Align certain CMP/FCMP and CSEL/FCSEL instruction pairs", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.alternate_sextload_cvt_f32_pattern)] = .{ .llvm_name = "alternate-sextload-cvt-f32-pattern", .description = "Use alternative pattern for sextload convert to f32", @@ -476,11 +486,6 @@ pub const all_features = blk: { .description = "Enable Clear BHB instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.cmh)] = .{ - .llvm_name = "cmh", - .description = "Enable Armv9.7-A Contention Management Hints", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.cmp_bcc_fusion)] = .{ .llvm_name = "cmp-bcc-fusion", .description = "CPU fuses cmp+bcc operations", @@ -533,6 +538,11 @@ pub const all_features = blk: { .lse128, }), }; + result[@backingInt(Feature.disable_distinct_predicate_dst_reg)] = .{ + .llvm_name = "disable-distinct-predicate-dst-reg", + .description = "Disabling selecting a distinct predicate register for the destination operand of instructions that take a governing predicate", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.disable_fast_inc_vl)] = .{ .llvm_name = "disable-fast-inc-vl", .description = "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL", @@ -545,7 +555,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.disable_ldp)] = .{ .llvm_name = "disable-ldp", - .description = "Do not emit ldp", + .description = "Prefer not to emit ldp", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.disable_maximize_scalable_bandwidth)] = .{ @@ -555,7 +565,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.disable_stp)] = .{ .llvm_name = "disable-stp", - .description = "Do not emit stp", + .description = "Prefer not to emit stp", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.disable_unpredicated_ld_st_lower)] = .{ @@ -671,6 +681,11 @@ pub const all_features = blk: { .neon, }), }; + result[@backingInt(Feature.fast_ld1_single)] = .{ + .llvm_name = "fast-ld1-single", + .description = "Single-element LD1 to vector lane has same performance as regular load", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.fgt)] = .{ .llvm_name = "fgt", .description = "Enable fine grained virtualization traps extension", @@ -681,6 +696,11 @@ pub const all_features = blk: { .description = "Mitigate Cortex-A53 Erratum 835769", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.fixed_load_latency_4)] = .{ + .llvm_name = "fixed-load-latency-4", + .description = "Use a fixed latency of 4 for loads instead of querying the scheduling model", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.flagm)] = .{ .llvm_name = "flagm", .description = "Enable Armv8.4-A Flag Manipulation instructions", @@ -813,6 +833,11 @@ pub const all_features = blk: { .description = "CPU can fuse CMP and CSET operations", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.fuse_fcsel)] = .{ + .llvm_name = "fuse-fcsel", + .description = "CPU can fuse FCMP and FCSEL operations", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.fuse_literals)] = .{ .llvm_name = "fuse-literals", .description = "CPU fuses literal generation operations", @@ -845,14 +870,19 @@ pub const all_features = blk: { .description = "Harden against straight line speculation across RET and BR instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.has_limited_64bit_vector_mul_bandwidth)] = .{ + .llvm_name = "has-limited-64bit-vector-mul-bandwidth", + .description = "Has limited 64bit vector multiply bandwidth compared to scalar multiply", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.hbc)] = .{ .llvm_name = "hbc", .description = "Enable Armv8.8-A Hinted Conditional Branches Extension", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.hcx)] = .{ - .llvm_name = "hcx", - .description = "Enable Armv8.7-A HCRX_EL2 system register", + result[@backingInt(Feature.hinte)] = .{ + .llvm_name = "hinte", + .description = "Enable extended A64 hint instruction space", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.i8mm)] = .{ @@ -962,11 +992,6 @@ pub const all_features = blk: { .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.mpamv2)] = .{ - .llvm_name = "mpamv2", - .description = "Enable Armv9.7-A MPAMv2 Lookaside Buffer Invalidate instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mte)] = .{ .llvm_name = "mte", .description = "Enable Memory Tagging Extension", @@ -996,6 +1021,16 @@ pub const all_features = blk: { .description = "Don't place a BTI instruction after a return-twice", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.no_lfi_loads)] = .{ + .llvm_name = "no-lfi-loads", + .description = "Disable LFI sandboxing for load instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.no_lfi_stores)] = .{ + .llvm_name = "no-lfi-stores", + .description = "Disable LFI sandboxing for store instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.no_neg_immediates)] = .{ .llvm_name = "no-neg-immediates", .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", @@ -1063,11 +1098,6 @@ pub const all_features = blk: { .description = "Enable Armv9.5-A PAC enhancements", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.pcdphint)] = .{ - .llvm_name = "pcdphint", - .description = "Enable Armv9.6-A Producer Consumer Data Placement hints", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.perfmon)] = .{ .llvm_name = "perfmon", .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension", @@ -1813,7 +1843,6 @@ pub const all_features = blk: { .llvm_name = "v8.7a", .description = "Support ARM v8.7a architecture", .dependencies = featureSet(&[_]Feature{ - .hcx, .spe_eef, .v8_6a, .wfxt, @@ -1931,6 +1960,7 @@ pub const all_features = blk: { .description = "Support ARM v9.6a architecture", .dependencies = featureSet(&[_]Feature{ .cmpbr, + .hinte, .lsui, .occmo, .v9_5a, @@ -2265,12 +2295,14 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .aes, .aggressive_fma, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .altnzcv, .arith_bcc_fusion, .arith_cbz_fusion, .ccdp, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fptoint, .fuse_address, @@ -2301,10 +2333,12 @@ pub const cpu = struct { .llvm_name = "apple-a15", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2332,10 +2366,12 @@ pub const cpu = struct { .llvm_name = "apple-a16", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2344,8 +2380,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, - .hcx, .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, @@ -2364,10 +2400,12 @@ pub const cpu = struct { .llvm_name = "apple-a17", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2376,8 +2414,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, - .hcx, .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, @@ -2396,10 +2434,12 @@ pub const cpu = struct { .llvm_name = "apple-a18", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2408,6 +2448,7 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, .max_interleave_factor_4, .no_zcz_fpr64, @@ -2429,11 +2470,13 @@ pub const cpu = struct { .llvm_name = "apple-a19", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .cssc, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2442,6 +2485,7 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, .hbc, .max_interleave_factor_4, @@ -2541,12 +2585,14 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .aes, .aggressive_fma, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .altnzcv, .arith_bcc_fusion, .arith_cbz_fusion, .ccdp, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fptoint, .fuse_address, @@ -2577,10 +2623,12 @@ pub const cpu = struct { .llvm_name = "apple-m2", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2608,10 +2656,12 @@ pub const cpu = struct { .llvm_name = "apple-m3", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2620,8 +2670,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, - .hcx, .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, @@ -2640,10 +2690,12 @@ pub const cpu = struct { .llvm_name = "apple-m4", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2652,6 +2704,7 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, .max_interleave_factor_4, .no_zcz_fpr64, @@ -2673,11 +2726,13 @@ pub const cpu = struct { .llvm_name = "apple-m5", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .cssc, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2686,6 +2741,7 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, .hbc, .max_interleave_factor_4, @@ -2712,10 +2768,12 @@ pub const cpu = struct { .llvm_name = "apple-s10", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2724,8 +2782,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, - .hcx, .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, @@ -2864,10 +2922,12 @@ pub const cpu = struct { .llvm_name = "apple-s9", .features = featureSet(&[_]Feature{ .aes, + .align_cmp_csel_pairs, .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, .disable_latency_sched_heuristic, + .fast_ld1_single, .fp16fml, .fpac, .fuse_address, @@ -2876,8 +2936,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_crypto_eor, .fuse_csel, + .fuse_fcsel, .fuse_literals, - .hcx, .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, @@ -2891,6 +2951,34 @@ pub const cpu = struct { .zcz_gpr64, }), }; + pub const armagicpu: CpuModel = .{ + .name = "armagicpu", + .llvm_name = "armagicpu", + .features = featureSet(&[_]Feature{ + .alu_lsl_fast, + .avoid_ldapur, + .brbe, + .enable_select_opt, + .ete, + .fp16fml, + .fpac, + .fuse_adrp_add, + .fuse_aes, + .fuse_csel, + .fuse_cset, + .has_limited_64bit_vector_mul_bandwidth, + .ls64, + .mte, + .perfmon, + .predictable_select_expensive, + .rand, + .spe, + .sve_bitperm, + .use_fixed_over_scalable_if_equal_cost, + .use_postra_scheduler, + .v9_2a, + }), + }; pub const c1_nano: CpuModel = .{ .name = "c1_nano", .llvm_name = "c1-nano", @@ -2987,6 +3075,7 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3016,7 +3105,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .bf16, - .disable_maximize_scalable_bandwidth, .enable_select_opt, .ete, .fp16fml, @@ -3025,11 +3113,13 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .has_limited_64bit_vector_mul_bandwidth, .i8mm, .mte, .perfmon, .predictable_select_expensive, .sve_bitperm, + .use_fixed_over_scalable_if_equal_cost, .use_postra_scheduler, .v9a, }), @@ -3562,6 +3652,7 @@ pub const cpu = struct { .fullfp16, .fuse_adrp_add, .fuse_aes, + .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .rcpc, @@ -3587,6 +3678,7 @@ pub const cpu = struct { .fuse_adrp_add, .fuse_aes, .lse2, + .max_interleave_factor_4, .pauth, .perfmon, .predictable_select_expensive, @@ -3612,6 +3704,7 @@ pub const cpu = struct { .fuse_adrp_add, .fuse_aes, .i8mm, + .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3635,6 +3728,7 @@ pub const cpu = struct { .fuse_adrp_add, .fuse_aes, .i8mm, + .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3659,6 +3753,7 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3683,6 +3778,7 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3898,6 +3994,7 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3917,6 +4014,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .enable_select_opt, .ete, + .fixed_load_latency_4, .fuse_adrp_add, .fuse_aes, .neon, @@ -3955,6 +4053,36 @@ pub const cpu = struct { .v9a, }), }; + pub const hip12: CpuModel = .{ + .name = "hip12", + .llvm_name = "hip12", + .features = featureSet(&[_]Feature{ + .addr_lsl_slow_14, + .alu_lsl_fast, + .brbe, + .cmp_bcc_fusion, + .ete, + .fp16fml, + .fpac, + .fuse_aes, + .hbc, + .ls64, + .nmi, + .perfmon, + .rand, + .rcpc3, + .rme, + .spe, + .store_pair_suppress, + .sve2, + .sve_aes, + .sve_bitperm, + .sve_sha3, + .sve_sm4, + .use_postra_scheduler, + .v8_7a, + }), + }; pub const kryo: CpuModel = .{ .name = "kryo", .llvm_name = "kryo", @@ -4045,7 +4173,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .bf16, - .disable_maximize_scalable_bandwidth, .enable_select_opt, .ete, .fp16fml, @@ -4054,11 +4181,13 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .has_limited_64bit_vector_mul_bandwidth, .i8mm, .mte, .perfmon, .predictable_select_expensive, .sve_bitperm, + .use_fixed_over_scalable_if_equal_cost, .use_postra_scheduler, .v9a, }), @@ -4169,6 +4298,7 @@ pub const cpu = struct { .rand, .spe, .sve_bitperm, + .use_fixed_over_scalable_if_equal_cost, .use_postra_scheduler, .v9_2a, }), @@ -4188,14 +4318,15 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, + .has_limited_64bit_vector_mul_bandwidth, .ls64, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .rand, .spe, .sve_bitperm, + .use_fixed_over_scalable_if_equal_cost, .use_postra_scheduler, .v9_2a, }), @@ -4248,6 +4379,33 @@ pub const cpu = struct { .v8_6a, }), }; + pub const rigel: CpuModel = .{ + .name = "rigel", + .llvm_name = "rigel", + .features = featureSet(&[_]Feature{ + .brbe, + .chk, + .ete, + .faminmax, + .fp16fml, + .fp8dot2, + .fp8dot4, + .fp8fma, + .fpac, + .ls64, + .lut, + .mte, + .olympus, + .perfmon, + .rand, + .spe, + .sve_aes, + .sve_bitperm, + .sve_sha3, + .sve_sm4, + .v9_2a, + }), + }; pub const saphira: CpuModel = .{ .name = "saphira", .llvm_name = "saphira", diff --git a/lib/std/Target/amdgcn.zig b/lib/std/Target/amdgcn.zig index b5b9108213a0c7fd3bc5abddbd7aca3ee90cbca1..9493dc2bf77031ce4fd2be0a2f73a868b64dc21d 100644 --- a/lib/std/Target/amdgcn.zig +++ b/lib/std/Target/amdgcn.zig @@ -6,6 +6,7 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"1024_addressable_vgprs", + @"1536_physical_vgprs", @"16_bit_insts", @"45_bit_num_records_buffer_resource", @"64_bit_literals", @@ -18,12 +19,12 @@ pub const Feature = enum { addressablelocalmemorysize327680, addressablelocalmemorysize65536, agent_scope_fine_grained_remote_memory_atomics, - allocate1_5xvgprs, aperture_regs, architected_flat_scratch, architected_sgprs, ashr_pk_insts, assembler_permissive_wavesize, + asynccnt, atomic_buffer_global_pk_add_f16_insts, atomic_buffer_global_pk_add_f16_no_rtn_insts, atomic_buffer_pk_add_bf16_inst, @@ -75,9 +76,12 @@ pub const Feature = enum { dpp, dpp8, dpp_64bit, + dpp_row_bcast, dpp_src1_sgpr, + dpp_wavefront_shifts, ds128, ds_src2_insts, + dx10_clamp_and_ieee_mode, emulated_system_scope_atomics, extended_image_insts, f16bf16_to_fp6bf6_cvt_scale_insts, @@ -91,13 +95,17 @@ pub const Feature = enum { flat_global_insts, flat_gvs_mode, flat_inst_offsets, + flat_offset_bits_12, + flat_offset_bits_24, flat_scratch, flat_scratch_insts, flat_segment_offset_bug, + flat_signed_offset, fma_mix_bf16_insts, fma_mix_insts, fmacf64_inst, fmaf, + formatted_mubuf_insts, fp4_cvt_scale_insts, fp64, fp6bf6_cvt_scale_insts, @@ -116,10 +124,15 @@ pub const Feature = enum { gfx10_b_encoding, gfx10_insts, gfx11, + gfx11_7_insts, gfx11_insts, gfx12, gfx1250_insts, + gfx1251_gemm_insts, + gfx125x_lowest_rate_wmma, gfx12_insts, + gfx13, + gfx13_insts, gfx7_gfx8_gfx9_insts, gfx8_insts, gfx9, @@ -135,6 +148,8 @@ pub const Feature = enum { image_insts, image_store_d16_bug, inst_fwd_prefetch_bug, + instcachelinesize128, + instcachelinesize64, int_clamp_insts, inv_2pi_inline_imm, kernarg_preload, @@ -149,6 +164,7 @@ pub const Feature = enum { mad_intra_fwd_bug, mad_mac_f32_insts, mad_mix_insts, + mad_nc_64_32_insts, mad_u32_inst, mai_insts, max_hard_clause_length_32, @@ -161,22 +177,31 @@ pub const Feature = enum { mfma_inline_literal_bug, mimg_r128, min3_max3_pkf16, + min_max_i64_insts, minimum3_maximum3_f16, minimum3_maximum3_f32, minimum3_maximum3_pkf16, movrel, + mqsad_insts, + mqsad_pk_insts, msaa_load_dst_sel_bug, + msad_insts, + mtbuf_insts, negative_scratch_offset_bug, negative_unaligned_scratch_offset_bug, no_data_dep_hazard, + no_f16_pseudo_scalar_trans_inline_constants, no_sdst_cmpx, nsa_clause_bug, nsa_encoding, nsa_to_vmem_bug, offset_3f_bug, packed_fp32_ops, + packed_fp64_ops, packed_tid, + packed_u64_ops, partial_nsa_encoding, + permlane16_insts, permlane16_swap, permlane32_swap, pk_add_min_max_insts, @@ -185,23 +210,25 @@ pub const Feature = enum { precise_memory, priv_enabled_trap2_nop_bug, prng_inst, - promote_alloca, prt_strict_null, pseudo_scalar_trans, qsad_insts, r128_a16, real_true16, - relaxed_buffer_oob_mode, required_export_priority, requires_cov6, + requires_initial_unclause_vmem, restricted_soffset, + s_barrier_leave_imm, s_memrealtime, s_memtime_inst, s_wakeup_barrier_inst, + s_wakeup_imm, sad_insts, safe_cu_prefetch, safe_smem_prefetch, salu_float, + salu_minimum_maximum_insts, scalar_atomics, scalar_dwordx3_loads, scalar_flat_scratch_insts, @@ -219,13 +246,17 @@ pub const Feature = enum { shader_cycles_hi_lo_registers, shader_cycles_register, si_scheduler, + smem_prefetch_insts, smem_to_vector_write_hazard, southern_islands, sramecc, sramecc_support, + swmmac_gfx1200_insts, + swmmac_gfx1250_insts, tanh_insts, tensor_cvt_lut_insts, - tgsplit, + tgsplit_support, + trans_coexecution_hazard, transpose_load_f4f6_insts, trap_handler, trig_reduced_range, @@ -236,7 +267,10 @@ pub const Feature = enum { unaligned_scratch_access, unpacked_d16_vmem, unsafe_ds_offset_folding, + use_add_pc64_inst, user_sgpr_init16_bug, + v_mov_b64_inst, + v_mul_u64_inst, valu_trans_use_hazard, vcmpx_exec_war_hazard, vcmpx_permlane_hazard, @@ -249,6 +283,7 @@ pub const Feature = enum { volcanic_islands, vop3_literal, vop3p, + vop3px2_increments_va_vdst_twice, vopd, vscnt, wait_xcnt, @@ -256,8 +291,12 @@ pub const Feature = enum { wavefrontsize16, wavefrontsize32, wavefrontsize64, + wmma_128b_insts, + wmma_256b_insts, + wmma_coexecution_hazards, xf32_insts, xnack, + xnack_on_off_modes, xnack_support, }; @@ -276,6 +315,11 @@ pub const all_features = blk: { .description = "Has 1024 addressable VGPRs", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.@"1536_physical_vgprs")] = .{ + .llvm_name = "1536-physical-vgprs", + .description = "Has 1536 physical VGPRs per SIMD", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.@"16_bit_insts")] = .{ .llvm_name = "16-bit-insts", .description = "Has i16/f16 instructions", @@ -336,11 +380,6 @@ pub const all_features = blk: { .description = "Agent (device) scoped atomic operations, excluding those directly supported by PCIe (i.e. integer atomic add, exchange, and compare-and-swap), are functional for allocations in host or peer device memory.", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.allocate1_5xvgprs)] = .{ - .llvm_name = "allocate1_5xvgprs", - .description = "Has 50% more physical VGPRs and 50% larger allocation granule", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.aperture_regs)] = .{ .llvm_name = "aperture-regs", .description = "Has Memory Aperture Base and Size Registers", @@ -363,7 +402,12 @@ pub const all_features = blk: { }; result[@backingInt(Feature.assembler_permissive_wavesize)] = .{ .llvm_name = "assembler-permissive-wavesize", - .description = "allow parsing wave32 and wave64 variants of instructions", + .description = "Allow parsing wave32 and wave64 variants of instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.asynccnt)] = .{ + .llvm_name = "asynccnt", + .description = "Has separate asynccnt counter", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{ @@ -637,11 +681,21 @@ pub const all_features = blk: { .description = "Support DPP (Data Parallel Primitives) extension in DP ALU", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.dpp_row_bcast)] = .{ + .llvm_name = "dpp-row-bcast", + .description = "Support DPP row_bcast15/row_bcast31", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.dpp_src1_sgpr)] = .{ .llvm_name = "dpp-src1-sgpr", .description = "Support SGPR for Src1 of DPP instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.dpp_wavefront_shifts)] = .{ + .llvm_name = "dpp-wavefront-shifts", + .description = "Support DPP wave_shl/wave_rol/wave_shr/wave_ror", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.ds128)] = .{ .llvm_name = "enable-ds128", .description = "Use ds_{read|write}_b128", @@ -652,6 +706,11 @@ pub const all_features = blk: { .description = "Has ds_*_src2 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.dx10_clamp_and_ieee_mode)] = .{ + .llvm_name = "dx10-clamp-and-ieee-mode", + .description = "Target has DX10_CLAMP and IEEE_MODE kernel descriptor bits", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.emulated_system_scope_atomics)] = .{ .llvm_name = "emulated-system-scope-atomics", .description = "System scope atomics unsupported by the PCI-e are emulated in HW via CAS loop and functional.", @@ -723,6 +782,16 @@ pub const all_features = blk: { .description = "Flat instructions have immediate offset addressing mode", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.flat_offset_bits_12)] = .{ + .llvm_name = "flat-offset-bits-12", + .description = "Number of bits for flat offset encoding", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.flat_offset_bits_24)] = .{ + .llvm_name = "flat-offset-bits-24", + .description = "Number of bits for flat offset encoding", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.flat_scratch)] = .{ .llvm_name = "enable-flat-scratch", .description = "Use scratch_* flat memory instructions to access scratch", @@ -740,6 +809,11 @@ pub const all_features = blk: { .description = "GFX10 bug where inst_offset is ignored when flat instructions access global memory", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.flat_signed_offset)] = .{ + .llvm_name = "flat-signed-offset", + .description = "Immediate offset of FLAT instructions are always signed", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.fma_mix_bf16_insts)] = .{ .llvm_name = "fma-mix-bf16-insts", .description = "Has v_fma_mix_f32_bf16, v_fma_mixlo_bf16, v_fma_mixhi_bf16 instructions", @@ -760,6 +834,11 @@ pub const all_features = blk: { .description = "Enable single precision FMA (not as fast as mul+add, but fused)", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.formatted_mubuf_insts)] = .{ + .llvm_name = "formatted-mubuf-insts", + .description = "Has formatted memory untyped buffer instructions.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.fp4_cvt_scale_insts)] = .{ .llvm_name = "fp4-cvt-scale-insts", .description = "Has fp4 conversion scale instructions", @@ -841,13 +920,16 @@ pub const all_features = blk: { .default_component_zero, .dpp, .dpp8, + .dx10_clamp_and_ieee_mode, .extended_image_insts, .fast_denormal_f32, .fast_fmaf, .flat_global_insts, .flat_inst_offsets, + .flat_offset_bits_12, .flat_scratch_insts, .fma_mix_insts, + .formatted_mubuf_insts, .fp64, .g16, .gds, @@ -856,14 +938,20 @@ pub const all_features = blk: { .gfx9_insts, .gws, .image_insts, + .instcachelinesize64, .int_clamp_insts, .inv_2pi_inline_imm, .lerp_inst, .max_hard_clause_length_63, .mimg_r128, .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .no_data_dep_hazard, .no_sdst_cmpx, + .permlane16_insts, .pk_fmac_f16_inst, .qsad_insts, .s_memrealtime, @@ -929,6 +1017,7 @@ pub const all_features = blk: { .flat_inst_offsets, .flat_scratch_insts, .fma_mix_insts, + .formatted_mubuf_insts, .fp64, .g16, .gds, @@ -940,14 +1029,20 @@ pub const all_features = blk: { .gfx8_insts, .gfx9_insts, .gws, + .instcachelinesize128, .int_clamp_insts, .inv_2pi_inline_imm, .lerp_inst, .max_hard_clause_length_32, .mimg_r128, .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .no_data_dep_hazard, .no_sdst_cmpx, + .permlane16_insts, .pk_fmac_f16_inst, .qsad_insts, .sad_insts, @@ -962,6 +1057,11 @@ pub const all_features = blk: { .vscnt, }), }; + result[@backingInt(Feature.gfx11_7_insts)] = .{ + .llvm_name = "gfx11-7-insts", + .description = "Additional instructions for GFX11.7", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.gfx11_insts)] = .{ .llvm_name = "gfx11-insts", .description = "Additional instructions for GFX11+", @@ -986,7 +1086,9 @@ pub const all_features = blk: { .fast_fmaf, .flat_global_insts, .flat_inst_offsets, + .flat_offset_bits_24, .flat_scratch_insts, + .flat_signed_offset, .fma_mix_insts, .fp64, .g16, @@ -999,6 +1101,7 @@ pub const all_features = blk: { .gfx8_insts, .gfx9_insts, .ieee_minimum_maximum_insts, + .instcachelinesize128, .int_clamp_insts, .inv_2pi_inline_imm, .max_hard_clause_length_32, @@ -1008,7 +1111,9 @@ pub const all_features = blk: { .movrel, .no_data_dep_hazard, .no_sdst_cmpx, + .permlane16_insts, .pk_fmac_f16_inst, + .salu_minimum_maximum_insts, .true16, .unaligned_buffer_access, .unaligned_ds_access, @@ -1024,11 +1129,91 @@ pub const all_features = blk: { .description = "Additional instructions for GFX1250+", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.gfx1251_gemm_insts)] = .{ + .llvm_name = "gfx1251-gemm-insts", + .description = "Has additional gfx1251 DGEMM instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.gfx125x_lowest_rate_wmma)] = .{ + .llvm_name = "gfx125x-lowest-rate-wmma", + .description = "Has the lowest rate wmma in the gfx125x family, mainly for the gfx12-5-generic", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.gfx12_insts)] = .{ .llvm_name = "gfx12-insts", .description = "Additional instructions for GFX12+", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.gfx13)] = .{ + .llvm_name = "gfx13", + .description = "GFX13 GPU generation", + .dependencies = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, + .ci_insts, + .default_component_broadcast, + .dpp, + .dpp8, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gfx10_3_insts, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx10_insts, + .gfx11_insts, + .gfx12_insts, + .gfx13_insts, + .gfx8_insts, + .gfx9_insts, + .ieee_minimum_maximum_insts, + .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, + .max_hard_clause_length_32, + .mimg_r128, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .movrel, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, + .permlane16_insts, + .pk_fmac_f16_inst, + .salu_minimum_maximum_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, + }), + }; + result[@backingInt(Feature.gfx13_insts)] = .{ + .llvm_name = "gfx13-insts", + .description = "Additional instructions for GFX13+", + .dependencies = featureSet(&[_]Feature{ + .s_barrier_leave_imm, + .s_wakeup_imm, + }), + }; result[@backingInt(Feature.gfx7_gfx8_gfx9_insts)] = .{ .llvm_name = "gfx7-gfx8-gfx9-insts", .description = "Instructions shared in GFX7, GFX8, GFX9", @@ -1054,20 +1239,29 @@ pub const all_features = blk: { .cvt_pknorm_vop3_insts, .default_component_zero, .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .dx10_clamp_and_ieee_mode, .fast_denormal_f32, .fast_fmaf, .flat_global_insts, .flat_inst_offsets, .flat_scratch_insts, + .formatted_mubuf_insts, .fp64, .gcn3_encoding, .gfx7_gfx8_gfx9_insts, .gfx8_insts, .gfx9_insts, .gws, + .instcachelinesize64, .int_clamp_insts, .inv_2pi_inline_imm, .lerp_inst, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .negative_scratch_offset_bug, .qsad_insts, .r128_a16, @@ -1089,7 +1283,7 @@ pub const all_features = blk: { .vmem_write_vgpr_in_order, .vop3p, .wavefrontsize64, - .xnack_support, + .xnack_on_off_modes, }), }; result[@backingInt(Feature.gfx90a_insts)] = .{ @@ -1142,7 +1336,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.ieee_minimum_maximum_insts)] = .{ .llvm_name = "ieee-minimum-maximum-insts", - .description = "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32 and v_pk_minimum/maximum_f16 instructions", + .description = "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32 andv_pk_minimum/maximum_f16 instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.image_gather4_d16_bug)] = .{ @@ -1165,6 +1359,16 @@ pub const all_features = blk: { .description = "S_INST_PREFETCH instruction causes shader to hang", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.instcachelinesize128)] = .{ + .llvm_name = "instcachelinesize128", + .description = "Instruction cache line size in bytes.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.instcachelinesize64)] = .{ + .llvm_name = "instcachelinesize64", + .description = "Instruction cache line size in bytes.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.int_clamp_insts)] = .{ .llvm_name = "int-clamp-insts", .description = "Support clamp for integer destination", @@ -1235,6 +1439,11 @@ pub const all_features = blk: { .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.mad_nc_64_32_insts)] = .{ + .llvm_name = "mad-nc-64-32-insts", + .description = "Has v_mad_nc_{u64_u32|i64_i32} instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.mad_u32_inst)] = .{ .llvm_name = "mad-u32-inst", .description = "Has v_mad_u32 instruction", @@ -1295,6 +1504,11 @@ pub const all_features = blk: { .description = "Has v_pk_min3_num_f16 and v_pk_max3_num_f16 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.min_max_i64_insts)] = .{ + .llvm_name = "min-max-i64-insts", + .description = "Has v_{min|max}_{i|u}64 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.minimum3_maximum3_f16)] = .{ .llvm_name = "minimum3-maximum3-f16", .description = "Has v_minimum3_f16 and v_maximum3_f16 instructions", @@ -1315,11 +1529,31 @@ pub const all_features = blk: { .description = "Has v_movrel*_b32 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.mqsad_insts)] = .{ + .llvm_name = "mqsad-insts", + .description = "Has v_mqsad_u32_u8 instruction", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mqsad_pk_insts)] = .{ + .llvm_name = "mqsad-pk-insts", + .description = "Has v_mqsad_pk_u16_u8 instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.msaa_load_dst_sel_bug)] = .{ .llvm_name = "msaa-load-dst-sel-bug", .description = "MSAA loads not honoring dst_sel bug", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.msad_insts)] = .{ + .llvm_name = "msad-insts", + .description = "Has v_msad_u8 instruction", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mtbuf_insts)] = .{ + .llvm_name = "mtbuf-insts", + .description = "Has memory typed buffer instructions.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.negative_scratch_offset_bug)] = .{ .llvm_name = "negative-scratch-offset-bug", .description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9", @@ -1327,7 +1561,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.negative_unaligned_scratch_offset_bug)] = .{ .llvm_name = "negative-unaligned-scratch-offset-bug", - .description = "Scratch instructions with a VGPR offset and a negative immediate offset that is not a multiple of 4 read wrong memory on GFX10", + .description = "Scratch instructions with a VGPR offset and a negative immediate offset thatis not a multiple of 4 read wrong memory on GFX10", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.no_data_dep_hazard)] = .{ @@ -1335,6 +1569,11 @@ pub const all_features = blk: { .description = "Does not need SW waitstates", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.no_f16_pseudo_scalar_trans_inline_constants)] = .{ + .llvm_name = "no-f16-pseudo-scalar-trans-inline-constants", + .description = "Inline constants are not supported for F16 pseudo scalar transcendentals", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.no_sdst_cmpx)] = .{ .llvm_name = "no-sdst-cmpx", .description = "V_CMPX does not write VCC/SGPR in addition to EXEC", @@ -1365,16 +1604,31 @@ pub const all_features = blk: { .description = "Support packed fp32 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.packed_fp64_ops)] = .{ + .llvm_name = "packed-fp64-ops", + .description = "Support packed fp64 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.packed_tid)] = .{ .llvm_name = "packed-tid", .description = "Workitem IDs are packed into v0 at kernel launch", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.packed_u64_ops)] = .{ + .llvm_name = "packed-u64-ops", + .description = "Support packed uint64 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.partial_nsa_encoding)] = .{ .llvm_name = "partial-nsa-encoding", .description = "Support partial NSA encoding for image instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.permlane16_insts)] = .{ + .llvm_name = "permlane16-insts", + .description = "Has v_permlane16_b32/v_permlanex16_b32 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.permlane16_swap)] = .{ .llvm_name = "permlane16-swap", .description = "Has v_permlane16_swap_b32 instructions", @@ -1415,11 +1669,6 @@ pub const all_features = blk: { .description = "Has v_prng_b32 instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.promote_alloca)] = .{ - .llvm_name = "promote-alloca", - .description = "Enable promote alloca pass", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.prt_strict_null)] = .{ .llvm_name = "enable-prt-strict-null", .description = "Enable zeroing of result registers for sparse texture fetches", @@ -1445,11 +1694,6 @@ pub const all_features = blk: { .description = "Use true 16-bit registers", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.relaxed_buffer_oob_mode)] = .{ - .llvm_name = "relaxed-buffer-oob-mode", - .description = "Disable strict out-of-bounds buffer guarantees. An OOB access may potentially cause an adjacent access to be treated as if it were also OOB", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.required_export_priority)] = .{ .llvm_name = "required-export-priority", .description = "Export priority must be explicitly manipulated on GFX11.5", @@ -1460,11 +1704,21 @@ pub const all_features = blk: { .description = "Target Requires Code Object V6", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.requires_initial_unclause_vmem)] = .{ + .llvm_name = "requires-initial-unclause-vmem", + .description = "Hardware entrypoints require first VMEM instruction to be unclaused", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.restricted_soffset)] = .{ .llvm_name = "restricted-soffset", .description = "Has restricted SOffset (immediate not supported).", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.s_barrier_leave_imm)] = .{ + .llvm_name = "s-barrier-leave-imm", + .description = "s_barrier_leave takes an immediate operand", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.s_memrealtime)] = .{ .llvm_name = "s-memrealtime", .description = "Has s_memrealtime instruction", @@ -1480,6 +1734,11 @@ pub const all_features = blk: { .description = "Has s_wakeup_barrier instruction.", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.s_wakeup_imm)] = .{ + .llvm_name = "s-wakeup-imm", + .description = "s_wakeup takes an immediate operand", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.sad_insts)] = .{ .llvm_name = "sad-insts", .description = "Has v_sad* instructions", @@ -1500,6 +1759,11 @@ pub const all_features = blk: { .description = "Has SALU floating point instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.salu_minimum_maximum_insts)] = .{ + .llvm_name = "salu-minimum-maximum-insts", + .description = "Has s_minimum/maximum_f16/f32 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.scalar_atomics)] = .{ .llvm_name = "scalar-atomics", .description = "Has atomic scalar memory instructions", @@ -1564,16 +1828,23 @@ pub const all_features = blk: { .cvt_pknorm_vop2_insts, .default_component_zero, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .formatted_mubuf_insts, .fp64, .gds, .gfx7_gfx8_gfx9_insts, .gws, .image_insts, + .instcachelinesize64, .lerp_inst, .mad_mac_f32_insts, .mimg_r128, .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .qsad_insts, .s_memtime_inst, .sad_insts, @@ -1613,6 +1884,11 @@ pub const all_features = blk: { .description = "Enable SI Machine Scheduler", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.smem_prefetch_insts)] = .{ + .llvm_name = "smem-prefetch-insts", + .description = "Has s_prefetch_inst, s_prefetch_inst_pc_rel, s_prefetch_data and s_prefetch_data_pc_rel instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.smem_to_vector_write_hazard)] = .{ .llvm_name = "smem-to-vector-write-hazard", .description = "s_load_dword followed by v_cmp page faults", @@ -1629,16 +1905,22 @@ pub const all_features = blk: { .cvt_pknorm_vop2_insts, .default_component_zero, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .formatted_mubuf_insts, .fp64, .gds, .gws, .image_insts, + .instcachelinesize64, .ldsbankcount32, .lerp_inst, .mad_mac_f32_insts, .mimg_r128, .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .s_memtime_inst, .sad_insts, .trig_reduced_range, @@ -1656,6 +1938,16 @@ pub const all_features = blk: { .description = "Hardware supports SRAMECC", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.swmmac_gfx1200_insts)] = .{ + .llvm_name = "swmmac-gfx1200-insts", + .description = "Has GFX1200 SWMMAC instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.swmmac_gfx1250_insts)] = .{ + .llvm_name = "swmmac-gfx1250-insts", + .description = "Has GFX1250 SWMMAC instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.tanh_insts)] = .{ .llvm_name = "tanh-insts", .description = "Has v_tanh_f32/f16 instructions", @@ -1666,9 +1958,14 @@ pub const all_features = blk: { .description = "Has v_perm_pk16* instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.tgsplit)] = .{ - .llvm_name = "tgsplit", - .description = "Enable threadgroup split execution", + result[@backingInt(Feature.tgsplit_support)] = .{ + .llvm_name = "tgsplit-support", + .description = "Hardware support for threadgroup split execution mode", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.trans_coexecution_hazard)] = .{ + .llvm_name = "trans-coexecution-hazard", + .description = "Hazard when TRANS co-executes with other VALU instruction", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.transpose_load_f4f6_insts)] = .{ @@ -1721,11 +2018,26 @@ pub const all_features = blk: { .description = "Force using DS instruction immediate offsets on SI", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.use_add_pc64_inst)] = .{ + .llvm_name = "use-add-pc64-inst", + .description = "Use s_add_pc_i64 instruction.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.user_sgpr_init16_bug)] = .{ .llvm_name = "user-sgpr-init16-bug", .description = "Bug requiring at least 16 user+system SGPRs to be enabled", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.v_mov_b64_inst)] = .{ + .llvm_name = "v-mov-b64-inst", + .description = "Has v_mov_b64 instruction", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.v_mul_u64_inst)] = .{ + .llvm_name = "v-mul-u64-inst", + .description = "Has v_mul_u64 instruction.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.valu_trans_use_hazard)] = .{ .llvm_name = "valu-trans-use-hazard", .description = "Hazard when TRANS instructions are closely followed by a use of the result", @@ -1758,7 +2070,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.vmem_to_lds_load_insts)] = .{ .llvm_name = "vmem-to-lds-load-insts", - .description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_load w/lds bit set or global_load_lds. This does not include scratch_load_lds.", + .description = "The platform has memory to lds instructions (global_load w/lds bit set, buffer_loadw/lds bit set or global_load_lds. This does not include scratch_load_lds.", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.vmem_to_scalar_write_hazard)] = .{ @@ -1782,10 +2094,14 @@ pub const all_features = blk: { .cvt_pknorm_vop2_insts, .default_component_zero, .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, .fast_denormal_f32, .flat_address_space, + .formatted_mubuf_insts, .fp64, .gcn3_encoding, .gds, @@ -1793,12 +2109,17 @@ pub const all_features = blk: { .gfx8_insts, .gws, .image_insts, + .instcachelinesize64, .int_clamp_insts, .inv_2pi_inline_imm, .lerp_inst, .mad_mac_f32_insts, .mimg_r128, .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .qsad_insts, .s_memrealtime, .s_memtime_inst, @@ -1824,6 +2145,11 @@ pub const all_features = blk: { .description = "Has VOP3P packed instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.vop3px2_increments_va_vdst_twice)] = .{ + .llvm_name = "vop3px2-increments-va-vdst-twice", + .description = "VOP3PX2 encoded instructions increment the VaVdst counter twice", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.vopd)] = .{ .llvm_name = "vopd", .description = "Has VOPD dual issue wave32 instructions", @@ -1859,6 +2185,21 @@ pub const all_features = blk: { .description = "The number of threads per wavefront", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.wmma_128b_insts)] = .{ + .llvm_name = "wmma-128b-insts", + .description = "Has WMMA instructions where A and B matrices do not have duplicated data", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.wmma_256b_insts)] = .{ + .llvm_name = "wmma-256b-insts", + .description = "Has WMMA instructions where A and B matrices have duplicated data", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.wmma_coexecution_hazards)] = .{ + .llvm_name = "wmma-coexecution-hazards", + .description = "Hazards when WMMA co-executes with other WMMA/VALU instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.xf32_insts)] = .{ .llvm_name = "xf32-insts", .description = "Has instructions that support xf32 format, such as v_mfma_f32_16x16x8_xf32 and v_mfma_f32_32x32x4_xf32", @@ -1867,7 +2208,16 @@ pub const all_features = blk: { result[@backingInt(Feature.xnack)] = .{ .llvm_name = "xnack", .description = "Enable XNACK support", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .xnack_support, + }), + }; + result[@backingInt(Feature.xnack_on_off_modes)] = .{ + .llvm_name = "xnack-on-off-modes", + .description = "Target supports XNACK on/off modes", + .dependencies = featureSet(&[_]Feature{ + .xnack_support, + }), }; result[@backingInt(Feature.xnack_support)] = .{ .llvm_name = "xnack-support", @@ -1900,7 +2250,7 @@ pub const cpu = struct { .ldsbankcount32, .unpacked_d16_vmem, .volcanic_islands, - .xnack_support, + .xnack_on_off_modes, }), }; pub const fiji: CpuModel = .{ @@ -1951,7 +2301,7 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx1011: CpuModel = .{ @@ -1987,7 +2337,7 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx1012: CpuModel = .{ @@ -2023,7 +2373,7 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx1013: CpuModel = .{ @@ -2054,7 +2404,7 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx1030: CpuModel = .{ @@ -2232,7 +2582,7 @@ pub const cpu = struct { .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, .vmem_to_scalar_write_hazard, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx10_3_generic: CpuModel = .{ @@ -2261,7 +2611,7 @@ pub const cpu = struct { .name = "gfx1100", .llvm_name = "gfx1100", .features = featureSet(&[_]Feature{ - .allocate1_5xvgprs, + .@"1536_physical_vgprs", .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -2274,6 +2624,7 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2290,13 +2641,14 @@ pub const cpu = struct { .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1101: CpuModel = .{ .name = "gfx1101", .llvm_name = "gfx1101", .features = featureSet(&[_]Feature{ - .allocate1_5xvgprs, + .@"1536_physical_vgprs", .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -2309,6 +2661,7 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2324,6 +2677,7 @@ pub const cpu = struct { .shader_cycles_register, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1102: CpuModel = .{ @@ -2342,6 +2696,7 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2358,6 +2713,7 @@ pub const cpu = struct { .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1103: CpuModel = .{ @@ -2376,6 +2732,7 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2391,6 +2748,7 @@ pub const cpu = struct { .shader_cycles_register, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1150: CpuModel = .{ @@ -2410,6 +2768,7 @@ pub const cpu = struct { .dot8_insts, .dot9_insts, .dpp_src1_sgpr, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2424,13 +2783,14 @@ pub const cpu = struct { .salu_float, .shader_cycles_register, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1151: CpuModel = .{ .name = "gfx1151", .llvm_name = "gfx1151", .features = featureSet(&[_]Feature{ - .allocate1_5xvgprs, + .@"1536_physical_vgprs", .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, @@ -2444,6 +2804,7 @@ pub const cpu = struct { .dot8_insts, .dot9_insts, .dpp_src1_sgpr, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2458,6 +2819,7 @@ pub const cpu = struct { .salu_float, .shader_cycles_register, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1152: CpuModel = .{ @@ -2477,6 +2839,7 @@ pub const cpu = struct { .dot8_insts, .dot9_insts, .dpp_src1_sgpr, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2491,6 +2854,7 @@ pub const cpu = struct { .salu_float, .shader_cycles_register, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1153: CpuModel = .{ @@ -2510,6 +2874,7 @@ pub const cpu = struct { .dot8_insts, .dot9_insts, .dpp_src1_sgpr, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2523,6 +2888,198 @@ pub const cpu = struct { .salu_float, .shader_cycles_register, .vcmpx_permlane_hazard, + .wmma_256b_insts, + }), + }; + pub const gfx1154: CpuModel = .{ + .name = "gfx1154", + .llvm_name = "gfx1154", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .back_off_barrier, + .d16_write_vgpr32, + .dl_insts, + .dot10_insts, + .dot12_insts, + .dot5_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .dx10_clamp_and_ieee_mode, + .flat_atomic_fadd_f32_inst, + .gfx11, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .real_true16, + .required_export_priority, + .salu_float, + .shader_cycles_register, + .vcmpx_permlane_hazard, + .wmma_256b_insts, + }), + }; + pub const gfx1170: CpuModel = .{ + .name = "gfx1170", + .llvm_name = "gfx1170", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .back_off_barrier, + .d16_write_vgpr32, + .dl_insts, + .dot10_insts, + .dot11_insts, + .dot12_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .flat_atomic_fadd_f32_inst, + .fp8_conversion_insts, + .gfx11, + .gfx11_7_insts, + .ieee_minimum_maximum_insts, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .no_f16_pseudo_scalar_trans_inline_constants, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .real_true16, + .salu_float, + .shader_cycles_register, + .swmmac_gfx1200_insts, + .vcmpx_permlane_hazard, + .wmma_128b_insts, + }), + }; + pub const gfx1171: CpuModel = .{ + .name = "gfx1171", + .llvm_name = "gfx1171", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .back_off_barrier, + .d16_write_vgpr32, + .dl_insts, + .dot10_insts, + .dot11_insts, + .dot12_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .flat_atomic_fadd_f32_inst, + .fp8_conversion_insts, + .gfx11, + .gfx11_7_insts, + .ieee_minimum_maximum_insts, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .no_f16_pseudo_scalar_trans_inline_constants, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .real_true16, + .salu_float, + .shader_cycles_register, + .swmmac_gfx1200_insts, + .vcmpx_permlane_hazard, + .wmma_128b_insts, + }), + }; + pub const gfx1172: CpuModel = .{ + .name = "gfx1172", + .llvm_name = "gfx1172", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .back_off_barrier, + .d16_write_vgpr32, + .dl_insts, + .dot10_insts, + .dot11_insts, + .dot12_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .flat_atomic_fadd_f32_inst, + .fp8_conversion_insts, + .gfx11, + .gfx11_7_insts, + .ieee_minimum_maximum_insts, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .no_f16_pseudo_scalar_trans_inline_constants, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .real_true16, + .salu_float, + .shader_cycles_register, + .swmmac_gfx1200_insts, + .vcmpx_permlane_hazard, + .wmma_128b_insts, + }), + }; + pub const gfx11_7_generic: CpuModel = .{ + .name = "gfx11_7_generic", + .llvm_name = "gfx11-7-generic", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .back_off_barrier, + .d16_write_vgpr32, + .dl_insts, + .dot10_insts, + .dot11_insts, + .dot12_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .dpp_src1_sgpr, + .flat_atomic_fadd_f32_inst, + .fp8_conversion_insts, + .gfx11, + .gfx11_7_insts, + .ieee_minimum_maximum_insts, + .image_insts, + .ldsbankcount32, + .memory_atomic_fadd_f32_denormal_support, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .no_f16_pseudo_scalar_trans_inline_constants, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .real_true16, + .requires_cov6, + .salu_float, + .shader_cycles_register, + .swmmac_gfx1200_insts, + .vcmpx_permlane_hazard, + .wmma_128b_insts, }), }; pub const gfx11_generic: CpuModel = .{ @@ -2541,6 +3098,7 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dx10_clamp_and_ieee_mode, .flat_atomic_fadd_f32_inst, .gfx11, .image_insts, @@ -2559,14 +3117,15 @@ pub const cpu = struct { .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .wmma_256b_insts, }), }; pub const gfx1200: CpuModel = .{ .name = "gfx1200", .llvm_name = "gfx1200", .features = featureSet(&[_]Feature{ + .@"1536_physical_vgprs", .addressablelocalmemorysize65536, - .allocate1_5xvgprs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, @@ -2593,32 +3152,42 @@ pub const cpu = struct { .dpp_src1_sgpr, .extended_image_insts, .flat_atomic_fadd_f32_inst, + .formatted_mubuf_insts, .fp8_conversion_insts, .gfx12, .image_insts, .ldsbankcount32, .lerp_inst, .memory_atomic_fadd_f32_denormal_support, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_f16_pseudo_scalar_trans_inline_constants, .nsa_encoding, .packed_tid, .partial_nsa_encoding, .pseudo_scalar_trans, .qsad_insts, + .real_true16, .restricted_soffset, .sad_insts, .salu_float, .scalar_dwordx3_loads, .shader_cycles_hi_lo_registers, + .smem_prefetch_insts, + .swmmac_gfx1200_insts, .vcmpx_permlane_hazard, .waits_before_system_scope_stores, + .wmma_128b_insts, }), }; pub const gfx1201: CpuModel = .{ .name = "gfx1201", .llvm_name = "gfx1201", .features = featureSet(&[_]Feature{ + .@"1536_physical_vgprs", .addressablelocalmemorysize65536, - .allocate1_5xvgprs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, @@ -2645,24 +3214,34 @@ pub const cpu = struct { .dpp_src1_sgpr, .extended_image_insts, .flat_atomic_fadd_f32_inst, + .formatted_mubuf_insts, .fp8_conversion_insts, .gfx12, .image_insts, .ldsbankcount32, .lerp_inst, .memory_atomic_fadd_f32_denormal_support, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_f16_pseudo_scalar_trans_inline_constants, .nsa_encoding, .packed_tid, .partial_nsa_encoding, .pseudo_scalar_trans, .qsad_insts, + .real_true16, .restricted_soffset, .sad_insts, .salu_float, .scalar_dwordx3_loads, .shader_cycles_hi_lo_registers, + .smem_prefetch_insts, + .swmmac_gfx1200_insts, .vcmpx_permlane_hazard, .waits_before_system_scope_stores, + .wmma_128b_insts, }), }; pub const gfx1250: CpuModel = .{ @@ -2678,6 +3257,7 @@ pub const cpu = struct { .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, + .asynccnt, .atomic_buffer_global_pk_add_f16_insts, .atomic_buffer_pk_add_bf16_inst, .atomic_ds_pk_add_16_insts, @@ -2687,6 +3267,7 @@ pub const cpu = struct { .atomic_fmin_fmax_flat_f64, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, + .back_off_barrier, .bf16_cvt_insts, .bf16_pk_insts, .bf16_trans_insts, @@ -2719,12 +3300,18 @@ pub const cpu = struct { .ldsbankcount32, .lerp_inst, .lshl_add_u64_inst, + .mad_nc_64_32_insts, .mad_u32_inst, .max_hard_clause_length_63, .mcast_load_insts, .memory_atomic_fadd_f32_denormal_support, .min3_max3_pkf16, + .min_max_i64_insts, .minimum3_maximum3_pkf16, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .no_f16_pseudo_scalar_trans_inline_constants, .packed_fp32_ops, .packed_tid, .permlane16_swap, @@ -2732,6 +3319,8 @@ pub const cpu = struct { .prng_inst, .pseudo_scalar_trans, .qsad_insts, + .real_true16, + .requires_initial_unclause_vmem, .restricted_soffset, .s_wakeup_barrier_inst, .sad_insts, @@ -2740,17 +3329,24 @@ pub const cpu = struct { .setprio_inc_wg_inst, .setreg_vgpr_msb_fixup, .shader_cycles_hi_lo_registers, + .smem_prefetch_insts, .sramecc_support, + .swmmac_gfx1200_insts, + .swmmac_gfx1250_insts, .tanh_insts, .tensor_cvt_lut_insts, + .trans_coexecution_hazard, .transpose_load_f4f6_insts, + .v_mov_b64_inst, + .v_mul_u64_inst, .vcmpx_permlane_hazard, .vgpr_align2, .vmem_pref_insts, + .vop3px2_increments_va_vdst_twice, .wait_xcnt, .wavefrontsize32, + .wmma_coexecution_hazards, .xnack, - .xnack_support, }), }; pub const gfx1251: CpuModel = .{ @@ -2766,6 +3362,7 @@ pub const cpu = struct { .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, + .asynccnt, .atomic_buffer_global_pk_add_f16_insts, .atomic_buffer_pk_add_bf16_inst, .atomic_ds_pk_add_16_insts, @@ -2775,6 +3372,7 @@ pub const cpu = struct { .atomic_fmin_fmax_flat_f64, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, + .back_off_barrier, .bf16_cvt_insts, .bf16_pk_insts, .bf16_trans_insts, @@ -2800,27 +3398,40 @@ pub const cpu = struct { .fmacf64_inst, .fp8_conversion_insts, .fp8e5m3_insts, + .full_rate_64_ops, .gfx12, .gfx1250_insts, + .gfx1251_gemm_insts, + .gfx125x_lowest_rate_wmma, .globally_addressable_scratch, .kernarg_preload, .lds_barrier_arrive_atomic, .ldsbankcount32, .lerp_inst, .lshl_add_u64_inst, + .mad_nc_64_32_insts, .mad_u32_inst, .max_hard_clause_length_63, .mcast_load_insts, .memory_atomic_fadd_f32_denormal_support, .min3_max3_pkf16, + .min_max_i64_insts, .minimum3_maximum3_pkf16, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .no_f16_pseudo_scalar_trans_inline_constants, .packed_fp32_ops, + .packed_fp64_ops, .packed_tid, + .packed_u64_ops, .permlane16_swap, .pk_add_min_max_insts, .prng_inst, .pseudo_scalar_trans, .qsad_insts, + .real_true16, + .requires_initial_unclause_vmem, .restricted_soffset, .s_wakeup_barrier_inst, .sad_insts, @@ -2828,25 +3439,127 @@ pub const cpu = struct { .scalar_dwordx3_loads, .setprio_inc_wg_inst, .shader_cycles_hi_lo_registers, + .smem_prefetch_insts, .sramecc_support, + .swmmac_gfx1200_insts, + .swmmac_gfx1250_insts, .tanh_insts, .tensor_cvt_lut_insts, + .trans_coexecution_hazard, .transpose_load_f4f6_insts, + .use_add_pc64_inst, + .v_mov_b64_inst, + .v_mul_u64_inst, .vcmpx_permlane_hazard, .vgpr_align2, .vmem_pref_insts, + .vop3px2_increments_va_vdst_twice, .wait_xcnt, .wavefrontsize32, + .wmma_coexecution_hazards, + .xnack, + }), + }; + pub const gfx12_5_generic: CpuModel = .{ + .name = "gfx12_5_generic", + .llvm_name = "gfx12-5-generic", + .features = featureSet(&[_]Feature{ + .@"1024_addressable_vgprs", + .@"45_bit_num_records_buffer_resource", + .@"64_bit_literals", + .add_min_max_insts, + .add_sub_u64_insts, + .addressablelocalmemorysize327680, + .architected_flat_scratch, + .architected_sgprs, + .ashr_pk_insts, + .asynccnt, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_buffer_pk_add_bf16_inst, + .atomic_ds_pk_add_16_insts, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, + .atomic_global_pk_add_bf16_inst, + .back_off_barrier, + .bf16_cvt_insts, + .bf16_pk_insts, + .bf16_trans_insts, + .bitop3_insts, + .clusters, + .cumode, + .cvt_pk_f16_f32_inst, + .d16_write_vgpr32, + .dl_insts, + .dot7_insts, + .dot8_insts, + .dpp_src1_sgpr, + .emulated_system_scope_atomics, + .flat_atomic_fadd_f32_inst, + .flat_buffer_global_fadd_f64_inst, + .flat_gvs_mode, + .fma_mix_bf16_insts, + .fmacf64_inst, + .fp8_conversion_insts, + .fp8e5m3_insts, + .gfx12, + .gfx1250_insts, + .gfx125x_lowest_rate_wmma, + .globally_addressable_scratch, + .kernarg_preload, + .lds_barrier_arrive_atomic, + .ldsbankcount32, + .lshl_add_u64_inst, + .mad_nc_64_32_insts, + .mad_u32_inst, + .max_hard_clause_length_63, + .mcast_load_insts, + .memory_atomic_fadd_f32_denormal_support, + .min3_max3_pkf16, + .min_max_i64_insts, + .minimum3_maximum3_pkf16, + .no_f16_pseudo_scalar_trans_inline_constants, + .packed_fp32_ops, + .packed_tid, + .permlane16_swap, + .pk_add_min_max_insts, + .prng_inst, + .pseudo_scalar_trans, + .real_true16, + .requires_cov6, + .requires_initial_unclause_vmem, + .restricted_soffset, + .s_wakeup_barrier_inst, + .salu_float, + .scalar_dwordx3_loads, + .setprio_inc_wg_inst, + .setreg_vgpr_msb_fixup, + .shader_cycles_hi_lo_registers, + .smem_prefetch_insts, + .sramecc_support, + .tanh_insts, + .tensor_cvt_lut_insts, + .trans_coexecution_hazard, + .transpose_load_f4f6_insts, + .v_mov_b64_inst, + .v_mul_u64_inst, + .vcmpx_permlane_hazard, + .vgpr_align2, + .vmem_pref_insts, + .wait_xcnt, + .wavefrontsize32, + .wmma_coexecution_hazards, .xnack, - .xnack_support, }), }; pub const gfx12_generic: CpuModel = .{ .name = "gfx12_generic", .llvm_name = "gfx12-generic", .features = featureSet(&[_]Feature{ + .@"1536_physical_vgprs", .addressablelocalmemorysize65536, - .allocate1_5xvgprs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, @@ -2873,25 +3586,170 @@ pub const cpu = struct { .dpp_src1_sgpr, .extended_image_insts, .flat_atomic_fadd_f32_inst, + .formatted_mubuf_insts, .fp8_conversion_insts, .gfx12, .image_insts, .ldsbankcount32, .lerp_inst, .memory_atomic_fadd_f32_denormal_support, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_f16_pseudo_scalar_trans_inline_constants, .nsa_encoding, .packed_tid, .partial_nsa_encoding, .pseudo_scalar_trans, .qsad_insts, + .real_true16, .requires_cov6, .restricted_soffset, .sad_insts, .salu_float, .scalar_dwordx3_loads, .shader_cycles_hi_lo_registers, + .smem_prefetch_insts, + .swmmac_gfx1200_insts, .vcmpx_permlane_hazard, .waits_before_system_scope_stores, + .wmma_128b_insts, + }), + }; + pub const gfx1310: CpuModel = .{ + .name = "gfx1310", + .llvm_name = "gfx1310", + .features = featureSet(&[_]Feature{ + .@"1536_physical_vgprs", + .@"64_bit_literals", + .addressablelocalmemorysize65536, + .architected_flat_scratch, + .architected_sgprs, + .ashr_pk_insts, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_buffer_pk_add_bf16_inst, + .atomic_ds_pk_add_16_insts, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, + .atomic_global_pk_add_bf16_inst, + .bf16_cvt_insts, + .bf16_pk_insts, + .bf16_trans_insts, + .bitop3_insts, + .clusters, + .cube_insts, + .cvt_norm_insts, + .cvt_pk_f16_f32_inst, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .dl_insts, + .dot7_insts, + .dot8_insts, + .dpp_src1_sgpr, + .f16bf16_to_fp6bf6_cvt_scale_insts, + .flat_atomic_fadd_f32_inst, + .flat_gvs_mode, + .fma_mix_bf16_insts, + .fmacf64_inst, + .fp8_conversion_insts, + .gfx1250_insts, + .gfx13, + .globally_addressable_scratch, + .ldsbankcount32, + .lerp_inst, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .permlane16_swap, + .prng_inst, + .pseudo_scalar_trans, + .qsad_insts, + .restricted_soffset, + .s_wakeup_barrier_inst, + .sad_insts, + .salu_float, + .scalar_dwordx3_loads, + .shader_cycles_register, + .smem_prefetch_insts, + .tanh_insts, + .tensor_cvt_lut_insts, + .transpose_load_f4f6_insts, + .vcmpx_permlane_hazard, + }), + }; + pub const gfx13_generic: CpuModel = .{ + .name = "gfx13_generic", + .llvm_name = "gfx13-generic", + .features = featureSet(&[_]Feature{ + .@"1536_physical_vgprs", + .@"64_bit_literals", + .addressablelocalmemorysize65536, + .architected_flat_scratch, + .architected_sgprs, + .ashr_pk_insts, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_buffer_pk_add_bf16_inst, + .atomic_ds_pk_add_16_insts, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f64, + .atomic_global_pk_add_bf16_inst, + .bf16_cvt_insts, + .bf16_pk_insts, + .bf16_trans_insts, + .bitop3_insts, + .clusters, + .cube_insts, + .cvt_norm_insts, + .cvt_pk_f16_f32_inst, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .dl_insts, + .dot7_insts, + .dot8_insts, + .dpp_src1_sgpr, + .f16bf16_to_fp6bf6_cvt_scale_insts, + .flat_atomic_fadd_f32_inst, + .flat_gvs_mode, + .fma_mix_bf16_insts, + .fmacf64_inst, + .fp8_conversion_insts, + .gfx1250_insts, + .gfx13, + .globally_addressable_scratch, + .ldsbankcount32, + .lerp_inst, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .permlane16_swap, + .prng_inst, + .pseudo_scalar_trans, + .qsad_insts, + .requires_cov6, + .restricted_soffset, + .s_wakeup_barrier_inst, + .sad_insts, + .salu_float, + .scalar_dwordx3_loads, + .shader_cycles_register, + .smem_prefetch_insts, + .tanh_insts, + .tensor_cvt_lut_insts, + .transpose_load_f4f6_insts, + .vcmpx_permlane_hazard, }), }; pub const gfx600: CpuModel = .{ @@ -2977,7 +3835,7 @@ pub const cpu = struct { .ldsbankcount32, .unpacked_d16_vmem, .volcanic_islands, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx802: CpuModel = .{ @@ -3017,7 +3875,7 @@ pub const cpu = struct { .image_store_d16_bug, .ldsbankcount16, .volcanic_islands, - .xnack_support, + .xnack_on_off_modes, }), }; pub const gfx900: CpuModel = .{ @@ -3175,6 +4033,7 @@ pub const cpu = struct { .packed_tid, .pk_fmac_f16_inst, .sramecc_support, + .tgsplit_support, .vgpr_align2, }), }; @@ -3239,6 +4098,8 @@ pub const cpu = struct { .packed_tid, .pk_fmac_f16_inst, .sramecc_support, + .tgsplit_support, + .v_mov_b64_inst, .vgpr_align2, .xf32_insts, }), @@ -3295,6 +4156,8 @@ pub const cpu = struct { .pk_fmac_f16_inst, .prng_inst, .sramecc_support, + .tgsplit_support, + .v_mov_b64_inst, .vgpr_align2, }), }; @@ -3342,6 +4205,8 @@ pub const cpu = struct { .pk_fmac_f16_inst, .requires_cov6, .sramecc_support, + .tgsplit_support, + .v_mov_b64_inst, .vgpr_align2, }), }; @@ -3452,7 +4317,7 @@ pub const cpu = struct { .image_store_d16_bug, .ldsbankcount16, .volcanic_islands, - .xnack_support, + .xnack_on_off_modes, }), }; pub const tahiti: CpuModel = .{ diff --git a/lib/std/Target/hexagon.zig b/lib/std/Target/hexagon.zig index 2342edacb1bdb089971030a5dc891e1b08bd4ab3..14e1d7725eb0ffb8abf94eacbab0fd9e73f73907 100644 --- a/lib/std/Target/hexagon.zig +++ b/lib/std/Target/hexagon.zig @@ -34,7 +34,41 @@ pub const Feature = enum { nvs, packets, prev65, + reserved_r10, + reserved_r11, + reserved_r12, + reserved_r13, + reserved_r14, + reserved_r15, + reserved_r16, + reserved_r17, + reserved_r18, reserved_r19, + reserved_r20, + reserved_r21, + reserved_r22, + reserved_r23, + reserved_r24, + reserved_r25, + reserved_r26, + reserved_r27, + reserved_r28, + reserved_r6, + reserved_r7, + reserved_r8, + reserved_r9, + scs_reg_r16, + scs_reg_r17, + scs_reg_r18, + scs_reg_r19, + scs_reg_r20, + scs_reg_r21, + scs_reg_r22, + scs_reg_r23, + scs_reg_r24, + scs_reg_r25, + scs_reg_r26, + scs_reg_r27, small_data, tinycore, v5, @@ -241,11 +275,181 @@ pub const all_features = blk: { .description = "Support features deprecated in v65", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.reserved_r10)] = .{ + .llvm_name = "reserved-r10", + .description = "Reserve register R10", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r11)] = .{ + .llvm_name = "reserved-r11", + .description = "Reserve register R11", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r12)] = .{ + .llvm_name = "reserved-r12", + .description = "Reserve register R12", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r13)] = .{ + .llvm_name = "reserved-r13", + .description = "Reserve register R13", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r14)] = .{ + .llvm_name = "reserved-r14", + .description = "Reserve register R14", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r15)] = .{ + .llvm_name = "reserved-r15", + .description = "Reserve register R15", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r16)] = .{ + .llvm_name = "reserved-r16", + .description = "Reserve register R16", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r17)] = .{ + .llvm_name = "reserved-r17", + .description = "Reserve register R17", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r18)] = .{ + .llvm_name = "reserved-r18", + .description = "Reserve register R18", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.reserved_r19)] = .{ .llvm_name = "reserved-r19", .description = "Reserve register R19", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.reserved_r20)] = .{ + .llvm_name = "reserved-r20", + .description = "Reserve register R20", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r21)] = .{ + .llvm_name = "reserved-r21", + .description = "Reserve register R21", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r22)] = .{ + .llvm_name = "reserved-r22", + .description = "Reserve register R22", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r23)] = .{ + .llvm_name = "reserved-r23", + .description = "Reserve register R23", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r24)] = .{ + .llvm_name = "reserved-r24", + .description = "Reserve register R24", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r25)] = .{ + .llvm_name = "reserved-r25", + .description = "Reserve register R25", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r26)] = .{ + .llvm_name = "reserved-r26", + .description = "Reserve register R26", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r27)] = .{ + .llvm_name = "reserved-r27", + .description = "Reserve register R27", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r28)] = .{ + .llvm_name = "reserved-r28", + .description = "Reserve register R28", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r6)] = .{ + .llvm_name = "reserved-r6", + .description = "Reserve register R6", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r7)] = .{ + .llvm_name = "reserved-r7", + .description = "Reserve register R7", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r8)] = .{ + .llvm_name = "reserved-r8", + .description = "Reserve register R8", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserved_r9)] = .{ + .llvm_name = "reserved-r9", + .description = "Reserve register R9", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r16)] = .{ + .llvm_name = "scs-reg-r16", + .description = "Use register R16 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r17)] = .{ + .llvm_name = "scs-reg-r17", + .description = "Use register R17 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r18)] = .{ + .llvm_name = "scs-reg-r18", + .description = "Use register R18 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r19)] = .{ + .llvm_name = "scs-reg-r19", + .description = "Use register R19 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r20)] = .{ + .llvm_name = "scs-reg-r20", + .description = "Use register R20 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r21)] = .{ + .llvm_name = "scs-reg-r21", + .description = "Use register R21 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r22)] = .{ + .llvm_name = "scs-reg-r22", + .description = "Use register R22 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r23)] = .{ + .llvm_name = "scs-reg-r23", + .description = "Use register R23 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r24)] = .{ + .llvm_name = "scs-reg-r24", + .description = "Use register R24 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r25)] = .{ + .llvm_name = "scs-reg-r25", + .description = "Use register R25 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r26)] = .{ + .llvm_name = "scs-reg-r26", + .description = "Use register R26 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.scs_reg_r27)] = .{ + .llvm_name = "scs-reg-r27", + .description = "Use register R27 as the shadow call stack pointer", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.small_data)] = .{ .llvm_name = "small-data", .description = "Allow GP-relative addressing of global variables", diff --git a/lib/std/Target/mips.zig b/lib/std/Target/mips.zig index 532fb7871cfb697c3c707b58d1c4ad0bc81e7fc9..ad19d451abb49fac96c0506fdfe21d66addd76ee 100644 --- a/lib/std/Target/mips.zig +++ b/lib/std/Target/mips.zig @@ -13,6 +13,7 @@ pub const Feature = enum { dspr2, dspr3, eva, + fix_r5900, fp64, fpxx, ginv, @@ -52,6 +53,7 @@ pub const Feature = enum { notraps, p5600, ptr64, + r5900, single_float, soft_float, strict_align, @@ -121,6 +123,11 @@ pub const all_features = blk: { .description = "Mips EVA ASE", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.fix_r5900)] = .{ + .llvm_name = "fix-r5900", + .description = "Enable R5900 short loop erratum fix", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.fp64)] = .{ .llvm_name = "fp64", .description = "Support 64-bit FP registers", @@ -372,6 +379,15 @@ pub const all_features = blk: { .description = "Pointers are 64-bit wide", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.r5900)] = .{ + .llvm_name = "r5900", + .description = "R5900 (PS2 Emotion Engine) Support", + .dependencies = featureSet(&[_]Feature{ + .fix_r5900, + .mips3, + .single_float, + }), + }; result[@backingInt(Feature.single_float)] = .{ .llvm_name = "single-float", .description = "Only supports single precision float", @@ -596,4 +612,11 @@ pub const cpu = struct { .soft_float, }), }; + pub const r5900: CpuModel = .{ + .name = "r5900", + .llvm_name = "r5900", + .features = featureSet(&[_]Feature{ + .r5900, + }), + }; }; diff --git a/lib/std/Target/nvptx.zig b/lib/std/Target/nvptx.zig index 2bd9cda037c90aeb3542d92c1883fba5da333337..493a04b27db4d16d6dcf4a10202881be0f4045dd 100644 --- a/lib/std/Target/nvptx.zig +++ b/lib/std/Target/nvptx.zig @@ -36,6 +36,9 @@ pub const Feature = enum { ptx87, ptx88, ptx90, + ptx91, + ptx92, + ptx93, sm_100, sm_100a, sm_100f, @@ -242,6 +245,21 @@ pub const all_features = blk: { .description = "Use PTX version 90", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.ptx91)] = .{ + .llvm_name = "ptx91", + .description = "Use PTX version 91", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.ptx92)] = .{ + .llvm_name = "ptx92", + .description = "Use PTX version 92", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.ptx93)] = .{ + .llvm_name = "ptx93", + .description = "Use PTX version 93", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.sm_100)] = .{ .llvm_name = "sm_100", .description = "Target SM 100", diff --git a/lib/std/Target/powerpc.zig b/lib/std/Target/powerpc.zig index 14c18791ffd52f94f3c768db72ebf4de13644263..5b0e5034593aef4dcaa9d7826376a2bb4fd03b75 100644 --- a/lib/std/Target/powerpc.zig +++ b/lib/std/Target/powerpc.zig @@ -43,6 +43,7 @@ pub const Feature = enum { fuse_wideimm, fuse_zeromove, fusion, + future_vector, hard_float, htm, icbt, @@ -83,6 +84,7 @@ pub const Feature = enum { spe, stfiwx, two_const_nr, + use_ptrgl_helper, vectors_use_two_units, vsx, }; @@ -342,6 +344,14 @@ pub const all_features = blk: { .description = "Target supports instruction fusion", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.future_vector)] = .{ + .llvm_name = "future-vector", + .description = "Enable Future vector instructions", + .dependencies = featureSet(&[_]Feature{ + .isa_future_instructions, + .power10_vector, + }), + }; result[@backingInt(Feature.hard_float)] = .{ .llvm_name = "hard-float", .description = "Enable floating-point instructions", @@ -441,6 +451,7 @@ pub const all_features = blk: { .description = "32Byte load and store instructions", .dependencies = featureSet(&[_]Feature{ .isa_v30_instructions, + .vsx, }), }; result[@backingInt(Feature.partword_atomics)] = .{ @@ -580,6 +591,11 @@ pub const all_features = blk: { .description = "Requires two constant Newton-Raphson computation", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.use_ptrgl_helper)] = .{ + .llvm_name = "use-ptrgl-helper", + .description = "Use ._ptrgl for indirect calls", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.vectors_use_two_units)] = .{ .llvm_name = "vectors-use-two-units", .description = "Vectors use two units", @@ -803,8 +819,8 @@ pub const cpu = struct { .fuse_logical_add, .fuse_sha3, .fuse_store, + .future_vector, .icbt, - .isa_future_instructions, .isa_v206_instructions, .isel, .ldbrx, @@ -814,7 +830,6 @@ pub const cpu = struct { .partword_atomics, .pcrelative_memops, .popcntd, - .power10_vector, .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, diff --git a/lib/std/Target/riscv.zig b/lib/std/Target/riscv.zig index 495e8629badfb24396e9981eaf2f9e42a3f56819..3f9f11b9e92f174e00d443714357d5cfad59b575 100644 --- a/lib/std/Target/riscv.zig +++ b/lib/std/Target/riscv.zig @@ -8,13 +8,8 @@ pub const Feature = enum { @"32bit", @"64bit", a, - add_load_fusion, - addi_load_fusion, andes45, - auipc_addi_fusion, - auipc_load_fusion, b, - bfext_fusion, c, conditional_cmv_fusion, d, @@ -25,6 +20,7 @@ pub const Feature = enum { disable_postmisched_store_clustering, dlen_factor_2, e, + enable_select_opt, enable_vsetvli_sched_heuristic, exact_asm, experimental, @@ -32,26 +28,57 @@ pub const Feature = enum { experimental_rvm23u32, experimental_smpmpmt, experimental_svukte, - experimental_xrivosvisni, - experimental_xrivosvizip, + experimental_xqccmt, experimental_xsfmclic, experimental_xsfsclic, + experimental_y, experimental_zibi, experimental_zicfilp, experimental_zicfiss, + experimental_zvabd, experimental_zvbc32e, + experimental_zvdot4a8i, + experimental_zvfbdota32f, experimental_zvfbfa, experimental_zvfofp8min, + experimental_zvfqwbdota8f, + experimental_zvfqwdota8f, + experimental_zvfwbdota16bf, + experimental_zvfwdota16bf, experimental_zvkgs, - experimental_zvqdotq, + experimental_zvqwbdota16i, + experimental_zvqwbdota8i, + experimental_zvqwdota16i, + experimental_zvqwdota8i, + experimental_zvvfmm, + experimental_zvvmm, + experimental_zvvmtls, + experimental_zvvmttls, + experimental_zvzip, f, forced_atomics, + fusion_add_load, + fusion_add_mem, + fusion_addi_load, + fusion_auipc_addi, + fusion_auipc_load, + fusion_bfext, + fusion_ld_add, + fusion_logic_imm_reg, + fusion_logic_reg_imm, + fusion_logic_reg_reg, + fusion_lui_addi, + fusion_lui_load, + fusion_mul_add, + fusion_qc_e_li_load_store, + fusion_shift_bit_extract, + fusion_shifted_zextw, + fusion_shxadd_load, + fusion_zexth, + fusion_zextw, h, i, - ld_add_fusion, log_vrgather, - lui_addi_fusion, - lui_load_fusion, m, mips_p8700, no_default_unroll, @@ -67,6 +94,7 @@ pub const Feature = enum { optimized_zero_stride_load, permissive_zalrsc, predictable_select_expensive, + prefer_ascending_load_store, prefer_vsetvli_over_read_vlenb, prefer_w_inst, q, @@ -118,17 +146,16 @@ pub const Feature = enum { sha, shcounterenw, shgatpa, - shifted_zextw_fusion, shlcofideleg, short_forward_branch_ialu, short_forward_branch_iload, short_forward_branch_iminmax, + short_forward_branch_imm, short_forward_branch_imul, shtvala, shvsatpa, shvstvala, shvstvecd, - shxadd_load_fusion, single_element_vec_fp64, smaia, smcdeleg, @@ -165,6 +192,7 @@ pub const Feature = enum { svinval, svnapot, svpbmt, + svrsw60t59b, svvptc, tagged_globals, unaligned_scalar_mem, @@ -174,6 +202,7 @@ pub const Feature = enum { ventana_veyron, vl_dependent_latency, vxrm_pipeline_flush, + xaifet, xandesbfhcvt, xandesperf, xandesvbfhcvt, @@ -181,6 +210,7 @@ pub const Feature = enum { xandesvpackfph, xandesvsinth, xandesvsintload, + xcheriot, xcvalu, xcvbi, xcvbitmanip, @@ -215,6 +245,7 @@ pub const Feature = enum { xsfcease, xsfmm128t, xsfmm16t, + xsfmm32a, xsfmm32a16f, xsfmm32a32f, xsfmm32a8f, @@ -236,6 +267,7 @@ pub const Feature = enum { xsifivecdiscarddlone, xsifivecflushdlone, xsmtvdot, + xsmtvdotii, xtheadba, xtheadbb, xtheadbs, @@ -275,8 +307,6 @@ pub const Feature = enum { zcmp, zcmt, zdinx, - zexth_fusion, - zextw_fusion, zfa, zfbfmin, zfh, @@ -290,6 +320,7 @@ pub const Feature = enum { zicboz, ziccamoa, ziccamoc, + ziccid, ziccif, zicclsm, ziccrse, @@ -301,7 +332,7 @@ pub const Feature = enum { zihintpause, zihpm, zilsd, - zilsd_4byte_align, + zilsd_word_align, zimop, zk, zkn, @@ -382,31 +413,11 @@ pub const all_features = blk: { .zalrsc, }), }; - result[@backingInt(Feature.add_load_fusion)] = .{ - .llvm_name = "add-load-fusion", - .description = "Enable ADD(.UW) + load macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.addi_load_fusion)] = .{ - .llvm_name = "addi-load-fusion", - .description = "Enable ADDI + load macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.andes45)] = .{ .llvm_name = "andes45", .description = "Andes 45-Series processors", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.auipc_addi_fusion)] = .{ - .llvm_name = "auipc-addi-fusion", - .description = "Enable AUIPC+ADDI macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.auipc_load_fusion)] = .{ - .llvm_name = "auipc-load-fusion", - .description = "Enable AUIPC + load macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.b)] = .{ .llvm_name = "b", .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)", @@ -416,11 +427,6 @@ pub const all_features = blk: { .zbs, }), }; - result[@backingInt(Feature.bfext_fusion)] = .{ - .llvm_name = "bfext-fusion", - .description = "Enable SLLI+SRLI (bitfield extract) macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.c)] = .{ .llvm_name = "c", .description = "'C' (Compressed Instructions)", @@ -475,6 +481,11 @@ pub const all_features = blk: { .description = "'E' (Embedded Instruction Set with 16 GPRs)", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.enable_select_opt)] = .{ + .llvm_name = "enable-select-opt", + .description = "Enable the select optimize pass for select loop heuristics", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.enable_vsetvli_sched_heuristic)] = .{ .llvm_name = "enable-vsetvli-sched-heuristic", .description = "Enable vsetvli-based scheduling heuristic", @@ -493,7 +504,12 @@ pub const all_features = blk: { result[@backingInt(Feature.experimental_p)] = .{ .llvm_name = "experimental-p", .description = "'P' ('Base P' (Packed SIMD))", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .zba, + .zbb, + .zicsr, + .zmmul, + }), }; result[@backingInt(Feature.experimental_rvm23u32)] = .{ .llvm_name = "experimental-rvm23u32", @@ -522,15 +538,13 @@ pub const all_features = blk: { .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.experimental_xrivosvisni)] = .{ - .llvm_name = "experimental-xrivosvisni", - .description = "'XRivosVisni' (Rivos Vector Integer Small New)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_xrivosvizip)] = .{ - .llvm_name = "experimental-xrivosvizip", - .description = "'XRivosVizip' (Rivos Vector Register Zips)", - .dependencies = featureSet(&[_]Feature{}), + result[@backingInt(Feature.experimental_xqccmt)] = .{ + .llvm_name = "experimental-xqccmt", + .description = "'Xqccmt' (Qualcomm 16-bit Table Jump)", + .dependencies = featureSet(&[_]Feature{ + .zca, + .zicsr, + }), }; result[@backingInt(Feature.experimental_xsfmclic)] = .{ .llvm_name = "experimental-xsfmclic", @@ -542,6 +556,11 @@ pub const all_features = blk: { .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.experimental_y)] = .{ + .llvm_name = "experimental-y", + .description = "'Y' ('Base Y' (CHERI))", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.experimental_zibi)] = .{ .llvm_name = "experimental-zibi", .description = "'Zibi' (Branch with Immediate)", @@ -562,6 +581,11 @@ pub const all_features = blk: { .zimop, }), }; + result[@backingInt(Feature.experimental_zvabd)] = .{ + .llvm_name = "experimental-zvabd", + .description = "'Zvabd' (Vector Absolute Difference)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.experimental_zvbc32e)] = .{ .llvm_name = "experimental-zvbc32e", .description = "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)", @@ -569,6 +593,20 @@ pub const all_features = blk: { .zve32x, }), }; + result[@backingInt(Feature.experimental_zvdot4a8i)] = .{ + .llvm_name = "experimental-zvdot4a8i", + .description = "'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@backingInt(Feature.experimental_zvfbdota32f)] = .{ + .llvm_name = "experimental-zvfbdota32f", + .description = "'Zvfbdota32f' (FP32 batched dot-product extension)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; result[@backingInt(Feature.experimental_zvfbfa)] = .{ .llvm_name = "experimental-zvfbfa", .description = "'Zvfbfa' (Additional BF16 vector compute support)", @@ -584,6 +622,34 @@ pub const all_features = blk: { .zve32f, }), }; + result[@backingInt(Feature.experimental_zvfqwbdota8f)] = .{ + .llvm_name = "experimental-zvfqwbdota8f", + .description = "'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; + result[@backingInt(Feature.experimental_zvfqwdota8f)] = .{ + .llvm_name = "experimental-zvfqwdota8f", + .description = "'Zvfqwdota8f' (OCP FP8 Dot-Product)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; + result[@backingInt(Feature.experimental_zvfwbdota16bf)] = .{ + .llvm_name = "experimental-zvfwbdota16bf", + .description = "'Zvfwbdota16bf' (BF16 batched dot-product extension)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; + result[@backingInt(Feature.experimental_zvfwdota16bf)] = .{ + .llvm_name = "experimental-zvfwdota16bf", + .description = "'Zvfwdota16bf' (BF16 Dot-Product)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; result[@backingInt(Feature.experimental_zvkgs)] = .{ .llvm_name = "experimental-zvkgs", .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)", @@ -591,9 +657,65 @@ pub const all_features = blk: { .zvkg, }), }; - result[@backingInt(Feature.experimental_zvqdotq)] = .{ - .llvm_name = "experimental-zvqdotq", - .description = "'Zvqdotq' (Vector quad widening 4D Dot Product)", + result[@backingInt(Feature.experimental_zvqwbdota16i)] = .{ + .llvm_name = "experimental-zvqwbdota16i", + .description = "'Zvqwbdota16i' (16-bit integer batched dot-product extension)", + .dependencies = featureSet(&[_]Feature{ + .zve64x, + }), + }; + result[@backingInt(Feature.experimental_zvqwbdota8i)] = .{ + .llvm_name = "experimental-zvqwbdota8i", + .description = "'Zvqwbdota8i' (8-bit integer batched dot-product extension)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@backingInt(Feature.experimental_zvqwdota16i)] = .{ + .llvm_name = "experimental-zvqwdota16i", + .description = "'Zvqwdota16i' (16-bit Integer Dot-Product)", + .dependencies = featureSet(&[_]Feature{ + .zve64x, + }), + }; + result[@backingInt(Feature.experimental_zvqwdota8i)] = .{ + .llvm_name = "experimental-zvqwdota8i", + .description = "'Zvqwdota8i' (8-bit Integer Dot-Product)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@backingInt(Feature.experimental_zvvfmm)] = .{ + .llvm_name = "experimental-zvvfmm", + .description = "'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; + result[@backingInt(Feature.experimental_zvvmm)] = .{ + .llvm_name = "experimental-zvvmm", + .description = "'Zvvmm' (Integer Matrix Multiply-Accumulate)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@backingInt(Feature.experimental_zvvmtls)] = .{ + .llvm_name = "experimental-zvvmtls", + .description = "'Zvvmtls' (Matrix Tile Load/Store)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@backingInt(Feature.experimental_zvvmttls)] = .{ + .llvm_name = "experimental-zvvmttls", + .description = "'Zvvmttls' (Transposing Matrix Tile Load/Store)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@backingInt(Feature.experimental_zvzip)] = .{ + .llvm_name = "experimental-zvzip", + .description = "'Zvzip' (Vector Reordering Structured Data)", .dependencies = featureSet(&[_]Feature{ .zve32x, }), @@ -610,6 +732,101 @@ pub const all_features = blk: { .description = "Assume that lock-free native-width atomics are available", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.fusion_add_load)] = .{ + .llvm_name = "fusion-add-load", + .description = "Enable ADD(.UW) + load macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_add_mem)] = .{ + .llvm_name = "fusion-add-mem", + .description = "Enable ADD+LOAD/STORE macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_addi_load)] = .{ + .llvm_name = "fusion-addi-load", + .description = "Enable ADDI + load macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_auipc_addi)] = .{ + .llvm_name = "fusion-auipc-addi", + .description = "Enable AUIPC+ADDI macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_auipc_load)] = .{ + .llvm_name = "fusion-auipc-load", + .description = "Enable AUIPC + load macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_bfext)] = .{ + .llvm_name = "fusion-bfext", + .description = "Enable SLLI+SRLI (bitfield extract) macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_ld_add)] = .{ + .llvm_name = "fusion-ld-add", + .description = "Enable LD+ADD macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_logic_imm_reg)] = .{ + .llvm_name = "fusion-logic-imm-reg", + .description = "Enable ANDI/ORI/XORI+AND/OR/XOR macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_logic_reg_imm)] = .{ + .llvm_name = "fusion-logic-reg-imm", + .description = "Enable AND/OR/XOR+ANDI/ORI/XORI macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_logic_reg_reg)] = .{ + .llvm_name = "fusion-logic-reg-reg", + .description = "Enable AND/OR/XOR+AND/OR/XOR macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_lui_addi)] = .{ + .llvm_name = "fusion-lui-addi", + .description = "Enable LUI+ADDI macro fusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_lui_load)] = .{ + .llvm_name = "fusion-lui-load", + .description = "Enable LUI + load macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_mul_add)] = .{ + .llvm_name = "fusion-mul-add", + .description = "Enable MUL+ADD macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_qc_e_li_load_store)] = .{ + .llvm_name = "fusion-qc-e-li-load-store", + .description = "Enable QC.E.LI + Load/Store macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_shift_bit_extract)] = .{ + .llvm_name = "fusion-shift-bit-extract", + .description = "Enable SLLI+SRLI/SRAI macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_shifted_zextw)] = .{ + .llvm_name = "fusion-shifted-zextw", + .description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_shxadd_load)] = .{ + .llvm_name = "fusion-shxadd-load", + .description = "Enable SH(1|2|3)ADD(.UW) + load macrofusion", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_zexth)] = .{ + .llvm_name = "fusion-zexth", + .description = "Enable SLLI+SRLI to be fused to zero extension of halfword", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fusion_zextw)] = .{ + .llvm_name = "fusion-zextw", + .description = "Enable SLLI+SRLI to be fused to zero extension of word", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.h)] = .{ .llvm_name = "h", .description = "'H' (Hypervisor)", @@ -620,26 +837,11 @@ pub const all_features = blk: { .description = "'I' (Base Integer Instruction Set)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ld_add_fusion)] = .{ - .llvm_name = "ld-add-fusion", - .description = "Enable LD+ADD macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.log_vrgather)] = .{ .llvm_name = "log-vrgather", .description = "Has vrgather.vv with LMUL*log2(LMUL) latency", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.lui_addi_fusion)] = .{ - .llvm_name = "lui-addi-fusion", - .description = "Enable LUI+ADDI macro fusion", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.lui_load_fusion)] = .{ - .llvm_name = "lui-load-fusion", - .description = "Enable LUI + load macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.m)] = .{ .llvm_name = "m", .description = "'M' (Integer Multiplication and Division)", @@ -654,7 +856,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.no_default_unroll)] = .{ .llvm_name = "no-default-unroll", - .description = "Disable default unroll preference.", + .description = "Disable default unroll preference", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.no_sink_splat_operands)] = .{ @@ -664,7 +866,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.no_trailing_seq_cst_fence)] = .{ .llvm_name = "no-trailing-seq-cst-fence", - .description = "Disable trailing fence for seq-cst store.", + .description = "Disable trailing fence for seq-cst store", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.optimized_nf2_segment_load_store)] = .{ @@ -717,6 +919,11 @@ pub const all_features = blk: { .description = "Prefer likely predicted branches over selects", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.prefer_ascending_load_store)] = .{ + .llvm_name = "prefer-ascending-load-store", + .description = "Prefer ascending load/store order for better clustering and performance", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.prefer_vsetvli_over_read_vlenb)] = .{ .llvm_name = "prefer-vsetvli-over-read-vlenb", .description = "Prefer vsetvli over read vlenb CSR to calculate VLEN", @@ -736,7 +943,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.relax)] = .{ .llvm_name = "relax", - .description = "Enable Linker relaxation.", + .description = "Enable Linker relaxation", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.reserve_x1)] = .{ @@ -1187,7 +1394,7 @@ pub const all_features = blk: { }; result[@backingInt(Feature.save_restore)] = .{ .llvm_name = "save-restore", - .description = "Enable save/restore.", + .description = "Enable save/restore", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.sdext)] = .{ @@ -1224,11 +1431,6 @@ pub const all_features = blk: { .description = "'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.shifted_zextw_fusion)] = .{ - .llvm_name = "shifted-zextw-fusion", - .description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.shlcofideleg)] = .{ .llvm_name = "shlcofideleg", .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)", @@ -1253,6 +1455,13 @@ pub const all_features = blk: { .short_forward_branch_ialu, }), }; + result[@backingInt(Feature.short_forward_branch_imm)] = .{ + .llvm_name = "short-forward-branch-imm", + .description = "Enable short forward branch optimization for branches with immediates", + .dependencies = featureSet(&[_]Feature{ + .short_forward_branch_ialu, + }), + }; result[@backingInt(Feature.short_forward_branch_imul)] = .{ .llvm_name = "short-forward-branch-imul", .description = "Enable short forward branch optimization for MUL instruction", @@ -1280,11 +1489,6 @@ pub const all_features = blk: { .description = "'Shvstvecd' (vstvec supports Direct mode)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.shxadd_load_fusion)] = .{ - .llvm_name = "shxadd-load-fusion", - .description = "Enable SH(1|2|3)ADD(.UW) + load macrofusion", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.single_element_vec_fp64)] = .{ .llvm_name = "single-element-vec-fp64", .description = "Certain vector FP64 operations produce a single result element per cycle", @@ -1473,6 +1677,11 @@ pub const all_features = blk: { .description = "'Svpbmt' (Page-Based Memory Types)", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.svrsw60t59b)] = .{ + .llvm_name = "svrsw60t59b", + .description = "'Svrsw60t59b' (PTE Reserved-for-Software Bits 60-59)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.svvptc)] = .{ .llvm_name = "svvptc", .description = "'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)", @@ -1521,6 +1730,13 @@ pub const all_features = blk: { .description = "VXRM writes causes pipeline flush", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.xaifet)] = .{ + .llvm_name = "xaifet", + .description = "'XAIFET' (AI Foundry ET Extension)", + .dependencies = featureSet(&[_]Feature{ + .f, + }), + }; result[@backingInt(Feature.xandesbfhcvt)] = .{ .llvm_name = "xandesbfhcvt", .description = "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)", @@ -1568,6 +1784,15 @@ pub const all_features = blk: { .zve32x, }), }; + result[@backingInt(Feature.xcheriot)] = .{ + .llvm_name = "xcheriot", + .description = "'XCheriot' (CHERIoT extension)", + .dependencies = featureSet(&[_]Feature{ + .e, + .m, + .zca, + }), + }; result[@backingInt(Feature.xcvalu)] = .{ .llvm_name = "xcvalu", .description = "'XCValu' (CORE-V ALU Operations)", @@ -1787,6 +2012,15 @@ pub const all_features = blk: { .zvl64b, }), }; + result[@backingInt(Feature.xsfmm32a)] = .{ + .llvm_name = "xsfmm32a", + .description = "'XSfmm32a' (TEW=32-bit accumulation operands - int: 8b; float: fp16, bf16, fp32)", + .dependencies = featureSet(&[_]Feature{ + .xsfmm32a16f, + .xsfmm32a32f, + .xsfmm32a8i, + }), + }; result[@backingInt(Feature.xsfmm32a16f)] = .{ .llvm_name = "xsfmm32a16f", .description = "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF))", @@ -1938,6 +2172,13 @@ pub const all_features = blk: { .zve32f, }), }; + result[@backingInt(Feature.xsmtvdotii)] = .{ + .llvm_name = "xsmtvdotii", + .description = "'XSMTVDotII' (SpacemiT Vector Extension for Matrix 2.0)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; result[@backingInt(Feature.xtheadba)] = .{ .llvm_name = "xtheadba", .description = "'XTHeadBa' (T-Head address calculation instructions)", @@ -2069,7 +2310,9 @@ pub const all_features = blk: { result[@backingInt(Feature.zbc)] = .{ .llvm_name = "zbc", .description = "'Zbc' (Carry-Less Multiplication)", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .zbkc, + }), }; result[@backingInt(Feature.zbkb)] = .{ .llvm_name = "zbkb", @@ -2165,16 +2408,6 @@ pub const all_features = blk: { .zfinx, }), }; - result[@backingInt(Feature.zexth_fusion)] = .{ - .llvm_name = "zexth-fusion", - .description = "Enable SLLI+SRLI to be fused to zero extension of halfword", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.zextw_fusion)] = .{ - .llvm_name = "zextw-fusion", - .description = "Enable SLLI+SRLI to be fused to zero extension of word", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.zfa)] = .{ .llvm_name = "zfa", .description = "'Zfa' (Additional Floating-Point)", @@ -2254,6 +2487,13 @@ pub const all_features = blk: { .description = "'Ziccamoc' (Main Memory Supports Atomics in Zacas)", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.ziccid)] = .{ + .llvm_name = "ziccid", + .description = "'Ziccid' (Instruction/Data Coherence and Consistency)", + .dependencies = featureSet(&[_]Feature{ + .ziccif, + }), + }; result[@backingInt(Feature.ziccif)] = .{ .llvm_name = "ziccif", .description = "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)", @@ -2313,8 +2553,8 @@ pub const all_features = blk: { .description = "'Zilsd' (Load/Store Pair Instructions)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.zilsd_4byte_align)] = .{ - .llvm_name = "zilsd-4byte-align", + result[@backingInt(Feature.zilsd_word_align)] = .{ + .llvm_name = "zilsd-word-align", .description = "Allow 4-byte alignment for Zilsd LD/SD instructions", .dependencies = featureSet(&[_]Feature{}), }; @@ -2543,6 +2783,7 @@ pub const all_features = blk: { .description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", .dependencies = featureSet(&[_]Feature{ .zve64x, + .zvknha, }), }; result[@backingInt(Feature.zvks)] = .{ @@ -2681,6 +2922,16 @@ pub const all_features = blk: { }; pub const cpu = struct { + pub const an_erbium: CpuModel = .{ + .name = "an_erbium", + .llvm_name = "an-erbium", + .features = featureSet(&[_]Feature{ + .@"64bit", + .c, + .m, + .xaifet, + }), + }; pub const andes_45_series: CpuModel = .{ .name = "andes_45_series", .llvm_name = "andes-45-series", @@ -2833,6 +3084,16 @@ pub const cpu = struct { .m, }), }; + pub const et_soc1: CpuModel = .{ + .name = "et_soc1", + .llvm_name = "et-soc1", + .features = featureSet(&[_]Feature{ + .@"64bit", + .c, + .m, + .xaifet, + }), + }; pub const generic: CpuModel = .{ .name = "generic", .llvm_name = "generic", @@ -2848,6 +3109,7 @@ pub const cpu = struct { .llvm_name = "generic-rv32", .features = featureSet(&[_]Feature{ .@"32bit", + .enable_select_opt, .i, .optimized_nf2_segment_load_store, }), @@ -2857,6 +3119,7 @@ pub const cpu = struct { .llvm_name = "generic-rv64", .features = featureSet(&[_]Feature{ .@"64bit", + .enable_select_opt, .i, .optimized_nf2_segment_load_store, }), @@ -3020,13 +3283,13 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, .d, + .fusion_auipc_addi, + .fusion_lui_addi, .i, - .lui_addi_fusion, .m, .no_default_unroll, .unaligned_scalar_mem, @@ -3055,12 +3318,12 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, + .fusion_auipc_addi, + .fusion_lui_addi, .i, - .lui_addi_fusion, .m, .no_default_unroll, .no_sink_splat_operands, @@ -3099,12 +3362,13 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .auipc_addi_fusion, .c, .conditional_cmv_fusion, .d, + .enable_select_opt, + .fusion_auipc_addi, + .fusion_lui_addi, .i, - .lui_addi_fusion, .m, .no_default_unroll, .use_postra_scheduler, @@ -3119,12 +3383,12 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, + .fusion_auipc_addi, + .fusion_lui_addi, .i, - .lui_addi_fusion, .m, .no_default_unroll, .no_sink_splat_operands, @@ -3155,18 +3419,18 @@ pub const cpu = struct { .zvksg, }), }; - pub const sifive_p870: CpuModel = .{ - .name = "sifive_p870", - .llvm_name = "sifive-p870", + pub const sifive_p870_d: CpuModel = .{ + .name = "sifive_p870_d", + .llvm_name = "sifive-p870-d", .features = featureSet(&[_]Feature{ .@"64bit", .a, - .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, + .fusion_auipc_addi, + .fusion_lui_addi, .i, - .lui_addi_fusion, .m, .no_default_unroll, .no_sink_splat_operands, @@ -3294,6 +3558,103 @@ pub const cpu = struct { .zifencei, }), }; + pub const sifive_x160: CpuModel = .{ + .name = "sifive_x160", + .llvm_name = "sifive-x160", + .features = featureSet(&[_]Feature{ + .@"32bit", + .a, + .b, + .c, + .dlen_factor_2, + .experimental_zicfilp, + .experimental_zvdot4a8i, + .experimental_zvfbfa, + .i, + .m, + .no_default_unroll, + .optimized_nf2_segment_load_store, + .optimized_zero_stride_load, + .short_forward_branch_ialu, + .use_postra_scheduler, + .vl_dependent_latency, + .xsfcease, + .zawrs, + .zce, + .zcf, + .zcmop, + .zfa, + .zfh, + .zicbom, + .zicbop, + .zicboz, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, + .zvfbfwma, + .zvfh, + .zvkt, + .zvl128b, + }), + }; + pub const sifive_x180: CpuModel = .{ + .name = "sifive_x180", + .llvm_name = "sifive-x180", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .dlen_factor_2, + .experimental_zicfilp, + .experimental_zvdot4a8i, + .experimental_zvfbfa, + .i, + .m, + .no_default_unroll, + .optimized_nf2_segment_load_store, + .optimized_zero_stride_load, + .short_forward_branch_ialu, + .use_postra_scheduler, + .v, + .vl_dependent_latency, + .xsfcease, + .xsfvfbfexp16e, + .xsfvfexp16e, + .xsfvfexp32e, + .xsfvfexpa, + .xsifivecflushdlone, + .za64rs, + .zawrs, + .zcb, + .zcd, + .zcmop, + .zfa, + .zfh, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .ziccrse, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, + .zvfbfwma, + .zvkt, + }), + }; pub const sifive_x280: CpuModel = .{ .name = "sifive_x280", .llvm_name = "sifive-x280", @@ -3372,7 +3733,7 @@ pub const cpu = struct { }; pub const spacemit_a100: CpuModel = .{ .name = "spacemit_a100", - .llvm_name = null, + .llvm_name = "spacemit-a100", .features = featureSet(&[_]Feature{ .@"64bit", .a, @@ -3405,10 +3766,10 @@ pub const cpu = struct { .unaligned_scalar_mem, .v, .vxrm_pipeline_flush, + .xsmtvdotii, .za64rs, .zawrs, .zbc, - .zbkc, .zcb, .zcmop, .zfa, @@ -3433,7 +3794,6 @@ pub const cpu = struct { .zvfbfwma, .zvfh, .zvkng, - .zvknha, .zvksc, .zvksg, .zvl1024b, @@ -3441,27 +3801,75 @@ pub const cpu = struct { }; pub const spacemit_x100: CpuModel = .{ .name = "spacemit_x100", - .llvm_name = null, + .llvm_name = "spacemit-x100", .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, .dlen_factor_2, + .fusion_add_mem, + .fusion_logic_imm_reg, + .fusion_logic_reg_imm, + .fusion_logic_reg_reg, + .fusion_mul_add, + .fusion_shift_bit_extract, + .i, + .m, + .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_nf3_segment_load_store, .optimized_nf4_segment_load_store, - .rva23s64, + .sha, .smepmp, .smnpm, .smstateen, + .ssccptr, + .sscofpmf, + .sscounterenw, + .ssnpm, .sspm, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .supm, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, .unaligned_scalar_mem, + .v, .vxrm_pipeline_flush, .xsmtvdot, + .za64rs, + .zawrs, .zbc, - .zbkc, + .zcb, + .zcmop, + .zfa, .zfh, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, .zvfbfwma, .zvfh, .zvkng, - .zvknha, .zvksc, .zvksg, .zvl256b, @@ -3476,11 +3884,13 @@ pub const cpu = struct { .b, .c, .dlen_factor_2, + .enable_select_opt, .i, .m, .optimized_nf2_segment_load_store, .optimized_nf3_segment_load_store, .optimized_nf4_segment_load_store, + .prefer_ascending_load_store, .ssccptr, .sscofpmf, .sscounterenw, @@ -3498,7 +3908,6 @@ pub const cpu = struct { .xsmtvdot, .za64rs, .zbc, - .zbkc, .zfh, .zic64b, .zicbom, @@ -3652,9 +4061,9 @@ pub const cpu = struct { .zkn, }), }; - pub const tt_ascalon_d8: CpuModel = .{ - .name = "tt_ascalon_d8", - .llvm_name = "tt-ascalon-d8", + pub const tt_ascalon_x: CpuModel = .{ + .name = "tt_ascalon_x", + .llvm_name = "tt-ascalon-x", .features = featureSet(&[_]Feature{ .@"64bit", .a, @@ -3674,6 +4083,10 @@ pub const cpu = struct { .optimized_zero_stride_load, .sha, .smaia, + .smmpm, + .smnpm, + .smrnmi, + .smstateen, .ssaia, .ssccptr, .sscofpmf, @@ -3715,6 +4128,7 @@ pub const cpu = struct { .zihintpause, .zihpm, .zimop, + .zkr, .zkt, .zvbb, .zvbc, @@ -3730,27 +4144,27 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .add_load_fusion, - .auipc_addi_fusion, - .auipc_load_fusion, .c, .d, .disable_misched_load_clustering, .disable_postmisched_load_clustering, .disable_postmisched_store_clustering, + .fusion_add_load, + .fusion_auipc_addi, + .fusion_auipc_load, + .fusion_lui_addi, + .fusion_lui_load, + .fusion_shifted_zextw, + .fusion_zexth, + .fusion_zextw, .i, - .lui_addi_fusion, - .lui_load_fusion, .m, - .shifted_zextw_fusion, .ventana_veyron, .xventanacondops, .zba, .zbb, .zbc, .zbs, - .zexth_fusion, - .zextw_fusion, .zicbom, .zicbop, .zicboz, @@ -3768,11 +4182,13 @@ pub const cpu = struct { .a, .b, .c, + .fusion_shifted_zextw, + .fusion_zexth, + .fusion_zextw, .i, .m, .no_default_unroll, .sha, - .shifted_zextw_fusion, .smaia, .smcsrind, .smdbltrp, @@ -3806,8 +4222,6 @@ pub const cpu = struct { .zbc, .zcb, .zcmop, - .zexth_fusion, - .zextw_fusion, .zfa, .zfh, .zic64b, @@ -3841,17 +4255,17 @@ pub const cpu = struct { .a, .c, .d, + .fusion_shifted_zextw, + .fusion_zexth, + .fusion_zextw, .i, .m, .no_default_unroll, - .shifted_zextw_fusion, .svinval, .zba, .zbb, .zbc, .zbs, - .zexth_fusion, - .zextw_fusion, .zicbom, .zicboz, .zifencei, @@ -3860,4 +4274,129 @@ pub const cpu = struct { .zksh, }), }; + pub const xt_c910v2: CpuModel = .{ + .name = "xt_c910v2", + .llvm_name = "xt-c910v2", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .i, + .m, + .ssccptr, + .sscofpmf, + .sscounterenw, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .unaligned_scalar_mem, + .use_postra_scheduler, + .vxrm_pipeline_flush, + .xtheadba, + .xtheadbb, + .xtheadbs, + .xtheadcmo, + .xtheadcondmov, + .xtheadfmemidx, + .xtheadmac, + .xtheadmemidx, + .xtheadmempair, + .xtheadsync, + .za64rs, + .zawrs, + .zbc, + .zcb, + .zcd, + .zcmop, + .zfa, + .zfbfmin, + .zfh, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + }), + }; + pub const xt_c920v2: CpuModel = .{ + .name = "xt_c920v2", + .llvm_name = "xt-c920v2", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .i, + .m, + .ssccptr, + .sscofpmf, + .sscounterenw, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .unaligned_scalar_mem, + .use_postra_scheduler, + .vxrm_pipeline_flush, + .xtheadba, + .xtheadbb, + .xtheadbs, + .xtheadcmo, + .xtheadcondmov, + .xtheadfmemidx, + .xtheadmac, + .xtheadmemidx, + .xtheadmempair, + .xtheadsync, + .xtheadvdot, + .za64rs, + .zawrs, + .zbc, + .zcb, + .zcd, + .zcmop, + .zfa, + .zfh, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvfbfwma, + .zvfh, + }), + }; }; diff --git a/lib/std/Target/sparc.zig b/lib/std/Target/sparc.zig index 11080ecb6a8fbe3891a0997aa963ced516e00861..4b303a133d36354afe1b2dec477f620e77978afa 100644 --- a/lib/std/Target/sparc.zig +++ b/lib/std/Target/sparc.zig @@ -462,6 +462,7 @@ pub const cpu = struct { .name = "leon3", .llvm_name = "leon3", .features = featureSet(&[_]Feature{ + .hasleoncasa, .hasumacsmac, .leon, }), diff --git a/lib/std/Target/wasm.zig b/lib/std/Target/wasm.zig index 4f1df4e2720408c5f9cec0257ff89a648f135df5..8e8eb370c4a5a3b6e79e4d0c254046f0f9e4b659 100644 --- a/lib/std/Target/wasm.zig +++ b/lib/std/Target/wasm.zig @@ -19,6 +19,7 @@ pub const Feature = enum { nontrapping_bulk_memory_len0, nontrapping_fptoint, reference_types, + relaxed_atomics, relaxed_simd, sign_ext, simd128, @@ -60,7 +61,10 @@ pub const all_features = blk: { result[@backingInt(Feature.exception_handling)] = .{ .llvm_name = "exception-handling", .description = "Enable Wasm exception handling", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .multivalue, + .reference_types, + }), }; result[@backingInt(Feature.extended_const)] = .{ .llvm_name = "extended-const", @@ -75,7 +79,9 @@ pub const all_features = blk: { result[@backingInt(Feature.gc)] = .{ .llvm_name = "gc", .description = "Enable wasm gc", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .reference_types, + }), }; result[@backingInt(Feature.multimemory)] = .{ .llvm_name = "multimemory", @@ -111,6 +117,11 @@ pub const all_features = blk: { .call_indirect_overlong, }), }; + result[@backingInt(Feature.relaxed_atomics)] = .{ + .llvm_name = "relaxed-atomics", + .description = "Enable relaxed-atomics proposal", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.relaxed_simd)] = .{ .llvm_name = "relaxed-simd", .description = "Enable relaxed-simd instructions", @@ -156,10 +167,8 @@ pub const cpu = struct { .fp16, .gc, .multimemory, - .multivalue, .mutable_globals, .nontrapping_fptoint, - .reference_types, .relaxed_simd, .sign_ext, .simd128, diff --git a/lib/std/Target/x86.zig b/lib/std/Target/x86.zig index 8e6823918c41ddd951082d5c4d117011fd532783..0bcc2638f16f0bb4cb553d35d3b94a3f7962b7ed 100644 --- a/lib/std/Target/x86.zig +++ b/lib/std/Target/x86.zig @@ -20,7 +20,6 @@ pub const Feature = enum { amx_fp8, amx_int8, amx_movrs, - amx_tf32, amx_tile, avx, avx10_1, @@ -28,6 +27,7 @@ pub const Feature = enum { avx2, avx512bf16, avx512bitalg, + avx512bmm, avx512bw, avx512cd, avx512dq, @@ -67,13 +67,17 @@ pub const Feature = enum { enqcmd, ermsb, f16c, + false_deps_bls, + false_deps_compress, + false_deps_expand, false_deps_getmant, - false_deps_lzcnt_tzcnt, + false_deps_lzcnt, false_deps_mulc, false_deps_mullq, false_deps_perm, false_deps_popcnt, false_deps_range, + false_deps_tzcnt, fast_11bytenop, fast_15bytenop, fast_7bytenop, @@ -105,6 +109,7 @@ pub const Feature = enum { idivq_to_divl, inline_asm_use_gpr32, invpcid, + jmpabs, kl, lea_sp, lea_uses_ag, @@ -137,6 +142,7 @@ pub const Feature = enum { prefer_legacy_setcc, prefer_mask_registers, prefer_movmsk_over_vtest, + prefer_ndd_mem, prefer_no_gather, prefer_no_scatter, prefetchi, @@ -149,6 +155,31 @@ pub const Feature = enum { rdpru, rdrnd, rdseed, + reserve_edi, + reserve_r10, + reserve_r11, + reserve_r12, + reserve_r13, + reserve_r14, + reserve_r15, + reserve_r16, + reserve_r17, + reserve_r18, + reserve_r19, + reserve_r20, + reserve_r21, + reserve_r22, + reserve_r23, + reserve_r24, + reserve_r25, + reserve_r26, + reserve_r27, + reserve_r28, + reserve_r29, + reserve_r30, + reserve_r31, + reserve_r8, + reserve_r9, retpoline, retpoline_external_thunk, retpoline_indirect_branches, @@ -164,6 +195,7 @@ pub const Feature = enum { shstk, slow_3ops_lea, slow_incdec, + slow_indirect_call, slow_lea, slow_pmaddwd, slow_pmulld, @@ -313,13 +345,6 @@ pub const all_features = blk: { .amx_tile, }), }; - result[@backingInt(Feature.amx_tf32)] = .{ - .llvm_name = "amx-tf32", - .description = "Support AMX-TF32 instructions", - .dependencies = featureSet(&[_]Feature{ - .amx_tile, - }), - }; result[@backingInt(Feature.amx_tile)] = .{ .llvm_name = "amx-tile", .description = "Support AMX-TILE instructions", @@ -377,6 +402,13 @@ pub const all_features = blk: { .avx512bw, }), }; + result[@backingInt(Feature.avx512bmm)] = .{ + .llvm_name = "avx512bmm", + .description = "Enable AVX512 Bit Matrix Multiply", + .dependencies = featureSet(&[_]Feature{ + .avx512bw, + }), + }; result[@backingInt(Feature.avx512bw)] = .{ .llvm_name = "avx512bw", .description = "Enable AVX-512 Byte and Word Instructions", @@ -616,14 +648,29 @@ pub const all_features = blk: { .avx, }), }; + result[@backingInt(Feature.false_deps_bls)] = .{ + .llvm_name = "false-deps-bls", + .description = "BLSR/BLSI/BLSMSK have a false dependency on dest register", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.false_deps_compress)] = .{ + .llvm_name = "false-deps-compress", + .description = "V[P]COMPRESSPD/PS/Q/D/W/B with zero-masking has a false dependency on dest register", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.false_deps_expand)] = .{ + .llvm_name = "false-deps-expand", + .description = "V[P]EXPANDPD/PS/Q/D/W/B with zero-masking has a false dependency on dest register", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.false_deps_getmant)] = .{ .llvm_name = "false-deps-getmant", .description = "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a false dependency on dest register", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.false_deps_lzcnt_tzcnt)] = .{ - .llvm_name = "false-deps-lzcnt-tzcnt", - .description = "LZCNT/TZCNT have a false dependency on dest register", + result[@backingInt(Feature.false_deps_lzcnt)] = .{ + .llvm_name = "false-deps-lzcnt", + .description = "LZCNT has a false dependency on dest register", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.false_deps_mulc)] = .{ @@ -651,6 +698,11 @@ pub const all_features = blk: { .description = "VRANGEPD/PS/SD/SS has a false dependency on dest register", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.false_deps_tzcnt)] = .{ + .llvm_name = "false-deps-tzcnt", + .description = "TZCNT has a false dependency on dest register", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.fast_11bytenop)] = .{ .llvm_name = "fast-11bytenop", .description = "Target can quickly decode up to 11 byte NOPs", @@ -813,6 +865,11 @@ pub const all_features = blk: { .description = "Invalidate Process-Context Identifier", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.jmpabs)] = .{ + .llvm_name = "jmpabs", + .description = "Support 64-bit absolute JMP", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.kl)] = .{ .llvm_name = "kl", .description = "Support Key Locker kl Instructions", @@ -977,6 +1034,11 @@ pub const all_features = blk: { .description = "Prefer movmsk over vtest instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.prefer_ndd_mem)] = .{ + .llvm_name = "prefer-ndd-mem", + .description = "Prefer NDD memory addressing", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.prefer_no_gather)] = .{ .llvm_name = "prefer-no-gather", .description = "Prefer no gather instructions", @@ -1037,6 +1099,131 @@ pub const all_features = blk: { .description = "Support RDSEED instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.reserve_edi)] = .{ + .llvm_name = "reserve-edi", + .description = "Reserve EDI, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r10)] = .{ + .llvm_name = "reserve-r10", + .description = "Reserve R10, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r11)] = .{ + .llvm_name = "reserve-r11", + .description = "Reserve R11, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r12)] = .{ + .llvm_name = "reserve-r12", + .description = "Reserve R12, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r13)] = .{ + .llvm_name = "reserve-r13", + .description = "Reserve R13, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r14)] = .{ + .llvm_name = "reserve-r14", + .description = "Reserve R14, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r15)] = .{ + .llvm_name = "reserve-r15", + .description = "Reserve R15, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r16)] = .{ + .llvm_name = "reserve-r16", + .description = "Reserve R16, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r17)] = .{ + .llvm_name = "reserve-r17", + .description = "Reserve R17, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r18)] = .{ + .llvm_name = "reserve-r18", + .description = "Reserve R18, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r19)] = .{ + .llvm_name = "reserve-r19", + .description = "Reserve R19, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r20)] = .{ + .llvm_name = "reserve-r20", + .description = "Reserve R20, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r21)] = .{ + .llvm_name = "reserve-r21", + .description = "Reserve R21, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r22)] = .{ + .llvm_name = "reserve-r22", + .description = "Reserve R22, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r23)] = .{ + .llvm_name = "reserve-r23", + .description = "Reserve R23, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r24)] = .{ + .llvm_name = "reserve-r24", + .description = "Reserve R24, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r25)] = .{ + .llvm_name = "reserve-r25", + .description = "Reserve R25, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r26)] = .{ + .llvm_name = "reserve-r26", + .description = "Reserve R26, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r27)] = .{ + .llvm_name = "reserve-r27", + .description = "Reserve R27, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r28)] = .{ + .llvm_name = "reserve-r28", + .description = "Reserve R28, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r29)] = .{ + .llvm_name = "reserve-r29", + .description = "Reserve R29, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r30)] = .{ + .llvm_name = "reserve-r30", + .description = "Reserve R30, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r31)] = .{ + .llvm_name = "reserve-r31", + .description = "Reserve R31, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r8)] = .{ + .llvm_name = "reserve-r8", + .description = "Reserve R8, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reserve_r9)] = .{ + .llvm_name = "reserve-r9", + .description = "Reserve R9, making it unavailable as a GPR", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.retpoline)] = .{ .llvm_name = "retpoline", .description = "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", @@ -1123,6 +1310,11 @@ pub const all_features = blk: { .description = "INC and DEC instructions are slower than ADD and SUB", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.slow_indirect_call)] = .{ + .llvm_name = "slow-indirect-call", + .description = "Indirect calls from memory are slow", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.slow_lea)] = .{ .llvm_name = "slow-lea", .description = "LEA instruction with certain arguments is slow", @@ -2039,8 +2231,9 @@ pub const cpu = struct { .cx16, .ermsb, .f16c, - .false_deps_lzcnt_tzcnt, + .false_deps_lzcnt, .false_deps_popcnt, + .false_deps_tzcnt, .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -2159,6 +2352,239 @@ pub const cpu = struct { .x87, }), }; + pub const c86_4g_m4: CpuModel = .{ + .name = "c86_4g_m4", + .llvm_name = "c86-4g-m4", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .aes, + .allow_light_256_bit, + .avx2, + .bmi, + .bmi2, + .clflushopt, + .clzero, + .cmov, + .cx16, + .f16c, + .fast_15bytenop, + .fast_bextr, + .fast_imm16, + .fast_lzcnt, + .fast_movbe, + .fast_scalar_fsqrt, + .fast_scalar_shift_masks, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fma, + .fsgsbase, + .fxsr, + .idivq_to_divl, + .lzcnt, + .mmx, + .movbe, + .mwaitx, + .nopl, + .pclmul, + .popcnt, + .prfchw, + .rdrnd, + .rdseed, + .sahf, + .sbb_dep_breaking, + .sha, + .slow_shld, + .sse4a, + .vzeroupper, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; + pub const c86_4g_m6: CpuModel = .{ + .name = "c86_4g_m6", + .llvm_name = "c86-4g-m6", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .aes, + .allow_light_256_bit, + .avx2, + .bmi, + .bmi2, + .clflushopt, + .clzero, + .cmov, + .cx16, + .f16c, + .fast_15bytenop, + .fast_bextr, + .fast_imm16, + .fast_lzcnt, + .fast_movbe, + .fast_scalar_fsqrt, + .fast_scalar_shift_masks, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fma, + .fsgsbase, + .fxsr, + .idivq_to_divl, + .lzcnt, + .mmx, + .movbe, + .mwaitx, + .nopl, + .pclmul, + .popcnt, + .prfchw, + .rdrnd, + .rdseed, + .sahf, + .sbb_dep_breaking, + .sha, + .slow_shld, + .sse4a, + .vzeroupper, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; + pub const c86_4g_m7: CpuModel = .{ + .name = "c86_4g_m7", + .llvm_name = "c86-4g-m7", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .allow_light_256_bit, + .avx512bf16, + .avx512bitalg, + .avx512cd, + .avx512dq, + .avx512ifma, + .avx512vbmi, + .avx512vbmi2, + .avx512vl, + .avx512vnni, + .avx512vpopcntdq, + .bmi, + .bmi2, + .branchfusion, + .clflushopt, + .clwb, + .clzero, + .cmov, + .cx16, + .fast_15bytenop, + .fast_bextr, + .fast_imm16, + .fast_lzcnt, + .fast_movbe, + .fast_scalar_fsqrt, + .fast_scalar_shift_masks, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fsgsbase, + .fxsr, + .gfni, + .idivq_to_divl, + .lzcnt, + .mmx, + .movbe, + .mwaitx, + .nopl, + .popcnt, + .prefer_256_bit, + .prefer_no_gather, + .prefer_no_scatter, + .prfchw, + .rdrnd, + .rdseed, + .sahf, + .sbb_dep_breaking, + .sha, + .slow_shld, + .sse4a, + .vaes, + .vpclmulqdq, + .vzeroupper, + .wbnoinvd, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; + pub const c86_4g_m8: CpuModel = .{ + .name = "c86_4g_m8", + .llvm_name = "c86-4g-m8", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .allow_light_256_bit, + .avx512bf16, + .avx512bitalg, + .avx512cd, + .avx512dq, + .avx512ifma, + .avx512vbmi, + .avx512vbmi2, + .avx512vl, + .avx512vnni, + .avx512vpopcntdq, + .bmi, + .bmi2, + .branchfusion, + .clflushopt, + .clwb, + .clzero, + .cmov, + .cx16, + .fast_15bytenop, + .fast_bextr, + .fast_imm16, + .fast_lzcnt, + .fast_movbe, + .fast_scalar_fsqrt, + .fast_scalar_shift_masks, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fsgsbase, + .fxsr, + .gfni, + .idivq_to_divl, + .lzcnt, + .mmx, + .movbe, + .mwaitx, + .nopl, + .popcnt, + .prefer_256_bit, + .prefer_no_gather, + .prefer_no_scatter, + .prfchw, + .rdrnd, + .rdseed, + .sahf, + .sbb_dep_breaking, + .sha, + .shstk, + .slow_shld, + .sse4a, + .vaes, + .vpclmulqdq, + .vzeroupper, + .wbnoinvd, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; pub const cannonlake: CpuModel = .{ .name = "cannonlake", .llvm_name = "cannonlake", @@ -2467,7 +2893,6 @@ pub const cpu = struct { .amx_fp8, .amx_int8, .amx_movrs, - .amx_tf32, .avx10_2, .avxifma, .avxneconvert, @@ -2505,6 +2930,7 @@ pub const cpu = struct { .gfni, .idivq_to_divl, .invpcid, + .jmpabs, .lzcnt, .macrofusion, .mmx, @@ -2523,6 +2949,7 @@ pub const cpu = struct { .popcnt, .ppx, .prefer_256_bit, + .prefer_legacy_setcc, .prefetchi, .prfchw, .ptwrite, @@ -3056,8 +3483,9 @@ pub const cpu = struct { .cx16, .ermsb, .f16c, - .false_deps_lzcnt_tzcnt, + .false_deps_lzcnt, .false_deps_popcnt, + .false_deps_tzcnt, .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -3679,6 +4107,7 @@ pub const cpu = struct { .hreset, .idivq_to_divl, .invpcid, + .jmpabs, .lzcnt, .macrofusion, .mmx, @@ -3696,6 +4125,7 @@ pub const cpu = struct { .pku, .popcnt, .ppx, + .prefer_legacy_setcc, .prefer_movmsk_over_vtest, .prefetchi, .prfchw, @@ -4813,8 +5243,9 @@ pub const cpu = struct { .cmov, .cx16, .f16c, - .false_deps_lzcnt_tzcnt, + .false_deps_lzcnt, .false_deps_popcnt, + .false_deps_tzcnt, .fast_15bytenop, .fast_scalar_fsqrt, .fast_shld_rotate, @@ -5086,6 +5517,8 @@ pub const cpu = struct { .clzero, .cmov, .cx16, + .false_deps_compress, + .false_deps_expand, .fast_15bytenop, .fast_bextr, .fast_dpwssd, @@ -5159,6 +5592,10 @@ pub const cpu = struct { .clzero, .cmov, .cx16, + .false_deps_bls, + .false_deps_compress, + .false_deps_expand, + .false_deps_tzcnt, .fast_15bytenop, .fast_bextr, .fast_dpwssd, @@ -5195,6 +5632,7 @@ pub const cpu = struct { .sbb_dep_breaking, .sha, .shstk, + .slow_indirect_call, .smap, .smep, .sse4a, @@ -5208,4 +5646,83 @@ pub const cpu = struct { .xsaves, }), }; + pub const znver6: CpuModel = .{ + .name = "znver6", + .llvm_name = "znver6", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .allow_light_256_bit, + .avx512bf16, + .avx512bitalg, + .avx512bmm, + .avx512cd, + .avx512dq, + .avx512fp16, + .avx512ifma, + .avx512vbmi, + .avx512vbmi2, + .avx512vl, + .avx512vnni, + .avx512vp2intersect, + .avx512vpopcntdq, + .avxifma, + .avxneconvert, + .avxvnni, + .avxvnniint8, + .bmi, + .bmi2, + .branchfusion, + .clflushopt, + .clwb, + .clzero, + .cmov, + .cx16, + .fast_15bytenop, + .fast_bextr, + .fast_dpwssd, + .fast_imm16, + .fast_lzcnt, + .fast_movbe, + .fast_scalar_fsqrt, + .fast_scalar_shift_masks, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fsgsbase, + .fsrm, + .fxsr, + .gfni, + .idivq_to_divl, + .invpcid, + .lzcnt, + .macrofusion, + .mmx, + .movbe, + .movdir64b, + .movdiri, + .mwaitx, + .nopl, + .pku, + .popcnt, + .prefetchi, + .prfchw, + .rdpid, + .rdpru, + .rdrnd, + .rdseed, + .sahf, + .sbb_dep_breaking, + .sha, + .shstk, + .sse4a, + .vaes, + .vpclmulqdq, + .vzeroupper, + .wbnoinvd, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; }; diff --git a/lib/std/Target/xtensa.zig b/lib/std/Target/xtensa.zig index f2ca1f44043e75ced107f19002b51967edf3af08..2a95e224cbf6e5164e66c38434f76f4b4780298e 100644 --- a/lib/std/Target/xtensa.zig +++ b/lib/std/Target/xtensa.zig @@ -13,6 +13,7 @@ pub const Feature = enum { density, dfpaccel, div32, + esp32s2ops, exception, extendedl32r, forced_atomics, @@ -93,6 +94,11 @@ pub const all_features = blk: { .description = "Enable Xtensa Div32 option", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.esp32s2ops)] = .{ + .llvm_name = "esp32s2ops", + .description = "Support Xtensa esp32-s2 ISA extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.exception)] = .{ .llvm_name = "exception", .description = "Enable Xtensa Exception option", @@ -291,6 +297,35 @@ pub const cpu = struct { .windowed, }), }; + pub const esp32s2: CpuModel = .{ + .name = "esp32s2", + .llvm_name = "esp32s2", + .features = featureSet(&[_]Feature{ + .clamps, + .coprocessor, + .dcache, + .debug, + .density, + .div32, + .esp32s2ops, + .exception, + .highpriinterrupts_level7, + .interrupt, + .minmax, + .miscsr, + .mul16, + .mul32, + .mul32high, + .nsa, + .prid, + .regprotect, + .rvector, + .sext, + .threadptr, + .timers3, + .windowed, + }), + }; pub const esp8266: CpuModel = .{ .name = "esp8266", .llvm_name = "esp8266", diff --git a/src/codegen/x86_64/CodeGen.zig b/src/codegen/x86_64/CodeGen.zig index 410e2a878c767b55a85740a4576af8c3f4e9e8d8..c5c858510c3af826013ddc1a278c9a42c56a8355 100644 --- a/src/codegen/x86_64/CodeGen.zig +++ b/src/codegen/x86_64/CodeGen.zig @@ -67564,7 +67564,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .sia(32, .src0, .sub_bit_size), ._, ._ }, } }, }, .{ - .required_features = .{ .false_deps_lzcnt_tzcnt, .lzcnt, null, null }, + .required_features = .{ .false_deps_lzcnt, .lzcnt, null, null }, .src_constraints = .{ .{ .exact_int = 16 }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mut_gpr, .none, .none } }, @@ -67600,7 +67600,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .sia(16, .src0, .sub_bit_size), ._, ._ }, } }, }, .{ - .required_features = .{ .false_deps_lzcnt_tzcnt, .lzcnt, null, null }, + .required_features = .{ .false_deps_lzcnt, .lzcnt, null, null }, .src_constraints = .{ .{ .unsigned_int = .word }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mut_gpr, .none, .none } }, @@ -67625,7 +67625,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .sia(16, .src0, .sub_bit_size), ._, ._ }, } }, }, .{ - .required_features = .{ .false_deps_lzcnt_tzcnt, .lzcnt, null, null }, + .required_features = .{ .false_deps_lzcnt, .lzcnt, null, null }, .src_constraints = .{ .{ .exact_int = 32 }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mut_gpr, .none, .none } }, @@ -67661,7 +67661,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .sia(32, .src0, .sub_bit_size), ._, ._ }, } }, }, .{ - .required_features = .{ .false_deps_lzcnt_tzcnt, .lzcnt, null, null }, + .required_features = .{ .false_deps_lzcnt, .lzcnt, null, null }, .src_constraints = .{ .{ .unsigned_int = .dword }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mut_gpr, .none, .none } }, @@ -67686,7 +67686,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .sia(32, .src0, .sub_bit_size), ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .exact_int = 64 }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mut_gpr, .none, .none } }, @@ -67724,7 +67724,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .sia(64, .src0, .sub_bit_size), ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .unsigned_int = .qword }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mut_gpr, .none, .none } }, @@ -68581,7 +68581,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .sub, .dst0b, .tmp0b, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .unsigned_or_exact_remainder_int = .{ .of = .xword, .is = .qword } }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mem, .none, .none } }, @@ -68709,7 +68709,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .neg, .dst0d, ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .unsigned_or_exact_remainder_int = .{ .of = .xword, .is = .xword } }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mem, .none, .none } }, @@ -68837,7 +68837,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .neg, .dst0d, ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .remainder_int = .{ .of = .xword, .is = .qword } }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mem, .none, .none } }, @@ -68940,7 +68940,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .neg, .dst0d, ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .remainder_int = .{ .of = .xword, .is = .xword } }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mem, .none, .none } }, @@ -70096,7 +70096,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._nz, .j, .@"0b", ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .scalar_remainder_int = .{ .of = .xword, .is = .qword } }, .any, .any }, .dst_constraints = .{ .{ .scalar_int_is = .byte }, .any }, .patterns = &.{ @@ -70220,7 +70220,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._nc, .j, .@"0b", ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .scalar_remainder_int = .{ .of = .xword, .is = .xword } }, .any, .any }, .dst_constraints = .{ .{ .scalar_int_is = .byte }, .any }, .patterns = &.{ @@ -70344,7 +70344,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._nc, .j, .@"0b", ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .scalar_remainder_int = .{ .of = .xword, .is = .qword } }, .any, .any }, .dst_constraints = .{ .{ .scalar_int_is = .word }, .any }, .patterns = &.{ @@ -70468,7 +70468,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._nc, .j, .@"0b", ._, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .false_deps_lzcnt_tzcnt, .lzcnt, null }, + .required_features = .{ .@"64bit", .false_deps_lzcnt, .lzcnt, null }, .src_constraints = .{ .{ .scalar_remainder_int = .{ .of = .xword, .is = .xword } }, .any, .any }, .dst_constraints = .{ .{ .scalar_int_is = .word }, .any }, .patterns = &.{ @@ -70653,7 +70653,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .tzcnt, .dst0w, .src0w, ._, ._ }, } }, }, .{ - .required_features = .{ .bmi, .false_deps_lzcnt_tzcnt, null, null }, + .required_features = .{ .bmi, .false_deps_tzcnt, null, null }, .src_constraints = .{ .{ .exact_int = 32 }, .any, .any }, .patterns = &.{ .{ .src = .{ .mem, .none, .none } }, @@ -70690,7 +70690,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._, .tzcnt, .dst0d, .src0d, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .bmi, .false_deps_lzcnt_tzcnt, null }, + .required_features = .{ .@"64bit", .bmi, .false_deps_tzcnt, null }, .src_constraints = .{ .{ .exact_int = 64 }, .any, .any }, .patterns = &.{ .{ .src = .{ .mem, .none, .none } }, @@ -70867,7 +70867,7 @@ fn genBody(cg: *CodeGen, body: []const Air.Inst.Index) InnerError!void { .{ ._, ._f, .bs, .dst0q, .src0q, ._, ._ }, } }, }, .{ - .required_features = .{ .@"64bit", .bmi, .false_deps_lzcnt_tzcnt, null }, + .required_features = .{ .@"64bit", .bmi, .false_deps_tzcnt, null }, .src_constraints = .{ .{ .remainder_int = .{ .of = .qword, .is = .qword } }, .any, .any }, .patterns = &.{ .{ .src = .{ .to_mem, .none, .none } }, @@ -182371,12 +182371,13 @@ fn hasFeature(cg: *CodeGen, feature: std.Target.x86.Feature) bool { .x86_64 => true, }, .false_deps_getmant, - .false_deps_lzcnt_tzcnt, + .false_deps_lzcnt, .false_deps_mulc, .false_deps_mullq, .false_deps_perm, .false_deps_popcnt, .false_deps_range, + .false_deps_tzcnt, .slow_3ops_lea, .slow_incdec, .slow_lea, diff --git a/src/link/Wasm.zig b/src/link/Wasm.zig index c0aa2f1ea4f9a6c957c1d46799fe21dc56d0b0e2..f4d1ff3efe2d655317824bc01ca3e7b1cbe910f7 100644 --- a/src/link/Wasm.zig +++ b/src/link/Wasm.zig @@ -3254,6 +3254,7 @@ pub const Feature = packed struct(u8) { @"tail-call", @"shared-mem", @"wide-arithmetic", + @"relaxed-atomics", pub fn fromCpuFeature(feature: std.Target.wasm.Feature) Tag { return switch (feature) { @@ -3271,6 +3272,7 @@ pub const Feature = packed struct(u8) { .nontrapping_bulk_memory_len0 => .@"nontrapping-bulk-memory-len0", // Zig extension. .nontrapping_fptoint => .@"nontrapping-fptoint", .reference_types => .@"reference-types", + .relaxed_atomics => .@"relaxed-atomics", .relaxed_simd => .@"relaxed-simd", .sign_ext => .@"sign-ext", .simd128 => .simd128, @@ -3296,6 +3298,7 @@ pub const Feature = packed struct(u8) { .@"nontrapping-bulk-memory-len0" => .nontrapping_bulk_memory_len0, // Zig extension. .@"nontrapping-fptoint" => .nontrapping_fptoint, .@"reference-types" => .reference_types, + .@"relaxed-atomics" => .relaxed_atomics, .@"relaxed-simd" => .relaxed_simd, .@"sign-ext" => .sign_ext, .simd128 => .simd128, diff --git a/src/target.zig b/src/target.zig index 5edf18e9581df4d786b515f6b5a2bfdf33e34561..9b47363f13ad621300e73c44ffb7dc09c282a0d5 100644 --- a/src/target.zig +++ b/src/target.zig @@ -415,6 +415,9 @@ pub fn hasDebugInfo(target: *const std.Target) bool { .ptx87, .ptx88, .ptx90, + .ptx91, + .ptx92, + .ptx93, }), .bpfel, .bpfeb => false, else => true, diff --git a/test/tests.zig b/test/tests.zig index 41e54a82fc7020b6b728f1a6ade49592c1332d9a..81d39016626a584c2293200552a3df7595dc0b58 100644 --- a/test/tests.zig +++ b/test/tests.zig @@ -2357,13 +2357,17 @@ pub fn isNative(actual_target: *const std.Build.ResolvedTarget, host: *const std .@"16bit_mode", .@"32bit_mode", .@"64bit", + .false_deps_bls, + .false_deps_compress, + .false_deps_expand, .false_deps_getmant, - .false_deps_lzcnt_tzcnt, + .false_deps_lzcnt, .false_deps_mulc, .false_deps_mullq, .false_deps_perm, .false_deps_popcnt, .false_deps_range, + .false_deps_tzcnt, .fast_11bytenop, .fast_15bytenop, .fast_7bytenop, @@ -2391,10 +2395,12 @@ pub fn isNative(actual_target: *const std.Build.ResolvedTarget, host: *const std .prefer_legacy_setcc, .prefer_mask_registers, .prefer_movmsk_over_vtest, + .prefer_ndd_mem, .prefer_no_gather, .prefer_no_scatter, .slow_3ops_lea, .slow_incdec, + .slow_indirect_call, .slow_lea, .slow_pmaddwd, .slow_pmulld, @@ -2406,10 +2412,13 @@ pub fn isNative(actual_target: *const std.Build.ResolvedTarget, host: *const std }), .aarch64, .aarch64_be => std.Target.aarch64.featureSet(&.{ .addr_lsl_slow_14, + .align_cmp_csel_pairs, .alu_lsl_fast, .avoid_ldapur, .disable_fast_inc_vl, .exynos_cheap_as_move, + .fast_ld1_single, + .fixed_load_latency_4, .fuse_address, .fuse_addsub_2reg_const1, .fuse_adrp_add, @@ -2418,7 +2427,9 @@ pub fn isNative(actual_target: *const std.Build.ResolvedTarget, host: *const std .fuse_crypto_eor, .fuse_csel, .fuse_cset, + .fuse_fcsel, .fuse_literals, + .has_limited_64bit_vector_mul_bandwidth, .predictable_select_expensive, .slow_misaligned_128store, .slow_paired_128, diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index 8d0e142ab87423a56116043c5a1873da694172d4..4fd1d1a8fb3a58bf7bfe46381b7d740629dbc2bd 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -131,6 +131,14 @@ const targets = [_]ArchTarget{ .zig_name = "contextidr_el2", .desc = "Enable RW operand Context ID Register (EL2)", }, + .{ + .llvm_name = "hip12", + .flatten = true, + }, + .{ + .llvm_name = "mca-streaming-sched", + .omit = true, + }, .{ .llvm_name = "neoversee1", .flatten = true, @@ -1553,103 +1561,6 @@ const targets = [_]ArchTarget{ .zig_name = "baseline_rv64", .features = &.{ "64bit", "a", "c", "d", "f", "i", "m" }, }, - .{ - .llvm_name = null, - .zig_name = "spacemit_a100", - .features = &.{ - "64bit", - "a", - "b", - "c", - "dlen_factor_2", - "i", - "m", - "optimized_nf2_segment_load_store", - "optimized_nf3_segment_load_store", - "optimized_nf4_segment_load_store", - "smepmp", - "smnpm", - "smstateen", - "ssccptr", - "sscofpmf", - "sscounterenw", - "ssnpm", - "sspm", - "sstc", - "sstvala", - "sstvecd", - "ssu64xl", - "supm", - "svade", - "svbare", - "svinval", - "svnapot", - "svpbmt", - "unaligned_scalar_mem", - "v", - "vxrm_pipeline_flush", - "za64rs", - "zawrs", - "zbc", - "zbkc", - "zcb", - "zcmop", - "zfa", - "zfh", - "zic64b", - "zicbom", - "zicbop", - "zicboz", - "ziccamoa", - "ziccif", - "zicclsm", - "ziccrse", - "zicntr", - "zicond", - "zifencei", - "zihintntl", - "zihintpause", - "zihpm", - "zimop", - "zkt", - "zvbb", - "zvfbfwma", - "zvfh", - "zvkng", - "zvknha", - "zvksc", - "zvksg", - "zvl1024b", - }, - }, - .{ - .llvm_name = null, - .zig_name = "spacemit_x100", - .features = &.{ - "dlen_factor_2", - "optimized_nf2_segment_load_store", - "optimized_nf3_segment_load_store", - "optimized_nf4_segment_load_store", - "rva23s64", - "smepmp", - "smnpm", - "smstateen", - "sspm", - "unaligned_scalar_mem", - "vxrm_pipeline_flush", - "xsmtvdot", - "zbc", - "zbkc", - "zfh", - "zvfbfwma", - "zvfh", - "zvkng", - "zvknha", - "zvksc", - "zvksg", - "zvl256b", - }, - }, }, }, .{ @@ -2450,7 +2361,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { for (all_features.items) |feature| { if (feature.llvm_name) |llvm_name| { try w.print( - \\ result[@intFromEnum(Feature.{f})] = .{{ + \\ result[@backingInt(Feature.{f})] = .{{ \\ .llvm_name = "{f}", \\ .description = "{f}", \\ .dependencies = featureSet(&[_]Feature{{ @@ -2463,7 +2374,7 @@ fn processOneTargetInner(io: Io, job: Job) !void { ); } else { try w.print( - \\ result[@intFromEnum(Feature.{f})] = .{{ + \\ result[@backingInt(Feature.{f})] = .{{ \\ .llvm_name = null, \\ .description = "{f}", \\ .dependencies = featureSet(&[_]Feature{{