Commit 7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2 | zig

author	Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-03-19 19:48:27+01:00
committer	Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-03-19 19:48:27+01:00
log	7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2
tree	6444e2961ca1509b573de24e8c34ffacaa4a529a
parent	956d9f4ce019243ed0bd7f587acdeb1af4b5f61c
signature	Commit is signed but in an unrecognized format.

3 files changed, 33 insertions(+), 0 deletions(-)

src/arch/riscv64/CodeGen.zig+14

...	...	@@ -2074,6 +2074,20 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
2074	2074	return self.fail("TODO genSetReg 33-64 bit immediates for riscv64", .{}); // glhf
2075	2075	}
2076	2076	},
	2077	.register => \|src_reg\| {
	2078	// If the registers are the same, nothing to do.
	2079	if (src_reg.id() == reg.id())
	2080	return;
	2081
	2082	// mov reg, src_reg
	2083	_ = try self.addInst(.{
	2084	.tag = .mv,
	2085	.data = .{ .rr = .{
	2086	.rd = reg,
	2087	.rs = src_reg,
	2088	} },
	2089	});
	2090	},
2077	2091	.memory => \|addr\| {
2078	2092	// The value is in memory at a hard-coded address.
2079	2093	// If the type is a pointer, it means the pointer address is at this memory location.

src/arch/riscv64/Emit.zig+11

...	...	@@ -56,6 +56,8 @@ pub fn emitMir(
56	56	.dbg_prologue_end => try emit.mirDebugPrologueEnd(),
57	57	.dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
58	58
	59	.mv => try emit.mirRR(inst),
	60
59	61	.nop => try emit.mirNop(inst),
60	62	.ret => try emit.mirNop(inst),
61	63
...	...	@@ -186,6 +188,15 @@ fn mirDebugEpilogueBegin(self: *Emit) !void {
186	188	}
187	189	}
188	190
	191	fn mirRR(emit: *Emit, inst: Mir.Inst.Index) !void {
	192	const tag = emit.mir.instructions.items(.tag)[inst];
	193	const rr = emit.mir.instructions.items(.data)[inst].rr;
	194
	195	switch (tag) {
	196	.mv => try emit.writeInstruction(Instruction.addi(rr.rd, rr.rs, 0)),
	197	else => unreachable,
	198	}
	199	}
189	200	fn mirUType(emit: *Emit, inst: Mir.Inst.Index) !void {
190	201	const tag = emit.mir.instructions.items(.tag)[inst];
191	202	const u_type = emit.mir.instructions.items(.data)[inst].u_type;

src/arch/riscv64/Mir.zig+8