authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-04-01 22:10:15-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-04-02 04:49:53-04:00
log83a208c3551ae470f92753592a4c88984d2154d3
treea0f878390944963fe6810944eb4640933f488b16
parent677427bc3ac839629654175f0a2aaaec9fd6fb6c

x86_64: implement large cmp

23 files changed, 226 insertions(+), 299 deletions(-)

lib/std/os.zig+2
......@@ -1937,6 +1937,8 @@ pub fn getenv(key: []const u8) ?[]const u8 {
19371937 if (builtin.os.tag == .windows) {
19381938 @compileError("std.os.getenv is unavailable for Windows because environment string is in WTF-16 format. See std.process.getEnvVarOwned for cross-platform API or std.os.getenvW for Windows-specific API.");
19391939 }
1940 // The simplified start logic doesn't populate environ.
1941 if (std.start.simplified_logic) return null;
19401942 // TODO see https://github.com/ziglang/zig/issues/4524
19411943 for (environ) |ptr| {
19421944 var line_i: usize = 0;
lib/std/start.zig+13-11
......@@ -14,22 +14,24 @@ var argc_argv_ptr: [*]usize = undefined;
1414
1515const start_sym_name = if (native_arch.isMIPS()) "__start" else "_start";
1616
17// The self-hosted compiler is not fully capable of handling all of this start.zig file.
18// Until then, we have simplified logic here for self-hosted. TODO remove this once
19// self-hosted is capable enough to handle all of the real start.zig logic.
20pub const simplified_logic =
21 builtin.zig_backend == .stage2_wasm or
22 builtin.zig_backend == .stage2_x86_64 or
23 builtin.zig_backend == .stage2_x86 or
24 builtin.zig_backend == .stage2_aarch64 or
25 builtin.zig_backend == .stage2_arm or
26 builtin.zig_backend == .stage2_riscv64 or
27 builtin.zig_backend == .stage2_sparc64;
28
1729comptime {
1830 // No matter what, we import the root file, so that any export, test, comptime
1931 // decls there get run.
2032 _ = root;
2133
22 // The self-hosted compiler is not fully capable of handling all of this start.zig file.
23 // Until then, we have simplified logic here for self-hosted. TODO remove this once
24 // self-hosted is capable enough to handle all of the real start.zig logic.
25 if (builtin.zig_backend == .stage2_wasm or
26 builtin.zig_backend == .stage2_x86_64 or
27 builtin.zig_backend == .stage2_x86 or
28 builtin.zig_backend == .stage2_aarch64 or
29 builtin.zig_backend == .stage2_arm or
30 builtin.zig_backend == .stage2_riscv64 or
31 builtin.zig_backend == .stage2_sparc64)
32 {
34 if (simplified_logic) {
3335 if (builtin.output_mode == .Exe) {
3436 if ((builtin.link_libc or builtin.object_format == .c) and @hasDecl(root, "main")) {
3537 if (@typeInfo(@TypeOf(root.main)).Fn.calling_convention != .C) {
src/arch/x86_64/CodeGen.zig+197-252
......@@ -3986,7 +3986,7 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue
39863986 .eflags => unreachable,
39873987 .register_overflow => unreachable,
39883988 .register => |dst_reg| try self.asmRegister(mir_tag, registerAlias(dst_reg, abi_size)),
3989 .ptr_stack_offset, .stack_offset => |off| {
3989 .stack_offset => |off| {
39903990 if (abi_size > 8) {
39913991 return self.fail("TODO implement {} for stack dst with large ABI", .{mir_tag});
39923992 }
......@@ -3996,20 +3996,13 @@ fn genUnOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValue
39963996 .disp = -off,
39973997 }));
39983998 },
3999 .ptr_stack_offset => unreachable,
39994000 .memory, .linker_load => {
40004001 const addr_reg = (try self.register_manager.allocReg(null, gp)).to64();
40014002 const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
40024003 defer self.register_manager.unlockReg(addr_reg_lock);
40034004
40044005 try self.loadMemPtrIntoRegister(addr_reg, Type.usize, dst_mcv);
4005
4006 // To get the actual address of the value we want to modify we have to go through the GOT
4007 try self.asmRegisterMemory(
4008 .mov,
4009 addr_reg,
4010 Memory.sib(.qword, .{ .base = addr_reg }),
4011 );
4012
40134006 try self.asmMemory(
40144007 mir_tag,
40154008 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = addr_reg }),
......@@ -4454,7 +4447,7 @@ fn genBinOp(
44544447
44554448 else => false,
44564449 };
4457 const needs_reg_dst = switch (tag) {
4450 const dst_mem_ok = switch (tag) {
44584451 .add,
44594452 .addwrap,
44604453 .sub,
......@@ -4464,9 +4457,9 @@ fn genBinOp(
44644457 .div_exact,
44654458 .div_trunc,
44664459 .div_floor,
4467 => lhs_ty.isRuntimeFloat(),
4460 => !lhs_ty.isRuntimeFloat(),
44684461
4469 else => false,
4462 else => true,
44704463 };
44714464
44724465 const lhs_lock: ?RegisterLock = switch (lhs) {
......@@ -4482,18 +4475,21 @@ fn genBinOp(
44824475 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
44834476
44844477 var flipped: bool = false;
4485 const dst_mcv: MCValue = blk: {
4478 const dst_mcv: MCValue = dst: {
44864479 if (maybe_inst) |inst| {
4487 if ((!needs_reg_dst or lhs.isRegister()) and self.reuseOperand(inst, lhs_air, 0, lhs)) {
4488 break :blk lhs;
4480 if ((dst_mem_ok or lhs.isRegister()) and self.reuseOperand(inst, lhs_air, 0, lhs)) {
4481 break :dst lhs;
44894482 }
4490 if (is_commutative and (!needs_reg_dst or rhs.isRegister()) and self.reuseOperand(inst, rhs_air, 1, rhs)) {
4483 if (is_commutative and (dst_mem_ok or rhs.isRegister()) and
4484 self.reuseOperand(inst, rhs_air, 1, rhs))
4485 {
44914486 flipped = true;
4492 break :blk rhs;
4487 break :dst rhs;
44934488 }
4494 break :blk try self.copyToRegisterWithInstTracking(inst, lhs_ty, lhs);
44954489 }
4496 break :blk MCValue{ .register = try self.copyToTmpRegister(lhs_ty, lhs) };
4490 const dst_mcv = try self.allocRegOrMemAdvanced(lhs_ty, maybe_inst, true);
4491 try self.setRegOrMem(lhs_ty, dst_mcv, lhs);
4492 break :dst dst_mcv;
44974493 };
44984494 const dst_mcv_lock: ?RegisterLock = switch (dst_mcv) {
44994495 .register => |reg| self.register_manager.lockReg(reg),
......@@ -4501,17 +4497,7 @@ fn genBinOp(
45014497 };
45024498 defer if (dst_mcv_lock) |lock| self.register_manager.unlockReg(lock);
45034499
4504 const src_mcv: MCValue = blk: {
4505 const mcv = if (flipped) lhs else rhs;
4506 if (mcv.isRegister() or mcv.isMemory()) break :blk mcv;
4507 break :blk MCValue{ .register = try self.copyToTmpRegister(rhs_ty, mcv) };
4508 };
4509 const src_mcv_lock: ?RegisterLock = switch (src_mcv) {
4510 .register => |reg| self.register_manager.lockReg(reg),
4511 else => null,
4512 };
4513 defer if (src_mcv_lock) |lock| self.register_manager.unlockReg(lock);
4514
4500 const src_mcv = if (flipped) lhs else rhs;
45154501 switch (tag) {
45164502 .add,
45174503 .addwrap,
......@@ -4573,14 +4559,18 @@ fn genBinOp(
45734559 .ptr_add,
45744560 .ptr_sub,
45754561 => {
4576 const mir_tag: Mir.Inst.Tag = switch (tag) {
4562 const tmp_reg = try self.copyToTmpRegister(rhs_ty, src_mcv);
4563 const tmp_mcv = MCValue{ .register = tmp_reg };
4564 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
4565 defer self.register_manager.unlockReg(tmp_lock);
4566
4567 const elem_size = lhs_ty.elemType2().abiSize(self.target.*);
4568 try self.genIntMulComplexOpMir(rhs_ty, tmp_mcv, .{ .immediate = elem_size });
4569 try self.genBinOpMir(switch (tag) {
45774570 .ptr_add => .add,
45784571 .ptr_sub => .sub,
45794572 else => unreachable,
4580 };
4581 const elem_size = lhs_ty.elemType2().abiSize(self.target.*);
4582 try self.genIntMulComplexOpMir(rhs_ty, src_mcv, .{ .immediate = elem_size });
4583 try self.genBinOpMir(mir_tag, lhs_ty, dst_mcv, src_mcv);
4573 }, lhs_ty, dst_mcv, tmp_mcv);
45844574 },
45854575
45864576 .bool_or,
......@@ -4657,16 +4647,8 @@ fn genBinOp(
46574647 const addr_reg = (try self.register_manager.allocReg(null, gp)).to64();
46584648 const addr_reg_lock = self.register_manager.lockRegAssumeUnused(addr_reg);
46594649 defer self.register_manager.unlockReg(addr_reg_lock);
4660 try self.loadMemPtrIntoRegister(addr_reg, Type.usize, mat_src_mcv);
4661
4662 // To get the actual address of the value we want to modify we
4663 // we have to go through the GOT
4664 try self.asmRegisterMemory(
4665 .mov,
4666 addr_reg,
4667 Memory.sib(.qword, .{ .base = addr_reg }),
4668 );
46694650
4651 try self.loadMemPtrIntoRegister(addr_reg, Type.usize, mat_src_mcv);
46704652 try self.asmCmovccRegisterMemory(
46714653 registerAlias(tmp_reg, abi_size),
46724654 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = addr_reg }),
......@@ -4706,6 +4688,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
47064688 .eflags => unreachable,
47074689 .register_overflow => unreachable,
47084690 .register => |dst_reg| {
4691 const dst_alias = registerAlias(dst_reg, abi_size);
47094692 switch (src_mcv) {
47104693 .none => unreachable,
47114694 .undef => unreachable,
......@@ -4728,41 +4711,47 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
47284711 },
47294712 else => try self.asmRegisterRegister(
47304713 mir_tag,
4731 registerAlias(dst_reg, abi_size),
4714 dst_alias,
47324715 registerAlias(src_reg, abi_size),
47334716 ),
47344717 },
47354718 .immediate => |imm| {
47364719 switch (self.regBitSize(ty)) {
4737 8, 16, 32 => {
4738 try self.asmRegisterImmediate(
4739 mir_tag,
4740 registerAlias(dst_reg, abi_size),
4720 8 => try self.asmRegisterImmediate(
4721 mir_tag,
4722 dst_alias,
4723 if (math.cast(i8, @bitCast(i64, imm))) |small|
4724 Immediate.s(small)
4725 else
4726 Immediate.u(@intCast(u8, imm)),
4727 ),
4728 16 => try self.asmRegisterImmediate(
4729 mir_tag,
4730 dst_alias,
4731 if (math.cast(i16, @bitCast(i64, imm))) |small|
4732 Immediate.s(small)
4733 else
4734 Immediate.u(@intCast(u16, imm)),
4735 ),
4736 32 => try self.asmRegisterImmediate(
4737 mir_tag,
4738 dst_alias,
4739 if (math.cast(i32, @bitCast(i64, imm))) |small|
4740 Immediate.s(small)
4741 else
47414742 Immediate.u(@intCast(u32, imm)),
4742 );
4743 },
4744 64 => {
4745 if (math.cast(i32, @bitCast(i64, imm))) |small| {
4746 try self.asmRegisterImmediate(
4747 mir_tag,
4748 registerAlias(dst_reg, abi_size),
4749 Immediate.s(small),
4750 );
4751 } else {
4752 try self.asmRegisterRegister(
4753 mir_tag,
4754 registerAlias(dst_reg, abi_size),
4755 registerAlias(try self.copyToTmpRegister(ty, src_mcv), abi_size),
4756 );
4757 }
4758 },
4759 else => return self.fail("TODO genBinOpMir implement large immediate ABI", .{}),
4743 ),
4744 64 => if (math.cast(i32, @bitCast(i64, imm))) |small|
4745 try self.asmRegisterImmediate(mir_tag, dst_alias, Immediate.s(small))
4746 else
4747 try self.asmRegisterRegister(mir_tag, dst_alias, registerAlias(
4748 try self.copyToTmpRegister(ty, src_mcv),
4749 abi_size,
4750 )),
4751 else => unreachable,
47604752 }
47614753 },
4762 .memory,
4763 .linker_load,
4764 .eflags,
4765 => {
4754 .memory, .linker_load, .eflags => {
47664755 assert(abi_size <= 8);
47674756 const dst_reg_lock = self.register_manager.lockReg(dst_reg);
47684757 defer if (dst_reg_lock) |lock| self.register_manager.unlockReg(lock);
......@@ -4779,7 +4768,27 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
47794768 },
47804769 }
47814770 },
4782 .ptr_stack_offset, .stack_offset => |dst_off| {
4771 .memory, .linker_load, .stack_offset => {
4772 const dst: ?struct {
4773 addr_reg: Register,
4774 addr_lock: RegisterLock,
4775 } = switch (dst_mcv) {
4776 else => unreachable,
4777 .memory, .linker_load => dst: {
4778 const dst_addr_reg = try self.register_manager.allocReg(null, gp);
4779 const dst_addr_lock = self.register_manager.lockRegAssumeUnused(dst_addr_reg);
4780 errdefer self.register_manager.unlockReg(dst_addr_lock);
4781
4782 try self.loadMemPtrIntoRegister(dst_addr_reg, Type.usize, dst_mcv);
4783 break :dst .{
4784 .addr_reg = dst_addr_reg,
4785 .addr_lock = dst_addr_lock,
4786 };
4787 },
4788 .stack_offset => null,
4789 };
4790 defer if (dst) |lock| self.register_manager.unlockReg(lock.addr_lock);
4791
47834792 const src: ?struct {
47844793 limb_reg: Register,
47854794 limb_lock: RegisterLock,
......@@ -4787,7 +4796,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
47874796 addr_lock: RegisterLock,
47884797 } = switch (src_mcv) {
47894798 else => null,
4790 .memory, .linker_load => addr: {
4799 .memory, .linker_load => src: {
47914800 const src_limb_reg = try self.register_manager.allocReg(null, gp);
47924801 const src_limb_lock = self.register_manager.lockRegAssumeUnused(src_limb_reg);
47934802 errdefer self.register_manager.unlockReg(src_limb_lock);
......@@ -4797,15 +4806,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
47974806 errdefer self.register_manager.unlockReg(src_addr_lock);
47984807
47994808 try self.loadMemPtrIntoRegister(src_addr_reg, Type.usize, src_mcv);
4800 // To get the actual address of the value we want to modify we
4801 // we have to go through the GOT
4802 try self.asmRegisterMemory(
4803 .mov,
4804 src_addr_reg,
4805 Memory.sib(.qword, .{ .base = src_addr_reg }),
4806 );
4807
4808 break :addr .{
4809 break :src .{
48094810 .addr_reg = src_addr_reg,
48104811 .addr_lock = src_addr_lock,
48114812 .limb_reg = src_limb_reg,
......@@ -4831,7 +4832,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
48314832 0 => mir_tag,
48324833 else => switch (mir_tag) {
48334834 .add => .adc,
4834 .sub => .sbb,
4835 .sub, .cmp => .sbb,
48354836 .@"or", .@"and", .xor => mir_tag,
48364837 else => return self.fail("TODO genBinOpMir implement large ABI for {s}", .{
48374838 @tagName(mir_tag),
......@@ -4840,7 +4841,14 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
48404841 };
48414842 const dst_limb_mem = Memory.sib(
48424843 Memory.PtrSize.fromSize(limb_abi_size),
4843 .{ .base = .rbp, .disp = off - dst_off },
4844 switch (dst_mcv) {
4845 else => unreachable,
4846 .stack_offset => |dst_off| .{
4847 .base = .rbp,
4848 .disp = off - dst_off,
4849 },
4850 .memory, .linker_load => .{ .base = dst.?.addr_reg, .disp = off },
4851 },
48444852 );
48454853 switch (src_mcv) {
48464854 .none => unreachable,
......@@ -4861,34 +4869,45 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
48614869 .unsigned => 0,
48624870 };
48634871 switch (self.regBitSize(limb_ty)) {
4864 8, 16, 32 => {
4872 8 => try self.asmMemoryImmediate(
4873 mir_limb_tag,
4874 dst_limb_mem,
4875 if (math.cast(i8, @bitCast(i64, imm))) |small|
4876 Immediate.s(small)
4877 else
4878 Immediate.u(@intCast(u8, imm)),
4879 ),
4880 16 => try self.asmMemoryImmediate(
4881 mir_limb_tag,
4882 dst_limb_mem,
4883 if (math.cast(i16, @bitCast(i64, imm))) |small|
4884 Immediate.s(small)
4885 else
4886 Immediate.u(@intCast(u16, imm)),
4887 ),
4888 32 => try self.asmMemoryImmediate(
4889 mir_limb_tag,
4890 dst_limb_mem,
4891 if (math.cast(i32, @bitCast(i64, imm))) |small|
4892 Immediate.s(small)
4893 else
4894 Immediate.u(@intCast(u32, imm)),
4895 ),
4896 64 => if (math.cast(i32, @bitCast(i64, imm))) |small|
48654897 try self.asmMemoryImmediate(
48664898 mir_limb_tag,
48674899 dst_limb_mem,
4868 if (math.cast(i32, @bitCast(i64, imm))) |small|
4869 Immediate.s(small)
4870 else
4871 Immediate.u(@intCast(u32, imm)),
4872 );
4873 },
4874 64 => {
4875 if (math.cast(i32, @bitCast(i64, imm))) |small| {
4876 try self.asmMemoryImmediate(
4877 mir_limb_tag,
4878 dst_limb_mem,
4879 Immediate.s(small),
4880 );
4881 } else {
4882 try self.asmMemoryRegister(
4883 mir_limb_tag,
4884 dst_limb_mem,
4885 registerAlias(
4886 try self.copyToTmpRegister(limb_ty, .{ .immediate = imm }),
4887 limb_abi_size,
4888 ),
4889 );
4890 }
4891 },
4900 Immediate.s(small),
4901 )
4902 else
4903 try self.asmMemoryRegister(
4904 mir_limb_tag,
4905 dst_limb_mem,
4906 registerAlias(
4907 try self.copyToTmpRegister(limb_ty, .{ .immediate = imm }),
4908 limb_abi_size,
4909 ),
4910 ),
48924911 else => unreachable,
48934912 }
48944913 },
......@@ -4930,12 +4949,7 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, ty: Type, dst_mcv: MCValue, s
49304949 }
49314950 }
49324951 },
4933 .memory => {
4934 return self.fail("TODO implement x86 genBinOpMir destination memory", .{});
4935 },
4936 .linker_load => {
4937 return self.fail("TODO implement x86 genBinOpMir destination symbol at index", .{});
4938 },
4952 .ptr_stack_offset => unreachable,
49394953 }
49404954}
49414955
......@@ -5452,79 +5466,61 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
54525466
54535467fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
54545468 const bin_op = self.air.instructions.items(.data)[inst].bin_op;
5469 const result: MCValue = if (self.liveness.isUnused(inst)) .dead else result: {
5470 const ty = self.air.typeOf(bin_op.lhs);
5471 const ty_abi_size = ty.abiSize(self.target.*);
5472 const can_reuse = ty_abi_size <= 8;
54555473
5456 if (self.liveness.isUnused(inst)) {
5457 return self.finishAir(inst, .dead, .{ bin_op.lhs, bin_op.rhs, .none });
5458 }
5459
5460 const ty = self.air.typeOf(bin_op.lhs);
5461 const abi_size = ty.abiSize(self.target.*);
5462 if (abi_size > 8) return self.fail("TODO implement cmp for large values", .{});
5463
5464 const signedness: std.builtin.Signedness = blk: {
5465 // For non-int types, we treat the values as unsigned
5466 if (ty.zigTypeTag() != .Int) break :blk .unsigned;
5467
5468 // Otherwise, we take the signedness of the actual int
5469 break :blk ty.intInfo(self.target.*).signedness;
5470 };
5471
5472 try self.spillEflagsIfOccupied();
5473 self.eflags_inst = inst;
5474 try self.spillEflagsIfOccupied();
5475 self.eflags_inst = inst;
54745476
5475 const result: MCValue = result: {
5476 // There are 2 operands, destination and source.
5477 // Either one, but not both, can be a memory operand.
5478 // Source operand can be an immediate, 8 bits or 32 bits.
5479 // TODO look into reusing the operand
5480 const lhs = try self.resolveInst(bin_op.lhs);
5481 const lhs_lock: ?RegisterLock = switch (lhs) {
5477 const lhs_mcv = try self.resolveInst(bin_op.lhs);
5478 const lhs_lock = switch (lhs_mcv) {
54825479 .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
54835480 else => null,
54845481 };
54855482 defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
54865483
5487 const dst_reg = try self.copyToTmpRegister(ty, lhs);
5488 const dst_reg_lock = self.register_manager.lockRegAssumeUnused(dst_reg);
5489 defer self.register_manager.unlockReg(dst_reg_lock);
5490
5491 const dst_mcv = MCValue{ .register = dst_reg };
5492
5493 const rhs_ty = self.air.typeOf(bin_op.rhs);
5494 // This instruction supports only signed 32-bit immediates at most.
5495 const src_mcv: MCValue = blk: {
5496 switch (rhs_ty.zigTypeTag()) {
5497 .Float => {
5498 const rhs = try self.resolveInst(bin_op.rhs);
5499 const rhs_lock: ?RegisterLock = switch (rhs) {
5500 .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
5501 else => null,
5502 };
5503 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
5504 const src_reg = try self.copyToTmpRegister(rhs_ty, rhs);
5505 break :blk MCValue{ .register = src_reg };
5506 },
5507 else => break :blk try self.limitImmediateType(bin_op.rhs, i32),
5508 }
5484 const rhs_mcv = try self.resolveInst(bin_op.rhs);
5485 const rhs_lock = switch (rhs_mcv) {
5486 .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
5487 else => null,
55095488 };
5510 const src_lock: ?RegisterLock = switch (src_mcv) {
5489 defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
5490
5491 const dst_mem_ok = !ty.isRuntimeFloat();
5492 var flipped = false;
5493 const dst_mcv: MCValue = if (can_reuse and !lhs_mcv.isImmediate() and
5494 (dst_mem_ok or lhs_mcv.isRegister()) and self.liveness.operandDies(inst, 0))
5495 lhs_mcv
5496 else if (can_reuse and !rhs_mcv.isImmediate() and
5497 (dst_mem_ok or rhs_mcv.isRegister()) and self.liveness.operandDies(inst, 1))
5498 dst: {
5499 flipped = true;
5500 break :dst rhs_mcv;
5501 } else if (dst_mem_ok) dst: {
5502 const dst_mcv = try self.allocTempRegOrMem(ty, true);
5503 try self.setRegOrMem(ty, dst_mcv, lhs_mcv);
5504 break :dst dst_mcv;
5505 } else .{ .register = try self.copyToTmpRegister(ty, lhs_mcv) };
5506 const dst_lock = switch (dst_mcv) {
55115507 .register => |reg| self.register_manager.lockReg(reg),
55125508 else => null,
55135509 };
5514 defer if (src_lock) |lock| self.register_manager.unlockReg(lock);
5510 defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
55155511
5512 const src_mcv = if (flipped) lhs_mcv else rhs_mcv;
55165513 try self.genBinOpMir(switch (ty.tag()) {
55175514 else => .cmp,
55185515 .f32 => .ucomiss,
55195516 .f64 => .ucomisd,
55205517 }, ty, dst_mcv, src_mcv);
55215518
5522 break :result switch (signedness) {
5523 .signed => MCValue{ .eflags = Condition.fromCompareOperatorSigned(op) },
5524 .unsigned => MCValue{ .eflags = Condition.fromCompareOperatorUnsigned(op) },
5519 const signedness = if (ty.isAbiInt()) ty.intInfo(self.target.*).signedness else .unsigned;
5520 break :result .{
5521 .eflags = Condition.fromCompareOperator(signedness, if (flipped) op.reverse() else op),
55255522 };
55265523 };
5527
55285524 return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
55295525}
55305526
......@@ -5785,13 +5781,6 @@ fn isNull(self: *Self, inst: Air.Inst.Index, opt_ty: Type, opt_mcv: MCValue) !MC
57855781
57865782 try self.loadMemPtrIntoRegister(addr_reg, Type.usize, opt_mcv);
57875783
5788 // To get the actual address of the value we want to modify we have to go through the GOT
5789 try self.asmRegisterMemory(
5790 .mov,
5791 addr_reg,
5792 Memory.sib(.qword, .{ .base = addr_reg }),
5793 );
5794
57955784 const some_abi_size = @intCast(u32, some_info.ty.abiSize(self.target.*));
57965785 try self.asmMemoryImmediate(.cmp, Memory.sib(
57975786 Memory.PtrSize.fromSize(some_abi_size),
......@@ -6803,22 +6792,14 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
68036792 },
68046793 }
68056794 },
6806 .memory, .linker_load => {
6807 if (abi_size <= 8) {
6808 const reg = try self.copyToTmpRegister(ty, mcv);
6809 return self.genSetStack(ty, stack_offset, MCValue{ .register = reg }, opts);
6810 }
6811
6812 try self.genInlineMemcpy(.{ .stack_offset = stack_offset }, mcv, .{ .immediate = abi_size }, opts);
6813 },
6814 .ptr_stack_offset => {
6815 const reg = try self.copyToTmpRegister(ty, mcv);
6816 return self.genSetStack(ty, stack_offset, MCValue{ .register = reg }, opts);
6817 },
6818 .stack_offset => |off| {
6819 if (stack_offset == off) {
6820 // Copy stack variable to itself; nothing to do.
6821 return;
6795 .memory, .linker_load, .stack_offset, .ptr_stack_offset => {
6796 switch (mcv) {
6797 else => unreachable,
6798 .memory, .linker_load, .ptr_stack_offset => {},
6799 .stack_offset => |src_off| if (stack_offset == src_off) {
6800 // Copy stack variable to itself; nothing to do.
6801 return;
6802 },
68226803 }
68236804
68246805 if (abi_size <= 8) {
......@@ -7096,69 +7077,38 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
70967077
70977078 try self.asmRegisterRegister(.mov, registerAlias(reg, abi_size), registerAlias(src_reg, abi_size));
70987079 },
7099 .linker_load => {
7100 switch (ty.zigTypeTag()) {
7101 .Float => {
7102 const base_reg = try self.register_manager.allocReg(null, gp);
7103 try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
7104
7105 if (intrinsicsAllowed(self.target.*, ty)) {
7106 const tag: Mir.Inst.Tag = switch (ty.tag()) {
7107 .f32 => .movss,
7108 .f64 => .movsd,
7109 else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
7110 };
7111 const ptr_size: Memory.PtrSize = switch (ty.tag()) {
7112 .f32 => .dword,
7113 .f64 => .qword,
7114 else => unreachable,
7115 };
7116 return self.asmRegisterMemory(
7117 tag,
7118 reg.to128(),
7119 Memory.sib(ptr_size, .{ .base = base_reg.to64() }),
7120 );
7121 }
7122
7123 return self.fail("TODO genSetReg from memory for float with no intrinsics", .{});
7124 },
7125 else => {
7126 try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
7127 try self.asmRegisterMemory(
7128 .mov,
7129 registerAlias(reg, abi_size),
7130 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = reg.to64() }),
7131 );
7132 },
7133 }
7134 },
7135 .memory => |x| switch (ty.zigTypeTag()) {
7080 .memory, .linker_load => switch (ty.zigTypeTag()) {
71367081 .Float => {
71377082 const base_reg = try self.register_manager.allocReg(null, gp);
71387083 try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
71397084
71407085 if (intrinsicsAllowed(self.target.*, ty)) {
7141 const tag: Mir.Inst.Tag = switch (ty.tag()) {
7142 .f32 => .movss,
7143 .f64 => .movsd,
7144 else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
7145 };
7146 const ptr_size: Memory.PtrSize = switch (ty.tag()) {
7147 .f32 => .dword,
7148 .f64 => .qword,
7149 else => unreachable,
7150 };
71517086 return self.asmRegisterMemory(
7152 tag,
7087 switch (ty.tag()) {
7088 .f32 => .movss,
7089 .f64 => .movsd,
7090 else => return self.fail("TODO genSetReg from memory for {}", .{
7091 ty.fmt(self.bin_file.options.module.?),
7092 }),
7093 },
71537094 reg.to128(),
7154 Memory.sib(ptr_size, .{ .base = base_reg.to64() }),
7095 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = base_reg.to64() }),
71557096 );
71567097 }
71577098
71587099 return self.fail("TODO genSetReg from memory for float with no intrinsics", .{});
71597100 },
7160 else => {
7161 if (x <= math.maxInt(i32)) {
7101 else => switch (mcv) {
7102 else => unreachable,
7103 .linker_load => {
7104 try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
7105 try self.asmRegisterMemory(
7106 .mov,
7107 registerAlias(reg, abi_size),
7108 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = reg.to64() }),
7109 );
7110 },
7111 .memory => |x| if (x <= math.maxInt(i32)) {
71627112 try self.asmRegisterMemory(
71637113 .mov,
71647114 registerAlias(reg, abi_size),
......@@ -7185,7 +7135,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
71857135 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = reg.to64() }),
71867136 );
71877137 }
7188 }
7138 },
71897139 },
71907140 },
71917141 .stack_offset => |off| {
......@@ -7226,15 +7176,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
72267176 .{ty.fmtDebug()},
72277177 ),
72287178 };
7229 const ptr_size: Memory.PtrSize = switch (ty.tag()) {
7230 .f32 => .dword,
7231 .f64 => .qword,
7232 else => unreachable,
7233 };
7234 return self.asmRegisterMemory(tag, reg.to128(), Memory.sib(ptr_size, .{
7235 .base = .rbp,
7236 .disp = -off,
7237 }));
7179 return self.asmRegisterMemory(tag, reg.to128(), Memory.sib(
7180 Memory.PtrSize.fromSize(abi_size),
7181 .{ .base = .rbp, .disp = -off },
7182 ));
72387183 }
72397184 return self.fail("TODO genSetReg from stack offset for float with no intrinsics", .{});
72407185 },
src/arch/x86_64/bits.zig+10
......@@ -100,6 +100,16 @@ pub const Condition = enum(u5) {
100100 };
101101 }
102102
103 pub fn fromCompareOperator(
104 signedness: std.builtin.Signedness,
105 op: std.math.CompareOperator,
106 ) Condition {
107 return switch (signedness) {
108 .signed => fromCompareOperatorSigned(op),
109 .unsigned => fromCompareOperatorUnsigned(op),
110 };
111 }
112
103113 /// Returns the condition which is true iff the given condition is false
104114 pub fn negate(cond: Condition) Condition {
105115 return switch (cond) {
test/behavior/align.zig-3
......@@ -271,7 +271,6 @@ fn sliceExpects4(slice: []align(4) u32) void {
271271
272272test "return error union with 128-bit integer" {
273273 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
274 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
275274 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
276275 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
277276
......@@ -477,7 +476,6 @@ const DefaultAligned = struct {
477476
478477test "read 128-bit field from default aligned struct in stack memory" {
479478 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
480 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
481479 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
482480 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
483481
......@@ -494,7 +492,6 @@ var default_aligned_global = DefaultAligned{
494492};
495493
496494test "read 128-bit field from default aligned struct in global memory" {
497 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
498495 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
499496 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
500497 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/basic.zig-8
......@@ -39,7 +39,6 @@ test "truncate to non-power-of-two integers" {
3939
4040test "truncate to non-power-of-two integers from 128-bit" {
4141 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
42 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
4342 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
4443 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
4544 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -345,7 +344,6 @@ fn copy(src: *const u64, dst: *u64) void {
345344test "call result of if else expression" {
346345 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
347346 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
348 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
349347 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
350348
351349 try expect(mem.eql(u8, f2(true), "a"));
......@@ -663,7 +661,6 @@ test "multiline string literal is null terminated" {
663661test "string escapes" {
664662 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
665663 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
666 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
667664 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
668665
669666 try expectEqualStrings("\"", "\x22");
......@@ -682,8 +679,6 @@ test "explicit cast optional pointers" {
682679}
683680
684681test "pointer comparison" {
685 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
686
687682 const a = @as([]const u8, "a");
688683 const b = &a;
689684 try expect(ptrEql(b, b));
......@@ -695,7 +690,6 @@ fn ptrEql(a: *const []const u8, b: *const []const u8) bool {
695690test "string concatenation" {
696691 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
697692 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
698 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
699693 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
700694
701695 const a = "OK" ++ " IT " ++ "WORKED";
......@@ -916,7 +910,6 @@ test "vector initialized with array init syntax has proper type" {
916910}
917911
918912test "weird array and tuple initializations" {
919 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
920913 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
921914 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
922915 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -1060,7 +1053,6 @@ test "inline call of function with a switch inside the return statement" {
10601053
10611054test "namespace lookup ignores decl causing the lookup" {
10621055 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1063 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
10641056 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
10651057 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
10661058
test/behavior/bitcast.zig-1
......@@ -20,7 +20,6 @@ test "@bitCast iX -> uX (32, 64)" {
2020
2121test "@bitCast iX -> uX (8, 16, 128)" {
2222 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
23 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
2423 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
2524 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
2625
test/behavior/bugs/6905.zig-1
......@@ -3,7 +3,6 @@ const builtin = @import("builtin");
33
44test "sentinel-terminated 0-length slices" {
55 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
6 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
76 if (builtin.zig_backend == .stage2_x86) return error.SkipZigTest; // TODO
87 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
98 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
test/behavior/builtin_functions_returning_void_or_noreturn.zig-1
......@@ -8,7 +8,6 @@ var x: u8 = 1;
88test {
99 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
1010 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
11 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1211 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1312 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1413 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/cast.zig-1
......@@ -1178,7 +1178,6 @@ fn castToOptionalSlice() ?[]const u8 {
11781178test "cast u128 to f128 and back" {
11791179 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
11801180 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1181 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
11821181 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
11831182 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
11841183
test/behavior/cast_int.zig-1
......@@ -5,7 +5,6 @@ const maxInt = std.math.maxInt;
55
66test "@intCast i32 to u7" {
77 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
8 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
98 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
109 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1110 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/error.zig-2
......@@ -561,7 +561,6 @@ test "error union comptime caching" {
561561}
562562
563563test "@errorName" {
564 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
565564 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
566565 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
567566 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -798,7 +797,6 @@ test "error union of noreturn used with catch" {
798797}
799798
800799test "alignment of wrapping an error union payload" {
801 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
802800 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
803801 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
804802 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/eval.zig-1
......@@ -458,7 +458,6 @@ test "binary math operator in partially inlined function" {
458458
459459test "comptime shl" {
460460 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
461 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
462461 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
463462 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
464463 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/int128.zig-3
......@@ -5,7 +5,6 @@ const minInt = std.math.minInt;
55const builtin = @import("builtin");
66
77test "uint128" {
8 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
98 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
109 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1110 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -24,7 +23,6 @@ test "uint128" {
2423}
2524
2625test "undefined 128 bit int" {
27 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
2826 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
2927 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
3028 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -87,7 +85,6 @@ test "truncate int128" {
8785
8886test "shift int128" {
8987 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
90 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
9188 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
9289 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
9390 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/int_div.zig-1
......@@ -97,7 +97,6 @@ test "large integer division" {
9797 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
9898 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
9999 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
100 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
101100
102101 {
103102 var numerator: u256 = 99999999999999999997315645440;
test/behavior/optional.zig-1
......@@ -412,7 +412,6 @@ test "orelse on C pointer" {
412412}
413413
414414test "alignment of wrapping an optional payload" {
415 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
416415 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
417416 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
418417 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/pointers.zig-1
......@@ -160,7 +160,6 @@ test "implicit casting between C pointer and optional non-C pointer" {
160160}
161161
162162test "implicit cast error unions with non-optional to optional pointer" {
163 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
164163 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
165164 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
166165 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/struct.zig-1
......@@ -800,7 +800,6 @@ test "fn with C calling convention returns struct by value" {
800800}
801801
802802test "non-packed struct with u128 entry in union" {
803 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
804803 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
805804 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
806805 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/behavior/typename.zig-6
......@@ -12,7 +12,6 @@ const expectStringStartsWith = std.testing.expectStringStartsWith;
1212// failures.
1313
1414test "anon fn param" {
15 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1615 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
1716 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1817 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -38,7 +37,6 @@ test "anon fn param" {
3837}
3938
4039test "anon field init" {
41 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
4240 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
4341 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
4442 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -87,7 +85,6 @@ test "basic" {
8785}
8886
8987test "top level decl" {
90 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
9188 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
9289 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
9390 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -137,7 +134,6 @@ const B = struct {
137134};
138135
139136test "fn param" {
140 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
141137 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
142138 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
143139 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -208,7 +204,6 @@ pub fn expectEqualStringsIgnoreDigits(expected: []const u8, actual: []const u8)
208204}
209205
210206test "local variable" {
211 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
212207 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
213208 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
214209 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
......@@ -236,7 +231,6 @@ test "comptime parameters not converted to anytype in function type" {
236231}
237232
238233test "anon name strategy used in sub expression" {
239 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
240234 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
241235 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
242236 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
test/cases/aarch64-macos/hello_world_with_updates.0.zig+1-1
......@@ -2,4 +2,4 @@
22// output_mode=Exe
33// target=aarch64-macos
44//
5// :108:9: error: root struct of file 'tmp' has no member named 'main'
5// :110:9: error: root struct of file 'tmp' has no member named 'main'
test/cases/x86_64-linux/hello_world_with_updates.0.zig+1-1
......@@ -2,4 +2,4 @@
22// output_mode=Exe
33// target=x86_64-linux
44//
5// :108:9: error: root struct of file 'tmp' has no member named 'main'
5// :110:9: error: root struct of file 'tmp' has no member named 'main'
test/cases/x86_64-macos/hello_world_with_updates.0.zig+1-1
......@@ -2,4 +2,4 @@
22// output_mode=Exe
33// target=x86_64-macos
44//
5// :108:9: error: root struct of file 'tmp' has no member named 'main'
5// :110:9: error: root struct of file 'tmp' has no member named 'main'
test/cases/x86_64-windows/hello_world_with_updates.0.zig+1-1
......@@ -2,4 +2,4 @@
22// output_mode=Exe
33// target=x86_64-windows
44//
5// :129:9: error: root struct of file 'tmp' has no member named 'main'
5// :131:9: error: root struct of file 'tmp' has no member named 'main'