| ... | ... | @@ -1352,7 +1352,7 @@ fn lowerToIEnc(tag: Tag, imm: i32, code: *std.ArrayList(u8)) LoweringError!void |
| 1352 | 1352 | const opc = getOpCode(tag, .i, immOpSize(imm) == 8).?; |
| 1353 | 1353 | const encoder = try Encoder.init(code, 5); |
| 1354 | 1354 | if (immOpSize(imm) == 16) { |
| 1355 | | encoder.opcode_1byte(0x66); |
| 1355 | encoder.prefix16BitMode(); |
| 1356 | 1356 | } |
| 1357 | 1357 | opc.encode(encoder); |
| 1358 | 1358 | if (immOpSize(imm) == 8) { |
| ... | ... | @@ -1371,7 +1371,7 @@ fn lowerToOEnc(tag: Tag, reg: Register, code: *std.ArrayList(u8)) LoweringError! |
| 1371 | 1371 | const opc = getOpCode(tag, .o, false).?; |
| 1372 | 1372 | const encoder = try Encoder.init(code, 3); |
| 1373 | 1373 | if (reg.size() == 16) { |
| 1374 | | encoder.opcode_1byte(0x66); |
| 1374 | encoder.prefix16BitMode(); |
| 1375 | 1375 | } |
| 1376 | 1376 | encoder.rex(.{ |
| 1377 | 1377 | .w = false, |
| ... | ... | @@ -1402,7 +1402,7 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8)) |
| 1402 | 1402 | } |
| 1403 | 1403 | const encoder = try Encoder.init(code, 4); |
| 1404 | 1404 | if (reg.size() == 16) { |
| 1405 | | encoder.opcode_1byte(0x66); |
| 1405 | encoder.prefix16BitMode(); |
| 1406 | 1406 | } |
| 1407 | 1407 | encoder.rex(.{ |
| 1408 | 1408 | .w = switch (reg) { |
| ... | ... | @@ -1420,7 +1420,7 @@ fn lowerToMEnc(tag: Tag, reg_or_mem: RegisterOrMemory, code: *std.ArrayList(u8)) |
| 1420 | 1420 | } |
| 1421 | 1421 | const encoder = try Encoder.init(code, 8); |
| 1422 | 1422 | if (mem_op.ptr_size == .word_ptr) { |
| 1423 | | encoder.opcode_1byte(0x66); |
| 1423 | encoder.prefix16BitMode(); |
| 1424 | 1424 | } |
| 1425 | 1425 | if (mem_op.reg) |reg| { |
| 1426 | 1426 | if (reg.size() != 64) { |
| ... | ... | @@ -1467,7 +1467,7 @@ fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: i64, code: *std.ArrayList(u8), |
| 1467 | 1467 | getOpCode(tag, .fd, reg.size() == 8).?; |
| 1468 | 1468 | const encoder = try Encoder.init(code, 10); |
| 1469 | 1469 | if (reg.size() == 16) { |
| 1470 | | encoder.opcode_1byte(0x66); |
| 1470 | encoder.prefix16BitMode(); |
| 1471 | 1471 | } |
| 1472 | 1472 | encoder.rex(.{ |
| 1473 | 1473 | .w = setRexWRegister(reg), |
| ... | ... | @@ -1500,7 +1500,7 @@ fn lowerToOiEnc(tag: Tag, reg: Register, imm: i64, code: *std.ArrayList(u8)) Low |
| 1500 | 1500 | const opc = getOpCode(tag, .oi, reg.size() == 8).?; |
| 1501 | 1501 | const encoder = try Encoder.init(code, 10); |
| 1502 | 1502 | if (reg.size() == 16) { |
| 1503 | | encoder.opcode_1byte(0x66); |
| 1503 | encoder.prefix16BitMode(); |
| 1504 | 1504 | } |
| 1505 | 1505 | encoder.rex(.{ |
| 1506 | 1506 | .w = setRexWRegister(reg), |
| ... | ... | @@ -1537,7 +1537,7 @@ fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: i32, code: *std.Arr |
| 1537 | 1537 | // 0x66 prefix switches to the non-default size; here we assume a switch from |
| 1538 | 1538 | // the default 32bits to 16bits operand-size. |
| 1539 | 1539 | // More info: https://www.cs.uni-potsdam.de/desn/lehre/ss15/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf#page=32&zoom=auto,-159,773 |
| 1540 | | encoder.opcode_1byte(0x66); |
| 1540 | encoder.prefix16BitMode(); |
| 1541 | 1541 | } |
| 1542 | 1542 | encoder.rex(.{ |
| 1543 | 1543 | .w = setRexWRegister(dst_reg), |
| ... | ... | @@ -1562,7 +1562,7 @@ fn lowerToMiEnc(tag: Tag, reg_or_mem: RegisterOrMemory, imm: i32, code: *std.Arr |
| 1562 | 1562 | const opc = getOpCode(tag, .mi, dst_mem.ptr_size == .byte_ptr).?; |
| 1563 | 1563 | const encoder = try Encoder.init(code, 12); |
| 1564 | 1564 | if (dst_mem.ptr_size == .word_ptr) { |
| 1565 | | encoder.opcode_1byte(0x66); |
| 1565 | encoder.prefix16BitMode(); |
| 1566 | 1566 | } |
| 1567 | 1567 | if (dst_mem.reg) |dst_reg| { |
| 1568 | 1568 | if (dst_reg.size() != 64) { |
| ... | ... | @@ -1628,7 +1628,7 @@ fn lowerToRmEnc( |
| 1628 | 1628 | } |
| 1629 | 1629 | const encoder = try Encoder.init(code, 9); |
| 1630 | 1630 | if (reg.size() == 16) { |
| 1631 | | encoder.opcode_1byte(0x66); |
| 1631 | encoder.prefix16BitMode(); |
| 1632 | 1632 | } |
| 1633 | 1633 | if (src_mem.reg) |src_reg| { |
| 1634 | 1634 | // TODO handle 32-bit base register - requires prefix 0x67 |
| ... | ... | @@ -1688,7 +1688,7 @@ fn lowerToMrEnc( |
| 1688 | 1688 | } |
| 1689 | 1689 | const encoder = try Encoder.init(code, 9); |
| 1690 | 1690 | if (reg.size() == 16) { |
| 1691 | | encoder.opcode_1byte(0x66); |
| 1691 | encoder.prefix16BitMode(); |
| 1692 | 1692 | } |
| 1693 | 1693 | if (dst_mem.reg) |dst_reg| { |
| 1694 | 1694 | if (dst_reg.size() != 64) { |
| ... | ... | @@ -1732,7 +1732,7 @@ fn lowerToRmiEnc( |
| 1732 | 1732 | const opc = getOpCode(tag, .rmi, false).?; |
| 1733 | 1733 | const encoder = try Encoder.init(code, 13); |
| 1734 | 1734 | if (reg.size() == 16) { |
| 1735 | | encoder.opcode_1byte(0x66); |
| 1735 | encoder.prefix16BitMode(); |
| 1736 | 1736 | } |
| 1737 | 1737 | switch (reg_or_mem) { |
| 1738 | 1738 | .register => |src_reg| { |