authorgravatar for lgustaf1@binghamton.eduLayne Gustafson <lgustaf1@binghamton.edu> 2020-01-16 15:02:45-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-01-19 20:53:20-05:00
log8902f3ca32c22656e1f11b562dc3ad6030da14ac
treedc30d8fb85886990b2d78e049107367b623b298c
parentde8a5cf5f54650a5d043c6ad2c41827037f7f75d
signature Commit is signed but in an unrecognized format.

Enable 64bit feature for riscv64

1 files changed, 18 insertions(+), 3 deletions(-)

src-self-hosted/stage1.zig+18-3
...@@ -833,7 +833,17 @@ export fn stage2_target_details_get_builtin_str(target_details: ?*const Stage2Ta...@@ -833,7 +833,17 @@ export fn stage2_target_details_get_builtin_str(target_details: ?*const Stage2Ta
833 return @as([*:0]const u8, null_terminated_empty_string);833 return @as([*:0]const u8, null_terminated_empty_string);
834}834}
835835
836const riscv_default_features: []*const std.target.Feature = &[_]*const std.target.Feature {836const riscv32_default_features: []*const std.target.Feature = &[_]*const std.target.Feature {
837 &std.target.riscv.feature_a,
838 &std.target.riscv.feature_c,
839 &std.target.riscv.feature_d,
840 &std.target.riscv.feature_f,
841 &std.target.riscv.feature_m,
842 &std.target.riscv.feature_relax,
843};
844
845const riscv64_default_features: []*const std.target.Feature = &[_]*const std.target.Feature {
846 &std.target.riscv.feature_bit64,
837 &std.target.riscv.feature_a,847 &std.target.riscv.feature_a,
838 &std.target.riscv.feature_c,848 &std.target.riscv.feature_c,
839 &std.target.riscv.feature_d,849 &std.target.riscv.feature_d,
...@@ -880,9 +890,14 @@ fn createDefaultTargetDetails(arch: @TagType(std.Target.Arch), os: std.Target.Os...@@ -880,9 +890,14 @@ fn createDefaultTargetDetails(arch: @TagType(std.Target.Arch), os: std.Target.Os
880 const allocator = std.heap.c_allocator;890 const allocator = std.heap.c_allocator;
881891
882 return switch (arch) {892 return switch (arch) {
883 .riscv32, .riscv64 => blk: {893 .riscv32 => blk: {
894 const ptr = try allocator.create(Stage2TargetDetails);
895 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, riscv32_default_features);
896 break :blk ptr;
897 },
898 .riscv64 => blk: {
884 const ptr = try allocator.create(Stage2TargetDetails);899 const ptr = try allocator.create(Stage2TargetDetails);
885 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, riscv_default_features);900 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, riscv64_default_features);
886 break :blk ptr;901 break :blk ptr;
887 },902 },
888 .i386 => blk: {903 .i386 => blk: {