| author |  LemonBoy <thatlemon@gmail.com> 2021-04-06 10:47:29+02:00 |
| committer |  Andrew Kelley <andrew@ziglang.org> 2021-04-06 10:18:11-07:00 |
| log | 89df41e5d859fcd53863c9f707e8c697b794148c |
| tree | 81e9ca43a572041e84d1311d127c6df2f58b35db |
| parent | 2bfc6d14d500dcaf66b8ee7d24637e25e3795a5e |
stage2: Default AVR generic cpu to avr2
The avr1 target is a very minimal subset of the AVR ISA, quoting the GCC
manual:
> This ISA is implemented by the minimal AVR core and supported for
> assembler only.
Default to avr2 as GCC and Clang do.1 files changed, 1 insertions(+), 1 deletions(-)
lib- std
lib/std/target.zig+1-1
| ... | ... | @@ -1170,7 +1170,7 @@ pub const Target = struct { |
| 1170 | 1170 | return switch (arch) { |
| 1171 | 1171 | .arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic, |
| 1172 | 1172 | .aarch64, .aarch64_be, .aarch64_32 => &aarch64.cpu.generic, |
| 1173 | .avr => &avr.cpu.avr1, | |
| 1173 | .avr => &avr.cpu.avr2, | |
| 1174 | 1174 | .bpfel, .bpfeb => &bpf.cpu.generic, |
| 1175 | 1175 | .hexagon => &hexagon.cpu.generic, |
| 1176 | 1176 | .mips, .mipsel => &mips.cpu.mips32, |