authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-05-05 22:33:03+02:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-05-05 22:33:03+02:00
log90a8817f558bb5c5b4292c666b2ed61b4a415f8d
tree0c9378078313be90d1e6859ab5ca9f305cfa2a35
parenteab5a1bd5a6b6fb6f968cb99895a862ad5639f15

aarch64: ensure we set correct operand size at codegen stage

2 files changed, 11 insertions(+), 6 deletions(-)

src/arch/aarch64/CodeGen.zig+7-2
...@@ -1335,8 +1335,6 @@ fn binOpRegister(...@@ -1335,8 +1335,6 @@ fn binOpRegister(
1335 .shift = .lsl,1335 .shift = .lsl,
1336 } },1336 } },
1337 .mul,1337 .mul,
1338 .smull,
1339 .umull,
1340 .lsl_register,1338 .lsl_register,
1341 .asr_register,1339 .asr_register,
1342 .lsr_register,1340 .lsr_register,
...@@ -1345,6 +1343,13 @@ fn binOpRegister(...@@ -1345,6 +1343,13 @@ fn binOpRegister(
1345 .rn = lhs_reg,1343 .rn = lhs_reg,
1346 .rm = rhs_reg,1344 .rm = rhs_reg,
1347 } },1345 } },
1346 .smull,
1347 .umull,
1348 => .{ .rrr = .{
1349 .rd = dest_reg.to64(),
1350 .rn = lhs_reg,
1351 .rm = rhs_reg,
1352 } },
1348 .and_shifted_register,1353 .and_shifted_register,
1349 .orr_shifted_register,1354 .orr_shifted_register,
1350 .eor_shifted_register,1355 .eor_shifted_register,
src/arch/aarch64/Emit.zig+4-4
...@@ -1060,10 +1060,10 @@ fn mirDataProcessing3Source(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -1060,10 +1060,10 @@ fn mirDataProcessing3Source(emit: *Emit, inst: Mir.Inst.Index) !void {
10601060
1061 switch (tag) {1061 switch (tag) {
1062 .mul => try emit.writeInstruction(Instruction.mul(rrr.rd, rrr.rn, rrr.rm)),1062 .mul => try emit.writeInstruction(Instruction.mul(rrr.rd, rrr.rn, rrr.rm)),
1063 .smulh => try emit.writeInstruction(Instruction.smulh(rrr.rd.to64(), rrr.rn.to64(), rrr.rm.to64())),1063 .smulh => try emit.writeInstruction(Instruction.smulh(rrr.rd, rrr.rn, rrr.rm)),
1064 .smull => try emit.writeInstruction(Instruction.smull(rrr.rd.to64(), rrr.rn.to32(), rrr.rm.to32())),1064 .smull => try emit.writeInstruction(Instruction.smull(rrr.rd, rrr.rn, rrr.rm)),
1065 .umulh => try emit.writeInstruction(Instruction.umulh(rrr.rd.to64(), rrr.rn.to64(), rrr.rm.to64())),1065 .umulh => try emit.writeInstruction(Instruction.umulh(rrr.rd, rrr.rn, rrr.rm)),
1066 .umull => try emit.writeInstruction(Instruction.umull(rrr.rd.to64(), rrr.rn.to32(), rrr.rm.to32())),1066 .umull => try emit.writeInstruction(Instruction.umull(rrr.rd, rrr.rn, rrr.rm)),
1067 else => unreachable,1067 else => unreachable,
1068 }1068 }
1069}1069}