authorgravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2022-12-20 18:32:06+02:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2022-12-20 18:34:33+02:00
log9f23702c21645aeddd64bcf203bc8b62a328f75f
tree5305f31f4a4bfa34630cbab71f20c6f76e34f659
parent6da070c5ac1707f2f5370e2e26124a3e114e25ea

llvm: fix C ABI for <=256 bit vectors

Closes #13918

3 files changed, 32 insertions(+), 1 deletions(-)

src/arch/x86_64/abi.zig+2-1
...@@ -143,7 +143,8 @@ pub fn classifySystemV(ty: Type, target: Target, ctx: Context) [8]Class {...@@ -143,7 +143,8 @@ pub fn classifySystemV(ty: Type, target: Target, ctx: Context) [8]Class {
143 .integer, .integer, .integer, .integer,143 .integer, .integer, .integer, .integer,
144 .integer, .integer, .integer, .integer,144 .integer, .integer, .integer, .integer,
145 };145 };
146 if (has_avx512 and bit_size <= 256) return .{146 const has_avx = target.cpu.features.isEnabled(@enumToInt(std.Target.x86.Feature.avx));
147 if (has_avx and bit_size <= 256) return .{
147 .integer, .integer, .integer, .integer,148 .integer, .integer, .integer, .integer,
148 .none, .none, .none, .none,149 .none, .none, .none, .none,
149 };150 };
test/c_abi/cfuncs.c+13
...@@ -742,6 +742,19 @@ SmallVec c_ret_small_vec(void) {...@@ -742,6 +742,19 @@ SmallVec c_ret_small_vec(void) {
742 return (SmallVec){3, 4};742 return (SmallVec){3, 4};
743}743}
744744
745typedef size_t MediumVec __attribute__((vector_size(4 * sizeof(size_t))));
746
747void c_medium_vec(MediumVec vec) {
748 assert_or_panic(vec[0] == 1);
749 assert_or_panic(vec[1] == 2);
750 assert_or_panic(vec[2] == 3);
751 assert_or_panic(vec[3] == 4);
752}
753
754MediumVec c_ret_medium_vec(void) {
755 return (MediumVec){5, 6, 7, 8};
756}
757
745typedef size_t BigVec __attribute__((vector_size(8 * sizeof(size_t))));758typedef size_t BigVec __attribute__((vector_size(8 * sizeof(size_t))));
746759
747void c_big_vec(BigVec vec) {760void c_big_vec(BigVec vec) {
test/c_abi/main.zig+17
...@@ -801,6 +801,23 @@ test "small simd vector" {...@@ -801,6 +801,23 @@ test "small simd vector" {
801 try expect(x[1] == 4);801 try expect(x[1] == 4);
802}802}
803803
804const MediumVec = @Vector(4, usize);
805
806extern fn c_medium_vec(MediumVec) void;
807extern fn c_ret_medium_vec() MediumVec;
808
809test "medium simd vector" {
810 if (comptime builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
811
812 c_medium_vec(.{ 1, 2, 3, 4 });
813
814 var x = c_ret_medium_vec();
815 try expect(x[0] == 5);
816 try expect(x[1] == 6);
817 try expect(x[2] == 7);
818 try expect(x[3] == 8);
819}
820
804const BigVec = @Vector(8, usize);821const BigVec = @Vector(8, usize);
805822
806extern fn c_big_vec(BigVec) void;823extern fn c_big_vec(BigVec) void;