| ... | @@ -401,21 +401,11 @@ fn unwindFrameInner(si: *SelfInfo, gpa: Allocator, context: *UnwindContext) !usi | ... | @@ -401,21 +401,11 @@ fn unwindFrameInner(si: *SelfInfo, gpa: Allocator, context: *UnwindContext) !usi |
| 401 | } | 401 | } |
| 402 | } | 402 | } |
| 403 | | 403 | |
| 404 | inline for (@typeInfo(@TypeOf(frame.d_reg_pairs)).@"struct".fields, 0..) |field, i| { | 404 | // We intentionally skip restoring `frame.d_reg_pairs`; we know we don't support |
| 405 | if (@field(frame.d_reg_pairs, field.name) != 0) { | 405 | // vector registers in the AArch64 `cpu_context` anyway, so there's no reason to |
| 406 | // Only the lower half of the 128-bit V registers are restored during unwinding | 406 | // fail a legitimate unwind just because we're asked to restore the registers here. |
| 407 | { | 407 | // If some weird/broken unwind info tells us to read them later, we will fail then. |
| 408 | const dest: *align(1) usize = @ptrCast(try context.cpu_state.dwarfRegisterBytes(64 + 8 + i)); | 408 | reg_addr += 16 * @as(usize, @popCount(@as(u4, @bitCast(frame.d_reg_pairs)))); |
| 409 | dest.* = @as(*const usize, @ptrFromInt(reg_addr)).*; | | |
| 410 | } | | |
| 411 | reg_addr += @sizeOf(usize); | | |
| 412 | { | | |
| 413 | const dest: *align(1) usize = @ptrCast(try context.cpu_state.dwarfRegisterBytes(64 + 9 + i)); | | |
| 414 | dest.* = @as(*const usize, @ptrFromInt(reg_addr)).*; | | |
| 415 | } | | |
| 416 | reg_addr += @sizeOf(usize); | | |
| 417 | } | | |
| 418 | } | | |
| 419 | | 409 | |
| 420 | const new_ip = @as(*const usize, @ptrFromInt(ip_ptr)).*; | 410 | const new_ip = @as(*const usize, @ptrFromInt(ip_ptr)).*; |
| 421 | const new_fp = @as(*const usize, @ptrFromInt(fp)).*; | 411 | const new_fp = @as(*const usize, @ptrFromInt(fp)).*; |