From b8705ed6527e779a140e8beccb48d424dbbdf856 Mon Sep 17 00:00:00 2001 From: YANG Xudong Date: Thu, 8 Aug 2024 04:06:29 +0800 Subject: [PATCH] loongarch: various architecture specific fixes (#20912) --- lib/std/mem.zig | 8 ++++++++ lib/std/os/linux.zig | 1 + src/glibc.zig | 1 + src/musl.zig | 3 ++- 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/lib/std/mem.zig b/lib/std/mem.zig index 984f1198acd6bccb24c7c549504817775c181607..1fd8af950a94b3f8003f650aec96a7fb8715b4e7 100644 --- a/lib/std/mem.zig +++ b/lib/std/mem.zig @@ -17,6 +17,14 @@ pub const page_size = switch (builtin.cpu.arch) { else => 4 * 1024, }, .sparc64 => 8 * 1024, + .loongarch32, .loongarch64 => switch (builtin.os.tag) { + // Linux default KConfig value is 16KiB + .linux => 16 * 1024, + // FIXME: + // There is no other OS supported yet. Use the same value + // as Linux for now. + else => 16 * 1024, + }, else => 4 * 1024, }; diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig index 5f3f043d321d186385f3bcd18a2dba95e0547c41..8f3b6a8eccc3ffbca1d8b2b849cc0bd994712814 100644 --- a/lib/std/os/linux.zig +++ b/lib/std/os/linux.zig @@ -132,6 +132,7 @@ pub const SYS = switch (@import("builtin").cpu.arch) { .riscv64 => syscalls.RiscV64, .sparc => syscalls.Sparc, .sparc64 => syscalls.Sparc64, + .loongarch64 => syscalls.LoongArch64, .m68k => syscalls.M68k, .mips, .mipsel => syscalls.MipsO32, .mips64, .mips64el => if (builtin.abi == .gnuabin32) diff --git a/src/glibc.zig b/src/glibc.zig index a2c8e17430e35cd417e8e55248682407036311fe..2424690960230612329d20dbaf9c23566ee4e032 100644 --- a/src/glibc.zig +++ b/src/glibc.zig @@ -1182,6 +1182,7 @@ fn buildSharedLib( pub fn needsCrtiCrtn(target: std.Target) bool { return switch (target.cpu.arch) { .riscv32, .riscv64 => false, + .loongarch64 => false, else => true, }; } diff --git a/src/musl.zig b/src/musl.zig index a267993fbe6a9c7e88c9b8e49edf064c01e54585..1c20c209687bc1079f55cc1085fb46777261f1cf 100644 --- a/src/musl.zig +++ b/src/musl.zig @@ -293,7 +293,8 @@ pub fn needsCrtiCrtn(target: std.Target) bool { return switch (target.cpu.arch) { .riscv32, .riscv64, - .wasm32, .wasm64 => return false, + .wasm32, .wasm64 => false, + .loongarch64 => false, else => true, }; // zig fmt: on -- 2.54.0