| ... | ... | @@ -13715,7 +13715,9 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr |
| 13715 | 13715 | .load_frame => |frame_addr| try self.moveStrategy( |
| 13716 | 13716 | ty, |
| 13717 | 13717 | dst_reg.class(), |
| 13718 | | self.getFrameAddrAlignment(frame_addr).compare(.gte, ty.abiAlignment(mod)), |
| 13718 | self.getFrameAddrAlignment(frame_addr).compare(.gte, Alignment.fromLog2Units( |
| 13719 | std.math.log2_int_ceil(u10, @divExact(dst_reg.bitSize(), 8)), |
| 13720 | )), |
| 13719 | 13721 | ), |
| 13720 | 13722 | .lea_frame => .{ .move = .{ ._, .lea } }, |
| 13721 | 13723 | else => unreachable, |