authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-03-05 07:59:58+01:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-04-04 06:08:10+02:00
logcf9c6f5298924f95e83f2be0e9efb50fe2f61d92
treef7e12a708869a4fd8e32a20b227adac084caa91c
parent4c5c5bcd917fe718609360793a8883fbc77f1885
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

compiler: Update max int alignments for some targets.

2 files changed, 36 insertions(+), 84 deletions(-)

src/Type.zig+23-32
...@@ -1641,69 +1641,60 @@ pub fn intAbiAlignment(bits: u16, target: Target) Alignment {...@@ -1641,69 +1641,60 @@ pub fn intAbiAlignment(bits: u16, target: Target) Alignment {
1641pub fn maxIntAlignment(target: std.Target) u16 {1641pub fn maxIntAlignment(target: std.Target) u16 {
1642 return switch (target.cpu.arch) {1642 return switch (target.cpu.arch) {
1643 .avr => 1,1643 .avr => 1,
1644
1644 .msp430 => 2,1645 .msp430 => 2,
1645 .xcore => 4,
1646 .propeller => 4,
16471646
1647 .xcore,
1648 .propeller,
1649 => 4,
1650
1651 .amdgcn,
1648 .arm,1652 .arm,
1649 .armeb,1653 .armeb,
1650 .thumb,1654 .thumb,
1651 .thumbeb,1655 .thumbeb,
1656 .lanai,
1652 .hexagon,1657 .hexagon,
1653 .mips,1658 .mips,
1654 .mipsel,1659 .mipsel,
1655 .powerpc,1660 .powerpc,
1656 .powerpcle,1661 .powerpcle,
1657 .amdgcn,
1658 .riscv32,1662 .riscv32,
1659 .sparc,
1660 .s390x,1663 .s390x,
1661 .lanai,
1662 .wasm32,
1663 .wasm64,
1664 => 8,1664 => 8,
16651665
1666 // For these, LLVMABIAlignmentOfType(i128) reports 8. Note that 16
1667 // is a relevant number in three cases:
1668 // 1. Different machine code instruction when loading into SIMD register.
1669 // 2. The C ABI wants 16 for extern structs.
1670 // 3. 16-byte cmpxchg needs 16-byte alignment.
1671 // Same logic for powerpc64, mips64, sparc64.
1672 .powerpc64,
1673 .powerpc64le,
1674 .mips64,
1675 .mips64el,
1676 .sparc64,
1677 => switch (target.ofmt) {
1678 .c => 16,
1679 else => 8,
1680 },
1681
1682 .x86_64 => 16,
1683
1684 // Even LLVMABIAlignmentOfType(i128) agrees on these targets.1666 // Even LLVMABIAlignmentOfType(i128) agrees on these targets.
1685 .x86,
1686 .aarch64,1667 .aarch64,
1687 .aarch64_be,1668 .aarch64_be,
1688 .riscv64,
1689 .bpfel,1669 .bpfel,
1690 .bpfeb,1670 .bpfeb,
1671 .mips64,
1672 .mips64el,
1691 .nvptx,1673 .nvptx,
1692 .nvptx64,1674 .nvptx64,
1675 .powerpc64,
1676 .powerpc64le,
1677 .riscv64,
1678 .sparc,
1679 .sparc64,
1680 .wasm32,
1681 .wasm64,
1682 .x86,
1683 .x86_64,
1693 => 16,1684 => 16,
16941685
1695 // Below this comment are unverified but based on the fact that C requires1686 // Below this comment are unverified but based on the fact that C requires
1696 // int128_t to be 16 bytes aligned, it's a safe default.1687 // int128_t to be 16 bytes aligned, it's a safe default.
1697 .csky,
1698 .arc,1688 .arc,
1699 .m68k,1689 .csky,
1700 .kalimba,1690 .kalimba,
1691 .loongarch32,
1692 .loongarch64,
1693 .m68k,
1701 .spirv,1694 .spirv,
1702 .spirv32,1695 .spirv32,
1703 .ve,
1704 .spirv64,1696 .spirv64,
1705 .loongarch32,1697 .ve,
1706 .loongarch64,
1707 .xtensa,1698 .xtensa,
1708 => 16,1699 => 16,
1709 };1700 };
test/behavior/align.zig+13-52
...@@ -85,22 +85,19 @@ test "alignment and size of structs with 128-bit fields" {...@@ -85,22 +85,19 @@ test "alignment and size of structs with 128-bit fields" {
85 y: u8,85 y: u8,
86 };86 };
87 const expected = switch (builtin.cpu.arch) {87 const expected = switch (builtin.cpu.arch) {
88 .amdgcn,
88 .arm,89 .arm,
89 .armeb,90 .armeb,
90 .thumb,91 .thumb,
91 .thumbeb,92 .thumbeb,
92 .hexagon,93 .hexagon,
94 .lanai,
93 .mips,95 .mips,
94 .mipsel,96 .mipsel,
95 .powerpc,97 .powerpc,
96 .powerpcle,98 .powerpcle,
97 .amdgcn,
98 .riscv32,99 .riscv32,
99 .sparc,
100 .s390x,100 .s390x,
101 .lanai,
102 .wasm32,
103 .wasm64,
104 => .{101 => .{
105 .a_align = 8,102 .a_align = 8,
106 .a_size = 16,103 .a_size = 16,
...@@ -114,59 +111,23 @@ test "alignment and size of structs with 128-bit fields" {...@@ -114,59 +111,23 @@ test "alignment and size of structs with 128-bit fields" {
114 .u129_size = 24,111 .u129_size = 24,
115 },112 },
116113
117 .mips64,
118 .mips64el,
119 .powerpc64,
120 .powerpc64le,
121 .sparc64,
122 => switch (builtin.object_format) {
123 .c => .{
124 .a_align = 16,
125 .a_size = 16,
126
127 .b_align = 16,
128 .b_size = 32,
129
130 .u128_align = 16,
131 .u128_size = 16,
132 .u129_align = 16,
133 .u129_size = 32,
134 },
135 else => .{
136 .a_align = 8,
137 .a_size = 16,
138
139 .b_align = 16,
140 .b_size = 32,
141
142 .u128_align = 8,
143 .u128_size = 16,
144 .u129_align = 8,
145 .u129_size = 24,
146 },
147 },
148
149 .x86_64 => .{
150 .a_align = 16,
151 .a_size = 16,
152
153 .b_align = 16,
154 .b_size = 32,
155
156 .u128_align = 16,
157 .u128_size = 16,
158 .u129_align = 16,
159 .u129_size = 32,
160 },
161
162 .x86,
163 .aarch64,114 .aarch64,
164 .aarch64_be,115 .aarch64_be,
165 .riscv64,
166 .bpfel,116 .bpfel,
167 .bpfeb,117 .bpfeb,
118 .mips64,
119 .mips64el,
168 .nvptx,120 .nvptx,
169 .nvptx64,121 .nvptx64,
122 .powerpc64,
123 .powerpc64le,
124 .sparc,
125 .sparc64,
126 .riscv64,
127 .wasm32,
128 .wasm64,
129 .x86,
130 .x86_64,
170 => .{131 => .{
171 .a_align = 16,132 .a_align = 16,
172 .a_size = 16,133 .a_size = 16,