| ... | ... | @@ -484,7 +484,23 @@ pub const Instruction = union(enum) { |
| 484 | 484 | } |
| 485 | 485 | }; |
| 486 | 486 | |
| 487 | | fn loadStoreRegister(rt: Register, rn: Register, offset: LoadStoreOffset, load: bool) Instruction { |
| 487 | /// Which kind of load/store to perform |
| 488 | const LoadStoreVariant = enum { |
| 489 | /// 32-bit or 64-bit |
| 490 | normal, |
| 491 | /// 16-bit |
| 492 | half, |
| 493 | /// 8-bit |
| 494 | byte, |
| 495 | }; |
| 496 | |
| 497 | fn loadStoreRegister( |
| 498 | rt: Register, |
| 499 | rn: Register, |
| 500 | offset: LoadStoreOffset, |
| 501 | variant: LoadStoreVariant, |
| 502 | load: bool, |
| 503 | ) Instruction { |
| 488 | 504 | const off = offset.toU12(); |
| 489 | 505 | const op1: u2 = blk: { |
| 490 | 506 | switch (offset) { |
| ... | ... | @@ -497,35 +513,27 @@ pub const Instruction = union(enum) { |
| 497 | 513 | break :blk 0b00; |
| 498 | 514 | }; |
| 499 | 515 | const opc: u2 = if (load) 0b01 else 0b00; |
| 500 | | switch (rt.size()) { |
| 501 | | 32 => { |
| 502 | | return Instruction{ |
| 503 | | .LoadStoreRegister = .{ |
| 504 | | .rt = rt.id(), |
| 505 | | .rn = rn.id(), |
| 506 | | .offset = offset.toU12(), |
| 507 | | .opc = opc, |
| 508 | | .op1 = op1, |
| 509 | | .v = 0, |
| 510 | | .size = 0b10, |
| 511 | | }, |
| 512 | | }; |
| 513 | | }, |
| 514 | | 64 => { |
| 515 | | return Instruction{ |
| 516 | | .LoadStoreRegister = .{ |
| 517 | | .rt = rt.id(), |
| 518 | | .rn = rn.id(), |
| 519 | | .offset = offset.toU12(), |
| 520 | | .opc = opc, |
| 521 | | .op1 = op1, |
| 522 | | .v = 0, |
| 523 | | .size = 0b11, |
| 524 | | }, |
| 525 | | }; |
| 516 | return Instruction{ |
| 517 | .LoadStoreRegister = .{ |
| 518 | .rt = rt.id(), |
| 519 | .rn = rn.id(), |
| 520 | .offset = off, |
| 521 | .opc = opc, |
| 522 | .op1 = op1, |
| 523 | .v = 0, |
| 524 | .size = blk: { |
| 525 | switch (variant) { |
| 526 | .normal => switch (rt.size()) { |
| 527 | 32 => break :blk 0b10, |
| 528 | 64 => break :blk 0b11, |
| 529 | else => unreachable, // unexpected register size |
| 530 | }, |
| 531 | .half => break :blk 0b01, |
| 532 | .byte => break :blk 0b00, |
| 533 | } |
| 534 | }, |
| 526 | 535 | }, |
| 527 | | else => unreachable, // unexpected register size |
| 528 | | } |
| 536 | }; |
| 529 | 537 | } |
| 530 | 538 | |
| 531 | 539 | fn loadStorePairOfRegisters( |
| ... | ... | @@ -748,7 +756,7 @@ pub const Instruction = union(enum) { |
| 748 | 756 | |
| 749 | 757 | pub fn ldr(rt: Register, args: LdrArgs) Instruction { |
| 750 | 758 | switch (args) { |
| 751 | | .register => |info| return loadStoreRegister(rt, info.rn, info.offset, true), |
| 759 | .register => |info| return loadStoreRegister(rt, info.rn, info.offset, .normal, true), |
| 752 | 760 | .literal => |literal| return loadLiteral(rt, literal), |
| 753 | 761 | } |
| 754 | 762 | } |
| ... | ... | @@ -758,7 +766,15 @@ pub const Instruction = union(enum) { |
| 758 | 766 | }; |
| 759 | 767 | |
| 760 | 768 | pub fn str(rt: Register, rn: Register, args: StrArgs) Instruction { |
| 761 | | return loadStoreRegister(rt, rn, args.offset, false); |
| 769 | return loadStoreRegister(rt, rn, args.offset, .normal, false); |
| 770 | } |
| 771 | |
| 772 | pub fn strh(rt: Register, rn: Register, args: StrArgs) Instruction { |
| 773 | return loadStoreRegister(rt, rn, args.offset, .half, false); |
| 774 | } |
| 775 | |
| 776 | pub fn strb(rt: Register, rn: Register, args: StrArgs) Instruction { |
| 777 | return loadStoreRegister(rt, rn, args.offset, .byte, false); |
| 762 | 778 | } |
| 763 | 779 | |
| 764 | 780 | // Load or store pair of registers |
| ... | ... | @@ -996,6 +1012,14 @@ test "serialize instructions" { |
| 996 | 1012 | .inst = Instruction.str(.x2, .x1, .{ .offset = Instruction.LoadStoreOffset.reg(.x3) }), |
| 997 | 1013 | .expected = 0b11_111_0_00_00_1_00011_011_0_10_00001_00010, |
| 998 | 1014 | }, |
| 1015 | .{ // strh w0, [x1] |
| 1016 | .inst = Instruction.strh(.w0, .x1, .{}), |
| 1017 | .expected = 0b01_111_0_01_00_000000000000_00001_00000, |
| 1018 | }, |
| 1019 | .{ // strb w8, [x9] |
| 1020 | .inst = Instruction.strb(.w8, .x9, .{}), |
| 1021 | .expected = 0b00_111_0_01_00_000000000000_01001_01000, |
| 1022 | }, |
| 999 | 1023 | .{ // adr x2, #0x8 |
| 1000 | 1024 | .inst = Instruction.adr(.x2, 0x8), |
| 1001 | 1025 | .expected = 0b0_00_10000_0000000000000000010_00010, |