authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2024-06-22 22:13:49-07:00
committergravatar for mlugg@mlugg.co.ukMatthew Lugg <mlugg@mlugg.co.uk> 2024-06-23 15:26:14+01:00
loge73ae94b3640ef74c9614c2da6a0200ff444f3e8
tree247f825ed81e6f85eb35ed69cdbaad076d53d0ec
parentf3655fd07dbd30d3c7ed95d92df192a78b081a3a

riscv: remove deprecated `Module` usages

4 files changed, 14 insertions(+), 22 deletions(-)

src/arch/riscv64/CodeGen.zig+8-10
......@@ -11,12 +11,10 @@ const Type = @import("../../type.zig").Type;
1111const Value = @import("../../Value.zig");
1212const link = @import("../../link.zig");
1313const Zcu = @import("../../Zcu.zig");
14/// Deprecated.
15const Module = Zcu;
1614const Package = @import("../../Package.zig");
1715const InternPool = @import("../../InternPool.zig");
1816const Compilation = @import("../../Compilation.zig");
19const ErrorMsg = Module.ErrorMsg;
17const ErrorMsg = Zcu.ErrorMsg;
2018const Target = std.Target;
2119const Allocator = mem.Allocator;
2220const trace = @import("../../tracy.zig").trace;
......@@ -61,7 +59,7 @@ args: []MCValue,
6159ret_mcv: InstTracking,
6260fn_type: Type,
6361arg_index: usize,
64src_loc: Module.SrcLoc,
62src_loc: Zcu.SrcLoc,
6563
6664/// MIR Instructions
6765mir_instructions: std.MultiArrayList(Mir.Inst) = .{},
......@@ -543,13 +541,13 @@ const FrameAlloc = struct {
543541 .ref_count = 0,
544542 };
545543 }
546 fn initType(ty: Type, zcu: *Module) FrameAlloc {
544 fn initType(ty: Type, zcu: *Zcu) FrameAlloc {
547545 return init(.{
548546 .size = ty.abiSize(zcu),
549547 .alignment = ty.abiAlignment(zcu),
550548 });
551549 }
552 fn initSpill(ty: Type, zcu: *Module) FrameAlloc {
550 fn initSpill(ty: Type, zcu: *Zcu) FrameAlloc {
553551 const abi_size = ty.abiSize(zcu);
554552 const spill_size = if (abi_size < 8)
555553 math.ceilPowerOfTwoAssert(u64, abi_size)
......@@ -698,7 +696,7 @@ const CallView = enum(u1) {
698696
699697pub fn generate(
700698 bin_file: *link.File,
701 src_loc: Module.SrcLoc,
699 src_loc: Zcu.SrcLoc,
702700 func_index: InternPool.Index,
703701 air: Air,
704702 liveness: Liveness,
......@@ -922,7 +920,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir)
922920}
923921
924922const FormatDeclData = struct {
925 mod: *Module,
923 mod: *Zcu,
926924 decl_index: InternPool.DeclIndex,
927925};
928926fn formatDecl(
......@@ -6636,7 +6634,7 @@ fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool {
66366634 return Target.riscv.featureSetHas(func.target.cpu.features, feature);
66376635}
66386636
6639pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {
6637pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Zcu) u64 {
66406638 if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;
66416639 const payload_align = payload_ty.abiAlignment(zcu);
66426640 const error_align = Type.anyerror.abiAlignment(zcu);
......@@ -6647,7 +6645,7 @@ pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {
66476645 }
66486646}
66496647
6650pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Module) u64 {
6648pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Zcu) u64 {
66516649 if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;
66526650 const payload_align = payload_ty.abiAlignment(zcu);
66536651 const error_align = Type.anyerror.abiAlignment(zcu);
src/arch/riscv64/Lower.zig+2-4
......@@ -8,7 +8,7 @@ allocator: Allocator,
88mir: Mir,
99cc: std.builtin.CallingConvention,
1010err_msg: ?*ErrorMsg = null,
11src_loc: Module.SrcLoc,
11src_loc: Zcu.SrcLoc,
1212result_insts_len: u8 = undefined,
1313result_relocs_len: u8 = undefined,
1414result_insts: [
......@@ -520,10 +520,8 @@ const log = std.log.scoped(.lower);
520520
521521const Air = @import("../../Air.zig");
522522const Allocator = std.mem.Allocator;
523const ErrorMsg = Module.ErrorMsg;
523const ErrorMsg = Zcu.ErrorMsg;
524524const Mir = @import("Mir.zig");
525525const Zcu = @import("../../Zcu.zig");
526/// Deprecated.
527const Module = Zcu;
528526const Instruction = encoder.Instruction;
529527const Immediate = bits.Immediate;
src/arch/riscv64/abi.zig+3-5
......@@ -5,13 +5,11 @@ const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
55const Type = @import("../../type.zig").Type;
66const InternPool = @import("../../InternPool.zig");
77const Zcu = @import("../../Zcu.zig");
8/// Deprecated.
9const Module = Zcu;
108const assert = std.debug.assert;
119
1210pub const Class = enum { memory, byval, integer, double_integer, fields };
1311
14pub fn classifyType(ty: Type, mod: *Module) Class {
12pub fn classifyType(ty: Type, mod: *Zcu) Class {
1513 const target = mod.getTarget();
1614 std.debug.assert(ty.hasRuntimeBitsIgnoreComptime(mod));
1715
......@@ -99,7 +97,7 @@ pub const SystemClass = enum { integer, float, memory, none };
9997
10098/// There are a maximum of 8 possible return slots. Returned values are in
10199/// the beginning of the array; unused slots are filled with .none.
102pub fn classifySystem(ty: Type, zcu: *Module) [8]SystemClass {
100pub fn classifySystem(ty: Type, zcu: *Zcu) [8]SystemClass {
103101 var result = [1]SystemClass{.none} ** 8;
104102 const memory_class = [_]SystemClass{
105103 .memory, .none, .none, .none,
......@@ -202,7 +200,7 @@ fn classifyStruct(
202200 result: *[8]Class,
203201 byte_offset: *u64,
204202 loaded_struct: InternPool.LoadedStructType,
205 zcu: *Module,
203 zcu: *Zcu,
206204) void {
207205 const ip = &zcu.intern_pool;
208206 var field_it = loaded_struct.iterateRuntimeOrder(ip);
src/arch/riscv64/bits.zig+1-3
......@@ -5,8 +5,6 @@ const testing = std.testing;
55const Target = std.Target;
66
77const Zcu = @import("../../Zcu.zig");
8/// Deprecated.
9const Module = Zcu;
108const Encoding = @import("Encoding.zig");
119const Mir = @import("Mir.zig");
1210const abi = @import("abi.zig");
......@@ -202,7 +200,7 @@ pub const Register = enum(u8) {
202200 return @as(u8, reg.id());
203201 }
204202
205 pub fn bitSize(reg: Register, zcu: *const Module) u32 {
203 pub fn bitSize(reg: Register, zcu: *const Zcu) u32 {
206204 const features = zcu.getTarget().cpu.features;
207205
208206 return switch (@intFromEnum(reg)) {