| author | |
| committer | |
| log | ee06b2ce760d927b62726de1e2e3cb33b48d4932 |
| tree | 6046947d801d8c10b3dd1fd98d3ae8aba5da187a |
| parent | d18eaf8586cf173d5605d5885fcbe26d64af00c5 |
4 files changed, 9 insertions(+), 20 deletions(-)
lib/std/Target/spirv.zig+1-13| ... | ... | @@ -10,8 +10,6 @@ pub const Feature = enum { |
| 10 | 10 | v1_4, |
| 11 | 11 | v1_5, |
| 12 | 12 | v1_6, |
| 13 | int8, | |
| 14 | int16, | |
| 15 | 13 | int64, |
| 16 | 14 | float16, |
| 17 | 15 | float64, |
| ... | ... | @@ -71,16 +69,6 @@ pub const all_features = blk: { |
| 71 | 69 | .description = "Enable version 1.6", |
| 72 | 70 | .dependencies = featureSet(&[_]Feature{.v1_5}), |
| 73 | 71 | }; |
| 74 | result[@intFromEnum(Feature.int8)] = .{ | |
| 75 | .llvm_name = null, | |
| 76 | .description = "Enable Int8 capability", | |
| 77 | .dependencies = featureSet(&[_]Feature{.v1_0}), | |
| 78 | }; | |
| 79 | result[@intFromEnum(Feature.int16)] = .{ | |
| 80 | .llvm_name = null, | |
| 81 | .description = "Enable Int16 capability", | |
| 82 | .dependencies = featureSet(&[_]Feature{.v1_0}), | |
| 83 | }; | |
| 84 | 72 | result[@intFromEnum(Feature.int64)] = .{ |
| 85 | 73 | .llvm_name = null, |
| 86 | 74 | .description = "Enable Int64 capability", |
| ... | ... | @@ -109,7 +97,7 @@ pub const all_features = blk: { |
| 109 | 97 | result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{ |
| 110 | 98 | .llvm_name = null, |
| 111 | 99 | .description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability", |
| 112 | .dependencies = featureSet(&[_]Feature{ .v1_5, .int8, .int16 }), | |
| 100 | .dependencies = featureSet(&[_]Feature{.v1_5}), | |
| 113 | 101 | }; |
| 114 | 102 | result[@intFromEnum(Feature.kernel)] = .{ |
| 115 | 103 | .llvm_name = null, |
src/codegen/spirv.zig+4-4| ... | ... | @@ -588,11 +588,11 @@ const NavGen = struct { |
| 588 | 588 | |
| 589 | 589 | if (self.spv.hasFeature(.arbitrary_precision_integers) and bits <= 32) return bits; |
| 590 | 590 | |
| 591 | // 8, 16 and 64-bit integers require the Int8, Int16 and Inr64 capabilities respectively. | |
| 591 | // We require Int8 and Int16 capabilities and benefit Int64 when available. | |
| 592 | 592 | // 32-bit integers are always supported (see spec, 2.16.1, Data rules). |
| 593 | 593 | const ints = [_]struct { bits: u16, feature: ?Target.spirv.Feature }{ |
| 594 | .{ .bits = 8, .feature = .int8 }, | |
| 595 | .{ .bits = 16, .feature = .int16 }, | |
| 594 | .{ .bits = 8, .feature = null }, | |
| 595 | .{ .bits = 16, .feature = null }, | |
| 596 | 596 | .{ .bits = 32, .feature = null }, |
| 597 | 597 | .{ .bits = 64, .feature = .int64 }, |
| 598 | 598 | }; |
| ... | ... | @@ -1373,7 +1373,7 @@ const NavGen = struct { |
| 1373 | 1373 | var member_types: [4]IdRef = undefined; |
| 1374 | 1374 | var member_names: [4][]const u8 = undefined; |
| 1375 | 1375 | |
| 1376 | const u8_ty_id = try self.resolveType(Type.u8, .direct); // TODO: What if Int8Type is not enabled? | |
| 1376 | const u8_ty_id = try self.resolveType(Type.u8, .direct); | |
| 1377 | 1377 | |
| 1378 | 1378 | if (layout.tag_size != 0) { |
| 1379 | 1379 | const tag_ty_id = try self.resolveType(Type.fromInterned(union_obj.enum_tag_ty), .indirect); |
src/codegen/spirv/Module.zig+3-2| ... | ... | @@ -333,8 +333,6 @@ pub fn finalize(self: *Module, a: Allocator) ![]Word { |
| 333 | 333 | // Versions |
| 334 | 334 | .v1_0, .v1_1, .v1_2, .v1_3, .v1_4, .v1_5, .v1_6 => {}, |
| 335 | 335 | // Features with no dependencies |
| 336 | .int8 => try self.addCapability(.Int8), | |
| 337 | .int16 => try self.addCapability(.Int16), | |
| 338 | 336 | .int64 => try self.addCapability(.Int64), |
| 339 | 337 | .float16 => try self.addCapability(.Float16), |
| 340 | 338 | .float64 => try self.addCapability(.Float64), |
| ... | ... | @@ -361,6 +359,9 @@ pub fn finalize(self: *Module, a: Allocator) ![]Word { |
| 361 | 359 | } |
| 362 | 360 | } |
| 363 | 361 | } |
| 362 | // These are well supported | |
| 363 | try self.addCapability(.Int8); | |
| 364 | try self.addCapability(.Int16); | |
| 364 | 365 | |
| 365 | 366 | // Emit memory model |
| 366 | 367 | const addressing_model: spec.AddressingModel = blk: { |
test/tests.zig+1-1| ... | ... | @@ -143,7 +143,7 @@ const test_targets = blk: { |
| 143 | 143 | .{ |
| 144 | 144 | .target = std.Target.Query.parse(.{ |
| 145 | 145 | .arch_os_abi = "spirv64-vulkan", |
| 146 | .cpu_features = "vulkan_v1_2+int8+int16+int64+float16+float64", | |
| 146 | .cpu_features = "vulkan_v1_2+int64+float16+float64", | |
| 147 | 147 | }) catch unreachable, |
| 148 | 148 | .use_llvm = false, |
| 149 | 149 | .use_lld = false, |