authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-29 20:26:39+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-08-01 01:07:56-07:00
logf03d54f0692967872f6d5664597d3e349d79c2a3
treea53cf0543f7a310f05e29d49c9abd252e1b24293
parent604e87a95868094bdddbcc6a4579f8535ae5e2a9

std.atomic: Don't lie to the compiler about memory clobbers in spinLoopHint().

1 files changed, 8 insertions(+), 16 deletions(-)

lib/std/atomic.zig+8-16
......@@ -380,7 +380,7 @@ pub inline fn spinLoopHint() void {
380380 // https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
381381 .x86,
382382 .x86_64,
383 => asm volatile ("pause" ::: "memory"),
383 => asm volatile ("pause"),
384384
385385 // No-op instruction that serves as a hardware-thread resource yield hint.
386386 // https://stackoverflow.com/a/7588941
......@@ -388,7 +388,7 @@ pub inline fn spinLoopHint() void {
388388 .powerpcle,
389389 .powerpc64,
390390 .powerpc64le,
391 => asm volatile ("or 27, 27, 27" ::: "memory"),
391 => asm volatile ("or 27, 27, 27"),
392392
393393 // `isb` appears more reliable for releasing execution resources than `yield`
394394 // on common aarch64 CPUs.
......@@ -396,7 +396,7 @@ pub inline fn spinLoopHint() void {
396396 // https://bugs.mysql.com/bug.php?id=100664
397397 .aarch64,
398398 .aarch64_be,
399 => asm volatile ("isb" ::: "memory"),
399 => asm volatile ("isb"),
400400
401401 // `yield` was introduced in v6k but is also available on v6m.
402402 // https://www.keil.com/support/man/docs/armasm/armasm_dom1361289926796.htm
......@@ -409,30 +409,22 @@ pub inline fn spinLoopHint() void {
409409 .has_v6k, .has_v6m,
410410 });
411411 if (can_yield) {
412 asm volatile ("yield" ::: "memory");
413 } else {
414 asm volatile ("" ::: "memory");
412 asm volatile ("yield");
415413 }
416414 },
417415
418416 // The 8-bit immediate specifies the amount of cycles to pause for. We can't really be too
419417 // opinionated here.
420418 .hexagon,
421 => asm volatile ("pause(#1)" ::: "memory"),
419 => asm volatile ("pause(#1)"),
422420
423421 .riscv32,
424422 .riscv64,
425 => {
426 if (comptime std.Target.riscv.featureSetHas(builtin.target.cpu.features, .zihintpause)) {
427 asm volatile ("pause" ::: "memory");
428 } else {
429 asm volatile ("" ::: "memory");
430 }
423 => if (comptime std.Target.riscv.featureSetHas(builtin.target.cpu.features, .zihintpause)) {
424 asm volatile ("pause");
431425 },
432426
433 // Memory barrier to prevent the compiler from optimizing away the spin-loop
434 // even if no hint_instruction was provided.
435 else => asm volatile ("" ::: "memory"),
427 else => {},
436428 }
437429}
438430