authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-03-01 19:11:37-08:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2021-03-01 19:11:37-08:00
logf296c95599dc66b5aed48dcb93c6b63784c853d8
treeb86ae0ae282dfffdfd617a375e92f8491456e8a8
parentf9c9b9217551b98a1d25ff6462c035b8d3a99fe1
parent278bd60732df558cd43b67166cde8e0410e45428
signature Signed by PGP key 4AEE18F83AFDEB23

Merge pull request #8120 from joachimschmidt557/stage2-arm

stage2 ARM: implement basic integer multiplication

5 files changed, 82 insertions(+), 0 deletions(-)

src/codegen.zig+43
...@@ -899,6 +899,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -899,6 +899,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
899 .load => return self.genLoad(inst.castTag(.load).?),899 .load => return self.genLoad(inst.castTag(.load).?),
900 .loop => return self.genLoop(inst.castTag(.loop).?),900 .loop => return self.genLoop(inst.castTag(.loop).?),
901 .not => return self.genNot(inst.castTag(.not).?),901 .not => return self.genNot(inst.castTag(.not).?),
902 .mul => return self.genMul(inst.castTag(.mul).?),
902 .ptrtoint => return self.genPtrToInt(inst.castTag(.ptrtoint).?),903 .ptrtoint => return self.genPtrToInt(inst.castTag(.ptrtoint).?),
903 .ref => return self.genRef(inst.castTag(.ref).?),904 .ref => return self.genRef(inst.castTag(.ref).?),
904 .ret => return self.genRet(inst.castTag(.ret).?),905 .ret => return self.genRet(inst.castTag(.ret).?),
...@@ -1128,6 +1129,16 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1128,6 +1129,16 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1128 }1129 }
1129 }1130 }
11301131
1132 fn genMul(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
1133 // No side effects, so if it's unreferenced, do nothing.
1134 if (inst.base.isUnused())
1135 return MCValue.dead;
1136 switch (arch) {
1137 .arm, .armeb => return try self.genArmMul(&inst.base, inst.lhs, inst.rhs),
1138 else => return self.fail(inst.base.src, "TODO implement mul for {}", .{self.target.cpu.arch}),
1139 }
1140 }
1141
1131 fn genBitAnd(self: *Self, inst: *ir.Inst.BinOp) !MCValue {1142 fn genBitAnd(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
1132 // No side effects, so if it's unreferenced, do nothing.1143 // No side effects, so if it's unreferenced, do nothing.
1133 if (inst.base.isUnused())1144 if (inst.base.isUnused())
...@@ -1478,6 +1489,38 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -1478,6 +1489,38 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
1478 }1489 }
1479 }1490 }
14801491
1492 fn genArmMul(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst) !MCValue {
1493 const lhs = try self.resolveInst(op_lhs);
1494 const rhs = try self.resolveInst(op_rhs);
1495
1496 // Destination must be a register
1497 // LHS must be a register
1498 // RHS must be a register
1499 var dst_mcv: MCValue = undefined;
1500 var lhs_mcv: MCValue = undefined;
1501 var rhs_mcv: MCValue = undefined;
1502 if (self.reuseOperand(inst, 0, lhs)) {
1503 // LHS is the destination
1504 lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs;
1505 rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
1506 dst_mcv = lhs_mcv;
1507 } else if (self.reuseOperand(inst, 1, rhs)) {
1508 // RHS is the destination
1509 lhs_mcv = if (lhs != .register) try self.copyToNewRegister(inst, lhs) else lhs;
1510 rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
1511 dst_mcv = rhs_mcv;
1512 } else {
1513 // TODO save 1 copy instruction by directly allocating the destination register
1514 // LHS is the destination
1515 lhs_mcv = try self.copyToNewRegister(inst, lhs);
1516 rhs_mcv = if (rhs != .register) try self.copyToNewRegister(inst, rhs) else rhs;
1517 dst_mcv = lhs_mcv;
1518 }
1519
1520 writeInt(u32, try self.code.addManyAsArray(4), Instruction.mul(.al, dst_mcv.register, lhs_mcv.register, rhs_mcv.register).toU32());
1521 return dst_mcv;
1522 }
1523
1481 /// ADD, SUB, XOR, OR, AND1524 /// ADD, SUB, XOR, OR, AND
1482 fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue {1525 fn genX8664BinMath(self: *Self, inst: *ir.Inst, op_lhs: *ir.Inst, op_rhs: *ir.Inst, opx: u8, mr: u8) !MCValue {
1483 try self.code.ensureCapacity(self.code.items.len + 8);1526 try self.code.ensureCapacity(self.code.items.len + 8);
src/ir.zig+2
...@@ -106,6 +106,7 @@ pub const Inst = struct {...@@ -106,6 +106,7 @@ pub const Inst = struct {
106 store,106 store,
107 sub,107 sub,
108 unreach,108 unreach,
109 mul,
109 not,110 not,
110 floatcast,111 floatcast,
111 intcast,112 intcast,
...@@ -165,6 +166,7 @@ pub const Inst = struct {...@@ -165,6 +166,7 @@ pub const Inst = struct {
165166
166 .add,167 .add,
167 .sub,168 .sub,
169 .mul,
168 .cmp_lt,170 .cmp_lt,
169 .cmp_lte,171 .cmp_lte,
170 .cmp_eq,172 .cmp_eq,
src/zir.zig+2
...@@ -1649,6 +1649,7 @@ const DumpTzir = struct {...@@ -1649,6 +1649,7 @@ const DumpTzir = struct {
16491649
1650 .add,1650 .add,
1651 .sub,1651 .sub,
1652 .mul,
1652 .cmp_lt,1653 .cmp_lt,
1653 .cmp_lte,1654 .cmp_lte,
1654 .cmp_eq,1655 .cmp_eq,
...@@ -1771,6 +1772,7 @@ const DumpTzir = struct {...@@ -1771,6 +1772,7 @@ const DumpTzir = struct {
17711772
1772 .add,1773 .add,
1773 .sub,1774 .sub,
1775 .mul,
1774 .cmp_lt,1776 .cmp_lt,
1775 .cmp_lte,1777 .cmp_lte,
1776 .cmp_eq,1778 .cmp_eq,
src/zir_sema.zig+1
...@@ -2075,6 +2075,7 @@ fn zirArithmetic(mod: *Module, scope: *Scope, inst: *zir.Inst.BinOp) InnerError!...@@ -2075,6 +2075,7 @@ fn zirArithmetic(mod: *Module, scope: *Scope, inst: *zir.Inst.BinOp) InnerError!
2075 const ir_tag = switch (inst.base.tag) {2075 const ir_tag = switch (inst.base.tag) {
2076 .add => Inst.Tag.add,2076 .add => Inst.Tag.add,
2077 .sub => Inst.Tag.sub,2077 .sub => Inst.Tag.sub,
2078 .mul => Inst.Tag.mul,
2078 else => return mod.fail(scope, inst.base.src, "TODO implement arithmetic for operand '{s}''", .{@tagName(inst.base.tag)}),2079 else => return mod.fail(scope, inst.base.src, "TODO implement arithmetic for operand '{s}''", .{@tagName(inst.base.tag)}),
2079 };2080 };
20802081
test/stage2/arm.zig+34
...@@ -344,4 +344,38 @@ pub fn addCases(ctx: *TestContext) !void {...@@ -344,4 +344,38 @@ pub fn addCases(ctx: *TestContext) !void {
344 "",344 "",
345 );345 );
346 }346 }
347
348 {
349 var case = ctx.exe("integer multiplication", linux_arm);
350 // Simple u32 integer multiplication
351 case.addCompareOutput(
352 \\export fn _start() noreturn {
353 \\ assert(mul(1, 1) == 1);
354 \\ assert(mul(42, 1) == 42);
355 \\ assert(mul(1, 42) == 42);
356 \\ assert(mul(123, 42) == 5166);
357 \\ exit();
358 \\}
359 \\
360 \\fn mul(x: u32, y: u32) u32 {
361 \\ return x * y;
362 \\}
363 \\
364 \\fn assert(ok: bool) void {
365 \\ if (!ok) unreachable;
366 \\}
367 \\
368 \\fn exit() noreturn {
369 \\ asm volatile ("svc #0"
370 \\ :
371 \\ : [number] "{r7}" (1),
372 \\ [arg1] "{r0}" (0)
373 \\ : "memory"
374 \\ );
375 \\ unreachable;
376 \\}
377 ,
378 "",
379 );
380 }
347}381}