| author |  Alex Rønne Petersen <alex@alexrp.com> 2025-04-07 18:15:31+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2025-04-11 02:28:35+02:00 |
| log | 01b5e8b296e0b68f8bc90b3779e1543e3e14a8ed |
| tree | 94d711bcddeff6118f9ac8401a3c92d5f2435cf1 |
| parent | 382aa48f044ff87d50e1c185a12173be562275f2 |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std: Disable some vector-related tests for hexagon.
See:
* https://github.com/llvm/llvm-project/issues/118879
* https://github.com/llvm/llvm-project/issues/1346592 files changed, 4 insertions(+), 1 deletions(-)
lib/std/mem.zig+3-1
| ... | @@ -431,7 +431,9 @@ test zeroes { | ... | @@ -431,7 +431,9 @@ test zeroes { |
| 431 | } | 431 | } |
| 432 | try testing.expectEqual(@as(@TypeOf(b.vector_u32), @splat(0)), b.vector_u32); | 432 | try testing.expectEqual(@as(@TypeOf(b.vector_u32), @splat(0)), b.vector_u32); |
| 433 | try testing.expectEqual(@as(@TypeOf(b.vector_f32), @splat(0.0)), b.vector_f32); | 433 | try testing.expectEqual(@as(@TypeOf(b.vector_f32), @splat(0.0)), b.vector_f32); |
| 434 | try testing.expectEqual(@as(@TypeOf(b.vector_bool), @splat(false)), b.vector_bool); | 434 | if (!(builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon)) { |
| 435 | try testing.expectEqual(@as(@TypeOf(b.vector_bool), @splat(false)), b.vector_bool); | ||
| 436 | } | ||
| 435 | try testing.expectEqual(@as(?u8, null), b.optional_int); | 437 | try testing.expectEqual(@as(?u8, null), b.optional_int); |
| 436 | for (b.sentinel) |e| { | 438 | for (b.sentinel) |e| { |
| 437 | try testing.expectEqual(@as(u8, 0), e); | 439 | try testing.expectEqual(@as(u8, 0), e); |
lib/std/simd.zig+1
| ... | @@ -464,6 +464,7 @@ test "vector prefix scan" { | ... | @@ -464,6 +464,7 @@ test "vector prefix scan" { |
| 464 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; | 464 | if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; |
| 465 | if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060 | 465 | if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060 |
| 466 | if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893 | 466 | if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893 |
| 467 | if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest; | ||
| 467 | 468 | ||
| 468 | if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; | 469 | if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; |
| 469 | 470 |