| author |  Andrew Kelley <andrew@ziglang.org> 2019-07-18 11:43:39-04:00 |
| committer | Andrew Kelley <andrew@ziglang.org> 2019-07-18 11:43:39-04:00 |
| log | 04ce5376a8ba030249765779d5dcda0770445979 |
| tree | 445433b21feb3959adacfd138c81f04401464760 |
| parent | aaa4bf75d386058d6aca8c4db7244c51c27ce386 |
| signature | Commit is signed but in an unrecognized format. |
carry some upstream patches to musl to fix riscv inline asm
Upstream commits:
* 8eb49e0485fc547eead9e47200bbee6d81f391c1
* 2dcbeabd917e404a0dde0195388da401b849b9a4
* f0eb2e77b2132a88e2f00d8e06ffa7638c40b4bc
These will be in the next version of musl, so no harm carrying them
here.2 files changed, 13 insertions(+), 9 deletions(-)
lib
libc
musl
arch
riscv64
lib/libc/musl/arch/riscv64/atomic_arch.h+12-8
| ... | @@ -8,13 +8,15 @@ static inline void a_barrier() | ... | @@ -8,13 +8,15 @@ static inline void a_barrier() |
| 8 | static inline int a_cas(volatile int *p, int t, int s) | 8 | static inline int a_cas(volatile int *p, int t, int s) |
| 9 | { | 9 | { |
| 10 | int old, tmp; | 10 | int old, tmp; |
| 11 | __asm__("\n1: lr.w.aqrl %0, %2\n" | 11 | __asm__ __volatile__ ( |
| 12 | "\n1: lr.w.aqrl %0, (%2)\n" | ||
| 12 | " bne %0, %3, 1f\n" | 13 | " bne %0, %3, 1f\n" |
| 13 | " sc.w.aqrl %1, %4, %2\n" | 14 | " sc.w.aqrl %1, %4, (%2)\n" |
| 14 | " bnez %1, 1b\n" | 15 | " bnez %1, 1b\n" |
| 15 | "1:" | 16 | "1:" |
| 16 | : "=&r"(old), "+r"(tmp), "+A"(*p) | 17 | : "=&r"(old), "=r"(tmp) |
| 17 | : "r"(t), "r"(s)); | 18 | : "r"(p), "r"(t), "r"(s) |
| 19 | : "memory"); | ||
| 18 | return old; | 20 | return old; |
| 19 | } | 21 | } |
| 20 | 22 | ||
| ... | @@ -23,12 +25,14 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s) | ... | @@ -23,12 +25,14 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s) |
| 23 | { | 25 | { |
| 24 | void *old; | 26 | void *old; |
| 25 | int tmp; | 27 | int tmp; |
| 26 | __asm__("\n1: lr.d.aqrl %0, %2\n" | 28 | __asm__ __volatile__ ( |
| 29 | "\n1: lr.d.aqrl %0, (%2)\n" | ||
| 27 | " bne %0, %3, 1f\n" | 30 | " bne %0, %3, 1f\n" |
| 28 | " sc.d.aqrl %1, %4, %2\n" | 31 | " sc.d.aqrl %1, %4, (%2)\n" |
| 29 | " bnez %1, 1b\n" | 32 | " bnez %1, 1b\n" |
| 30 | "1:" | 33 | "1:" |
| 31 | : "=&r"(old), "+r"(tmp), "+A"(*(long *)p) | 34 | : "=&r"(old), "=r"(tmp) |
| 32 | : "r"(t), "r"(s)); | 35 | : "r"(p), "r"(t), "r"(s) |
| 36 | : "memory"); | ||
| 33 | return old; | 37 | return old; |
| 34 | } | 38 | } |
lib/libc/musl/arch/riscv64/syscall_arch.h+1-1
| ... | @@ -3,7 +3,7 @@ | ... | @@ -3,7 +3,7 @@ |
| 3 | 3 | ||
| 4 | #define __asm_syscall(...) \ | 4 | #define __asm_syscall(...) \ |
| 5 | __asm__ __volatile__ ("ecall\n\t" \ | 5 | __asm__ __volatile__ ("ecall\n\t" \ |
| 6 | : "+r"(a0) : __VA_ARGS__ : "memory"); \ | 6 | : "=r"(a0) : __VA_ARGS__ : "memory"); \ |
| 7 | return a0; \ | 7 | return a0; \ |
| 8 | 8 | ||
| 9 | static inline long __syscall0(long n) | 9 | static inline long __syscall0(long n) |