Commit 07114e6bc69106fb77beb879a8a2f78a4ba4b256 | zig

author	Alex Rønne Petersen <alex@alexrp.com> 2025-06-30 07:01:35+02:00
committer	Alex Rønne Petersen <alex@alexrp.com> 2025-07-01 18:16:40+02:00
log	07114e6bc69106fb77beb879a8a2f78a4ba4b256
tree	a3d4833ac74c53c13520e5508140f68ed7ee8b4f
parent	aa7b32d78189a66bb1fb62fd9735be5d15651d5b
signature	Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

4 files changed, 15 insertions(+), 6 deletions(-)

src/codegen/llvm.zig+3

...	...	@@ -1068,6 +1068,9 @@ pub const Object = struct {
1068	1068	.full => .FullPreLink,
1069	1069	},
1070	1070	.allow_fast_isel = true,
	1071	// LLVM's RISC-V backend for some reason enables the machine outliner by default even
	1072	// though it's clearly not ready and produces multiple miscompilations in our std tests.
	1073	.allow_machine_outliner = !comp.root_mod.resolved_target.result.cpu.arch.isRISCV(),
1071	1074	.asm_filename = null,
1072	1075	.bin_filename = options.bin_path,
1073	1076	.llvm_ir_filename = options.post_ir_path,

src/codegen/llvm/bindings.zig+1

...	...	@@ -92,6 +92,7 @@ pub const TargetMachine = opaque {
92	92	sancov: bool,
93	93	lto: LtoPhase,
94	94	allow_fast_isel: bool,
	95	allow_machine_outliner: bool,
95	96	asm_filename: ?[*:0]const u8,
96	97	bin_filename: ?[*:0]const u8,
97	98	llvm_ir_filename: ?[*:0]const u8,

src/zig_llvm.cpp+10-6

...	...	@@ -260,6 +260,16 @@ ZIG_EXTERN_C bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machi
260	260
261	261	TargetMachine &target_machine = reinterpret_cast<TargetMachine>(targ_machine_ref);
262	262
	263	if (options->allow_fast_isel) {
	264	target_machine.setO0WantsFastISel(true);
	265	} else {
	266	target_machine.setFastISel(false);
	267	}
	268
	269	if (!options->allow_machine_outliner) {
	270	target_machine.setMachineOutliner(false);
	271	}
	272
263	273	Module &llvm_module = *unwrap(module_ref);
264	274
265	275	// Pipeline configurations
...	...	@@ -385,12 +395,6 @@ ZIG_EXTERN_C bool ZigLLVMTargetMachineEmitToFile(LLVMTargetMachineRef targ_machi
385	395	}
386	396	}
387	397
388		if (options->allow_fast_isel) {
389		target_machine.setO0WantsFastISel(true);
390		} else {
391		target_machine.setFastISel(false);
392		}
393
394	398	// Optimization phase
395	399	module_pm.run(llvm_module, module_am);
396	400

src/zig_llvm.h+1

...	...	@@ -71,6 +71,7 @@ struct ZigLLVMEmitOptions {
71	71	bool sancov;
72	72	ZigLLVMThinOrFullLTOPhase lto;
73	73	bool allow_fast_isel;
	74	bool allow_machine_outliner;
74	75	const char *asm_filename;
75	76	const char *bin_filename;
76	77	const char *llvm_ir_filename;