Commit 093332c02ed828c6c24d6c7e113ae2804ba7e6f3 | zig

author	Koakuma <koachan@protonmail.com> 2022-05-26 20:20:48+07:00
committer	Koakuma <koachan@protonmail.com> 2022-06-06 20:34:53+07:00
log	093332c02ed828c6c24d6c7e113ae2804ba7e6f3
tree	3012fb6b684e016a778c24c280be07f5af3841e9
parent	38aa431e03b19897a7c3c8505f66f4305d8c29b2

stage2: sparc64: Implement condition code spilling

3 files changed, 90 insertions(+), 20 deletions(-)

src
- arch
  - sparc64
    CodeGen.zig
    Emit.zig
    Mir.zig

src/arch/sparc64/CodeGen.zig+68-20

 @@ -131,12 +131,18 @@ const MCValue = union(enum) {
     stack_offset: u32,
     /// The value is a pointer to one of the stack variables (payload is stack offset).
     ptr_stack_offset: u32,
-    /// The value is in the compare flags assuming an unsigned operation,
+    /// The value is in the specified CCR assuming an unsigned operation,
-    /// with this operator applied on top of it.
+    /// with the operator applied on top of it.
-    compare_flags_unsigned: math.CompareOperator,
+    compare_flags_unsigned: struct {
-    /// The value is in the compare flags assuming a signed operation,
+        cmp: math.CompareOperator,
-    /// with this operator applied on top of it.
+        ccr: Instruction.CCR,
-    compare_flags_signed: math.CompareOperator,
+    },
+    /// The value is in the specified CCR assuming an signed operation,
+    /// with the operator applied on top of it.
+    compare_flags_signed: struct {
+        cmp: math.CompareOperator,
+        ccr: Instruction.CCR,
+    },
     fn isMemory(mcv: MCValue) bool {
         return switch (mcv) {
 @@ -1086,8 +1092,8 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
             self.compare_flags_inst = inst;
             break :result switch (int_info.signedness) {
-                .signed => MCValue{ .compare_flags_signed = op },
+                .signed => MCValue{ .compare_flags_signed = .{ .cmp = op, .ccr = .xcc } },
-                .unsigned => MCValue{ .compare_flags_unsigned = op },
+                .unsigned => MCValue{ .compare_flags_unsigned = .{ .cmp = op, .ccr = .xcc } },
             };
         } else {
             return self.fail("TODO SPARCv9 cmp for ints > 64 bits", .{});
 @@ -1113,16 +1119,20 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
             .tag = .bpcc,
             .data = .{
                 .branch_predict_int = .{
-                    .ccr = .xcc,
+                    .ccr = switch (cond) {
+                        .compare_flags_signed => |cmp_op| cmp_op.ccr,
+                        .compare_flags_unsigned => |cmp_op| cmp_op.ccr,
+                        else => unreachable,
+                    },
                     .cond = switch (cond) {
                         .compare_flags_signed => |cmp_op| blk: {
                             // Here we map to the opposite condition because the jump is to the false branch.
-                            const condition = Instruction.ICondition.fromCompareOperatorSigned(cmp_op);
+                            const condition = Instruction.ICondition.fromCompareOperatorSigned(cmp_op.cmp);
                             break :blk condition.negate();
                         },
                         .compare_flags_unsigned => |cmp_op| blk: {
                             // Here we map to the opposite condition because the jump is to the false branch.
-                            const condition = Instruction.ICondition.fromCompareOperatorUnsigned(cmp_op);
+                            const condition = Instruction.ICondition.fromCompareOperatorUnsigned(cmp_op.cmp);
                             break :blk condition.negate();
                         },
                         else => unreachable,
 @@ -2290,8 +2300,47 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
     switch (mcv) {
         .dead => unreachable,
         .unreach, .none => return, // Nothing to do.
-        .compare_flags_signed => return self.fail("TODO: genSetReg for compare_flags_signed", .{}),
+        .compare_flags_signed,
-        .compare_flags_unsigned => return self.fail("TODO: genSetReg for compare_flags_unsigned", .{}),
+        .compare_flags_unsigned,
+        => {
+            const condition = switch (mcv) {
+                .compare_flags_unsigned => |op| Instruction.ICondition.fromCompareOperatorUnsigned(op.cmp),
+                .compare_flags_signed => |op| Instruction.ICondition.fromCompareOperatorSigned(op.cmp),
+                else => unreachable,
+            };
+            const ccr = switch (mcv) {
+                .compare_flags_unsigned => |op| op.ccr,
+                .compare_flags_signed => |op| op.ccr,
+                else => unreachable,
+            };
+            // TODO handle floating point CCRs
+            assert(ccr == .xcc or ccr == .icc);
+            _ = try self.addInst(.{
+                .tag = .mov,
+                .data = .{
+                    .arithmetic_2op = .{
+                        .is_imm = false,
+                        .rs1 = reg,
+                        .rs2_or_imm = .{ .rs2 = .g0 },
+                    },
+                },
+            });
+            _ = try self.addInst(.{
+                .tag = .movcc,
+                .data = .{
+                    .conditional_move = .{
+                        .ccr = ccr,
+                        .cond = .{ .icond = condition },
+                        .is_imm = true,
+                        .rd = reg,
+                        .rs2_or_imm = .{ .imm = 1 },
+                    },
+                },
+            });
+        },
         .undef => {
             if (!self.wantSafety())
                 return; // The already existing value will do just fine.
 @@ -2644,7 +2693,7 @@ fn isErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
                 } },
             });
-            return MCValue{ .compare_flags_unsigned = .gt };
+            return MCValue{ .compare_flags_unsigned = .{ .cmp = .gt, .ccr = .xcc } };
         } else {
             return self.fail("TODO isErr for errors with size > 8", .{});
         }
 @@ -2658,8 +2707,8 @@ fn isNonErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
     const is_err_result = try self.isErr(ty, operand);
     switch (is_err_result) {
         .compare_flags_unsigned => |op| {
-            assert(op == .gt);
+            assert(op.cmp == .gt);
-            return MCValue{ .compare_flags_unsigned = .lte };
+            return MCValue{ .compare_flags_unsigned = .{ .cmp = .gt, .ccr = op.ccr } };
         },
         .immediate => |imm| {
             assert(imm == 0);
 @@ -3014,14 +3063,13 @@ fn setRegOrMem(self: *Self, ty: Type, loc: MCValue, val: MCValue) !void {
 fn spillCompareFlagsIfOccupied(self: *Self) !void {
     if (self.compare_flags_inst) |inst_to_save| {
         const mcv = self.getResolvedInstValue(inst_to_save);
-        switch (mcv) {
+        const new_mcv = switch (mcv) {
             .compare_flags_signed,
             .compare_flags_unsigned,
-            => {},
+            => try self.allocRegOrMem(inst_to_save, true),
             else => unreachable, // mcv doesn't occupy the compare flags
-        }
+        };
-        const new_mcv = try self.allocRegOrMem(inst_to_save, true);
         try self.setRegOrMem(self.air.typeOfIndex(inst_to_save), new_mcv, mcv);
         log.debug("spilling {d} to mcv {any}", .{ inst_to_save, new_mcv });

src/arch/sparc64/Emit.zig+2

...	@@ -94,6 +94,8 @@ pub fn emitMir(	...	@@ -94,6 +94,8 @@ pub fn emitMir(
94		94
95	.@"or" => try emit.mirArithmetic3Op(inst),	95	.@"or" => try emit.mirArithmetic3Op(inst),
96		96
		97	.movcc => @panic("TODO implement sparc64 movcc"),
		98
97	.mulx => try emit.mirArithmetic3Op(inst),	99	.mulx => try emit.mirArithmetic3Op(inst),
98		100
99	.nop => try emit.mirNop(),	101	.nop => try emit.mirNop(),

src/arch/sparc64/Mir.zig+20

...	@@ -74,6 +74,10 @@ pub const Inst = struct {	...	@@ -74,6 +74,10 @@ pub const Inst = struct {
74	// TODO add other operations.	74	// TODO add other operations.
75	@"or",	75	@"or",
76		76
		77	/// A.35 Move Integer Register on Condition (MOVcc)
		78	/// This uses the conditional_move field.
		79	movcc,
		80
77	/// A.37 Multiply and Divide (64-bit)	81	/// A.37 Multiply and Divide (64-bit)
78	/// This uses the arithmetic_3op field.	82	/// This uses the arithmetic_3op field.
79	// TODO add other operations.	83	// TODO add other operations.
...	@@ -216,6 +220,22 @@ pub const Inst = struct {	...	@@ -216,6 +220,22 @@ pub const Inst = struct {
216	inst: Index,	220	inst: Index,
217	},	221	},
218		222
		223	/// Conditional move.
		224	/// if is_imm true then it uses the imm field of rs2_or_imm,
		225	/// otherwise it uses rs2 field.
		226	///
		227	/// Used by e.g. movcc
		228	conditional_move: struct {
		229	is_imm: bool,
		230	ccr: Instruction.CCR,
		231	cond: Instruction.Condition,
		232	rd: Register,
		233	rs2_or_imm: union {
		234	rs2: Register,
		235	imm: i11,
		236	},
		237	},
		238
219	/// No additional data	239	/// No additional data
220	///	240	///
221	/// Used by e.g. flushw	241	/// Used by e.g. flushw