| ... | @@ -17443,21 +17443,22 @@ fn genBinOp( | ... | @@ -17443,21 +17443,22 @@ fn genBinOp( |
| 17443 | .float => switch (lhs_ty.floatBits(self.target.*)) { | 17443 | .float => switch (lhs_ty.floatBits(self.target.*)) { |
| 17444 | 16 => { | 17444 | 16 => { |
| 17445 | assert(self.hasFeature(.f16c)); | 17445 | assert(self.hasFeature(.f16c)); |
| 17446 | const tmp_reg = | 17446 | const lhs_reg = if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size); |
| 17447 | (try self.register_manager.allocReg(null, abi.RegisterClass.sse)).to128(); | 17447 | |
| | 17448 | const tmp_reg = (try self.register_manager.allocReg(null, abi.RegisterClass.sse)).to128(); |
| 17448 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); | 17449 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 17449 | defer self.register_manager.unlockReg(tmp_lock); | 17450 | defer self.register_manager.unlockReg(tmp_lock); |
| 17450 | | 17451 | |
| 17451 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate( | 17452 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate( |
| 17452 | .{ .vp_w, .insr }, | 17453 | .{ .vp_w, .insr }, |
| 17453 | dst_reg, | 17454 | dst_reg, |
| 17454 | dst_reg, | 17455 | lhs_reg, |
| 17455 | try src_mcv.mem(self, .{ .size = .word }), | 17456 | try src_mcv.mem(self, .{ .size = .word }), |
| 17456 | .u(1), | 17457 | .u(1), |
| 17457 | ) else try self.asmRegisterRegisterRegister( | 17458 | ) else try self.asmRegisterRegisterRegister( |
| 17458 | .{ .vp_, .unpcklwd }, | 17459 | .{ .vp_, .unpcklwd }, |
| 17459 | dst_reg, | 17460 | dst_reg, |
| 17460 | dst_reg, | 17461 | lhs_reg, |
| 17461 | (if (src_mcv.isRegister()) | 17462 | (if (src_mcv.isRegister()) |
| 17462 | src_mcv.getReg().? | 17463 | src_mcv.getReg().? |
| 17463 | else | 17464 | else |
| ... | @@ -17885,25 +17886,24 @@ fn genBinOp( | ... | @@ -17885,25 +17886,24 @@ fn genBinOp( |
| 17885 | .float => switch (lhs_ty.childType(zcu).floatBits(self.target.*)) { | 17886 | .float => switch (lhs_ty.childType(zcu).floatBits(self.target.*)) { |
| 17886 | 16 => tag: { | 17887 | 16 => tag: { |
| 17887 | assert(self.hasFeature(.f16c)); | 17888 | assert(self.hasFeature(.f16c)); |
| | 17889 | const lhs_reg = if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size); |
| 17888 | switch (lhs_ty.vectorLen(zcu)) { | 17890 | switch (lhs_ty.vectorLen(zcu)) { |
| 17889 | 1 => { | 17891 | 1 => { |
| 17890 | const tmp_reg = (try self.register_manager.allocReg( | 17892 | const tmp_reg = |
| 17891 | null, | 17893 | (try self.register_manager.allocReg(null, abi.RegisterClass.sse)).to128(); |
| 17892 | abi.RegisterClass.sse, | | |
| 17893 | )).to128(); | | |
| 17894 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); | 17894 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 17895 | defer self.register_manager.unlockReg(tmp_lock); | 17895 | defer self.register_manager.unlockReg(tmp_lock); |
| 17896 | | 17896 | |
| 17897 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate( | 17897 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate( |
| 17898 | .{ .vp_w, .insr }, | 17898 | .{ .vp_w, .insr }, |
| 17899 | dst_reg, | 17899 | dst_reg, |
| 17900 | dst_reg, | 17900 | lhs_reg, |
| 17901 | try src_mcv.mem(self, .{ .size = .word }), | 17901 | try src_mcv.mem(self, .{ .size = .word }), |
| 17902 | .u(1), | 17902 | .u(1), |
| 17903 | ) else try self.asmRegisterRegisterRegister( | 17903 | ) else try self.asmRegisterRegisterRegister( |
| 17904 | .{ .vp_, .unpcklwd }, | 17904 | .{ .vp_, .unpcklwd }, |
| 17905 | dst_reg, | 17905 | dst_reg, |
| 17906 | dst_reg, | 17906 | lhs_reg, |
| 17907 | (if (src_mcv.isRegister()) | 17907 | (if (src_mcv.isRegister()) |
| 17908 | src_mcv.getReg().? | 17908 | src_mcv.getReg().? |
| 17909 | else | 17909 | else |
| ... | @@ -17941,15 +17941,16 @@ fn genBinOp( | ... | @@ -17941,15 +17941,16 @@ fn genBinOp( |
| 17941 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); | 17941 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 17942 | defer self.register_manager.unlockReg(tmp_lock); | 17942 | defer self.register_manager.unlockReg(tmp_lock); |
| 17943 | | 17943 | |
| 17944 | if (src_mcv.isBase()) try self.asmRegisterMemoryImmediate( | 17944 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemoryImmediate( |
| 17945 | .{ .vp_d, .insr }, | 17945 | .{ .vp_d, .insr }, |
| 17946 | dst_reg, | 17946 | dst_reg, |
| | 17947 | lhs_reg, |
| 17947 | try src_mcv.mem(self, .{ .size = .dword }), | 17948 | try src_mcv.mem(self, .{ .size = .dword }), |
| 17948 | .u(1), | 17949 | .u(1), |
| 17949 | ) else try self.asmRegisterRegisterRegister( | 17950 | ) else try self.asmRegisterRegisterRegister( |
| 17950 | .{ .v_ps, .unpckl }, | 17951 | .{ .v_ps, .unpckl }, |
| 17951 | dst_reg, | 17952 | dst_reg, |
| 17952 | dst_reg, | 17953 | lhs_reg, |
| 17953 | (if (src_mcv.isRegister()) | 17954 | (if (src_mcv.isRegister()) |
| 17954 | src_mcv.getReg().? | 17955 | src_mcv.getReg().? |
| 17955 | else | 17956 | else |
| ... | @@ -17992,7 +17993,7 @@ fn genBinOp( | ... | @@ -17992,7 +17993,7 @@ fn genBinOp( |
| 17992 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); | 17993 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 17993 | defer self.register_manager.unlockReg(tmp_lock); | 17994 | defer self.register_manager.unlockReg(tmp_lock); |
| 17994 | | 17995 | |
| 17995 | try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, dst_reg); | 17996 | try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg, lhs_reg); |
| 17996 | if (src_mcv.isBase()) try self.asmRegisterMemory( | 17997 | if (src_mcv.isBase()) try self.asmRegisterMemory( |
| 17997 | .{ .v_ps, .cvtph2 }, | 17998 | .{ .v_ps, .cvtph2 }, |
| 17998 | tmp_reg, | 17999 | tmp_reg, |
| ... | @@ -18035,7 +18036,7 @@ fn genBinOp( | ... | @@ -18035,7 +18036,7 @@ fn genBinOp( |
| 18035 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); | 18036 | const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg); |
| 18036 | defer self.register_manager.unlockReg(tmp_lock); | 18037 | defer self.register_manager.unlockReg(tmp_lock); |
| 18037 | | 18038 | |
| 18038 | try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg.to256(), dst_reg); | 18039 | try self.asmRegisterRegister(.{ .v_ps, .cvtph2 }, dst_reg.to256(), lhs_reg); |
| 18039 | if (src_mcv.isBase()) try self.asmRegisterMemory( | 18040 | if (src_mcv.isBase()) try self.asmRegisterMemory( |
| 18040 | .{ .v_ps, .cvtph2 }, | 18041 | .{ .v_ps, .cvtph2 }, |
| 18041 | tmp_reg, | 18042 | tmp_reg, |
| ... | @@ -18196,8 +18197,7 @@ fn genBinOp( | ... | @@ -18196,8 +18197,7 @@ fn genBinOp( |
| 18196 | | 18197 | |
| 18197 | switch (mir_tag[1]) { | 18198 | switch (mir_tag[1]) { |
| 18198 | else => if (self.hasFeature(.avx)) { | 18199 | else => if (self.hasFeature(.avx)) { |
| 18199 | const lhs_reg = | 18200 | const lhs_reg = if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size); |
| 18200 | if (copied_to_dst) dst_reg else registerAlias(lhs_mcv.getReg().?, abi_size); | | |
| 18201 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemory( | 18201 | if (src_mcv.isBase()) try self.asmRegisterRegisterMemory( |
| 18202 | mir_tag, | 18202 | mir_tag, |
| 18203 | dst_reg, | 18203 | dst_reg, |
Jacob Young <jacobly@ziglang.org> 2025-01-03 05:44:03-05:00