authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-12-05 17:48:54+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-12-05 22:35:07+01:00
log12e34e70377882363dbedf2a7afdc8737a7435c5
treec3e01b1a26a83062425af5fabaef8c0fc92092cf
parent97827d6d38ecd078fbbcff3d71a7e104341695cd

dwarf: pull out debug line program internals into DeclState helpers

7 files changed, 56 insertions(+), 97 deletions(-)

src/arch/aarch64/Emit.zig+3-17
......@@ -10,8 +10,6 @@ const link = @import("../../link.zig");
1010const Module = @import("../../Module.zig");
1111const ErrorMsg = Module.ErrorMsg;
1212const assert = std.debug.assert;
13const DW = std.dwarf;
14const leb128 = std.leb;
1513const Instruction = bits.Instruction;
1614const Register = bits.Register;
1715const log = std.log.scoped(.aarch64_emit);
......@@ -440,19 +438,7 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
440438 const delta_pc: usize = self.code.items.len - self.prev_di_pc;
441439 switch (self.debug_output) {
442440 .dwarf => |dw| {
443 // TODO Look into using the DWARF special opcodes to compress this data.
444 // It lets you emit single-byte opcodes that add different numbers to
445 // both the PC and the line number at the same time.
446 const dbg_line = &dw.dbg_line;
447 try dbg_line.ensureUnusedCapacity(11);
448 dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
449 leb128.writeULEB128(dbg_line.writer(), delta_pc) catch unreachable;
450 if (delta_line != 0) {
451 dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
452 leb128.writeILEB128(dbg_line.writer(), delta_line) catch unreachable;
453 }
454 dbg_line.appendAssumeCapacity(DW.LNS.copy);
455 self.prev_di_pc = self.code.items.len;
441 try dw.advancePCAndLine(delta_line, delta_pc);
456442 self.prev_di_line = line;
457443 self.prev_di_column = column;
458444 self.prev_di_pc = self.code.items.len;
......@@ -652,7 +638,7 @@ fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
652638fn mirDebugPrologueEnd(self: *Emit) !void {
653639 switch (self.debug_output) {
654640 .dwarf => |dw| {
655 try dw.dbg_line.append(DW.LNS.set_prologue_end);
641 try dw.setPrologueEnd();
656642 try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
657643 },
658644 .plan9 => {},
......@@ -663,7 +649,7 @@ fn mirDebugPrologueEnd(self: *Emit) !void {
663649fn mirDebugEpilogueBegin(self: *Emit) !void {
664650 switch (self.debug_output) {
665651 .dwarf => |dw| {
666 try dw.dbg_line.append(DW.LNS.set_epilogue_begin);
652 try dw.setEpilogueBegin();
667653 try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
668654 },
669655 .plan9 => {},
src/arch/arm/Emit.zig+3-17
......@@ -13,8 +13,6 @@ const Type = @import("../../type.zig").Type;
1313const ErrorMsg = Module.ErrorMsg;
1414const Target = std.Target;
1515const assert = std.debug.assert;
16const DW = std.dwarf;
17const leb128 = std.leb;
1816const Instruction = bits.Instruction;
1917const Register = bits.Register;
2018const log = std.log.scoped(.aarch64_emit);
......@@ -356,19 +354,7 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
356354 const delta_pc: usize = self.code.items.len - self.prev_di_pc;
357355 switch (self.debug_output) {
358356 .dwarf => |dw| {
359 // TODO Look into using the DWARF special opcodes to compress this data.
360 // It lets you emit single-byte opcodes that add different numbers to
361 // both the PC and the line number at the same time.
362 const dbg_line = &dw.dbg_line;
363 try dbg_line.ensureUnusedCapacity(11);
364 dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
365 leb128.writeULEB128(dbg_line.writer(), delta_pc) catch unreachable;
366 if (delta_line != 0) {
367 dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
368 leb128.writeILEB128(dbg_line.writer(), delta_line) catch unreachable;
369 }
370 dbg_line.appendAssumeCapacity(DW.LNS.copy);
371 self.prev_di_pc = self.code.items.len;
357 try dw.advancePCAndLine(delta_line, delta_pc);
372358 self.prev_di_line = line;
373359 self.prev_di_column = column;
374360 self.prev_di_pc = self.code.items.len;
......@@ -543,7 +529,7 @@ fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
543529fn mirDebugPrologueEnd(emit: *Emit) !void {
544530 switch (emit.debug_output) {
545531 .dwarf => |dw| {
546 try dw.dbg_line.append(DW.LNS.set_prologue_end);
532 try dw.setPrologueEnd();
547533 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
548534 },
549535 .plan9 => {},
......@@ -554,7 +540,7 @@ fn mirDebugPrologueEnd(emit: *Emit) !void {
554540fn mirDebugEpilogueBegin(emit: *Emit) !void {
555541 switch (emit.debug_output) {
556542 .dwarf => |dw| {
557 try dw.dbg_line.append(DW.LNS.set_epilogue_begin);
543 try dw.setEpilogueBegin();
558544 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
559545 },
560546 .plan9 => {},
src/arch/riscv64/Emit.zig+3-17
......@@ -10,8 +10,6 @@ const link = @import("../../link.zig");
1010const Module = @import("../../Module.zig");
1111const ErrorMsg = Module.ErrorMsg;
1212const assert = std.debug.assert;
13const DW = std.dwarf;
14const leb128 = std.leb;
1513const Instruction = bits.Instruction;
1614const Register = bits.Register;
1715const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
......@@ -90,19 +88,7 @@ fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
9088 const delta_pc: usize = self.code.items.len - self.prev_di_pc;
9189 switch (self.debug_output) {
9290 .dwarf => |dw| {
93 // TODO Look into using the DWARF special opcodes to compress this data.
94 // It lets you emit single-byte opcodes that add different numbers to
95 // both the PC and the line number at the same time.
96 const dbg_line = &dw.dbg_line;
97 try dbg_line.ensureUnusedCapacity(11);
98 dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
99 leb128.writeULEB128(dbg_line.writer(), delta_pc) catch unreachable;
100 if (delta_line != 0) {
101 dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
102 leb128.writeILEB128(dbg_line.writer(), delta_line) catch unreachable;
103 }
104 dbg_line.appendAssumeCapacity(DW.LNS.copy);
105 self.prev_di_pc = self.code.items.len;
91 try dw.advancePCAndLine(delta_line, delta_pc);
10692 self.prev_di_line = line;
10793 self.prev_di_column = column;
10894 self.prev_di_pc = self.code.items.len;
......@@ -184,7 +170,7 @@ fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
184170fn mirDebugPrologueEnd(self: *Emit) !void {
185171 switch (self.debug_output) {
186172 .dwarf => |dw| {
187 try dw.dbg_line.append(DW.LNS.set_prologue_end);
173 try dw.setPrologueEnd();
188174 try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
189175 },
190176 .plan9 => {},
......@@ -195,7 +181,7 @@ fn mirDebugPrologueEnd(self: *Emit) !void {
195181fn mirDebugEpilogueBegin(self: *Emit) !void {
196182 switch (self.debug_output) {
197183 .dwarf => |dw| {
198 try dw.dbg_line.append(DW.LNS.set_epilogue_begin);
184 try dw.setEpilogueBegin();
199185 try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
200186 },
201187 .plan9 => {},
src/arch/sparc64/Emit.zig+3-16
......@@ -10,8 +10,6 @@ const ErrorMsg = Module.ErrorMsg;
1010const Liveness = @import("../../Liveness.zig");
1111const log = std.log.scoped(.sparcv9_emit);
1212const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
13const DW = std.dwarf;
14const leb128 = std.leb;
1513
1614const Emit = @This();
1715const Mir = @import("Mir.zig");
......@@ -168,7 +166,7 @@ fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
168166fn mirDebugPrologueEnd(emit: *Emit) !void {
169167 switch (emit.debug_output) {
170168 .dwarf => |dbg_out| {
171 try dbg_out.dbg_line.append(DW.LNS.set_prologue_end);
169 try dbg_out.setPrologueEnd();
172170 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
173171 },
174172 .plan9 => {},
......@@ -179,7 +177,7 @@ fn mirDebugPrologueEnd(emit: *Emit) !void {
179177fn mirDebugEpilogueBegin(emit: *Emit) !void {
180178 switch (emit.debug_output) {
181179 .dwarf => |dbg_out| {
182 try dbg_out.dbg_line.append(DW.LNS.set_epilogue_begin);
180 try dbg_out.setEpilogueBegin();
183181 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
184182 },
185183 .plan9 => {},
......@@ -468,18 +466,7 @@ fn dbgAdvancePCAndLine(emit: *Emit, line: u32, column: u32) !void {
468466 const delta_pc: usize = emit.code.items.len - emit.prev_di_pc;
469467 switch (emit.debug_output) {
470468 .dwarf => |dbg_out| {
471 // TODO Look into using the DWARF special opcodes to compress this data.
472 // It lets you emit single-byte opcodes that add different numbers to
473 // both the PC and the line number at the same time.
474 try dbg_out.dbg_line.ensureUnusedCapacity(11);
475 dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
476 leb128.writeULEB128(dbg_out.dbg_line.writer(), delta_pc) catch unreachable;
477 if (delta_line != 0) {
478 dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
479 leb128.writeILEB128(dbg_out.dbg_line.writer(), delta_line) catch unreachable;
480 }
481 dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.copy);
482 emit.prev_di_pc = emit.code.items.len;
469 try dbg_out.advancePCAndLine(delta_line, delta_pc);
483470 emit.prev_di_line = line;
484471 emit.prev_di_column = column;
485472 emit.prev_di_pc = emit.code.items.len;
src/arch/wasm/Emit.zig+6-12
......@@ -444,18 +444,12 @@ fn emitDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
444444fn dbgAdvancePCAndLine(emit: *Emit, line: u32, column: u32) !void {
445445 if (emit.dbg_output != .dwarf) return;
446446
447 const dbg_line = &emit.dbg_output.dwarf.dbg_line;
448 try dbg_line.ensureUnusedCapacity(11);
449 dbg_line.appendAssumeCapacity(std.dwarf.LNS.advance_pc);
447 const delta_line = @intCast(i32, line) - @intCast(i32, emit.prev_di_line);
448 const delta_pc = emit.offset() - emit.prev_di_offset;
450449 // TODO: This must emit a relocation to calculate the offset relative
451450 // to the code section start.
452 leb128.writeULEB128(dbg_line.writer(), emit.offset() - emit.prev_di_offset) catch unreachable;
453 const delta_line = @intCast(i32, line) - @intCast(i32, emit.prev_di_line);
454 if (delta_line != 0) {
455 dbg_line.appendAssumeCapacity(std.dwarf.LNS.advance_line);
456 leb128.writeILEB128(dbg_line.writer(), delta_line) catch unreachable;
457 }
458 dbg_line.appendAssumeCapacity(std.dwarf.LNS.copy);
451 try emit.dbg_output.dwarf.advancePCAndLine(delta_line, delta_pc);
452
459453 emit.prev_di_line = line;
460454 emit.prev_di_column = column;
461455 emit.prev_di_offset = emit.offset();
......@@ -464,13 +458,13 @@ fn dbgAdvancePCAndLine(emit: *Emit, line: u32, column: u32) !void {
464458fn emitDbgPrologueEnd(emit: *Emit) !void {
465459 if (emit.dbg_output != .dwarf) return;
466460
467 try emit.dbg_output.dwarf.dbg_line.append(std.dwarf.LNS.set_prologue_end);
461 try emit.dbg_output.dwarf.setPrologueEnd();
468462 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
469463}
470464
471465fn emitDbgEpilogueBegin(emit: *Emit) !void {
472466 if (emit.dbg_output != .dwarf) return;
473467
474 try emit.dbg_output.dwarf.dbg_line.append(std.dwarf.LNS.set_epilogue_begin);
468 try emit.dbg_output.dwarf.setEpilogueBegin();
475469 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
476470}
src/arch/x86_64/Emit.zig+11-18
......@@ -7,7 +7,6 @@ const std = @import("std");
77const assert = std.debug.assert;
88const bits = @import("bits.zig");
99const abi = @import("abi.zig");
10const leb128 = std.leb;
1110const link = @import("../../link.zig");
1211const log = std.log.scoped(.codegen);
1312const math = std.math;
......@@ -18,7 +17,6 @@ const Air = @import("../../Air.zig");
1817const Allocator = mem.Allocator;
1918const CodeGen = @import("CodeGen.zig");
2019const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
21const DW = std.dwarf;
2220const Encoder = bits.Encoder;
2321const ErrorMsg = Module.ErrorMsg;
2422const MCValue = @import("CodeGen.zig").MCValue;
......@@ -1184,18 +1182,7 @@ fn dbgAdvancePCAndLine(emit: *Emit, line: u32, column: u32) InnerError!void {
11841182 log.debug(" (advance pc={d} and line={d})", .{ delta_line, delta_pc });
11851183 switch (emit.debug_output) {
11861184 .dwarf => |dw| {
1187 // TODO Look into using the DWARF special opcodes to compress this data.
1188 // It lets you emit single-byte opcodes that add different numbers to
1189 // both the PC and the line number at the same time.
1190 const dbg_line = &dw.dbg_line;
1191 try dbg_line.ensureUnusedCapacity(11);
1192 dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
1193 leb128.writeULEB128(dbg_line.writer(), delta_pc) catch unreachable;
1194 if (delta_line != 0) {
1195 dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
1196 leb128.writeILEB128(dbg_line.writer(), delta_line) catch unreachable;
1197 }
1198 dbg_line.appendAssumeCapacity(DW.LNS.copy);
1185 try dw.advancePCAndLine(delta_line, delta_pc);
11991186 emit.prev_di_line = line;
12001187 emit.prev_di_column = column;
12011188 emit.prev_di_pc = emit.code.items.len;
......@@ -1244,8 +1231,11 @@ fn mirDbgPrologueEnd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
12441231 assert(tag == .dbg_prologue_end);
12451232 switch (emit.debug_output) {
12461233 .dwarf => |dw| {
1247 try dw.dbg_line.append(DW.LNS.set_prologue_end);
1248 log.debug("mirDbgPrologueEnd (line={d}, col={d})", .{ emit.prev_di_line, emit.prev_di_column });
1234 try dw.setPrologueEnd();
1235 log.debug("mirDbgPrologueEnd (line={d}, col={d})", .{
1236 emit.prev_di_line,
1237 emit.prev_di_column,
1238 });
12491239 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
12501240 },
12511241 .plan9 => {},
......@@ -1258,8 +1248,11 @@ fn mirDbgEpilogueBegin(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
12581248 assert(tag == .dbg_epilogue_begin);
12591249 switch (emit.debug_output) {
12601250 .dwarf => |dw| {
1261 try dw.dbg_line.append(DW.LNS.set_epilogue_begin);
1262 log.debug("mirDbgEpilogueBegin (line={d}, col={d})", .{ emit.prev_di_line, emit.prev_di_column });
1251 try dw.setEpilogueBegin();
1252 log.debug("mirDbgEpilogueBegin (line={d}, col={d})", .{
1253 emit.prev_di_line,
1254 emit.prev_di_column,
1255 });
12631256 try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
12641257 },
12651258 .plan9 => {},
src/link/Dwarf.zig+27
......@@ -778,6 +778,33 @@ pub const DeclState = struct {
778778 try self.addTypeRelocGlobal(atom, child_ty, @intCast(u32, index));
779779 dbg_info.appendSliceAssumeCapacity(name_with_null); // DW.AT.name, DW.FORM.string
780780 }
781
782 pub fn advancePCAndLine(
783 self: *DeclState,
784 delta_line: i32,
785 delta_pc: usize,
786 ) error{OutOfMemory}!void {
787 // TODO Look into using the DWARF special opcodes to compress this data.
788 // It lets you emit single-byte opcodes that add different numbers to
789 // both the PC and the line number at the same time.
790 const dbg_line = &self.dbg_line;
791 try dbg_line.ensureUnusedCapacity(11);
792 dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
793 leb128.writeULEB128(dbg_line.writer(), delta_pc) catch unreachable;
794 if (delta_line != 0) {
795 dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
796 leb128.writeILEB128(dbg_line.writer(), delta_line) catch unreachable;
797 }
798 dbg_line.appendAssumeCapacity(DW.LNS.copy);
799 }
800
801 pub fn setPrologueEnd(self: *DeclState) error{OutOfMemory}!void {
802 try self.dbg_line.append(DW.LNS.set_prologue_end);
803 }
804
805 pub fn setEpilogueBegin(self: *DeclState) error{OutOfMemory}!void {
806 try self.dbg_line.append(DW.LNS.set_epilogue_begin);
807 }
781808};
782809
783810pub const AbbrevEntry = struct {