authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2023-11-22 14:27:49-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2023-11-22 14:27:49-07:00
log1fa2e911d923d9f843f1f179db28ab815d4a105d
tree7184e51747cbfeb6d42b5eb1a849423a34f9a1ec
parente4977f3e89fcc164a4d02cd38eb066cfe1a1124f

std.atomic: remove some APIs

* remove `std.atomic.Ordering` - it is provided by the language with `std.builtin.AtomicOrder`. * remove `std.atomic.fence` - it is provided by the language with `@fence`. * remove `std.atomic.compilerFence` - if this is desired, it should be a language feature, not a standard library function with inline asm.

2 files changed, 43 insertions(+), 71 deletions(-)

lib/std/atomic.zig+4-32
......@@ -1,8 +1,6 @@
11const std = @import("std.zig");
22const builtin = @import("builtin");
33
4pub const Ordering = std.builtin.AtomicOrder;
5
64pub const Stack = @import("atomic/stack.zig").Stack;
75pub const Queue = @import("atomic/queue.zig").Queue;
86pub const Atomic = @import("atomic/Atomic.zig").Atomic;
......@@ -13,31 +11,6 @@ test {
1311 _ = @import("atomic/Atomic.zig");
1412}
1513
16pub inline fn fence(comptime ordering: Ordering) void {
17 switch (ordering) {
18 .Acquire, .Release, .AcqRel, .SeqCst => {
19 @fence(ordering);
20 },
21 else => {
22 @compileLog(ordering, " only applies to a given memory location");
23 },
24 }
25}
26
27pub inline fn compilerFence(comptime ordering: Ordering) void {
28 switch (ordering) {
29 .Acquire, .Release, .AcqRel, .SeqCst => asm volatile ("" ::: "memory"),
30 else => @compileLog(ordering, " only applies to a given memory location"),
31 }
32}
33
34test "fence/compilerFence" {
35 inline for (.{ .Acquire, .Release, .AcqRel, .SeqCst }) |ordering| {
36 compilerFence(ordering);
37 fence(ordering);
38 }
39}
40
4114/// Signals to the processor that the caller is inside a busy-wait spin-loop.
4215pub inline fn spinLoopHint() void {
4316 switch (builtin.target.cpu.arch) {
......@@ -74,9 +47,8 @@ pub inline fn spinLoopHint() void {
7447 }
7548}
7649
77test "spinLoopHint" {
78 var i: usize = 10;
79 while (i > 0) : (i -= 1) {
50test spinLoopHint {
51 for (0..10) |_| {
8052 spinLoopHint();
8153 }
8254}
......@@ -85,8 +57,8 @@ test "spinLoopHint" {
8557/// Add this much padding or align to this boundary to avoid atomically-updated
8658/// memory from forcing cache invalidations on near, but non-atomic, memory.
8759///
88// https://en.wikipedia.org/wiki/False_sharing
89// https://github.com/golang/go/search?q=CacheLinePadSize
60/// https://en.wikipedia.org/wiki/False_sharing
61/// https://github.com/golang/go/search?q=CacheLinePadSize
9062pub const cache_line = switch (builtin.cpu.arch) {
9163 // x86_64: Starting from Intel's Sandy Bridge, the spatial prefetcher pulls in pairs of 64-byte cache lines at a time.
9264 // - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
lib/std/atomic/Atomic.zig+39-39
......@@ -2,7 +2,7 @@ const std = @import("../std.zig");
22const builtin = @import("builtin");
33
44const testing = std.testing;
5const Ordering = std.atomic.Ordering;
5const AtomicOrder = std.builtin.AtomicOrder;
66
77pub fn Atomic(comptime T: type) type {
88 return extern struct {
......@@ -38,7 +38,7 @@ pub fn Atomic(comptime T: type) type {
3838 /// }
3939 /// };
4040 /// ```
41 pub inline fn fence(self: *Self, comptime ordering: Ordering) void {
41 pub inline fn fence(self: *Self, comptime ordering: AtomicOrder) void {
4242 // LLVM's ThreadSanitizer doesn't support the normal fences so we specialize for it.
4343 if (builtin.sanitize_thread) {
4444 const tsan = struct {
......@@ -58,7 +58,14 @@ pub fn Atomic(comptime T: type) type {
5858 };
5959 }
6060
61 return std.atomic.fence(ordering);
61 return @fence(ordering);
62 }
63
64 test fence {
65 inline for (.{ .Acquire, .Release, .AcqRel, .SeqCst }) |ordering| {
66 var x = Atomic(usize).init(0);
67 x.fence(ordering);
68 }
6269 }
6370
6471 /// Non-atomically load from the atomic value without synchronization.
......@@ -73,23 +80,23 @@ pub fn Atomic(comptime T: type) type {
7380 self.value = value;
7481 }
7582
76 pub inline fn load(self: *const Self, comptime ordering: Ordering) T {
83 pub inline fn load(self: *const Self, comptime ordering: AtomicOrder) T {
7784 return switch (ordering) {
78 .AcqRel => @compileError(@tagName(ordering) ++ " implies " ++ @tagName(Ordering.Release) ++ " which is only allowed on atomic stores"),
85 .AcqRel => @compileError(@tagName(ordering) ++ " implies " ++ @tagName(AtomicOrder.Release) ++ " which is only allowed on atomic stores"),
7986 .Release => @compileError(@tagName(ordering) ++ " is only allowed on atomic stores"),
8087 else => @atomicLoad(T, &self.value, ordering),
8188 };
8289 }
8390
84 pub inline fn store(self: *Self, value: T, comptime ordering: Ordering) void {
91 pub inline fn store(self: *Self, value: T, comptime ordering: AtomicOrder) void {
8592 switch (ordering) {
86 .AcqRel => @compileError(@tagName(ordering) ++ " implies " ++ @tagName(Ordering.Acquire) ++ " which is only allowed on atomic loads"),
93 .AcqRel => @compileError(@tagName(ordering) ++ " implies " ++ @tagName(AtomicOrder.Acquire) ++ " which is only allowed on atomic loads"),
8794 .Acquire => @compileError(@tagName(ordering) ++ " is only allowed on atomic loads"),
8895 else => @atomicStore(T, &self.value, value, ordering),
8996 }
9097 }
9198
92 pub inline fn swap(self: *Self, value: T, comptime ordering: Ordering) T {
99 pub inline fn swap(self: *Self, value: T, comptime ordering: AtomicOrder) T {
93100 return self.rmw(.Xchg, value, ordering);
94101 }
95102
......@@ -97,8 +104,8 @@ pub fn Atomic(comptime T: type) type {
97104 self: *Self,
98105 compare: T,
99106 exchange: T,
100 comptime success: Ordering,
101 comptime failure: Ordering,
107 comptime success: AtomicOrder,
108 comptime failure: AtomicOrder,
102109 ) ?T {
103110 return self.cmpxchg(true, compare, exchange, success, failure);
104111 }
......@@ -107,8 +114,8 @@ pub fn Atomic(comptime T: type) type {
107114 self: *Self,
108115 compare: T,
109116 exchange: T,
110 comptime success: Ordering,
111 comptime failure: Ordering,
117 comptime success: AtomicOrder,
118 comptime failure: AtomicOrder,
112119 ) ?T {
113120 return self.cmpxchg(false, compare, exchange, success, failure);
114121 }
......@@ -118,16 +125,16 @@ pub fn Atomic(comptime T: type) type {
118125 comptime is_strong: bool,
119126 compare: T,
120127 exchange: T,
121 comptime success: Ordering,
122 comptime failure: Ordering,
128 comptime success: AtomicOrder,
129 comptime failure: AtomicOrder,
123130 ) ?T {
124131 if (success == .Unordered or failure == .Unordered) {
125 @compileError(@tagName(Ordering.Unordered) ++ " is only allowed on atomic loads and stores");
132 @compileError(@tagName(AtomicOrder.Unordered) ++ " is only allowed on atomic loads and stores");
126133 }
127134
128135 const success_is_stronger = switch (failure) {
129136 .SeqCst => success == .SeqCst,
130 .AcqRel => @compileError(@tagName(failure) ++ " implies " ++ @tagName(Ordering.Release) ++ " which is only allowed on success"),
137 .AcqRel => @compileError(@tagName(failure) ++ " implies " ++ @tagName(AtomicOrder.Release) ++ " which is only allowed on success"),
131138 .Acquire => success == .SeqCst or success == .AcqRel or success == .Acquire,
132139 .Release => @compileError(@tagName(failure) ++ " is only allowed on success"),
133140 .Monotonic => true,
......@@ -148,40 +155,40 @@ pub fn Atomic(comptime T: type) type {
148155 self: *Self,
149156 comptime op: std.builtin.AtomicRmwOp,
150157 value: T,
151 comptime ordering: Ordering,
158 comptime ordering: AtomicOrder,
152159 ) T {
153160 return @atomicRmw(T, &self.value, op, value, ordering);
154161 }
155162
156 pub inline fn fetchAdd(self: *Self, value: T, comptime ordering: Ordering) T {
163 pub inline fn fetchAdd(self: *Self, value: T, comptime ordering: AtomicOrder) T {
157164 return self.rmw(.Add, value, ordering);
158165 }
159166
160 pub inline fn fetchSub(self: *Self, value: T, comptime ordering: Ordering) T {
167 pub inline fn fetchSub(self: *Self, value: T, comptime ordering: AtomicOrder) T {
161168 return self.rmw(.Sub, value, ordering);
162169 }
163170
164 pub inline fn fetchMin(self: *Self, value: T, comptime ordering: Ordering) T {
171 pub inline fn fetchMin(self: *Self, value: T, comptime ordering: AtomicOrder) T {
165172 return self.rmw(.Min, value, ordering);
166173 }
167174
168 pub inline fn fetchMax(self: *Self, value: T, comptime ordering: Ordering) T {
175 pub inline fn fetchMax(self: *Self, value: T, comptime ordering: AtomicOrder) T {
169176 return self.rmw(.Max, value, ordering);
170177 }
171178
172 pub inline fn fetchAnd(self: *Self, value: T, comptime ordering: Ordering) T {
179 pub inline fn fetchAnd(self: *Self, value: T, comptime ordering: AtomicOrder) T {
173180 return self.rmw(.And, value, ordering);
174181 }
175182
176 pub inline fn fetchNand(self: *Self, value: T, comptime ordering: Ordering) T {
183 pub inline fn fetchNand(self: *Self, value: T, comptime ordering: AtomicOrder) T {
177184 return self.rmw(.Nand, value, ordering);
178185 }
179186
180 pub inline fn fetchOr(self: *Self, value: T, comptime ordering: Ordering) T {
187 pub inline fn fetchOr(self: *Self, value: T, comptime ordering: AtomicOrder) T {
181188 return self.rmw(.Or, value, ordering);
182189 }
183190
184 pub inline fn fetchXor(self: *Self, value: T, comptime ordering: Ordering) T {
191 pub inline fn fetchXor(self: *Self, value: T, comptime ordering: AtomicOrder) T {
185192 return self.rmw(.Xor, value, ordering);
186193 }
187194
......@@ -192,19 +199,19 @@ pub fn Atomic(comptime T: type) type {
192199 Toggle,
193200 };
194201
195 pub inline fn bitSet(self: *Self, bit: Bit, comptime ordering: Ordering) u1 {
202 pub inline fn bitSet(self: *Self, bit: Bit, comptime ordering: AtomicOrder) u1 {
196203 return bitRmw(self, .Set, bit, ordering);
197204 }
198205
199 pub inline fn bitReset(self: *Self, bit: Bit, comptime ordering: Ordering) u1 {
206 pub inline fn bitReset(self: *Self, bit: Bit, comptime ordering: AtomicOrder) u1 {
200207 return bitRmw(self, .Reset, bit, ordering);
201208 }
202209
203 pub inline fn bitToggle(self: *Self, bit: Bit, comptime ordering: Ordering) u1 {
210 pub inline fn bitToggle(self: *Self, bit: Bit, comptime ordering: AtomicOrder) u1 {
204211 return bitRmw(self, .Toggle, bit, ordering);
205212 }
206213
207 inline fn bitRmw(self: *Self, comptime op: BitRmwOp, bit: Bit, comptime ordering: Ordering) u1 {
214 inline fn bitRmw(self: *Self, comptime op: BitRmwOp, bit: Bit, comptime ordering: AtomicOrder) u1 {
208215 // x86 supports dedicated bitwise instructions
209216 if (comptime builtin.target.cpu.arch.isX86() and @sizeOf(T) >= 2 and @sizeOf(T) <= 8) {
210217 // TODO: this causes std lib test failures when enabled
......@@ -223,7 +230,7 @@ pub fn Atomic(comptime T: type) type {
223230 return @intFromBool(value & mask != 0);
224231 }
225232
226 inline fn x86BitRmw(self: *Self, comptime op: BitRmwOp, bit: Bit, comptime ordering: Ordering) u1 {
233 inline fn x86BitRmw(self: *Self, comptime op: BitRmwOp, bit: Bit, comptime ordering: AtomicOrder) u1 {
227234 const old_bit: u8 = switch (@sizeOf(T)) {
228235 2 => switch (op) {
229236 .Set => asm volatile ("lock btsw %[bit], %[ptr]"
......@@ -305,13 +312,6 @@ pub fn Atomic(comptime T: type) type {
305312 };
306313}
307314
308test "Atomic.fence" {
309 inline for (.{ .Acquire, .Release, .AcqRel, .SeqCst }) |ordering| {
310 var x = Atomic(usize).init(0);
311 x.fence(ordering);
312 }
313}
314
315315fn atomicIntTypes() []const type {
316316 comptime var bytes = 1;
317317 comptime var types: []const type = &[_]type{};
......@@ -357,7 +357,7 @@ test "Atomic.store" {
357357 }
358358}
359359
360const atomic_rmw_orderings = [_]Ordering{
360const atomic_rmw_orderings = [_]AtomicOrder{
361361 .Monotonic,
362362 .Acquire,
363363 .Release,
......@@ -389,7 +389,7 @@ test "Atomic.swap" {
389389 }
390390}
391391
392const atomic_cmpxchg_orderings = [_][2]Ordering{
392const atomic_cmpxchg_orderings = [_][2]AtomicOrder{
393393 .{ .Monotonic, .Monotonic },
394394 .{ .Acquire, .Monotonic },
395395 .{ .Acquire, .Acquire },