| author |  Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-09-17 12:26:21+02:00 |
| committer | Joachim Schmidt <joachim.schmidt557@outlook.com> 2022-09-20 17:14:27+02:00 |
| log | 258b058eecb54e160ac60e72b0354f99f3202bdf |
| tree | aee5b0c2b12871e9047d0983c1926afe29d6ac5a |
| parent | 4521456f66122c6348ef6980ae1eecdb94f4f110 |
| signature | Commit is signed but in an unrecognized format. |
stage2 ARM: make sub_sp_scratch MIR instruction use r4
r0 is used for argument passing, so this register is not available as
a scratch register upon function entry.3 files changed, 12 insertions(+), 43 deletions(-)
src
arch
src/arch/arm/CodeGen.zig+6-37
| ... | ... | @@ -169,40 +169,6 @@ const MCValue = union(enum) { |
| 169 | 169 | cpsr_flags: Condition, |
| 170 | 170 | /// The value is a function argument passed via the stack. |
| 171 | 171 | stack_argument_offset: u32, |
| 172 | ||
| 173 | fn isMemory(mcv: MCValue) bool { | |
| 174 | return switch (mcv) { | |
| 175 | .memory, .stack_offset, .stack_argument_offset => true, | |
| 176 | else => false, | |
| 177 | }; | |
| 178 | } | |
| 179 | ||
| 180 | fn isImmediate(mcv: MCValue) bool { | |
| 181 | return switch (mcv) { | |
| 182 | .immediate => true, | |
| 183 | else => false, | |
| 184 | }; | |
| 185 | } | |
| 186 | ||
| 187 | fn isMutable(mcv: MCValue) bool { | |
| 188 | return switch (mcv) { | |
| 189 | .none => unreachable, | |
| 190 | .unreach => unreachable, | |
| 191 | .dead => unreachable, | |
| 192 | ||
| 193 | .immediate, | |
| 194 | .memory, | |
| 195 | .cpsr_flags, | |
| 196 | .ptr_stack_offset, | |
| 197 | .undef, | |
| 198 | .stack_argument_offset, | |
| 199 | => false, | |
| 200 | ||
| 201 | .register, | |
| 202 | .stack_offset, | |
| 203 | => true, | |
| 204 | }; | |
| 205 | } | |
| 206 | 172 | }; |
| 207 | 173 | |
| 208 | 174 | const Branch = struct { |
| ... | ... | @@ -447,6 +413,11 @@ fn gen(self: *Self) !void { |
| 447 | 413 | // sub sp, sp, #reloc |
| 448 | 414 | const sub_reloc = try self.addNop(); |
| 449 | 415 | |
| 416 | // The sub_sp_scratch_r4 instruction may use r4, so we mark r4 | |
| 417 | // as allocated by this function. | |
| 418 | const index = RegisterManager.indexOfRegIntoTracked(.r4).?; | |
| 419 | self.register_manager.allocated_registers.set(index); | |
| 420 | ||
| 450 | 421 | if (self.ret_mcv == .stack_offset) { |
| 451 | 422 | // The address of where to store the return value is in |
| 452 | 423 | // r0. As this register might get overwritten along the |
| ... | ... | @@ -477,7 +448,6 @@ fn gen(self: *Self) !void { |
| 477 | 448 | self.saved_regs_stack_space += 4; |
| 478 | 449 | } |
| 479 | 450 | } |
| 480 | ||
| 481 | 451 | self.mir_instructions.set(push_reloc, .{ |
| 482 | 452 | .tag = .push, |
| 483 | 453 | .data = .{ .register_list = saved_regs }, |
| ... | ... | @@ -489,7 +459,7 @@ fn gen(self: *Self) !void { |
| 489 | 459 | const stack_size = aligned_total_stack_end - self.saved_regs_stack_space; |
| 490 | 460 | self.max_end_stack = stack_size; |
| 491 | 461 | self.mir_instructions.set(sub_reloc, .{ |
| 492 | .tag = .sub_sp_scratch_r0, | |
| 462 | .tag = .sub_sp_scratch_r4, | |
| 493 | 463 | .data = .{ .imm32 = stack_size }, |
| 494 | 464 | }); |
| 495 | 465 | |
| ... | ... | @@ -4042,7 +4012,6 @@ fn genArgDbgInfo(self: *Self, inst: Air.Inst.Index, arg_index: u32) error{OutOfM |
| 4042 | 4012 | => { |
| 4043 | 4013 | switch (self.debug_output) { |
| 4044 | 4014 | .dwarf => |dw| { |
| 4045 | // const abi_size = @intCast(u32, ty.abiSize(self.target.*)); | |
| 4046 | 4015 | const adjusted_stack_offset = switch (mcv) { |
| 4047 | 4016 | .stack_offset => |offset| -@intCast(i32, offset), |
| 4048 | 4017 | .stack_argument_offset => |offset| @intCast(i32, self.saved_regs_stack_space + offset), |
src/arch/arm/Emit.zig+4-4
| ... | ... | @@ -94,7 +94,7 @@ pub fn emitMir( |
| 94 | 94 | .sub => try emit.mirDataProcessing(inst), |
| 95 | 95 | .subs => try emit.mirDataProcessing(inst), |
| 96 | 96 | |
| 97 | .sub_sp_scratch_r0 => try emit.mirSubStackPointer(inst), | |
| 97 | .sub_sp_scratch_r4 => try emit.mirSubStackPointer(inst), | |
| 98 | 98 | |
| 99 | 99 | .asr => try emit.mirShift(inst), |
| 100 | 100 | .lsl => try emit.mirShift(inst), |
| ... | ... | @@ -194,7 +194,7 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize { |
| 194 | 194 | .dbg_prologue_end, |
| 195 | 195 | => return 0, |
| 196 | 196 | |
| 197 | .sub_sp_scratch_r0 => { | |
| 197 | .sub_sp_scratch_r4 => { | |
| 198 | 198 | const imm32 = emit.mir.instructions.items(.data)[inst].imm32; |
| 199 | 199 | |
| 200 | 200 | if (imm32 == 0) { |
| ... | ... | @@ -454,11 +454,11 @@ fn mirSubStackPointer(emit: *Emit, inst: Mir.Inst.Index) !void { |
| 454 | 454 | const imm32 = emit.mir.instructions.items(.data)[inst].imm32; |
| 455 | 455 | |
| 456 | 456 | switch (tag) { |
| 457 | .sub_sp_scratch_r0 => { | |
| 457 | .sub_sp_scratch_r4 => { | |
| 458 | 458 | if (imm32 == 0) return; |
| 459 | 459 | |
| 460 | 460 | const operand = Instruction.Operand.fromU32(imm32) orelse blk: { |
| 461 | const scratch: Register = .r0; | |
| 461 | const scratch: Register = .r4; | |
| 462 | 462 | |
| 463 | 463 | if (Target.arm.featureSetHas(emit.target.cpu.features, .has_v7)) { |
| 464 | 464 | try emit.writeInstruction(Instruction.movw(cond, scratch, @truncate(u16, imm32))); |
src/arch/arm/Mir.zig+2-2
| ... | ... | @@ -113,9 +113,9 @@ pub const Inst = struct { |
| 113 | 113 | sub, |
| 114 | 114 | /// Pseudo-instruction: Subtract 32-bit immediate from stack |
| 115 | 115 | /// |
| 116 | /// r0 can be used by Emit as a scratch register for loading | |
| 116 | /// r4 can be used by Emit as a scratch register for loading | |
| 117 | 117 | /// the immediate |
| 118 | sub_sp_scratch_r0, | |
| 118 | sub_sp_scratch_r4, | |
| 119 | 119 | /// Subtract, update condition flags |
| 120 | 120 | subs, |
| 121 | 121 | /// Supervisor Call |