authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-08-03 15:21:46+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-08-30 06:36:41+02:00
log2cb412ff1b6f9cfe027f7534488a6616d3ddc64f
tree7e0b6b91e31c990f7823ecdb909a9d9d5b88ffe4
parent0683e1564c7a4515eb0060a4c740eb6c0d922bb9
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

test: re-enable a bunch of vector behavior tests on hexagon

2 files changed, 6 insertions(+), 6 deletions(-)

test/behavior.zig+1-5
......@@ -102,11 +102,7 @@ test {
102102 _ = @import("behavior/union.zig");
103103 _ = @import("behavior/union_with_members.zig");
104104 _ = @import("behavior/var_args.zig");
105 // https://github.com/llvm/llvm-project/issues/118879
106 // https://github.com/llvm/llvm-project/issues/134659
107 if (!(builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon)) {
108 _ = @import("behavior/vector.zig");
109 }
105 _ = @import("behavior/vector.zig");
110106 _ = @import("behavior/void.zig");
111107 _ = @import("behavior/while.zig");
112108 _ = @import("behavior/widening.zig");
test/behavior/vector.zig+5-1
......@@ -639,6 +639,7 @@ test "vector division operators" {
639639
640640 try comptime S.doTheTest();
641641 if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060
642 if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
642643 try S.doTheTest();
643644}
644645
......@@ -767,8 +768,9 @@ test "vector shift operators" {
767768 }
768769 };
769770
770 try S.doTheTest();
771771 try comptime S.doTheTest();
772 if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
773 try S.doTheTest();
772774}
773775
774776test "vector reduce operation" {
......@@ -1271,6 +1273,7 @@ test "byte vector initialized in inline function" {
12711273 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
12721274 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
12731275 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
1276 if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
12741277
12751278 if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and comptime builtin.cpu.has(.x86, .avx512f)) {
12761279 // TODO https://github.com/ziglang/zig/issues/13279
......@@ -1337,6 +1340,7 @@ test "@intCast to u0" {
13371340 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
13381341 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
13391342 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1343 if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
13401344
13411345 var zeros = @Vector(2, u32){ 0, 0 };
13421346 _ = &zeros;