authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-07-23 20:04:26-07:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-07-23 20:04:26-07:00
log399f4fe7d69723eb94db7e13d2e8ffdc0ce4345b
tree69334f0de7a410fbc2445489bbf9825f3ce13ee5
parent7aaebd17746dc97111585563c64e166e27b334af
parent2d4fc1bb7a0c8b7ac42ace3e2bc05cc72c0efba9
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #20719 from alexrp/misc-porting

`std.os.linux`: A handful of random porting fixes, mostly for `armeb` and `thumbeb`

2 files changed, 94 insertions(+), 15 deletions(-)

lib/std/os/linux.zig+72-9
...@@ -38,7 +38,7 @@ const arch_bits = switch (native_arch) {...@@ -38,7 +38,7 @@ const arch_bits = switch (native_arch) {
38 .x86 => @import("linux/x86.zig"),38 .x86 => @import("linux/x86.zig"),
39 .x86_64 => @import("linux/x86_64.zig"),39 .x86_64 => @import("linux/x86_64.zig"),
40 .aarch64, .aarch64_be => @import("linux/arm64.zig"),40 .aarch64, .aarch64_be => @import("linux/arm64.zig"),
41 .arm, .thumb => @import("linux/arm-eabi.zig"),41 .arm, .armeb, .thumb, .thumbeb => @import("linux/arm-eabi.zig"),
42 .riscv64 => @import("linux/riscv64.zig"),42 .riscv64 => @import("linux/riscv64.zig"),
43 .sparc64 => @import("linux/sparc64.zig"),43 .sparc64 => @import("linux/sparc64.zig"),
44 .mips, .mipsel => @import("linux/mips.zig"),44 .mips, .mipsel => @import("linux/mips.zig"),
...@@ -103,7 +103,7 @@ pub const SYS = switch (@import("builtin").cpu.arch) {...@@ -103,7 +103,7 @@ pub const SYS = switch (@import("builtin").cpu.arch) {
103 .x86 => syscalls.X86,103 .x86 => syscalls.X86,
104 .x86_64 => syscalls.X64,104 .x86_64 => syscalls.X64,
105 .aarch64, .aarch64_be => syscalls.Arm64,105 .aarch64, .aarch64_be => syscalls.Arm64,
106 .arm, .thumb => syscalls.Arm,106 .arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
107 .riscv64 => syscalls.RiscV64,107 .riscv64 => syscalls.RiscV64,
108 .sparc64 => syscalls.Sparc64,108 .sparc64 => syscalls.Sparc64,
109 .mips, .mipsel => syscalls.Mips,109 .mips, .mipsel => syscalls.Mips,
...@@ -142,7 +142,7 @@ pub const MAP = switch (native_arch) {...@@ -142,7 +142,7 @@ pub const MAP = switch (native_arch) {
142 UNINITIALIZED: bool = false,142 UNINITIALIZED: bool = false,
143 _: u5 = 0,143 _: u5 = 0,
144 },144 },
145 .aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {145 .aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
146 TYPE: MAP_TYPE,146 TYPE: MAP_TYPE,
147 FIXED: bool = false,147 FIXED: bool = false,
148 ANONYMOUS: bool = false,148 ANONYMOUS: bool = false,
...@@ -290,7 +290,7 @@ pub const O = switch (native_arch) {...@@ -290,7 +290,7 @@ pub const O = switch (native_arch) {
290 TMPFILE: bool = false,290 TMPFILE: bool = false,
291 _: u9 = 0,291 _: u9 = 0,
292 },292 },
293 .aarch64, .aarch64_be, .arm, .thumb => packed struct(u32) {293 .aarch64, .aarch64_be, .arm, .armeb, .thumb, .thumbeb => packed struct(u32) {
294 ACCMODE: ACCMODE = .RDONLY,294 ACCMODE: ACCMODE = .RDONLY,
295 _2: u4 = 0,295 _2: u4 = 0,
296 CREAT: bool = false,296 CREAT: bool = false,
...@@ -4787,13 +4787,72 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {...@@ -4787,13 +4787,72 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
4787}4787}
47884788
4789pub const MINSIGSTKSZ = switch (native_arch) {4789pub const MINSIGSTKSZ = switch (native_arch) {
4790 .x86, .x86_64, .arm, .mipsel => 2048,4790 .arc,
4791 .aarch64 => 5120,4791 .arm,
4792 .armeb,
4793 .csky,
4794 .hexagon,
4795 .m68k,
4796 .mips,
4797 .mipsel,
4798 .mips64,
4799 .mips64el,
4800 .powerpc,
4801 .powerpcle,
4802 .riscv32,
4803 .riscv64,
4804 .s390x,
4805 .thumb,
4806 .thumbeb,
4807 .x86,
4808 .x86_64,
4809 .xtensa,
4810 => 2048,
4811 .loongarch64,
4812 .sparc,
4813 .sparcel,
4814 .sparc64,
4815 => 4096,
4816 .aarch64,
4817 .aarch64_be,
4818 => 5120,
4819 .powerpc64,
4820 .powerpc64le,
4821 => 8192,
4792 else => @compileError("MINSIGSTKSZ not defined for this architecture"),4822 else => @compileError("MINSIGSTKSZ not defined for this architecture"),
4793};4823};
4794pub const SIGSTKSZ = switch (native_arch) {4824pub const SIGSTKSZ = switch (native_arch) {
4795 .x86, .x86_64, .arm, .mipsel => 8192,4825 .arc,
4796 .aarch64 => 16384,4826 .arm,
4827 .armeb,
4828 .csky,
4829 .hexagon,
4830 .m68k,
4831 .mips,
4832 .mipsel,
4833 .mips64,
4834 .mips64el,
4835 .powerpc,
4836 .powerpcle,
4837 .riscv32,
4838 .riscv64,
4839 .s390x,
4840 .thumb,
4841 .thumbeb,
4842 .x86,
4843 .x86_64,
4844 .xtensa,
4845 => 8192,
4846 .aarch64,
4847 .aarch64_be,
4848 .loongarch64,
4849 .sparc,
4850 .sparcel,
4851 .sparc64,
4852 => 16384,
4853 .powerpc64,
4854 .powerpc64le,
4855 => 32768,
4797 else => @compileError("SIGSTKSZ not defined for this architecture"),4856 else => @compileError("SIGSTKSZ not defined for this architecture"),
4798};4857};
47994858
...@@ -7294,7 +7353,7 @@ pub const AUDIT = struct {...@@ -7294,7 +7353,7 @@ pub const AUDIT = struct {
7294 ARMEB = toAudit(.armeb),7353 ARMEB = toAudit(.armeb),
7295 CSKY = toAudit(.csky),7354 CSKY = toAudit(.csky),
7296 HEXAGON = @intFromEnum(std.elf.EM.HEXAGON),7355 HEXAGON = @intFromEnum(std.elf.EM.HEXAGON),
7297 X86 = toAudit(.x86),7356 LOONGARCH64 = toAudit(.loongarch64),
7298 M68K = toAudit(.m68k),7357 M68K = toAudit(.m68k),
7299 MIPS = toAudit(.mips),7358 MIPS = toAudit(.mips),
7300 MIPSEL = toAudit(.mips) | LE,7359 MIPSEL = toAudit(.mips) | LE,
...@@ -7308,18 +7367,22 @@ pub const AUDIT = struct {...@@ -7308,18 +7367,22 @@ pub const AUDIT = struct {
7308 S390X = toAudit(.s390x),7367 S390X = toAudit(.s390x),
7309 SPARC = toAudit(.sparc),7368 SPARC = toAudit(.sparc),
7310 SPARC64 = toAudit(.sparc64),7369 SPARC64 = toAudit(.sparc64),
7370 X86 = toAudit(.x86),
7311 X86_64 = toAudit(.x86_64),7371 X86_64 = toAudit(.x86_64),
7372 XTENSA = toAudit(.xtensa),
73127373
7313 fn toAudit(arch: std.Target.Cpu.Arch) u32 {7374 fn toAudit(arch: std.Target.Cpu.Arch) u32 {
7314 var res: u32 = @intFromEnum(arch.toElfMachine());7375 var res: u32 = @intFromEnum(arch.toElfMachine());
7315 if (arch.endian() == .little) res |= LE;7376 if (arch.endian() == .little) res |= LE;
7316 switch (arch) {7377 switch (arch) {
7317 .aarch64,7378 .aarch64,
7379 .loongarch64,
7318 .mips64,7380 .mips64,
7319 .mips64el,7381 .mips64el,
7320 .powerpc64,7382 .powerpc64,
7321 .powerpc64le,7383 .powerpc64le,
7322 .riscv64,7384 .riscv64,
7385 .s390x,
7323 .sparc64,7386 .sparc64,
7324 .x86_64,7387 .x86_64,
7325 => res |= @"64BIT",7388 => res |= @"64BIT",
lib/std/os/linux/tls.zig+22-6
...@@ -49,7 +49,23 @@ const TLSVariant = enum {...@@ -49,7 +49,23 @@ const TLSVariant = enum {
49};49};
5050
51const tls_variant = switch (native_arch) {51const tls_variant = switch (native_arch) {
52 .arm, .armeb, .thumb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => TLSVariant.VariantI,52 .arm,
53 .armeb,
54 .thumb,
55 .thumbeb,
56 .aarch64,
57 .aarch64_be,
58 .riscv32,
59 .riscv64,
60 .mips,
61 .mipsel,
62 .mips64,
63 .mips64el,
64 .powerpc,
65 .powerpcle,
66 .powerpc64,
67 .powerpc64le,
68 => TLSVariant.VariantI,
53 .x86_64, .x86, .sparc64 => TLSVariant.VariantII,69 .x86_64, .x86, .sparc64 => TLSVariant.VariantII,
54 else => @compileError("undefined tls_variant for this architecture"),70 else => @compileError("undefined tls_variant for this architecture"),
55};71};
...@@ -58,14 +74,14 @@ const tls_variant = switch (native_arch) {...@@ -58,14 +74,14 @@ const tls_variant = switch (native_arch) {
58const tls_tcb_size = switch (native_arch) {74const tls_tcb_size = switch (native_arch) {
59 // ARM EABI mandates enough space for two pointers: the first one points to75 // ARM EABI mandates enough space for two pointers: the first one points to
60 // the DTV while the second one is unspecified but reserved76 // the DTV while the second one is unspecified but reserved
61 .arm, .armeb, .thumb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),77 .arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
62 // One pointer-sized word that points either to the DTV or the TCB itself78 // One pointer-sized word that points either to the DTV or the TCB itself
63 else => @sizeOf(usize),79 else => @sizeOf(usize),
64};80};
6581
66// Controls if the TP points to the end of the TCB instead of its beginning82// Controls if the TP points to the end of the TCB instead of its beginning
67const tls_tp_points_past_tcb = switch (native_arch) {83const tls_tp_points_past_tcb = switch (native_arch) {
68 .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => true,84 .riscv32, .riscv64, .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => true,
69 else => false,85 else => false,
70};86};
7187
...@@ -73,12 +89,12 @@ const tls_tp_points_past_tcb = switch (native_arch) {...@@ -73,12 +89,12 @@ const tls_tp_points_past_tcb = switch (native_arch) {
73// make the generated code more efficient89// make the generated code more efficient
7490
75const tls_tp_offset = switch (native_arch) {91const tls_tp_offset = switch (native_arch) {
76 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x7000,92 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x7000,
77 else => 0,93 else => 0,
78};94};
7995
80const tls_dtv_offset = switch (native_arch) {96const tls_dtv_offset = switch (native_arch) {
81 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpc64, .powerpc64le => 0x8000,97 .mips, .mipsel, .mips64, .mips64el, .powerpc, .powerpcle, .powerpc64, .powerpc64le => 0x8000,
82 .riscv32, .riscv64 => 0x800,98 .riscv32, .riscv64 => 0x800,
83 else => 0,99 else => 0,
84};100};
...@@ -150,7 +166,7 @@ pub fn setThreadPointer(addr: usize) void {...@@ -150,7 +166,7 @@ pub fn setThreadPointer(addr: usize) void {
150 : [addr] "r" (addr),166 : [addr] "r" (addr),
151 );167 );
152 },168 },
153 .arm, .thumb => {169 .arm, .armeb, .thumb, .thumbeb => {
154 const rc = @call(.always_inline, linux.syscall1, .{ .set_tls, addr });170 const rc = @call(.always_inline, linux.syscall1, .{ .set_tls, addr });
155 assert(rc == 0);171 assert(rc == 0);
156 },172 },