| ... | ... | @@ -57,6 +57,84 @@ pub fn addCases(cases: *tests.CompileErrorContext) void { |
| 57 | 57 | "tmp.zig:1:22: note: type u2 cannot fit values in range 0...4", |
| 58 | 58 | }); |
| 59 | 59 | |
| 60 | cases.addCase(x: { |
| 61 | var tc = cases.create("callconv(.Interrupt) on unsupported platform", |
| 62 | \\export fn entry() callconv(.Interrupt) void {} |
| 63 | , &[_][]const u8{ |
| 64 | "tmp.zig:1:28: error: callconv 'Interrupt' is only available on x86, x86_64, AVR, and MSP430, not aarch64", |
| 65 | }); |
| 66 | tc.target = std.zig.CrossTarget{ |
| 67 | .cpu_arch = .aarch64, |
| 68 | .os_tag = .linux, |
| 69 | .abi = .none, |
| 70 | }; |
| 71 | break :x tc; |
| 72 | }); |
| 73 | |
| 74 | cases.addCase(x: { |
| 75 | var tc = cases.create("callconv(.Signal) on unsupported platform", |
| 76 | \\export fn entry() callconv(.Signal) void {} |
| 77 | , &[_][]const u8{ |
| 78 | "tmp.zig:1:28: error: callconv 'Signal' is only available on AVR, not x86_64", |
| 79 | }); |
| 80 | tc.target = std.zig.CrossTarget{ |
| 81 | .cpu_arch = .x86_64, |
| 82 | .os_tag = .linux, |
| 83 | .abi = .none, |
| 84 | }; |
| 85 | break :x tc; |
| 86 | }); |
| 87 | |
| 88 | cases.addCase(x: { |
| 89 | var tc = cases.create("callconv(.Stdcall, .Fastcall, .Thiscall) on unsupported platform", |
| 90 | \\export fn entry1() callconv(.Stdcall) void {} |
| 91 | \\export fn entry2() callconv(.Fastcall) void {} |
| 92 | \\export fn entry3() callconv(.Thiscall) void {} |
| 93 | , &[_][]const u8{ |
| 94 | "tmp.zig:1:29: error: callconv 'Stdcall' is only available on x86, not x86_64", |
| 95 | "tmp.zig:2:29: error: callconv 'Fastcall' is only available on x86, not x86_64", |
| 96 | "tmp.zig:3:29: error: callconv 'Thiscall' is only available on x86, not x86_64", |
| 97 | }); |
| 98 | tc.target = std.zig.CrossTarget{ |
| 99 | .cpu_arch = .x86_64, |
| 100 | .os_tag = .linux, |
| 101 | .abi = .none, |
| 102 | }; |
| 103 | break :x tc; |
| 104 | }); |
| 105 | |
| 106 | cases.addCase(x: { |
| 107 | var tc = cases.create("callconv(.Vectorcall) on unsupported platform", |
| 108 | \\export fn entry() callconv(.Vectorcall) void {} |
| 109 | , &[_][]const u8{ |
| 110 | "tmp.zig:1:28: error: callconv 'Vectorcall' is only available on x86 and AArch64, not x86_64", |
| 111 | }); |
| 112 | tc.target = std.zig.CrossTarget{ |
| 113 | .cpu_arch = .x86_64, |
| 114 | .os_tag = .linux, |
| 115 | .abi = .none, |
| 116 | }; |
| 117 | break :x tc; |
| 118 | }); |
| 119 | |
| 120 | cases.addCase(x: { |
| 121 | var tc = cases.create("callconv(.APCS, .AAPCS, .AAPCSVFP) on unsupported platform", |
| 122 | \\export fn entry1() callconv(.APCS) void {} |
| 123 | \\export fn entry2() callconv(.AAPCS) void {} |
| 124 | \\export fn entry3() callconv(.AAPCSVFP) void {} |
| 125 | , &[_][]const u8{ |
| 126 | "tmp.zig:1:29: error: callconv 'APCS' is only available on ARM, not x86_64", |
| 127 | "tmp.zig:2:29: error: callconv 'AAPCS' is only available on ARM, not x86_64", |
| 128 | "tmp.zig:3:29: error: callconv 'AAPCSVFP' is only available on ARM, not x86_64", |
| 129 | }); |
| 130 | tc.target = std.zig.CrossTarget{ |
| 131 | .cpu_arch = .x86_64, |
| 132 | .os_tag = .linux, |
| 133 | .abi = .none, |
| 134 | }; |
| 135 | break :x tc; |
| 136 | }); |
| 137 | |
| 60 | 138 | cases.add("unreachable executed at comptime", |
| 61 | 139 | \\fn foo(comptime x: i32) i32 { |
| 62 | 140 | \\ comptime { |