authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 01:44:26-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 03:07:51-04:00
log40457a3696da015fe1396d6c84191b83731910db
treeb1e9791cbeca7d2aec7c3c995db07b95b9c06dff
parentf39ff6cc68ab7a0d8ef349d4d930118890c19b01

x86_64: implement integer vector bitwise operations

2 files changed, 25 insertions(+), 1 deletions(-)

src/arch/x86_64/CodeGen.zig+25
...@@ -6531,6 +6531,9 @@ fn genBinOp(...@@ -6531,6 +6531,9 @@ fn genBinOp(
6531 .sub,6531 .sub,
6532 .subwrap,6532 .subwrap,
6533 => if (self.hasFeature(.avx)) .{ .vp_b, .sub } else .{ .p_b, .sub },6533 => if (self.hasFeature(.avx)) .{ .vp_b, .sub } else .{ .p_b, .sub },
6534 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6535 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6536 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
6534 else => null,6537 else => null,
6535 },6538 },
6536 17...32 => switch (air_tag) {6539 17...32 => switch (air_tag) {
...@@ -6540,6 +6543,9 @@ fn genBinOp(...@@ -6540,6 +6543,9 @@ fn genBinOp(
6540 .sub,6543 .sub,
6541 .subwrap,6544 .subwrap,
6542 => if (self.hasFeature(.avx2)) .{ .vp_b, .sub } else null,6545 => if (self.hasFeature(.avx2)) .{ .vp_b, .sub } else null,
6546 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6547 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6548 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
6543 else => null,6549 else => null,
6544 },6550 },
6545 else => null,6551 else => null,
...@@ -6555,6 +6561,9 @@ fn genBinOp(...@@ -6555,6 +6561,9 @@ fn genBinOp(
6555 .mul,6561 .mul,
6556 .mulwrap,6562 .mulwrap,
6557 => if (self.hasFeature(.avx)) .{ .vp_w, .mull } else .{ .p_d, .mull },6563 => if (self.hasFeature(.avx)) .{ .vp_w, .mull } else .{ .p_d, .mull },
6564 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6565 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6566 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
6558 else => null,6567 else => null,
6559 },6568 },
6560 9...16 => switch (air_tag) {6569 9...16 => switch (air_tag) {
...@@ -6567,6 +6576,9 @@ fn genBinOp(...@@ -6567,6 +6576,9 @@ fn genBinOp(
6567 .mul,6576 .mul,
6568 .mulwrap,6577 .mulwrap,
6569 => if (self.hasFeature(.avx2)) .{ .vp_w, .mull } else null,6578 => if (self.hasFeature(.avx2)) .{ .vp_w, .mull } else null,
6579 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6580 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6581 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
6570 else => null,6582 else => null,
6571 },6583 },
6572 else => null,6584 else => null,
...@@ -6587,6 +6599,9 @@ fn genBinOp(...@@ -6587,6 +6599,9 @@ fn genBinOp(
6587 .{ .p_d, .mull }6599 .{ .p_d, .mull }
6588 else6600 else
6589 null,6601 null,
6602 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6603 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6604 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
6590 else => null,6605 else => null,
6591 },6606 },
6592 5...8 => switch (air_tag) {6607 5...8 => switch (air_tag) {
...@@ -6599,6 +6614,9 @@ fn genBinOp(...@@ -6599,6 +6614,9 @@ fn genBinOp(
6599 .mul,6614 .mul,
6600 .mulwrap,6615 .mulwrap,
6601 => if (self.hasFeature(.avx2)) .{ .vp_d, .mull } else null,6616 => if (self.hasFeature(.avx2)) .{ .vp_d, .mull } else null,
6617 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6618 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6619 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
6602 else => null,6620 else => null,
6603 },6621 },
6604 else => null,6622 else => null,
...@@ -6611,6 +6629,9 @@ fn genBinOp(...@@ -6611,6 +6629,9 @@ fn genBinOp(
6611 .sub,6629 .sub,
6612 .subwrap,6630 .subwrap,
6613 => if (self.hasFeature(.avx)) .{ .vp_q, .sub } else .{ .p_q, .sub },6631 => if (self.hasFeature(.avx)) .{ .vp_q, .sub } else .{ .p_q, .sub },
6632 .bit_and => if (self.hasFeature(.avx)) .{ .vp_, .@"and" } else .{ .p_, .@"and" },
6633 .bit_or => if (self.hasFeature(.avx)) .{ .vp_, .@"or" } else .{ .p_, .@"or" },
6634 .xor => if (self.hasFeature(.avx)) .{ .vp_, .xor } else .{ .p_, .xor },
6614 else => null,6635 else => null,
6615 },6636 },
6616 3...4 => switch (air_tag) {6637 3...4 => switch (air_tag) {
...@@ -6620,6 +6641,9 @@ fn genBinOp(...@@ -6620,6 +6641,9 @@ fn genBinOp(
6620 .sub,6641 .sub,
6621 .subwrap,6642 .subwrap,
6622 => if (self.hasFeature(.avx2)) .{ .vp_q, .sub } else null,6643 => if (self.hasFeature(.avx2)) .{ .vp_q, .sub } else null,
6644 .bit_and => if (self.hasFeature(.avx2)) .{ .vp_, .@"and" } else null,
6645 .bit_or => if (self.hasFeature(.avx2)) .{ .vp_, .@"or" } else null,
6646 .xor => if (self.hasFeature(.avx2)) .{ .vp_, .xor } else null,
6623 else => null,6647 else => null,
6624 },6648 },
6625 else => null,6649 else => null,
...@@ -6929,6 +6953,7 @@ fn genBinOp(...@@ -6929,6 +6953,7 @@ fn genBinOp(
6929 else => unreachable,6953 else => unreachable,
6930 },6954 },
6931 ),6955 ),
6956 .bit_and, .bit_or, .xor => {},
6932 .max, .min => {}, // TODO: unordered select6957 .max, .min => {}, // TODO: unordered select
6933 else => unreachable,6958 else => unreachable,
6934 }6959 }
test/behavior/vector.zig-1
...@@ -120,7 +120,6 @@ test "vector float operators" {...@@ -120,7 +120,6 @@ test "vector float operators" {
120120
121test "vector bit operators" {121test "vector bit operators" {
122 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO122 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
123 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
124 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO123 if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
125 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO124 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
126 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO125 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO