authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2022-01-10 01:48:49-05:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2022-01-10 01:48:49-05:00
log42ef95d79d9cb60fde8c83bfb2eef49969e7c8e3
treeeb7f1e0781b19b5671881912277681989a912aab
parentd66c97d0ef0434ce0814d1921877b9ffa877a645
parentb5f03b3b7a33a1c63855a609ea2bb224f4a76065
signaturebadge-question-mark Signed by PGP key 4AEE18F83AFDEB23

Merge pull request #10554 from joachimschmidt557/stage2-arm

stage2 ARM: refactor and pass 1 more behavior test file

6 files changed, 236 insertions(+), 263 deletions(-)

src/arch/aarch64/CodeGen.zig+3-4
...@@ -2104,17 +2104,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {...@@ -2104,17 +2104,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
2104 // block results.2104 // block results.
2105 .mcv = MCValue{ .none = {} },2105 .mcv = MCValue{ .none = {} },
2106 });2106 });
2107 const block_data = self.blocks.getPtr(inst).?;2107 defer self.blocks.getPtr(inst).?.relocs.deinit(self.gpa);
2108 defer block_data.relocs.deinit(self.gpa);
21092108
2110 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;2109 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
2111 const extra = self.air.extraData(Air.Block, ty_pl.payload);2110 const extra = self.air.extraData(Air.Block, ty_pl.payload);
2112 const body = self.air.extra[extra.end..][0..extra.data.body_len];2111 const body = self.air.extra[extra.end..][0..extra.data.body_len];
2113 try self.genBody(body);2112 try self.genBody(body);
21142113
2115 for (block_data.relocs.items) |reloc| try self.performReloc(reloc);2114 for (self.blocks.getPtr(inst).?.relocs.items) |reloc| try self.performReloc(reloc);
21162115
2117 const result = @bitCast(MCValue, block_data.mcv);2116 const result = self.blocks.getPtr(inst).?.mcv;
2118 return self.finishAir(inst, result, .{ .none, .none, .none });2117 return self.finishAir(inst, result, .{ .none, .none, .none });
2119}2118}
21202119
src/arch/arm/CodeGen.zig+35-63
...@@ -338,7 +338,6 @@ fn addInst(self: *Self, inst: Mir.Inst) error{OutOfMemory}!Mir.Inst.Index {...@@ -338,7 +338,6 @@ fn addInst(self: *Self, inst: Mir.Inst) error{OutOfMemory}!Mir.Inst.Index {
338fn addNop(self: *Self) error{OutOfMemory}!Mir.Inst.Index {338fn addNop(self: *Self) error{OutOfMemory}!Mir.Inst.Index {
339 return try self.addInst(.{339 return try self.addInst(.{
340 .tag = .nop,340 .tag = .nop,
341 .cond = .al,
342 .data = .{ .nop = {} },341 .data = .{ .nop = {} },
343 });342 });
344}343}
...@@ -371,7 +370,6 @@ fn gen(self: *Self) !void {...@@ -371,7 +370,6 @@ fn gen(self: *Self) !void {
371 // mov fp, sp370 // mov fp, sp
372 _ = try self.addInst(.{371 _ = try self.addInst(.{
373 .tag = .mov,372 .tag = .mov,
374 .cond = .al,
375 .data = .{ .rr_op = .{373 .data = .{ .rr_op = .{
376 .rd = .fp,374 .rd = .fp,
377 .rn = .r0,375 .rn = .r0,
...@@ -405,7 +403,6 @@ fn gen(self: *Self) !void {...@@ -405,7 +403,6 @@ fn gen(self: *Self) !void {
405403
406 self.mir_instructions.set(push_reloc, .{404 self.mir_instructions.set(push_reloc, .{
407 .tag = .push,405 .tag = .push,
408 .cond = .al,
409 .data = .{ .register_list = saved_regs },406 .data = .{ .register_list = saved_regs },
410 });407 });
411408
...@@ -416,7 +413,6 @@ fn gen(self: *Self) !void {...@@ -416,7 +413,6 @@ fn gen(self: *Self) !void {
416 if (Instruction.Operand.fromU32(stack_size)) |op| {413 if (Instruction.Operand.fromU32(stack_size)) |op| {
417 self.mir_instructions.set(sub_reloc, .{414 self.mir_instructions.set(sub_reloc, .{
418 .tag = .sub,415 .tag = .sub,
419 .cond = .al,
420 .data = .{ .rr_op = .{ .rd = .sp, .rn = .sp, .op = op } },416 .data = .{ .rr_op = .{ .rd = .sp, .rn = .sp, .op = op } },
421 });417 });
422 } else {418 } else {
...@@ -440,7 +436,6 @@ fn gen(self: *Self) !void {...@@ -440,7 +436,6 @@ fn gen(self: *Self) !void {
440 } else for (self.exitlude_jump_relocs.items) |jmp_reloc| {436 } else for (self.exitlude_jump_relocs.items) |jmp_reloc| {
441 self.mir_instructions.set(jmp_reloc, .{437 self.mir_instructions.set(jmp_reloc, .{
442 .tag = .b,438 .tag = .b,
443 .cond = .al,
444 .data = .{ .inst = @intCast(u32, self.mir_instructions.len) },439 .data = .{ .inst = @intCast(u32, self.mir_instructions.len) },
445 });440 });
446 }441 }
...@@ -452,7 +447,6 @@ fn gen(self: *Self) !void {...@@ -452,7 +447,6 @@ fn gen(self: *Self) !void {
452 // mov sp, fp447 // mov sp, fp
453 _ = try self.addInst(.{448 _ = try self.addInst(.{
454 .tag = .mov,449 .tag = .mov,
455 .cond = .al,
456 .data = .{ .rr_op = .{450 .data = .{ .rr_op = .{
457 .rd = .sp,451 .rd = .sp,
458 .rn = .r0,452 .rn = .r0,
...@@ -463,7 +457,6 @@ fn gen(self: *Self) !void {...@@ -463,7 +457,6 @@ fn gen(self: *Self) !void {
463 // pop {fp, pc}457 // pop {fp, pc}
464 _ = try self.addInst(.{458 _ = try self.addInst(.{
465 .tag = .pop,459 .tag = .pop,
466 .cond = .al,
467 .data = .{ .register_list = saved_regs },460 .data = .{ .register_list = saved_regs },
468 });461 });
469 } else {462 } else {
...@@ -1251,7 +1244,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1251,7 +1244,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
12511244
1252 _ = try self.addInst(.{1245 _ = try self.addInst(.{
1253 .tag = tag,1246 .tag = tag,
1254 .cond = .al,
1255 .data = .{ .rr_offset = .{1247 .data = .{ .rr_offset = .{
1256 .rt = dst_reg,1248 .rt = dst_reg,
1257 .rn = base_mcv.register,1249 .rn = base_mcv.register,
...@@ -1262,7 +1254,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {...@@ -1262,7 +1254,6 @@ fn airSliceElemVal(self: *Self, inst: Air.Inst.Index) !void {
1262 2 => {1254 2 => {
1263 _ = try self.addInst(.{1255 _ = try self.addInst(.{
1264 .tag = .ldrh,1256 .tag = .ldrh,
1265 .cond = .al,
1266 .data = .{ .rr_extra_offset = .{1257 .data = .{ .rr_extra_offset = .{
1267 .rt = dst_reg,1258 .rt = dst_reg,
1268 .rn = base_mcv.register,1259 .rn = base_mcv.register,
...@@ -1406,7 +1397,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1406,7 +1397,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1406 .register => |dst_reg| {1397 .register => |dst_reg| {
1407 _ = try self.addInst(.{1398 _ = try self.addInst(.{
1408 .tag = .ldr,1399 .tag = .ldr,
1409 .cond = .al,
1410 .data = .{ .rr_offset = .{1400 .data = .{ .rr_offset = .{
1411 .rt = dst_reg,1401 .rt = dst_reg,
1412 .rn = reg,1402 .rn = reg,
...@@ -1430,7 +1420,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1430,7 +1420,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1430 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{reg});1420 const tmp_regs = try self.register_manager.allocRegs(2, .{ null, null }, &.{reg});
1431 _ = try self.addInst(.{1421 _ = try self.addInst(.{
1432 .tag = .ldr,1422 .tag = .ldr,
1433 .cond = .al,
1434 .data = .{ .rr_offset = .{1423 .data = .{ .rr_offset = .{
1435 .rt = tmp_regs[0],1424 .rt = tmp_regs[0],
1436 .rn = reg,1425 .rn = reg,
...@@ -1439,7 +1428,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1439,7 +1428,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1439 });1428 });
1440 _ = try self.addInst(.{1429 _ = try self.addInst(.{
1441 .tag = .ldr,1430 .tag = .ldr,
1442 .cond = .al,
1443 .data = .{ .rr_offset = .{1431 .data = .{ .rr_offset = .{
1444 .rt = tmp_regs[1],1432 .rt = tmp_regs[1],
1445 .rn = reg,1433 .rn = reg,
...@@ -1465,7 +1453,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1465,7 +1453,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1465 };1453 };
1466 _ = try self.addInst(.{1454 _ = try self.addInst(.{
1467 .tag = .sub,1455 .tag = .sub,
1468 .cond = .al,
1469 .data = .{ .rr_op = .{1456 .data = .{ .rr_op = .{
1470 .rd = dst_reg,1457 .rd = dst_reg,
1471 .rn = .fp,1458 .rn = .fp,
...@@ -1479,7 +1466,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo...@@ -1479,7 +1466,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
1479 };1466 };
1480 _ = try self.addInst(.{1467 _ = try self.addInst(.{
1481 .tag = .mov,1468 .tag = .mov,
1482 .cond = .al,
1483 .data = .{ .rr_op = .{1469 .data = .{ .rr_op = .{
1484 .rd = len_reg,1470 .rd = len_reg,
1485 .rn = .r0,1471 .rn = .r0,
...@@ -1560,7 +1546,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type...@@ -1560,7 +1546,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
1560 .register => |value_reg| {1546 .register => |value_reg| {
1561 _ = try self.addInst(.{1547 _ = try self.addInst(.{
1562 .tag = .str,1548 .tag = .str,
1563 .cond = .al,
1564 .data = .{ .rr_offset = .{1549 .data = .{ .rr_offset = .{
1565 .rt = value_reg,1550 .rt = value_reg,
1566 .rn = addr_reg,1551 .rn = addr_reg,
...@@ -1866,7 +1851,6 @@ fn genArmBinOpCode(...@@ -1866,7 +1851,6 @@ fn genArmBinOpCode(
18661851
1867 _ = try self.addInst(.{1852 _ = try self.addInst(.{
1868 .tag = tag,1853 .tag = tag,
1869 .cond = .al,
1870 .data = .{ .rr_op = .{1854 .data = .{ .rr_op = .{
1871 .rd = dst_reg,1855 .rd = dst_reg,
1872 .rn = op1,1856 .rn = op1,
...@@ -1879,7 +1863,6 @@ fn genArmBinOpCode(...@@ -1879,7 +1863,6 @@ fn genArmBinOpCode(
18791863
1880 _ = try self.addInst(.{1864 _ = try self.addInst(.{
1881 .tag = tag,1865 .tag = tag,
1882 .cond = .al,
1883 .data = .{ .rr_op = .{1866 .data = .{ .rr_op = .{
1884 .rd = dst_reg,1867 .rd = dst_reg,
1885 .rn = op1,1868 .rn = op1,
...@@ -1890,7 +1873,6 @@ fn genArmBinOpCode(...@@ -1890,7 +1873,6 @@ fn genArmBinOpCode(
1890 .cmp_eq => {1873 .cmp_eq => {
1891 _ = try self.addInst(.{1874 _ = try self.addInst(.{
1892 .tag = .cmp,1875 .tag = .cmp,
1893 .cond = .al,
1894 .data = .{ .rr_op = .{1876 .data = .{ .rr_op = .{
1895 .rd = .r0,1877 .rd = .r0,
1896 .rn = op1,1878 .rn = op1,
...@@ -1916,7 +1898,6 @@ fn genArmBinOpCode(...@@ -1916,7 +1898,6 @@ fn genArmBinOpCode(
19161898
1917 _ = try self.addInst(.{1899 _ = try self.addInst(.{
1918 .tag = tag,1900 .tag = tag,
1919 .cond = .al,
1920 .data = .{ .rr_shift = .{1901 .data = .{ .rr_shift = .{
1921 .rd = dst_reg,1902 .rd = dst_reg,
1922 .rm = op1,1903 .rm = op1,
...@@ -1993,7 +1974,6 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai...@@ -1993,7 +1974,6 @@ fn genArmMul(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs: Ai
19931974
1994 _ = try self.addInst(.{1975 _ = try self.addInst(.{
1995 .tag = .mul,1976 .tag = .mul,
1996 .cond = .al,
1997 .data = .{ .rrr = .{1977 .data = .{ .rrr = .{
1998 .rd = dst_mcv.register,1978 .rd = dst_mcv.register,
1999 .rn = lhs_mcv.register,1979 .rn = lhs_mcv.register,
...@@ -2045,7 +2025,6 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind...@@ -2045,7 +2025,6 @@ fn genArmMulConstant(self: *Self, inst: Air.Inst.Index, op: Air.Inst.Ref, op_ind
20452025
2046 _ = try self.addInst(.{2026 _ = try self.addInst(.{
2047 .tag = .mul,2027 .tag = .mul,
2048 .cond = .al,
2049 .data = .{ .rrr = .{2028 .data = .{ .rrr = .{
2050 .rd = dst_mcv.register,2029 .rd = dst_mcv.register,
2051 .rn = lhs_mcv.register,2030 .rn = lhs_mcv.register,
...@@ -2066,7 +2045,6 @@ fn genArmInlineMemcpy(...@@ -2066,7 +2045,6 @@ fn genArmInlineMemcpy(
2066 // mov count, #02045 // mov count, #0
2067 _ = try self.addInst(.{2046 _ = try self.addInst(.{
2068 .tag = .mov,2047 .tag = .mov,
2069 .cond = .al,
2070 .data = .{ .rr_op = .{2048 .data = .{ .rr_op = .{
2071 .rd = count,2049 .rd = count,
2072 .rn = .r0,2050 .rn = .r0,
...@@ -2078,7 +2056,6 @@ fn genArmInlineMemcpy(...@@ -2078,7 +2056,6 @@ fn genArmInlineMemcpy(
2078 // cmp count, len2056 // cmp count, len
2079 _ = try self.addInst(.{2057 _ = try self.addInst(.{
2080 .tag = .cmp,2058 .tag = .cmp,
2081 .cond = .al,
2082 .data = .{ .rr_op = .{2059 .data = .{ .rr_op = .{
2083 .rd = .r0,2060 .rd = .r0,
2084 .rn = count,2061 .rn = count,
...@@ -2096,7 +2073,6 @@ fn genArmInlineMemcpy(...@@ -2096,7 +2073,6 @@ fn genArmInlineMemcpy(
2096 // ldrb tmp, [src, count]2073 // ldrb tmp, [src, count]
2097 _ = try self.addInst(.{2074 _ = try self.addInst(.{
2098 .tag = .ldrb,2075 .tag = .ldrb,
2099 .cond = .al,
2100 .data = .{ .rr_offset = .{2076 .data = .{ .rr_offset = .{
2101 .rt = tmp,2077 .rt = tmp,
2102 .rn = src,2078 .rn = src,
...@@ -2107,7 +2083,6 @@ fn genArmInlineMemcpy(...@@ -2107,7 +2083,6 @@ fn genArmInlineMemcpy(
2107 // strb tmp, [src, count]2083 // strb tmp, [src, count]
2108 _ = try self.addInst(.{2084 _ = try self.addInst(.{
2109 .tag = .strb,2085 .tag = .strb,
2110 .cond = .al,
2111 .data = .{ .rr_offset = .{2086 .data = .{ .rr_offset = .{
2112 .rt = tmp,2087 .rt = tmp,
2113 .rn = dst,2088 .rn = dst,
...@@ -2118,7 +2093,6 @@ fn genArmInlineMemcpy(...@@ -2118,7 +2093,6 @@ fn genArmInlineMemcpy(
2118 // add count, count, #12093 // add count, count, #1
2119 _ = try self.addInst(.{2094 _ = try self.addInst(.{
2120 .tag = .add,2095 .tag = .add,
2121 .cond = .al,
2122 .data = .{ .rr_op = .{2096 .data = .{ .rr_op = .{
2123 .rd = count,2097 .rd = count,
2124 .rn = count,2098 .rn = count,
...@@ -2129,7 +2103,6 @@ fn genArmInlineMemcpy(...@@ -2129,7 +2103,6 @@ fn genArmInlineMemcpy(
2129 // b loop2103 // b loop
2130 _ = try self.addInst(.{2104 _ = try self.addInst(.{
2131 .tag = .b,2105 .tag = .b,
2132 .cond = .al,
2133 .data = .{ .inst = @intCast(u32, self.mir_instructions.len - 5) },2106 .data = .{ .inst = @intCast(u32, self.mir_instructions.len - 5) },
2134 });2107 });
21352108
...@@ -2236,7 +2209,6 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {...@@ -2236,7 +2209,6 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
2236fn airBreakpoint(self: *Self) !void {2209fn airBreakpoint(self: *Self) !void {
2237 _ = try self.addInst(.{2210 _ = try self.addInst(.{
2238 .tag = .bkpt,2211 .tag = .bkpt,
2239 .cond = .al,
2240 .data = .{ .imm16 = 0 },2212 .data = .{ .imm16 = 0 },
2241 });2213 });
2242 return self.finishAirBookkeeping();2214 return self.finishAirBookkeeping();
...@@ -2348,14 +2320,12 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {...@@ -2348,14 +2320,12 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
2348 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {2320 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
2349 _ = try self.addInst(.{2321 _ = try self.addInst(.{
2350 .tag = .blx,2322 .tag = .blx,
2351 .cond = .al,
2352 .data = .{ .reg = .lr },2323 .data = .{ .reg = .lr },
2353 });2324 });
2354 } else {2325 } else {
2355 return self.fail("TODO fix blx emulation for ARM <v5", .{});2326 return self.fail("TODO fix blx emulation for ARM <v5", .{});
2356 // _ = try self.addInst(.{2327 // _ = try self.addInst(.{
2357 // .tag = .mov,2328 // .tag = .mov,
2358 // .cond = .al,
2359 // .data = .{ .rr_op = .{2329 // .data = .{ .rr_op = .{
2360 // .rd = .lr,2330 // .rd = .lr,
2361 // .rn = .r0,2331 // .rn = .r0,
...@@ -2364,7 +2334,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {...@@ -2364,7 +2334,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index) !void {
2364 // });2334 // });
2365 // _ = try self.addInst(.{2335 // _ = try self.addInst(.{
2366 // .tag = .bx,2336 // .tag = .bx,
2367 // .cond = .al,
2368 // .data = .{ .reg = .lr },2337 // .data = .{ .reg = .lr },
2369 // });2338 // });
2370 }2339 }
...@@ -2535,6 +2504,8 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {...@@ -2535,6 +2504,8 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
2535 break :blk condition.negate();2504 break :blk condition.negate();
2536 },2505 },
2537 .register => |reg| blk: {2506 .register => |reg| blk: {
2507 try self.spillCompareFlagsIfOccupied();
2508
2538 // cmp reg, 12509 // cmp reg, 1
2539 // bne ...2510 // bne ...
2540 _ = try self.addInst(.{2511 _ = try self.addInst(.{
...@@ -2549,6 +2520,26 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {...@@ -2549,6 +2520,26 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
25492520
2550 break :blk .ne;2521 break :blk .ne;
2551 },2522 },
2523 .stack_offset,
2524 .memory,
2525 => blk: {
2526 try self.spillCompareFlagsIfOccupied();
2527
2528 const reg = try self.copyToTmpRegister(Type.initTag(.bool), cond);
2529
2530 // cmp reg, 1
2531 // bne ...
2532 _ = try self.addInst(.{
2533 .tag = .cmp,
2534 .data = .{ .rr_op = .{
2535 .rd = .r0,
2536 .rn = reg,
2537 .op = Instruction.Operand.imm(1, 0),
2538 } },
2539 });
2540
2541 break :blk .ne;
2542 },
2552 else => return self.fail("TODO implement condbr {} when condition is {s}", .{ self.target.cpu.arch, @tagName(cond) }),2543 else => return self.fail("TODO implement condbr {} when condition is {s}", .{ self.target.cpu.arch, @tagName(cond) }),
2553 };2544 };
25542545
...@@ -2889,7 +2880,6 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {...@@ -2889,7 +2880,6 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {
2889fn jump(self: *Self, inst: Mir.Inst.Index) !void {2880fn jump(self: *Self, inst: Mir.Inst.Index) !void {
2890 _ = try self.addInst(.{2881 _ = try self.addInst(.{
2891 .tag = .b,2882 .tag = .b,
2892 .cond = .al,
2893 .data = .{ .inst = inst },2883 .data = .{ .inst = inst },
2894 });2884 });
2895}2885}
...@@ -2905,17 +2895,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {...@@ -2905,17 +2895,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
2905 // block results.2895 // block results.
2906 .mcv = MCValue{ .none = {} },2896 .mcv = MCValue{ .none = {} },
2907 });2897 });
2908 const block_data = self.blocks.getPtr(inst).?;2898 defer self.blocks.getPtr(inst).?.relocs.deinit(self.gpa);
2909 defer block_data.relocs.deinit(self.gpa);
29102899
2911 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;2900 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
2912 const extra = self.air.extraData(Air.Block, ty_pl.payload);2901 const extra = self.air.extraData(Air.Block, ty_pl.payload);
2913 const body = self.air.extra[extra.end..][0..extra.data.body_len];2902 const body = self.air.extra[extra.end..][0..extra.data.body_len];
2914 try self.genBody(body);2903 try self.genBody(body);
29152904
2916 for (block_data.relocs.items) |reloc| try self.performReloc(reloc);2905 for (self.blocks.getPtr(inst).?.relocs.items) |reloc| try self.performReloc(reloc);
29172906
2918 const result = @bitCast(MCValue, block_data.mcv);2907 const result = self.blocks.getPtr(inst).?.mcv;
2919 return self.finishAir(inst, result, .{ .none, .none, .none });2908 return self.finishAir(inst, result, .{ .none, .none, .none });
2920}2909}
29212910
...@@ -2959,7 +2948,16 @@ fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {...@@ -2959,7 +2948,16 @@ fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {
2959 const operand_mcv = try self.resolveInst(operand);2948 const operand_mcv = try self.resolveInst(operand);
2960 const block_mcv = block_data.mcv;2949 const block_mcv = block_data.mcv;
2961 if (block_mcv == .none) {2950 if (block_mcv == .none) {
2962 block_data.mcv = operand_mcv;2951 block_data.mcv = switch (operand_mcv) {
2952 .none, .dead, .unreach => unreachable,
2953 .register, .stack_offset, .memory => operand_mcv,
2954 .immediate => blk: {
2955 const new_mcv = try self.allocRegOrMem(block, true);
2956 try self.setRegOrMem(self.air.typeOfIndex(block), new_mcv, operand_mcv);
2957 break :blk new_mcv;
2958 },
2959 else => return self.fail("TODO implement block_data.mcv = operand_mcv for {}", .{operand_mcv}),
2960 };
2963 } else {2961 } else {
2964 try self.setRegOrMem(self.air.typeOfIndex(block), block_mcv, operand_mcv);2962 try self.setRegOrMem(self.air.typeOfIndex(block), block_mcv, operand_mcv);
2965 }2963 }
...@@ -2973,7 +2971,6 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {...@@ -2973,7 +2971,6 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {
2973 // Emit a jump with a relocation. It will be patched up after the block ends.2971 // Emit a jump with a relocation. It will be patched up after the block ends.
2974 try block_data.relocs.append(self.gpa, try self.addInst(.{2972 try block_data.relocs.append(self.gpa, try self.addInst(.{
2975 .tag = .b,2973 .tag = .b,
2976 .cond = .al,
2977 .data = .{ .inst = undefined }, // populated later through performReloc2974 .data = .{ .inst = undefined }, // populated later through performReloc
2978 }));2975 }));
2979}2976}
...@@ -3029,7 +3026,6 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {...@@ -3029,7 +3026,6 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
3029 if (mem.eql(u8, asm_source, "svc #0")) {3026 if (mem.eql(u8, asm_source, "svc #0")) {
3030 _ = try self.addInst(.{3027 _ = try self.addInst(.{
3031 .tag = .svc,3028 .tag = .svc,
3032 .cond = .al,
3033 .data = .{ .imm24 = 0 },3029 .data = .{ .imm24 = 0 },
3034 });3030 });
3035 } else {3031 } else {
...@@ -3135,7 +3131,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3135,7 +3131,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
31353131
3136 _ = try self.addInst(.{3132 _ = try self.addInst(.{
3137 .tag = tag,3133 .tag = tag,
3138 .cond = .al,
3139 .data = .{ .rr_offset = .{3134 .data = .{ .rr_offset = .{
3140 .rt = reg,3135 .rt = reg,
3141 .rn = .fp,3136 .rn = .fp,
...@@ -3153,7 +3148,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3153,7 +3148,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
31533148
3154 _ = try self.addInst(.{3149 _ = try self.addInst(.{
3155 .tag = .strh,3150 .tag = .strh,
3156 .cond = .al,
3157 .data = .{ .rr_extra_offset = .{3151 .data = .{ .rr_extra_offset = .{
3158 .rt = reg,3152 .rt = reg,
3159 .rn = .fp,3153 .rn = .fp,
...@@ -3200,7 +3194,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3200,7 +3194,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
3200 };3194 };
3201 _ = try self.addInst(.{3195 _ = try self.addInst(.{
3202 .tag = .sub,3196 .tag = .sub,
3203 .cond = .al,
3204 .data = .{ .rr_op = .{3197 .data = .{ .rr_op = .{
3205 .rd = src_reg,3198 .rd = src_reg,
3206 .rn = .fp,3199 .rn = .fp,
...@@ -3215,7 +3208,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3215,7 +3208,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
3215 };3208 };
3216 _ = try self.addInst(.{3209 _ = try self.addInst(.{
3217 .tag = .sub,3210 .tag = .sub,
3218 .cond = .al,
3219 .data = .{ .rr_op = .{3211 .data = .{ .rr_op = .{
3220 .rd = dst_reg,3212 .rd = dst_reg,
3221 .rn = .fp,3213 .rn = .fp,
...@@ -3230,7 +3222,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -3230,7 +3222,6 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
3230 };3222 };
3231 _ = try self.addInst(.{3223 _ = try self.addInst(.{
3232 .tag = .mov,3224 .tag = .mov,
3233 .cond = .al,
3234 .data = .{ .rr_op = .{3225 .data = .{ .rr_op = .{
3235 .rd = len_reg,3226 .rd = len_reg,
3236 .rn = .r0,3227 .rn = .r0,
...@@ -3272,7 +3263,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3272,7 +3263,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3272 // mov reg, 03263 // mov reg, 0
3273 _ = try self.addInst(.{3264 _ = try self.addInst(.{
3274 .tag = .mov,3265 .tag = .mov,
3275 .cond = .al,
3276 .data = .{ .rr_op = .{3266 .data = .{ .rr_op = .{
3277 .rd = reg,3267 .rd = reg,
3278 .rn = .r0,3268 .rn = .r0,
...@@ -3297,7 +3287,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3297,7 +3287,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3297 if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {3287 if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {
3298 _ = try self.addInst(.{3288 _ = try self.addInst(.{
3299 .tag = .mov,3289 .tag = .mov,
3300 .cond = .al,
3301 .data = .{ .rr_op = .{3290 .data = .{ .rr_op = .{
3302 .rd = reg,3291 .rd = reg,
3303 .rn = .r0,3292 .rn = .r0,
...@@ -3307,7 +3296,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3307,7 +3296,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3307 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {3296 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
3308 _ = try self.addInst(.{3297 _ = try self.addInst(.{
3309 .tag = .mvn,3298 .tag = .mvn,
3310 .cond = .al,
3311 .data = .{ .rr_op = .{3299 .data = .{ .rr_op = .{
3312 .rd = reg,3300 .rd = reg,
3313 .rn = .r0,3301 .rn = .r0,
...@@ -3318,7 +3306,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3318,7 +3306,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3318 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {3306 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
3319 _ = try self.addInst(.{3307 _ = try self.addInst(.{
3320 .tag = .movw,3308 .tag = .movw,
3321 .cond = .al,
3322 .data = .{ .r_imm16 = .{3309 .data = .{ .r_imm16 = .{
3323 .rd = reg,3310 .rd = reg,
3324 .imm16 = @intCast(u16, x),3311 .imm16 = @intCast(u16, x),
...@@ -3327,7 +3314,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3327,7 +3314,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3327 } else {3314 } else {
3328 _ = try self.addInst(.{3315 _ = try self.addInst(.{
3329 .tag = .mov,3316 .tag = .mov,
3330 .cond = .al,
3331 .data = .{ .rr_op = .{3317 .data = .{ .rr_op = .{
3332 .rd = reg,3318 .rd = reg,
3333 .rn = .r0,3319 .rn = .r0,
...@@ -3336,7 +3322,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3336,7 +3322,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3336 });3322 });
3337 _ = try self.addInst(.{3323 _ = try self.addInst(.{
3338 .tag = .orr,3324 .tag = .orr,
3339 .cond = .al,
3340 .data = .{ .rr_op = .{3325 .data = .{ .rr_op = .{
3341 .rd = reg,3326 .rd = reg,
3342 .rn = reg,3327 .rn = reg,
...@@ -3353,7 +3338,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3353,7 +3338,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3353 // movt reg, #0xaaaa3338 // movt reg, #0xaaaa
3354 _ = try self.addInst(.{3339 _ = try self.addInst(.{
3355 .tag = .movw,3340 .tag = .movw,
3356 .cond = .al,
3357 .data = .{ .r_imm16 = .{3341 .data = .{ .r_imm16 = .{
3358 .rd = reg,3342 .rd = reg,
3359 .imm16 = @truncate(u16, x),3343 .imm16 = @truncate(u16, x),
...@@ -3361,7 +3345,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3361,7 +3345,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3361 });3345 });
3362 _ = try self.addInst(.{3346 _ = try self.addInst(.{
3363 .tag = .movt,3347 .tag = .movt,
3364 .cond = .al,
3365 .data = .{ .r_imm16 = .{3348 .data = .{ .r_imm16 = .{
3366 .rd = reg,3349 .rd = reg,
3367 .imm16 = @truncate(u16, x >> 16),3350 .imm16 = @truncate(u16, x >> 16),
...@@ -3375,7 +3358,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3375,7 +3358,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3375 // orr reg, reg, #0xdd, 83358 // orr reg, reg, #0xdd, 8
3376 _ = try self.addInst(.{3359 _ = try self.addInst(.{
3377 .tag = .mov,3360 .tag = .mov,
3378 .cond = .al,
3379 .data = .{ .rr_op = .{3361 .data = .{ .rr_op = .{
3380 .rd = reg,3362 .rd = reg,
3381 .rn = .r0,3363 .rn = .r0,
...@@ -3384,7 +3366,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3384,7 +3366,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3384 });3366 });
3385 _ = try self.addInst(.{3367 _ = try self.addInst(.{
3386 .tag = .orr,3368 .tag = .orr,
3387 .cond = .al,
3388 .data = .{ .rr_op = .{3369 .data = .{ .rr_op = .{
3389 .rd = reg,3370 .rd = reg,
3390 .rn = reg,3371 .rn = reg,
...@@ -3393,7 +3374,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3393,7 +3374,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3393 });3374 });
3394 _ = try self.addInst(.{3375 _ = try self.addInst(.{
3395 .tag = .orr,3376 .tag = .orr,
3396 .cond = .al,
3397 .data = .{ .rr_op = .{3377 .data = .{ .rr_op = .{
3398 .rd = reg,3378 .rd = reg,
3399 .rn = reg,3379 .rn = reg,
...@@ -3402,7 +3382,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3402,7 +3382,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3402 });3382 });
3403 _ = try self.addInst(.{3383 _ = try self.addInst(.{
3404 .tag = .orr,3384 .tag = .orr,
3405 .cond = .al,
3406 .data = .{ .rr_op = .{3385 .data = .{ .rr_op = .{
3407 .rd = reg,3386 .rd = reg,
3408 .rn = reg,3387 .rn = reg,
...@@ -3420,7 +3399,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3420,7 +3399,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3420 // mov reg, src_reg3399 // mov reg, src_reg
3421 _ = try self.addInst(.{3400 _ = try self.addInst(.{
3422 .tag = .mov,3401 .tag = .mov,
3423 .cond = .al,
3424 .data = .{ .rr_op = .{3402 .data = .{ .rr_op = .{
3425 .rd = reg,3403 .rd = reg,
3426 .rn = .r0,3404 .rn = .r0,
...@@ -3434,7 +3412,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3434,7 +3412,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3434 try self.genSetReg(ty, reg, .{ .immediate = @intCast(u32, addr) });3412 try self.genSetReg(ty, reg, .{ .immediate = @intCast(u32, addr) });
3435 _ = try self.addInst(.{3413 _ = try self.addInst(.{
3436 .tag = .ldr,3414 .tag = .ldr,
3437 .cond = .al,
3438 .data = .{ .rr_offset = .{3415 .data = .{ .rr_offset = .{
3439 .rt = reg,3416 .rt = reg,
3440 .rn = reg,3417 .rn = reg,
...@@ -3461,7 +3438,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3461,7 +3438,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34613438
3462 _ = try self.addInst(.{3439 _ = try self.addInst(.{
3463 .tag = tag,3440 .tag = tag,
3464 .cond = .al,
3465 .data = .{ .rr_offset = .{3441 .data = .{ .rr_offset = .{
3466 .rt = reg,3442 .rt = reg,
3467 .rn = .fp,3443 .rn = .fp,
...@@ -3479,7 +3455,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3479,7 +3455,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
34793455
3480 _ = try self.addInst(.{3456 _ = try self.addInst(.{
3481 .tag = .ldrh,3457 .tag = .ldrh,
3482 .cond = .al,
3483 .data = .{ .rr_extra_offset = .{3458 .data = .{ .rr_extra_offset = .{
3484 .rt = reg,3459 .rt = reg,
3485 .rn = .fp,3460 .rn = .fp,
...@@ -3507,7 +3482,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3507,7 +3482,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
35073482
3508 _ = try self.addInst(.{3483 _ = try self.addInst(.{
3509 .tag = tag,3484 .tag = tag,
3510 .cond = .al,
3511 .data = .{ .r_stack_offset = .{3485 .data = .{ .r_stack_offset = .{
3512 .rt = reg,3486 .rt = reg,
3513 .stack_offset = @intCast(u32, adj_off),3487 .stack_offset = @intCast(u32, adj_off),
...@@ -3551,7 +3525,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I...@@ -3551,7 +3525,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
35513525
3552 _ = try self.addInst(.{3526 _ = try self.addInst(.{
3553 .tag = tag,3527 .tag = tag,
3554 .cond = .al,
3555 .data = .{ .rr_offset = .{3528 .data = .{ .rr_offset = .{
3556 .rt = reg,3529 .rt = reg,
3557 .rn = .sp,3530 .rn = .sp,
...@@ -3566,7 +3539,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I...@@ -3566,7 +3539,6 @@ fn genSetStackArgument(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) I
35663539
3567 _ = try self.addInst(.{3540 _ = try self.addInst(.{
3568 .tag = .strh,3541 .tag = .strh,
3569 .cond = .al,
3570 .data = .{ .rr_extra_offset = .{3542 .data = .{ .rr_extra_offset = .{
3571 .rt = reg,3543 .rt = reg,
3572 .rn = .sp,3544 .rn = .sp,
src/arch/arm/Mir.zig+1-1
...@@ -20,7 +20,7 @@ extra: []const u32,...@@ -20,7 +20,7 @@ extra: []const u32,
2020
21pub const Inst = struct {21pub const Inst = struct {
22 tag: Tag,22 tag: Tag,
23 cond: bits.Condition,23 cond: bits.Condition = .al,
24 /// The meaning of this depends on `tag`.24 /// The meaning of this depends on `tag`.
25 data: Data,25 data: Data,
2626
src/arch/riscv64/CodeGen.zig+3-4
...@@ -1720,17 +1720,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {...@@ -1720,17 +1720,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
1720 // block results.1720 // block results.
1721 .mcv = MCValue{ .none = {} },1721 .mcv = MCValue{ .none = {} },
1722 });1722 });
1723 const block_data = self.blocks.getPtr(inst).?;1723 defer self.blocks.getPtr(inst).?.relocs.deinit(self.gpa);
1724 defer block_data.relocs.deinit(self.gpa);
17251724
1726 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;1725 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
1727 const extra = self.air.extraData(Air.Block, ty_pl.payload);1726 const extra = self.air.extraData(Air.Block, ty_pl.payload);
1728 const body = self.air.extra[extra.end..][0..extra.data.body_len];1727 const body = self.air.extra[extra.end..][0..extra.data.body_len];
1729 try self.genBody(body);1728 try self.genBody(body);
17301729
1731 for (block_data.relocs.items) |reloc| try self.performReloc(reloc);1730 for (self.blocks.getPtr(inst).?.relocs.items) |reloc| try self.performReloc(reloc);
17321731
1733 const result = @bitCast(MCValue, block_data.mcv);1732 const result = self.blocks.getPtr(inst).?.mcv;
1734 return self.finishAir(inst, result, .{ .none, .none, .none });1733 return self.finishAir(inst, result, .{ .none, .none, .none });
1735}1734}
17361735
src/arch/x86_64/CodeGen.zig+3-4
...@@ -2853,17 +2853,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {...@@ -2853,17 +2853,16 @@ fn airBlock(self: *Self, inst: Air.Inst.Index) !void {
2853 // block results.2853 // block results.
2854 .mcv = MCValue{ .none = {} },2854 .mcv = MCValue{ .none = {} },
2855 });2855 });
2856 const block_data = self.blocks.getPtr(inst).?;2856 defer self.blocks.getPtr(inst).?.relocs.deinit(self.gpa);
2857 defer block_data.relocs.deinit(self.gpa);
28582857
2859 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;2858 const ty_pl = self.air.instructions.items(.data)[inst].ty_pl;
2860 const extra = self.air.extraData(Air.Block, ty_pl.payload);2859 const extra = self.air.extraData(Air.Block, ty_pl.payload);
2861 const body = self.air.extra[extra.end..][0..extra.data.body_len];2860 const body = self.air.extra[extra.end..][0..extra.data.body_len];
2862 try self.genBody(body);2861 try self.genBody(body);
28632862
2864 for (block_data.relocs.items) |reloc| try self.performReloc(reloc);2863 for (self.blocks.getPtr(inst).?.relocs.items) |reloc| try self.performReloc(reloc);
28652864
2866 const result = @bitCast(MCValue, block_data.mcv);2865 const result = self.blocks.getPtr(inst).?.mcv;
2867 return self.finishAir(inst, result, .{ .none, .none, .none });2866 return self.finishAir(inst, result, .{ .none, .none, .none });
2868}2867}
28692868
test/behavior.zig+191-187
...@@ -14,198 +14,202 @@ test {...@@ -14,198 +14,202 @@ test {
14 _ = @import("behavior/type_info.zig");14 _ = @import("behavior/type_info.zig");
15 _ = @import("behavior/type.zig");15 _ = @import("behavior/type.zig");
1616
17 if (builtin.zig_backend != .stage2_arm and builtin.zig_backend != .stage2_x86_64) {17 if (builtin.zig_backend != .stage2_x86_64) {
18 // Tests that pass for stage1, llvm backend, C backend, wasm backend.18 // Tests that pass for stage1, llvm backend, C backend, wasm backend, and arm backend.
19 _ = @import("behavior/array.zig");
20 _ = @import("behavior/bugs/3586.zig");
21 _ = @import("behavior/basic.zig");
22 _ = @import("behavior/bitcast.zig");
23 _ = @import("behavior/bool.zig");19 _ = @import("behavior/bool.zig");
24 _ = @import("behavior/bugs/624.zig");
25 _ = @import("behavior/bugs/655.zig");
26 _ = @import("behavior/bugs/704.zig");
27 _ = @import("behavior/bugs/1486.zig");
28 _ = @import("behavior/bugs/2692.zig");
29 _ = @import("behavior/bugs/2889.zig");
30 _ = @import("behavior/bugs/3046.zig");
31 _ = @import("behavior/bugs/4560.zig");
32 _ = @import("behavior/bugs/4769_a.zig");
33 _ = @import("behavior/bugs/4769_b.zig");
34 _ = @import("behavior/bugs/4954.zig");
35 _ = @import("behavior/byval_arg_var.zig");
36 _ = @import("behavior/call.zig");
37 _ = @import("behavior/defer.zig");
38 _ = @import("behavior/enum.zig");
39 _ = @import("behavior/error.zig");
40 _ = @import("behavior/for.zig");
41 _ = @import("behavior/generics.zig");
42 _ = @import("behavior/if.zig");
43 _ = @import("behavior/import.zig");
44 _ = @import("behavior/incomplete_struct_param_tld.zig");
45 _ = @import("behavior/inttoptr.zig");
46 _ = @import("behavior/member_func.zig");
47 _ = @import("behavior/null.zig");
48 _ = @import("behavior/pointers.zig");
49 _ = @import("behavior/ptrcast.zig");
50 _ = @import("behavior/ref_var_in_if_after_if_2nd_switch_prong.zig");
51 _ = @import("behavior/struct.zig");
52 _ = @import("behavior/this.zig");
53 _ = @import("behavior/truncate.zig");
54 _ = @import("behavior/undefined.zig");
55 _ = @import("behavior/underscore.zig");
56 _ = @import("behavior/usingnamespace.zig");
57 _ = @import("behavior/void.zig");
58 _ = @import("behavior/while.zig");
5920
60 if (builtin.zig_backend != .stage2_wasm) {21 if (builtin.zig_backend != .stage2_arm and builtin.zig_backend != .stage2_x86_64) {
61 // Tests that pass for stage1, llvm backend, C backend22 // Tests that pass for stage1, llvm backend, C backend, wasm backend.
62 _ = @import("behavior/align.zig");23 _ = @import("behavior/array.zig");
63 _ = @import("behavior/cast.zig");24 _ = @import("behavior/bugs/3586.zig");
64 _ = @import("behavior/int128.zig");25 _ = @import("behavior/basic.zig");
65 _ = @import("behavior/optional.zig");26 _ = @import("behavior/bitcast.zig");
66 _ = @import("behavior/translate_c_macros.zig");27 _ = @import("behavior/bugs/624.zig");
67 _ = @import("behavior/try.zig");28 _ = @import("behavior/bugs/655.zig");
68 _ = @import("behavior/src.zig");29 _ = @import("behavior/bugs/704.zig");
30 _ = @import("behavior/bugs/1486.zig");
31 _ = @import("behavior/bugs/2692.zig");
32 _ = @import("behavior/bugs/2889.zig");
33 _ = @import("behavior/bugs/3046.zig");
34 _ = @import("behavior/bugs/4560.zig");
35 _ = @import("behavior/bugs/4769_a.zig");
36 _ = @import("behavior/bugs/4769_b.zig");
37 _ = @import("behavior/bugs/4954.zig");
38 _ = @import("behavior/byval_arg_var.zig");
39 _ = @import("behavior/call.zig");
40 _ = @import("behavior/defer.zig");
41 _ = @import("behavior/enum.zig");
42 _ = @import("behavior/error.zig");
43 _ = @import("behavior/for.zig");
44 _ = @import("behavior/generics.zig");
45 _ = @import("behavior/if.zig");
46 _ = @import("behavior/import.zig");
47 _ = @import("behavior/incomplete_struct_param_tld.zig");
48 _ = @import("behavior/inttoptr.zig");
49 _ = @import("behavior/member_func.zig");
50 _ = @import("behavior/null.zig");
51 _ = @import("behavior/pointers.zig");
52 _ = @import("behavior/ptrcast.zig");
53 _ = @import("behavior/ref_var_in_if_after_if_2nd_switch_prong.zig");
54 _ = @import("behavior/struct.zig");
55 _ = @import("behavior/this.zig");
56 _ = @import("behavior/truncate.zig");
57 _ = @import("behavior/undefined.zig");
58 _ = @import("behavior/underscore.zig");
59 _ = @import("behavior/usingnamespace.zig");
60 _ = @import("behavior/void.zig");
61 _ = @import("behavior/while.zig");
6962
70 if (builtin.zig_backend != .stage2_c) {63 if (builtin.zig_backend != .stage2_wasm) {
71 // Tests that pass for stage1 and the llvm backend.64 // Tests that pass for stage1, llvm backend, C backend
72 _ = @import("behavior/align_llvm.zig");65 _ = @import("behavior/align.zig");
73 _ = @import("behavior/alignof.zig");66 _ = @import("behavior/cast.zig");
74 _ = @import("behavior/array_llvm.zig");67 _ = @import("behavior/int128.zig");
75 _ = @import("behavior/atomics.zig");68 _ = @import("behavior/optional.zig");
76 _ = @import("behavior/basic_llvm.zig");69 _ = @import("behavior/translate_c_macros.zig");
77 _ = @import("behavior/bit_shifting.zig");70 _ = @import("behavior/try.zig");
78 _ = @import("behavior/bugs/394.zig");71 _ = @import("behavior/src.zig");
79 _ = @import("behavior/bugs/656.zig");
80 _ = @import("behavior/bugs/1277.zig");
81 _ = @import("behavior/bugs/1310.zig");
82 _ = @import("behavior/bugs/1381.zig");
83 _ = @import("behavior/bugs/1500.zig");
84 _ = @import("behavior/bugs/1735.zig");
85 _ = @import("behavior/bugs/1741.zig");
86 _ = @import("behavior/bugs/2006.zig");
87 _ = @import("behavior/bugs/2578.zig");
88 _ = @import("behavior/bugs/3007.zig");
89 _ = @import("behavior/bugs/3112.zig");
90 _ = @import("behavior/bugs/3367.zig");
91 _ = @import("behavior/bugs/7250.zig");
92 _ = @import("behavior/bugs/9584.zig");
93 _ = @import("behavior/cast_llvm.zig");
94 _ = @import("behavior/enum_llvm.zig");
95 _ = @import("behavior/error_llvm.zig");
96 _ = @import("behavior/eval.zig");
97 _ = @import("behavior/floatop.zig");
98 _ = @import("behavior/fn.zig");
99 _ = @import("behavior/generics_llvm.zig");
100 _ = @import("behavior/math.zig");
101 _ = @import("behavior/maximum_minimum.zig");
102 _ = @import("behavior/merge_error_sets.zig");
103 _ = @import("behavior/namespace_depends_on_compile_var.zig");
104 _ = @import("behavior/null_llvm.zig");
105 _ = @import("behavior/optional_llvm.zig");
106 _ = @import("behavior/popcount.zig");
107 _ = @import("behavior/saturating_arithmetic.zig");
108 _ = @import("behavior/sizeof_and_typeof.zig");
109 _ = @import("behavior/slice.zig");
110 _ = @import("behavior/struct_llvm.zig");
111 _ = @import("behavior/switch.zig");
112 _ = @import("behavior/union.zig");
113 _ = @import("behavior/widening.zig");
11472
115 if (builtin.zig_backend != .stage1) {73 if (builtin.zig_backend != .stage2_c) {
116 // When all comptime_memory.zig tests pass, #9646 can be closed.74 // Tests that pass for stage1 and the llvm backend.
117 // _ = @import("behavior/comptime_memory.zig");75 _ = @import("behavior/align_llvm.zig");
118 _ = @import("behavior/slice_stage2.zig");76 _ = @import("behavior/alignof.zig");
119 } else {77 _ = @import("behavior/array_llvm.zig");
120 // Tests that only pass for the stage1 backend.78 _ = @import("behavior/atomics.zig");
121 _ = @import("behavior/align_stage1.zig");79 _ = @import("behavior/basic_llvm.zig");
122 _ = @import("behavior/array_stage1.zig");80 _ = @import("behavior/bit_shifting.zig");
123 if (builtin.os.tag != .wasi) {81 _ = @import("behavior/bugs/394.zig");
124 _ = @import("behavior/asm.zig");82 _ = @import("behavior/bugs/656.zig");
125 _ = @import("behavior/async_fn.zig");83 _ = @import("behavior/bugs/1277.zig");
126 }84 _ = @import("behavior/bugs/1310.zig");
127 _ = @import("behavior/await_struct.zig");85 _ = @import("behavior/bugs/1381.zig");
128 _ = @import("behavior/bitcast_stage1.zig");86 _ = @import("behavior/bugs/1500.zig");
129 _ = @import("behavior/bitreverse.zig");87 _ = @import("behavior/bugs/1735.zig");
130 _ = @import("behavior/bugs/421.zig");88 _ = @import("behavior/bugs/1741.zig");
131 _ = @import("behavior/bugs/529.zig");89 _ = @import("behavior/bugs/2006.zig");
132 _ = @import("behavior/bugs/718.zig");90 _ = @import("behavior/bugs/2578.zig");
133 _ = @import("behavior/bugs/726.zig");91 _ = @import("behavior/bugs/3007.zig");
134 _ = @import("behavior/bugs/828.zig");92 _ = @import("behavior/bugs/3112.zig");
135 _ = @import("behavior/bugs/920.zig");93 _ = @import("behavior/bugs/3367.zig");
136 _ = @import("behavior/bugs/1025.zig");94 _ = @import("behavior/bugs/7250.zig");
137 _ = @import("behavior/bugs/1076.zig");95 _ = @import("behavior/bugs/9584.zig");
138 _ = @import("behavior/bugs/1120.zig");96 _ = @import("behavior/cast_llvm.zig");
139 _ = @import("behavior/bugs/1421.zig");97 _ = @import("behavior/enum_llvm.zig");
140 _ = @import("behavior/bugs/1442.zig");98 _ = @import("behavior/error_llvm.zig");
141 _ = @import("behavior/bugs/1607.zig");99 _ = @import("behavior/eval.zig");
142 _ = @import("behavior/bugs/1851.zig");100 _ = @import("behavior/floatop.zig");
143 _ = @import("behavior/bugs/1914.zig");101 _ = @import("behavior/fn.zig");
144 _ = @import("behavior/bugs/2114.zig");102 _ = @import("behavior/generics_llvm.zig");
145 _ = @import("behavior/bugs/3384.zig");103 _ = @import("behavior/math.zig");
146 _ = @import("behavior/bugs/3742.zig");104 _ = @import("behavior/maximum_minimum.zig");
147 _ = @import("behavior/bugs/3779.zig");105 _ = @import("behavior/merge_error_sets.zig");
148 _ = @import("behavior/bugs/4328.zig");106 _ = @import("behavior/namespace_depends_on_compile_var.zig");
149 _ = @import("behavior/bugs/5398.zig");107 _ = @import("behavior/null_llvm.zig");
150 _ = @import("behavior/bugs/5413.zig");108 _ = @import("behavior/optional_llvm.zig");
151 _ = @import("behavior/bugs/5474.zig");109 _ = @import("behavior/popcount.zig");
152 _ = @import("behavior/bugs/5487.zig");110 _ = @import("behavior/saturating_arithmetic.zig");
153 _ = @import("behavior/bugs/6456.zig");111 _ = @import("behavior/sizeof_and_typeof.zig");
154 _ = @import("behavior/bugs/6781.zig");112 _ = @import("behavior/slice.zig");
155 _ = @import("behavior/bugs/7003.zig");113 _ = @import("behavior/struct_llvm.zig");
156 _ = @import("behavior/bugs/7027.zig");114 _ = @import("behavior/switch.zig");
157 _ = @import("behavior/bugs/7047.zig");115 _ = @import("behavior/union.zig");
158 _ = @import("behavior/bugs/10147.zig");116 _ = @import("behavior/widening.zig");
159 _ = @import("behavior/byteswap.zig");117
160 _ = @import("behavior/call_stage1.zig");118 if (builtin.zig_backend != .stage1) {
161 _ = @import("behavior/cast_stage1.zig");119 // When all comptime_memory.zig tests pass, #9646 can be closed.
162 _ = @import("behavior/const_slice_child.zig");120 // _ = @import("behavior/comptime_memory.zig");
163 _ = @import("behavior/defer_stage1.zig");121 _ = @import("behavior/slice_stage2.zig");
164 _ = @import("behavior/enum_stage1.zig");122 } else {
165 _ = @import("behavior/error_stage1.zig");123 // Tests that only pass for the stage1 backend.
166 _ = @import("behavior/eval_stage1.zig");124 _ = @import("behavior/align_stage1.zig");
167 _ = @import("behavior/field_parent_ptr.zig");125 _ = @import("behavior/array_stage1.zig");
168 _ = @import("behavior/floatop_stage1.zig");126 if (builtin.os.tag != .wasi) {
169 _ = @import("behavior/fn_stage1.zig");127 _ = @import("behavior/asm.zig");
170 _ = @import("behavior/fn_delegation.zig");128 _ = @import("behavior/async_fn.zig");
171 _ = @import("behavior/for_stage1.zig");129 }
172 _ = @import("behavior/if_stage1.zig");130 _ = @import("behavior/await_struct.zig");
173 _ = @import("behavior/ir_block_deps.zig");131 _ = @import("behavior/bitcast_stage1.zig");
174 _ = @import("behavior/math_stage1.zig");132 _ = @import("behavior/bitreverse.zig");
175 _ = @import("behavior/misc.zig");133 _ = @import("behavior/bugs/421.zig");
176 _ = @import("behavior/muladd.zig");134 _ = @import("behavior/bugs/529.zig");
177 _ = @import("behavior/null_stage1.zig");135 _ = @import("behavior/bugs/718.zig");
178 _ = @import("behavior/optional_stage1.zig");136 _ = @import("behavior/bugs/726.zig");
179 _ = @import("behavior/pointers_stage1.zig");137 _ = @import("behavior/bugs/828.zig");
180 _ = @import("behavior/popcount_stage1.zig");138 _ = @import("behavior/bugs/920.zig");
181 _ = @import("behavior/prefetch.zig");139 _ = @import("behavior/bugs/1025.zig");
182 _ = @import("behavior/ptrcast_stage1.zig");140 _ = @import("behavior/bugs/1076.zig");
183 _ = @import("behavior/reflection.zig");141 _ = @import("behavior/bugs/1120.zig");
184 _ = @import("behavior/saturating_arithmetic_stage1.zig");142 _ = @import("behavior/bugs/1421.zig");
185 _ = @import("behavior/select.zig");143 _ = @import("behavior/bugs/1442.zig");
186 _ = @import("behavior/shuffle.zig");144 _ = @import("behavior/bugs/1607.zig");
187 _ = @import("behavior/sizeof_and_typeof_stage1.zig");145 _ = @import("behavior/bugs/1851.zig");
188 _ = @import("behavior/slice_stage1.zig");146 _ = @import("behavior/bugs/1914.zig");
189 _ = @import("behavior/struct_contains_null_ptr_itself.zig");147 _ = @import("behavior/bugs/2114.zig");
190 _ = @import("behavior/struct_contains_slice_of_itself.zig");148 _ = @import("behavior/bugs/3384.zig");
191 _ = @import("behavior/struct_stage1.zig");149 _ = @import("behavior/bugs/3742.zig");
192 _ = @import("behavior/switch_prong_err_enum.zig");150 _ = @import("behavior/bugs/3779.zig");
193 _ = @import("behavior/switch_prong_implicit_cast.zig");151 _ = @import("behavior/bugs/4328.zig");
194 _ = @import("behavior/switch_stage1.zig");152 _ = @import("behavior/bugs/5398.zig");
195 _ = @import("behavior/truncate_stage1.zig");153 _ = @import("behavior/bugs/5413.zig");
196 _ = @import("behavior/tuple.zig");154 _ = @import("behavior/bugs/5474.zig");
197 _ = @import("behavior/type_stage1.zig");155 _ = @import("behavior/bugs/5487.zig");
198 _ = @import("behavior/type_info_stage1.zig");156 _ = @import("behavior/bugs/6456.zig");
199 _ = @import("behavior/typename.zig");157 _ = @import("behavior/bugs/6781.zig");
200 _ = @import("behavior/union_stage1.zig");158 _ = @import("behavior/bugs/7003.zig");
201 _ = @import("behavior/union_with_members.zig");159 _ = @import("behavior/bugs/7027.zig");
202 _ = @import("behavior/var_args.zig");160 _ = @import("behavior/bugs/7047.zig");
203 _ = @import("behavior/vector.zig");161 _ = @import("behavior/bugs/10147.zig");
204 if (builtin.target.cpu.arch == .wasm32) {162 _ = @import("behavior/byteswap.zig");
205 _ = @import("behavior/wasm.zig");163 _ = @import("behavior/call_stage1.zig");
164 _ = @import("behavior/cast_stage1.zig");
165 _ = @import("behavior/const_slice_child.zig");
166 _ = @import("behavior/defer_stage1.zig");
167 _ = @import("behavior/enum_stage1.zig");
168 _ = @import("behavior/error_stage1.zig");
169 _ = @import("behavior/eval_stage1.zig");
170 _ = @import("behavior/field_parent_ptr.zig");
171 _ = @import("behavior/floatop_stage1.zig");
172 _ = @import("behavior/fn_stage1.zig");
173 _ = @import("behavior/fn_delegation.zig");
174 _ = @import("behavior/for_stage1.zig");
175 _ = @import("behavior/if_stage1.zig");
176 _ = @import("behavior/ir_block_deps.zig");
177 _ = @import("behavior/math_stage1.zig");
178 _ = @import("behavior/misc.zig");
179 _ = @import("behavior/muladd.zig");
180 _ = @import("behavior/null_stage1.zig");
181 _ = @import("behavior/optional_stage1.zig");
182 _ = @import("behavior/pointers_stage1.zig");
183 _ = @import("behavior/popcount_stage1.zig");
184 _ = @import("behavior/prefetch.zig");
185 _ = @import("behavior/ptrcast_stage1.zig");
186 _ = @import("behavior/reflection.zig");
187 _ = @import("behavior/saturating_arithmetic_stage1.zig");
188 _ = @import("behavior/select.zig");
189 _ = @import("behavior/shuffle.zig");
190 _ = @import("behavior/sizeof_and_typeof_stage1.zig");
191 _ = @import("behavior/slice_stage1.zig");
192 _ = @import("behavior/struct_contains_null_ptr_itself.zig");
193 _ = @import("behavior/struct_contains_slice_of_itself.zig");
194 _ = @import("behavior/struct_stage1.zig");
195 _ = @import("behavior/switch_prong_err_enum.zig");
196 _ = @import("behavior/switch_prong_implicit_cast.zig");
197 _ = @import("behavior/switch_stage1.zig");
198 _ = @import("behavior/truncate_stage1.zig");
199 _ = @import("behavior/tuple.zig");
200 _ = @import("behavior/type_stage1.zig");
201 _ = @import("behavior/type_info_stage1.zig");
202 _ = @import("behavior/typename.zig");
203 _ = @import("behavior/union_stage1.zig");
204 _ = @import("behavior/union_with_members.zig");
205 _ = @import("behavior/var_args.zig");
206 _ = @import("behavior/vector.zig");
207 if (builtin.target.cpu.arch == .wasm32) {
208 _ = @import("behavior/wasm.zig");
209 }
210 _ = @import("behavior/while_stage1.zig");
211 _ = @import("behavior/translate_c_macros_stage1.zig");
206 }212 }
207 _ = @import("behavior/while_stage1.zig");
208 _ = @import("behavior/translate_c_macros_stage1.zig");
209 }213 }
210 }214 }
211 }215 }