authorgravatar for xtex@astrafall.orgxtex <xtex@astrafall.org> 2026-08-07 15:16:01+08:00
committergravatar for xtex@astrafall.orgxtex <xtex@astrafall.org> 2026-08-09 11:10:26+08:00
log4605f7fbbfe44dea013a05b51b4a17e55e9a91ad
treef3bc2788d56f57b87e4431b259ee8a8a0304eabe
parent726f539fe5975afee1ad857bff0c59032f146516
signaturebadge-check Signed by SSH key SHA256:IEYEjkZlkUTr5U9GiDAmZU/4eZus2t2RsxusyhQqwao

std: support loongarch backend

7 files changed, 36 insertions(+), 1 deletions(-)

lib/compiler/test_runner.zig+1
...@@ -26,6 +26,7 @@ const runner_threaded_io: Io = Io.Threaded.global_single_threaded.io();...@@ -26,6 +26,7 @@ const runner_threaded_io: Io = Io.Threaded.global_single_threaded.io();
26/// the test runner will communicate with the build runner via `std.zig.Server`.26/// the test runner will communicate with the build runner via `std.zig.Server`.
27const need_simple = switch (builtin.zig_backend) {27const need_simple = switch (builtin.zig_backend) {
28 .stage2_aarch64,28 .stage2_aarch64,
29 .stage2_loongarch,
29 .stage2_powerpc,30 .stage2_powerpc,
30 .stage2_riscv64,31 .stage2_riscv64,
31 => true,32 => true,
lib/std/debug.zig+1
...@@ -498,6 +498,7 @@ threadlocal var panic_stage: usize = 0;...@@ -498,6 +498,7 @@ threadlocal var panic_stage: usize = 0;
498const use_trap_panic = switch (builtin.zig_backend) {498const use_trap_panic = switch (builtin.zig_backend) {
499 .stage2_aarch64,499 .stage2_aarch64,
500 .stage2_arm,500 .stage2_arm,
501 .stage2_loongarch,
501 .stage2_powerpc,502 .stage2_powerpc,
502 .stage2_riscv64,503 .stage2_riscv64,
503 .stage2_spirv,504 .stage2_spirv,
lib/std/mem.zig+1
...@@ -735,6 +735,7 @@ test lessThan {...@@ -735,6 +735,7 @@ test lessThan {
735const use_vectors = switch (builtin.zig_backend) {735const use_vectors = switch (builtin.zig_backend) {
736 // These backends don't support vectors yet.736 // These backends don't support vectors yet.
737 .stage2_aarch64,737 .stage2_aarch64,
738 .stage2_loongarch,
738 .stage2_powerpc,739 .stage2_powerpc,
739 .stage2_riscv64,740 .stage2_riscv64,
740 => false,741 => false,
lib/std/os/linux.zig+1
...@@ -681,6 +681,7 @@ pub var elf_aux_maybe: ?[*]std.elf.Auxv = null;...@@ -681,6 +681,7 @@ pub var elf_aux_maybe: ?[*]std.elf.Auxv = null;
681const extern_getauxval = switch (builtin.zig_backend) {681const extern_getauxval = switch (builtin.zig_backend) {
682 // Calling extern functions is not yet supported with these backends682 // Calling extern functions is not yet supported with these backends
683 .stage2_arm,683 .stage2_arm,
684 .stage2_loongarch,
684 .stage2_powerpc,685 .stage2_powerpc,
685 .stage2_riscv64,686 .stage2_riscv64,
686 .stage2_sparc64,687 .stage2_sparc64,
lib/std/start.zig+30-1
...@@ -180,7 +180,10 @@ fn _start() callconv(.naked) noreturn {...@@ -180,7 +180,10 @@ fn _start() callconv(.naked) noreturn {
180 .csky => ".cfi_undefined lr",180 .csky => ".cfi_undefined lr",
181 .hexagon => ".cfi_undefined r31",181 .hexagon => ".cfi_undefined r31",
182 .kvx => ".cfi_undefined r14",182 .kvx => ".cfi_undefined r14",
183 .loongarch32, .loongarch64 => ".cfi_undefined 1",183 .loongarch32, .loongarch64 => if (builtin.zig_backend == .stage2_loongarch)
184 ""
185 else
186 ".cfi_undefined 1",
184 .m68k => ".cfi_undefined %%pc",187 .m68k => ".cfi_undefined %%pc",
185 .m88k => ".cfi_undefined %%r1",188 .m88k => ".cfi_undefined %%r1",
186 .microblaze, .microblazeel => "", // No CFI support.189 .microblaze, .microblazeel => "", // No CFI support.
...@@ -215,6 +218,32 @@ fn _start() callconv(.naked) noreturn {...@@ -215,6 +218,32 @@ fn _start() callconv(.naked) noreturn {
215 // kernel is usually good about upholding the ABI guarantees, the same cannot be said of dynamic218 // kernel is usually good about upholding the ABI guarantees, the same cannot be said of dynamic
216 // linkers; musl's ldso, for example, opts to not align the stack when invoking the dynamic219 // linkers; musl's ldso, for example, opts to not align the stack when invoking the dynamic
217 // linker explicitly.220 // linker explicitly.
221 if (builtin.zig_backend == .stage2_loongarch) {
222 // TODO: need "X" constraint support
223 asm volatile (switch (native_arch) {
224 .loongarch32 =>
225 \\ move $fp, $zero
226 \\ move $ra, $zero
227 \\ move $a0, $sp
228 \\ srli.w $sp, $sp, 4
229 \\ slli.w $sp, $sp, 4
230 \\ jirl $ra, %[posixCallMainAndExit], 0
231 ,
232 .loongarch64 =>
233 \\ move $fp, $zero
234 \\ move $ra, $zero
235 \\ move $a0, $sp
236 \\ bstrins.d $sp, $zero, 3, 0
237 \\ jirl $ra, %[posixCallMainAndExit], 0
238 ,
239 else => unreachable,
240 }
241 :
242 : [posixCallMainAndExit] "r" (&posixCallMainAndExit),
243 : .{ .r1 = true, .r4 = true, .r22 = true });
244 unreachable;
245 }
246
218 asm volatile (switch (native_arch) {247 asm volatile (switch (native_arch) {
219 .x86_64 =>248 .x86_64 =>
220 \\ xorl %%ebp, %%ebp249 \\ xorl %%ebp, %%ebp
lib/std/testing.zig+1
...@@ -34,6 +34,7 @@ pub var log_level = std.log.Level.warn;...@@ -34,6 +34,7 @@ pub var log_level = std.log.Level.warn;
34// Disable printing in tests for simple backends.34// Disable printing in tests for simple backends.
35pub const backend_can_print = switch (builtin.zig_backend) {35pub const backend_can_print = switch (builtin.zig_backend) {
36 .stage2_aarch64,36 .stage2_aarch64,
37 .stage2_loongarch,
37 .stage2_powerpc,38 .stage2_powerpc,
38 .stage2_riscv64,39 .stage2_riscv64,
39 .stage2_spirv,40 .stage2_spirv,
lib/ubsan_rt.zig+1
...@@ -647,6 +647,7 @@ fn exportHandlerWithAbort(...@@ -647,6 +647,7 @@ fn exportHandlerWithAbort(
647}647}
648648
649const can_build_ubsan = switch (builtin.zig_backend) {649const can_build_ubsan = switch (builtin.zig_backend) {
650 .stage2_loongarch,
650 .stage2_powerpc,651 .stage2_powerpc,
651 .stage2_riscv64,652 .stage2_riscv64,
652 => false,653 => false,