authorgravatar for 51252236+xdBronch@users.noreply.github.comxdBronch <51252236+xdBronch@users.noreply.github.com> 2023-05-13 06:21:49-04:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2023-05-13 13:35:50+03:00
log46527292178d64daa9f81be3eef378d78d254b5d
treedbaed78fb0aab3ab0ea0d908ec6fd2a48fae7f91
parent68bacad8047df050c8ab6bf52c2921f482647d57

std.simd.suggestVectorSizeForCpu: fix missing argument in body

1 files changed, 1 insertions(+), 1 deletions(-)

lib/std/simd.zig+1-1
...@@ -12,7 +12,7 @@ pub fn suggestVectorSizeForCpu(comptime T: type, comptime cpu: std.Target.Cpu) ?...@@ -12,7 +12,7 @@ pub fn suggestVectorSizeForCpu(comptime T: type, comptime cpu: std.Target.Cpu) ?
12 const element_bit_size = @max(8, std.math.ceilPowerOfTwo(u16, @bitSizeOf(T)) catch unreachable);12 const element_bit_size = @max(8, std.math.ceilPowerOfTwo(u16, @bitSizeOf(T)) catch unreachable);
13 const vector_bit_size: u16 = blk: {13 const vector_bit_size: u16 = blk: {
14 if (cpu.arch.isX86()) {14 if (cpu.arch.isX86()) {
15 if (T == bool and std.Target.x86.featureSetHas(.prefer_mask_registers)) return 64;15 if (T == bool and std.Target.x86.featureSetHas(cpu.features, .prefer_mask_registers)) return 64;
16 if (std.Target.x86.featureSetHas(cpu.features, .avx512f) and !std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .prefer_128_bit })) break :blk 512;16 if (std.Target.x86.featureSetHas(cpu.features, .avx512f) and !std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .prefer_128_bit })) break :blk 512;
17 if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256;17 if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256;
18 if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128;18 if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128;